drivers/staging/brcm80211/brcmfmac/dhd_sdio.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/printk.h>
  20 #include <linux/pci_ids.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/sched.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <asm/unaligned.h>
  25 #include <bcmdefs.h>
  26 #include <bcmsdh.h>
  27
  28 #include <bcmdefs.h>
  29 #include <bcmwifi.h>
  30 #include <bcmutils.h>
  31 #include <bcmdevs.h>
  32
  33 #include <bcmsoc.h>
  34 #ifdef DHD_DEBUG
  35
  36 /* ARM trap handling */
  37
  38 /* Trap types defined by ARM (see arminc.h) */
  39
  40 /* Trap locations in lo memory */
  41 #define TRAP_STRIDE     4
  42 #define FIRST_TRAP      TR_RST
  43 #define LAST_TRAP       (TR_FIQ * TRAP_STRIDE)
  44
  45 #if defined(__ARM_ARCH_4T__)
  46 #define MAX_TRAP_TYPE   (TR_FIQ + 1)
  47 #elif defined(__ARM_ARCH_7M__)
  48 #define MAX_TRAP_TYPE   (TR_ISR + ARMCM3_NUMINTS)
  49 #endif                          /* __ARM_ARCH_7M__ */
  50
  51 /* The trap structure is defined here as offsets for assembly */
  52 #define TR_TYPE         0x00
  53 #define TR_EPC          0x04
  54 #define TR_CPSR         0x08
  55 #define TR_SPSR         0x0c
  56 #define TR_REGS         0x10
  57 #define TR_REG(n)       (TR_REGS + (n) * 4)
  58 #define TR_SP           TR_REG(13)
  59 #define TR_LR           TR_REG(14)
  60 #define TR_PC           TR_REG(15)
  61
  62 #define TRAP_T_SIZE     80
  63
  64 typedef struct _trap_struct {
  65         u32 type;
  66         u32 epc;
  67         u32 cpsr;
  68         u32 spsr;
  69         u32 r0;
  70         u32 r1;
  71         u32 r2;
  72         u32 r3;
  73         u32 r4;
  74         u32 r5;
  75         u32 r6;
  76         u32 r7;
  77         u32 r8;
  78         u32 r9;
  79         u32 r10;
  80         u32 r11;
  81         u32 r12;
  82         u32 r13;
  83         u32 r14;
  84         u32 pc;
  85 } trap_t;
  86
  87 #define CBUF_LEN        (128)
  88
  89 #define LOG_BUF_LEN     1024
  90
  91 typedef struct {
  92         u32 buf;                /* Can't be pointer on (64-bit) hosts */
  93         uint buf_size;
  94         uint idx;
  95         char *_buf_compat;      /* Redundant pointer for backward compat. */
  96 } rte_log_t;
  97
  98 typedef struct {
  99         /* Virtual UART
 100          * When there is no UART (e.g. Quickturn),
 101          * the host should write a complete
 102          * input line directly into cbuf and then write
 103          * the length into vcons_in.
 104          * This may also be used when there is a real UART
 105          * (at risk of conflicting with
 106          * the real UART).  vcons_out is currently unused.
 107          */
 108         volatile uint vcons_in;
 109         volatile uint vcons_out;
 110
 111         /* Output (logging) buffer
 112          * Console output is written to a ring buffer log_buf at index log_idx.
 113          * The host may read the output when it sees log_idx advance.
 114          * Output will be lost if the output wraps around faster than the host
 115          * polls.
 116          */
 117         rte_log_t log;
 118
 119         /* Console input line buffer
 120          * Characters are read one at a time into cbuf
 121          * until <CR> is received, then
 122          * the buffer is processed as a command line.
 123          * Also used for virtual UART.
 124          */
 125         uint cbuf_idx;
 126         char cbuf[CBUF_LEN];
 127 } rte_cons_t;
 128
 129 #endif                          /* DHD_DEBUG */
 130 #include <chipcommon.h>
 131
 132 #include <sbsdio.h>
 133
 134 #include <dngl_stats.h>
 135 #include <dhd.h>
 136 #include <dhd_bus.h>
 137 #include <dhd_proto.h>
 138 #include <dhd_dbg.h>
 139 #include <sdiovar.h>
 140 #include <bcmchip.h>
 141
 142 #ifndef DHDSDIO_MEM_DUMP_FNAME
 143 #define DHDSDIO_MEM_DUMP_FNAME         "mem_dump"
 144 #endif
 145
 146 #define TXQLEN          2048    /* bulk tx queue length */
 147 #define TXHI            (TXQLEN - 256)  /* turn on flow control above TXHI */
 148 #define TXLOW           (TXHI - 256)    /* turn off flow control below TXLOW */
 149 #define PRIOMASK        7
 150
 151 #define TXRETRIES       2       /* # of retries for tx frames */
 152
 153 #if defined(CONFIG_MACH_SANDGATE2G)
 154 #define DHD_RXBOUND     250     /* Default for max rx frames in
 155                                  one scheduling */
 156 #else
 157 #define DHD_RXBOUND     50      /* Default for max rx frames in
 158                                  one scheduling */
 159 #endif                          /* defined(CONFIG_MACH_SANDGATE2G) */
 160
 161 #define DHD_TXBOUND     20      /* Default for max tx frames in
 162                                  one scheduling */
 163
 164 #define DHD_TXMINMAX    1       /* Max tx frames if rx still pending */
 165
 166 #define MEMBLOCK        2048    /* Block size used for downloading
 167                                  of dongle image */
 168 #define MAX_DATA_BUF    (32 * 1024)     /* Must be large enough to hold
 169                                  biggest possible glom */
 170
 171 /* Packet alignment for most efficient SDIO (can change based on platform) */
 172 #ifndef DHD_SDALIGN
 173 #define DHD_SDALIGN     32
 174 #endif
 175 #if !ISPOWEROF2(DHD_SDALIGN)
 176 #error DHD_SDALIGN is not a power of 2!
 177 #endif
 178
 179 #ifndef DHD_FIRSTREAD
 180 #define DHD_FIRSTREAD   32
 181 #endif
 182 #if !ISPOWEROF2(DHD_FIRSTREAD)
 183 #error DHD_FIRSTREAD is not a power of 2!
 184 #endif
 185
 186 /* Total length of frame header for dongle protocol */
 187 #define SDPCM_HDRLEN    (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
 188 #ifdef SDTEST
 189 #define SDPCM_RESERVE   (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
 190 #else
 191 #define SDPCM_RESERVE   (SDPCM_HDRLEN + DHD_SDALIGN)
 192 #endif
 193
 194 /*
 195  * Software allocation of To SB Mailbox resources
 196  */
 197
 198 /* tosbmailbox bits corresponding to intstatus bits */
 199 #define SMB_NAK         (1 << 0)        /* Frame NAK */
 200 #define SMB_INT_ACK     (1 << 1)        /* Host Interrupt ACK */
 201 #define SMB_USE_OOB     (1 << 2)        /* Use OOB Wakeup */
 202 #define SMB_DEV_INT     (1 << 3)        /* Miscellaneous Interrupt */
 203
 204 /* tosbmailboxdata */
 205 #define SMB_DATA_VERSION_SHIFT  16      /* host protocol version */
 206
 207 /*
 208  * Software allocation of To Host Mailbox resources
 209  */
 210
 211 /* intstatus bits */
 212 #define I_HMB_FC_STATE  I_HMB_SW0       /* Flow Control State */
 213 #define I_HMB_FC_CHANGE I_HMB_SW1       /* Flow Control State Changed */
 214 #define I_HMB_FRAME_IND I_HMB_SW2       /* Frame Indication */
 215 #define I_HMB_HOST_INT  I_HMB_SW3       /* Miscellaneous Interrupt */
 216
 217 /* tohostmailboxdata */
 218 #define HMB_DATA_NAKHANDLED     1       /* retransmit NAK'd frame */
 219 #define HMB_DATA_DEVREADY       2       /* talk to host after enable */
 220 #define HMB_DATA_FC             4       /* per prio flowcontrol update flag */
 221 #define HMB_DATA_FWREADY        8       /* fw ready for protocol activity */
 222
 223 #define HMB_DATA_FCDATA_MASK    0xff000000
 224 #define HMB_DATA_FCDATA_SHIFT   24
 225
 226 #define HMB_DATA_VERSION_MASK   0x00ff0000
 227 #define HMB_DATA_VERSION_SHIFT  16
 228
 229 /*
 230  * Software-defined protocol header
 231  */
 232
 233 /* Current protocol version */
 234 #define SDPCM_PROT_VERSION      4
 235
 236 /* SW frame header */
 237 #define SDPCM_PACKET_SEQUENCE(p)        (((u8 *)p)[0] & 0xff)
 238
 239 #define SDPCM_CHANNEL_MASK              0x00000f00
 240 #define SDPCM_CHANNEL_SHIFT             8
 241 #define SDPCM_PACKET_CHANNEL(p)         (((u8 *)p)[1] & 0x0f)
 242
 243 #define SDPCM_NEXTLEN_OFFSET            2
 244
 245 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
 246 #define SDPCM_DOFFSET_OFFSET            3       /* Data Offset */
 247 #define SDPCM_DOFFSET_VALUE(p)          (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
 248 #define SDPCM_DOFFSET_MASK              0xff000000
 249 #define SDPCM_DOFFSET_SHIFT             24
 250 #define SDPCM_FCMASK_OFFSET             4       /* Flow control */
 251 #define SDPCM_FCMASK_VALUE(p)           (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
 252 #define SDPCM_WINDOW_OFFSET             5       /* Credit based fc */
 253 #define SDPCM_WINDOW_VALUE(p)           (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
 254
 255 #define SDPCM_SWHEADER_LEN      8       /* SW header is 64 bits */
 256
 257 /* logical channel numbers */
 258 #define SDPCM_CONTROL_CHANNEL   0       /* Control channel Id */
 259 #define SDPCM_EVENT_CHANNEL     1       /* Asyc Event Indication Channel Id */
 260 #define SDPCM_DATA_CHANNEL      2       /* Data Xmit/Recv Channel Id */
 261 #define SDPCM_GLOM_CHANNEL      3       /* For coalesced packets */
 262 #define SDPCM_TEST_CHANNEL      15      /* Reserved for test/debug packets */
 263
 264 #define SDPCM_SEQUENCE_WRAP     256     /* wrap-around val for 8bit frame seq */
 265
 266 #define SDPCM_GLOMDESC(p)       (((u8 *)p)[1] & 0x80)
 267
 268 /* For TEST_CHANNEL packets, define another 4-byte header */
 269 #define SDPCM_TEST_HDRLEN       4       /*
 270                                          * Generally: Cmd(1), Ext(1), Len(2);
 271                                          * Semantics of Ext byte depend on
 272                                          * command. Len is current or requested
 273                                          * frame length, not including test
 274                                          * header; sent little-endian.
 275                                          */
 276 #define SDPCM_TEST_DISCARD      0x01    /* Receiver discards. Ext:pattern id. */
 277 #define SDPCM_TEST_ECHOREQ      0x02    /* Echo request. Ext:pattern id. */
 278 #define SDPCM_TEST_ECHORSP      0x03    /* Echo response. Ext:pattern id. */
 279 #define SDPCM_TEST_BURST        0x04    /*
 280                                          * Receiver to send a burst.
 281                                          * Ext is a frame count
 282                                          */
 283 #define SDPCM_TEST_SEND         0x05    /*
 284                                          * Receiver sets send mode.
 285                                          * Ext is boolean on/off
 286                                          */
 287
 288 /* Handy macro for filling in datagen packets with a pattern */
 289 #define SDPCM_TEST_FILL(byteno, id)     ((u8)(id + byteno))
 290
 291 /*
 292  * Shared structure between dongle and the host.
 293  * The structure contains pointers to trap or assert information.
 294  */
 295 #define SDPCM_SHARED_VERSION       0x0002
 296 #define SDPCM_SHARED_VERSION_MASK  0x00FF
 297 #define SDPCM_SHARED_ASSERT_BUILT  0x0100
 298 #define SDPCM_SHARED_ASSERT        0x0200
 299 #define SDPCM_SHARED_TRAP          0x0400
 300
 301
 302 /* Space for header read, limit for data packets */
 303 #ifndef MAX_HDR_READ
 304 #define MAX_HDR_READ    32
 305 #endif
 306 #if !ISPOWEROF2(MAX_HDR_READ)
 307 #error MAX_HDR_READ is not a power of 2!
 308 #endif
 309
 310 #define MAX_RX_DATASZ   2048
 311
 312 /* Maximum milliseconds to wait for F2 to come up */
 313 #define DHD_WAIT_F2RDY  3000
 314
 315 /* Bump up limit on waiting for HT to account for first startup;
 316  * if the image is doing a CRC calculation before programming the PMU
 317  * for HT availability, it could take a couple hundred ms more, so
 318  * max out at a 1 second (1000000us).
 319  */
 320 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
 321 #undef PMU_MAX_TRANSITION_DLY
 322 #define PMU_MAX_TRANSITION_DLY 1000000
 323 #endif
 324
 325 /* Value for ChipClockCSR during initial setup */
 326 #define DHD_INIT_CLKCTL1        (SBSDIO_FORCE_HW_CLKREQ_OFF |   \
 327                                         SBSDIO_ALP_AVAIL_REQ)
 328 #define DHD_INIT_CLKCTL2        (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
 329
 330 /* Flags for SDH calls */
 331 #define F2SYNC  (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
 332
 333 /* sbimstate */
 334 #define SBIM_IBE                0x20000 /* inbanderror */
 335 #define SBIM_TO                 0x40000 /* timeout */
 336 #define SBIM_BY                 0x01800000      /* busy (sonics >= 2.3) */
 337 #define SBIM_RJ                 0x02000000      /* reject (sonics >= 2.3) */
 338
 339 /* sbtmstatelow */
 340 #define SBTML_RESET             0x0001  /* reset */
 341 #define SBTML_REJ_MASK          0x0006  /* reject field */
 342 #define SBTML_REJ               0x0002  /* reject */
 343 #define SBTML_TMPREJ            0x0004  /* temporary reject, for error recovery */
 344
 345 #define SBTML_SICF_SHIFT        16      /* Shift to locate the SI control flags in sbtml */
 346
 347 /* sbtmstatehigh */
 348 #define SBTMH_SERR              0x0001  /* serror */
 349 #define SBTMH_INT               0x0002  /* interrupt */
 350 #define SBTMH_BUSY              0x0004  /* busy */
 351 #define SBTMH_TO                0x0020  /* timeout (sonics >= 2.3) */
 352
 353 #define SBTMH_SISF_SHIFT        16      /* Shift to locate the SI status flags in sbtmh */
 354
 355 /* sbidlow */
 356 #define SBIDL_INIT              0x80    /* initiator */
 357
 358 /* sbidhigh */
 359 #define SBIDH_RC_MASK           0x000f  /* revision code */
 360 #define SBIDH_RCE_MASK          0x7000  /* revision code extension field */
 361 #define SBIDH_RCE_SHIFT         8
 362 #define SBCOREREV(sbidh) \
 363         ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
 364 #define SBIDH_CC_MASK           0x8ff0  /* core code */
 365 #define SBIDH_CC_SHIFT          4
 366 #define SBIDH_VC_MASK           0xffff0000      /* vendor code */
 367 #define SBIDH_VC_SHIFT          16
 368
 369 /*
 370  * Conversion of 802.1D priority to precedence level
 371  */
 372 #define PRIO2PREC(prio) \
 373         (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
 374         ((prio^2)) : (prio))
 375
 376 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
 377 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
 378                             uint len);
 379
 380 /* Core reg address translation */
 381 #define CORE_CC_REG(base, field)        (base + offsetof(chipcregs_t, field))
 382 #define CORE_BUS_REG(base, field) \
 383                 (base + offsetof(struct sdpcmd_regs, field))
 384 #define CORE_SB(base, field) \
 385                 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
 386
 387 #ifdef DHD_DEBUG
 388 /* Device console log buffer state */
 389 typedef struct dhd_console {
 390         uint count;             /* Poll interval msec counter */
 391         uint log_addr;          /* Log struct address (fixed) */
 392         rte_log_t log;  /* Log struct (host copy) */
 393         uint bufsize;           /* Size of log buffer */
 394         u8 *buf;                /* Log buffer (host copy) */
 395         uint last;              /* Last buffer read index */
 396 } dhd_console_t;
 397 #endif                          /* DHD_DEBUG */
 398
 399 struct sdpcm_shared {
 400         u32 flags;
 401         u32 trap_addr;
 402         u32 assert_exp_addr;
 403         u32 assert_file_addr;
 404         u32 assert_line;
 405         u32 console_addr;       /* Address of rte_cons_t */
 406         u32 msgtrace_addr;
 407         u8 tag[32];
 408 };
 409
 410
 411 /* misc chip info needed by some of the routines */
 412 struct chip_info {
 413         u32 chip;
 414         u32 chiprev;
 415         u32 cccorebase;
 416         u32 ccrev;
 417         u32 cccaps;
 418         u32 buscorebase;
 419         u32 buscorerev;
 420         u32 buscoretype;
 421         u32 ramcorebase;
 422         u32 armcorebase;
 423         u32 pmurev;
 424         u32 ramsize;
 425 };
 426
 427 /* Private data for SDIO bus interaction */
 428 typedef struct dhd_bus {
 429         dhd_pub_t *dhd;
 430
 431         bcmsdh_info_t *sdh;     /* Handle for BCMSDH calls */
 432         struct chip_info *ci;   /* Chip info struct */
 433         char *vars;             /* Variables (from CIS and/or other) */
 434         uint varsz;             /* Size of variables buffer */
 435         u32 sbaddr;             /* Current SB window pointer (-1, invalid) */
 436
 437         struct sdpcmd_regs *regs;       /* SDIO core */
 438         uint sdpcmrev;          /* SDIO core revision */
 439         uint armrev;            /* CPU core revision */
 440         uint ramrev;            /* SOCRAM core revision */
 441         u32 ramsize;            /* Size of RAM in SOCRAM (bytes) */
 442         u32 orig_ramsize;       /* Size of RAM in SOCRAM (bytes) */
 443
 444         u32 bus;                /* gSPI or SDIO bus */
 445         u32 hostintmask;        /* Copy of Host Interrupt Mask */
 446         u32 intstatus;  /* Intstatus bits (events) pending */
 447         bool dpc_sched;         /* Indicates DPC schedule (intrpt rcvd) */
 448         bool fcstate;           /* State of dongle flow-control */
 449
 450         u16 cl_devid;   /* cached devid for dhdsdio_probe_attach() */
 451         char *fw_path;          /* module_param: path to firmware image */
 452         char *nv_path;          /* module_param: path to nvram vars file */
 453         const char *nvram_params;       /* user specified nvram params. */
 454
 455         uint blocksize;         /* Block size of SDIO transfers */
 456         uint roundup;           /* Max roundup limit */
 457
 458         struct pktq txq;        /* Queue length used for flow-control */
 459         u8 flowcontrol; /* per prio flow control bitmask */
 460         u8 tx_seq;              /* Transmit sequence number (next) */
 461         u8 tx_max;              /* Maximum transmit sequence allowed */
 462
 463         u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
 464         u8 *rxhdr;              /* Header of current rx frame (in hdrbuf) */
 465         u16 nextlen;            /* Next Read Len from last header */
 466         u8 rx_seq;              /* Receive sequence number (expected) */
 467         bool rxskip;            /* Skip receive (awaiting NAK ACK) */
 468
 469         struct sk_buff *glomd;  /* Packet containing glomming descriptor */
 470         struct sk_buff *glom;   /* Packet chain for glommed superframe */
 471         uint glomerr;           /* Glom packet read errors */
 472
 473         u8 *rxbuf;              /* Buffer for receiving control packets */
 474         uint rxblen;            /* Allocated length of rxbuf */
 475         u8 *rxctl;              /* Aligned pointer into rxbuf */
 476         u8 *databuf;            /* Buffer for receiving big glom packet */
 477         u8 *dataptr;            /* Aligned pointer into databuf */
 478         uint rxlen;             /* Length of valid data in buffer */
 479
 480         u8 sdpcm_ver;   /* Bus protocol reported by dongle */
 481
 482         bool intr;              /* Use interrupts */
 483         bool poll;              /* Use polling */
 484         bool ipend;             /* Device interrupt is pending */
 485         bool intdis;            /* Interrupts disabled by isr */
 486         uint intrcount;         /* Count of device interrupt callbacks */
 487         uint lastintrs;         /* Count as of last watchdog timer */
 488         uint spurious;          /* Count of spurious interrupts */
 489         uint pollrate;          /* Ticks between device polls */
 490         uint polltick;          /* Tick counter */
 491         uint pollcnt;           /* Count of active polls */
 492
 493 #ifdef DHD_DEBUG
 494         dhd_console_t console;  /* Console output polling support */
 495         uint console_addr;      /* Console address from shared struct */
 496 #endif                          /* DHD_DEBUG */
 497
 498         uint regfails;          /* Count of R_REG/W_REG failures */
 499
 500         uint clkstate;          /* State of sd and backplane clock(s) */
 501         bool activity;          /* Activity flag for clock down */
 502         s32 idletime;           /* Control for activity timeout */
 503         s32 idlecount;  /* Activity timeout counter */
 504         s32 idleclock;  /* How to set bus driver when idle */
 505         s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
 506         bool use_rxchain;       /* If dhd should use PKT chains */
 507         bool sleeping;          /* Is SDIO bus sleeping? */
 508         bool rxflow_mode;       /* Rx flow control mode */
 509         bool rxflow;            /* Is rx flow control on */
 510         uint prev_rxlim_hit;    /* Is prev rx limit exceeded
 511                                          (per dpc schedule) */
 512         bool alp_only;          /* Don't use HT clock (ALP only) */
 513 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
 514         bool usebufpool;
 515
 516 #ifdef SDTEST
 517         /* external loopback */
 518         bool ext_loop;
 519         u8 loopid;
 520
 521         /* pktgen configuration */
 522         uint pktgen_freq;       /* Ticks between bursts */
 523         uint pktgen_count;      /* Packets to send each burst */
 524         uint pktgen_print;      /* Bursts between count displays */
 525         uint pktgen_total;      /* Stop after this many */
 526         uint pktgen_minlen;     /* Minimum packet data len */
 527         uint pktgen_maxlen;     /* Maximum packet data len */
 528         uint pktgen_mode;       /* Configured mode: tx, rx, or echo */
 529         uint pktgen_stop;       /* Number of tx failures causing stop */
 530
 531         /* active pktgen fields */
 532         uint pktgen_tick;       /* Tick counter for bursts */
 533         uint pktgen_ptick;      /* Burst counter for printing */
 534         uint pktgen_sent;       /* Number of test packets generated */
 535         uint pktgen_rcvd;       /* Number of test packets received */
 536         uint pktgen_fail;       /* Number of failed send attempts */
 537         u16 pktgen_len; /* Length of next packet to send */
 538 #endif                          /* SDTEST */
 539
 540         /* Some additional counters */
 541         uint tx_sderrs;         /* Count of tx attempts with sd errors */
 542         uint fcqueued;          /* Tx packets that got queued */
 543         uint rxrtx;             /* Count of rtx requests (NAK to dongle) */
 544         uint rx_toolong;        /* Receive frames too long to receive */
 545         uint rxc_errors;        /* SDIO errors when reading control frames */
 546         uint rx_hdrfail;        /* SDIO errors on header reads */
 547         uint rx_badhdr;         /* Bad received headers (roosync?) */
 548         uint rx_badseq;         /* Mismatched rx sequence number */
 549         uint fc_rcvd;           /* Number of flow-control events received */
 550         uint fc_xoff;           /* Number which turned on flow-control */
 551         uint fc_xon;            /* Number which turned off flow-control */
 552         uint rxglomfail;        /* Failed deglom attempts */
 553         uint rxglomframes;      /* Number of glom frames (superframes) */
 554         uint rxglompkts;        /* Number of packets from glom frames */
 555         uint f2rxhdrs;          /* Number of header reads */
 556         uint f2rxdata;          /* Number of frame data reads */
 557         uint f2txdata;          /* Number of f2 frame writes */
 558         uint f1regdata;         /* Number of f1 register accesses */
 559
 560         u8 *ctrl_frame_buf;
 561         u32 ctrl_frame_len;
 562         bool ctrl_frame_stat;
 563 } dhd_bus_t;
 564
 565 typedef volatile struct _sbconfig {
 566         u32 PAD[2];
 567         u32 sbipsflag;  /* initiator port ocp slave flag */
 568         u32 PAD[3];
 569         u32 sbtpsflag;  /* target port ocp slave flag */
 570         u32 PAD[11];
 571         u32 sbtmerrloga;        /* (sonics >= 2.3) */
 572         u32 PAD;
 573         u32 sbtmerrlog; /* (sonics >= 2.3) */
 574         u32 PAD[3];
 575         u32 sbadmatch3; /* address match3 */
 576         u32 PAD;
 577         u32 sbadmatch2; /* address match2 */
 578         u32 PAD;
 579         u32 sbadmatch1; /* address match1 */
 580         u32 PAD[7];
 581         u32 sbimstate;  /* initiator agent state */
 582         u32 sbintvec;   /* interrupt mask */
 583         u32 sbtmstatelow;       /* target state */
 584         u32 sbtmstatehigh;      /* target state */
 585         u32 sbbwa0;             /* bandwidth allocation table0 */
 586         u32 PAD;
 587         u32 sbimconfiglow;      /* initiator configuration */
 588         u32 sbimconfighigh;     /* initiator configuration */
 589         u32 sbadmatch0; /* address match0 */
 590         u32 PAD;
 591         u32 sbtmconfiglow;      /* target configuration */
 592         u32 sbtmconfighigh;     /* target configuration */
 593         u32 sbbconfig;  /* broadcast configuration */
 594         u32 PAD;
 595         u32 sbbstate;   /* broadcast state */
 596         u32 PAD[3];
 597         u32 sbactcnfg;  /* activate configuration */
 598         u32 PAD[3];
 599         u32 sbflagst;   /* current sbflags */
 600         u32 PAD[3];
 601         u32 sbidlow;            /* identification */
 602         u32 sbidhigh;   /* identification */
 603 } sbconfig_t;
 604
 605 /* clkstate */
 606 #define CLK_NONE        0
 607 #define CLK_SDONLY      1
 608 #define CLK_PENDING     2       /* Not used yet */
 609 #define CLK_AVAIL       3
 610
 611 #define DHD_NOPMU(dhd)  (false)
 612
 613 #ifdef DHD_DEBUG
 614 static int qcount[NUMPRIO];
 615 static int tx_packets[NUMPRIO];
 616 #endif                          /* DHD_DEBUG */
 617
 618 /* Deferred transmit */
 619 const uint dhd_deferred_tx = 1;
 620
 621 extern uint dhd_watchdog_ms;
 622 extern void dhd_os_wd_timer(void *bus, uint wdtick);
 623
 624 /* Tx/Rx bounds */
 625 uint dhd_txbound;
 626 uint dhd_rxbound;
 627 uint dhd_txminmax;
 628
 629 /* override the RAM size if possible */
 630 #define DONGLE_MIN_MEMSIZE (128 * 1024)
 631 int dhd_dongle_memsize;
 632
 633 static bool dhd_alignctl;
 634
 635 static bool sd1idle;
 636
 637 static bool retrydata;
 638 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
 639
 640 static const uint watermark = 8;
 641 static const uint firstread = DHD_FIRSTREAD;
 642
 643 #define HDATLEN (firstread - (SDPCM_HDRLEN))
 644
 645 /* Retry count for register access failures */
 646 static const uint retry_limit = 2;
 647
 648 /* Force even SD lengths (some host controllers mess up on odd bytes) */
 649 static bool forcealign;
 650
 651 #define ALIGNMENT  4
 652
 653 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
 654 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
 655 #endif
 656
 657 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
 658 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
 659 #endif  /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
 660 #define PKTALIGN(_p, _len, _align)                              \
 661         do {                                                            \
 662                 uint datalign;                                          \
 663                 datalign = (unsigned long)((_p)->data);                 \
 664                 datalign = roundup(datalign, (_align)) - datalign;      \
 665                 ASSERT(datalign < (_align));                            \
 666                 ASSERT((_p)->len >= ((_len) + datalign));               \
 667                 if (datalign)                                           \
 668                         skb_pull((_p), datalign);                       \
 669                 __skb_trim((_p), (_len));                               \
 670         } while (0)
 671
 672 /* Limit on rounding up frames */
 673 static const uint max_roundup = 512;
 674
 675 /* Try doing readahead */
 676 static bool dhd_readahead;
 677
 678 /* To check if there's window offered */
 679 #define DATAOK(bus) \
 680         (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
 681         (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
 682
 683 /* Macros to get register read/write status */
 684 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
 685 #define R_SDREG(regvar, regaddr, retryvar) \
 686 do { \
 687         retryvar = 0; \
 688         do { \
 689                 regvar = R_REG(regaddr); \
 690         } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
 691         if (retryvar) { \
 692                 bus->regfails += (retryvar-1); \
 693                 if (retryvar > retry_limit) { \
 694                         DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
 695                         __func__, __LINE__)); \
 696                         regvar = 0; \
 697                 } \
 698         } \
 699 } while (0)
 700
 701 #define W_SDREG(regval, regaddr, retryvar) \
 702 do { \
 703         retryvar = 0; \
 704         do { \
 705                 W_REG(regaddr, regval); \
 706         } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
 707         if (retryvar) { \
 708                 bus->regfails += (retryvar-1); \
 709                 if (retryvar > retry_limit) \
 710                         DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
 711                         __func__, __LINE__)); \
 712         } \
 713 } while (0)
 714
 715 #define DHD_BUS                 SDIO_BUS
 716
 717 #define PKT_AVAILABLE()         (intstatus & I_HMB_FRAME_IND)
 718
 719 #define HOSTINTMASK             (I_HMB_SW_MASK | I_CHIPACTIVE)
 720
 721 #ifdef SDTEST
 722 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
 723 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
 724 #endif
 725
 726 #ifdef DHD_DEBUG
 727 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
 728 static int dhdsdio_mem_dump(dhd_bus_t *bus);
 729 #endif                          /* DHD_DEBUG  */
 730 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
 731
 732 static void dhdsdio_release(dhd_bus_t *bus);
 733 static void dhdsdio_release_malloc(dhd_bus_t *bus);
 734 static void dhdsdio_disconnect(void *ptr);
 735 static bool dhdsdio_chipmatch(u16 chipid);
 736 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
 737                                  void *regsva, u16 devid);
 738 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
 739 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
 740 static void dhdsdio_release_dongle(dhd_bus_t *bus);
 741
 742 static uint process_nvram_vars(char *varbuf, uint len);
 743
 744 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
 745 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
 746                                uint flags, u8 *buf, uint nbytes,
 747                                struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
 748                                void *handle);
 749
 750 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
 751 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
 752
 753 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
 754 static int dhdsdio_download_nvram(struct dhd_bus *bus);
 755 static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
 756 static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
 757 static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
 758 static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
 759                                         u32 drivestrength);
 760 static void dhdsdio_chip_detach(struct dhd_bus *bus);
 761
 762 /* Packet free applicable unconditionally for sdio and sdspi.
 763  * Conditional if bufpool was present for gspi bus.
 764  */
 765 static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
 766 {
 767         dhd_os_sdlock_rxq(bus->dhd);
 768         if ((bus->bus != SPI_BUS) || bus->usebufpool)
 769                 bcm_pkt_buf_free_skb(pkt);
 770         dhd_os_sdunlock_rxq(bus->dhd);
 771 }
 772
 773 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
 774 {
 775         s32 min_size = DONGLE_MIN_MEMSIZE;
 776         /* Restrict the memsize to user specified limit */
 777         DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
 778                 dhd_dongle_memsize, min_size));
 779         if ((dhd_dongle_memsize > min_size) &&
 780             (dhd_dongle_memsize < (s32) bus->orig_ramsize))
 781                 bus->ramsize = dhd_dongle_memsize;
 782 }
 783
 784 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
 785 {
 786         int err = 0;
 787         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
 788                          (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
 789         if (!err)
 790                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
 791                                  (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
 792         if (!err)
 793                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
 794                                  (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
 795                                  &err);
 796         return err;
 797 }
 798
 799 /* Turn backplane clock on or off */
 800 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
 801 {
 802         int err;
 803         u8 clkctl, clkreq, devctl;
 804         bcmsdh_info_t *sdh;
 805
 806         DHD_TRACE(("%s: Enter\n", __func__));
 807
 808 #if defined(OOB_INTR_ONLY)
 809         pendok = false;
 810 #endif
 811         clkctl = 0;
 812         sdh = bus->sdh;
 813
 814         if (on) {
 815                 /* Request HT Avail */
 816                 clkreq =
 817                     bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
 818
 819                 if ((bus->ci->chip == BCM4329_CHIP_ID)
 820                     && (bus->ci->chiprev == 0))
 821                         clkreq |= SBSDIO_FORCE_ALP;
 822
 823                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 824                                  clkreq, &err);
 825                 if (err) {
 826                         DHD_ERROR(("%s: HT Avail request error: %d\n",
 827                                    __func__, err));
 828                         return -EBADE;
 829                 }
 830
 831                 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
 832                                && (bus->ci->buscorerev == 9))) {
 833                         u32 dummy, retries;
 834                         R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
 835                 }
 836
 837                 /* Check current status */
 838                 clkctl =
 839                     bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 840                                     &err);
 841                 if (err) {
 842                         DHD_ERROR(("%s: HT Avail read error: %d\n",
 843                                    __func__, err));
 844                         return -EBADE;
 845                 }
 846
 847                 /* Go to pending and await interrupt if appropriate */
 848                 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
 849                         /* Allow only clock-available interrupt */
 850                         devctl =
 851                             bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 852                                             &err);
 853                         if (err) {
 854                                 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
 855                                         __func__, err));
 856                                 return -EBADE;
 857                         }
 858
 859                         devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
 860                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 861                                          devctl, &err);
 862                         DHD_INFO(("CLKCTL: set PENDING\n"));
 863                         bus->clkstate = CLK_PENDING;
 864
 865                         return 0;
 866                 } else if (bus->clkstate == CLK_PENDING) {
 867                         /* Cancel CA-only interrupt filter */
 868                         devctl =
 869                             bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 870                                             &err);
 871                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
 872                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 873                                          devctl, &err);
 874                 }
 875
 876                 /* Otherwise, wait here (polling) for HT Avail */
 877                 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
 878                         SPINWAIT_SLEEP(sdioh_spinwait_sleep,
 879                                        ((clkctl =
 880                                          bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
 881                                                  SBSDIO_FUNC1_CHIPCLKCSR,
 882                                                          &err)),
 883                                         !SBSDIO_CLKAV(clkctl, bus->alp_only)),
 884                                        PMU_MAX_TRANSITION_DLY);
 885                 }
 886                 if (err) {
 887                         DHD_ERROR(("%s: HT Avail request error: %d\n",
 888                                    __func__, err));
 889                         return -EBADE;
 890                 }
 891                 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
 892                         DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
 893                                    __func__, PMU_MAX_TRANSITION_DLY, clkctl));
 894                         return -EBADE;
 895                 }
 896
 897                 /* Mark clock available */
 898                 bus->clkstate = CLK_AVAIL;
 899                 DHD_INFO(("CLKCTL: turned ON\n"));
 900
 901 #if defined(DHD_DEBUG)
 902                 if (bus->alp_only == true) {
 903 #if !defined(BCMLXSDMMC)
 904                         if (!SBSDIO_ALPONLY(clkctl)) {
 905                                 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
 906                                            __func__));
 907                         }
 908 #endif                          /* !defined(BCMLXSDMMC) */
 909                 } else {
 910                         if (SBSDIO_ALPONLY(clkctl)) {
 911                                 DHD_ERROR(("%s: HT Clock should be on.\n",
 912                                            __func__));
 913                         }
 914                 }
 915 #endif                          /* defined (DHD_DEBUG) */
 916
 917                 bus->activity = true;
 918         } else {
 919                 clkreq = 0;
 920
 921                 if (bus->clkstate == CLK_PENDING) {
 922                         /* Cancel CA-only interrupt filter */
 923                         devctl =
 924                             bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 925                                             &err);
 926                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
 927                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 928                                          devctl, &err);
 929                 }
 930
 931                 bus->clkstate = CLK_SDONLY;
 932                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 933                                  clkreq, &err);
 934                 DHD_INFO(("CLKCTL: turned OFF\n"));
 935                 if (err) {
 936                         DHD_ERROR(("%s: Failed access turning clock off: %d\n",
 937                                    __func__, err));
 938                         return -EBADE;
 939                 }
 940         }
 941         return 0;
 942 }
 943
 944 /* Change idle/active SD state */
 945 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
 946 {
 947         DHD_TRACE(("%s: Enter\n", __func__));
 948
 949         if (on)
 950                 bus->clkstate = CLK_SDONLY;
 951         else
 952                 bus->clkstate = CLK_NONE;
 953
 954         return 0;
 955 }
 956
 957 /* Transition SD and backplane clock readiness */
 958 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
 959 {
 960 #ifdef DHD_DEBUG
 961         uint oldstate = bus->clkstate;
 962 #endif                          /* DHD_DEBUG */
 963
 964         DHD_TRACE(("%s: Enter\n", __func__));
 965
 966         /* Early exit if we're already there */
 967         if (bus->clkstate == target) {
 968                 if (target == CLK_AVAIL) {
 969                         dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
 970                         bus->activity = true;
 971                 }
 972                 return 0;
 973         }
 974
 975         switch (target) {
 976         case CLK_AVAIL:
 977                 /* Make sure SD clock is available */
 978                 if (bus->clkstate == CLK_NONE)
 979                         dhdsdio_sdclk(bus, true);
 980                 /* Now request HT Avail on the backplane */
 981                 dhdsdio_htclk(bus, true, pendok);
 982                 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
 983                 bus->activity = true;
 984                 break;
 985
 986         case CLK_SDONLY:
 987                 /* Remove HT request, or bring up SD clock */
 988                 if (bus->clkstate == CLK_NONE)
 989                         dhdsdio_sdclk(bus, true);
 990                 else if (bus->clkstate == CLK_AVAIL)
 991                         dhdsdio_htclk(bus, false, false);
 992                 else
 993                         DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
 994                                    bus->clkstate, target));
 995                 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
 996                 break;
 997
 998         case CLK_NONE:
 999                 /* Make sure to remove HT request */
1000                 if (bus->clkstate == CLK_AVAIL)
1001                         dhdsdio_htclk(bus, false, false);
1002                 /* Now remove the SD clock */
1003                 dhdsdio_sdclk(bus, false);
1004                 dhd_os_wd_timer(bus->dhd, 0);
1005                 break;
1006         }
1007 #ifdef DHD_DEBUG
1008         DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1009 #endif                          /* DHD_DEBUG */
1010
1011         return 0;
1012 }
1013
1014 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
1015 {
1016         bcmsdh_info_t *sdh = bus->sdh;
1017         struct sdpcmd_regs *regs = bus->regs;
1018         uint retries = 0;
1019
1020         DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
1021                   (sleep ? "SLEEP" : "WAKE"),
1022                   (bus->sleeping ? "SLEEP" : "WAKE")));
1023
1024         /* Done if we're already in the requested state */
1025         if (sleep == bus->sleeping)
1026                 return 0;
1027
1028         /* Going to sleep: set the alarm and turn off the lights... */
1029         if (sleep) {
1030                 /* Don't sleep if something is pending */
1031                 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1032                         return -EBUSY;
1033
1034                 /* Disable SDIO interrupts (no longer interested) */
1035                 bcmsdh_intr_disable(bus->sdh);
1036
1037                 /* Make sure the controller has the bus up */
1038                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1039
1040                 /* Tell device to start using OOB wakeup */
1041                 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
1042                 if (retries > retry_limit)
1043                         DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1044
1045                 /* Turn off our contribution to the HT clock request */
1046                 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1047
1048                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1049                                  SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1050
1051                 /* Isolate the bus */
1052                 if (bus->ci->chip != BCM4329_CHIP_ID
1053                     && bus->ci->chip != BCM4319_CHIP_ID) {
1054                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
1055                                          SBSDIO_DEVCTL_PADS_ISO, NULL);
1056                 }
1057
1058                 /* Change state */
1059                 bus->sleeping = true;
1060
1061         } else {
1062                 /* Waking up: bus power up is ok, set local state */
1063
1064                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1065                                  0, NULL);
1066
1067                 /* Force pad isolation off if possible
1068                          (in case power never toggled) */
1069                 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1070                     && (bus->ci->buscorerev >= 10))
1071                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
1072                                          NULL);
1073
1074                 /* Make sure the controller has the bus up */
1075                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1076
1077                 /* Send misc interrupt to indicate OOB not needed */
1078                 W_SDREG(0, &regs->tosbmailboxdata, retries);
1079                 if (retries <= retry_limit)
1080                         W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
1081
1082                 if (retries > retry_limit)
1083                         DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1084
1085                 /* Make sure we have SD bus access */
1086                 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1087
1088                 /* Change state */
1089                 bus->sleeping = false;
1090
1091                 /* Enable interrupts again */
1092                 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
1093                         bus->intdis = false;
1094                         bcmsdh_intr_enable(bus->sdh);
1095                 }
1096         }
1097
1098         return 0;
1099 }
1100
1101 #if defined(OOB_INTR_ONLY)
1102 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
1103 {
1104 #if defined(HW_OOB)
1105         bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
1106 #else
1107         sdpcmd_regs_t *regs = bus->regs;
1108         uint retries = 0;
1109
1110         dhdsdio_clkctl(bus, CLK_AVAIL, false);
1111         if (enable == true) {
1112
1113                 /* Tell device to start using OOB wakeup */
1114                 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
1115                 if (retries > retry_limit)
1116                         DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1117
1118         } else {
1119                 /* Send misc interrupt to indicate OOB not needed */
1120                 W_SDREG(0, &regs->tosbmailboxdata, retries);
1121                 if (retries <= retry_limit)
1122                         W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
1123         }
1124
1125         /* Turn off our contribution to the HT clock request */
1126         dhdsdio_clkctl(bus, CLK_SDONLY, false);
1127 #endif                          /* !defined(HW_OOB) */
1128 }
1129 #endif                          /* defined(OOB_INTR_ONLY) */
1130
1131 #define BUS_WAKE(bus) \
1132         do { \
1133                 if ((bus)->sleeping) \
1134                         dhdsdio_bussleep((bus), false); \
1135         } while (0);
1136
1137 /* Writes a HW/SW header into the packet and sends it. */
1138 /* Assumes: (a) header space already there, (b) caller holds lock */
1139 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1140                          bool free_pkt)
1141 {
1142         int ret;
1143         u8 *frame;
1144         u16 len, pad = 0;
1145         u32 swheader;
1146         uint retries = 0;
1147         bcmsdh_info_t *sdh;
1148         struct sk_buff *new;
1149         int i;
1150
1151         DHD_TRACE(("%s: Enter\n", __func__));
1152
1153         sdh = bus->sdh;
1154
1155         if (bus->dhd->dongle_reset) {
1156                 ret = -EPERM;
1157                 goto done;
1158         }
1159
1160         frame = (u8 *) (pkt->data);
1161
1162         /* Add alignment padding, allocate new packet if needed */
1163         pad = ((unsigned long)frame % DHD_SDALIGN);
1164         if (pad) {
1165                 if (skb_headroom(pkt) < pad) {
1166                         DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1167                                   __func__, skb_headroom(pkt), pad));
1168                         bus->dhd->tx_realloc++;
1169                         new = bcm_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1170                         if (!new) {
1171                                 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1172                                         "packet\n",
1173                                         __func__, pkt->len + DHD_SDALIGN));
1174                                 ret = -ENOMEM;
1175                                 goto done;
1176                         }
1177
1178                         PKTALIGN(new, pkt->len, DHD_SDALIGN);
1179                         memcpy(new->data, pkt->data, pkt->len);
1180                         if (free_pkt)
1181                                 bcm_pkt_buf_free_skb(pkt);
1182                         /* free the pkt if canned one is not used */
1183                         free_pkt = true;
1184                         pkt = new;
1185                         frame = (u8 *) (pkt->data);
1186                         ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1187                         pad = 0;
1188                 } else {
1189                         skb_push(pkt, pad);
1190                         frame = (u8 *) (pkt->data);
1191
1192                         ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1193                         memset(frame, 0, pad + SDPCM_HDRLEN);
1194                 }
1195         }
1196         ASSERT(pad < DHD_SDALIGN);
1197
1198         /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1199         len = (u16) (pkt->len);
1200         *(u16 *) frame = cpu_to_le16(len);
1201         *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1202
1203         /* Software tag: channel, sequence number, data offset */
1204         swheader =
1205             ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1206             (((pad +
1207                SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1208
1209         put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1210         put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1211
1212 #ifdef DHD_DEBUG
1213         tx_packets[pkt->priority]++;
1214         if (DHD_BYTES_ON() &&
1215             (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1216               (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1217                 printk(KERN_DEBUG "Tx Frame:\n");
1218                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1219         } else if (DHD_HDRS_ON()) {
1220                 printk(KERN_DEBUG "TxHdr:\n");
1221                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1222                                      frame, min_t(u16, len, 16));
1223         }
1224 #endif
1225
1226         /* Raise len to next SDIO block to eliminate tail command */
1227         if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1228                 u16 pad = bus->blocksize - (len % bus->blocksize);
1229                 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1230 #ifdef NOTUSED
1231                         if (pad <= skb_tailroom(pkt))
1232 #endif                          /* NOTUSED */
1233                                 len += pad;
1234         } else if (len % DHD_SDALIGN) {
1235                 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1236         }
1237
1238         /* Some controllers have trouble with odd bytes -- round to even */
1239         if (forcealign && (len & (ALIGNMENT - 1))) {
1240 #ifdef NOTUSED
1241                 if (skb_tailroom(pkt))
1242 #endif
1243                         len = roundup(len, ALIGNMENT);
1244 #ifdef NOTUSED
1245                 else
1246                         DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1247                                    __func__, len));
1248 #endif
1249         }
1250
1251         do {
1252                 ret =
1253                     dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1254                                         F2SYNC, frame, len, pkt, NULL, NULL);
1255                 bus->f2txdata++;
1256                 ASSERT(ret != -BCME_PENDING);
1257
1258                 if (ret < 0) {
1259                         /* On failure, abort the command
1260                          and terminate the frame */
1261                         DHD_INFO(("%s: sdio error %d, abort command and "
1262                                 "terminate frame.\n", __func__, ret));
1263                         bus->tx_sderrs++;
1264
1265                         bcmsdh_abort(sdh, SDIO_FUNC_2);
1266                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1267                                          SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1268                                          NULL);
1269                         bus->f1regdata++;
1270
1271                         for (i = 0; i < 3; i++) {
1272                                 u8 hi, lo;
1273                                 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1274                                                      SBSDIO_FUNC1_WFRAMEBCHI,
1275                                                      NULL);
1276                                 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1277                                                      SBSDIO_FUNC1_WFRAMEBCLO,
1278                                                      NULL);
1279                                 bus->f1regdata += 2;
1280                                 if ((hi == 0) && (lo == 0))
1281                                         break;
1282                         }
1283
1284                 }
1285                 if (ret == 0)
1286                         bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1287
1288         } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1289
1290 done:
1291         /* restore pkt buffer pointer before calling tx complete routine */
1292         skb_pull(pkt, SDPCM_HDRLEN + pad);
1293         dhd_os_sdunlock(bus->dhd);
1294         dhd_txcomplete(bus->dhd, pkt, ret != 0);
1295         dhd_os_sdlock(bus->dhd);
1296
1297         if (free_pkt)
1298                 bcm_pkt_buf_free_skb(pkt);
1299
1300         return ret;
1301 }
1302
1303 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1304 {
1305         int ret = -EBADE;
1306         uint datalen, prec;
1307
1308         DHD_TRACE(("%s: Enter\n", __func__));
1309
1310         datalen = pkt->len;
1311
1312 #ifdef SDTEST
1313         /* Push the test header if doing loopback */
1314         if (bus->ext_loop) {
1315                 u8 *data;
1316                 skb_push(pkt, SDPCM_TEST_HDRLEN);
1317                 data = pkt->data;
1318                 *data++ = SDPCM_TEST_ECHOREQ;
1319                 *data++ = (u8) bus->loopid++;
1320                 *data++ = (datalen >> 0);
1321                 *data++ = (datalen >> 8);
1322                 datalen += SDPCM_TEST_HDRLEN;
1323         }
1324 #endif                          /* SDTEST */
1325
1326         /* Add space for the header */
1327         skb_push(pkt, SDPCM_HDRLEN);
1328         ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1329
1330         prec = PRIO2PREC((pkt->priority & PRIOMASK));
1331
1332         /* Check for existing queue, current flow-control,
1333                          pending event, or pending clock */
1334         if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1335             || bus->dpc_sched || (!DATAOK(bus))
1336             || (bus->flowcontrol & NBITVAL(prec))
1337             || (bus->clkstate != CLK_AVAIL)) {
1338                 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1339                            pktq_len(&bus->txq)));
1340                 bus->fcqueued++;
1341
1342                 /* Priority based enq */
1343                 dhd_os_sdlock_txq(bus->dhd);
1344                 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1345                         skb_pull(pkt, SDPCM_HDRLEN);
1346                         dhd_txcomplete(bus->dhd, pkt, false);
1347                         bcm_pkt_buf_free_skb(pkt);
1348                         DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1349                         ret = -ENOSR;
1350                 } else {
1351                         ret = 0;
1352                 }
1353                 dhd_os_sdunlock_txq(bus->dhd);
1354
1355                 if (pktq_len(&bus->txq) >= TXHI)
1356                         dhd_txflowcontrol(bus->dhd, 0, ON);
1357
1358 #ifdef DHD_DEBUG
1359                 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1360                         qcount[prec] = pktq_plen(&bus->txq, prec);
1361 #endif
1362                 /* Schedule DPC if needed to send queued packet(s) */
1363                 if (dhd_deferred_tx && !bus->dpc_sched) {
1364                         bus->dpc_sched = true;
1365                         dhd_sched_dpc(bus->dhd);
1366                 }
1367         } else {
1368                 /* Lock: we're about to use shared data/code (and SDIO) */
1369                 dhd_os_sdlock(bus->dhd);
1370
1371                 /* Otherwise, send it now */
1372                 BUS_WAKE(bus);
1373                 /* Make sure back plane ht clk is on, no pending allowed */
1374                 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1375
1376 #ifndef SDTEST
1377                 DHD_TRACE(("%s: calling txpkt\n", __func__));
1378                 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1379 #else
1380                 ret = dhdsdio_txpkt(bus, pkt,
1381                                     (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1382                                      SDPCM_DATA_CHANNEL), true);
1383 #endif
1384                 if (ret)
1385                         bus->dhd->tx_errors++;
1386                 else
1387                         bus->dhd->dstats.tx_bytes += datalen;
1388
1389                 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1390                         bus->activity = false;
1391                         dhdsdio_clkctl(bus, CLK_NONE, true);
1392                 }
1393
1394                 dhd_os_sdunlock(bus->dhd);
1395         }
1396
1397         return ret;
1398 }
1399
1400 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1401 {
1402         struct sk_buff *pkt;
1403         u32 intstatus = 0;
1404         uint retries = 0;
1405         int ret = 0, prec_out;
1406         uint cnt = 0;
1407         uint datalen;
1408         u8 tx_prec_map;
1409
1410         dhd_pub_t *dhd = bus->dhd;
1411         struct sdpcmd_regs *regs = bus->regs;
1412
1413         DHD_TRACE(("%s: Enter\n", __func__));
1414
1415         tx_prec_map = ~bus->flowcontrol;
1416
1417         /* Send frames until the limit or some other event */
1418         for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1419                 dhd_os_sdlock_txq(bus->dhd);
1420                 pkt = bcm_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1421                 if (pkt == NULL) {
1422                         dhd_os_sdunlock_txq(bus->dhd);
1423                         break;
1424                 }
1425                 dhd_os_sdunlock_txq(bus->dhd);
1426                 datalen = pkt->len - SDPCM_HDRLEN;
1427
1428 #ifndef SDTEST
1429                 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1430 #else
1431                 ret = dhdsdio_txpkt(bus, pkt,
1432                                     (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1433                                      SDPCM_DATA_CHANNEL), true);
1434 #endif
1435                 if (ret)
1436                         bus->dhd->tx_errors++;
1437                 else
1438                         bus->dhd->dstats.tx_bytes += datalen;
1439
1440                 /* In poll mode, need to check for other events */
1441                 if (!bus->intr && cnt) {
1442                         /* Check device status, signal pending interrupt */
1443                         R_SDREG(intstatus, &regs->intstatus, retries);
1444                         bus->f2txdata++;
1445                         if (bcmsdh_regfail(bus->sdh))
1446                                 break;
1447                         if (intstatus & bus->hostintmask)
1448                                 bus->ipend = true;
1449                 }
1450         }
1451
1452         /* Deflow-control stack if needed */
1453         if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1454             dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1455                 dhd_txflowcontrol(dhd, 0, OFF);
1456
1457         return cnt;
1458 }
1459
1460 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1461 {
1462         u8 *frame;
1463         u16 len;
1464         u32 swheader;
1465         uint retries = 0;
1466         bcmsdh_info_t *sdh = bus->sdh;
1467         u8 doff = 0;
1468         int ret = -1;
1469         int i;
1470
1471         DHD_TRACE(("%s: Enter\n", __func__));
1472
1473         if (bus->dhd->dongle_reset)
1474                 return -EIO;
1475
1476         /* Back the pointer to make a room for bus header */
1477         frame = msg - SDPCM_HDRLEN;
1478         len = (msglen += SDPCM_HDRLEN);
1479
1480         /* Add alignment padding (optional for ctl frames) */
1481         if (dhd_alignctl) {
1482                 doff = ((unsigned long)frame % DHD_SDALIGN);
1483                 if (doff) {
1484                         frame -= doff;
1485                         len += doff;
1486                         msglen += doff;
1487                         memset(frame, 0, doff + SDPCM_HDRLEN);
1488                 }
1489                 ASSERT(doff < DHD_SDALIGN);
1490         }
1491         doff += SDPCM_HDRLEN;
1492
1493         /* Round send length to next SDIO block */
1494         if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1495                 u16 pad = bus->blocksize - (len % bus->blocksize);
1496                 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1497                         len += pad;
1498         } else if (len % DHD_SDALIGN) {
1499                 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1500         }
1501
1502         /* Satisfy length-alignment requirements */
1503         if (forcealign && (len & (ALIGNMENT - 1)))
1504                 len = roundup(len, ALIGNMENT);
1505
1506         ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1507
1508         /* Need to lock here to protect txseq and SDIO tx calls */
1509         dhd_os_sdlock(bus->dhd);
1510
1511         BUS_WAKE(bus);
1512
1513         /* Make sure backplane clock is on */
1514         dhdsdio_clkctl(bus, CLK_AVAIL, false);
1515
1516         /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1517         *(u16 *) frame = cpu_to_le16((u16) msglen);
1518         *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1519
1520         /* Software tag: channel, sequence number, data offset */
1521         swheader =
1522             ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1523              SDPCM_CHANNEL_MASK)
1524             | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1525                              SDPCM_DOFFSET_MASK);
1526         put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1527         put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1528
1529         if (!DATAOK(bus)) {
1530                 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1531                           __func__, bus->tx_max, bus->tx_seq));
1532                 bus->ctrl_frame_stat = true;
1533                 /* Send from dpc */
1534                 bus->ctrl_frame_buf = frame;
1535                 bus->ctrl_frame_len = len;
1536
1537                 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1538
1539                 if (bus->ctrl_frame_stat == false) {
1540                         DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1541                         ret = 0;
1542                 } else {
1543                         DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1544                         ret = -1;
1545                 }
1546         }
1547
1548         if (ret == -1) {
1549 #ifdef DHD_DEBUG
1550                 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1551                         printk(KERN_DEBUG "Tx Frame:\n");
1552                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1553                                              frame, len);
1554                 } else if (DHD_HDRS_ON()) {
1555                         printk(KERN_DEBUG "TxHdr:\n");
1556                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1557                                              frame, min_t(u16, len, 16));
1558                 }
1559 #endif
1560
1561                 do {
1562                         bus->ctrl_frame_stat = false;
1563                         ret =
1564                             dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1565                                                 SDIO_FUNC_2, F2SYNC, frame, len,
1566                                                 NULL, NULL, NULL);
1567
1568                         ASSERT(ret != -BCME_PENDING);
1569
1570                         if (ret < 0) {
1571                                 /* On failure, abort the command and
1572                                  terminate the frame */
1573                                 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1574                                         __func__, ret));
1575                                 bus->tx_sderrs++;
1576
1577                                 bcmsdh_abort(sdh, SDIO_FUNC_2);
1578
1579                                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1580                                                  SBSDIO_FUNC1_FRAMECTRL,
1581                                                  SFC_WF_TERM, NULL);
1582                                 bus->f1regdata++;
1583
1584                                 for (i = 0; i < 3; i++) {
1585                                         u8 hi, lo;
1586                                         hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1587                                              SBSDIO_FUNC1_WFRAMEBCHI,
1588                                              NULL);
1589                                         lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1590                                              SBSDIO_FUNC1_WFRAMEBCLO,
1591                                                              NULL);
1592                                         bus->f1regdata += 2;
1593                                         if ((hi == 0) && (lo == 0))
1594                                                 break;
1595                                 }
1596
1597                         }
1598                         if (ret == 0) {
1599                                 bus->tx_seq =
1600                                     (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1601                         }
1602                 } while ((ret < 0) && retries++ < TXRETRIES);
1603         }
1604
1605         if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1606                 bus->activity = false;
1607                 dhdsdio_clkctl(bus, CLK_NONE, true);
1608         }
1609
1610         dhd_os_sdunlock(bus->dhd);
1611
1612         if (ret)
1613                 bus->dhd->tx_ctlerrs++;
1614         else
1615                 bus->dhd->tx_ctlpkts++;
1616
1617         return ret ? -EIO : 0;
1618 }
1619
1620 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1621 {
1622         int timeleft;
1623         uint rxlen = 0;
1624         bool pending;
1625
1626         DHD_TRACE(("%s: Enter\n", __func__));
1627
1628         if (bus->dhd->dongle_reset)
1629                 return -EIO;
1630
1631         /* Wait until control frame is available */
1632         timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1633
1634         dhd_os_sdlock(bus->dhd);
1635         rxlen = bus->rxlen;
1636         memcpy(msg, bus->rxctl, min(msglen, rxlen));
1637         bus->rxlen = 0;
1638         dhd_os_sdunlock(bus->dhd);
1639
1640         if (rxlen) {
1641                 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1642                          __func__, rxlen, msglen));
1643         } else if (timeleft == 0) {
1644                 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1645 #ifdef DHD_DEBUG
1646                 dhd_os_sdlock(bus->dhd);
1647                 dhdsdio_checkdied(bus, NULL, 0);
1648                 dhd_os_sdunlock(bus->dhd);
1649 #endif                          /* DHD_DEBUG */
1650         } else if (pending == true) {
1651                 DHD_CTL(("%s: cancelled\n", __func__));
1652                 return -ERESTARTSYS;
1653         } else {
1654                 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1655 #ifdef DHD_DEBUG
1656                 dhd_os_sdlock(bus->dhd);
1657                 dhdsdio_checkdied(bus, NULL, 0);
1658                 dhd_os_sdunlock(bus->dhd);
1659 #endif                          /* DHD_DEBUG */
1660         }
1661
1662         if (rxlen)
1663                 bus->dhd->rx_ctlpkts++;
1664         else
1665                 bus->dhd->rx_ctlerrs++;
1666
1667         return rxlen ? (int)rxlen : -ETIMEDOUT;
1668 }
1669
1670 /* IOVar table */
1671 enum {
1672         IOV_INTR = 1,
1673         IOV_POLLRATE,
1674         IOV_SDREG,
1675         IOV_SBREG,
1676         IOV_SDCIS,
1677         IOV_MEMBYTES,
1678         IOV_MEMSIZE,
1679 #ifdef DHD_DEBUG
1680         IOV_CHECKDIED,
1681 #endif
1682         IOV_DOWNLOAD,
1683         IOV_FORCEEVEN,
1684         IOV_SDIOD_DRIVE,
1685         IOV_READAHEAD,
1686         IOV_SDRXCHAIN,
1687         IOV_ALIGNCTL,
1688         IOV_SDALIGN,
1689         IOV_DEVRESET,
1690         IOV_CPU,
1691 #ifdef SDTEST
1692         IOV_PKTGEN,
1693         IOV_EXTLOOP,
1694 #endif                          /* SDTEST */
1695         IOV_SPROM,
1696         IOV_TXBOUND,
1697         IOV_RXBOUND,
1698         IOV_TXMINMAX,
1699         IOV_IDLETIME,
1700         IOV_IDLECLOCK,
1701         IOV_SD1IDLE,
1702         IOV_SLEEP,
1703         IOV_VARS
1704 };
1705
1706 const bcm_iovar_t dhdsdio_iovars[] = {
1707         {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1708         {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1709         {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1710         {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1711         {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1712         {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1713         {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1714         {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1715         {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1716         {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1717         {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1718         {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1719         {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1720         {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1721         {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1722         {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1723 #ifdef DHD_DEBUG
1724         {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1725         ,
1726         {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1727         ,
1728         {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1729         ,
1730         {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1731         ,
1732         {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1733         ,
1734         {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1735         ,
1736         {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1737         ,
1738         {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1739         ,
1740 #ifdef DHD_DEBUG
1741         {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1742         ,
1743 #endif                          /* DHD_DEBUG  */
1744 #endif                          /* DHD_DEBUG */
1745 #ifdef SDTEST
1746         {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1747         ,
1748         {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1749         ,
1750 #endif                          /* SDTEST */
1751
1752         {NULL, 0, 0, 0, 0}
1753 };
1754
1755 static void
1756 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1757 {
1758         uint q1, q2;
1759
1760         if (!div) {
1761                 bcm_bprintf(strbuf, "%s N/A", desc);
1762         } else {
1763                 q1 = num / div;
1764                 q2 = (100 * (num - (q1 * div))) / div;
1765                 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1766         }
1767 }
1768
1769 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1770 {
1771         dhd_bus_t *bus = dhdp->bus;
1772
1773         bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1774         bcm_bprintf(strbuf,
1775                     "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1776                     bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1777         bcm_bprintf(strbuf,
1778                     "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1779                     bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1780                     bus->rxskip, bus->rxlen, bus->rx_seq);
1781         bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1782                     bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1783         bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1784                     bus->pollrate, bus->pollcnt, bus->regfails);
1785
1786         bcm_bprintf(strbuf, "\nAdditional counters:\n");
1787         bcm_bprintf(strbuf,
1788                     "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1789                     bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1790                     bus->rxc_errors);
1791         bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1792                     bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1793         bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1794                     bus->fc_xoff, bus->fc_xon);
1795         bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1796                     bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1797         bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1798                     (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1799                     bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1800         {
1801                 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1802                              (bus->f2rxhdrs + bus->f2rxdata));
1803                 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1804                              bus->f1regdata);
1805                 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1806                              (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1807                 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1808                              bus->intrcount);
1809                 bcm_bprintf(strbuf, "\n");
1810
1811                 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1812                              bus->dhd->rx_packets);
1813                 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1814                              bus->rxglomframes);
1815                 bcm_bprintf(strbuf, "\n");
1816
1817                 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1818                              bus->f2txdata);
1819                 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1820                              bus->f1regdata);
1821                 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1822                              (bus->f2txdata + bus->f1regdata));
1823                 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1824                              bus->intrcount);
1825                 bcm_bprintf(strbuf, "\n");
1826
1827                 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1828                              (bus->dhd->tx_packets + bus->dhd->rx_packets),
1829                              (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1830                 dhd_dump_pct(strbuf, ", pkts/f1sd",
1831                              (bus->dhd->tx_packets + bus->dhd->rx_packets),
1832                              bus->f1regdata);
1833                 dhd_dump_pct(strbuf, ", pkts/sd",
1834                              (bus->dhd->tx_packets + bus->dhd->rx_packets),
1835                              (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1836                               bus->f1regdata));
1837                 dhd_dump_pct(strbuf, ", pkts/int",
1838                              (bus->dhd->tx_packets + bus->dhd->rx_packets),
1839                              bus->intrcount);
1840                 bcm_bprintf(strbuf, "\n\n");
1841         }
1842
1843 #ifdef SDTEST
1844         if (bus->pktgen_count) {
1845                 bcm_bprintf(strbuf, "pktgen config and count:\n");
1846                 bcm_bprintf(strbuf,
1847                             "freq %d count %d print %d total %d min %d len %d\n",
1848                             bus->pktgen_freq, bus->pktgen_count,
1849                             bus->pktgen_print, bus->pktgen_total,
1850                             bus->pktgen_minlen, bus->pktgen_maxlen);
1851                 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1852                             bus->pktgen_sent, bus->pktgen_rcvd,
1853                             bus->pktgen_fail);
1854         }
1855 #endif                          /* SDTEST */
1856 #ifdef DHD_DEBUG
1857         bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1858                     bus->dpc_sched,
1859                     (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1860         bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1861                     bus->roundup);
1862 #endif                          /* DHD_DEBUG */
1863         bcm_bprintf(strbuf,
1864                     "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1865                     bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1866                     bus->sleeping);
1867 }
1868
1869 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1870 {
1871         dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1872
1873         bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1874         bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1875         bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1876         bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1877         bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1878         bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1879 }
1880
1881 #ifdef SDTEST
1882 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1883 {
1884         dhd_pktgen_t pktgen;
1885
1886         pktgen.version = DHD_PKTGEN_VERSION;
1887         pktgen.freq = bus->pktgen_freq;
1888         pktgen.count = bus->pktgen_count;
1889         pktgen.print = bus->pktgen_print;
1890         pktgen.total = bus->pktgen_total;
1891         pktgen.minlen = bus->pktgen_minlen;
1892         pktgen.maxlen = bus->pktgen_maxlen;
1893         pktgen.numsent = bus->pktgen_sent;
1894         pktgen.numrcvd = bus->pktgen_rcvd;
1895         pktgen.numfail = bus->pktgen_fail;
1896         pktgen.mode = bus->pktgen_mode;
1897         pktgen.stop = bus->pktgen_stop;
1898
1899         memcpy(arg, &pktgen, sizeof(pktgen));
1900
1901         return 0;
1902 }
1903
1904 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1905 {
1906         dhd_pktgen_t pktgen;
1907         uint oldcnt, oldmode;
1908
1909         memcpy(&pktgen, arg, sizeof(pktgen));
1910         if (pktgen.version != DHD_PKTGEN_VERSION)
1911                 return -EINVAL;
1912
1913         oldcnt = bus->pktgen_count;
1914         oldmode = bus->pktgen_mode;
1915
1916         bus->pktgen_freq = pktgen.freq;
1917         bus->pktgen_count = pktgen.count;
1918         bus->pktgen_print = pktgen.print;
1919         bus->pktgen_total = pktgen.total;
1920         bus->pktgen_minlen = pktgen.minlen;
1921         bus->pktgen_maxlen = pktgen.maxlen;
1922         bus->pktgen_mode = pktgen.mode;
1923         bus->pktgen_stop = pktgen.stop;
1924
1925         bus->pktgen_tick = bus->pktgen_ptick = 0;
1926         bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1927         bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1928
1929         /* Clear counts for a new pktgen (mode change, or was stopped) */
1930         if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1931                 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1932
1933         return 0;
1934 }
1935 #endif                          /* SDTEST */
1936
1937 static int
1938 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1939                  uint size)
1940 {
1941         int bcmerror = 0;
1942         u32 sdaddr;
1943         uint dsize;
1944
1945         /* Determine initial transfer parameters */
1946         sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1947         if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1948                 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1949         else
1950                 dsize = size;
1951
1952         /* Set the backplane window to include the start address */
1953         bcmerror = dhdsdio_set_siaddr_window(bus, address);
1954         if (bcmerror) {
1955                 DHD_ERROR(("%s: window change failed\n", __func__));
1956                 goto xfer_done;
1957         }
1958
1959         /* Do the transfer(s) */
1960         while (size) {
1961                 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1962                           __func__, (write ? "write" : "read"), dsize,
1963                           sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1964                 bcmerror =
1965                      bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1966                 if (bcmerror) {
1967                         DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1968                         break;
1969                 }
1970
1971                 /* Adjust for next transfer (if any) */
1972                 size -= dsize;
1973                 if (size) {
1974                         data += dsize;
1975                         address += dsize;
1976                         bcmerror = dhdsdio_set_siaddr_window(bus, address);
1977                         if (bcmerror) {
1978                                 DHD_ERROR(("%s: window change failed\n",
1979                                            __func__));
1980                                 break;
1981                         }
1982                         sdaddr = 0;
1983                         dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1984                 }
1985         }
1986
1987 xfer_done:
1988         /* Return the window to backplane enumeration space for core access */
1989         if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1990                 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1991                            __func__, bcmsdh_cur_sbwad(bus->sdh)));
1992         }
1993
1994         return bcmerror;
1995 }
1996
1997 #ifdef DHD_DEBUG
1998 static int dhdsdio_readshared(dhd_bus_t *bus, struct sdpcm_shared *sh)
1999 {
2000         u32 addr;
2001         int rv;
2002
2003         /* Read last word in memory to determine address of
2004                          sdpcm_shared structure */
2005         rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
2006         if (rv < 0)
2007                 return rv;
2008
2009         addr = le32_to_cpu(addr);
2010
2011         DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
2012
2013         /*
2014          * Check if addr is valid.
2015          * NVRAM length at the end of memory should have been overwritten.
2016          */
2017         if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2018                 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
2019                            __func__, addr));
2020                 return -EBADE;
2021         }
2022
2023         /* Read rte_shared structure */
2024         rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
2025                               sizeof(struct sdpcm_shared));
2026         if (rv < 0)
2027                 return rv;
2028
2029         /* Endianness */
2030         sh->flags = le32_to_cpu(sh->flags);
2031         sh->trap_addr = le32_to_cpu(sh->trap_addr);
2032         sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2033         sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2034         sh->assert_line = le32_to_cpu(sh->assert_line);
2035         sh->console_addr = le32_to_cpu(sh->console_addr);
2036         sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2037
2038         if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2039                 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
2040                            "is different than sdpcm_shared version %d in dongle\n",
2041                            __func__, SDPCM_SHARED_VERSION,
2042                            sh->flags & SDPCM_SHARED_VERSION_MASK));
2043                 return -EBADE;
2044         }
2045
2046         return 0;
2047 }
2048
2049 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
2050 {
2051         int bcmerror = 0;
2052         uint msize = 512;
2053         char *mbuffer = NULL;
2054         uint maxstrlen = 256;
2055         char *str = NULL;
2056         trap_t tr;
2057         struct sdpcm_shared sdpcm_shared;
2058         struct bcmstrbuf strbuf;
2059
2060         DHD_TRACE(("%s: Enter\n", __func__));
2061
2062         if (data == NULL) {
2063                 /*
2064                  * Called after a rx ctrl timeout. "data" is NULL.
2065                  * allocate memory to trace the trap or assert.
2066                  */
2067                 size = msize;
2068                 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2069                 if (mbuffer == NULL) {
2070                         DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
2071                                    msize));
2072                         bcmerror = -ENOMEM;
2073                         goto done;
2074                 }
2075         }
2076
2077         str = kmalloc(maxstrlen, GFP_ATOMIC);
2078         if (str == NULL) {
2079                 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
2080                 bcmerror = -ENOMEM;
2081                 goto done;
2082         }
2083
2084         bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
2085         if (bcmerror < 0)
2086                 goto done;
2087
2088         bcm_binit(&strbuf, data, size);
2089
2090         bcm_bprintf(&strbuf,
2091                     "msgtrace address : 0x%08X\nconsole address  : 0x%08X\n",
2092                     sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2093
2094         if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2095                 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2096                  * (Avoids conflict with real asserts for programmatic
2097                  * parsing of output.)
2098                  */
2099                 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
2100         }
2101
2102         if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2103             0) {
2104                 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2105                  * (Avoids conflict with real asserts for programmatic
2106                  * parsing of output.)
2107                  */
2108                 bcm_bprintf(&strbuf, "No trap%s in dongle",
2109                             (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2110                             ? "/assrt" : "");
2111         } else {
2112                 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2113                         /* Download assert */
2114                         bcm_bprintf(&strbuf, "Dongle assert");
2115                         if (sdpcm_shared.assert_exp_addr != 0) {
2116                                 str[0] = '\0';
2117                                 bcmerror = dhdsdio_membytes(bus, false,
2118                                                 sdpcm_shared.assert_exp_addr,
2119                                                 (u8 *) str, maxstrlen);
2120                                 if (bcmerror < 0)
2121                                         goto done;
2122
2123                                 str[maxstrlen - 1] = '\0';
2124                                 bcm_bprintf(&strbuf, " expr \"%s\"", str);
2125                         }
2126
2127                         if (sdpcm_shared.assert_file_addr != 0) {
2128                                 str[0] = '\0';
2129                                 bcmerror = dhdsdio_membytes(bus, false,
2130                                                 sdpcm_shared.assert_file_addr,
2131                                                 (u8 *) str, maxstrlen);
2132                                 if (bcmerror < 0)
2133                                         goto done;
2134
2135                                 str[maxstrlen - 1] = '\0';
2136                                 bcm_bprintf(&strbuf, " file \"%s\"", str);
2137                         }
2138
2139                         bcm_bprintf(&strbuf, " line %d ",
2140                                     sdpcm_shared.assert_line);
2141                 }
2142
2143                 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2144                         bcmerror = dhdsdio_membytes(bus, false,
2145                                         sdpcm_shared.trap_addr, (u8 *)&tr,
2146                                         sizeof(trap_t));
2147                         if (bcmerror < 0)
2148                                 goto done;
2149
2150                         bcm_bprintf(&strbuf,
2151                                     "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2152                                     "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2153                                     "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2154                                     tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2155                                     tr.r14, tr.pc, sdpcm_shared.trap_addr,
2156                                     tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2157                                     tr.r6, tr.r7);
2158                 }
2159         }
2160
2161         if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2162                 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2163
2164 #ifdef DHD_DEBUG
2165         if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2166                 /* Mem dump to a file on device */
2167                 dhdsdio_mem_dump(bus);
2168         }
2169 #endif                          /* DHD_DEBUG */
2170
2171 done:
2172         kfree(mbuffer);
2173         kfree(str);
2174
2175         return bcmerror;
2176 }
2177
2178 static int dhdsdio_mem_dump(dhd_bus_t *bus)
2179 {
2180         int ret = 0;
2181         int size;               /* Full mem size */
2182         int start = 0;          /* Start address */
2183         int read_size = 0;      /* Read size of each iteration */
2184         u8 *buf = NULL, *databuf = NULL;
2185
2186         /* Get full mem size */
2187         size = bus->ramsize;
2188         buf = kmalloc(size, GFP_ATOMIC);
2189         if (!buf) {
2190                 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2191                 return -1;
2192         }
2193
2194         /* Read mem content */
2195         printk(KERN_DEBUG "Dump dongle memory");
2196         databuf = buf;
2197         while (size) {
2198                 read_size = min(MEMBLOCK, size);
2199                 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
2200                 if (ret) {
2201                         DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2202                         kfree(buf);
2203                         return -1;
2204                 }
2205                 printk(".");
2206
2207                 /* Decrement size and increment start address */
2208                 size -= read_size;
2209                 start += read_size;
2210                 databuf += read_size;
2211         }
2212         printk(KERN_DEBUG "Done\n");
2213
2214         /* free buf before return !!! */
2215         if (write_to_file(bus->dhd, buf, bus->ramsize)) {
2216                 DHD_ERROR(("%s: Error writing to files\n", __func__));
2217                 return -1;
2218         }
2219
2220         /* buf free handled in write_to_file, not here */
2221         return 0;
2222 }
2223
2224 #define CONSOLE_LINE_MAX        192
2225
2226 static int dhdsdio_readconsole(dhd_bus_t *bus)
2227 {
2228         dhd_console_t *c = &bus->console;
2229         u8 line[CONSOLE_LINE_MAX], ch;
2230         u32 n, idx, addr;
2231         int rv;
2232
2233         /* Don't do anything until FWREADY updates console address */
2234         if (bus->console_addr == 0)
2235                 return 0;
2236
2237         /* Read console log struct */
2238         addr = bus->console_addr + offsetof(rte_cons_t, log);
2239         rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2240                                 sizeof(c->log));
2241         if (rv < 0)
2242                 return rv;
2243
2244         /* Allocate console buffer (one time only) */
2245         if (c->buf == NULL) {
2246                 c->bufsize = le32_to_cpu(c->log.buf_size);
2247                 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2248                 if (c->buf == NULL)
2249                         return -ENOMEM;
2250         }
2251
2252         idx = le32_to_cpu(c->log.idx);
2253
2254         /* Protect against corrupt value */
2255         if (idx > c->bufsize)
2256                 return -EBADE;
2257
2258         /* Skip reading the console buffer if the index pointer
2259          has not moved */
2260         if (idx == c->last)
2261                 return 0;
2262
2263         /* Read the console buffer */
2264         addr = le32_to_cpu(c->log.buf);
2265         rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2266         if (rv < 0)
2267                 return rv;
2268
2269         while (c->last != idx) {
2270                 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2271                         if (c->last == idx) {
2272                                 /* This would output a partial line.
2273                                  * Instead, back up
2274                                  * the buffer pointer and output this
2275                                  * line next time around.
2276                                  */
2277                                 if (c->last >= n)
2278                                         c->last -= n;
2279                                 else
2280                                         c->last = c->bufsize - n;
2281                                 goto break2;
2282                         }
2283                         ch = c->buf[c->last];
2284                         c->last = (c->last + 1) % c->bufsize;
2285                         if (ch == '\n')
2286                                 break;
2287                         line[n] = ch;
2288                 }
2289
2290                 if (n > 0) {
2291                         if (line[n - 1] == '\r')
2292                                 n--;
2293                         line[n] = 0;
2294                         printk(KERN_DEBUG "CONSOLE: %s\n", line);
2295                 }
2296         }
2297 break2:
2298
2299         return 0;
2300 }
2301 #endif                          /* DHD_DEBUG */
2302
2303 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2304 {
2305         int bcmerror = 0;
2306
2307         DHD_TRACE(("%s: Enter\n", __func__));
2308
2309         /* Basic sanity checks */
2310         if (bus->dhd->up) {
2311                 bcmerror = -EISCONN;
2312                 goto err;
2313         }
2314         if (!len) {
2315                 bcmerror = -EOVERFLOW;
2316                 goto err;
2317         }
2318
2319         /* Free the old ones and replace with passed variables */
2320         kfree(bus->vars);
2321
2322         bus->vars = kmalloc(len, GFP_ATOMIC);
2323         bus->varsz = bus->vars ? len : 0;
2324         if (bus->vars == NULL) {
2325                 bcmerror = -ENOMEM;
2326                 goto err;
2327         }
2328
2329         /* Copy the passed variables, which should include the
2330                  terminating double-null */
2331         memcpy(bus->vars, arg, bus->varsz);
2332 err:
2333         return bcmerror;
2334 }
2335
2336 static int
2337 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2338                 const char *name, void *params, int plen, void *arg, int len,
2339                 int val_size)
2340 {
2341         int bcmerror = 0;
2342         s32 int_val = 0;
2343         bool bool_val = 0;
2344
2345         DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2346                 "len %d val_size %d\n",
2347                 __func__, actionid, name, params, plen, arg, len, val_size));
2348
2349         bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2350         if (bcmerror != 0)
2351                 goto exit;
2352
2353         if (plen >= (int)sizeof(int_val))
2354                 memcpy(&int_val, params, sizeof(int_val));
2355
2356         bool_val = (int_val != 0) ? true : false;
2357
2358         /* Some ioctls use the bus */
2359         dhd_os_sdlock(bus->dhd);
2360
2361         /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2362         if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2363                                         actionid == IOV_GVAL(IOV_DEVRESET))) {
2364                 bcmerror = -EPERM;
2365                 goto exit;
2366         }
2367
2368         /* Handle sleep stuff before any clock mucking */
2369         if (vi->varid == IOV_SLEEP) {
2370                 if (IOV_ISSET(actionid)) {
2371                         bcmerror = dhdsdio_bussleep(bus, bool_val);
2372                 } else {
2373                         int_val = (s32) bus->sleeping;
2374                         memcpy(arg, &int_val, val_size);
2375                 }
2376                 goto exit;
2377         }
2378
2379         /* Request clock to allow SDIO accesses */
2380         if (!bus->dhd->dongle_reset) {
2381                 BUS_WAKE(bus);
2382                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2383         }
2384
2385         switch (actionid) {
2386         case IOV_GVAL(IOV_INTR):
2387                 int_val = (s32) bus->intr;
2388                 memcpy(arg, &int_val, val_size);
2389                 break;
2390
2391         case IOV_SVAL(IOV_INTR):
2392                 bus->intr = bool_val;
2393                 bus->intdis = false;
2394                 if (bus->dhd->up) {
2395                         if (bus->intr) {
2396                                 DHD_INTR(("%s: enable SDIO device interrupts\n",
2397                                           __func__));
2398                                 bcmsdh_intr_enable(bus->sdh);
2399                         } else {
2400                                 DHD_INTR(("%s: disable SDIO interrupts\n",
2401                                           __func__));
2402                                 bcmsdh_intr_disable(bus->sdh);
2403                         }
2404                 }
2405                 break;
2406
2407         case IOV_GVAL(IOV_POLLRATE):
2408                 int_val = (s32) bus->pollrate;
2409                 memcpy(arg, &int_val, val_size);
2410                 break;
2411
2412         case IOV_SVAL(IOV_POLLRATE):
2413                 bus->pollrate = (uint) int_val;
2414                 bus->poll = (bus->pollrate != 0);
2415                 break;
2416
2417         case IOV_GVAL(IOV_IDLETIME):
2418                 int_val = bus->idletime;
2419                 memcpy(arg, &int_val, val_size);
2420                 break;
2421
2422         case IOV_SVAL(IOV_IDLETIME):
2423                 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2424                         bcmerror = -EINVAL;
2425                 else
2426                         bus->idletime = int_val;
2427                 break;
2428
2429         case IOV_GVAL(IOV_IDLECLOCK):
2430                 int_val = (s32) bus->idleclock;
2431                 memcpy(arg, &int_val, val_size);
2432                 break;
2433
2434         case IOV_SVAL(IOV_IDLECLOCK):
2435                 bus->idleclock = int_val;
2436                 break;
2437
2438         case IOV_GVAL(IOV_SD1IDLE):
2439                 int_val = (s32) sd1idle;
2440                 memcpy(arg, &int_val, val_size);
2441                 break;
2442
2443         case IOV_SVAL(IOV_SD1IDLE):
2444                 sd1idle = bool_val;
2445                 break;
2446
2447         case IOV_SVAL(IOV_MEMBYTES):
2448         case IOV_GVAL(IOV_MEMBYTES):
2449                 {
2450                         u32 address;
2451                         uint size, dsize;
2452                         u8 *data;
2453
2454                         bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2455
2456                         ASSERT(plen >= 2 * sizeof(int));
2457
2458                         address = (u32) int_val;
2459                         memcpy(&int_val, (char *)params + sizeof(int_val),
2460                                sizeof(int_val));
2461                         size = (uint) int_val;
2462
2463                         /* Do some validation */
2464                         dsize = set ? plen - (2 * sizeof(int)) : len;
2465                         if (dsize < size) {
2466                                 DHD_ERROR(("%s: error on %s membytes, addr "
2467                                 "0x%08x size %d dsize %d\n",
2468                                 __func__, (set ? "set" : "get"),
2469                                 address, size, dsize));
2470                                 bcmerror = -EINVAL;
2471                                 break;
2472                         }
2473
2474                         DHD_INFO(("%s: Request to %s %d bytes at address "
2475                         "0x%08x\n",
2476                         __func__, (set ? "write" : "read"), size, address));
2477
2478                         /* If we know about SOCRAM, check for a fit */
2479                         if ((bus->orig_ramsize) &&
2480                             ((address > bus->orig_ramsize)
2481                              || (address + size > bus->orig_ramsize))) {
2482                                 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2483                                 "bytes at 0x%08x\n",
2484                                 __func__, bus->orig_ramsize, size, address));
2485                                 bcmerror = -EINVAL;
2486                                 break;
2487                         }
2488
2489                         /* Generate the actual data pointer */
2490                         data =
2491                             set ? (u8 *) params +
2492                             2 * sizeof(int) : (u8 *) arg;
2493
2494                         /* Call to do the transfer */
2495                         bcmerror =
2496                             dhdsdio_membytes(bus, set, address, data, size);
2497
2498                         break;
2499                 }
2500
2501         case IOV_GVAL(IOV_MEMSIZE):
2502                 int_val = (s32) bus->ramsize;
2503                 memcpy(arg, &int_val, val_size);
2504                 break;
2505
2506         case IOV_GVAL(IOV_SDIOD_DRIVE):
2507                 int_val = (s32) dhd_sdiod_drive_strength;
2508                 memcpy(arg, &int_val, val_size);
2509                 break;
2510
2511         case IOV_SVAL(IOV_SDIOD_DRIVE):
2512                 dhd_sdiod_drive_strength = int_val;
2513                 dhdsdio_sdiod_drive_strength_init(bus,
2514                                              dhd_sdiod_drive_strength);
2515                 break;
2516
2517         case IOV_SVAL(IOV_DOWNLOAD):
2518                 bcmerror = dhdsdio_download_state(bus, bool_val);
2519                 break;
2520
2521         case IOV_SVAL(IOV_VARS):
2522                 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2523                 break;
2524
2525         case IOV_GVAL(IOV_READAHEAD):
2526                 int_val = (s32) dhd_readahead;
2527                 memcpy(arg, &int_val, val_size);
2528                 break;
2529
2530         case IOV_SVAL(IOV_READAHEAD):
2531                 if (bool_val && !dhd_readahead)
2532                         bus->nextlen = 0;
2533                 dhd_readahead = bool_val;
2534                 break;
2535
2536         case IOV_GVAL(IOV_SDRXCHAIN):
2537                 int_val = (s32) bus->use_rxchain;
2538                 memcpy(arg, &int_val, val_size);
2539                 break;
2540
2541         case IOV_SVAL(IOV_SDRXCHAIN):
2542                 if (bool_val && !bus->sd_rxchain)
2543                         bcmerror = -ENOTSUPP;
2544                 else
2545                         bus->use_rxchain = bool_val;
2546                 break;
2547         case IOV_GVAL(IOV_ALIGNCTL):
2548                 int_val = (s32) dhd_alignctl;
2549                 memcpy(arg, &int_val, val_size);
2550                 break;
2551
2552         case IOV_SVAL(IOV_ALIGNCTL):
2553                 dhd_alignctl = bool_val;
2554                 break;
2555
2556         case IOV_GVAL(IOV_SDALIGN):
2557                 int_val = DHD_SDALIGN;
2558                 memcpy(arg, &int_val, val_size);
2559                 break;
2560
2561 #ifdef DHD_DEBUG
2562         case IOV_GVAL(IOV_VARS):
2563                 if (bus->varsz < (uint) len)
2564                         memcpy(arg, bus->vars, bus->varsz);
2565                 else
2566                         bcmerror = -EOVERFLOW;
2567                 break;
2568 #endif                          /* DHD_DEBUG */
2569
2570 #ifdef DHD_DEBUG
2571         case IOV_GVAL(IOV_SDREG):
2572                 {
2573                         sdreg_t *sd_ptr;
2574                         u32 addr, size;
2575
2576                         sd_ptr = (sdreg_t *) params;
2577
2578                         addr = (unsigned long)bus->regs + sd_ptr->offset;
2579                         size = sd_ptr->func;
2580                         int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2581                         if (bcmsdh_regfail(bus->sdh))
2582                                 bcmerror = -EIO;
2583                         memcpy(arg, &int_val, sizeof(s32));
2584                         break;
2585                 }
2586
2587         case IOV_SVAL(IOV_SDREG):
2588                 {
2589                         sdreg_t *sd_ptr;
2590                         u32 addr, size;
2591
2592                         sd_ptr = (sdreg_t *) params;
2593
2594                         addr = (unsigned long)bus->regs + sd_ptr->offset;
2595                         size = sd_ptr->func;
2596                         bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2597                         if (bcmsdh_regfail(bus->sdh))
2598                                 bcmerror = -EIO;
2599                         break;
2600                 }
2601
2602                 /* Same as above, but offset is not backplane
2603                  (not SDIO core) */
2604         case IOV_GVAL(IOV_SBREG):
2605                 {
2606                         sdreg_t sdreg;
2607                         u32 addr, size;
2608
2609                         memcpy(&sdreg, params, sizeof(sdreg));
2610
2611                         addr = SI_ENUM_BASE + sdreg.offset;
2612                         size = sdreg.func;
2613                         int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2614                         if (bcmsdh_regfail(bus->sdh))
2615                                 bcmerror = -EIO;
2616                         memcpy(arg, &int_val, sizeof(s32));
2617                         break;
2618                 }
2619
2620         case IOV_SVAL(IOV_SBREG):
2621                 {
2622                         sdreg_t sdreg;
2623                         u32 addr, size;
2624
2625                         memcpy(&sdreg, params, sizeof(sdreg));
2626
2627                         addr = SI_ENUM_BASE + sdreg.offset;
2628                         size = sdreg.func;
2629                         bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2630                         if (bcmsdh_regfail(bus->sdh))
2631                                 bcmerror = -EIO;
2632                         break;
2633                 }
2634
2635         case IOV_GVAL(IOV_SDCIS):
2636                 {
2637                         *(char *)arg = 0;
2638
2639                         strcat(arg, "\nFunc 0\n");
2640                         bcmsdh_cis_read(bus->sdh, 0x10,
2641                                         (u8 *) arg + strlen(arg),
2642                                         SBSDIO_CIS_SIZE_LIMIT);
2643                         strcat(arg, "\nFunc 1\n");
2644                         bcmsdh_cis_read(bus->sdh, 0x11,
2645                                         (u8 *) arg + strlen(arg),
2646                                         SBSDIO_CIS_SIZE_LIMIT);
2647                         strcat(arg, "\nFunc 2\n");
2648                         bcmsdh_cis_read(bus->sdh, 0x12,
2649                                         (u8 *) arg + strlen(arg),
2650                                         SBSDIO_CIS_SIZE_LIMIT);
2651                         break;
2652                 }
2653
2654         case IOV_GVAL(IOV_FORCEEVEN):
2655                 int_val = (s32) forcealign;
2656                 memcpy(arg, &int_val, val_size);
2657                 break;
2658
2659         case IOV_SVAL(IOV_FORCEEVEN):
2660                 forcealign = bool_val;
2661                 break;
2662
2663         case IOV_GVAL(IOV_TXBOUND):
2664                 int_val = (s32) dhd_txbound;
2665                 memcpy(arg, &int_val, val_size);
2666                 break;
2667
2668         case IOV_SVAL(IOV_TXBOUND):
2669                 dhd_txbound = (uint) int_val;
2670                 break;
2671
2672         case IOV_GVAL(IOV_RXBOUND):
2673                 int_val = (s32) dhd_rxbound;
2674                 memcpy(arg, &int_val, val_size);
2675                 break;
2676
2677         case IOV_SVAL(IOV_RXBOUND):
2678                 dhd_rxbound = (uint) int_val;
2679                 break;
2680
2681         case IOV_GVAL(IOV_TXMINMAX):
2682                 int_val = (s32) dhd_txminmax;
2683                 memcpy(arg, &int_val, val_size);
2684                 break;
2685
2686         case IOV_SVAL(IOV_TXMINMAX):
2687                 dhd_txminmax = (uint) int_val;
2688                 break;
2689 #endif                          /* DHD_DEBUG */
2690
2691 #ifdef SDTEST
2692         case IOV_GVAL(IOV_EXTLOOP):
2693                 int_val = (s32) bus->ext_loop;
2694                 memcpy(arg, &int_val, val_size);
2695                 break;
2696
2697         case IOV_SVAL(IOV_EXTLOOP):
2698                 bus->ext_loop = bool_val;
2699                 break;
2700
2701         case IOV_GVAL(IOV_PKTGEN):
2702                 bcmerror = dhdsdio_pktgen_get(bus, arg);
2703                 break;
2704
2705         case IOV_SVAL(IOV_PKTGEN):
2706                 bcmerror = dhdsdio_pktgen_set(bus, arg);
2707                 break;
2708 #endif                          /* SDTEST */
2709
2710         case IOV_SVAL(IOV_DEVRESET):
2711                 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2712                         "busstate=%d\n",
2713                         __func__, bool_val, bus->dhd->dongle_reset,
2714                         bus->dhd->busstate));
2715
2716                 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2717
2718                 break;
2719
2720         case IOV_GVAL(IOV_DEVRESET):
2721                 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2722
2723                 /* Get its status */
2724                 int_val = (bool) bus->dhd->dongle_reset;
2725                 memcpy(arg, &int_val, val_size);
2726
2727                 break;
2728
2729         default:
2730                 bcmerror = -ENOTSUPP;
2731                 break;
2732         }
2733
2734 exit:
2735         if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2736                 bus->activity = false;
2737                 dhdsdio_clkctl(bus, CLK_NONE, true);
2738         }
2739
2740         dhd_os_sdunlock(bus->dhd);
2741
2742         if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2743                 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2744
2745         return bcmerror;
2746 }
2747
2748 static int dhdsdio_write_vars(dhd_bus_t *bus)
2749 {
2750         int bcmerror = 0;
2751         u32 varsize;
2752         u32 varaddr;
2753         u8 *vbuffer;
2754         u32 varsizew;
2755 #ifdef DHD_DEBUG
2756         char *nvram_ularray;
2757 #endif                          /* DHD_DEBUG */
2758
2759         /* Even if there are no vars are to be written, we still
2760                  need to set the ramsize. */
2761         varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2762         varaddr = (bus->ramsize - 4) - varsize;
2763
2764         if (bus->vars) {
2765                 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2766                 if (!vbuffer)
2767                         return -ENOMEM;
2768
2769                 memcpy(vbuffer, bus->vars, bus->varsz);
2770
2771                 /* Write the vars list */
2772                 bcmerror =
2773                     dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2774 #ifdef DHD_DEBUG
2775                 /* Verify NVRAM bytes */
2776                 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2777                 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2778                 if (!nvram_ularray)
2779                         return -ENOMEM;
2780
2781                 /* Upload image to verify downloaded contents. */
2782                 memset(nvram_ularray, 0xaa, varsize);
2783
2784                 /* Read the vars list to temp buffer for comparison */
2785                 bcmerror =
2786                     dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2787                                      varsize);
2788                 if (bcmerror) {
2789                         DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2790                         "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2791                 }
2792                 /* Compare the org NVRAM with the one read from RAM */
2793                 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2794                         DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2795                                    __func__));
2796                 } else
2797                         DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2798                                 __func__));
2799
2800                 kfree(nvram_ularray);
2801 #endif                          /* DHD_DEBUG */
2802
2803                 kfree(vbuffer);
2804         }
2805
2806         /* adjust to the user specified RAM */
2807         DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2808                   bus->orig_ramsize, bus->ramsize));
2809         DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2810         varsize = ((bus->orig_ramsize - 4) - varaddr);
2811
2812         /*
2813          * Determine the length token:
2814          * Varsize, converted to words, in lower 16-bits, checksum
2815          * in upper 16-bits.
2816          */
2817         if (bcmerror) {
2818                 varsizew = 0;
2819         } else {
2820                 varsizew = varsize / 4;
2821                 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2822                 varsizew = cpu_to_le32(varsizew);
2823         }
2824
2825         DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2826                   varsizew));
2827
2828         /* Write the length token to the last word */
2829         bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2830                                     (u8 *)&varsizew, 4);
2831
2832         return bcmerror;
2833 }
2834
2835 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2836 {
2837         uint retries;
2838         u32 regdata;
2839         int bcmerror = 0;
2840
2841         /* To enter download state, disable ARM and reset SOCRAM.
2842          * To exit download state, simply reset ARM (default is RAM boot).
2843          */
2844         if (enter) {
2845                 bus->alp_only = true;
2846
2847                 dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2848
2849                 dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2850
2851                 /* Clear the top bit of memory */
2852                 if (bus->ramsize) {
2853                         u32 zeros = 0;
2854                         dhdsdio_membytes(bus, true, bus->ramsize - 4,
2855                                          (u8 *)&zeros, 4);
2856                 }
2857         } else {
2858                 regdata = bcmsdh_reg_read(bus->sdh,
2859                         CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2860                 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2861                         (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2862                 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2863                         DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2864                                    __func__));
2865                         bcmerror = -EBADE;
2866                         goto fail;
2867                 }
2868
2869                 bcmerror = dhdsdio_write_vars(bus);
2870                 if (bcmerror) {
2871                         DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2872                         bcmerror = 0;
2873                 }
2874
2875                 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2876
2877                 dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2878
2879                 /* Allow HT Clock now that the ARM is running. */
2880                 bus->alp_only = false;
2881
2882                 bus->dhd->busstate = DHD_BUS_LOAD;
2883         }
2884 fail:
2885         return bcmerror;
2886 }
2887
2888 int
2889 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2890                  void *params, int plen, void *arg, int len, bool set)
2891 {
2892         dhd_bus_t *bus = dhdp->bus;
2893         const bcm_iovar_t *vi = NULL;
2894         int bcmerror = 0;
2895         int val_size;
2896         u32 actionid;
2897
2898         DHD_TRACE(("%s: Enter\n", __func__));
2899
2900         ASSERT(name);
2901         ASSERT(len >= 0);
2902
2903         /* Get MUST have return space */
2904         ASSERT(set || (arg && len));
2905
2906         /* Set does NOT take qualifiers */
2907         ASSERT(!set || (!params && !plen));
2908
2909         /* Look up var locally; if not found pass to host driver */
2910         vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2911         if (vi == NULL) {
2912                 dhd_os_sdlock(bus->dhd);
2913
2914                 BUS_WAKE(bus);
2915
2916                 /* Turn on clock in case SD command needs backplane */
2917                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2918
2919                 bcmerror =
2920                     bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2921                                     set);
2922
2923                 /* Similar check for blocksize change */
2924                 if (set && strcmp(name, "sd_blocksize") == 0) {
2925                         s32 fnum = 2;
2926                         if (bcmsdh_iovar_op
2927                             (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2928                              &bus->blocksize, sizeof(s32),
2929                              false) != 0) {
2930                                 bus->blocksize = 0;
2931                                 DHD_ERROR(("%s: fail on %s get\n", __func__,
2932                                            "sd_blocksize"));
2933                         } else {
2934                                 DHD_INFO(("%s: noted %s update, value now %d\n",
2935                                           __func__, "sd_blocksize",
2936                                           bus->blocksize));
2937                         }
2938                 }
2939                 bus->roundup = min(max_roundup, bus->blocksize);
2940
2941                 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2942                         bus->activity = false;
2943                         dhdsdio_clkctl(bus, CLK_NONE, true);
2944                 }
2945
2946                 dhd_os_sdunlock(bus->dhd);
2947                 goto exit;
2948         }
2949
2950         DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2951                  name, (set ? "set" : "get"), len, plen));
2952
2953         /* set up 'params' pointer in case this is a set command so that
2954          * the convenience int and bool code can be common to set and get
2955          */
2956         if (params == NULL) {
2957                 params = arg;
2958                 plen = len;
2959         }
2960
2961         if (vi->type == IOVT_VOID)
2962                 val_size = 0;
2963         else if (vi->type == IOVT_BUFFER)
2964                 val_size = len;
2965         else
2966                 /* all other types are integer sized */
2967                 val_size = sizeof(int);
2968
2969         actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2970         bcmerror =
2971             dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2972                             val_size);
2973
2974 exit:
2975         return bcmerror;
2976 }
2977
2978 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2979 {
2980         u32 local_hostintmask;
2981         u8 saveclk;
2982         uint retries;
2983         int err;
2984
2985         DHD_TRACE(("%s: Enter\n", __func__));
2986
2987         if (enforce_mutex)
2988                 dhd_os_sdlock(bus->dhd);
2989
2990         BUS_WAKE(bus);
2991
2992         /* Enable clock for device interrupts */
2993         dhdsdio_clkctl(bus, CLK_AVAIL, false);
2994
2995         /* Disable and clear interrupts at the chip level also */
2996         W_SDREG(0, &bus->regs->hostintmask, retries);
2997         local_hostintmask = bus->hostintmask;
2998         bus->hostintmask = 0;
2999
3000         /* Change our idea of bus state */
3001         bus->dhd->busstate = DHD_BUS_DOWN;
3002
3003         /* Force clocks on backplane to be sure F2 interrupt propagates */
3004         saveclk =
3005             bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3006                             &err);
3007         if (!err) {
3008                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3009                                  (saveclk | SBSDIO_FORCE_HT), &err);
3010         }
3011         if (err) {
3012                 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3013                            __func__, err));
3014         }
3015
3016         /* Turn off the bus (F2), free any pending packets */
3017         DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3018         bcmsdh_intr_disable(bus->sdh);
3019         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3020                          SDIO_FUNC_ENABLE_1, NULL);
3021
3022         /* Clear any pending interrupts now that F2 is disabled */
3023         W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
3024
3025         /* Turn off the backplane clock (only) */
3026         dhdsdio_clkctl(bus, CLK_SDONLY, false);
3027
3028         /* Clear the data packet queues */
3029         bcm_pktq_flush(&bus->txq, true, NULL, NULL);
3030
3031         /* Clear any held glomming stuff */
3032         if (bus->glomd)
3033                 bcm_pkt_buf_free_skb(bus->glomd);
3034
3035         if (bus->glom)
3036                 bcm_pkt_buf_free_skb(bus->glom);
3037
3038         bus->glom = bus->glomd = NULL;
3039
3040         /* Clear rx control and wake any waiters */
3041         bus->rxlen = 0;
3042         dhd_os_ioctl_resp_wake(bus->dhd);
3043
3044         /* Reset some F2 state stuff */
3045         bus->rxskip = false;
3046         bus->tx_seq = bus->rx_seq = 0;
3047
3048         if (enforce_mutex)
3049                 dhd_os_sdunlock(bus->dhd);
3050 }
3051
3052 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
3053 {
3054         dhd_bus_t *bus = dhdp->bus;
3055         dhd_timeout_t tmo;
3056         uint retries = 0;
3057         u8 ready, enable;
3058         int err, ret = 0;
3059         u8 saveclk;
3060
3061         DHD_TRACE(("%s: Enter\n", __func__));
3062
3063         ASSERT(bus->dhd);
3064         if (!bus->dhd)
3065                 return 0;
3066
3067         if (enforce_mutex)
3068                 dhd_os_sdlock(bus->dhd);
3069
3070         /* Make sure backplane clock is on, needed to generate F2 interrupt */
3071         dhdsdio_clkctl(bus, CLK_AVAIL, false);
3072         if (bus->clkstate != CLK_AVAIL)
3073                 goto exit;
3074
3075         /* Force clocks on backplane to be sure F2 interrupt propagates */
3076         saveclk =
3077             bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3078                             &err);
3079         if (!err) {
3080                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3081                                  (saveclk | SBSDIO_FORCE_HT), &err);
3082         }
3083         if (err) {
3084                 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3085                            __func__, err));
3086                 goto exit;
3087         }
3088
3089         /* Enable function 2 (frame transfers) */
3090         W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
3091                 &bus->regs->tosbmailboxdata, retries);
3092         enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3093
3094         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable, NULL);
3095
3096         /* Give the dongle some time to do its thing and set IOR2 */
3097         dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3098
3099         ready = 0;
3100         while (ready != enable && !dhd_timeout_expired(&tmo))
3101                 ready =
3102                     bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IORx,
3103                                     NULL);
3104
3105         DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3106                   __func__, enable, ready, tmo.elapsed));
3107
3108         /* If F2 successfully enabled, set core and enable interrupts */
3109         if (ready == enable) {
3110                 /* Set up the interrupt mask and enable interrupts */
3111                 bus->hostintmask = HOSTINTMASK;
3112                 W_SDREG(bus->hostintmask,
3113                         (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
3114                         hostintmask), retries);
3115
3116                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3117                                  (u8) watermark, &err);
3118
3119                 /* Set bus state according to enable result */
3120                 dhdp->busstate = DHD_BUS_DATA;
3121
3122                 /* bcmsdh_intr_unmask(bus->sdh); */
3123
3124                 bus->intdis = false;
3125                 if (bus->intr) {
3126                         DHD_INTR(("%s: enable SDIO device interrupts\n",
3127                                   __func__));
3128                         bcmsdh_intr_enable(bus->sdh);
3129                 } else {
3130                         DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3131                         bcmsdh_intr_disable(bus->sdh);
3132                 }
3133
3134         }
3135
3136         else {
3137                 /* Disable F2 again */
3138                 enable = SDIO_FUNC_ENABLE_1;
3139                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable,
3140                                  NULL);
3141         }
3142
3143         /* Restore previous clock setting */
3144         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3145                          saveclk, &err);
3146
3147         /* If we didn't come up, turn off backplane clock */
3148         if (dhdp->busstate != DHD_BUS_DATA)
3149                 dhdsdio_clkctl(bus, CLK_NONE, false);
3150
3151 exit:
3152         if (enforce_mutex)
3153                 dhd_os_sdunlock(bus->dhd);
3154
3155         return ret;
3156 }
3157
3158 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3159 {
3160         bcmsdh_info_t *sdh = bus->sdh;
3161         struct sdpcmd_regs *regs = bus->regs;
3162         uint retries = 0;
3163         u16 lastrbc;
3164         u8 hi, lo;
3165         int err;
3166
3167         DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3168                    (abort ? "abort command, " : ""),
3169                    (rtx ? ", send NAK" : "")));
3170
3171         if (abort)
3172                 bcmsdh_abort(sdh, SDIO_FUNC_2);
3173
3174         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3175                          &err);
3176         bus->f1regdata++;
3177
3178         /* Wait until the packet has been flushed (device/FIFO stable) */
3179         for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3180                 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3181                                      NULL);
3182                 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3183                                      NULL);
3184                 bus->f1regdata += 2;
3185
3186                 if ((hi == 0) && (lo == 0))
3187                         break;
3188
3189                 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3190                         DHD_ERROR(("%s: count growing: last 0x%04x now "
3191                                 "0x%04x\n",
3192                                 __func__, lastrbc, ((hi << 8) + lo)));
3193                 }
3194                 lastrbc = (hi << 8) + lo;
3195         }
3196
3197         if (!retries) {
3198                 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3199                            __func__, lastrbc));
3200         } else {
3201                 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3202                           (0xffff - retries)));
3203         }
3204
3205         if (rtx) {
3206                 bus->rxrtx++;
3207                 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3208                 bus->f1regdata++;
3209                 if (retries <= retry_limit)
3210                         bus->rxskip = true;
3211         }
3212
3213         /* Clear partial in any case */
3214         bus->nextlen = 0;
3215
3216         /* If we can't reach the device, signal failure */
3217         if (err || bcmsdh_regfail(sdh))
3218                 bus->dhd->busstate = DHD_BUS_DOWN;
3219 }
3220
3221 static void
3222 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3223 {
3224         bcmsdh_info_t *sdh = bus->sdh;
3225         uint rdlen, pad;
3226
3227         int sdret;
3228
3229         DHD_TRACE(("%s: Enter\n", __func__));
3230
3231         /* Control data already received in aligned rxctl */
3232         if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3233                 goto gotpkt;
3234
3235         ASSERT(bus->rxbuf);
3236         /* Set rxctl for frame (w/optional alignment) */
3237         bus->rxctl = bus->rxbuf;
3238         if (dhd_alignctl) {
3239                 bus->rxctl += firstread;
3240                 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3241                 if (pad)
3242                         bus->rxctl += (DHD_SDALIGN - pad);
3243                 bus->rxctl -= firstread;
3244         }
3245         ASSERT(bus->rxctl >= bus->rxbuf);
3246
3247         /* Copy the already-read portion over */
3248         memcpy(bus->rxctl, hdr, firstread);
3249         if (len <= firstread)
3250                 goto gotpkt;
3251
3252         /* Copy the full data pkt in gSPI case and process ioctl. */
3253         if (bus->bus == SPI_BUS) {
3254                 memcpy(bus->rxctl, hdr, len);
3255                 goto gotpkt;
3256         }
3257
3258         /* Raise rdlen to next SDIO block to avoid tail command */
3259         rdlen = len - firstread;
3260         if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3261                 pad = bus->blocksize - (rdlen % bus->blocksize);
3262                 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3263                     ((len + pad) < bus->dhd->maxctl))
3264                         rdlen += pad;
3265         } else if (rdlen % DHD_SDALIGN) {
3266                 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3267         }
3268
3269         /* Satisfy length-alignment requirements */
3270         if (forcealign && (rdlen & (ALIGNMENT - 1)))
3271                 rdlen = roundup(rdlen, ALIGNMENT);
3272
3273         /* Drop if the read is too big or it exceeds our maximum */
3274         if ((rdlen + firstread) > bus->dhd->maxctl) {
3275                 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3276                            __func__, rdlen, bus->dhd->maxctl));
3277                 bus->dhd->rx_errors++;
3278                 dhdsdio_rxfail(bus, false, false);
3279                 goto done;
3280         }
3281
3282         if ((len - doff) > bus->dhd->maxctl) {
3283                 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3284                         "%d-byte limit\n",
3285                         __func__, len, (len - doff), bus->dhd->maxctl));
3286                 bus->dhd->rx_errors++;
3287                 bus->rx_toolong++;
3288                 dhdsdio_rxfail(bus, false, false);
3289                 goto done;
3290         }
3291
3292         /* Read remainder of frame body into the rxctl buffer */
3293         sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3294                                 F2SYNC, (bus->rxctl + firstread), rdlen,
3295                                 NULL, NULL, NULL);
3296         bus->f2rxdata++;
3297         ASSERT(sdret != -BCME_PENDING);
3298
3299         /* Control frame failures need retransmission */
3300         if (sdret < 0) {
3301                 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3302                            __func__, rdlen, sdret));
3303                 bus->rxc_errors++;      /* dhd.rx_ctlerrs is higher level */
3304                 dhdsdio_rxfail(bus, true, true);
3305                 goto done;
3306         }
3307
3308 gotpkt:
3309
3310 #ifdef DHD_DEBUG
3311         if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3312                 printk(KERN_DEBUG "RxCtrl:\n");
3313                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3314         }
3315 #endif
3316
3317         /* Point to valid data and indicate its length */
3318         bus->rxctl += doff;
3319         bus->rxlen = len - doff;
3320
3321 done:
3322         /* Awake any waiters */
3323         dhd_os_ioctl_resp_wake(bus->dhd);
3324 }
3325
3326 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3327 {
3328         u16 dlen, totlen;
3329         u8 *dptr, num = 0;
3330
3331         u16 sublen, check;
3332         struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3333
3334         int errcode;
3335         u8 chan, seq, doff, sfdoff;
3336         u8 txmax;
3337
3338         int ifidx = 0;
3339         bool usechain = bus->use_rxchain;
3340
3341         /* If packets, issue read(s) and send up packet chain */
3342         /* Return sequence numbers consumed? */
3343
3344         DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3345                    bus->glom));
3346
3347         /* If there's a descriptor, generate the packet chain */
3348         if (bus->glomd) {
3349                 dhd_os_sdlock_rxq(bus->dhd);
3350
3351                 pfirst = plast = pnext = NULL;
3352                 dlen = (u16) (bus->glomd->len);
3353                 dptr = bus->glomd->data;
3354                 if (!dlen || (dlen & 1)) {
3355                         DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3356                         __func__, dlen));
3357                         dlen = 0;
3358                 }
3359
3360                 for (totlen = num = 0; dlen; num++) {
3361                         /* Get (and move past) next length */
3362                         sublen = get_unaligned_le16(dptr);
3363                         dlen -= sizeof(u16);
3364                         dptr += sizeof(u16);
3365                         if ((sublen < SDPCM_HDRLEN) ||
3366                             ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3367                                 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3368                                            __func__, num, sublen));
3369                                 pnext = NULL;
3370                                 break;
3371                         }
3372                         if (sublen % DHD_SDALIGN) {
3373                                 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3374                                 __func__, sublen, DHD_SDALIGN));
3375                                 usechain = false;
3376                         }
3377                         totlen += sublen;
3378
3379                         /* For last frame, adjust read len so total
3380                                  is a block multiple */
3381                         if (!dlen) {
3382                                 sublen +=
3383                                     (roundup(totlen, bus->blocksize) - totlen);
3384                                 totlen = roundup(totlen, bus->blocksize);
3385                         }
3386
3387                         /* Allocate/chain packet for next subframe */
3388                         pnext = bcm_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3389                         if (pnext == NULL) {
3390                                 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3391                                         "num %d len %d\n", __func__,
3392                                         num, sublen));
3393                                 break;
3394                         }
3395                         ASSERT(!(pnext->prev));
3396                         if (!pfirst) {
3397                                 ASSERT(!plast);
3398                                 pfirst = plast = pnext;
3399                         } else {
3400                                 ASSERT(plast);
3401                                 plast->next = pnext;
3402                                 plast = pnext;
3403                         }
3404
3405                         /* Adhere to start alignment requirements */
3406                         PKTALIGN(pnext, sublen, DHD_SDALIGN);
3407                 }
3408
3409                 /* If all allocations succeeded, save packet chain
3410                          in bus structure */
3411                 if (pnext) {
3412                         DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3413                                 "subframes\n", __func__, totlen, num));
3414                         if (DHD_GLOM_ON() && bus->nextlen) {
3415                                 if (totlen != bus->nextlen) {
3416                                         DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3417                                                 __func__, bus->nextlen,
3418                                                 totlen, rxseq));
3419                                 }
3420                         }
3421                         bus->glom = pfirst;
3422                         pfirst = pnext = NULL;
3423                 } else {
3424                         if (pfirst)
3425                                 bcm_pkt_buf_free_skb(pfirst);
3426                         bus->glom = NULL;
3427                         num = 0;
3428                 }
3429
3430                 /* Done with descriptor packet */
3431                 bcm_pkt_buf_free_skb(bus->glomd);
3432                 bus->glomd = NULL;
3433                 bus->nextlen = 0;
3434
3435                 dhd_os_sdunlock_rxq(bus->dhd);
3436         }
3437
3438         /* Ok -- either we just generated a packet chain,
3439                  or had one from before */
3440         if (bus->glom) {
3441                 if (DHD_GLOM_ON()) {
3442                         DHD_GLOM(("%s: try superframe read, packet chain:\n",
3443                                 __func__));
3444                         for (pnext = bus->glom; pnext; pnext = pnext->next) {
3445                                 DHD_GLOM(("    %p: %p len 0x%04x (%d)\n",
3446                                           pnext, (u8 *) (pnext->data),
3447                                           pnext->len, pnext->len));
3448                         }
3449                 }
3450
3451                 pfirst = bus->glom;
3452                 dlen = (u16) bcm_pkttotlen(pfirst);
3453
3454                 /* Do an SDIO read for the superframe.  Configurable iovar to
3455                  * read directly into the chained packet, or allocate a large
3456                  * packet and and copy into the chain.
3457                  */
3458                 if (usechain) {
3459                         errcode = bcmsdh_recv_buf(bus,
3460                                         bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3461                                         F2SYNC, (u8 *) pfirst->data, dlen,
3462                                         pfirst, NULL, NULL);
3463                 } else if (bus->dataptr) {
3464                         errcode = bcmsdh_recv_buf(bus,
3465                                         bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3466                                         F2SYNC, bus->dataptr, dlen,
3467                                         NULL, NULL, NULL);
3468                         sublen = (u16) bcm_pktfrombuf(pfirst, 0, dlen,
3469                                                 bus->dataptr);
3470                         if (sublen != dlen) {
3471                                 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3472                                         __func__, dlen, sublen));
3473                                 errcode = -1;
3474                         }
3475                         pnext = NULL;
3476                 } else {
3477                         DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3478                                 dlen));
3479                         errcode = -1;
3480                 }
3481                 bus->f2rxdata++;
3482                 ASSERT(errcode != -BCME_PENDING);
3483
3484                 /* On failure, kill the superframe, allow a couple retries */
3485                 if (errcode < 0) {
3486                         DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3487                                    __func__, dlen, errcode));
3488                         bus->dhd->rx_errors++;
3489
3490                         if (bus->glomerr++ < 3) {
3491                                 dhdsdio_rxfail(bus, true, true);
3492                         } else {
3493                                 bus->glomerr = 0;
3494                                 dhdsdio_rxfail(bus, true, false);
3495                                 dhd_os_sdlock_rxq(bus->dhd);
3496                                 bcm_pkt_buf_free_skb(bus->glom);
3497                                 dhd_os_sdunlock_rxq(bus->dhd);
3498                                 bus->rxglomfail++;
3499                                 bus->glom = NULL;
3500                         }
3501                         return 0;
3502                 }
3503 #ifdef DHD_DEBUG
3504                 if (DHD_GLOM_ON()) {
3505                         printk(KERN_DEBUG "SUPERFRAME:\n");
3506                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3507                                 pfirst->data, min_t(int, pfirst->len, 48));
3508                 }
3509 #endif
3510
3511                 /* Validate the superframe header */
3512                 dptr = (u8 *) (pfirst->data);
3513                 sublen = get_unaligned_le16(dptr);
3514                 check = get_unaligned_le16(dptr + sizeof(u16));
3515
3516                 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3517                 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3518                 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3519                 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3520                         DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3521                                 __func__, bus->nextlen, seq));
3522                         bus->nextlen = 0;
3523                 }
3524                 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3525                 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3526
3527                 errcode = 0;
3528                 if ((u16)~(sublen ^ check)) {
3529                         DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3530                                 "0x%04x/0x%04x\n", __func__, sublen, check));
3531                         errcode = -1;
3532                 } else if (roundup(sublen, bus->blocksize) != dlen) {
3533                         DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3534                                 "0x%04x, expect 0x%04x\n",
3535                                 __func__, sublen,
3536                                 roundup(sublen, bus->blocksize), dlen));
3537                         errcode = -1;
3538                 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3539                            SDPCM_GLOM_CHANNEL) {
3540                         DHD_ERROR(("%s (superframe): bad channel %d\n",
3541                                    __func__,
3542                                    SDPCM_PACKET_CHANNEL(&dptr
3543                                                         [SDPCM_FRAMETAG_LEN])));
3544                         errcode = -1;
3545                 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3546                         DHD_ERROR(("%s (superframe): got second descriptor?\n",
3547                                    __func__));
3548                         errcode = -1;
3549                 } else if ((doff < SDPCM_HDRLEN) ||
3550                            (doff > (pfirst->len - SDPCM_HDRLEN))) {
3551                         DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3552                                 "pkt %d min %d\n",
3553                                 __func__, doff, sublen,
3554                                 pfirst->len, SDPCM_HDRLEN));
3555                         errcode = -1;
3556                 }
3557
3558                 /* Check sequence number of superframe SW header */
3559                 if (rxseq != seq) {
3560                         DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3561                                   __func__, seq, rxseq));
3562                         bus->rx_badseq++;
3563                         rxseq = seq;
3564                 }
3565
3566                 /* Check window for sanity */
3567                 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3568                         DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3569                                 __func__, txmax, bus->tx_seq));
3570                         txmax = bus->tx_seq + 2;
3571                 }
3572                 bus->tx_max = txmax;
3573
3574                 /* Remove superframe header, remember offset */
3575                 skb_pull(pfirst, doff);
3576                 sfdoff = doff;
3577
3578                 /* Validate all the subframe headers */
3579                 for (num = 0, pnext = pfirst; pnext && !errcode;
3580                      num++, pnext = pnext->next) {
3581                         dptr = (u8 *) (pnext->data);
3582                         dlen = (u16) (pnext->len);
3583                         sublen = get_unaligned_le16(dptr);
3584                         check = get_unaligned_le16(dptr + sizeof(u16));
3585                         chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3586                         doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3587 #ifdef DHD_DEBUG
3588                         if (DHD_GLOM_ON()) {
3589                                 printk(KERN_DEBUG "subframe:\n");
3590                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3591                                                      dptr, 32);
3592                         }
3593 #endif
3594
3595                         if ((u16)~(sublen ^ check)) {
3596                                 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3597                                            "len/check 0x%04x/0x%04x\n",
3598                                            __func__, num, sublen, check));
3599                                 errcode = -1;
3600                         } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3601                                 DHD_ERROR(("%s (subframe %d): length mismatch: "
3602                                            "len 0x%04x, expect 0x%04x\n",
3603                                            __func__, num, sublen, dlen));
3604                                 errcode = -1;
3605                         } else if ((chan != SDPCM_DATA_CHANNEL) &&
3606                                    (chan != SDPCM_EVENT_CHANNEL)) {
3607                                 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3608                                            __func__, num, chan));
3609                                 errcode = -1;
3610                         } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3611                                 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3612                                         __func__, num, doff, sublen,
3613                                         SDPCM_HDRLEN));
3614                                 errcode = -1;
3615                         }
3616                 }
3617
3618                 if (errcode) {
3619                         /* Terminate frame on error, request
3620                                  a couple retries */
3621                         if (bus->glomerr++ < 3) {
3622                                 /* Restore superframe header space */
3623                                 skb_push(pfirst, sfdoff);
3624                                 dhdsdio_rxfail(bus, true, true);
3625                         } else {
3626                                 bus->glomerr = 0;
3627                                 dhdsdio_rxfail(bus, true, false);
3628                                 dhd_os_sdlock_rxq(bus->dhd);
3629                                 bcm_pkt_buf_free_skb(bus->glom);
3630                                 dhd_os_sdunlock_rxq(bus->dhd);
3631                                 bus->rxglomfail++;
3632                                 bus->glom = NULL;
3633                         }
3634                         bus->nextlen = 0;
3635                         return 0;
3636                 }
3637
3638                 /* Basic SD framing looks ok - process each packet (header) */
3639                 save_pfirst = pfirst;
3640                 bus->glom = NULL;
3641                 plast = NULL;
3642
3643                 dhd_os_sdlock_rxq(bus->dhd);
3644                 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3645                         pnext = pfirst->next;
3646                         pfirst->next = NULL;
3647
3648                         dptr = (u8 *) (pfirst->data);
3649                         sublen = get_unaligned_le16(dptr);
3650                         chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3651                         seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3652                         doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3653
3654                         DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3655                                 "chan %d seq %d\n",
3656                                 __func__, num, pfirst, pfirst->data,
3657                                 pfirst->len, sublen, chan, seq));
3658
3659                         ASSERT((chan == SDPCM_DATA_CHANNEL)
3660                                || (chan == SDPCM_EVENT_CHANNEL));
3661
3662                         if (rxseq != seq) {
3663                                 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3664                                           __func__, seq, rxseq));
3665                                 bus->rx_badseq++;
3666                                 rxseq = seq;
3667                         }
3668 #ifdef DHD_DEBUG
3669                         if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3670                                 printk(KERN_DEBUG "Rx Subframe Data:\n");
3671                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3672                                                      dptr, dlen);
3673                         }
3674 #endif
3675
3676                         __skb_trim(pfirst, sublen);
3677                         skb_pull(pfirst, doff);
3678
3679                         if (pfirst->len == 0) {
3680                                 bcm_pkt_buf_free_skb(pfirst);
3681                                 if (plast) {
3682                                         plast->next = pnext;
3683                                 } else {
3684                                         ASSERT(save_pfirst == pfirst);
3685                                         save_pfirst = pnext;
3686                                 }
3687                                 continue;
3688                         } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3689                                    0) {
3690                                 DHD_ERROR(("%s: rx protocol error\n",
3691                                            __func__));
3692                                 bus->dhd->rx_errors++;
3693                                 bcm_pkt_buf_free_skb(pfirst);
3694                                 if (plast) {
3695                                         plast->next = pnext;
3696                                 } else {
3697                                         ASSERT(save_pfirst == pfirst);
3698                                         save_pfirst = pnext;
3699                                 }
3700                                 continue;
3701                         }
3702
3703                         /* this packet will go up, link back into
3704                                  chain and count it */
3705                         pfirst->next = pnext;
3706                         plast = pfirst;
3707                         num++;
3708
3709 #ifdef DHD_DEBUG
3710                         if (DHD_GLOM_ON()) {
3711                                 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3712                                 "nxt/lnk %p/%p\n",
3713                                 __func__, num, pfirst, pfirst->data,
3714                                 pfirst->len, pfirst->next,
3715                                 pfirst->prev));
3716                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3717                                                 pfirst->data,
3718                                                 min_t(int, pfirst->len, 32));
3719                         }
3720 #endif                          /* DHD_DEBUG */
3721                 }
3722                 dhd_os_sdunlock_rxq(bus->dhd);
3723                 if (num) {
3724                         dhd_os_sdunlock(bus->dhd);
3725                         dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3726                         dhd_os_sdlock(bus->dhd);
3727                 }
3728
3729                 bus->rxglomframes++;
3730                 bus->rxglompkts += num;
3731         }
3732         return num;
3733 }
3734
3735 /* Return true if there may be more frames to read */
3736 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3737 {
3738         bcmsdh_info_t *sdh = bus->sdh;
3739
3740         u16 len, check; /* Extracted hardware header fields */
3741         u8 chan, seq, doff;     /* Extracted software header fields */
3742         u8 fcbits;              /* Extracted fcbits from software header */
3743
3744         struct sk_buff *pkt;            /* Packet for event or data frames */
3745         u16 pad;                /* Number of pad bytes to read */
3746         u16 rdlen;              /* Total number of bytes to read */
3747         u8 rxseq;               /* Next sequence number to expect */
3748         uint rxleft = 0;        /* Remaining number of frames allowed */
3749         int sdret;              /* Return code from bcmsdh calls */
3750         u8 txmax;               /* Maximum tx sequence offered */
3751         bool len_consistent;    /* Result of comparing readahead len and
3752                                          len from hw-hdr */
3753         u8 *rxbuf;
3754         int ifidx = 0;
3755         uint rxcount = 0;       /* Total frames read */
3756
3757 #if defined(DHD_DEBUG) || defined(SDTEST)
3758         bool sdtest = false;    /* To limit message spew from test mode */
3759 #endif
3760
3761         DHD_TRACE(("%s: Enter\n", __func__));
3762
3763         ASSERT(maxframes);
3764
3765 #ifdef SDTEST
3766         /* Allow pktgen to override maxframes */
3767         if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3768                 maxframes = bus->pktgen_count;
3769                 sdtest = true;
3770         }
3771 #endif
3772
3773         /* Not finished unless we encounter no more frames indication */
3774         *finished = false;
3775
3776         for (rxseq = bus->rx_seq, rxleft = maxframes;
3777              !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3778              rxseq++, rxleft--) {
3779
3780                 /* Handle glomming separately */
3781                 if (bus->glom || bus->glomd) {
3782                         u8 cnt;
3783                         DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3784                                   __func__, bus->glomd, bus->glom));
3785                         cnt = dhdsdio_rxglom(bus, rxseq);
3786                         DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3787                         rxseq += cnt - 1;
3788                         rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3789                         continue;
3790                 }
3791
3792                 /* Try doing single read if we can */
3793                 if (dhd_readahead && bus->nextlen) {
3794                         u16 nextlen = bus->nextlen;
3795                         bus->nextlen = 0;
3796
3797                         if (bus->bus == SPI_BUS) {
3798                                 rdlen = len = nextlen;
3799                         } else {
3800                                 rdlen = len = nextlen << 4;
3801
3802                                 /* Pad read to blocksize for efficiency */
3803                                 if (bus->roundup && bus->blocksize
3804                                     && (rdlen > bus->blocksize)) {
3805                                         pad =
3806                                             bus->blocksize -
3807                                             (rdlen % bus->blocksize);
3808                                         if ((pad <= bus->roundup)
3809                                             && (pad < bus->blocksize)
3810                                             && ((rdlen + pad + firstread) <
3811                                                 MAX_RX_DATASZ))
3812                                                 rdlen += pad;
3813                                 } else if (rdlen % DHD_SDALIGN) {
3814                                         rdlen +=
3815                                             DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3816                                 }
3817                         }
3818
3819                         /* We use bus->rxctl buffer in WinXP for initial
3820                          * control pkt receives.
3821                          * Later we use buffer-poll for data as well
3822                          * as control packets.
3823                          * This is required because dhd receives full
3824                          * frame in gSPI unlike SDIO.
3825                          * After the frame is received we have to
3826                          * distinguish whether it is data
3827                          * or non-data frame.
3828                          */
3829                         /* Allocate a packet buffer */
3830                         dhd_os_sdlock_rxq(bus->dhd);
3831                         pkt = bcm_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3832                         if (!pkt) {
3833                                 if (bus->bus == SPI_BUS) {
3834                                         bus->usebufpool = false;
3835                                         bus->rxctl = bus->rxbuf;
3836                                         if (dhd_alignctl) {
3837                                                 bus->rxctl += firstread;
3838                                                 pad = ((unsigned long)bus->rxctl %
3839                                                       DHD_SDALIGN);
3840                                                 if (pad)
3841                                                         bus->rxctl +=
3842                                                             (DHD_SDALIGN - pad);
3843                                                 bus->rxctl -= firstread;
3844                                         }
3845                                         ASSERT(bus->rxctl >= bus->rxbuf);
3846                                         rxbuf = bus->rxctl;
3847                                         /* Read the entire frame */
3848                                         sdret = bcmsdh_recv_buf(bus,
3849                                                     bcmsdh_cur_sbwad(sdh),
3850                                                     SDIO_FUNC_2, F2SYNC,
3851                                                     rxbuf, rdlen,
3852                                                     NULL, NULL, NULL);
3853                                         bus->f2rxdata++;
3854                                         ASSERT(sdret != -BCME_PENDING);
3855
3856                                         /* Control frame failures need
3857                                          retransmission */
3858                                         if (sdret < 0) {
3859                                                 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3860                                                         __func__,
3861                                                         rdlen, sdret));
3862                                                 /* dhd.rx_ctlerrs is higher */
3863                                                 bus->rxc_errors++;
3864                                                 dhd_os_sdunlock_rxq(bus->dhd);
3865                                                 dhdsdio_rxfail(bus, true,
3866                                                        (bus->bus ==
3867                                                         SPI_BUS) ? false
3868                                                        : true);
3869                                                 continue;
3870                                         }
3871                                 } else {
3872                                         /* Give up on data,
3873                                         request rtx of events */
3874                                         DHD_ERROR(("%s (nextlen): "
3875                                                    "bcm_pkt_buf_get_skb failed:"
3876                                                    " len %d rdlen %d expected"
3877                                                    " rxseq %d\n", __func__,
3878                                                    len, rdlen, rxseq));
3879                                         /* Just go try again w/normal
3880                                         header read */
3881                                         dhd_os_sdunlock_rxq(bus->dhd);
3882                                         continue;
3883                                 }
3884                         } else {
3885                                 if (bus->bus == SPI_BUS)
3886                                         bus->usebufpool = true;
3887
3888                                 ASSERT(!(pkt->prev));
3889                                 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3890                                 rxbuf = (u8 *) (pkt->data);
3891                                 /* Read the entire frame */
3892                                 sdret = bcmsdh_recv_buf(bus,
3893                                                 bcmsdh_cur_sbwad(sdh),
3894                                                 SDIO_FUNC_2, F2SYNC,
3895                                                 rxbuf, rdlen,
3896                                                 pkt, NULL, NULL);
3897                                 bus->f2rxdata++;
3898                                 ASSERT(sdret != -BCME_PENDING);
3899
3900                                 if (sdret < 0) {
3901                                         DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3902                                                 __func__, rdlen, sdret));
3903                                         bcm_pkt_buf_free_skb(pkt);
3904                                         bus->dhd->rx_errors++;
3905                                         dhd_os_sdunlock_rxq(bus->dhd);
3906                                         /* Force retry w/normal header read.
3907                                          * Don't attempt NAK for
3908                                          * gSPI
3909                                          */
3910                                         dhdsdio_rxfail(bus, true,
3911                                                        (bus->bus ==
3912                                                         SPI_BUS) ? false :
3913                                                        true);
3914                                         continue;
3915                                 }
3916                         }
3917                         dhd_os_sdunlock_rxq(bus->dhd);
3918
3919                         /* Now check the header */
3920                         memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3921
3922                         /* Extract hardware header fields */
3923                         len = get_unaligned_le16(bus->rxhdr);
3924                         check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3925
3926                         /* All zeros means readahead info was bad */
3927                         if (!(len | check)) {
3928                                 DHD_INFO(("%s (nextlen): read zeros in HW "
3929                                         "header???\n", __func__));
3930                                 dhdsdio_pktfree2(bus, pkt);
3931                                 continue;
3932                         }
3933
3934                         /* Validate check bytes */
3935                         if ((u16)~(len ^ check)) {
3936                                 DHD_ERROR(("%s (nextlen): HW hdr error:"
3937                                         " nextlen/len/check"
3938                                         " 0x%04x/0x%04x/0x%04x\n",
3939                                         __func__, nextlen, len, check));
3940                                 bus->rx_badhdr++;
3941                                 dhdsdio_rxfail(bus, false, false);
3942                                 dhdsdio_pktfree2(bus, pkt);
3943                                 continue;
3944                         }
3945
3946                         /* Validate frame length */
3947                         if (len < SDPCM_HDRLEN) {
3948                                 DHD_ERROR(("%s (nextlen): HW hdr length "
3949                                         "invalid: %d\n", __func__, len));
3950                                 dhdsdio_pktfree2(bus, pkt);
3951                                 continue;
3952                         }
3953
3954                         /* Check for consistency withreadahead info */
3955                         len_consistent = (nextlen != (roundup(len, 16) >> 4));
3956                         if (len_consistent) {
3957                                 /* Mismatch, force retry w/normal
3958                                         header (may be >4K) */
3959                                 DHD_ERROR(("%s (nextlen): mismatch, "
3960                                         "nextlen %d len %d rnd %d; "
3961                                         "expected rxseq %d\n",
3962                                         __func__, nextlen,
3963                                         len, roundup(len, 16), rxseq));
3964                                 dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
3965                                 dhdsdio_pktfree2(bus, pkt);
3966                                 continue;
3967                         }
3968
3969                         /* Extract software header fields */
3970                         chan = SDPCM_PACKET_CHANNEL(
3971                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3972                         seq = SDPCM_PACKET_SEQUENCE(
3973                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3974                         doff = SDPCM_DOFFSET_VALUE(
3975                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3976                         txmax = SDPCM_WINDOW_VALUE(
3977                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3978
3979                         bus->nextlen =
3980                             bus->rxhdr[SDPCM_FRAMETAG_LEN +
3981                                        SDPCM_NEXTLEN_OFFSET];
3982                         if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3983                                 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3984                                         __func__, bus->nextlen, seq));
3985                                 bus->nextlen = 0;
3986                         }
3987
3988                         bus->dhd->rx_readahead_cnt++;
3989
3990                         /* Handle Flow Control */
3991                         fcbits = SDPCM_FCMASK_VALUE(
3992                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3993
3994                         if (bus->flowcontrol != fcbits) {
3995                                 if (~bus->flowcontrol & fcbits)
3996                                         bus->fc_xoff++;
3997
3998                                 if (bus->flowcontrol & ~fcbits)
3999                                         bus->fc_xon++;
4000
4001                                 bus->fc_rcvd++;
4002                                 bus->flowcontrol = fcbits;
4003                         }
4004
4005                         /* Check and update sequence number */
4006                         if (rxseq != seq) {
4007                                 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
4008                                         "%d\n", __func__, seq, rxseq));
4009                                 bus->rx_badseq++;
4010                                 rxseq = seq;
4011                         }
4012
4013                         /* Check window for sanity */
4014                         if ((u8) (txmax - bus->tx_seq) > 0x40) {
4015                                 DHD_ERROR(("%s: got unlikely tx max %d with "
4016                                         "tx_seq %d\n",
4017                                         __func__, txmax, bus->tx_seq));
4018                                 txmax = bus->tx_seq + 2;
4019                         }
4020                         bus->tx_max = txmax;
4021
4022 #ifdef DHD_DEBUG
4023                         if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4024                                 printk(KERN_DEBUG "Rx Data:\n");
4025                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4026                                                      rxbuf, len);
4027                         } else if (DHD_HDRS_ON()) {
4028                                 printk(KERN_DEBUG "RxHdr:\n");
4029                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4030                                                      bus->rxhdr, SDPCM_HDRLEN);
4031                         }
4032 #endif
4033
4034                         if (chan == SDPCM_CONTROL_CHANNEL) {
4035                                 if (bus->bus == SPI_BUS) {
4036                                         dhdsdio_read_control(bus, rxbuf, len,
4037                                                              doff);
4038                                 } else {
4039                                         DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
4040                                                 __func__, seq));
4041                                         /* Force retry w/normal header read */
4042                                         bus->nextlen = 0;
4043                                         dhdsdio_rxfail(bus, false, true);
4044                                 }
4045                                 dhdsdio_pktfree2(bus, pkt);
4046                                 continue;
4047                         }
4048
4049                         if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4050                                 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
4051                                         len, chan));
4052                                 continue;
4053                         }
4054
4055                         /* Validate data offset */
4056                         if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4057                                 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4058                                         __func__, doff, len, SDPCM_HDRLEN));
4059                                 dhdsdio_rxfail(bus, false, false);
4060                                 dhdsdio_pktfree2(bus, pkt);
4061                                 continue;
4062                         }
4063
4064                         /* All done with this one -- now deliver the packet */
4065                         goto deliver;
4066                 }
4067                 /* gSPI frames should not be handled in fractions */
4068                 if (bus->bus == SPI_BUS)
4069                         break;
4070
4071                 /* Read frame header (hardware and software) */
4072                 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
4073                                 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
4074                                 NULL, NULL, NULL);
4075                 bus->f2rxhdrs++;
4076                 ASSERT(sdret != -BCME_PENDING);
4077
4078                 if (sdret < 0) {
4079                         DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
4080                                    sdret));
4081                         bus->rx_hdrfail++;
4082                         dhdsdio_rxfail(bus, true, true);
4083                         continue;
4084                 }
4085 #ifdef DHD_DEBUG
4086                 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4087                         printk(KERN_DEBUG "RxHdr:\n");
4088                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4089                                              bus->rxhdr, SDPCM_HDRLEN);
4090                 }
4091 #endif
4092
4093                 /* Extract hardware header fields */
4094                 len = get_unaligned_le16(bus->rxhdr);
4095                 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4096
4097                 /* All zeros means no more frames */
4098                 if (!(len | check)) {
4099                         *finished = true;
4100                         break;
4101                 }
4102
4103                 /* Validate check bytes */
4104                 if ((u16) ~(len ^ check)) {
4105                         DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4106                                 __func__, len, check));
4107                         bus->rx_badhdr++;
4108                         dhdsdio_rxfail(bus, false, false);
4109                         continue;
4110                 }
4111
4112                 /* Validate frame length */
4113                 if (len < SDPCM_HDRLEN) {
4114                         DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4115                                    __func__, len));
4116                         continue;
4117                 }
4118
4119                 /* Extract software header fields */
4120                 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4121                 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4122                 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4123                 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4124
4125                 /* Validate data offset */
4126                 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4127                         DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4128                                 "seq %d\n",
4129                                 __func__, doff, len, SDPCM_HDRLEN, seq));
4130                         bus->rx_badhdr++;
4131                         ASSERT(0);
4132                         dhdsdio_rxfail(bus, false, false);
4133                         continue;
4134                 }
4135
4136                 /* Save the readahead length if there is one */
4137                 bus->nextlen =
4138                     bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4139                 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4140                         DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4141                                 "(%d), seq %d\n",
4142                                 __func__, bus->nextlen, seq));
4143                         bus->nextlen = 0;
4144                 }
4145
4146                 /* Handle Flow Control */
4147                 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4148
4149                 if (bus->flowcontrol != fcbits) {
4150                         if (~bus->flowcontrol & fcbits)
4151                                 bus->fc_xoff++;
4152
4153                         if (bus->flowcontrol & ~fcbits)
4154                                 bus->fc_xon++;
4155
4156                         bus->fc_rcvd++;
4157                         bus->flowcontrol = fcbits;
4158                 }
4159
4160                 /* Check and update sequence number */
4161                 if (rxseq != seq) {
4162                         DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4163                                   seq, rxseq));
4164                         bus->rx_badseq++;
4165                         rxseq = seq;
4166                 }
4167
4168                 /* Check window for sanity */
4169                 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4170                         DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4171                                 __func__, txmax, bus->tx_seq));
4172                         txmax = bus->tx_seq + 2;
4173                 }
4174                 bus->tx_max = txmax;
4175
4176                 /* Call a separate function for control frames */
4177                 if (chan == SDPCM_CONTROL_CHANNEL) {
4178                         dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4179                         continue;
4180                 }
4181
4182                 ASSERT((chan == SDPCM_DATA_CHANNEL)
4183                        || (chan == SDPCM_EVENT_CHANNEL)
4184                        || (chan == SDPCM_TEST_CHANNEL)
4185                        || (chan == SDPCM_GLOM_CHANNEL));
4186
4187                 /* Length to read */
4188                 rdlen = (len > firstread) ? (len - firstread) : 0;
4189
4190                 /* May pad read to blocksize for efficiency */
4191                 if (bus->roundup && bus->blocksize &&
4192                         (rdlen > bus->blocksize)) {
4193                         pad = bus->blocksize - (rdlen % bus->blocksize);
4194                         if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4195                             ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4196                                 rdlen += pad;
4197                 } else if (rdlen % DHD_SDALIGN) {
4198                         rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4199                 }
4200
4201                 /* Satisfy length-alignment requirements */
4202                 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4203                         rdlen = roundup(rdlen, ALIGNMENT);
4204
4205                 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4206                         /* Too long -- skip this frame */
4207                         DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4208                                    __func__, len, rdlen));
4209                         bus->dhd->rx_errors++;
4210                         bus->rx_toolong++;
4211                         dhdsdio_rxfail(bus, false, false);
4212                         continue;
4213                 }
4214
4215                 dhd_os_sdlock_rxq(bus->dhd);
4216                 pkt = bcm_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4217                 if (!pkt) {
4218                         /* Give up on data, request rtx of events */
4219                         DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed: rdlen %d "
4220                                 "chan %d\n", __func__, rdlen, chan));
4221                         bus->dhd->rx_dropped++;
4222                         dhd_os_sdunlock_rxq(bus->dhd);
4223                         dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4224                         continue;
4225                 }
4226                 dhd_os_sdunlock_rxq(bus->dhd);
4227
4228                 ASSERT(!(pkt->prev));
4229
4230                 /* Leave room for what we already read, and align remainder */
4231                 ASSERT(firstread < pkt->len);
4232                 skb_pull(pkt, firstread);
4233                 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4234
4235                 /* Read the remaining frame data */
4236                 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4237                                         F2SYNC, ((u8 *) (pkt->data)), rdlen,
4238                                         pkt, NULL, NULL);
4239                 bus->f2rxdata++;
4240                 ASSERT(sdret != -BCME_PENDING);
4241
4242                 if (sdret < 0) {
4243                         DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4244                                    __func__, rdlen,
4245                                    ((chan ==
4246                                      SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4247                                         SDPCM_DATA_CHANNEL)
4248                                        ? "data" : "test")),
4249                                    sdret));
4250                         dhd_os_sdlock_rxq(bus->dhd);
4251                         bcm_pkt_buf_free_skb(pkt);
4252                         dhd_os_sdunlock_rxq(bus->dhd);
4253                         bus->dhd->rx_errors++;
4254                         dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4255                         continue;
4256                 }
4257
4258                 /* Copy the already-read portion */
4259                 skb_push(pkt, firstread);
4260                 memcpy(pkt->data, bus->rxhdr, firstread);
4261
4262 #ifdef DHD_DEBUG
4263                 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4264                         printk(KERN_DEBUG "Rx Data:\n");
4265                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4266                                              pkt->data, len);
4267                 }
4268 #endif
4269
4270 deliver:
4271                 /* Save superframe descriptor and allocate packet frame */
4272                 if (chan == SDPCM_GLOM_CHANNEL) {
4273                         if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4274                                 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4275                                         __func__, len));
4276 #ifdef DHD_DEBUG
4277                                 if (DHD_GLOM_ON()) {
4278                                         printk(KERN_DEBUG "Glom Data:\n");
4279                                         print_hex_dump_bytes("",
4280                                                              DUMP_PREFIX_OFFSET,
4281                                                              pkt->data, len);
4282                                 }
4283 #endif
4284                                 __skb_trim(pkt, len);
4285                                 ASSERT(doff == SDPCM_HDRLEN);
4286                                 skb_pull(pkt, SDPCM_HDRLEN);
4287                                 bus->glomd = pkt;
4288                         } else {
4289                                 DHD_ERROR(("%s: glom superframe w/o "
4290                                         "descriptor!\n", __func__));
4291                                 dhdsdio_rxfail(bus, false, false);
4292                         }
4293                         continue;
4294                 }
4295
4296                 /* Fill in packet len and prio, deliver upward */
4297                 __skb_trim(pkt, len);
4298                 skb_pull(pkt, doff);
4299
4300 #ifdef SDTEST
4301                 /* Test channel packets are processed separately */
4302                 if (chan == SDPCM_TEST_CHANNEL) {
4303                         dhdsdio_testrcv(bus, pkt, seq);
4304                         continue;
4305                 }
4306 #endif                          /* SDTEST */
4307
4308                 if (pkt->len == 0) {
4309                         dhd_os_sdlock_rxq(bus->dhd);
4310                         bcm_pkt_buf_free_skb(pkt);
4311                         dhd_os_sdunlock_rxq(bus->dhd);
4312                         continue;
4313                 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4314                         DHD_ERROR(("%s: rx protocol error\n", __func__));
4315                         dhd_os_sdlock_rxq(bus->dhd);
4316                         bcm_pkt_buf_free_skb(pkt);
4317                         dhd_os_sdunlock_rxq(bus->dhd);
4318                         bus->dhd->rx_errors++;
4319                         continue;
4320                 }
4321
4322                 /* Unlock during rx call */
4323                 dhd_os_sdunlock(bus->dhd);
4324                 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4325                 dhd_os_sdlock(bus->dhd);
4326         }
4327         rxcount = maxframes - rxleft;
4328 #ifdef DHD_DEBUG
4329         /* Message if we hit the limit */
4330         if (!rxleft && !sdtest)
4331                 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4332                           maxframes));
4333         else
4334 #endif                          /* DHD_DEBUG */
4335                 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4336         /* Back off rxseq if awaiting rtx, update rx_seq */
4337         if (bus->rxskip)
4338                 rxseq--;
4339         bus->rx_seq = rxseq;
4340
4341         return rxcount;
4342 }
4343
4344 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4345 {
4346         struct sdpcmd_regs *regs = bus->regs;
4347         u32 intstatus = 0;
4348         u32 hmb_data;
4349         u8 fcbits;
4350         uint retries = 0;
4351
4352         DHD_TRACE(("%s: Enter\n", __func__));
4353
4354         /* Read mailbox data and ack that we did so */
4355         R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4356         if (retries <= retry_limit)
4357                 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4358         bus->f1regdata += 2;
4359
4360         /* Dongle recomposed rx frames, accept them again */
4361         if (hmb_data & HMB_DATA_NAKHANDLED) {
4362                 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4363                           bus->rx_seq));
4364                 if (!bus->rxskip)
4365                         DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4366
4367                 bus->rxskip = false;
4368                 intstatus |= I_HMB_FRAME_IND;
4369         }
4370
4371         /*
4372          * DEVREADY does not occur with gSPI.
4373          */
4374         if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4375                 bus->sdpcm_ver =
4376                     (hmb_data & HMB_DATA_VERSION_MASK) >>
4377                     HMB_DATA_VERSION_SHIFT;
4378                 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4379                         DHD_ERROR(("Version mismatch, dongle reports %d, "
4380                                 "expecting %d\n",
4381                                 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4382                 else
4383                         DHD_INFO(("Dongle ready, protocol version %d\n",
4384                                   bus->sdpcm_ver));
4385         }
4386
4387         /*
4388          * Flow Control has been moved into the RX headers and this out of band
4389          * method isn't used any more.
4390          * remaining backward compatible with older dongles.
4391          */
4392         if (hmb_data & HMB_DATA_FC) {
4393                 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4394                                                         HMB_DATA_FCDATA_SHIFT;
4395
4396                 if (fcbits & ~bus->flowcontrol)
4397                         bus->fc_xoff++;
4398
4399                 if (bus->flowcontrol & ~fcbits)
4400                         bus->fc_xon++;
4401
4402                 bus->fc_rcvd++;
4403                 bus->flowcontrol = fcbits;
4404         }
4405
4406         /* Shouldn't be any others */
4407         if (hmb_data & ~(HMB_DATA_DEVREADY |
4408                          HMB_DATA_NAKHANDLED |
4409                          HMB_DATA_FC |
4410                          HMB_DATA_FWREADY |
4411                          HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4412                 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4413         }
4414
4415         return intstatus;
4416 }
4417
4418 bool dhdsdio_dpc(dhd_bus_t *bus)
4419 {
4420         bcmsdh_info_t *sdh = bus->sdh;
4421         struct sdpcmd_regs *regs = bus->regs;
4422         u32 intstatus, newstatus = 0;
4423         uint retries = 0;
4424         uint rxlimit = dhd_rxbound;     /* Rx frames to read before resched */
4425         uint txlimit = dhd_txbound;     /* Tx frames to send before resched */
4426         uint framecnt = 0;      /* Temporary counter of tx/rx frames */
4427         bool rxdone = true;     /* Flag for no more read data */
4428         bool resched = false;   /* Flag indicating resched wanted */
4429
4430         DHD_TRACE(("%s: Enter\n", __func__));
4431
4432         /* Start with leftover status bits */
4433         intstatus = bus->intstatus;
4434
4435         dhd_os_sdlock(bus->dhd);
4436
4437         /* If waiting for HTAVAIL, check status */
4438         if (bus->clkstate == CLK_PENDING) {
4439                 int err;
4440                 u8 clkctl, devctl = 0;
4441
4442 #ifdef DHD_DEBUG
4443                 /* Check for inconsistent device control */
4444                 devctl =
4445                     bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4446                 if (err) {
4447                         DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4448                                    __func__, err));
4449                         bus->dhd->busstate = DHD_BUS_DOWN;
4450                 } else {
4451                         ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4452                 }
4453 #endif                          /* DHD_DEBUG */
4454
4455                 /* Read CSR, if clock on switch to AVAIL, else ignore */
4456                 clkctl =
4457                     bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4458                                     &err);
4459                 if (err) {
4460                         DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4461                                    err));
4462                         bus->dhd->busstate = DHD_BUS_DOWN;
4463                 }
4464
4465                 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4466                           clkctl));
4467
4468                 if (SBSDIO_HTAV(clkctl)) {
4469                         devctl =
4470                             bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4471                                             &err);
4472                         if (err) {
4473                                 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4474                                            __func__, err));
4475                                 bus->dhd->busstate = DHD_BUS_DOWN;
4476                         }
4477                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4478                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4479                                          devctl, &err);
4480                         if (err) {
4481                                 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4482                                            __func__, err));
4483                                 bus->dhd->busstate = DHD_BUS_DOWN;
4484                         }
4485                         bus->clkstate = CLK_AVAIL;
4486                 } else {
4487                         goto clkwait;
4488                 }
4489         }
4490
4491         BUS_WAKE(bus);
4492
4493         /* Make sure backplane clock is on */
4494         dhdsdio_clkctl(bus, CLK_AVAIL, true);
4495         if (bus->clkstate == CLK_PENDING)
4496                 goto clkwait;
4497
4498         /* Pending interrupt indicates new device status */
4499         if (bus->ipend) {
4500                 bus->ipend = false;
4501                 R_SDREG(newstatus, &regs->intstatus, retries);
4502                 bus->f1regdata++;
4503                 if (bcmsdh_regfail(bus->sdh))
4504                         newstatus = 0;
4505                 newstatus &= bus->hostintmask;
4506                 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4507                 if (newstatus) {
4508                         W_SDREG(newstatus, &regs->intstatus, retries);
4509                         bus->f1regdata++;
4510                 }
4511         }
4512
4513         /* Merge new bits with previous */
4514         intstatus |= newstatus;
4515         bus->intstatus = 0;
4516
4517         /* Handle flow-control change: read new state in case our ack
4518          * crossed another change interrupt.  If change still set, assume
4519          * FC ON for safety, let next loop through do the debounce.
4520          */
4521         if (intstatus & I_HMB_FC_CHANGE) {
4522                 intstatus &= ~I_HMB_FC_CHANGE;
4523                 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4524                 R_SDREG(newstatus, &regs->intstatus, retries);
4525                 bus->f1regdata += 2;
4526                 bus->fcstate =
4527                     !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4528                 intstatus |= (newstatus & bus->hostintmask);
4529         }
4530
4531         /* Handle host mailbox indication */
4532         if (intstatus & I_HMB_HOST_INT) {
4533                 intstatus &= ~I_HMB_HOST_INT;
4534                 intstatus |= dhdsdio_hostmail(bus);
4535         }
4536
4537         /* Generally don't ask for these, can get CRC errors... */
4538         if (intstatus & I_WR_OOSYNC) {
4539                 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4540                 intstatus &= ~I_WR_OOSYNC;
4541         }
4542
4543         if (intstatus & I_RD_OOSYNC) {
4544                 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4545                 intstatus &= ~I_RD_OOSYNC;
4546         }
4547
4548         if (intstatus & I_SBINT) {
4549                 DHD_ERROR(("Dongle reports SBINT\n"));
4550                 intstatus &= ~I_SBINT;
4551         }
4552
4553         /* Would be active due to wake-wlan in gSPI */
4554         if (intstatus & I_CHIPACTIVE) {
4555                 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4556                 intstatus &= ~I_CHIPACTIVE;
4557         }
4558
4559         /* Ignore frame indications if rxskip is set */
4560         if (bus->rxskip)
4561                 intstatus &= ~I_HMB_FRAME_IND;
4562
4563         /* On frame indication, read available frames */
4564         if (PKT_AVAILABLE()) {
4565                 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4566                 if (rxdone || bus->rxskip)
4567                         intstatus &= ~I_HMB_FRAME_IND;
4568                 rxlimit -= min(framecnt, rxlimit);
4569         }
4570
4571         /* Keep still-pending events for next scheduling */
4572         bus->intstatus = intstatus;
4573
4574 clkwait:
4575 #if defined(OOB_INTR_ONLY)
4576         bcmsdh_oob_intr_set(1);
4577 #endif                          /* (OOB_INTR_ONLY) */
4578         /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4579          * or clock availability.  (Allows tx loop to check ipend if desired.)
4580          * (Unless register access seems hosed, as we may not be able to ACK...)
4581          */
4582         if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4583                 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4584                           __func__, rxdone, framecnt));
4585                 bus->intdis = false;
4586                 bcmsdh_intr_enable(sdh);
4587         }
4588
4589         if (DATAOK(bus) && bus->ctrl_frame_stat &&
4590                 (bus->clkstate == CLK_AVAIL)) {
4591                 int ret, i;
4592
4593                 ret =
4594                     dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4595                                         F2SYNC, (u8 *) bus->ctrl_frame_buf,
4596                                         (u32) bus->ctrl_frame_len, NULL,
4597                                         NULL, NULL);
4598                 ASSERT(ret != -BCME_PENDING);
4599
4600                 if (ret < 0) {
4601                         /* On failure, abort the command and
4602                                 terminate the frame */
4603                         DHD_INFO(("%s: sdio error %d, abort command and "
4604                                 "terminate frame.\n", __func__, ret));
4605                         bus->tx_sderrs++;
4606
4607                         bcmsdh_abort(sdh, SDIO_FUNC_2);
4608
4609                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4610                                          SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4611                                          NULL);
4612                         bus->f1regdata++;
4613
4614                         for (i = 0; i < 3; i++) {
4615                                 u8 hi, lo;
4616                                 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4617                                                      SBSDIO_FUNC1_WFRAMEBCHI,
4618                                                      NULL);
4619                                 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4620                                                      SBSDIO_FUNC1_WFRAMEBCLO,
4621                                                      NULL);
4622                                 bus->f1regdata += 2;
4623                                 if ((hi == 0) && (lo == 0))
4624                                         break;
4625                         }
4626
4627                 }
4628                 if (ret == 0)
4629                         bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4630
4631                 DHD_INFO(("Return_dpc value is : %d\n", ret));
4632                 bus->ctrl_frame_stat = false;
4633                 dhd_wait_event_wakeup(bus->dhd);
4634         }
4635         /* Send queued frames (limit 1 if rx may still be pending) */
4636         else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4637                  bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4638                  && DATAOK(bus)) {
4639                 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4640                 framecnt = dhdsdio_sendfromq(bus, framecnt);
4641                 txlimit -= framecnt;
4642         }
4643
4644         /* Resched if events or tx frames are pending,
4645                  else await next interrupt */
4646         /* On failed register access, all bets are off:
4647                  no resched or interrupts */
4648         if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4649                 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4650                         "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4651                 bus->dhd->busstate = DHD_BUS_DOWN;
4652                 bus->intstatus = 0;
4653         } else if (bus->clkstate == CLK_PENDING) {
4654                 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4655                         "I_CHIPACTIVE interrupt\n", __func__));
4656                 resched = true;
4657         } else if (bus->intstatus || bus->ipend ||
4658                 (!bus->fcstate && bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4659                         DATAOK(bus)) || PKT_AVAILABLE()) {
4660                 resched = true;
4661         }
4662
4663         bus->dpc_sched = resched;
4664
4665         /* If we're done for now, turn off clock request. */
4666         if ((bus->clkstate != CLK_PENDING)
4667             && bus->idletime == DHD_IDLE_IMMEDIATE) {
4668                 bus->activity = false;
4669                 dhdsdio_clkctl(bus, CLK_NONE, false);
4670         }
4671
4672         dhd_os_sdunlock(bus->dhd);
4673
4674         return resched;
4675 }
4676
4677 bool dhd_bus_dpc(struct dhd_bus *bus)
4678 {
4679         bool resched;
4680
4681         /* Call the DPC directly. */
4682         DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4683         resched = dhdsdio_dpc(bus);
4684
4685         return resched;
4686 }
4687
4688 void dhdsdio_isr(void *arg)
4689 {
4690         dhd_bus_t *bus = (dhd_bus_t *) arg;
4691         bcmsdh_info_t *sdh;
4692
4693         DHD_TRACE(("%s: Enter\n", __func__));
4694
4695         if (!bus) {
4696                 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4697                 return;
4698         }
4699         sdh = bus->sdh;
4700
4701         if (bus->dhd->busstate == DHD_BUS_DOWN) {
4702                 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4703                            __func__));
4704                 return;
4705         }
4706         /* Count the interrupt call */
4707         bus->intrcount++;
4708         bus->ipend = true;
4709
4710         /* Shouldn't get this interrupt if we're sleeping? */
4711         if (bus->sleeping) {
4712                 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4713                 return;
4714         }
4715
4716         /* Disable additional interrupts (is this needed now)? */
4717         if (bus->intr)
4718                 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4719         else
4720                 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4721
4722         bcmsdh_intr_disable(sdh);
4723         bus->intdis = true;
4724
4725 #if defined(SDIO_ISR_THREAD)
4726         DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4727         while (dhdsdio_dpc(bus))
4728                 ;
4729 #else
4730         bus->dpc_sched = true;
4731         dhd_sched_dpc(bus->dhd);
4732 #endif
4733
4734 }
4735
4736 #ifdef SDTEST
4737 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4738 {
4739         /* Default to specified length, or full range */
4740         if (dhd_pktgen_len) {
4741                 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4742                 bus->pktgen_minlen = bus->pktgen_maxlen;
4743         } else {
4744                 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4745                 bus->pktgen_minlen = 0;
4746         }
4747         bus->pktgen_len = (u16) bus->pktgen_minlen;
4748
4749         /* Default to per-watchdog burst with 10s print time */
4750         bus->pktgen_freq = 1;
4751         bus->pktgen_print = 10000 / dhd_watchdog_ms;
4752         bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4753
4754         /* Default to echo mode */
4755         bus->pktgen_mode = DHD_PKTGEN_ECHO;
4756         bus->pktgen_stop = 1;
4757 }
4758
4759 static void dhdsdio_pktgen(dhd_bus_t *bus)
4760 {
4761         struct sk_buff *pkt;
4762         u8 *data;
4763         uint pktcount;
4764         uint fillbyte;
4765         u16 len;
4766
4767         /* Display current count if appropriate */
4768         if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4769                 bus->pktgen_ptick = 0;
4770                 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4771                        __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4772         }
4773
4774         /* For recv mode, just make sure dongle has started sending */
4775         if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4776                 if (!bus->pktgen_rcvd)
4777                         dhdsdio_sdtest_set(bus, true);
4778                 return;
4779         }
4780
4781         /* Otherwise, generate or request the specified number of packets */
4782         for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4783                 /* Stop if total has been reached */
4784                 if (bus->pktgen_total
4785                     && (bus->pktgen_sent >= bus->pktgen_total)) {
4786                         bus->pktgen_count = 0;
4787                         break;
4788                 }
4789
4790                 /* Allocate an appropriate-sized packet */
4791                 len = bus->pktgen_len;
4792                 pkt = bcm_pkt_buf_get_skb(
4793                         (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4794                         true);
4795                 if (!pkt) {
4796                         DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n",
4797                                 __func__));
4798                         break;
4799                 }
4800                 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4801                          DHD_SDALIGN);
4802                 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4803
4804                 /* Write test header cmd and extra based on mode */
4805                 switch (bus->pktgen_mode) {
4806                 case DHD_PKTGEN_ECHO:
4807                         *data++ = SDPCM_TEST_ECHOREQ;
4808                         *data++ = (u8) bus->pktgen_sent;
4809                         break;
4810
4811                 case DHD_PKTGEN_SEND:
4812                         *data++ = SDPCM_TEST_DISCARD;
4813                         *data++ = (u8) bus->pktgen_sent;
4814                         break;
4815
4816                 case DHD_PKTGEN_RXBURST:
4817                         *data++ = SDPCM_TEST_BURST;
4818                         *data++ = (u8) bus->pktgen_count;
4819                         break;
4820
4821                 default:
4822                         DHD_ERROR(("Unrecognized pktgen mode %d\n",
4823                                    bus->pktgen_mode));
4824                         bcm_pkt_buf_free_skb(pkt, true);
4825                         bus->pktgen_count = 0;
4826                         return;
4827                 }
4828
4829                 /* Write test header length field */
4830                 *data++ = (len >> 0);
4831                 *data++ = (len >> 8);
4832
4833                 /* Then fill in the remainder -- N/A for burst,
4834                          but who cares... */
4835                 for (fillbyte = 0; fillbyte < len; fillbyte++)
4836                         *data++ =
4837                             SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4838
4839 #ifdef DHD_DEBUG
4840                 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4841                         data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4842                         printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
4843                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4844                                              pkt->len - SDPCM_HDRLEN);
4845                 }
4846 #endif
4847
4848                 /* Send it */
4849                 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4850                         bus->pktgen_fail++;
4851                         if (bus->pktgen_stop
4852                             && bus->pktgen_stop == bus->pktgen_fail)
4853                                 bus->pktgen_count = 0;
4854                 }
4855                 bus->pktgen_sent++;
4856
4857                 /* Bump length if not fixed, wrap at max */
4858                 if (++bus->pktgen_len > bus->pktgen_maxlen)
4859                         bus->pktgen_len = (u16) bus->pktgen_minlen;
4860
4861                 /* Special case for burst mode: just send one request! */
4862                 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4863                         break;
4864         }
4865 }
4866
4867 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4868 {
4869         struct sk_buff *pkt;
4870         u8 *data;
4871
4872         /* Allocate the packet */
4873         pkt = bcm_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4874                 DHD_SDALIGN, true);
4875         if (!pkt) {
4876                 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n", __func__));
4877                 return;
4878         }
4879         PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4880         data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4881
4882         /* Fill in the test header */
4883         *data++ = SDPCM_TEST_SEND;
4884         *data++ = start;
4885         *data++ = (bus->pktgen_maxlen >> 0);
4886         *data++ = (bus->pktgen_maxlen >> 8);
4887
4888         /* Send it */
4889         if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4890                 bus->pktgen_fail++;
4891 }
4892
4893 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4894 {
4895         u8 *data;
4896         uint pktlen;
4897
4898         u8 cmd;
4899         u8 extra;
4900         u16 len;
4901         u16 offset;
4902
4903         /* Check for min length */
4904         pktlen = pkt->len;
4905         if (pktlen < SDPCM_TEST_HDRLEN) {
4906                 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4907                            pktlen));
4908                 bcm_pkt_buf_free_skb(pkt, false);
4909                 return;
4910         }
4911
4912         /* Extract header fields */
4913         data = pkt->data;
4914         cmd = *data++;
4915         extra = *data++;
4916         len = *data++;
4917         len += *data++ << 8;
4918
4919         /* Check length for relevant commands */
4920         if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4921             || cmd == SDPCM_TEST_ECHORSP) {
4922                 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4923                         DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4924                                 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4925                                 pktlen, seq, cmd, extra, len));
4926                         bcm_pkt_buf_free_skb(pkt, false);
4927                         return;
4928                 }
4929         }
4930
4931         /* Process as per command */
4932         switch (cmd) {
4933         case SDPCM_TEST_ECHOREQ:
4934                 /* Rx->Tx turnaround ok (even on NDIS w/current
4935                          implementation) */
4936                 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4937                 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4938                         bus->pktgen_sent++;
4939                 } else {
4940                         bus->pktgen_fail++;
4941                         bcm_pkt_buf_free_skb(pkt, false);
4942                 }
4943                 bus->pktgen_rcvd++;
4944                 break;
4945
4946         case SDPCM_TEST_ECHORSP:
4947                 if (bus->ext_loop) {
4948                         bcm_pkt_buf_free_skb(pkt, false);
4949                         bus->pktgen_rcvd++;
4950                         break;
4951                 }
4952
4953                 for (offset = 0; offset < len; offset++, data++) {
4954                         if (*data != SDPCM_TEST_FILL(offset, extra)) {
4955                                 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4956                                         offset, len,
4957                                         SDPCM_TEST_FILL(offset, extra), *data));
4958                                 break;
4959                         }
4960                 }
4961                 bcm_pkt_buf_free_skb(pkt, false);
4962                 bus->pktgen_rcvd++;
4963                 break;
4964
4965         case SDPCM_TEST_DISCARD:
4966                 bcm_pkt_buf_free_skb(pkt, false);
4967                 bus->pktgen_rcvd++;
4968                 break;
4969
4970         case SDPCM_TEST_BURST:
4971         case SDPCM_TEST_SEND:
4972         default:
4973                 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4974                         "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4975                         pktlen, seq, cmd, extra, len));
4976                 bcm_pkt_buf_free_skb(pkt, false);
4977                 break;
4978         }
4979
4980         /* For recv mode, stop at limie (and tell dongle to stop sending) */
4981         if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4982                 if (bus->pktgen_total
4983                     && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4984                         bus->pktgen_count = 0;
4985                         dhdsdio_sdtest_set(bus, false);
4986                 }
4987         }
4988 }
4989 #endif                          /* SDTEST */
4990
4991 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4992 {
4993         dhd_bus_t *bus;
4994
4995         DHD_TIMER(("%s: Enter\n", __func__));
4996
4997         bus = dhdp->bus;
4998
4999         if (bus->dhd->dongle_reset)
5000                 return false;
5001
5002         /* Ignore the timer if simulating bus down */
5003         if (bus->sleeping)
5004                 return false;
5005
5006         dhd_os_sdlock(bus->dhd);
5007
5008         /* Poll period: check device if appropriate. */
5009         if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5010                 u32 intstatus = 0;
5011
5012                 /* Reset poll tick */
5013                 bus->polltick = 0;
5014
5015                 /* Check device if no interrupts */
5016                 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5017
5018                         if (!bus->dpc_sched) {
5019                                 u8 devpend;
5020                                 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
5021                                                           SDIO_CCCR_INTx,
5022                                                           NULL);
5023                                 intstatus =
5024                                     devpend & (INTR_STATUS_FUNC1 |
5025                                                INTR_STATUS_FUNC2);
5026                         }
5027
5028                         /* If there is something, make like the ISR and
5029                                  schedule the DPC */
5030                         if (intstatus) {
5031                                 bus->pollcnt++;
5032                                 bus->ipend = true;
5033                                 if (bus->intr)
5034                                         bcmsdh_intr_disable(bus->sdh);
5035
5036                                 bus->dpc_sched = true;
5037                                 dhd_sched_dpc(bus->dhd);
5038
5039                         }
5040                 }
5041
5042                 /* Update interrupt tracking */
5043                 bus->lastintrs = bus->intrcount;
5044         }
5045 #ifdef DHD_DEBUG
5046         /* Poll for console output periodically */
5047         if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
5048                 bus->console.count += dhd_watchdog_ms;
5049                 if (bus->console.count >= dhd_console_ms) {
5050                         bus->console.count -= dhd_console_ms;
5051                         /* Make sure backplane clock is on */
5052                         dhdsdio_clkctl(bus, CLK_AVAIL, false);
5053                         if (dhdsdio_readconsole(bus) < 0)
5054                                 dhd_console_ms = 0;     /* On error,
5055                                                          stop trying */
5056                 }
5057         }
5058 #endif                          /* DHD_DEBUG */
5059
5060 #ifdef SDTEST
5061         /* Generate packets if configured */
5062         if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5063                 /* Make sure backplane clock is on */
5064                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5065                 bus->pktgen_tick = 0;
5066                 dhdsdio_pktgen(bus);
5067         }
5068 #endif
5069
5070         /* On idle timeout clear activity flag and/or turn off clock */
5071         if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5072                 if (++bus->idlecount >= bus->idletime) {
5073                         bus->idlecount = 0;
5074                         if (bus->activity) {
5075                                 bus->activity = false;
5076                                 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
5077                         } else {
5078                                 dhdsdio_clkctl(bus, CLK_NONE, false);
5079                         }
5080                 }
5081         }
5082
5083         dhd_os_sdunlock(bus->dhd);
5084
5085         return bus->ipend;
5086 }
5087
5088 #ifdef DHD_DEBUG
5089 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
5090 {
5091         dhd_bus_t *bus = dhdp->bus;
5092         u32 addr, val;
5093         int rv;
5094         struct sk_buff *pkt;
5095
5096         /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5097         if (bus->console_addr == 0)
5098                 return -ENOTSUPP;
5099
5100         /* Exclusive bus access */
5101         dhd_os_sdlock(bus->dhd);
5102
5103         /* Don't allow input if dongle is in reset */
5104         if (bus->dhd->dongle_reset) {
5105                 dhd_os_sdunlock(bus->dhd);
5106                 return -EPERM;
5107         }
5108
5109         /* Request clock to allow SDIO accesses */
5110         BUS_WAKE(bus);
5111         /* No pend allowed since txpkt is called later, ht clk has to be on */
5112         dhdsdio_clkctl(bus, CLK_AVAIL, false);
5113
5114         /* Zero cbuf_index */
5115         addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5116         val = cpu_to_le32(0);
5117         rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5118         if (rv < 0)
5119                 goto done;
5120
5121         /* Write message into cbuf */
5122         addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5123         rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
5124         if (rv < 0)
5125                 goto done;
5126
5127         /* Write length into vcons_in */
5128         addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5129         val = cpu_to_le32(msglen);
5130         rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5131         if (rv < 0)
5132                 goto done;
5133
5134         /* Bump dongle by sending an empty event pkt.
5135          * sdpcm_sendup (RX) checks for virtual console input.
5136          */
5137         pkt = bcm_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5138         if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5139                 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5140
5141 done:
5142         if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5143                 bus->activity = false;
5144                 dhdsdio_clkctl(bus, CLK_NONE, true);
5145         }
5146
5147         dhd_os_sdunlock(bus->dhd);
5148
5149         return rv;
5150 }
5151 #endif                          /* DHD_DEBUG */
5152
5153 static bool dhdsdio_chipmatch(u16 chipid)
5154 {
5155         if (chipid == BCM4325_CHIP_ID)
5156                 return true;
5157         if (chipid == BCM4329_CHIP_ID)
5158                 return true;
5159         if (chipid == BCM4319_CHIP_ID)
5160                 return true;
5161         return false;
5162 }
5163
5164 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5165                            u16 slot, u16 func, uint bustype, void *regsva,
5166                            void *sdh)
5167 {
5168         int ret;
5169         dhd_bus_t *bus;
5170
5171         /* Init global variables at run-time, not as part of the declaration.
5172          * This is required to support init/de-init of the driver.
5173          * Initialization
5174          * of globals as part of the declaration results in non-deterministic
5175          * behavior since the value of the globals may be different on the
5176          * first time that the driver is initialized vs subsequent
5177          * initializations.
5178          */
5179         dhd_txbound = DHD_TXBOUND;
5180         dhd_rxbound = DHD_RXBOUND;
5181         dhd_alignctl = true;
5182         sd1idle = true;
5183         dhd_readahead = true;
5184         retrydata = false;
5185         dhd_dongle_memsize = 0;
5186         dhd_txminmax = DHD_TXMINMAX;
5187
5188         forcealign = true;
5189
5190         dhd_common_init();
5191
5192         DHD_TRACE(("%s: Enter\n", __func__));
5193         DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5194
5195         /* We make assumptions about address window mappings */
5196         ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5197
5198         /* BCMSDH passes venid and devid based on CIS parsing -- but
5199          * low-power start
5200          * means early parse could fail, so here we should get either an ID
5201          * we recognize OR (-1) indicating we must request power first.
5202          */
5203         /* Check the Vendor ID */
5204         switch (venid) {
5205         case 0x0000:
5206         case PCI_VENDOR_ID_BROADCOM:
5207                 break;
5208         default:
5209                 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5210                 return NULL;
5211         }
5212
5213         /* Check the Device ID and make sure it's one that we support */
5214         switch (devid) {
5215         case BCM4325_D11DUAL_ID:        /* 4325 802.11a/g id */
5216         case BCM4325_D11G_ID:   /* 4325 802.11g 2.4Ghz band id */
5217         case BCM4325_D11A_ID:   /* 4325 802.11a 5Ghz band id */
5218                 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5219                 break;
5220         case BCM4329_D11NDUAL_ID:       /* 4329 802.11n dualband device */
5221         case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5222         case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5223         case 0x4329:
5224                 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5225                 break;
5226         case BCM4319_D11N_ID:   /* 4319 802.11n id */
5227         case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5228         case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5229                 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5230                 break;
5231         case 0:
5232                 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5233                           __func__));
5234                 break;
5235
5236         default:
5237                 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5238                            __func__, venid, devid));
5239                 return NULL;
5240         }
5241
5242         /* Allocate private bus interface state */
5243         bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5244         if (!bus) {
5245                 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5246                 goto fail;
5247         }
5248         bus->sdh = sdh;
5249         bus->cl_devid = (u16) devid;
5250         bus->bus = DHD_BUS;
5251         bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5252         bus->usebufpool = false;        /* Use bufpool if allocated,
5253                                          else use locally malloced rxbuf */
5254
5255         /* attempt to attach to the dongle */
5256         if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5257                 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5258                 goto fail;
5259         }
5260
5261         /* Attach to the dhd/OS/network interface */
5262         bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5263         if (!bus->dhd) {
5264                 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5265                 goto fail;
5266         }
5267
5268         /* Allocate buffers */
5269         if (!(dhdsdio_probe_malloc(bus, sdh))) {
5270                 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5271                 goto fail;
5272         }
5273
5274         if (!(dhdsdio_probe_init(bus, sdh))) {
5275                 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5276                 goto fail;
5277         }
5278
5279         /* Register interrupt callback, but mask it (not operational yet). */
5280         DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5281                   __func__));
5282         bcmsdh_intr_disable(sdh);
5283         ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5284         if (ret != 0) {
5285                 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5286                            __func__, ret));
5287                 goto fail;
5288         }
5289         DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5290
5291         DHD_INFO(("%s: completed!!\n", __func__));
5292
5293         /* if firmware path present try to download and bring up bus */
5294         ret = dhd_bus_start(bus->dhd);
5295         if (ret != 0) {
5296                 if (ret == -ENOLINK) {
5297                         DHD_ERROR(("%s: dongle is not responding\n", __func__));
5298                         goto fail;
5299                 }
5300         }
5301         /* Ok, have the per-port tell the stack we're open for business */
5302         if (dhd_net_attach(bus->dhd, 0) != 0) {
5303                 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5304                 goto fail;
5305         }
5306
5307         return bus;
5308
5309 fail:
5310         dhdsdio_release(bus);
5311         return NULL;
5312 }
5313
5314 static bool
5315 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5316 {
5317         u8 clkctl = 0;
5318         int err = 0;
5319
5320         bus->alp_only = true;
5321
5322         /* Return the window to backplane enumeration space for core access */
5323         if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5324                 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5325
5326 #ifdef DHD_DEBUG
5327         printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5328                bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5329
5330 #endif                          /* DHD_DEBUG */
5331
5332         /*
5333          * Force PLL off until dhdsdio_chip_attach()
5334          * programs PLL control regs
5335          */
5336
5337         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5338                          DHD_INIT_CLKCTL1, &err);
5339         if (!err)
5340                 clkctl =
5341                     bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5342                                     &err);
5343
5344         if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5345                 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5346                         "0x%02x read 0x%02x\n",
5347                         err, DHD_INIT_CLKCTL1, clkctl));
5348                 goto fail;
5349         }
5350
5351         if (dhdsdio_chip_attach(bus, regsva)) {
5352                 DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
5353                 goto fail;
5354         }
5355
5356         bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5357
5358         if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
5359                 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5360                            __func__, bus->ci->chip));
5361                 goto fail;
5362         }
5363
5364         dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5365
5366         /* Get info on the ARM and SOCRAM cores... */
5367         if (!DHD_NOPMU(bus)) {
5368                 bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
5369                         CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5370                 bus->orig_ramsize = bus->ci->ramsize;
5371                 if (!(bus->orig_ramsize)) {
5372                         DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5373                                    __func__));
5374                         goto fail;
5375                 }
5376                 bus->ramsize = bus->orig_ramsize;
5377                 if (dhd_dongle_memsize)
5378                         dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5379
5380                 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5381                            bus->ramsize, bus->orig_ramsize));
5382         }
5383
5384         bus->regs = (void *)bus->ci->buscorebase;
5385
5386         /* Set core control so an SDIO reset does a backplane reset */
5387         OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5388
5389         bcm_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5390
5391         /* Locate an appropriately-aligned portion of hdrbuf */
5392         bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5393
5394         /* Set the poll and/or interrupt flags */
5395         bus->intr = (bool) dhd_intr;
5396         bus->poll = (bool) dhd_poll;
5397         if (bus->poll)
5398                 bus->pollrate = 1;
5399
5400         return true;
5401
5402 fail:
5403         return false;
5404 }
5405
5406 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5407 {
5408         DHD_TRACE(("%s: Enter\n", __func__));
5409
5410         if (bus->dhd->maxctl) {
5411                 bus->rxblen =
5412                     roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5413                             ALIGNMENT) + DHD_SDALIGN;
5414                 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5415                 if (!(bus->rxbuf)) {
5416                         DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5417                                    __func__, bus->rxblen));
5418                         goto fail;
5419                 }
5420         }
5421
5422         /* Allocate buffer to receive glomed packet */
5423         bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5424         if (!(bus->databuf)) {
5425                 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5426                            __func__, MAX_DATA_BUF));
5427                 /* release rxbuf which was already located as above */
5428                 if (!bus->rxblen)
5429                         kfree(bus->rxbuf);
5430                 goto fail;
5431         }
5432
5433         /* Align the buffer */
5434         if ((unsigned long)bus->databuf % DHD_SDALIGN)
5435                 bus->dataptr =
5436                     bus->databuf + (DHD_SDALIGN -
5437                                     ((unsigned long)bus->databuf % DHD_SDALIGN));
5438         else
5439                 bus->dataptr = bus->databuf;
5440
5441         return true;
5442
5443 fail:
5444         return false;
5445 }
5446
5447 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5448 {
5449         s32 fnum;
5450
5451         DHD_TRACE(("%s: Enter\n", __func__));
5452
5453 #ifdef SDTEST
5454         dhdsdio_pktgen_init(bus);
5455 #endif                          /* SDTEST */
5456
5457         /* Disable F2 to clear any intermediate frame state on the dongle */
5458         bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1,
5459                          NULL);
5460
5461         bus->dhd->busstate = DHD_BUS_DOWN;
5462         bus->sleeping = false;
5463         bus->rxflow = false;
5464         bus->prev_rxlim_hit = 0;
5465
5466         /* Done with backplane-dependent accesses, can drop clock... */
5467         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5468
5469         /* ...and initialize clock/power states */
5470         bus->clkstate = CLK_SDONLY;
5471         bus->idletime = (s32) dhd_idletime;
5472         bus->idleclock = DHD_IDLE_ACTIVE;
5473
5474         /* Query the F2 block size, set roundup accordingly */
5475         fnum = 2;
5476         if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5477                             &bus->blocksize, sizeof(s32), false) != 0) {
5478                 bus->blocksize = 0;
5479                 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5480         } else {
5481                 DHD_INFO(("%s: Initial value for %s is %d\n",
5482                           __func__, "sd_blocksize", bus->blocksize));
5483         }
5484         bus->roundup = min(max_roundup, bus->blocksize);
5485
5486         /* Query if bus module supports packet chaining,
5487                  default to use if supported */
5488         if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5489                             &bus->sd_rxchain, sizeof(s32),
5490                             false) != 0) {
5491                 bus->sd_rxchain = false;
5492         } else {
5493                 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5494                           __func__,
5495                           (bus->sd_rxchain ? "supports" : "does not support")));
5496         }
5497         bus->use_rxchain = (bool) bus->sd_rxchain;
5498
5499         return true;
5500 }
5501
5502 bool
5503 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5504 {
5505         bool ret;
5506         bus->fw_path = fw_path;
5507         bus->nv_path = nv_path;
5508
5509         ret = dhdsdio_download_firmware(bus, bus->sdh);
5510
5511         return ret;
5512 }
5513
5514 static bool
5515 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5516 {
5517         bool ret;
5518
5519         /* Download the firmware */
5520         dhdsdio_clkctl(bus, CLK_AVAIL, false);
5521
5522         ret = _dhdsdio_download_firmware(bus) == 0;
5523
5524         dhdsdio_clkctl(bus, CLK_SDONLY, false);
5525
5526         return ret;
5527 }
5528
5529 /* Detach and free everything */
5530 static void dhdsdio_release(dhd_bus_t *bus)
5531 {
5532         DHD_TRACE(("%s: Enter\n", __func__));
5533
5534         if (bus) {
5535                 /* De-register interrupt handler */
5536                 bcmsdh_intr_disable(bus->sdh);
5537                 bcmsdh_intr_dereg(bus->sdh);
5538
5539                 if (bus->dhd) {
5540                         dhd_detach(bus->dhd);
5541                         dhdsdio_release_dongle(bus);
5542                         bus->dhd = NULL;
5543                 }
5544
5545                 dhdsdio_release_malloc(bus);
5546
5547                 kfree(bus);
5548         }
5549
5550         DHD_TRACE(("%s: Disconnected\n", __func__));
5551 }
5552
5553 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5554 {
5555         DHD_TRACE(("%s: Enter\n", __func__));
5556
5557         if (bus->dhd && bus->dhd->dongle_reset)
5558                 return;
5559
5560         if (bus->rxbuf) {
5561                 kfree(bus->rxbuf);
5562                 bus->rxctl = bus->rxbuf = NULL;
5563                 bus->rxlen = 0;
5564         }
5565
5566         kfree(bus->databuf);
5567         bus->databuf = NULL;
5568 }
5569
5570 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5571 {
5572         DHD_TRACE(("%s: Enter\n", __func__));
5573
5574         if (bus->dhd && bus->dhd->dongle_reset)
5575                 return;
5576
5577         if (bus->ci) {
5578                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5579                 dhdsdio_clkctl(bus, CLK_NONE, false);
5580                 dhdsdio_chip_detach(bus);
5581                 if (bus->vars && bus->varsz)
5582                         kfree(bus->vars);
5583                 bus->vars = NULL;
5584         }
5585
5586         DHD_TRACE(("%s: Disconnected\n", __func__));
5587 }
5588
5589 static void dhdsdio_disconnect(void *ptr)
5590 {
5591         dhd_bus_t *bus = (dhd_bus_t *)ptr;
5592
5593         DHD_TRACE(("%s: Enter\n", __func__));
5594
5595         if (bus) {
5596                 ASSERT(bus->dhd);
5597                 dhdsdio_release(bus);
5598         }
5599
5600         DHD_TRACE(("%s: Disconnected\n", __func__));
5601 }
5602
5603 /* Register/Unregister functions are called by the main DHD entry
5604  * point (e.g. module insertion) to link with the bus driver, in
5605  * order to look for or await the device.
5606  */
5607
5608 static bcmsdh_driver_t dhd_sdio = {
5609         dhdsdio_probe,
5610         dhdsdio_disconnect
5611 };
5612
5613 int dhd_bus_register(void)
5614 {
5615         DHD_TRACE(("%s: Enter\n", __func__));
5616
5617         return bcmsdh_register(&dhd_sdio);
5618 }
5619
5620 void dhd_bus_unregister(void)
5621 {
5622         DHD_TRACE(("%s: Enter\n", __func__));
5623
5624         bcmsdh_unregister();
5625 }
5626
5627 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5628 {
5629         int bcmerror = -1;
5630         int offset = 0;
5631         uint len;
5632         void *image = NULL;
5633         u8 *memblock = NULL, *memptr;
5634
5635         DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5636
5637         image = dhd_os_open_image(fw_path);
5638         if (image == NULL)
5639                 goto err;
5640
5641         memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5642         if (memblock == NULL) {
5643                 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5644                            __func__, MEMBLOCK));
5645                 goto err;
5646         }
5647         if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5648                 memptr +=
5649                     (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5650
5651         /* Download image */
5652         while ((len =
5653                 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5654                 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5655                 if (bcmerror) {
5656                         DHD_ERROR(("%s: error %d on writing %d membytes at "
5657                         "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5658                         goto err;
5659                 }
5660
5661                 offset += MEMBLOCK;
5662         }
5663
5664 err:
5665         kfree(memblock);
5666
5667         if (image)
5668                 dhd_os_close_image(image);
5669
5670         return bcmerror;
5671 }
5672
5673 /*
5674  * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5675  * and ending in a NUL.
5676  * Removes carriage returns, empty lines, comment lines, and converts
5677  * newlines to NULs.
5678  * Shortens buffer as needed and pads with NULs.  End of buffer is marked
5679  * by two NULs.
5680 */
5681
5682 static uint process_nvram_vars(char *varbuf, uint len)
5683 {
5684         char *dp;
5685         bool findNewline;
5686         int column;
5687         uint buf_len, n;
5688
5689         dp = varbuf;
5690
5691         findNewline = false;
5692         column = 0;
5693
5694         for (n = 0; n < len; n++) {
5695                 if (varbuf[n] == 0)
5696                         break;
5697                 if (varbuf[n] == '\r')
5698                         continue;
5699                 if (findNewline && varbuf[n] != '\n')
5700                         continue;
5701                 findNewline = false;
5702                 if (varbuf[n] == '#') {
5703                         findNewline = true;
5704                         continue;
5705                 }
5706                 if (varbuf[n] == '\n') {
5707                         if (column == 0)
5708                                 continue;
5709                         *dp++ = 0;
5710                         column = 0;
5711                         continue;
5712                 }
5713                 *dp++ = varbuf[n];
5714                 column++;
5715         }
5716         buf_len = dp - varbuf;
5717
5718         while (dp < varbuf + n)
5719                 *dp++ = 0;
5720
5721         return buf_len;
5722 }
5723
5724 /*
5725         EXAMPLE: nvram_array
5726         nvram_arry format:
5727         name=value
5728         Use carriage return at the end of each assignment,
5729          and an empty string with
5730         carriage return at the end of array.
5731
5732         For example:
5733         unsigned char  nvram_array[] = {"name1=value1\n",
5734         "name2=value2\n", "\n"};
5735         Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5736
5737         Search "EXAMPLE: nvram_array" to see how the array is activated.
5738 */
5739
5740 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5741 {
5742         bus->nvram_params = nvram_params;
5743 }
5744
5745 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5746 {
5747         int bcmerror = -1;
5748         uint len;
5749         void *image = NULL;
5750         char *memblock = NULL;
5751         char *bufp;
5752         char *nv_path;
5753         bool nvram_file_exists;
5754
5755         nv_path = bus->nv_path;
5756
5757         nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5758         if (!nvram_file_exists && (bus->nvram_params == NULL))
5759                 return 0;
5760
5761         if (nvram_file_exists) {
5762                 image = dhd_os_open_image(nv_path);
5763                 if (image == NULL)
5764                         goto err;
5765         }
5766
5767         memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5768         if (memblock == NULL) {
5769                 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5770                            __func__, MEMBLOCK));
5771                 goto err;
5772         }
5773
5774         /* Download variables */
5775         if (nvram_file_exists) {
5776                 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5777         } else {
5778                 len = strlen(bus->nvram_params);
5779                 ASSERT(len <= MEMBLOCK);
5780                 if (len > MEMBLOCK)
5781                         len = MEMBLOCK;
5782                 memcpy(memblock, bus->nvram_params, len);
5783         }
5784
5785         if (len > 0 && len < MEMBLOCK) {
5786                 bufp = (char *)memblock;
5787                 bufp[len] = 0;
5788                 len = process_nvram_vars(bufp, len);
5789                 bufp += len;
5790                 *bufp++ = 0;
5791                 if (len)
5792                         bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5793                 if (bcmerror) {
5794                         DHD_ERROR(("%s: error downloading vars: %d\n",
5795                                    __func__, bcmerror));
5796                 }
5797         } else {
5798                 DHD_ERROR(("%s: error reading nvram file: %d\n",
5799                            __func__, len));
5800                 bcmerror = -EIO;
5801         }
5802
5803 err:
5804         kfree(memblock);
5805
5806         if (image)
5807                 dhd_os_close_image(image);
5808
5809         return bcmerror;
5810 }
5811
5812 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5813 {
5814         int bcmerror = -1;
5815
5816         bool embed = false;     /* download embedded firmware */
5817         bool dlok = false;      /* download firmware succeeded */
5818
5819         /* Out immediately if no image to download */
5820         if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0'))
5821                 return bcmerror;
5822
5823         /* Keep arm in reset */
5824         if (dhdsdio_download_state(bus, true)) {
5825                 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5826                 goto err;
5827         }
5828
5829         /* External image takes precedence if specified */
5830         if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5831                 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5832                         DHD_ERROR(("%s: dongle image file download failed\n",
5833                                    __func__));
5834                         goto err;
5835                 } else {
5836                         embed = false;
5837                         dlok = true;
5838                 }
5839         }
5840         if (!dlok) {
5841                 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5842                 goto err;
5843         }
5844
5845         /* EXAMPLE: nvram_array */
5846         /* If a valid nvram_arry is specified as above, it can be passed
5847                  down to dongle */
5848         /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5849
5850         /* External nvram takes precedence if specified */
5851         if (dhdsdio_download_nvram(bus)) {
5852                 DHD_ERROR(("%s: dongle nvram file download failed\n",
5853                            __func__));
5854         }
5855
5856         /* Take arm out of reset */
5857         if (dhdsdio_download_state(bus, false)) {
5858                 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5859                            __func__));
5860                 goto err;
5861         }
5862
5863         bcmerror = 0;
5864
5865 err:
5866         return bcmerror;
5867 }
5868
5869
5870 static int
5871 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5872                     u8 *buf, uint nbytes, struct sk_buff *pkt,
5873                     bcmsdh_cmplt_fn_t complete, void *handle)
5874 {
5875         return bcmsdh_send_buf
5876                 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5877                  handle);
5878 }
5879
5880 uint dhd_bus_chip(struct dhd_bus *bus)
5881 {
5882         ASSERT(bus->ci != NULL);
5883         return bus->ci->chip;
5884 }
5885
5886 void *dhd_bus_pub(struct dhd_bus *bus)
5887 {
5888         return bus->dhd;
5889 }
5890
5891 void *dhd_bus_txq(struct dhd_bus *bus)
5892 {
5893         return &bus->txq;
5894 }
5895
5896 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5897 {
5898         return SDPCM_HDRLEN;
5899 }
5900
5901 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5902 {
5903         int bcmerror = 0;
5904         dhd_bus_t *bus;
5905
5906         bus = dhdp->bus;
5907
5908         if (flag == true) {
5909                 if (!bus->dhd->dongle_reset) {
5910                         /* Expect app to have torn down any
5911                          connection before calling */
5912                         /* Stop the bus, disable F2 */
5913                         dhd_bus_stop(bus, false);
5914
5915                         /* Clean tx/rx buffer pointers,
5916                          detach from the dongle */
5917                         dhdsdio_release_dongle(bus);
5918
5919                         bus->dhd->dongle_reset = true;
5920                         bus->dhd->up = false;
5921
5922                         DHD_TRACE(("%s:  WLAN OFF DONE\n", __func__));
5923                         /* App can now remove power from device */
5924                 } else
5925                         bcmerror = -EIO;
5926         } else {
5927                 /* App must have restored power to device before calling */
5928
5929                 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
5930
5931                 if (bus->dhd->dongle_reset) {
5932                         /* Turn on WLAN */
5933                         /* Reset SD client */
5934                         bcmsdh_reset(bus->sdh);
5935
5936                         /* Attempt to re-attach & download */
5937                         if (dhdsdio_probe_attach(bus, bus->sdh,
5938                                                  (u32 *) SI_ENUM_BASE,
5939                                                  bus->cl_devid)) {
5940                                 /* Attempt to download binary to the dongle */
5941                                 if (dhdsdio_probe_init
5942                                     (bus, bus->sdh)
5943                                     && dhdsdio_download_firmware(bus,
5944                                                                  bus->sdh)) {
5945
5946                                         /* Re-init bus, enable F2 transfer */
5947                                         dhd_bus_init((dhd_pub_t *) bus->dhd,
5948                                                      false);
5949
5950 #if defined(OOB_INTR_ONLY)
5951                                         dhd_enable_oob_intr(bus, true);
5952 #endif                          /* defined(OOB_INTR_ONLY) */
5953
5954                                         bus->dhd->dongle_reset = false;
5955                                         bus->dhd->up = true;
5956
5957                                         DHD_TRACE(("%s: WLAN ON DONE\n",
5958                                                    __func__));
5959                                 } else
5960                                         bcmerror = -EIO;
5961                         } else
5962                                 bcmerror = -EIO;
5963                 } else {
5964                         bcmerror = -EISCONN;
5965                         DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
5966                                 "is on\n", __func__));
5967                         bcmerror = -EIO;
5968                 }
5969         }
5970         return bcmerror;
5971 }
5972
5973 static int
5974 dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
5975 {
5976         u32 regdata;
5977
5978         /*
5979          * Get CC core rev
5980          * Chipid is assume to be at offset 0 from regs arg
5981          * For different chiptypes or old sdio hosts w/o chipcommon,
5982          * other ways of recognition should be added here.
5983          */
5984         ci->cccorebase = (u32)regs;
5985         regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
5986         ci->chip = regdata & CID_ID_MASK;
5987         ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
5988
5989         DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
5990                 __func__, ci->chip, ci->chiprev));
5991
5992         /* Address of cores for new chips should be added here */
5993         switch (ci->chip) {
5994         case BCM4329_CHIP_ID:
5995                 ci->buscorebase = BCM4329_CORE_BUS_BASE;
5996                 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
5997                 ci->armcorebase = BCM4329_CORE_ARM_BASE;
5998                 ci->ramsize = BCM4329_RAMSIZE;
5999                 break;
6000         default:
6001                 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6002                         __func__, ci->chip));
6003                 return -ENODEV;
6004         }
6005
6006         regdata = bcmsdh_reg_read(sdh,
6007                 CORE_SB(ci->cccorebase, sbidhigh), 4);
6008         ci->ccrev = SBCOREREV(regdata);
6009
6010         regdata = bcmsdh_reg_read(sdh,
6011                 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6012         ci->pmurev = regdata & PCAP_REV_MASK;
6013
6014         regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
6015         ci->buscorerev = SBCOREREV(regdata);
6016         ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6017
6018         DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6019                 __func__, ci->ccrev, ci->pmurev,
6020                 ci->buscorerev, ci->buscoretype));
6021
6022         /* get chipcommon capabilites */
6023         ci->cccaps = bcmsdh_reg_read(sdh,
6024                 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6025
6026         return 0;
6027 }
6028
6029 static void
6030 dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
6031 {
6032         u32 regdata;
6033
6034         regdata = bcmsdh_reg_read(sdh,
6035                 CORE_SB(corebase, sbtmstatelow), 4);
6036         if (regdata & SBTML_RESET)
6037                 return;
6038
6039         regdata = bcmsdh_reg_read(sdh,
6040                 CORE_SB(corebase, sbtmstatelow), 4);
6041         if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6042                 /*
6043                  * set target reject and spin until busy is clear
6044                  * (preserve core-specific bits)
6045                  */
6046                 regdata = bcmsdh_reg_read(sdh,
6047                         CORE_SB(corebase, sbtmstatelow), 4);
6048                 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6049                         regdata | SBTML_REJ);
6050
6051                 regdata = bcmsdh_reg_read(sdh,
6052                         CORE_SB(corebase, sbtmstatelow), 4);
6053                 udelay(1);
6054                 SPINWAIT((bcmsdh_reg_read(sdh,
6055                         CORE_SB(corebase, sbtmstatehigh), 4) &
6056                         SBTMH_BUSY), 100000);
6057
6058                 regdata = bcmsdh_reg_read(sdh,
6059                         CORE_SB(corebase, sbtmstatehigh), 4);
6060                 if (regdata & SBTMH_BUSY)
6061                         DHD_ERROR(("%s: ARM core still busy\n", __func__));
6062
6063                 regdata = bcmsdh_reg_read(sdh,
6064                         CORE_SB(corebase, sbidlow), 4);
6065                 if (regdata & SBIDL_INIT) {
6066                         regdata = bcmsdh_reg_read(sdh,
6067                                 CORE_SB(corebase, sbimstate), 4) |
6068                                 SBIM_RJ;
6069                         bcmsdh_reg_write(sdh,
6070                                 CORE_SB(corebase, sbimstate), 4,
6071                                 regdata);
6072                         regdata = bcmsdh_reg_read(sdh,
6073                                 CORE_SB(corebase, sbimstate), 4);
6074                         udelay(1);
6075                         SPINWAIT((bcmsdh_reg_read(sdh,
6076                                 CORE_SB(corebase, sbimstate), 4) &
6077                                 SBIM_BY), 100000);
6078                 }
6079
6080                 /* set reset and reject while enabling the clocks */
6081                 bcmsdh_reg_write(sdh,
6082                         CORE_SB(corebase, sbtmstatelow), 4,
6083                         (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6084                         SBTML_REJ | SBTML_RESET));
6085                 regdata = bcmsdh_reg_read(sdh,
6086                         CORE_SB(corebase, sbtmstatelow), 4);
6087                 udelay(10);
6088
6089                 /* clear the initiator reject bit */
6090                 regdata = bcmsdh_reg_read(sdh,
6091                         CORE_SB(corebase, sbidlow), 4);
6092                 if (regdata & SBIDL_INIT) {
6093                         regdata = bcmsdh_reg_read(sdh,
6094                                 CORE_SB(corebase, sbimstate), 4) &
6095                                 ~SBIM_RJ;
6096                         bcmsdh_reg_write(sdh,
6097                                 CORE_SB(corebase, sbimstate), 4,
6098                                 regdata);
6099                 }
6100         }
6101
6102         /* leave reset and reject asserted */
6103         bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6104                 (SBTML_REJ | SBTML_RESET));
6105         udelay(1);
6106 }
6107
6108 static int
6109 dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
6110 {
6111         struct chip_info *ci;
6112         int err;
6113         u8 clkval, clkset;
6114
6115         DHD_TRACE(("%s: Enter\n", __func__));
6116
6117         /* alloc chip_info_t */
6118         ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6119         if (NULL == ci) {
6120                 DHD_ERROR(("%s: malloc failed!\n", __func__));
6121                 return -ENOMEM;
6122         }
6123
6124         memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6125
6126         /* bus/core/clk setup for register access */
6127         /* Try forcing SDIO core to do ALPAvail request only */
6128         clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6129         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6130                         clkset, &err);
6131         if (err) {
6132                 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6133                 goto fail;
6134         }
6135
6136         /* If register supported, wait for ALPAvail and then force ALP */
6137         /* This may take up to 15 milliseconds */
6138         clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6139                         SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6140         if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6141                 SPINWAIT(((clkval =
6142                                 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6143                                                 SBSDIO_FUNC1_CHIPCLKCSR,
6144                                                 NULL)),
6145                                 !SBSDIO_ALPAV(clkval)),
6146                                 PMU_MAX_TRANSITION_DLY);
6147                 if (!SBSDIO_ALPAV(clkval)) {
6148                         DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6149                                 __func__, clkval));
6150                         err = -EBUSY;
6151                         goto fail;
6152                 }
6153                 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6154                                 SBSDIO_FORCE_ALP;
6155                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
6156                                 SBSDIO_FUNC1_CHIPCLKCSR,
6157                                 clkset, &err);
6158                 udelay(65);
6159         } else {
6160                 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6161                         __func__, clkset, clkval));
6162                 err = -EACCES;
6163                 goto fail;
6164         }
6165
6166         /* Also, disable the extra SDIO pull-ups */
6167         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
6168                          NULL);
6169
6170         err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
6171         if (err)
6172                 goto fail;
6173
6174         /*
6175          * Make sure any on-chip ARM is off (in case strapping is wrong),
6176          * or downloaded code was already running.
6177          */
6178         dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
6179
6180         bcmsdh_reg_write(bus->sdh,
6181                 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6182         bcmsdh_reg_write(bus->sdh,
6183                 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6184
6185         /* Disable F2 to clear any intermediate frame state on the dongle */
6186         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
6187                 SDIO_FUNC_ENABLE_1, NULL);
6188
6189         /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6190         clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6191                         0, NULL);
6192
6193         /* Done with backplane-dependent accesses, can drop clock... */
6194         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
6195                          NULL);
6196
6197         bus->ci = ci;
6198         return 0;
6199 fail:
6200         bus->ci = NULL;
6201         kfree(ci);
6202         return err;
6203 }
6204
6205 static void
6206 dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
6207 {
6208         u32 regdata;
6209
6210         /*
6211          * Must do the disable sequence first to work for
6212          * arbitrary current core state.
6213          */
6214         dhdsdio_chip_disablecore(sdh, corebase);
6215
6216         /*
6217          * Now do the initialization sequence.
6218          * set reset while enabling the clock and
6219          * forcing them on throughout the core
6220          */
6221         bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6222                 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6223                 SBTML_RESET);
6224         udelay(1);
6225
6226         regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
6227         if (regdata & SBTMH_SERR)
6228                 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
6229
6230         regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6231         if (regdata & (SBIM_IBE | SBIM_TO))
6232                 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6233                         regdata & ~(SBIM_IBE | SBIM_TO));
6234
6235         /* clear reset and allow it to propagate throughout the core */
6236         bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6237                 (SICF_FGC << SBTML_SICF_SHIFT) |
6238                 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6239         udelay(1);
6240
6241         /* leave clock enabled */
6242         bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6243                 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6244         udelay(1);
6245 }
6246
6247 /* SDIO Pad drive strength to select value mappings */
6248 struct sdiod_drive_str {
6249         u8 strength;    /* Pad Drive Strength in mA */
6250         u8 sel;         /* Chip-specific select value */
6251 };
6252
6253 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6254 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6255         {
6256         4, 0x2}, {
6257         2, 0x3}, {
6258         1, 0x0}, {
6259         0, 0x0}
6260         };
6261
6262 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6263 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6264         {
6265         12, 0x7}, {
6266         10, 0x6}, {
6267         8, 0x5}, {
6268         6, 0x4}, {
6269         4, 0x2}, {
6270         2, 0x1}, {
6271         0, 0x0}
6272         };
6273
6274 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6275 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6276         {
6277         32, 0x7}, {
6278         26, 0x6}, {
6279         22, 0x5}, {
6280         16, 0x4}, {
6281         12, 0x3}, {
6282         8, 0x2}, {
6283         4, 0x1}, {
6284         0, 0x0}
6285         };
6286
6287 #define SDIOD_DRVSTR_KEY(chip, pmu)     (((chip) << 16) | (pmu))
6288
6289 static void
6290 dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6291         struct sdiod_drive_str *str_tab = NULL;
6292         u32 str_mask = 0;
6293         u32 str_shift = 0;
6294         char chn[8];
6295
6296         if (!(bus->ci->cccaps & CC_CAP_PMU))
6297                 return;
6298
6299         switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6300         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6301                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6302                 str_mask = 0x30000000;
6303                 str_shift = 28;
6304                 break;
6305         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6306         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6307                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6308                 str_mask = 0x00003800;
6309                 str_shift = 11;
6310                 break;
6311         case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6312                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6313                 str_mask = 0x00003800;
6314                 str_shift = 11;
6315                 break;
6316         default:
6317                 DHD_ERROR(("No SDIO Drive strength init"
6318                         "done for chip %s rev %d pmurev %d\n",
6319                         bcm_chipname(bus->ci->chip, chn, 8),
6320                         bus->ci->chiprev, bus->ci->pmurev));
6321                 break;
6322         }
6323
6324         if (str_tab != NULL) {
6325                 u32 drivestrength_sel = 0;
6326                 u32 cc_data_temp;
6327                 int i;
6328
6329                 for (i = 0; str_tab[i].strength != 0; i++) {
6330                         if (drivestrength >= str_tab[i].strength) {
6331                                 drivestrength_sel = str_tab[i].sel;
6332                                 break;
6333                         }
6334                 }
6335
6336                 bcmsdh_reg_write(bus->sdh,
6337                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6338                         4, 1);
6339                 cc_data_temp = bcmsdh_reg_read(bus->sdh,
6340                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6341                 cc_data_temp &= ~str_mask;
6342                 drivestrength_sel <<= str_shift;
6343                 cc_data_temp |= drivestrength_sel;
6344                 bcmsdh_reg_write(bus->sdh,
6345                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6346                         4, cc_data_temp);
6347
6348                 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6349                         drivestrength, cc_data_temp));
6350         }
6351 }
6352
6353 static void
6354 dhdsdio_chip_detach(struct dhd_bus *bus)
6355 {
6356         DHD_TRACE(("%s: Enter\n", __func__));
6357
6358         kfree(bus->ci);
6359         bus->ci = NULL;
6360 }