2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/printk.h>
20 #include <linux/pci_ids.h>
21 #include <linux/netdevice.h>
26 #include BCMEMBEDIMAGE
27 #endif /* BCMEMBEDIMAGE */
36 /* ARM trap handling */
38 /* Trap types defined by ARM (see arminc.h) */
40 /* Trap locations in lo memory */
42 #define FIRST_TRAP TR_RST
43 #define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
45 #if defined(__ARM_ARCH_4T__)
46 #define MAX_TRAP_TYPE (TR_FIQ + 1)
47 #elif defined(__ARM_ARCH_7M__)
48 #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
49 #endif /* __ARM_ARCH_7M__ */
51 /* The trap structure is defined here as offsets for assembly */
57 #define TR_REG(n) (TR_REGS + (n) * 4)
58 #define TR_SP TR_REG(13)
59 #define TR_LR TR_REG(14)
60 #define TR_PC TR_REG(15)
62 #define TRAP_T_SIZE 80
64 typedef struct _trap_struct {
87 #define CBUF_LEN (128)
89 #define LOG_BUF_LEN 1024
92 u32 buf; /* Can't be pointer on (64-bit) hosts */
95 char *_buf_compat; /* Redundant pointer for backward compat. */
100 * When there is no UART (e.g. Quickturn),
101 * the host should write a complete
102 * input line directly into cbuf and then write
103 * the length into vcons_in.
104 * This may also be used when there is a real UART
105 * (at risk of conflicting with
106 * the real UART). vcons_out is currently unused.
108 volatile uint vcons_in;
109 volatile uint vcons_out;
111 /* Output (logging) buffer
112 * Console output is written to a ring buffer log_buf at index log_idx.
113 * The host may read the output when it sees log_idx advance.
114 * Output will be lost if the output wraps around faster than the host
119 /* Console input line buffer
120 * Characters are read one at a time into cbuf
121 * until <CR> is received, then
122 * the buffer is processed as a command line.
123 * Also used for virtual UART.
129 #endif /* DHD_DEBUG */
130 #include <chipcommon.h>
134 #include <sbsdpcmdev.h>
135 #include <bcmsdpcm.h>
137 #include <dngl_stats.h>
140 #include <dhd_proto.h>
145 #ifndef DHDSDIO_MEM_DUMP_FNAME
146 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
149 #define TXQLEN 2048 /* bulk tx queue length */
150 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
151 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
154 #define TXRETRIES 2 /* # of retries for tx frames */
156 #if defined(CONFIG_MACH_SANDGATE2G)
157 #define DHD_RXBOUND 250 /* Default for max rx frames in
160 #define DHD_RXBOUND 50 /* Default for max rx frames in
162 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
164 #define DHD_TXBOUND 20 /* Default for max tx frames in
167 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
169 #define MEMBLOCK 2048 /* Block size used for downloading
171 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
172 biggest possible glom */
174 /* Packet alignment for most efficient SDIO (can change based on platform) */
176 #define DHD_SDALIGN 32
178 #if !ISPOWEROF2(DHD_SDALIGN)
179 #error DHD_SDALIGN is not a power of 2!
182 #ifndef DHD_FIRSTREAD
183 #define DHD_FIRSTREAD 32
185 #if !ISPOWEROF2(DHD_FIRSTREAD)
186 #error DHD_FIRSTREAD is not a power of 2!
189 /* Total length of frame header for dongle protocol */
190 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
192 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
194 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
197 /* Space for header read, limit for data packets */
199 #define MAX_HDR_READ 32
201 #if !ISPOWEROF2(MAX_HDR_READ)
202 #error MAX_HDR_READ is not a power of 2!
205 #define MAX_RX_DATASZ 2048
207 /* Maximum milliseconds to wait for F2 to come up */
208 #define DHD_WAIT_F2RDY 3000
210 /* Bump up limit on waiting for HT to account for first startup;
211 * if the image is doing a CRC calculation before programming the PMU
212 * for HT availability, it could take a couple hundred ms more, so
213 * max out at a 1 second (1000000us).
215 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
216 #undef PMU_MAX_TRANSITION_DLY
217 #define PMU_MAX_TRANSITION_DLY 1000000
220 /* Value for ChipClockCSR during initial setup */
221 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
222 SBSDIO_ALP_AVAIL_REQ)
223 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
225 /* Flags for SDH calls */
226 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
229 #define SBIM_IBE 0x20000 /* inbanderror */
230 #define SBIM_TO 0x40000 /* timeout */
231 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
232 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
235 #define SBTML_RESET 0x0001 /* reset */
236 #define SBTML_REJ_MASK 0x0006 /* reject field */
237 #define SBTML_REJ 0x0002 /* reject */
238 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
240 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
243 #define SBTMH_SERR 0x0001 /* serror */
244 #define SBTMH_INT 0x0002 /* interrupt */
245 #define SBTMH_BUSY 0x0004 /* busy */
246 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
248 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
251 #define SBIDL_INIT 0x80 /* initiator */
254 #define SBIDH_RC_MASK 0x000f /* revision code */
255 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
256 #define SBIDH_RCE_SHIFT 8
257 #define SBCOREREV(sbidh) \
258 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
259 #define SBIDH_CC_MASK 0x8ff0 /* core code */
260 #define SBIDH_CC_SHIFT 4
261 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
262 #define SBIDH_VC_SHIFT 16
265 * Conversion of 802.1D priority to precedence level
267 #define PRIO2PREC(prio) \
268 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
271 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
272 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
275 /* Core reg address translation */
276 #define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
277 #define CORE_BUS_REG(base, field) (base + offsetof(sdpcmd_regs_t, field))
278 #define CORE_SB(base, field) \
279 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
282 /* Device console log buffer state */
283 typedef struct dhd_console {
284 uint count; /* Poll interval msec counter */
285 uint log_addr; /* Log struct address (fixed) */
286 rte_log_t log; /* Log struct (host copy) */
287 uint bufsize; /* Size of log buffer */
288 u8 *buf; /* Log buffer (host copy) */
289 uint last; /* Last buffer read index */
291 #endif /* DHD_DEBUG */
293 /* misc chip info needed by some of the routines */
309 /* Private data for SDIO bus interaction */
310 typedef struct dhd_bus {
313 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
314 struct chip_info *ci; /* Chip info struct */
315 char *vars; /* Variables (from CIS and/or other) */
316 uint varsz; /* Size of variables buffer */
317 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
319 sdpcmd_regs_t *regs; /* Registers for SDIO core */
320 uint sdpcmrev; /* SDIO core revision */
321 uint armrev; /* CPU core revision */
322 uint ramrev; /* SOCRAM core revision */
323 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
324 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
326 u32 bus; /* gSPI or SDIO bus */
327 u32 hostintmask; /* Copy of Host Interrupt Mask */
328 u32 intstatus; /* Intstatus bits (events) pending */
329 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
330 bool fcstate; /* State of dongle flow-control */
332 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
333 char *fw_path; /* module_param: path to firmware image */
334 char *nv_path; /* module_param: path to nvram vars file */
335 const char *nvram_params; /* user specified nvram params. */
337 uint blocksize; /* Block size of SDIO transfers */
338 uint roundup; /* Max roundup limit */
340 struct pktq txq; /* Queue length used for flow-control */
341 u8 flowcontrol; /* per prio flow control bitmask */
342 u8 tx_seq; /* Transmit sequence number (next) */
343 u8 tx_max; /* Maximum transmit sequence allowed */
345 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
346 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
347 u16 nextlen; /* Next Read Len from last header */
348 u8 rx_seq; /* Receive sequence number (expected) */
349 bool rxskip; /* Skip receive (awaiting NAK ACK) */
351 struct sk_buff *glomd; /* Packet containing glomming descriptor */
352 struct sk_buff *glom; /* Packet chain for glommed superframe */
353 uint glomerr; /* Glom packet read errors */
355 u8 *rxbuf; /* Buffer for receiving control packets */
356 uint rxblen; /* Allocated length of rxbuf */
357 u8 *rxctl; /* Aligned pointer into rxbuf */
358 u8 *databuf; /* Buffer for receiving big glom packet */
359 u8 *dataptr; /* Aligned pointer into databuf */
360 uint rxlen; /* Length of valid data in buffer */
362 u8 sdpcm_ver; /* Bus protocol reported by dongle */
364 bool intr; /* Use interrupts */
365 bool poll; /* Use polling */
366 bool ipend; /* Device interrupt is pending */
367 bool intdis; /* Interrupts disabled by isr */
368 uint intrcount; /* Count of device interrupt callbacks */
369 uint lastintrs; /* Count as of last watchdog timer */
370 uint spurious; /* Count of spurious interrupts */
371 uint pollrate; /* Ticks between device polls */
372 uint polltick; /* Tick counter */
373 uint pollcnt; /* Count of active polls */
376 dhd_console_t console; /* Console output polling support */
377 uint console_addr; /* Console address from shared struct */
378 #endif /* DHD_DEBUG */
380 uint regfails; /* Count of R_REG/W_REG failures */
382 uint clkstate; /* State of sd and backplane clock(s) */
383 bool activity; /* Activity flag for clock down */
384 s32 idletime; /* Control for activity timeout */
385 s32 idlecount; /* Activity timeout counter */
386 s32 idleclock; /* How to set bus driver when idle */
387 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
388 bool use_rxchain; /* If dhd should use PKT chains */
389 bool sleeping; /* Is SDIO bus sleeping? */
390 bool rxflow_mode; /* Rx flow control mode */
391 bool rxflow; /* Is rx flow control on */
392 uint prev_rxlim_hit; /* Is prev rx limit exceeded
393 (per dpc schedule) */
394 bool alp_only; /* Don't use HT clock (ALP only) */
395 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
399 /* external loopback */
403 /* pktgen configuration */
404 uint pktgen_freq; /* Ticks between bursts */
405 uint pktgen_count; /* Packets to send each burst */
406 uint pktgen_print; /* Bursts between count displays */
407 uint pktgen_total; /* Stop after this many */
408 uint pktgen_minlen; /* Minimum packet data len */
409 uint pktgen_maxlen; /* Maximum packet data len */
410 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
411 uint pktgen_stop; /* Number of tx failures causing stop */
413 /* active pktgen fields */
414 uint pktgen_tick; /* Tick counter for bursts */
415 uint pktgen_ptick; /* Burst counter for printing */
416 uint pktgen_sent; /* Number of test packets generated */
417 uint pktgen_rcvd; /* Number of test packets received */
418 uint pktgen_fail; /* Number of failed send attempts */
419 u16 pktgen_len; /* Length of next packet to send */
422 /* Some additional counters */
423 uint tx_sderrs; /* Count of tx attempts with sd errors */
424 uint fcqueued; /* Tx packets that got queued */
425 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
426 uint rx_toolong; /* Receive frames too long to receive */
427 uint rxc_errors; /* SDIO errors when reading control frames */
428 uint rx_hdrfail; /* SDIO errors on header reads */
429 uint rx_badhdr; /* Bad received headers (roosync?) */
430 uint rx_badseq; /* Mismatched rx sequence number */
431 uint fc_rcvd; /* Number of flow-control events received */
432 uint fc_xoff; /* Number which turned on flow-control */
433 uint fc_xon; /* Number which turned off flow-control */
434 uint rxglomfail; /* Failed deglom attempts */
435 uint rxglomframes; /* Number of glom frames (superframes) */
436 uint rxglompkts; /* Number of packets from glom frames */
437 uint f2rxhdrs; /* Number of header reads */
438 uint f2rxdata; /* Number of frame data reads */
439 uint f2txdata; /* Number of f2 frame writes */
440 uint f1regdata; /* Number of f1 register accesses */
444 bool ctrl_frame_stat;
447 typedef volatile struct _sbconfig {
449 u32 sbipsflag; /* initiator port ocp slave flag */
451 u32 sbtpsflag; /* target port ocp slave flag */
453 u32 sbtmerrloga; /* (sonics >= 2.3) */
455 u32 sbtmerrlog; /* (sonics >= 2.3) */
457 u32 sbadmatch3; /* address match3 */
459 u32 sbadmatch2; /* address match2 */
461 u32 sbadmatch1; /* address match1 */
463 u32 sbimstate; /* initiator agent state */
464 u32 sbintvec; /* interrupt mask */
465 u32 sbtmstatelow; /* target state */
466 u32 sbtmstatehigh; /* target state */
467 u32 sbbwa0; /* bandwidth allocation table0 */
469 u32 sbimconfiglow; /* initiator configuration */
470 u32 sbimconfighigh; /* initiator configuration */
471 u32 sbadmatch0; /* address match0 */
473 u32 sbtmconfiglow; /* target configuration */
474 u32 sbtmconfighigh; /* target configuration */
475 u32 sbbconfig; /* broadcast configuration */
477 u32 sbbstate; /* broadcast state */
479 u32 sbactcnfg; /* activate configuration */
481 u32 sbflagst; /* current sbflags */
483 u32 sbidlow; /* identification */
484 u32 sbidhigh; /* identification */
490 #define CLK_PENDING 2 /* Not used yet */
493 #define DHD_NOPMU(dhd) (false)
496 static int qcount[NUMPRIO];
497 static int tx_packets[NUMPRIO];
498 #endif /* DHD_DEBUG */
500 /* Deferred transmit */
501 const uint dhd_deferred_tx = 1;
503 extern uint dhd_watchdog_ms;
504 extern void dhd_os_wd_timer(void *bus, uint wdtick);
511 /* override the RAM size if possible */
512 #define DONGLE_MIN_MEMSIZE (128 * 1024)
513 int dhd_dongle_memsize;
515 static bool dhd_alignctl;
519 static bool retrydata;
520 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
522 static const uint watermark = 8;
523 static const uint firstread = DHD_FIRSTREAD;
525 #define HDATLEN (firstread - (SDPCM_HDRLEN))
527 /* Retry count for register access failures */
528 static const uint retry_limit = 2;
530 /* Force even SD lengths (some host controllers mess up on odd bytes) */
531 static bool forcealign;
535 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
536 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
539 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
540 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
541 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
542 #define PKTALIGN(_p, _len, _align) \
545 datalign = (unsigned long)((_p)->data); \
546 datalign = roundup(datalign, (_align)) - datalign; \
547 ASSERT(datalign < (_align)); \
548 ASSERT((_p)->len >= ((_len) + datalign)); \
550 skb_pull((_p), datalign); \
551 __skb_trim((_p), (_len)); \
554 /* Limit on rounding up frames */
555 static const uint max_roundup = 512;
557 /* Try doing readahead */
558 static bool dhd_readahead;
560 /* To check if there's window offered */
561 #define DATAOK(bus) \
562 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
563 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
565 /* Macros to get register read/write status */
566 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
567 #define R_SDREG(regvar, regaddr, retryvar) \
571 regvar = R_REG(regaddr); \
572 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
574 bus->regfails += (retryvar-1); \
575 if (retryvar > retry_limit) { \
576 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
577 __func__, __LINE__)); \
583 #define W_SDREG(regval, regaddr, retryvar) \
587 W_REG(regaddr, regval); \
588 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
590 bus->regfails += (retryvar-1); \
591 if (retryvar > retry_limit) \
592 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
593 __func__, __LINE__)); \
597 #define DHD_BUS SDIO_BUS
599 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
601 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
604 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
605 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
609 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
610 static int dhdsdio_mem_dump(dhd_bus_t *bus);
611 #endif /* DHD_DEBUG */
612 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
614 static void dhdsdio_release(dhd_bus_t *bus);
615 static void dhdsdio_release_malloc(dhd_bus_t *bus);
616 static void dhdsdio_disconnect(void *ptr);
617 static bool dhdsdio_chipmatch(u16 chipid);
618 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
619 void *regsva, u16 devid);
620 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
621 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
622 static void dhdsdio_release_dongle(dhd_bus_t *bus);
624 static uint process_nvram_vars(char *varbuf, uint len);
626 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
627 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
628 uint flags, u8 *buf, uint nbytes,
629 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
632 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
633 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
635 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
636 static int dhdsdio_download_nvram(struct dhd_bus *bus);
638 static int dhdsdio_download_code_array(struct dhd_bus *bus);
640 static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
641 static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
642 static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
643 static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
645 static void dhdsdio_chip_detach(struct dhd_bus *bus);
647 /* Packet free applicable unconditionally for sdio and sdspi.
648 * Conditional if bufpool was present for gspi bus.
650 static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
652 dhd_os_sdlock_rxq(bus->dhd);
653 if ((bus->bus != SPI_BUS) || bus->usebufpool)
654 bcm_pkt_buf_free_skb(pkt);
655 dhd_os_sdunlock_rxq(bus->dhd);
658 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
660 s32 min_size = DONGLE_MIN_MEMSIZE;
661 /* Restrict the memsize to user specified limit */
662 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
663 dhd_dongle_memsize, min_size));
664 if ((dhd_dongle_memsize > min_size) &&
665 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
666 bus->ramsize = dhd_dongle_memsize;
669 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
672 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
673 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
675 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
676 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
678 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
679 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
684 /* Turn backplane clock on or off */
685 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
688 u8 clkctl, clkreq, devctl;
691 DHD_TRACE(("%s: Enter\n", __func__));
693 #if defined(OOB_INTR_ONLY)
700 /* Request HT Avail */
702 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
704 if ((bus->ci->chip == BCM4329_CHIP_ID)
705 && (bus->ci->chiprev == 0))
706 clkreq |= SBSDIO_FORCE_ALP;
708 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
711 DHD_ERROR(("%s: HT Avail request error: %d\n",
716 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
717 && (bus->ci->buscorerev == 9))) {
719 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
722 /* Check current status */
724 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
727 DHD_ERROR(("%s: HT Avail read error: %d\n",
732 /* Go to pending and await interrupt if appropriate */
733 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
734 /* Allow only clock-available interrupt */
736 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
739 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
744 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
745 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
747 DHD_INFO(("CLKCTL: set PENDING\n"));
748 bus->clkstate = CLK_PENDING;
751 } else if (bus->clkstate == CLK_PENDING) {
752 /* Cancel CA-only interrupt filter */
754 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
756 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
757 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
761 /* Otherwise, wait here (polling) for HT Avail */
762 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
763 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
765 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
766 SBSDIO_FUNC1_CHIPCLKCSR,
768 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
769 PMU_MAX_TRANSITION_DLY);
772 DHD_ERROR(("%s: HT Avail request error: %d\n",
776 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
777 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
778 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
782 /* Mark clock available */
783 bus->clkstate = CLK_AVAIL;
784 DHD_INFO(("CLKCTL: turned ON\n"));
786 #if defined(DHD_DEBUG)
787 if (bus->alp_only == true) {
788 #if !defined(BCMLXSDMMC)
789 if (!SBSDIO_ALPONLY(clkctl)) {
790 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
793 #endif /* !defined(BCMLXSDMMC) */
795 if (SBSDIO_ALPONLY(clkctl)) {
796 DHD_ERROR(("%s: HT Clock should be on.\n",
800 #endif /* defined (DHD_DEBUG) */
802 bus->activity = true;
806 if (bus->clkstate == CLK_PENDING) {
807 /* Cancel CA-only interrupt filter */
809 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
811 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
812 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
816 bus->clkstate = CLK_SDONLY;
817 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
819 DHD_INFO(("CLKCTL: turned OFF\n"));
821 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
829 /* Change idle/active SD state */
830 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
832 DHD_TRACE(("%s: Enter\n", __func__));
835 bus->clkstate = CLK_SDONLY;
837 bus->clkstate = CLK_NONE;
842 /* Transition SD and backplane clock readiness */
843 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
846 uint oldstate = bus->clkstate;
847 #endif /* DHD_DEBUG */
849 DHD_TRACE(("%s: Enter\n", __func__));
851 /* Early exit if we're already there */
852 if (bus->clkstate == target) {
853 if (target == CLK_AVAIL) {
854 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
855 bus->activity = true;
862 /* Make sure SD clock is available */
863 if (bus->clkstate == CLK_NONE)
864 dhdsdio_sdclk(bus, true);
865 /* Now request HT Avail on the backplane */
866 dhdsdio_htclk(bus, true, pendok);
867 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
868 bus->activity = true;
872 /* Remove HT request, or bring up SD clock */
873 if (bus->clkstate == CLK_NONE)
874 dhdsdio_sdclk(bus, true);
875 else if (bus->clkstate == CLK_AVAIL)
876 dhdsdio_htclk(bus, false, false);
878 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
879 bus->clkstate, target));
880 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
884 /* Make sure to remove HT request */
885 if (bus->clkstate == CLK_AVAIL)
886 dhdsdio_htclk(bus, false, false);
887 /* Now remove the SD clock */
888 dhdsdio_sdclk(bus, false);
889 dhd_os_wd_timer(bus->dhd, 0);
893 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
894 #endif /* DHD_DEBUG */
899 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
901 bcmsdh_info_t *sdh = bus->sdh;
902 sdpcmd_regs_t *regs = bus->regs;
905 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
906 (sleep ? "SLEEP" : "WAKE"),
907 (bus->sleeping ? "SLEEP" : "WAKE")));
909 /* Done if we're already in the requested state */
910 if (sleep == bus->sleeping)
913 /* Going to sleep: set the alarm and turn off the lights... */
915 /* Don't sleep if something is pending */
916 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
919 /* Disable SDIO interrupts (no longer interested) */
920 bcmsdh_intr_disable(bus->sdh);
922 /* Make sure the controller has the bus up */
923 dhdsdio_clkctl(bus, CLK_AVAIL, false);
925 /* Tell device to start using OOB wakeup */
926 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
927 if (retries > retry_limit)
928 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
930 /* Turn off our contribution to the HT clock request */
931 dhdsdio_clkctl(bus, CLK_SDONLY, false);
933 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
934 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
936 /* Isolate the bus */
937 if (bus->ci->chip != BCM4329_CHIP_ID
938 && bus->ci->chip != BCM4319_CHIP_ID) {
939 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
940 SBSDIO_DEVCTL_PADS_ISO, NULL);
944 bus->sleeping = true;
947 /* Waking up: bus power up is ok, set local state */
949 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
952 /* Force pad isolation off if possible
953 (in case power never toggled) */
954 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
955 && (bus->ci->buscorerev >= 10))
956 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
959 /* Make sure the controller has the bus up */
960 dhdsdio_clkctl(bus, CLK_AVAIL, false);
962 /* Send misc interrupt to indicate OOB not needed */
963 W_SDREG(0, ®s->tosbmailboxdata, retries);
964 if (retries <= retry_limit)
965 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
967 if (retries > retry_limit)
968 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
970 /* Make sure we have SD bus access */
971 dhdsdio_clkctl(bus, CLK_SDONLY, false);
974 bus->sleeping = false;
976 /* Enable interrupts again */
977 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
979 bcmsdh_intr_enable(bus->sdh);
986 #if defined(OOB_INTR_ONLY)
987 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
990 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
992 sdpcmd_regs_t *regs = bus->regs;
995 dhdsdio_clkctl(bus, CLK_AVAIL, false);
996 if (enable == true) {
998 /* Tell device to start using OOB wakeup */
999 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1000 if (retries > retry_limit)
1001 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1004 /* Send misc interrupt to indicate OOB not needed */
1005 W_SDREG(0, ®s->tosbmailboxdata, retries);
1006 if (retries <= retry_limit)
1007 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1010 /* Turn off our contribution to the HT clock request */
1011 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1012 #endif /* !defined(HW_OOB) */
1014 #endif /* defined(OOB_INTR_ONLY) */
1016 #define BUS_WAKE(bus) \
1018 if ((bus)->sleeping) \
1019 dhdsdio_bussleep((bus), false); \
1022 /* Writes a HW/SW header into the packet and sends it. */
1023 /* Assumes: (a) header space already there, (b) caller holds lock */
1024 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1033 struct sk_buff *new;
1036 DHD_TRACE(("%s: Enter\n", __func__));
1040 if (bus->dhd->dongle_reset) {
1045 frame = (u8 *) (pkt->data);
1047 /* Add alignment padding, allocate new packet if needed */
1048 pad = ((unsigned long)frame % DHD_SDALIGN);
1050 if (skb_headroom(pkt) < pad) {
1051 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1052 __func__, skb_headroom(pkt), pad));
1053 bus->dhd->tx_realloc++;
1054 new = bcm_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1056 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1058 __func__, pkt->len + DHD_SDALIGN));
1063 PKTALIGN(new, pkt->len, DHD_SDALIGN);
1064 memcpy(new->data, pkt->data, pkt->len);
1066 bcm_pkt_buf_free_skb(pkt);
1067 /* free the pkt if canned one is not used */
1070 frame = (u8 *) (pkt->data);
1071 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1075 frame = (u8 *) (pkt->data);
1077 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1078 memset(frame, 0, pad + SDPCM_HDRLEN);
1081 ASSERT(pad < DHD_SDALIGN);
1083 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1084 len = (u16) (pkt->len);
1085 *(u16 *) frame = cpu_to_le16(len);
1086 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1088 /* Software tag: channel, sequence number, data offset */
1090 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1092 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1094 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1095 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1098 tx_packets[pkt->priority]++;
1099 if (DHD_BYTES_ON() &&
1100 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1101 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1102 printk(KERN_DEBUG "Tx Frame:\n");
1103 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1104 } else if (DHD_HDRS_ON()) {
1105 printk(KERN_DEBUG "TxHdr:\n");
1106 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1107 frame, min_t(u16, len, 16));
1111 /* Raise len to next SDIO block to eliminate tail command */
1112 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1113 u16 pad = bus->blocksize - (len % bus->blocksize);
1114 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1116 if (pad <= skb_tailroom(pkt))
1117 #endif /* NOTUSED */
1119 } else if (len % DHD_SDALIGN) {
1120 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1123 /* Some controllers have trouble with odd bytes -- round to even */
1124 if (forcealign && (len & (ALIGNMENT - 1))) {
1126 if (skb_tailroom(pkt))
1128 len = roundup(len, ALIGNMENT);
1131 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1138 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1139 F2SYNC, frame, len, pkt, NULL, NULL);
1141 ASSERT(ret != -BCME_PENDING);
1144 /* On failure, abort the command
1145 and terminate the frame */
1146 DHD_INFO(("%s: sdio error %d, abort command and "
1147 "terminate frame.\n", __func__, ret));
1150 bcmsdh_abort(sdh, SDIO_FUNC_2);
1151 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1152 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1156 for (i = 0; i < 3; i++) {
1158 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1159 SBSDIO_FUNC1_WFRAMEBCHI,
1161 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1162 SBSDIO_FUNC1_WFRAMEBCLO,
1164 bus->f1regdata += 2;
1165 if ((hi == 0) && (lo == 0))
1171 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1173 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1176 /* restore pkt buffer pointer before calling tx complete routine */
1177 skb_pull(pkt, SDPCM_HDRLEN + pad);
1178 dhd_os_sdunlock(bus->dhd);
1179 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1180 dhd_os_sdlock(bus->dhd);
1183 bcm_pkt_buf_free_skb(pkt);
1188 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1193 DHD_TRACE(("%s: Enter\n", __func__));
1198 /* Push the test header if doing loopback */
1199 if (bus->ext_loop) {
1201 skb_push(pkt, SDPCM_TEST_HDRLEN);
1203 *data++ = SDPCM_TEST_ECHOREQ;
1204 *data++ = (u8) bus->loopid++;
1205 *data++ = (datalen >> 0);
1206 *data++ = (datalen >> 8);
1207 datalen += SDPCM_TEST_HDRLEN;
1211 /* Add space for the header */
1212 skb_push(pkt, SDPCM_HDRLEN);
1213 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1215 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1217 /* Check for existing queue, current flow-control,
1218 pending event, or pending clock */
1219 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1220 || bus->dpc_sched || (!DATAOK(bus))
1221 || (bus->flowcontrol & NBITVAL(prec))
1222 || (bus->clkstate != CLK_AVAIL)) {
1223 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1224 pktq_len(&bus->txq)));
1227 /* Priority based enq */
1228 dhd_os_sdlock_txq(bus->dhd);
1229 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1230 skb_pull(pkt, SDPCM_HDRLEN);
1231 dhd_txcomplete(bus->dhd, pkt, false);
1232 bcm_pkt_buf_free_skb(pkt);
1233 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1238 dhd_os_sdunlock_txq(bus->dhd);
1240 if (pktq_len(&bus->txq) >= TXHI)
1241 dhd_txflowcontrol(bus->dhd, 0, ON);
1244 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1245 qcount[prec] = pktq_plen(&bus->txq, prec);
1247 /* Schedule DPC if needed to send queued packet(s) */
1248 if (dhd_deferred_tx && !bus->dpc_sched) {
1249 bus->dpc_sched = true;
1250 dhd_sched_dpc(bus->dhd);
1253 /* Lock: we're about to use shared data/code (and SDIO) */
1254 dhd_os_sdlock(bus->dhd);
1256 /* Otherwise, send it now */
1258 /* Make sure back plane ht clk is on, no pending allowed */
1259 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1262 DHD_TRACE(("%s: calling txpkt\n", __func__));
1263 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1265 ret = dhdsdio_txpkt(bus, pkt,
1266 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1267 SDPCM_DATA_CHANNEL), true);
1270 bus->dhd->tx_errors++;
1272 bus->dhd->dstats.tx_bytes += datalen;
1274 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1275 bus->activity = false;
1276 dhdsdio_clkctl(bus, CLK_NONE, true);
1279 dhd_os_sdunlock(bus->dhd);
1285 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1287 struct sk_buff *pkt;
1290 int ret = 0, prec_out;
1295 dhd_pub_t *dhd = bus->dhd;
1296 sdpcmd_regs_t *regs = bus->regs;
1298 DHD_TRACE(("%s: Enter\n", __func__));
1300 tx_prec_map = ~bus->flowcontrol;
1302 /* Send frames until the limit or some other event */
1303 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1304 dhd_os_sdlock_txq(bus->dhd);
1305 pkt = bcm_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1307 dhd_os_sdunlock_txq(bus->dhd);
1310 dhd_os_sdunlock_txq(bus->dhd);
1311 datalen = pkt->len - SDPCM_HDRLEN;
1314 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1316 ret = dhdsdio_txpkt(bus, pkt,
1317 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1318 SDPCM_DATA_CHANNEL), true);
1321 bus->dhd->tx_errors++;
1323 bus->dhd->dstats.tx_bytes += datalen;
1325 /* In poll mode, need to check for other events */
1326 if (!bus->intr && cnt) {
1327 /* Check device status, signal pending interrupt */
1328 R_SDREG(intstatus, ®s->intstatus, retries);
1330 if (bcmsdh_regfail(bus->sdh))
1332 if (intstatus & bus->hostintmask)
1337 /* Deflow-control stack if needed */
1338 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1339 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1340 dhd_txflowcontrol(dhd, 0, OFF);
1345 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1351 bcmsdh_info_t *sdh = bus->sdh;
1356 DHD_TRACE(("%s: Enter\n", __func__));
1358 if (bus->dhd->dongle_reset)
1361 /* Back the pointer to make a room for bus header */
1362 frame = msg - SDPCM_HDRLEN;
1363 len = (msglen += SDPCM_HDRLEN);
1365 /* Add alignment padding (optional for ctl frames) */
1367 doff = ((unsigned long)frame % DHD_SDALIGN);
1372 memset(frame, 0, doff + SDPCM_HDRLEN);
1374 ASSERT(doff < DHD_SDALIGN);
1376 doff += SDPCM_HDRLEN;
1378 /* Round send length to next SDIO block */
1379 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1380 u16 pad = bus->blocksize - (len % bus->blocksize);
1381 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1383 } else if (len % DHD_SDALIGN) {
1384 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1387 /* Satisfy length-alignment requirements */
1388 if (forcealign && (len & (ALIGNMENT - 1)))
1389 len = roundup(len, ALIGNMENT);
1391 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1393 /* Need to lock here to protect txseq and SDIO tx calls */
1394 dhd_os_sdlock(bus->dhd);
1398 /* Make sure backplane clock is on */
1399 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1401 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1402 *(u16 *) frame = cpu_to_le16((u16) msglen);
1403 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1405 /* Software tag: channel, sequence number, data offset */
1407 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1409 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1410 SDPCM_DOFFSET_MASK);
1411 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1412 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1415 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1416 __func__, bus->tx_max, bus->tx_seq));
1417 bus->ctrl_frame_stat = true;
1419 bus->ctrl_frame_buf = frame;
1420 bus->ctrl_frame_len = len;
1422 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1424 if (bus->ctrl_frame_stat == false) {
1425 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1428 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1435 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1436 printk(KERN_DEBUG "Tx Frame:\n");
1437 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1439 } else if (DHD_HDRS_ON()) {
1440 printk(KERN_DEBUG "TxHdr:\n");
1441 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1442 frame, min_t(u16, len, 16));
1447 bus->ctrl_frame_stat = false;
1449 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1450 SDIO_FUNC_2, F2SYNC, frame, len,
1453 ASSERT(ret != -BCME_PENDING);
1456 /* On failure, abort the command and
1457 terminate the frame */
1458 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1462 bcmsdh_abort(sdh, SDIO_FUNC_2);
1464 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1465 SBSDIO_FUNC1_FRAMECTRL,
1469 for (i = 0; i < 3; i++) {
1471 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1472 SBSDIO_FUNC1_WFRAMEBCHI,
1474 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1475 SBSDIO_FUNC1_WFRAMEBCLO,
1477 bus->f1regdata += 2;
1478 if ((hi == 0) && (lo == 0))
1485 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1487 } while ((ret < 0) && retries++ < TXRETRIES);
1490 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1491 bus->activity = false;
1492 dhdsdio_clkctl(bus, CLK_NONE, true);
1495 dhd_os_sdunlock(bus->dhd);
1498 bus->dhd->tx_ctlerrs++;
1500 bus->dhd->tx_ctlpkts++;
1502 return ret ? -EIO : 0;
1505 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1511 DHD_TRACE(("%s: Enter\n", __func__));
1513 if (bus->dhd->dongle_reset)
1516 /* Wait until control frame is available */
1517 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1519 dhd_os_sdlock(bus->dhd);
1521 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1523 dhd_os_sdunlock(bus->dhd);
1526 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1527 __func__, rxlen, msglen));
1528 } else if (timeleft == 0) {
1529 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1531 dhd_os_sdlock(bus->dhd);
1532 dhdsdio_checkdied(bus, NULL, 0);
1533 dhd_os_sdunlock(bus->dhd);
1534 #endif /* DHD_DEBUG */
1535 } else if (pending == true) {
1536 DHD_CTL(("%s: cancelled\n", __func__));
1537 return -ERESTARTSYS;
1539 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1541 dhd_os_sdlock(bus->dhd);
1542 dhdsdio_checkdied(bus, NULL, 0);
1543 dhd_os_sdunlock(bus->dhd);
1544 #endif /* DHD_DEBUG */
1548 bus->dhd->rx_ctlpkts++;
1550 bus->dhd->rx_ctlerrs++;
1552 return rxlen ? (int)rxlen : -ETIMEDOUT;
1591 const bcm_iovar_t dhdsdio_iovars[] = {
1592 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1593 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1594 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1595 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1596 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1597 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1598 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1599 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1600 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1601 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1602 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1603 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1604 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1605 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1606 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1607 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1609 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1611 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1613 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1615 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1617 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1619 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1621 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1623 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1626 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1628 #endif /* DHD_DEBUG */
1629 #endif /* DHD_DEBUG */
1631 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1633 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1641 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1646 bcm_bprintf(strbuf, "%s N/A", desc);
1649 q2 = (100 * (num - (q1 * div))) / div;
1650 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1654 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1656 dhd_bus_t *bus = dhdp->bus;
1658 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1660 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1661 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1663 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1664 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1665 bus->rxskip, bus->rxlen, bus->rx_seq);
1666 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1667 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1668 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1669 bus->pollrate, bus->pollcnt, bus->regfails);
1671 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1673 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1674 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1676 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1677 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1678 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1679 bus->fc_xoff, bus->fc_xon);
1680 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1681 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1682 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1683 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1684 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1686 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1687 (bus->f2rxhdrs + bus->f2rxdata));
1688 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1690 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1691 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1692 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1694 bcm_bprintf(strbuf, "\n");
1696 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1697 bus->dhd->rx_packets);
1698 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1700 bcm_bprintf(strbuf, "\n");
1702 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1704 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1706 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1707 (bus->f2txdata + bus->f1regdata));
1708 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1710 bcm_bprintf(strbuf, "\n");
1712 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1713 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1714 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1715 dhd_dump_pct(strbuf, ", pkts/f1sd",
1716 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1718 dhd_dump_pct(strbuf, ", pkts/sd",
1719 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1720 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1722 dhd_dump_pct(strbuf, ", pkts/int",
1723 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1725 bcm_bprintf(strbuf, "\n\n");
1729 if (bus->pktgen_count) {
1730 bcm_bprintf(strbuf, "pktgen config and count:\n");
1732 "freq %d count %d print %d total %d min %d len %d\n",
1733 bus->pktgen_freq, bus->pktgen_count,
1734 bus->pktgen_print, bus->pktgen_total,
1735 bus->pktgen_minlen, bus->pktgen_maxlen);
1736 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1737 bus->pktgen_sent, bus->pktgen_rcvd,
1742 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1744 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1745 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1747 #endif /* DHD_DEBUG */
1749 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1750 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1754 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1756 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1758 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1759 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1760 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1761 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1762 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1763 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1767 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1769 dhd_pktgen_t pktgen;
1771 pktgen.version = DHD_PKTGEN_VERSION;
1772 pktgen.freq = bus->pktgen_freq;
1773 pktgen.count = bus->pktgen_count;
1774 pktgen.print = bus->pktgen_print;
1775 pktgen.total = bus->pktgen_total;
1776 pktgen.minlen = bus->pktgen_minlen;
1777 pktgen.maxlen = bus->pktgen_maxlen;
1778 pktgen.numsent = bus->pktgen_sent;
1779 pktgen.numrcvd = bus->pktgen_rcvd;
1780 pktgen.numfail = bus->pktgen_fail;
1781 pktgen.mode = bus->pktgen_mode;
1782 pktgen.stop = bus->pktgen_stop;
1784 memcpy(arg, &pktgen, sizeof(pktgen));
1789 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1791 dhd_pktgen_t pktgen;
1792 uint oldcnt, oldmode;
1794 memcpy(&pktgen, arg, sizeof(pktgen));
1795 if (pktgen.version != DHD_PKTGEN_VERSION)
1798 oldcnt = bus->pktgen_count;
1799 oldmode = bus->pktgen_mode;
1801 bus->pktgen_freq = pktgen.freq;
1802 bus->pktgen_count = pktgen.count;
1803 bus->pktgen_print = pktgen.print;
1804 bus->pktgen_total = pktgen.total;
1805 bus->pktgen_minlen = pktgen.minlen;
1806 bus->pktgen_maxlen = pktgen.maxlen;
1807 bus->pktgen_mode = pktgen.mode;
1808 bus->pktgen_stop = pktgen.stop;
1810 bus->pktgen_tick = bus->pktgen_ptick = 0;
1811 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1812 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1814 /* Clear counts for a new pktgen (mode change, or was stopped) */
1815 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1816 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1823 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1830 /* Determine initial transfer parameters */
1831 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1832 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1833 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1837 /* Set the backplane window to include the start address */
1838 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1840 DHD_ERROR(("%s: window change failed\n", __func__));
1844 /* Do the transfer(s) */
1846 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1847 __func__, (write ? "write" : "read"), dsize,
1848 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1850 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1852 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1856 /* Adjust for next transfer (if any) */
1861 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1863 DHD_ERROR(("%s: window change failed\n",
1868 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1873 /* Return the window to backplane enumeration space for core access */
1874 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1875 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1876 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1883 static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1888 /* Read last word in memory to determine address of
1889 sdpcm_shared structure */
1890 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
1894 addr = le32_to_cpu(addr);
1896 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1899 * Check if addr is valid.
1900 * NVRAM length at the end of memory should have been overwritten.
1902 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1903 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1908 /* Read rte_shared structure */
1909 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
1910 sizeof(sdpcm_shared_t));
1915 sh->flags = le32_to_cpu(sh->flags);
1916 sh->trap_addr = le32_to_cpu(sh->trap_addr);
1917 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
1918 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
1919 sh->assert_line = le32_to_cpu(sh->assert_line);
1920 sh->console_addr = le32_to_cpu(sh->console_addr);
1921 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
1923 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1924 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1925 "is different than sdpcm_shared version %d in dongle\n",
1926 __func__, SDPCM_SHARED_VERSION,
1927 sh->flags & SDPCM_SHARED_VERSION_MASK));
1934 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1938 char *mbuffer = NULL;
1939 uint maxstrlen = 256;
1942 sdpcm_shared_t sdpcm_shared;
1943 struct bcmstrbuf strbuf;
1945 DHD_TRACE(("%s: Enter\n", __func__));
1949 * Called after a rx ctrl timeout. "data" is NULL.
1950 * allocate memory to trace the trap or assert.
1953 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1954 if (mbuffer == NULL) {
1955 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1962 str = kmalloc(maxstrlen, GFP_ATOMIC);
1964 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1969 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1973 bcm_binit(&strbuf, data, size);
1975 bcm_bprintf(&strbuf,
1976 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1977 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1979 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1980 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1981 * (Avoids conflict with real asserts for programmatic
1982 * parsing of output.)
1984 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1987 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1989 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1990 * (Avoids conflict with real asserts for programmatic
1991 * parsing of output.)
1993 bcm_bprintf(&strbuf, "No trap%s in dongle",
1994 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1997 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1998 /* Download assert */
1999 bcm_bprintf(&strbuf, "Dongle assert");
2000 if (sdpcm_shared.assert_exp_addr != 0) {
2002 bcmerror = dhdsdio_membytes(bus, false,
2003 sdpcm_shared.assert_exp_addr,
2004 (u8 *) str, maxstrlen);
2008 str[maxstrlen - 1] = '\0';
2009 bcm_bprintf(&strbuf, " expr \"%s\"", str);
2012 if (sdpcm_shared.assert_file_addr != 0) {
2014 bcmerror = dhdsdio_membytes(bus, false,
2015 sdpcm_shared.assert_file_addr,
2016 (u8 *) str, maxstrlen);
2020 str[maxstrlen - 1] = '\0';
2021 bcm_bprintf(&strbuf, " file \"%s\"", str);
2024 bcm_bprintf(&strbuf, " line %d ",
2025 sdpcm_shared.assert_line);
2028 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2029 bcmerror = dhdsdio_membytes(bus, false,
2030 sdpcm_shared.trap_addr, (u8 *)&tr,
2035 bcm_bprintf(&strbuf,
2036 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2037 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2038 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2039 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2040 tr.r14, tr.pc, sdpcm_shared.trap_addr,
2041 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2046 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2047 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2050 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2051 /* Mem dump to a file on device */
2052 dhdsdio_mem_dump(bus);
2054 #endif /* DHD_DEBUG */
2063 static int dhdsdio_mem_dump(dhd_bus_t *bus)
2066 int size; /* Full mem size */
2067 int start = 0; /* Start address */
2068 int read_size = 0; /* Read size of each iteration */
2069 u8 *buf = NULL, *databuf = NULL;
2071 /* Get full mem size */
2072 size = bus->ramsize;
2073 buf = kmalloc(size, GFP_ATOMIC);
2075 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2079 /* Read mem content */
2080 printk(KERN_DEBUG "Dump dongle memory");
2083 read_size = min(MEMBLOCK, size);
2084 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
2086 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2092 /* Decrement size and increment start address */
2095 databuf += read_size;
2097 printk(KERN_DEBUG "Done\n");
2099 /* free buf before return !!! */
2100 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
2101 DHD_ERROR(("%s: Error writing to files\n", __func__));
2105 /* buf free handled in write_to_file, not here */
2109 #define CONSOLE_LINE_MAX 192
2111 static int dhdsdio_readconsole(dhd_bus_t *bus)
2113 dhd_console_t *c = &bus->console;
2114 u8 line[CONSOLE_LINE_MAX], ch;
2118 /* Don't do anything until FWREADY updates console address */
2119 if (bus->console_addr == 0)
2122 /* Read console log struct */
2123 addr = bus->console_addr + offsetof(rte_cons_t, log);
2124 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2129 /* Allocate console buffer (one time only) */
2130 if (c->buf == NULL) {
2131 c->bufsize = le32_to_cpu(c->log.buf_size);
2132 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2137 idx = le32_to_cpu(c->log.idx);
2139 /* Protect against corrupt value */
2140 if (idx > c->bufsize)
2143 /* Skip reading the console buffer if the index pointer
2148 /* Read the console buffer */
2149 addr = le32_to_cpu(c->log.buf);
2150 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2154 while (c->last != idx) {
2155 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2156 if (c->last == idx) {
2157 /* This would output a partial line.
2159 * the buffer pointer and output this
2160 * line next time around.
2165 c->last = c->bufsize - n;
2168 ch = c->buf[c->last];
2169 c->last = (c->last + 1) % c->bufsize;
2176 if (line[n - 1] == '\r')
2179 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2186 #endif /* DHD_DEBUG */
2188 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2192 DHD_TRACE(("%s: Enter\n", __func__));
2194 /* Basic sanity checks */
2196 bcmerror = -EISCONN;
2200 bcmerror = -EOVERFLOW;
2204 /* Free the old ones and replace with passed variables */
2207 bus->vars = kmalloc(len, GFP_ATOMIC);
2208 bus->varsz = bus->vars ? len : 0;
2209 if (bus->vars == NULL) {
2214 /* Copy the passed variables, which should include the
2215 terminating double-null */
2216 memcpy(bus->vars, arg, bus->varsz);
2222 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2223 const char *name, void *params, int plen, void *arg, int len,
2230 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2231 "len %d val_size %d\n",
2232 __func__, actionid, name, params, plen, arg, len, val_size));
2234 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2238 if (plen >= (int)sizeof(int_val))
2239 memcpy(&int_val, params, sizeof(int_val));
2241 bool_val = (int_val != 0) ? true : false;
2243 /* Some ioctls use the bus */
2244 dhd_os_sdlock(bus->dhd);
2246 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2247 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2248 actionid == IOV_GVAL(IOV_DEVRESET))) {
2253 /* Handle sleep stuff before any clock mucking */
2254 if (vi->varid == IOV_SLEEP) {
2255 if (IOV_ISSET(actionid)) {
2256 bcmerror = dhdsdio_bussleep(bus, bool_val);
2258 int_val = (s32) bus->sleeping;
2259 memcpy(arg, &int_val, val_size);
2264 /* Request clock to allow SDIO accesses */
2265 if (!bus->dhd->dongle_reset) {
2267 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2271 case IOV_GVAL(IOV_INTR):
2272 int_val = (s32) bus->intr;
2273 memcpy(arg, &int_val, val_size);
2276 case IOV_SVAL(IOV_INTR):
2277 bus->intr = bool_val;
2278 bus->intdis = false;
2281 DHD_INTR(("%s: enable SDIO device interrupts\n",
2283 bcmsdh_intr_enable(bus->sdh);
2285 DHD_INTR(("%s: disable SDIO interrupts\n",
2287 bcmsdh_intr_disable(bus->sdh);
2292 case IOV_GVAL(IOV_POLLRATE):
2293 int_val = (s32) bus->pollrate;
2294 memcpy(arg, &int_val, val_size);
2297 case IOV_SVAL(IOV_POLLRATE):
2298 bus->pollrate = (uint) int_val;
2299 bus->poll = (bus->pollrate != 0);
2302 case IOV_GVAL(IOV_IDLETIME):
2303 int_val = bus->idletime;
2304 memcpy(arg, &int_val, val_size);
2307 case IOV_SVAL(IOV_IDLETIME):
2308 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2311 bus->idletime = int_val;
2314 case IOV_GVAL(IOV_IDLECLOCK):
2315 int_val = (s32) bus->idleclock;
2316 memcpy(arg, &int_val, val_size);
2319 case IOV_SVAL(IOV_IDLECLOCK):
2320 bus->idleclock = int_val;
2323 case IOV_GVAL(IOV_SD1IDLE):
2324 int_val = (s32) sd1idle;
2325 memcpy(arg, &int_val, val_size);
2328 case IOV_SVAL(IOV_SD1IDLE):
2332 case IOV_SVAL(IOV_MEMBYTES):
2333 case IOV_GVAL(IOV_MEMBYTES):
2339 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2341 ASSERT(plen >= 2 * sizeof(int));
2343 address = (u32) int_val;
2344 memcpy(&int_val, (char *)params + sizeof(int_val),
2346 size = (uint) int_val;
2348 /* Do some validation */
2349 dsize = set ? plen - (2 * sizeof(int)) : len;
2351 DHD_ERROR(("%s: error on %s membytes, addr "
2352 "0x%08x size %d dsize %d\n",
2353 __func__, (set ? "set" : "get"),
2354 address, size, dsize));
2359 DHD_INFO(("%s: Request to %s %d bytes at address "
2361 __func__, (set ? "write" : "read"), size, address));
2363 /* If we know about SOCRAM, check for a fit */
2364 if ((bus->orig_ramsize) &&
2365 ((address > bus->orig_ramsize)
2366 || (address + size > bus->orig_ramsize))) {
2367 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2368 "bytes at 0x%08x\n",
2369 __func__, bus->orig_ramsize, size, address));
2374 /* Generate the actual data pointer */
2376 set ? (u8 *) params +
2377 2 * sizeof(int) : (u8 *) arg;
2379 /* Call to do the transfer */
2381 dhdsdio_membytes(bus, set, address, data, size);
2386 case IOV_GVAL(IOV_MEMSIZE):
2387 int_val = (s32) bus->ramsize;
2388 memcpy(arg, &int_val, val_size);
2391 case IOV_GVAL(IOV_SDIOD_DRIVE):
2392 int_val = (s32) dhd_sdiod_drive_strength;
2393 memcpy(arg, &int_val, val_size);
2396 case IOV_SVAL(IOV_SDIOD_DRIVE):
2397 dhd_sdiod_drive_strength = int_val;
2398 dhdsdio_sdiod_drive_strength_init(bus,
2399 dhd_sdiod_drive_strength);
2402 case IOV_SVAL(IOV_DOWNLOAD):
2403 bcmerror = dhdsdio_download_state(bus, bool_val);
2406 case IOV_SVAL(IOV_VARS):
2407 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2410 case IOV_GVAL(IOV_READAHEAD):
2411 int_val = (s32) dhd_readahead;
2412 memcpy(arg, &int_val, val_size);
2415 case IOV_SVAL(IOV_READAHEAD):
2416 if (bool_val && !dhd_readahead)
2418 dhd_readahead = bool_val;
2421 case IOV_GVAL(IOV_SDRXCHAIN):
2422 int_val = (s32) bus->use_rxchain;
2423 memcpy(arg, &int_val, val_size);
2426 case IOV_SVAL(IOV_SDRXCHAIN):
2427 if (bool_val && !bus->sd_rxchain)
2428 bcmerror = -ENOTSUPP;
2430 bus->use_rxchain = bool_val;
2432 case IOV_GVAL(IOV_ALIGNCTL):
2433 int_val = (s32) dhd_alignctl;
2434 memcpy(arg, &int_val, val_size);
2437 case IOV_SVAL(IOV_ALIGNCTL):
2438 dhd_alignctl = bool_val;
2441 case IOV_GVAL(IOV_SDALIGN):
2442 int_val = DHD_SDALIGN;
2443 memcpy(arg, &int_val, val_size);
2447 case IOV_GVAL(IOV_VARS):
2448 if (bus->varsz < (uint) len)
2449 memcpy(arg, bus->vars, bus->varsz);
2451 bcmerror = -EOVERFLOW;
2453 #endif /* DHD_DEBUG */
2456 case IOV_GVAL(IOV_SDREG):
2461 sd_ptr = (sdreg_t *) params;
2463 addr = (unsigned long)bus->regs + sd_ptr->offset;
2464 size = sd_ptr->func;
2465 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2466 if (bcmsdh_regfail(bus->sdh))
2468 memcpy(arg, &int_val, sizeof(s32));
2472 case IOV_SVAL(IOV_SDREG):
2477 sd_ptr = (sdreg_t *) params;
2479 addr = (unsigned long)bus->regs + sd_ptr->offset;
2480 size = sd_ptr->func;
2481 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2482 if (bcmsdh_regfail(bus->sdh))
2487 /* Same as above, but offset is not backplane
2489 case IOV_GVAL(IOV_SBREG):
2494 memcpy(&sdreg, params, sizeof(sdreg));
2496 addr = SI_ENUM_BASE + sdreg.offset;
2498 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2499 if (bcmsdh_regfail(bus->sdh))
2501 memcpy(arg, &int_val, sizeof(s32));
2505 case IOV_SVAL(IOV_SBREG):
2510 memcpy(&sdreg, params, sizeof(sdreg));
2512 addr = SI_ENUM_BASE + sdreg.offset;
2514 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2515 if (bcmsdh_regfail(bus->sdh))
2520 case IOV_GVAL(IOV_SDCIS):
2524 strcat(arg, "\nFunc 0\n");
2525 bcmsdh_cis_read(bus->sdh, 0x10,
2526 (u8 *) arg + strlen(arg),
2527 SBSDIO_CIS_SIZE_LIMIT);
2528 strcat(arg, "\nFunc 1\n");
2529 bcmsdh_cis_read(bus->sdh, 0x11,
2530 (u8 *) arg + strlen(arg),
2531 SBSDIO_CIS_SIZE_LIMIT);
2532 strcat(arg, "\nFunc 2\n");
2533 bcmsdh_cis_read(bus->sdh, 0x12,
2534 (u8 *) arg + strlen(arg),
2535 SBSDIO_CIS_SIZE_LIMIT);
2539 case IOV_GVAL(IOV_FORCEEVEN):
2540 int_val = (s32) forcealign;
2541 memcpy(arg, &int_val, val_size);
2544 case IOV_SVAL(IOV_FORCEEVEN):
2545 forcealign = bool_val;
2548 case IOV_GVAL(IOV_TXBOUND):
2549 int_val = (s32) dhd_txbound;
2550 memcpy(arg, &int_val, val_size);
2553 case IOV_SVAL(IOV_TXBOUND):
2554 dhd_txbound = (uint) int_val;
2557 case IOV_GVAL(IOV_RXBOUND):
2558 int_val = (s32) dhd_rxbound;
2559 memcpy(arg, &int_val, val_size);
2562 case IOV_SVAL(IOV_RXBOUND):
2563 dhd_rxbound = (uint) int_val;
2566 case IOV_GVAL(IOV_TXMINMAX):
2567 int_val = (s32) dhd_txminmax;
2568 memcpy(arg, &int_val, val_size);
2571 case IOV_SVAL(IOV_TXMINMAX):
2572 dhd_txminmax = (uint) int_val;
2574 #endif /* DHD_DEBUG */
2577 case IOV_GVAL(IOV_EXTLOOP):
2578 int_val = (s32) bus->ext_loop;
2579 memcpy(arg, &int_val, val_size);
2582 case IOV_SVAL(IOV_EXTLOOP):
2583 bus->ext_loop = bool_val;
2586 case IOV_GVAL(IOV_PKTGEN):
2587 bcmerror = dhdsdio_pktgen_get(bus, arg);
2590 case IOV_SVAL(IOV_PKTGEN):
2591 bcmerror = dhdsdio_pktgen_set(bus, arg);
2595 case IOV_SVAL(IOV_DEVRESET):
2596 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2598 __func__, bool_val, bus->dhd->dongle_reset,
2599 bus->dhd->busstate));
2601 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2605 case IOV_GVAL(IOV_DEVRESET):
2606 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2608 /* Get its status */
2609 int_val = (bool) bus->dhd->dongle_reset;
2610 memcpy(arg, &int_val, val_size);
2615 bcmerror = -ENOTSUPP;
2620 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2621 bus->activity = false;
2622 dhdsdio_clkctl(bus, CLK_NONE, true);
2625 dhd_os_sdunlock(bus->dhd);
2627 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2628 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2633 static int dhdsdio_write_vars(dhd_bus_t *bus)
2641 char *nvram_ularray;
2642 #endif /* DHD_DEBUG */
2644 /* Even if there are no vars are to be written, we still
2645 need to set the ramsize. */
2646 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2647 varaddr = (bus->ramsize - 4) - varsize;
2650 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2654 memcpy(vbuffer, bus->vars, bus->varsz);
2656 /* Write the vars list */
2658 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2660 /* Verify NVRAM bytes */
2661 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2662 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2666 /* Upload image to verify downloaded contents. */
2667 memset(nvram_ularray, 0xaa, varsize);
2669 /* Read the vars list to temp buffer for comparison */
2671 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2674 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2675 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2677 /* Compare the org NVRAM with the one read from RAM */
2678 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2679 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2682 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2685 kfree(nvram_ularray);
2686 #endif /* DHD_DEBUG */
2691 /* adjust to the user specified RAM */
2692 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2693 bus->orig_ramsize, bus->ramsize));
2694 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2695 varsize = ((bus->orig_ramsize - 4) - varaddr);
2698 * Determine the length token:
2699 * Varsize, converted to words, in lower 16-bits, checksum
2705 varsizew = varsize / 4;
2706 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2707 varsizew = cpu_to_le32(varsizew);
2710 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2713 /* Write the length token to the last word */
2714 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2715 (u8 *)&varsizew, 4);
2720 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2726 /* To enter download state, disable ARM and reset SOCRAM.
2727 * To exit download state, simply reset ARM (default is RAM boot).
2730 bus->alp_only = true;
2732 dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2734 dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2736 /* Clear the top bit of memory */
2739 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2743 regdata = bcmsdh_reg_read(bus->sdh,
2744 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2745 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2746 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2747 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2748 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2754 bcmerror = dhdsdio_write_vars(bus);
2756 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2760 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2762 dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2764 /* Allow HT Clock now that the ARM is running. */
2765 bus->alp_only = false;
2767 bus->dhd->busstate = DHD_BUS_LOAD;
2774 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2775 void *params, int plen, void *arg, int len, bool set)
2777 dhd_bus_t *bus = dhdp->bus;
2778 const bcm_iovar_t *vi = NULL;
2783 DHD_TRACE(("%s: Enter\n", __func__));
2788 /* Get MUST have return space */
2789 ASSERT(set || (arg && len));
2791 /* Set does NOT take qualifiers */
2792 ASSERT(!set || (!params && !plen));
2794 /* Look up var locally; if not found pass to host driver */
2795 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2797 dhd_os_sdlock(bus->dhd);
2801 /* Turn on clock in case SD command needs backplane */
2802 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2805 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2808 /* Similar check for blocksize change */
2809 if (set && strcmp(name, "sd_blocksize") == 0) {
2812 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2813 &bus->blocksize, sizeof(s32),
2816 DHD_ERROR(("%s: fail on %s get\n", __func__,
2819 DHD_INFO(("%s: noted %s update, value now %d\n",
2820 __func__, "sd_blocksize",
2824 bus->roundup = min(max_roundup, bus->blocksize);
2826 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2827 bus->activity = false;
2828 dhdsdio_clkctl(bus, CLK_NONE, true);
2831 dhd_os_sdunlock(bus->dhd);
2835 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2836 name, (set ? "set" : "get"), len, plen));
2838 /* set up 'params' pointer in case this is a set command so that
2839 * the convenience int and bool code can be common to set and get
2841 if (params == NULL) {
2846 if (vi->type == IOVT_VOID)
2848 else if (vi->type == IOVT_BUFFER)
2851 /* all other types are integer sized */
2852 val_size = sizeof(int);
2854 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2856 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2863 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2865 u32 local_hostintmask;
2870 DHD_TRACE(("%s: Enter\n", __func__));
2873 dhd_os_sdlock(bus->dhd);
2877 /* Enable clock for device interrupts */
2878 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2880 /* Disable and clear interrupts at the chip level also */
2881 W_SDREG(0, &bus->regs->hostintmask, retries);
2882 local_hostintmask = bus->hostintmask;
2883 bus->hostintmask = 0;
2885 /* Change our idea of bus state */
2886 bus->dhd->busstate = DHD_BUS_DOWN;
2888 /* Force clocks on backplane to be sure F2 interrupt propagates */
2890 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2893 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2894 (saveclk | SBSDIO_FORCE_HT), &err);
2897 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2901 /* Turn off the bus (F2), free any pending packets */
2902 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2903 bcmsdh_intr_disable(bus->sdh);
2904 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2905 SDIO_FUNC_ENABLE_1, NULL);
2907 /* Clear any pending interrupts now that F2 is disabled */
2908 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2910 /* Turn off the backplane clock (only) */
2911 dhdsdio_clkctl(bus, CLK_SDONLY, false);
2913 /* Clear the data packet queues */
2914 bcm_pktq_flush(&bus->txq, true, NULL, NULL);
2916 /* Clear any held glomming stuff */
2918 bcm_pkt_buf_free_skb(bus->glomd);
2921 bcm_pkt_buf_free_skb(bus->glom);
2923 bus->glom = bus->glomd = NULL;
2925 /* Clear rx control and wake any waiters */
2927 dhd_os_ioctl_resp_wake(bus->dhd);
2929 /* Reset some F2 state stuff */
2930 bus->rxskip = false;
2931 bus->tx_seq = bus->rx_seq = 0;
2934 dhd_os_sdunlock(bus->dhd);
2937 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2939 dhd_bus_t *bus = dhdp->bus;
2946 DHD_TRACE(("%s: Enter\n", __func__));
2953 dhd_os_sdlock(bus->dhd);
2955 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2956 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2957 if (bus->clkstate != CLK_AVAIL)
2960 /* Force clocks on backplane to be sure F2 interrupt propagates */
2962 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2965 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2966 (saveclk | SBSDIO_FORCE_HT), &err);
2969 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2974 /* Enable function 2 (frame transfers) */
2975 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2976 &bus->regs->tosbmailboxdata, retries);
2977 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2979 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2981 /* Give the dongle some time to do its thing and set IOR2 */
2982 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2985 while (ready != enable && !dhd_timeout_expired(&tmo))
2987 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2990 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2991 __func__, enable, ready, tmo.elapsed));
2993 /* If F2 successfully enabled, set core and enable interrupts */
2994 if (ready == enable) {
2995 /* Set up the interrupt mask and enable interrupts */
2996 bus->hostintmask = HOSTINTMASK;
2997 W_SDREG(bus->hostintmask,
2998 (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
2999 hostintmask), retries);
3001 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3002 (u8) watermark, &err);
3004 /* Set bus state according to enable result */
3005 dhdp->busstate = DHD_BUS_DATA;
3007 /* bcmsdh_intr_unmask(bus->sdh); */
3009 bus->intdis = false;
3011 DHD_INTR(("%s: enable SDIO device interrupts\n",
3013 bcmsdh_intr_enable(bus->sdh);
3015 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3016 bcmsdh_intr_disable(bus->sdh);
3022 /* Disable F2 again */
3023 enable = SDIO_FUNC_ENABLE_1;
3024 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
3028 /* Restore previous clock setting */
3029 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3032 /* If we didn't come up, turn off backplane clock */
3033 if (dhdp->busstate != DHD_BUS_DATA)
3034 dhdsdio_clkctl(bus, CLK_NONE, false);
3038 dhd_os_sdunlock(bus->dhd);
3043 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3045 bcmsdh_info_t *sdh = bus->sdh;
3046 sdpcmd_regs_t *regs = bus->regs;
3052 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3053 (abort ? "abort command, " : ""),
3054 (rtx ? ", send NAK" : "")));
3057 bcmsdh_abort(sdh, SDIO_FUNC_2);
3059 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3063 /* Wait until the packet has been flushed (device/FIFO stable) */
3064 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3065 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3067 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3069 bus->f1regdata += 2;
3071 if ((hi == 0) && (lo == 0))
3074 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3075 DHD_ERROR(("%s: count growing: last 0x%04x now "
3077 __func__, lastrbc, ((hi << 8) + lo)));
3079 lastrbc = (hi << 8) + lo;
3083 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3084 __func__, lastrbc));
3086 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3087 (0xffff - retries)));
3092 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3094 if (retries <= retry_limit)
3098 /* Clear partial in any case */
3101 /* If we can't reach the device, signal failure */
3102 if (err || bcmsdh_regfail(sdh))
3103 bus->dhd->busstate = DHD_BUS_DOWN;
3107 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3109 bcmsdh_info_t *sdh = bus->sdh;
3114 DHD_TRACE(("%s: Enter\n", __func__));
3116 /* Control data already received in aligned rxctl */
3117 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3121 /* Set rxctl for frame (w/optional alignment) */
3122 bus->rxctl = bus->rxbuf;
3124 bus->rxctl += firstread;
3125 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3127 bus->rxctl += (DHD_SDALIGN - pad);
3128 bus->rxctl -= firstread;
3130 ASSERT(bus->rxctl >= bus->rxbuf);
3132 /* Copy the already-read portion over */
3133 memcpy(bus->rxctl, hdr, firstread);
3134 if (len <= firstread)
3137 /* Copy the full data pkt in gSPI case and process ioctl. */
3138 if (bus->bus == SPI_BUS) {
3139 memcpy(bus->rxctl, hdr, len);
3143 /* Raise rdlen to next SDIO block to avoid tail command */
3144 rdlen = len - firstread;
3145 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3146 pad = bus->blocksize - (rdlen % bus->blocksize);
3147 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3148 ((len + pad) < bus->dhd->maxctl))
3150 } else if (rdlen % DHD_SDALIGN) {
3151 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3154 /* Satisfy length-alignment requirements */
3155 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3156 rdlen = roundup(rdlen, ALIGNMENT);
3158 /* Drop if the read is too big or it exceeds our maximum */
3159 if ((rdlen + firstread) > bus->dhd->maxctl) {
3160 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3161 __func__, rdlen, bus->dhd->maxctl));
3162 bus->dhd->rx_errors++;
3163 dhdsdio_rxfail(bus, false, false);
3167 if ((len - doff) > bus->dhd->maxctl) {
3168 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3170 __func__, len, (len - doff), bus->dhd->maxctl));
3171 bus->dhd->rx_errors++;
3173 dhdsdio_rxfail(bus, false, false);
3177 /* Read remainder of frame body into the rxctl buffer */
3178 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3179 F2SYNC, (bus->rxctl + firstread), rdlen,
3182 ASSERT(sdret != -BCME_PENDING);
3184 /* Control frame failures need retransmission */
3186 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3187 __func__, rdlen, sdret));
3188 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3189 dhdsdio_rxfail(bus, true, true);
3196 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3197 printk(KERN_DEBUG "RxCtrl:\n");
3198 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3202 /* Point to valid data and indicate its length */
3204 bus->rxlen = len - doff;
3207 /* Awake any waiters */
3208 dhd_os_ioctl_resp_wake(bus->dhd);
3211 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3217 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3220 u8 chan, seq, doff, sfdoff;
3224 bool usechain = bus->use_rxchain;
3226 /* If packets, issue read(s) and send up packet chain */
3227 /* Return sequence numbers consumed? */
3229 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3232 /* If there's a descriptor, generate the packet chain */
3234 dhd_os_sdlock_rxq(bus->dhd);
3236 pfirst = plast = pnext = NULL;
3237 dlen = (u16) (bus->glomd->len);
3238 dptr = bus->glomd->data;
3239 if (!dlen || (dlen & 1)) {
3240 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3245 for (totlen = num = 0; dlen; num++) {
3246 /* Get (and move past) next length */
3247 sublen = get_unaligned_le16(dptr);
3248 dlen -= sizeof(u16);
3249 dptr += sizeof(u16);
3250 if ((sublen < SDPCM_HDRLEN) ||
3251 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3252 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3253 __func__, num, sublen));
3257 if (sublen % DHD_SDALIGN) {
3258 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3259 __func__, sublen, DHD_SDALIGN));
3264 /* For last frame, adjust read len so total
3265 is a block multiple */
3268 (roundup(totlen, bus->blocksize) - totlen);
3269 totlen = roundup(totlen, bus->blocksize);
3272 /* Allocate/chain packet for next subframe */
3273 pnext = bcm_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3274 if (pnext == NULL) {
3275 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3276 "num %d len %d\n", __func__,
3280 ASSERT(!(pnext->prev));
3283 pfirst = plast = pnext;
3286 plast->next = pnext;
3290 /* Adhere to start alignment requirements */
3291 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3294 /* If all allocations succeeded, save packet chain
3297 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3298 "subframes\n", __func__, totlen, num));
3299 if (DHD_GLOM_ON() && bus->nextlen) {
3300 if (totlen != bus->nextlen) {
3301 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3302 __func__, bus->nextlen,
3307 pfirst = pnext = NULL;
3310 bcm_pkt_buf_free_skb(pfirst);
3315 /* Done with descriptor packet */
3316 bcm_pkt_buf_free_skb(bus->glomd);
3320 dhd_os_sdunlock_rxq(bus->dhd);
3323 /* Ok -- either we just generated a packet chain,
3324 or had one from before */
3326 if (DHD_GLOM_ON()) {
3327 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3329 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3330 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3331 pnext, (u8 *) (pnext->data),
3332 pnext->len, pnext->len));
3337 dlen = (u16) bcm_pkttotlen(pfirst);
3339 /* Do an SDIO read for the superframe. Configurable iovar to
3340 * read directly into the chained packet, or allocate a large
3341 * packet and and copy into the chain.
3344 errcode = bcmsdh_recv_buf(bus,
3345 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3346 F2SYNC, (u8 *) pfirst->data, dlen,
3347 pfirst, NULL, NULL);
3348 } else if (bus->dataptr) {
3349 errcode = bcmsdh_recv_buf(bus,
3350 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3351 F2SYNC, bus->dataptr, dlen,
3353 sublen = (u16) bcm_pktfrombuf(pfirst, 0, dlen,
3355 if (sublen != dlen) {
3356 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3357 __func__, dlen, sublen));
3362 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3367 ASSERT(errcode != -BCME_PENDING);
3369 /* On failure, kill the superframe, allow a couple retries */
3371 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3372 __func__, dlen, errcode));
3373 bus->dhd->rx_errors++;
3375 if (bus->glomerr++ < 3) {
3376 dhdsdio_rxfail(bus, true, true);
3379 dhdsdio_rxfail(bus, true, false);
3380 dhd_os_sdlock_rxq(bus->dhd);
3381 bcm_pkt_buf_free_skb(bus->glom);
3382 dhd_os_sdunlock_rxq(bus->dhd);
3389 if (DHD_GLOM_ON()) {
3390 printk(KERN_DEBUG "SUPERFRAME:\n");
3391 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3392 pfirst->data, min_t(int, pfirst->len, 48));
3396 /* Validate the superframe header */
3397 dptr = (u8 *) (pfirst->data);
3398 sublen = get_unaligned_le16(dptr);
3399 check = get_unaligned_le16(dptr + sizeof(u16));
3401 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3402 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3403 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3404 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3405 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3406 __func__, bus->nextlen, seq));
3409 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3410 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3413 if ((u16)~(sublen ^ check)) {
3414 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3415 "0x%04x/0x%04x\n", __func__, sublen, check));
3417 } else if (roundup(sublen, bus->blocksize) != dlen) {
3418 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3419 "0x%04x, expect 0x%04x\n",
3421 roundup(sublen, bus->blocksize), dlen));
3423 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3424 SDPCM_GLOM_CHANNEL) {
3425 DHD_ERROR(("%s (superframe): bad channel %d\n",
3427 SDPCM_PACKET_CHANNEL(&dptr
3428 [SDPCM_FRAMETAG_LEN])));
3430 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3431 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3434 } else if ((doff < SDPCM_HDRLEN) ||
3435 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3436 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3438 __func__, doff, sublen,
3439 pfirst->len, SDPCM_HDRLEN));
3443 /* Check sequence number of superframe SW header */
3445 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3446 __func__, seq, rxseq));
3451 /* Check window for sanity */
3452 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3453 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3454 __func__, txmax, bus->tx_seq));
3455 txmax = bus->tx_seq + 2;
3457 bus->tx_max = txmax;
3459 /* Remove superframe header, remember offset */
3460 skb_pull(pfirst, doff);
3463 /* Validate all the subframe headers */
3464 for (num = 0, pnext = pfirst; pnext && !errcode;
3465 num++, pnext = pnext->next) {
3466 dptr = (u8 *) (pnext->data);
3467 dlen = (u16) (pnext->len);
3468 sublen = get_unaligned_le16(dptr);
3469 check = get_unaligned_le16(dptr + sizeof(u16));
3470 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3471 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3473 if (DHD_GLOM_ON()) {
3474 printk(KERN_DEBUG "subframe:\n");
3475 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3480 if ((u16)~(sublen ^ check)) {
3481 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3482 "len/check 0x%04x/0x%04x\n",
3483 __func__, num, sublen, check));
3485 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3486 DHD_ERROR(("%s (subframe %d): length mismatch: "
3487 "len 0x%04x, expect 0x%04x\n",
3488 __func__, num, sublen, dlen));
3490 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3491 (chan != SDPCM_EVENT_CHANNEL)) {
3492 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3493 __func__, num, chan));
3495 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3496 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3497 __func__, num, doff, sublen,
3504 /* Terminate frame on error, request
3506 if (bus->glomerr++ < 3) {
3507 /* Restore superframe header space */
3508 skb_push(pfirst, sfdoff);
3509 dhdsdio_rxfail(bus, true, true);
3512 dhdsdio_rxfail(bus, true, false);
3513 dhd_os_sdlock_rxq(bus->dhd);
3514 bcm_pkt_buf_free_skb(bus->glom);
3515 dhd_os_sdunlock_rxq(bus->dhd);
3523 /* Basic SD framing looks ok - process each packet (header) */
3524 save_pfirst = pfirst;
3528 dhd_os_sdlock_rxq(bus->dhd);
3529 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3530 pnext = pfirst->next;
3531 pfirst->next = NULL;
3533 dptr = (u8 *) (pfirst->data);
3534 sublen = get_unaligned_le16(dptr);
3535 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3536 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3537 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3539 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3541 __func__, num, pfirst, pfirst->data,
3542 pfirst->len, sublen, chan, seq));
3544 ASSERT((chan == SDPCM_DATA_CHANNEL)
3545 || (chan == SDPCM_EVENT_CHANNEL));
3548 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3549 __func__, seq, rxseq));
3554 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3555 printk(KERN_DEBUG "Rx Subframe Data:\n");
3556 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3561 __skb_trim(pfirst, sublen);
3562 skb_pull(pfirst, doff);
3564 if (pfirst->len == 0) {
3565 bcm_pkt_buf_free_skb(pfirst);
3567 plast->next = pnext;
3569 ASSERT(save_pfirst == pfirst);
3570 save_pfirst = pnext;
3573 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3575 DHD_ERROR(("%s: rx protocol error\n",
3577 bus->dhd->rx_errors++;
3578 bcm_pkt_buf_free_skb(pfirst);
3580 plast->next = pnext;
3582 ASSERT(save_pfirst == pfirst);
3583 save_pfirst = pnext;
3588 /* this packet will go up, link back into
3589 chain and count it */
3590 pfirst->next = pnext;
3595 if (DHD_GLOM_ON()) {
3596 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3598 __func__, num, pfirst, pfirst->data,
3599 pfirst->len, pfirst->next,
3601 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3603 min_t(int, pfirst->len, 32));
3605 #endif /* DHD_DEBUG */
3607 dhd_os_sdunlock_rxq(bus->dhd);
3609 dhd_os_sdunlock(bus->dhd);
3610 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3611 dhd_os_sdlock(bus->dhd);
3614 bus->rxglomframes++;
3615 bus->rxglompkts += num;
3620 /* Return true if there may be more frames to read */
3621 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3623 bcmsdh_info_t *sdh = bus->sdh;
3625 u16 len, check; /* Extracted hardware header fields */
3626 u8 chan, seq, doff; /* Extracted software header fields */
3627 u8 fcbits; /* Extracted fcbits from software header */
3629 struct sk_buff *pkt; /* Packet for event or data frames */
3630 u16 pad; /* Number of pad bytes to read */
3631 u16 rdlen; /* Total number of bytes to read */
3632 u8 rxseq; /* Next sequence number to expect */
3633 uint rxleft = 0; /* Remaining number of frames allowed */
3634 int sdret; /* Return code from bcmsdh calls */
3635 u8 txmax; /* Maximum tx sequence offered */
3636 bool len_consistent; /* Result of comparing readahead len and
3640 uint rxcount = 0; /* Total frames read */
3642 #if defined(DHD_DEBUG) || defined(SDTEST)
3643 bool sdtest = false; /* To limit message spew from test mode */
3646 DHD_TRACE(("%s: Enter\n", __func__));
3651 /* Allow pktgen to override maxframes */
3652 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3653 maxframes = bus->pktgen_count;
3658 /* Not finished unless we encounter no more frames indication */
3661 for (rxseq = bus->rx_seq, rxleft = maxframes;
3662 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3663 rxseq++, rxleft--) {
3665 /* Handle glomming separately */
3666 if (bus->glom || bus->glomd) {
3668 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3669 __func__, bus->glomd, bus->glom));
3670 cnt = dhdsdio_rxglom(bus, rxseq);
3671 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3673 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3677 /* Try doing single read if we can */
3678 if (dhd_readahead && bus->nextlen) {
3679 u16 nextlen = bus->nextlen;
3682 if (bus->bus == SPI_BUS) {
3683 rdlen = len = nextlen;
3685 rdlen = len = nextlen << 4;
3687 /* Pad read to blocksize for efficiency */
3688 if (bus->roundup && bus->blocksize
3689 && (rdlen > bus->blocksize)) {
3692 (rdlen % bus->blocksize);
3693 if ((pad <= bus->roundup)
3694 && (pad < bus->blocksize)
3695 && ((rdlen + pad + firstread) <
3698 } else if (rdlen % DHD_SDALIGN) {
3700 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3704 /* We use bus->rxctl buffer in WinXP for initial
3705 * control pkt receives.
3706 * Later we use buffer-poll for data as well
3707 * as control packets.
3708 * This is required because dhd receives full
3709 * frame in gSPI unlike SDIO.
3710 * After the frame is received we have to
3711 * distinguish whether it is data
3712 * or non-data frame.
3714 /* Allocate a packet buffer */
3715 dhd_os_sdlock_rxq(bus->dhd);
3716 pkt = bcm_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3718 if (bus->bus == SPI_BUS) {
3719 bus->usebufpool = false;
3720 bus->rxctl = bus->rxbuf;
3722 bus->rxctl += firstread;
3723 pad = ((unsigned long)bus->rxctl %
3727 (DHD_SDALIGN - pad);
3728 bus->rxctl -= firstread;
3730 ASSERT(bus->rxctl >= bus->rxbuf);
3732 /* Read the entire frame */
3733 sdret = bcmsdh_recv_buf(bus,
3734 bcmsdh_cur_sbwad(sdh),
3735 SDIO_FUNC_2, F2SYNC,
3739 ASSERT(sdret != -BCME_PENDING);
3741 /* Control frame failures need
3744 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3747 /* dhd.rx_ctlerrs is higher */
3749 dhd_os_sdunlock_rxq(bus->dhd);
3750 dhdsdio_rxfail(bus, true,
3758 request rtx of events */
3759 DHD_ERROR(("%s (nextlen): "
3760 "bcm_pkt_buf_get_skb failed:"
3761 " len %d rdlen %d expected"
3762 " rxseq %d\n", __func__,
3763 len, rdlen, rxseq));
3764 /* Just go try again w/normal
3766 dhd_os_sdunlock_rxq(bus->dhd);
3770 if (bus->bus == SPI_BUS)
3771 bus->usebufpool = true;
3773 ASSERT(!(pkt->prev));
3774 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3775 rxbuf = (u8 *) (pkt->data);
3776 /* Read the entire frame */
3777 sdret = bcmsdh_recv_buf(bus,
3778 bcmsdh_cur_sbwad(sdh),
3779 SDIO_FUNC_2, F2SYNC,
3783 ASSERT(sdret != -BCME_PENDING);
3786 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3787 __func__, rdlen, sdret));
3788 bcm_pkt_buf_free_skb(pkt);
3789 bus->dhd->rx_errors++;
3790 dhd_os_sdunlock_rxq(bus->dhd);
3791 /* Force retry w/normal header read.
3792 * Don't attempt NAK for
3795 dhdsdio_rxfail(bus, true,
3802 dhd_os_sdunlock_rxq(bus->dhd);
3804 /* Now check the header */
3805 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3807 /* Extract hardware header fields */
3808 len = get_unaligned_le16(bus->rxhdr);
3809 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3811 /* All zeros means readahead info was bad */
3812 if (!(len | check)) {
3813 DHD_INFO(("%s (nextlen): read zeros in HW "
3814 "header???\n", __func__));
3815 dhdsdio_pktfree2(bus, pkt);
3819 /* Validate check bytes */
3820 if ((u16)~(len ^ check)) {
3821 DHD_ERROR(("%s (nextlen): HW hdr error:"
3822 " nextlen/len/check"
3823 " 0x%04x/0x%04x/0x%04x\n",
3824 __func__, nextlen, len, check));
3826 dhdsdio_rxfail(bus, false, false);
3827 dhdsdio_pktfree2(bus, pkt);
3831 /* Validate frame length */
3832 if (len < SDPCM_HDRLEN) {
3833 DHD_ERROR(("%s (nextlen): HW hdr length "
3834 "invalid: %d\n", __func__, len));
3835 dhdsdio_pktfree2(bus, pkt);
3839 /* Check for consistency withreadahead info */
3840 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3841 if (len_consistent) {
3842 /* Mismatch, force retry w/normal
3843 header (may be >4K) */
3844 DHD_ERROR(("%s (nextlen): mismatch, "
3845 "nextlen %d len %d rnd %d; "
3846 "expected rxseq %d\n",
3848 len, roundup(len, 16), rxseq));
3849 dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
3850 dhdsdio_pktfree2(bus, pkt);
3854 /* Extract software header fields */
3855 chan = SDPCM_PACKET_CHANNEL(
3856 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3857 seq = SDPCM_PACKET_SEQUENCE(
3858 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3859 doff = SDPCM_DOFFSET_VALUE(
3860 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3861 txmax = SDPCM_WINDOW_VALUE(
3862 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3865 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3866 SDPCM_NEXTLEN_OFFSET];
3867 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3868 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3869 __func__, bus->nextlen, seq));
3873 bus->dhd->rx_readahead_cnt++;
3875 /* Handle Flow Control */
3876 fcbits = SDPCM_FCMASK_VALUE(
3877 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3879 if (bus->flowcontrol != fcbits) {
3880 if (~bus->flowcontrol & fcbits)
3883 if (bus->flowcontrol & ~fcbits)
3887 bus->flowcontrol = fcbits;
3890 /* Check and update sequence number */
3892 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3893 "%d\n", __func__, seq, rxseq));
3898 /* Check window for sanity */
3899 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3900 DHD_ERROR(("%s: got unlikely tx max %d with "
3902 __func__, txmax, bus->tx_seq));
3903 txmax = bus->tx_seq + 2;
3905 bus->tx_max = txmax;
3908 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3909 printk(KERN_DEBUG "Rx Data:\n");
3910 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3912 } else if (DHD_HDRS_ON()) {
3913 printk(KERN_DEBUG "RxHdr:\n");
3914 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3915 bus->rxhdr, SDPCM_HDRLEN);
3919 if (chan == SDPCM_CONTROL_CHANNEL) {
3920 if (bus->bus == SPI_BUS) {
3921 dhdsdio_read_control(bus, rxbuf, len,
3924 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3926 /* Force retry w/normal header read */
3928 dhdsdio_rxfail(bus, false, true);
3930 dhdsdio_pktfree2(bus, pkt);
3934 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3935 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3940 /* Validate data offset */
3941 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3942 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3943 __func__, doff, len, SDPCM_HDRLEN));
3944 dhdsdio_rxfail(bus, false, false);
3945 dhdsdio_pktfree2(bus, pkt);
3949 /* All done with this one -- now deliver the packet */
3952 /* gSPI frames should not be handled in fractions */
3953 if (bus->bus == SPI_BUS)
3956 /* Read frame header (hardware and software) */
3957 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
3958 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
3961 ASSERT(sdret != -BCME_PENDING);
3964 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3967 dhdsdio_rxfail(bus, true, true);
3971 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
3972 printk(KERN_DEBUG "RxHdr:\n");
3973 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3974 bus->rxhdr, SDPCM_HDRLEN);
3978 /* Extract hardware header fields */
3979 len = get_unaligned_le16(bus->rxhdr);
3980 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3982 /* All zeros means no more frames */
3983 if (!(len | check)) {
3988 /* Validate check bytes */
3989 if ((u16) ~(len ^ check)) {
3990 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3991 __func__, len, check));
3993 dhdsdio_rxfail(bus, false, false);
3997 /* Validate frame length */
3998 if (len < SDPCM_HDRLEN) {
3999 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4004 /* Extract software header fields */
4005 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4006 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4007 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4008 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4010 /* Validate data offset */
4011 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4012 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4014 __func__, doff, len, SDPCM_HDRLEN, seq));
4017 dhdsdio_rxfail(bus, false, false);
4021 /* Save the readahead length if there is one */
4023 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4024 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4025 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4027 __func__, bus->nextlen, seq));
4031 /* Handle Flow Control */
4032 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4034 if (bus->flowcontrol != fcbits) {
4035 if (~bus->flowcontrol & fcbits)
4038 if (bus->flowcontrol & ~fcbits)
4042 bus->flowcontrol = fcbits;
4045 /* Check and update sequence number */
4047 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4053 /* Check window for sanity */
4054 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4055 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4056 __func__, txmax, bus->tx_seq));
4057 txmax = bus->tx_seq + 2;
4059 bus->tx_max = txmax;
4061 /* Call a separate function for control frames */
4062 if (chan == SDPCM_CONTROL_CHANNEL) {
4063 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4067 ASSERT((chan == SDPCM_DATA_CHANNEL)
4068 || (chan == SDPCM_EVENT_CHANNEL)
4069 || (chan == SDPCM_TEST_CHANNEL)
4070 || (chan == SDPCM_GLOM_CHANNEL));
4072 /* Length to read */
4073 rdlen = (len > firstread) ? (len - firstread) : 0;
4075 /* May pad read to blocksize for efficiency */
4076 if (bus->roundup && bus->blocksize &&
4077 (rdlen > bus->blocksize)) {
4078 pad = bus->blocksize - (rdlen % bus->blocksize);
4079 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4080 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4082 } else if (rdlen % DHD_SDALIGN) {
4083 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4086 /* Satisfy length-alignment requirements */
4087 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4088 rdlen = roundup(rdlen, ALIGNMENT);
4090 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4091 /* Too long -- skip this frame */
4092 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4093 __func__, len, rdlen));
4094 bus->dhd->rx_errors++;
4096 dhdsdio_rxfail(bus, false, false);
4100 dhd_os_sdlock_rxq(bus->dhd);
4101 pkt = bcm_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4103 /* Give up on data, request rtx of events */
4104 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed: rdlen %d "
4105 "chan %d\n", __func__, rdlen, chan));
4106 bus->dhd->rx_dropped++;
4107 dhd_os_sdunlock_rxq(bus->dhd);
4108 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4111 dhd_os_sdunlock_rxq(bus->dhd);
4113 ASSERT(!(pkt->prev));
4115 /* Leave room for what we already read, and align remainder */
4116 ASSERT(firstread < pkt->len);
4117 skb_pull(pkt, firstread);
4118 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4120 /* Read the remaining frame data */
4121 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4122 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4125 ASSERT(sdret != -BCME_PENDING);
4128 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4131 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4133 ? "data" : "test")),
4135 dhd_os_sdlock_rxq(bus->dhd);
4136 bcm_pkt_buf_free_skb(pkt);
4137 dhd_os_sdunlock_rxq(bus->dhd);
4138 bus->dhd->rx_errors++;
4139 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4143 /* Copy the already-read portion */
4144 skb_push(pkt, firstread);
4145 memcpy(pkt->data, bus->rxhdr, firstread);
4148 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4149 printk(KERN_DEBUG "Rx Data:\n");
4150 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4156 /* Save superframe descriptor and allocate packet frame */
4157 if (chan == SDPCM_GLOM_CHANNEL) {
4158 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4159 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4162 if (DHD_GLOM_ON()) {
4163 printk(KERN_DEBUG "Glom Data:\n");
4164 print_hex_dump_bytes("",
4169 __skb_trim(pkt, len);
4170 ASSERT(doff == SDPCM_HDRLEN);
4171 skb_pull(pkt, SDPCM_HDRLEN);
4174 DHD_ERROR(("%s: glom superframe w/o "
4175 "descriptor!\n", __func__));
4176 dhdsdio_rxfail(bus, false, false);
4181 /* Fill in packet len and prio, deliver upward */
4182 __skb_trim(pkt, len);
4183 skb_pull(pkt, doff);
4186 /* Test channel packets are processed separately */
4187 if (chan == SDPCM_TEST_CHANNEL) {
4188 dhdsdio_testrcv(bus, pkt, seq);
4193 if (pkt->len == 0) {
4194 dhd_os_sdlock_rxq(bus->dhd);
4195 bcm_pkt_buf_free_skb(pkt);
4196 dhd_os_sdunlock_rxq(bus->dhd);
4198 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4199 DHD_ERROR(("%s: rx protocol error\n", __func__));
4200 dhd_os_sdlock_rxq(bus->dhd);
4201 bcm_pkt_buf_free_skb(pkt);
4202 dhd_os_sdunlock_rxq(bus->dhd);
4203 bus->dhd->rx_errors++;
4207 /* Unlock during rx call */
4208 dhd_os_sdunlock(bus->dhd);
4209 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4210 dhd_os_sdlock(bus->dhd);
4212 rxcount = maxframes - rxleft;
4214 /* Message if we hit the limit */
4215 if (!rxleft && !sdtest)
4216 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4219 #endif /* DHD_DEBUG */
4220 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4221 /* Back off rxseq if awaiting rtx, update rx_seq */
4224 bus->rx_seq = rxseq;
4229 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4231 sdpcmd_regs_t *regs = bus->regs;
4237 DHD_TRACE(("%s: Enter\n", __func__));
4239 /* Read mailbox data and ack that we did so */
4240 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4241 if (retries <= retry_limit)
4242 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4243 bus->f1regdata += 2;
4245 /* Dongle recomposed rx frames, accept them again */
4246 if (hmb_data & HMB_DATA_NAKHANDLED) {
4247 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4250 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4252 bus->rxskip = false;
4253 intstatus |= I_HMB_FRAME_IND;
4257 * DEVREADY does not occur with gSPI.
4259 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4261 (hmb_data & HMB_DATA_VERSION_MASK) >>
4262 HMB_DATA_VERSION_SHIFT;
4263 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4264 DHD_ERROR(("Version mismatch, dongle reports %d, "
4266 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4268 DHD_INFO(("Dongle ready, protocol version %d\n",
4273 * Flow Control has been moved into the RX headers and this out of band
4274 * method isn't used any more.
4275 * remaining backward compatible with older dongles.
4277 if (hmb_data & HMB_DATA_FC) {
4278 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4279 HMB_DATA_FCDATA_SHIFT;
4281 if (fcbits & ~bus->flowcontrol)
4284 if (bus->flowcontrol & ~fcbits)
4288 bus->flowcontrol = fcbits;
4291 /* Shouldn't be any others */
4292 if (hmb_data & ~(HMB_DATA_DEVREADY |
4293 HMB_DATA_NAKHANDLED |
4296 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4297 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4303 bool dhdsdio_dpc(dhd_bus_t *bus)
4305 bcmsdh_info_t *sdh = bus->sdh;
4306 sdpcmd_regs_t *regs = bus->regs;
4307 u32 intstatus, newstatus = 0;
4309 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4310 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4311 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4312 bool rxdone = true; /* Flag for no more read data */
4313 bool resched = false; /* Flag indicating resched wanted */
4315 DHD_TRACE(("%s: Enter\n", __func__));
4317 /* Start with leftover status bits */
4318 intstatus = bus->intstatus;
4320 dhd_os_sdlock(bus->dhd);
4322 /* If waiting for HTAVAIL, check status */
4323 if (bus->clkstate == CLK_PENDING) {
4325 u8 clkctl, devctl = 0;
4328 /* Check for inconsistent device control */
4330 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4332 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4334 bus->dhd->busstate = DHD_BUS_DOWN;
4336 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4338 #endif /* DHD_DEBUG */
4340 /* Read CSR, if clock on switch to AVAIL, else ignore */
4342 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4345 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4347 bus->dhd->busstate = DHD_BUS_DOWN;
4350 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4353 if (SBSDIO_HTAV(clkctl)) {
4355 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4358 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4360 bus->dhd->busstate = DHD_BUS_DOWN;
4362 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4363 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4366 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4368 bus->dhd->busstate = DHD_BUS_DOWN;
4370 bus->clkstate = CLK_AVAIL;
4378 /* Make sure backplane clock is on */
4379 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4380 if (bus->clkstate == CLK_PENDING)
4383 /* Pending interrupt indicates new device status */
4386 R_SDREG(newstatus, ®s->intstatus, retries);
4388 if (bcmsdh_regfail(bus->sdh))
4390 newstatus &= bus->hostintmask;
4391 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4393 W_SDREG(newstatus, ®s->intstatus, retries);
4398 /* Merge new bits with previous */
4399 intstatus |= newstatus;
4402 /* Handle flow-control change: read new state in case our ack
4403 * crossed another change interrupt. If change still set, assume
4404 * FC ON for safety, let next loop through do the debounce.
4406 if (intstatus & I_HMB_FC_CHANGE) {
4407 intstatus &= ~I_HMB_FC_CHANGE;
4408 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4409 R_SDREG(newstatus, ®s->intstatus, retries);
4410 bus->f1regdata += 2;
4412 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4413 intstatus |= (newstatus & bus->hostintmask);
4416 /* Handle host mailbox indication */
4417 if (intstatus & I_HMB_HOST_INT) {
4418 intstatus &= ~I_HMB_HOST_INT;
4419 intstatus |= dhdsdio_hostmail(bus);
4422 /* Generally don't ask for these, can get CRC errors... */
4423 if (intstatus & I_WR_OOSYNC) {
4424 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4425 intstatus &= ~I_WR_OOSYNC;
4428 if (intstatus & I_RD_OOSYNC) {
4429 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4430 intstatus &= ~I_RD_OOSYNC;
4433 if (intstatus & I_SBINT) {
4434 DHD_ERROR(("Dongle reports SBINT\n"));
4435 intstatus &= ~I_SBINT;
4438 /* Would be active due to wake-wlan in gSPI */
4439 if (intstatus & I_CHIPACTIVE) {
4440 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4441 intstatus &= ~I_CHIPACTIVE;
4444 /* Ignore frame indications if rxskip is set */
4446 intstatus &= ~I_HMB_FRAME_IND;
4448 /* On frame indication, read available frames */
4449 if (PKT_AVAILABLE()) {
4450 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4451 if (rxdone || bus->rxskip)
4452 intstatus &= ~I_HMB_FRAME_IND;
4453 rxlimit -= min(framecnt, rxlimit);
4456 /* Keep still-pending events for next scheduling */
4457 bus->intstatus = intstatus;
4460 #if defined(OOB_INTR_ONLY)
4461 bcmsdh_oob_intr_set(1);
4462 #endif /* (OOB_INTR_ONLY) */
4463 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4464 * or clock availability. (Allows tx loop to check ipend if desired.)
4465 * (Unless register access seems hosed, as we may not be able to ACK...)
4467 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4468 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4469 __func__, rxdone, framecnt));
4470 bus->intdis = false;
4471 bcmsdh_intr_enable(sdh);
4474 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4475 (bus->clkstate == CLK_AVAIL)) {
4479 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4480 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4481 (u32) bus->ctrl_frame_len, NULL,
4483 ASSERT(ret != -BCME_PENDING);
4486 /* On failure, abort the command and
4487 terminate the frame */
4488 DHD_INFO(("%s: sdio error %d, abort command and "
4489 "terminate frame.\n", __func__, ret));
4492 bcmsdh_abort(sdh, SDIO_FUNC_2);
4494 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4495 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4499 for (i = 0; i < 3; i++) {
4501 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4502 SBSDIO_FUNC1_WFRAMEBCHI,
4504 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4505 SBSDIO_FUNC1_WFRAMEBCLO,
4507 bus->f1regdata += 2;
4508 if ((hi == 0) && (lo == 0))
4514 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4516 DHD_INFO(("Return_dpc value is : %d\n", ret));
4517 bus->ctrl_frame_stat = false;
4518 dhd_wait_event_wakeup(bus->dhd);
4520 /* Send queued frames (limit 1 if rx may still be pending) */
4521 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4522 bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4524 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4525 framecnt = dhdsdio_sendfromq(bus, framecnt);
4526 txlimit -= framecnt;
4529 /* Resched if events or tx frames are pending,
4530 else await next interrupt */
4531 /* On failed register access, all bets are off:
4532 no resched or interrupts */
4533 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4534 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4535 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4536 bus->dhd->busstate = DHD_BUS_DOWN;
4538 } else if (bus->clkstate == CLK_PENDING) {
4539 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4540 "I_CHIPACTIVE interrupt\n", __func__));
4542 } else if (bus->intstatus || bus->ipend ||
4543 (!bus->fcstate && bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4544 DATAOK(bus)) || PKT_AVAILABLE()) {
4548 bus->dpc_sched = resched;
4550 /* If we're done for now, turn off clock request. */
4551 if ((bus->clkstate != CLK_PENDING)
4552 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4553 bus->activity = false;
4554 dhdsdio_clkctl(bus, CLK_NONE, false);
4557 dhd_os_sdunlock(bus->dhd);
4562 bool dhd_bus_dpc(struct dhd_bus *bus)
4566 /* Call the DPC directly. */
4567 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4568 resched = dhdsdio_dpc(bus);
4573 void dhdsdio_isr(void *arg)
4575 dhd_bus_t *bus = (dhd_bus_t *) arg;
4578 DHD_TRACE(("%s: Enter\n", __func__));
4581 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4586 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4587 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4591 /* Count the interrupt call */
4595 /* Shouldn't get this interrupt if we're sleeping? */
4596 if (bus->sleeping) {
4597 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4601 /* Disable additional interrupts (is this needed now)? */
4603 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4605 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4607 bcmsdh_intr_disable(sdh);
4610 #if defined(SDIO_ISR_THREAD)
4611 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4612 while (dhdsdio_dpc(bus))
4615 bus->dpc_sched = true;
4616 dhd_sched_dpc(bus->dhd);
4622 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4624 /* Default to specified length, or full range */
4625 if (dhd_pktgen_len) {
4626 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4627 bus->pktgen_minlen = bus->pktgen_maxlen;
4629 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4630 bus->pktgen_minlen = 0;
4632 bus->pktgen_len = (u16) bus->pktgen_minlen;
4634 /* Default to per-watchdog burst with 10s print time */
4635 bus->pktgen_freq = 1;
4636 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4637 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4639 /* Default to echo mode */
4640 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4641 bus->pktgen_stop = 1;
4644 static void dhdsdio_pktgen(dhd_bus_t *bus)
4646 struct sk_buff *pkt;
4652 /* Display current count if appropriate */
4653 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4654 bus->pktgen_ptick = 0;
4655 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4656 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4659 /* For recv mode, just make sure dongle has started sending */
4660 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4661 if (!bus->pktgen_rcvd)
4662 dhdsdio_sdtest_set(bus, true);
4666 /* Otherwise, generate or request the specified number of packets */
4667 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4668 /* Stop if total has been reached */
4669 if (bus->pktgen_total
4670 && (bus->pktgen_sent >= bus->pktgen_total)) {
4671 bus->pktgen_count = 0;
4675 /* Allocate an appropriate-sized packet */
4676 len = bus->pktgen_len;
4677 pkt = bcm_pkt_buf_get_skb(
4678 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4681 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n",
4685 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4687 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4689 /* Write test header cmd and extra based on mode */
4690 switch (bus->pktgen_mode) {
4691 case DHD_PKTGEN_ECHO:
4692 *data++ = SDPCM_TEST_ECHOREQ;
4693 *data++ = (u8) bus->pktgen_sent;
4696 case DHD_PKTGEN_SEND:
4697 *data++ = SDPCM_TEST_DISCARD;
4698 *data++ = (u8) bus->pktgen_sent;
4701 case DHD_PKTGEN_RXBURST:
4702 *data++ = SDPCM_TEST_BURST;
4703 *data++ = (u8) bus->pktgen_count;
4707 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4709 bcm_pkt_buf_free_skb(pkt, true);
4710 bus->pktgen_count = 0;
4714 /* Write test header length field */
4715 *data++ = (len >> 0);
4716 *data++ = (len >> 8);
4718 /* Then fill in the remainder -- N/A for burst,
4720 for (fillbyte = 0; fillbyte < len; fillbyte++)
4722 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4725 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4726 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4727 printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
4728 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4729 pkt->len - SDPCM_HDRLEN);
4734 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4736 if (bus->pktgen_stop
4737 && bus->pktgen_stop == bus->pktgen_fail)
4738 bus->pktgen_count = 0;
4742 /* Bump length if not fixed, wrap at max */
4743 if (++bus->pktgen_len > bus->pktgen_maxlen)
4744 bus->pktgen_len = (u16) bus->pktgen_minlen;
4746 /* Special case for burst mode: just send one request! */
4747 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4752 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4754 struct sk_buff *pkt;
4757 /* Allocate the packet */
4758 pkt = bcm_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4761 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n", __func__));
4764 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4765 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4767 /* Fill in the test header */
4768 *data++ = SDPCM_TEST_SEND;
4770 *data++ = (bus->pktgen_maxlen >> 0);
4771 *data++ = (bus->pktgen_maxlen >> 8);
4774 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4778 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4788 /* Check for min length */
4790 if (pktlen < SDPCM_TEST_HDRLEN) {
4791 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4793 bcm_pkt_buf_free_skb(pkt, false);
4797 /* Extract header fields */
4802 len += *data++ << 8;
4804 /* Check length for relevant commands */
4805 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4806 || cmd == SDPCM_TEST_ECHORSP) {
4807 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4808 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4809 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4810 pktlen, seq, cmd, extra, len));
4811 bcm_pkt_buf_free_skb(pkt, false);
4816 /* Process as per command */
4818 case SDPCM_TEST_ECHOREQ:
4819 /* Rx->Tx turnaround ok (even on NDIS w/current
4821 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4822 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4826 bcm_pkt_buf_free_skb(pkt, false);
4831 case SDPCM_TEST_ECHORSP:
4832 if (bus->ext_loop) {
4833 bcm_pkt_buf_free_skb(pkt, false);
4838 for (offset = 0; offset < len; offset++, data++) {
4839 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4840 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4842 SDPCM_TEST_FILL(offset, extra), *data));
4846 bcm_pkt_buf_free_skb(pkt, false);
4850 case SDPCM_TEST_DISCARD:
4851 bcm_pkt_buf_free_skb(pkt, false);
4855 case SDPCM_TEST_BURST:
4856 case SDPCM_TEST_SEND:
4858 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4859 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4860 pktlen, seq, cmd, extra, len));
4861 bcm_pkt_buf_free_skb(pkt, false);
4865 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4866 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4867 if (bus->pktgen_total
4868 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4869 bus->pktgen_count = 0;
4870 dhdsdio_sdtest_set(bus, false);
4876 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4880 DHD_TIMER(("%s: Enter\n", __func__));
4884 if (bus->dhd->dongle_reset)
4887 /* Ignore the timer if simulating bus down */
4891 dhd_os_sdlock(bus->dhd);
4893 /* Poll period: check device if appropriate. */
4894 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4897 /* Reset poll tick */
4900 /* Check device if no interrupts */
4901 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4903 if (!bus->dpc_sched) {
4905 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4909 devpend & (INTR_STATUS_FUNC1 |
4913 /* If there is something, make like the ISR and
4919 bcmsdh_intr_disable(bus->sdh);
4921 bus->dpc_sched = true;
4922 dhd_sched_dpc(bus->dhd);
4927 /* Update interrupt tracking */
4928 bus->lastintrs = bus->intrcount;
4931 /* Poll for console output periodically */
4932 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4933 bus->console.count += dhd_watchdog_ms;
4934 if (bus->console.count >= dhd_console_ms) {
4935 bus->console.count -= dhd_console_ms;
4936 /* Make sure backplane clock is on */
4937 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4938 if (dhdsdio_readconsole(bus) < 0)
4939 dhd_console_ms = 0; /* On error,
4943 #endif /* DHD_DEBUG */
4946 /* Generate packets if configured */
4947 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4948 /* Make sure backplane clock is on */
4949 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4950 bus->pktgen_tick = 0;
4951 dhdsdio_pktgen(bus);
4955 /* On idle timeout clear activity flag and/or turn off clock */
4956 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4957 if (++bus->idlecount >= bus->idletime) {
4959 if (bus->activity) {
4960 bus->activity = false;
4961 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4963 dhdsdio_clkctl(bus, CLK_NONE, false);
4968 dhd_os_sdunlock(bus->dhd);
4974 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4976 dhd_bus_t *bus = dhdp->bus;
4979 struct sk_buff *pkt;
4981 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4982 if (bus->console_addr == 0)
4985 /* Exclusive bus access */
4986 dhd_os_sdlock(bus->dhd);
4988 /* Don't allow input if dongle is in reset */
4989 if (bus->dhd->dongle_reset) {
4990 dhd_os_sdunlock(bus->dhd);
4994 /* Request clock to allow SDIO accesses */
4996 /* No pend allowed since txpkt is called later, ht clk has to be on */
4997 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4999 /* Zero cbuf_index */
5000 addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5001 val = cpu_to_le32(0);
5002 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5006 /* Write message into cbuf */
5007 addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5008 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
5012 /* Write length into vcons_in */
5013 addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5014 val = cpu_to_le32(msglen);
5015 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5019 /* Bump dongle by sending an empty event pkt.
5020 * sdpcm_sendup (RX) checks for virtual console input.
5022 pkt = bcm_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5023 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5024 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5027 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5028 bus->activity = false;
5029 dhdsdio_clkctl(bus, CLK_NONE, true);
5032 dhd_os_sdunlock(bus->dhd);
5036 #endif /* DHD_DEBUG */
5039 static void dhd_dump_cis(uint fn, u8 *cis)
5041 uint byte, tag, tdata;
5042 DHD_INFO(("Function %d CIS:\n", fn));
5044 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5045 if ((byte % 16) == 0)
5047 DHD_INFO(("%02x ", cis[byte]));
5048 if ((byte % 16) == 15)
5056 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5057 tdata = cis[byte + 1] + 1;
5062 if ((byte % 16) != 15)
5065 #endif /* DHD_DEBUG */
5067 static bool dhdsdio_chipmatch(u16 chipid)
5069 if (chipid == BCM4325_CHIP_ID)
5071 if (chipid == BCM4329_CHIP_ID)
5073 if (chipid == BCM4319_CHIP_ID)
5078 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5079 u16 slot, u16 func, uint bustype, void *regsva,
5085 /* Init global variables at run-time, not as part of the declaration.
5086 * This is required to support init/de-init of the driver.
5088 * of globals as part of the declaration results in non-deterministic
5089 * behavior since the value of the globals may be different on the
5090 * first time that the driver is initialized vs subsequent
5093 dhd_txbound = DHD_TXBOUND;
5094 dhd_rxbound = DHD_RXBOUND;
5095 dhd_alignctl = true;
5097 dhd_readahead = true;
5099 dhd_dongle_memsize = 0;
5100 dhd_txminmax = DHD_TXMINMAX;
5106 DHD_TRACE(("%s: Enter\n", __func__));
5107 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5109 /* We make assumptions about address window mappings */
5110 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5112 /* BCMSDH passes venid and devid based on CIS parsing -- but
5114 * means early parse could fail, so here we should get either an ID
5115 * we recognize OR (-1) indicating we must request power first.
5117 /* Check the Vendor ID */
5120 case PCI_VENDOR_ID_BROADCOM:
5123 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5127 /* Check the Device ID and make sure it's one that we support */
5129 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5130 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5131 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5132 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5134 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5135 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5136 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5138 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5140 case BCM4319_D11N_ID: /* 4319 802.11n id */
5141 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5142 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5143 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5146 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5151 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5152 __func__, venid, devid));
5156 /* Allocate private bus interface state */
5157 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5159 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5163 bus->cl_devid = (u16) devid;
5165 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5166 bus->usebufpool = false; /* Use bufpool if allocated,
5167 else use locally malloced rxbuf */
5169 /* attempt to attach to the dongle */
5170 if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5171 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5175 /* Attach to the dhd/OS/network interface */
5176 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5178 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5182 /* Allocate buffers */
5183 if (!(dhdsdio_probe_malloc(bus, sdh))) {
5184 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5188 if (!(dhdsdio_probe_init(bus, sdh))) {
5189 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5193 /* Register interrupt callback, but mask it (not operational yet). */
5194 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5196 bcmsdh_intr_disable(sdh);
5197 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5199 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5203 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5205 DHD_INFO(("%s: completed!!\n", __func__));
5207 /* if firmware path present try to download and bring up bus */
5208 ret = dhd_bus_start(bus->dhd);
5210 if (ret == -ENOLINK) {
5211 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5215 /* Ok, have the per-port tell the stack we're open for business */
5216 if (dhd_net_attach(bus->dhd, 0) != 0) {
5217 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5224 dhdsdio_release(bus);
5229 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5234 bus->alp_only = true;
5236 /* Return the window to backplane enumeration space for core access */
5237 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5238 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5241 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5242 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5244 #endif /* DHD_DEBUG */
5247 * Force PLL off until dhdsdio_chip_attach()
5248 * programs PLL control regs
5251 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5252 DHD_INIT_CLKCTL1, &err);
5255 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5258 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5259 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5260 "0x%02x read 0x%02x\n",
5261 err, DHD_INIT_CLKCTL1, clkctl));
5265 if (DHD_INFO_ON()) {
5267 u8 *cis[SDIOD_MAX_IOFUNCS];
5270 numfn = bcmsdh_query_iofnum(sdh);
5271 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5273 /* Make sure ALP is available before trying to read CIS */
5274 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5275 SBSDIO_FUNC1_CHIPCLKCSR,
5277 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5279 /* Now request ALP be put on the bus */
5280 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5281 DHD_INIT_CLKCTL2, &err);
5284 for (fn = 0; fn <= numfn; fn++) {
5285 cis[fn] = kzalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5287 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5292 err = bcmsdh_cis_read(sdh, fn, cis[fn],
5293 SBSDIO_CIS_SIZE_LIMIT);
5295 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5296 "err %d\n", fn, err));
5300 dhd_dump_cis(fn, cis[fn]);
5309 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5313 #endif /* DHD_DEBUG */
5315 if (dhdsdio_chip_attach(bus, regsva)) {
5316 DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
5320 bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5322 if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
5323 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5324 __func__, bus->ci->chip));
5328 dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5330 /* Get info on the ARM and SOCRAM cores... */
5331 if (!DHD_NOPMU(bus)) {
5332 bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
5333 CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5334 bus->orig_ramsize = bus->ci->ramsize;
5335 if (!(bus->orig_ramsize)) {
5336 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5340 bus->ramsize = bus->orig_ramsize;
5341 if (dhd_dongle_memsize)
5342 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5344 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5345 bus->ramsize, bus->orig_ramsize));
5348 bus->regs = (void *)bus->ci->buscorebase;
5350 /* Set core control so an SDIO reset does a backplane reset */
5351 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5353 bcm_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5355 /* Locate an appropriately-aligned portion of hdrbuf */
5356 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5358 /* Set the poll and/or interrupt flags */
5359 bus->intr = (bool) dhd_intr;
5360 bus->poll = (bool) dhd_poll;
5370 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5372 DHD_TRACE(("%s: Enter\n", __func__));
5374 if (bus->dhd->maxctl) {
5376 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5377 ALIGNMENT) + DHD_SDALIGN;
5378 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5379 if (!(bus->rxbuf)) {
5380 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5381 __func__, bus->rxblen));
5386 /* Allocate buffer to receive glomed packet */
5387 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5388 if (!(bus->databuf)) {
5389 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5390 __func__, MAX_DATA_BUF));
5391 /* release rxbuf which was already located as above */
5397 /* Align the buffer */
5398 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5400 bus->databuf + (DHD_SDALIGN -
5401 ((unsigned long)bus->databuf % DHD_SDALIGN));
5403 bus->dataptr = bus->databuf;
5411 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5415 DHD_TRACE(("%s: Enter\n", __func__));
5418 dhdsdio_pktgen_init(bus);
5421 /* Disable F2 to clear any intermediate frame state on the dongle */
5422 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5425 bus->dhd->busstate = DHD_BUS_DOWN;
5426 bus->sleeping = false;
5427 bus->rxflow = false;
5428 bus->prev_rxlim_hit = 0;
5430 /* Done with backplane-dependent accesses, can drop clock... */
5431 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5433 /* ...and initialize clock/power states */
5434 bus->clkstate = CLK_SDONLY;
5435 bus->idletime = (s32) dhd_idletime;
5436 bus->idleclock = DHD_IDLE_ACTIVE;
5438 /* Query the F2 block size, set roundup accordingly */
5440 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5441 &bus->blocksize, sizeof(s32), false) != 0) {
5443 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5445 DHD_INFO(("%s: Initial value for %s is %d\n",
5446 __func__, "sd_blocksize", bus->blocksize));
5448 bus->roundup = min(max_roundup, bus->blocksize);
5450 /* Query if bus module supports packet chaining,
5451 default to use if supported */
5452 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5453 &bus->sd_rxchain, sizeof(s32),
5455 bus->sd_rxchain = false;
5457 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5459 (bus->sd_rxchain ? "supports" : "does not support")));
5461 bus->use_rxchain = (bool) bus->sd_rxchain;
5467 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5470 bus->fw_path = fw_path;
5471 bus->nv_path = nv_path;
5473 ret = dhdsdio_download_firmware(bus, bus->sdh);
5479 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5483 /* Download the firmware */
5484 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5486 ret = _dhdsdio_download_firmware(bus) == 0;
5488 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5493 /* Detach and free everything */
5494 static void dhdsdio_release(dhd_bus_t *bus)
5496 DHD_TRACE(("%s: Enter\n", __func__));
5499 /* De-register interrupt handler */
5500 bcmsdh_intr_disable(bus->sdh);
5501 bcmsdh_intr_dereg(bus->sdh);
5504 dhd_detach(bus->dhd);
5505 dhdsdio_release_dongle(bus);
5509 dhdsdio_release_malloc(bus);
5514 DHD_TRACE(("%s: Disconnected\n", __func__));
5517 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5519 DHD_TRACE(("%s: Enter\n", __func__));
5521 if (bus->dhd && bus->dhd->dongle_reset)
5526 bus->rxctl = bus->rxbuf = NULL;
5530 kfree(bus->databuf);
5531 bus->databuf = NULL;
5534 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5536 DHD_TRACE(("%s: Enter\n", __func__));
5538 if (bus->dhd && bus->dhd->dongle_reset)
5542 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5543 dhdsdio_clkctl(bus, CLK_NONE, false);
5544 dhdsdio_chip_detach(bus);
5545 if (bus->vars && bus->varsz)
5550 DHD_TRACE(("%s: Disconnected\n", __func__));
5553 static void dhdsdio_disconnect(void *ptr)
5555 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5557 DHD_TRACE(("%s: Enter\n", __func__));
5561 dhdsdio_release(bus);
5564 DHD_TRACE(("%s: Disconnected\n", __func__));
5567 /* Register/Unregister functions are called by the main DHD entry
5568 * point (e.g. module insertion) to link with the bus driver, in
5569 * order to look for or await the device.
5572 static bcmsdh_driver_t dhd_sdio = {
5577 int dhd_bus_register(void)
5579 DHD_TRACE(("%s: Enter\n", __func__));
5581 return bcmsdh_register(&dhd_sdio);
5584 void dhd_bus_unregister(void)
5586 DHD_TRACE(("%s: Enter\n", __func__));
5588 bcmsdh_unregister();
5591 #ifdef BCMEMBEDIMAGE
5592 static int dhdsdio_download_code_array(struct dhd_bus *bus)
5597 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5599 /* Download image */
5600 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5602 dhdsdio_membytes(bus, true, offset, dlarray + offset,
5605 DHD_ERROR(("%s: error %d on writing %d membytes at "
5607 __func__, bcmerror, MEMBLOCK, offset));
5614 if (offset < sizeof(dlarray)) {
5615 bcmerror = dhdsdio_membytes(bus, true, offset,
5617 sizeof(dlarray) - offset);
5619 DHD_ERROR(("%s: error %d on writing %d membytes at "
5620 "0x%08x\n", __func__, bcmerror,
5621 sizeof(dlarray) - offset, offset));
5626 /* Upload and compare the downloaded code */
5628 unsigned char *ularray;
5630 ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
5635 /* Upload image to verify downloaded contents. */
5637 memset(ularray, 0xaa, bus->ramsize);
5638 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5640 dhdsdio_membytes(bus, false, offset,
5641 ularray + offset, MEMBLOCK);
5643 DHD_ERROR(("%s: error %d on reading %d membytes"
5645 __func__, bcmerror, MEMBLOCK, offset));
5652 if (offset < sizeof(dlarray)) {
5653 bcmerror = dhdsdio_membytes(bus, false, offset,
5655 sizeof(dlarray) - offset);
5657 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5659 sizeof(dlarray) - offset, offset));
5664 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5665 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5670 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5675 #endif /* DHD_DEBUG */
5680 #endif /* BCMEMBEDIMAGE */
5682 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5688 u8 *memblock = NULL, *memptr;
5690 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5692 image = dhd_os_open_image(fw_path);
5696 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5697 if (memblock == NULL) {
5698 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5699 __func__, MEMBLOCK));
5702 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5704 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5706 /* Download image */
5708 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5709 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5711 DHD_ERROR(("%s: error %d on writing %d membytes at "
5712 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5723 dhd_os_close_image(image);
5729 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5730 * and ending in a NUL.
5731 * Removes carriage returns, empty lines, comment lines, and converts
5733 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5737 static uint process_nvram_vars(char *varbuf, uint len)
5746 findNewline = false;
5749 for (n = 0; n < len; n++) {
5752 if (varbuf[n] == '\r')
5754 if (findNewline && varbuf[n] != '\n')
5756 findNewline = false;
5757 if (varbuf[n] == '#') {
5761 if (varbuf[n] == '\n') {
5771 buf_len = dp - varbuf;
5773 while (dp < varbuf + n)
5780 EXAMPLE: nvram_array
5783 Use carriage return at the end of each assignment,
5784 and an empty string with
5785 carriage return at the end of array.
5788 unsigned char nvram_array[] = {"name1=value1\n",
5789 "name2=value2\n", "\n"};
5790 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5792 Search "EXAMPLE: nvram_array" to see how the array is activated.
5795 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5797 bus->nvram_params = nvram_params;
5800 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5805 char *memblock = NULL;
5808 bool nvram_file_exists;
5810 nv_path = bus->nv_path;
5812 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5813 if (!nvram_file_exists && (bus->nvram_params == NULL))
5816 if (nvram_file_exists) {
5817 image = dhd_os_open_image(nv_path);
5822 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5823 if (memblock == NULL) {
5824 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5825 __func__, MEMBLOCK));
5829 /* Download variables */
5830 if (nvram_file_exists) {
5831 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5833 len = strlen(bus->nvram_params);
5834 ASSERT(len <= MEMBLOCK);
5837 memcpy(memblock, bus->nvram_params, len);
5840 if (len > 0 && len < MEMBLOCK) {
5841 bufp = (char *)memblock;
5843 len = process_nvram_vars(bufp, len);
5847 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5849 DHD_ERROR(("%s: error downloading vars: %d\n",
5850 __func__, bcmerror));
5853 DHD_ERROR(("%s: error reading nvram file: %d\n",
5862 dhd_os_close_image(image);
5867 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5871 bool embed = false; /* download embedded firmware */
5872 bool dlok = false; /* download firmware succeeded */
5874 /* Out immediately if no image to download */
5875 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5876 #ifdef BCMEMBEDIMAGE
5883 /* Keep arm in reset */
5884 if (dhdsdio_download_state(bus, true)) {
5885 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5889 /* External image takes precedence if specified */
5890 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5891 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5892 DHD_ERROR(("%s: dongle image file download failed\n",
5894 #ifdef BCMEMBEDIMAGE
5904 #ifdef BCMEMBEDIMAGE
5906 if (dhdsdio_download_code_array(bus)) {
5907 DHD_ERROR(("%s: dongle image array download failed\n",
5916 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5920 /* EXAMPLE: nvram_array */
5921 /* If a valid nvram_arry is specified as above, it can be passed
5923 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5925 /* External nvram takes precedence if specified */
5926 if (dhdsdio_download_nvram(bus)) {
5927 DHD_ERROR(("%s: dongle nvram file download failed\n",
5931 /* Take arm out of reset */
5932 if (dhdsdio_download_state(bus, false)) {
5933 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5946 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5947 u8 *buf, uint nbytes, struct sk_buff *pkt,
5948 bcmsdh_cmplt_fn_t complete, void *handle)
5950 return bcmsdh_send_buf
5951 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5955 uint dhd_bus_chip(struct dhd_bus *bus)
5957 ASSERT(bus->ci != NULL);
5958 return bus->ci->chip;
5961 void *dhd_bus_pub(struct dhd_bus *bus)
5966 void *dhd_bus_txq(struct dhd_bus *bus)
5971 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5973 return SDPCM_HDRLEN;
5976 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5984 if (!bus->dhd->dongle_reset) {
5985 /* Expect app to have torn down any
5986 connection before calling */
5987 /* Stop the bus, disable F2 */
5988 dhd_bus_stop(bus, false);
5990 /* Clean tx/rx buffer pointers,
5991 detach from the dongle */
5992 dhdsdio_release_dongle(bus);
5994 bus->dhd->dongle_reset = true;
5995 bus->dhd->up = false;
5997 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
5998 /* App can now remove power from device */
6002 /* App must have restored power to device before calling */
6004 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6006 if (bus->dhd->dongle_reset) {
6008 /* Reset SD client */
6009 bcmsdh_reset(bus->sdh);
6011 /* Attempt to re-attach & download */
6012 if (dhdsdio_probe_attach(bus, bus->sdh,
6013 (u32 *) SI_ENUM_BASE,
6015 /* Attempt to download binary to the dongle */
6016 if (dhdsdio_probe_init
6018 && dhdsdio_download_firmware(bus,
6021 /* Re-init bus, enable F2 transfer */
6022 dhd_bus_init((dhd_pub_t *) bus->dhd,
6025 #if defined(OOB_INTR_ONLY)
6026 dhd_enable_oob_intr(bus, true);
6027 #endif /* defined(OOB_INTR_ONLY) */
6029 bus->dhd->dongle_reset = false;
6030 bus->dhd->up = true;
6032 DHD_TRACE(("%s: WLAN ON DONE\n",
6039 bcmerror = -EISCONN;
6040 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6041 "is on\n", __func__));
6049 dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
6055 * Chipid is assume to be at offset 0 from regs arg
6056 * For different chiptypes or old sdio hosts w/o chipcommon,
6057 * other ways of recognition should be added here.
6059 ci->cccorebase = (u32)regs;
6060 regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
6061 ci->chip = regdata & CID_ID_MASK;
6062 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
6064 DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
6065 __func__, ci->chip, ci->chiprev));
6067 /* Address of cores for new chips should be added here */
6069 case BCM4329_CHIP_ID:
6070 ci->buscorebase = BCM4329_CORE_BUS_BASE;
6071 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
6072 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6073 ci->ramsize = BCM4329_RAMSIZE;
6076 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6077 __func__, ci->chip));
6081 regdata = bcmsdh_reg_read(sdh,
6082 CORE_SB(ci->cccorebase, sbidhigh), 4);
6083 ci->ccrev = SBCOREREV(regdata);
6085 regdata = bcmsdh_reg_read(sdh,
6086 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6087 ci->pmurev = regdata & PCAP_REV_MASK;
6089 regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
6090 ci->buscorerev = SBCOREREV(regdata);
6091 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6093 DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6094 __func__, ci->ccrev, ci->pmurev,
6095 ci->buscorerev, ci->buscoretype));
6097 /* get chipcommon capabilites */
6098 ci->cccaps = bcmsdh_reg_read(sdh,
6099 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6105 dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
6109 regdata = bcmsdh_reg_read(sdh,
6110 CORE_SB(corebase, sbtmstatelow), 4);
6111 if (regdata & SBTML_RESET)
6114 regdata = bcmsdh_reg_read(sdh,
6115 CORE_SB(corebase, sbtmstatelow), 4);
6116 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6118 * set target reject and spin until busy is clear
6119 * (preserve core-specific bits)
6121 regdata = bcmsdh_reg_read(sdh,
6122 CORE_SB(corebase, sbtmstatelow), 4);
6123 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6124 regdata | SBTML_REJ);
6126 regdata = bcmsdh_reg_read(sdh,
6127 CORE_SB(corebase, sbtmstatelow), 4);
6129 SPINWAIT((bcmsdh_reg_read(sdh,
6130 CORE_SB(corebase, sbtmstatehigh), 4) &
6131 SBTMH_BUSY), 100000);
6133 regdata = bcmsdh_reg_read(sdh,
6134 CORE_SB(corebase, sbtmstatehigh), 4);
6135 if (regdata & SBTMH_BUSY)
6136 DHD_ERROR(("%s: ARM core still busy\n", __func__));
6138 regdata = bcmsdh_reg_read(sdh,
6139 CORE_SB(corebase, sbidlow), 4);
6140 if (regdata & SBIDL_INIT) {
6141 regdata = bcmsdh_reg_read(sdh,
6142 CORE_SB(corebase, sbimstate), 4) |
6144 bcmsdh_reg_write(sdh,
6145 CORE_SB(corebase, sbimstate), 4,
6147 regdata = bcmsdh_reg_read(sdh,
6148 CORE_SB(corebase, sbimstate), 4);
6150 SPINWAIT((bcmsdh_reg_read(sdh,
6151 CORE_SB(corebase, sbimstate), 4) &
6155 /* set reset and reject while enabling the clocks */
6156 bcmsdh_reg_write(sdh,
6157 CORE_SB(corebase, sbtmstatelow), 4,
6158 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6159 SBTML_REJ | SBTML_RESET));
6160 regdata = bcmsdh_reg_read(sdh,
6161 CORE_SB(corebase, sbtmstatelow), 4);
6164 /* clear the initiator reject bit */
6165 regdata = bcmsdh_reg_read(sdh,
6166 CORE_SB(corebase, sbidlow), 4);
6167 if (regdata & SBIDL_INIT) {
6168 regdata = bcmsdh_reg_read(sdh,
6169 CORE_SB(corebase, sbimstate), 4) &
6171 bcmsdh_reg_write(sdh,
6172 CORE_SB(corebase, sbimstate), 4,
6177 /* leave reset and reject asserted */
6178 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6179 (SBTML_REJ | SBTML_RESET));
6184 dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
6186 struct chip_info *ci;
6190 DHD_TRACE(("%s: Enter\n", __func__));
6192 /* alloc chip_info_t */
6193 ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6195 DHD_ERROR(("%s: malloc failed!\n", __func__));
6199 memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6201 /* bus/core/clk setup for register access */
6202 /* Try forcing SDIO core to do ALPAvail request only */
6203 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6204 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6207 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6211 /* If register supported, wait for ALPAvail and then force ALP */
6212 /* This may take up to 15 milliseconds */
6213 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6214 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6215 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6217 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6218 SBSDIO_FUNC1_CHIPCLKCSR,
6220 !SBSDIO_ALPAV(clkval)),
6221 PMU_MAX_TRANSITION_DLY);
6222 if (!SBSDIO_ALPAV(clkval)) {
6223 DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6228 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6230 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
6231 SBSDIO_FUNC1_CHIPCLKCSR,
6235 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6236 __func__, clkset, clkval));
6241 /* Also, disable the extra SDIO pull-ups */
6242 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
6245 err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
6250 * Make sure any on-chip ARM is off (in case strapping is wrong),
6251 * or downloaded code was already running.
6253 dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
6255 bcmsdh_reg_write(bus->sdh,
6256 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6257 bcmsdh_reg_write(bus->sdh,
6258 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6260 /* Disable F2 to clear any intermediate frame state on the dongle */
6261 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
6262 SDIO_FUNC_ENABLE_1, NULL);
6264 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6265 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6268 /* Done with backplane-dependent accesses, can drop clock... */
6269 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
6281 dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
6286 * Must do the disable sequence first to work for
6287 * arbitrary current core state.
6289 dhdsdio_chip_disablecore(sdh, corebase);
6292 * Now do the initialization sequence.
6293 * set reset while enabling the clock and
6294 * forcing them on throughout the core
6296 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6297 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6301 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
6302 if (regdata & SBTMH_SERR)
6303 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
6305 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6306 if (regdata & (SBIM_IBE | SBIM_TO))
6307 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6308 regdata & ~(SBIM_IBE | SBIM_TO));
6310 /* clear reset and allow it to propagate throughout the core */
6311 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6312 (SICF_FGC << SBTML_SICF_SHIFT) |
6313 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6316 /* leave clock enabled */
6317 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6318 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6322 /* SDIO Pad drive strength to select value mappings */
6323 struct sdiod_drive_str {
6324 u8 strength; /* Pad Drive Strength in mA */
6325 u8 sel; /* Chip-specific select value */
6328 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6329 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6337 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6338 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6349 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6350 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6362 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
6365 dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6366 struct sdiod_drive_str *str_tab = NULL;
6371 if (!(bus->ci->cccaps & CC_CAP_PMU))
6374 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6375 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6376 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6377 str_mask = 0x30000000;
6380 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6381 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6382 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6383 str_mask = 0x00003800;
6386 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6387 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6388 str_mask = 0x00003800;
6392 DHD_ERROR(("No SDIO Drive strength init"
6393 "done for chip %s rev %d pmurev %d\n",
6394 bcm_chipname(bus->ci->chip, chn, 8),
6395 bus->ci->chiprev, bus->ci->pmurev));
6399 if (str_tab != NULL) {
6400 u32 drivestrength_sel = 0;
6404 for (i = 0; str_tab[i].strength != 0; i++) {
6405 if (drivestrength >= str_tab[i].strength) {
6406 drivestrength_sel = str_tab[i].sel;
6411 bcmsdh_reg_write(bus->sdh,
6412 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6414 cc_data_temp = bcmsdh_reg_read(bus->sdh,
6415 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6416 cc_data_temp &= ~str_mask;
6417 drivestrength_sel <<= str_shift;
6418 cc_data_temp |= drivestrength_sel;
6419 bcmsdh_reg_write(bus->sdh,
6420 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6423 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6424 drivestrength, cc_data_temp));
6429 dhdsdio_chip_detach(struct dhd_bus *bus)
6431 DHD_TRACE(("%s: Enter\n", __func__));