2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/printk.h>
20 #include <linux/pci_ids.h>
21 #include <linux/netdevice.h>
22 #include <linux/sched.h>
23 #include <linux/mmc/sdio.h>
24 #include <asm/unaligned.h>
26 #include <brcmu_wifi.h>
27 #include <brcmu_utils.h>
28 #include <brcm_hw_ids.h>
30 #include "sdio_host.h"
32 /* register access macros */
36 brcmf_sdcard_reg_read(NULL, (unsigned long)(r), sizeof(*(r)))
40 __typeof(*(r)) __osl_v; \
41 __asm__ __volatile__("sync"); \
42 __osl_v = brcmf_sdcard_reg_read(NULL, (unsigned long)(r),\
44 __asm__ __volatile__("sync"); \
49 #define W_REG(r, v) do { \
50 brcmf_sdcard_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), \
53 #else /* __BIG_ENDIAN */
55 brcmf_sdcard_reg_read(NULL, (unsigned long)(r), sizeof(*(r)))
56 #define W_REG(r, v) do { \
57 brcmf_sdcard_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), \
60 #endif /* __BIG_ENDIAN */
62 #define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
63 #define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
65 #define SET_REG(r, mask, val) \
66 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
70 /* ARM trap handling */
72 /* Trap types defined by ARM (see arminc.h) */
74 /* Trap locations in lo memory */
76 #define FIRST_TRAP TR_RST
77 #define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
79 #if defined(__ARM_ARCH_4T__)
80 #define MAX_TRAP_TYPE (TR_FIQ + 1)
81 #elif defined(__ARM_ARCH_7M__)
82 #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
83 #endif /* __ARM_ARCH_7M__ */
85 /* The trap structure is defined here as offsets for assembly */
91 #define TR_REG(n) (TR_REGS + (n) * 4)
92 #define TR_SP TR_REG(13)
93 #define TR_LR TR_REG(14)
94 #define TR_PC TR_REG(15)
96 #define TRAP_T_SIZE 80
98 typedef struct _trap_struct {
121 #define CBUF_LEN (128)
123 #define LOG_BUF_LEN 1024
126 u32 buf; /* Can't be pointer on (64-bit) hosts */
129 char *_buf_compat; /* Redundant pointer for backward compat. */
134 * When there is no UART (e.g. Quickturn),
135 * the host should write a complete
136 * input line directly into cbuf and then write
137 * the length into vcons_in.
138 * This may also be used when there is a real UART
139 * (at risk of conflicting with
140 * the real UART). vcons_out is currently unused.
142 volatile uint vcons_in;
143 volatile uint vcons_out;
145 /* Output (logging) buffer
146 * Console output is written to a ring buffer log_buf at index log_idx.
147 * The host may read the output when it sees log_idx advance.
148 * Output will be lost if the output wraps around faster than the host
153 /* Console input line buffer
154 * Characters are read one at a time into cbuf
155 * until <CR> is received, then
156 * the buffer is processed as a command line.
157 * Also used for virtual UART.
163 #endif /* DHD_DEBUG */
164 #include <chipcommon.h>
168 #include "dngl_stats.h"
171 #include "dhd_proto.h"
176 #ifndef DHDSDIO_MEM_DUMP_FNAME
177 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
180 #define TXQLEN 2048 /* bulk tx queue length */
181 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
182 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
185 #define TXRETRIES 2 /* # of retries for tx frames */
187 #if defined(CONFIG_MACH_SANDGATE2G)
188 #define DHD_RXBOUND 250 /* Default for max rx frames in
191 #define DHD_RXBOUND 50 /* Default for max rx frames in
193 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
195 #define DHD_TXBOUND 20 /* Default for max tx frames in
198 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
200 #define MEMBLOCK 2048 /* Block size used for downloading
202 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
203 biggest possible glom */
205 /* Packet alignment for most efficient SDIO (can change based on platform) */
207 #define DHD_SDALIGN 32
209 #if !ISPOWEROF2(DHD_SDALIGN)
210 #error DHD_SDALIGN is not a power of 2!
213 #ifndef DHD_FIRSTREAD
214 #define DHD_FIRSTREAD 32
216 #if !ISPOWEROF2(DHD_FIRSTREAD)
217 #error DHD_FIRSTREAD is not a power of 2!
220 /* Total length of frame header for dongle protocol */
221 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
223 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
225 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
229 * Software allocation of To SB Mailbox resources
232 /* tosbmailbox bits corresponding to intstatus bits */
233 #define SMB_NAK (1 << 0) /* Frame NAK */
234 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
235 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
236 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
238 /* tosbmailboxdata */
239 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
242 * Software allocation of To Host Mailbox resources
246 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
247 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
248 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
249 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
251 /* tohostmailboxdata */
252 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
253 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
254 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
255 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
257 #define HMB_DATA_FCDATA_MASK 0xff000000
258 #define HMB_DATA_FCDATA_SHIFT 24
260 #define HMB_DATA_VERSION_MASK 0x00ff0000
261 #define HMB_DATA_VERSION_SHIFT 16
264 * Software-defined protocol header
267 /* Current protocol version */
268 #define SDPCM_PROT_VERSION 4
270 /* SW frame header */
271 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
273 #define SDPCM_CHANNEL_MASK 0x00000f00
274 #define SDPCM_CHANNEL_SHIFT 8
275 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
277 #define SDPCM_NEXTLEN_OFFSET 2
279 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
280 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
281 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
282 #define SDPCM_DOFFSET_MASK 0xff000000
283 #define SDPCM_DOFFSET_SHIFT 24
284 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
285 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
286 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
287 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
289 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
291 /* logical channel numbers */
292 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
293 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
294 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
295 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
296 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
298 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
300 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
302 /* For TEST_CHANNEL packets, define another 4-byte header */
303 #define SDPCM_TEST_HDRLEN 4 /*
304 * Generally: Cmd(1), Ext(1), Len(2);
305 * Semantics of Ext byte depend on
306 * command. Len is current or requested
307 * frame length, not including test
308 * header; sent little-endian.
310 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */
311 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */
312 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */
313 #define SDPCM_TEST_BURST 0x04 /*
314 * Receiver to send a burst.
315 * Ext is a frame count
317 #define SDPCM_TEST_SEND 0x05 /*
318 * Receiver sets send mode.
319 * Ext is boolean on/off
322 /* Handy macro for filling in datagen packets with a pattern */
323 #define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
326 * Shared structure between dongle and the host.
327 * The structure contains pointers to trap or assert information.
329 #define SDPCM_SHARED_VERSION 0x0002
330 #define SDPCM_SHARED_VERSION_MASK 0x00FF
331 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
332 #define SDPCM_SHARED_ASSERT 0x0200
333 #define SDPCM_SHARED_TRAP 0x0400
336 /* Space for header read, limit for data packets */
338 #define MAX_HDR_READ 32
340 #if !ISPOWEROF2(MAX_HDR_READ)
341 #error MAX_HDR_READ is not a power of 2!
344 #define MAX_RX_DATASZ 2048
346 /* Maximum milliseconds to wait for F2 to come up */
347 #define DHD_WAIT_F2RDY 3000
349 /* Bump up limit on waiting for HT to account for first startup;
350 * if the image is doing a CRC calculation before programming the PMU
351 * for HT availability, it could take a couple hundred ms more, so
352 * max out at a 1 second (1000000us).
354 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
355 #undef PMU_MAX_TRANSITION_DLY
356 #define PMU_MAX_TRANSITION_DLY 1000000
359 /* Value for ChipClockCSR during initial setup */
360 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
361 SBSDIO_ALP_AVAIL_REQ)
362 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
364 /* Flags for SDH calls */
365 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
368 #define SBIM_IBE 0x20000 /* inbanderror */
369 #define SBIM_TO 0x40000 /* timeout */
370 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
371 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
374 #define SBTML_RESET 0x0001 /* reset */
375 #define SBTML_REJ_MASK 0x0006 /* reject field */
376 #define SBTML_REJ 0x0002 /* reject */
377 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
379 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
382 #define SBTMH_SERR 0x0001 /* serror */
383 #define SBTMH_INT 0x0002 /* interrupt */
384 #define SBTMH_BUSY 0x0004 /* busy */
385 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
387 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
390 #define SBIDL_INIT 0x80 /* initiator */
393 #define SBIDH_RC_MASK 0x000f /* revision code */
394 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
395 #define SBIDH_RCE_SHIFT 8
396 #define SBCOREREV(sbidh) \
397 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
398 #define SBIDH_CC_MASK 0x8ff0 /* core code */
399 #define SBIDH_CC_SHIFT 4
400 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
401 #define SBIDH_VC_SHIFT 16
404 * Conversion of 802.1D priority to precedence level
406 #define PRIO2PREC(prio) \
407 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
410 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
411 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
414 /* Core reg address translation */
415 #define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
416 #define CORE_BUS_REG(base, field) \
417 (base + offsetof(struct sdpcmd_regs, field))
418 #define CORE_SB(base, field) \
419 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
422 /* Device console log buffer state */
423 typedef struct dhd_console {
424 uint count; /* Poll interval msec counter */
425 uint log_addr; /* Log struct address (fixed) */
426 rte_log_t log; /* Log struct (host copy) */
427 uint bufsize; /* Size of log buffer */
428 u8 *buf; /* Log buffer (host copy) */
429 uint last; /* Last buffer read index */
431 #endif /* DHD_DEBUG */
433 struct sdpcm_shared {
437 u32 assert_file_addr;
439 u32 console_addr; /* Address of rte_cons_t */
445 /* misc chip info needed by some of the routines */
461 /* Private data for SDIO bus interaction */
462 typedef struct dhd_bus {
465 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
466 struct chip_info *ci; /* Chip info struct */
467 char *vars; /* Variables (from CIS and/or other) */
468 uint varsz; /* Size of variables buffer */
469 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
471 struct sdpcmd_regs *regs; /* SDIO core */
472 uint sdpcmrev; /* SDIO core revision */
473 uint armrev; /* CPU core revision */
474 uint ramrev; /* SOCRAM core revision */
475 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
476 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
478 u32 bus; /* gSPI or SDIO bus */
479 u32 hostintmask; /* Copy of Host Interrupt Mask */
480 u32 intstatus; /* Intstatus bits (events) pending */
481 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
482 bool fcstate; /* State of dongle flow-control */
484 u16 cl_devid; /* cached devid for brcmf_sdio_probe_attach() */
485 char *fw_path; /* module_param: path to firmware image */
486 char *nv_path; /* module_param: path to nvram vars file */
487 const char *nvram_params; /* user specified nvram params. */
489 uint blocksize; /* Block size of SDIO transfers */
490 uint roundup; /* Max roundup limit */
492 struct pktq txq; /* Queue length used for flow-control */
493 u8 flowcontrol; /* per prio flow control bitmask */
494 u8 tx_seq; /* Transmit sequence number (next) */
495 u8 tx_max; /* Maximum transmit sequence allowed */
497 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
498 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
499 u16 nextlen; /* Next Read Len from last header */
500 u8 rx_seq; /* Receive sequence number (expected) */
501 bool rxskip; /* Skip receive (awaiting NAK ACK) */
503 struct sk_buff *glomd; /* Packet containing glomming descriptor */
504 struct sk_buff *glom; /* Packet chain for glommed superframe */
505 uint glomerr; /* Glom packet read errors */
507 u8 *rxbuf; /* Buffer for receiving control packets */
508 uint rxblen; /* Allocated length of rxbuf */
509 u8 *rxctl; /* Aligned pointer into rxbuf */
510 u8 *databuf; /* Buffer for receiving big glom packet */
511 u8 *dataptr; /* Aligned pointer into databuf */
512 uint rxlen; /* Length of valid data in buffer */
514 u8 sdpcm_ver; /* Bus protocol reported by dongle */
516 bool intr; /* Use interrupts */
517 bool poll; /* Use polling */
518 bool ipend; /* Device interrupt is pending */
519 bool intdis; /* Interrupts disabled by isr */
520 uint intrcount; /* Count of device interrupt callbacks */
521 uint lastintrs; /* Count as of last watchdog timer */
522 uint spurious; /* Count of spurious interrupts */
523 uint pollrate; /* Ticks between device polls */
524 uint polltick; /* Tick counter */
525 uint pollcnt; /* Count of active polls */
528 dhd_console_t console; /* Console output polling support */
529 uint console_addr; /* Console address from shared struct */
530 #endif /* DHD_DEBUG */
532 uint regfails; /* Count of R_REG/W_REG failures */
534 uint clkstate; /* State of sd and backplane clock(s) */
535 bool activity; /* Activity flag for clock down */
536 s32 idletime; /* Control for activity timeout */
537 s32 idlecount; /* Activity timeout counter */
538 s32 idleclock; /* How to set bus driver when idle */
539 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
540 bool use_rxchain; /* If dhd should use PKT chains */
541 bool sleeping; /* Is SDIO bus sleeping? */
542 bool rxflow_mode; /* Rx flow control mode */
543 bool rxflow; /* Is rx flow control on */
544 uint prev_rxlim_hit; /* Is prev rx limit exceeded
545 (per dpc schedule) */
546 bool alp_only; /* Don't use HT clock (ALP only) */
547 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
551 /* external loopback */
555 /* pktgen configuration */
556 uint pktgen_freq; /* Ticks between bursts */
557 uint pktgen_count; /* Packets to send each burst */
558 uint pktgen_print; /* Bursts between count displays */
559 uint pktgen_total; /* Stop after this many */
560 uint pktgen_minlen; /* Minimum packet data len */
561 uint pktgen_maxlen; /* Maximum packet data len */
562 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
563 uint pktgen_stop; /* Number of tx failures causing stop */
565 /* active pktgen fields */
566 uint pktgen_tick; /* Tick counter for bursts */
567 uint pktgen_ptick; /* Burst counter for printing */
568 uint pktgen_sent; /* Number of test packets generated */
569 uint pktgen_rcvd; /* Number of test packets received */
570 uint pktgen_fail; /* Number of failed send attempts */
571 u16 pktgen_len; /* Length of next packet to send */
574 /* Some additional counters */
575 uint tx_sderrs; /* Count of tx attempts with sd errors */
576 uint fcqueued; /* Tx packets that got queued */
577 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
578 uint rx_toolong; /* Receive frames too long to receive */
579 uint rxc_errors; /* SDIO errors when reading control frames */
580 uint rx_hdrfail; /* SDIO errors on header reads */
581 uint rx_badhdr; /* Bad received headers (roosync?) */
582 uint rx_badseq; /* Mismatched rx sequence number */
583 uint fc_rcvd; /* Number of flow-control events received */
584 uint fc_xoff; /* Number which turned on flow-control */
585 uint fc_xon; /* Number which turned off flow-control */
586 uint rxglomfail; /* Failed deglom attempts */
587 uint rxglomframes; /* Number of glom frames (superframes) */
588 uint rxglompkts; /* Number of packets from glom frames */
589 uint f2rxhdrs; /* Number of header reads */
590 uint f2rxdata; /* Number of frame data reads */
591 uint f2txdata; /* Number of f2 frame writes */
592 uint f1regdata; /* Number of f1 register accesses */
596 bool ctrl_frame_stat;
601 typedef volatile struct _sbconfig {
603 u32 sbipsflag; /* initiator port ocp slave flag */
605 u32 sbtpsflag; /* target port ocp slave flag */
607 u32 sbtmerrloga; /* (sonics >= 2.3) */
609 u32 sbtmerrlog; /* (sonics >= 2.3) */
611 u32 sbadmatch3; /* address match3 */
613 u32 sbadmatch2; /* address match2 */
615 u32 sbadmatch1; /* address match1 */
617 u32 sbimstate; /* initiator agent state */
618 u32 sbintvec; /* interrupt mask */
619 u32 sbtmstatelow; /* target state */
620 u32 sbtmstatehigh; /* target state */
621 u32 sbbwa0; /* bandwidth allocation table0 */
623 u32 sbimconfiglow; /* initiator configuration */
624 u32 sbimconfighigh; /* initiator configuration */
625 u32 sbadmatch0; /* address match0 */
627 u32 sbtmconfiglow; /* target configuration */
628 u32 sbtmconfighigh; /* target configuration */
629 u32 sbbconfig; /* broadcast configuration */
631 u32 sbbstate; /* broadcast state */
633 u32 sbactcnfg; /* activate configuration */
635 u32 sbflagst; /* current sbflags */
637 u32 sbidlow; /* identification */
638 u32 sbidhigh; /* identification */
644 #define CLK_PENDING 2 /* Not used yet */
647 #define DHD_NOPMU(dhd) (false)
650 static int qcount[NUMPRIO];
651 static int tx_packets[NUMPRIO];
652 #endif /* DHD_DEBUG */
654 /* Deferred transmit */
655 const uint dhd_deferred_tx = 1;
657 extern uint dhd_watchdog_ms;
658 extern void dhd_os_wd_timer(void *bus, uint wdtick);
665 /* override the RAM size if possible */
666 #define DONGLE_MIN_MEMSIZE (128 * 1024)
667 int dhd_dongle_memsize;
669 static bool dhd_alignctl;
673 static bool retrydata;
674 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
676 static const uint watermark = 8;
677 static const uint firstread = DHD_FIRSTREAD;
679 #define HDATLEN (firstread - (SDPCM_HDRLEN))
681 /* Retry count for register access failures */
682 static const uint retry_limit = 2;
684 /* Force even SD lengths (some host controllers mess up on odd bytes) */
685 static bool forcealign;
689 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
690 extern void brcmf_sdcard_enable_hw_oob_intr(void *sdh, bool enable);
693 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
694 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
695 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
696 #define PKTALIGN(_p, _len, _align) \
699 datalign = (unsigned long)((_p)->data); \
700 datalign = roundup(datalign, (_align)) - datalign; \
701 ASSERT(datalign < (_align)); \
702 ASSERT((_p)->len >= ((_len) + datalign)); \
704 skb_pull((_p), datalign); \
705 __skb_trim((_p), (_len)); \
708 /* Limit on rounding up frames */
709 static const uint max_roundup = 512;
711 /* Try doing readahead */
712 static bool dhd_readahead;
714 /* To check if there's window offered */
715 #define DATAOK(bus) \
716 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
717 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
719 /* Macros to get register read/write status */
720 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
721 #define R_SDREG(regvar, regaddr, retryvar) \
725 regvar = R_REG(regaddr); \
726 } while (brcmf_sdcard_regfail(bus->sdh) && \
727 (++retryvar <= retry_limit)); \
729 bus->regfails += (retryvar-1); \
730 if (retryvar > retry_limit) { \
731 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
732 __func__, __LINE__)); \
738 #define W_SDREG(regval, regaddr, retryvar) \
742 W_REG(regaddr, regval); \
743 } while (brcmf_sdcard_regfail(bus->sdh) && \
744 (++retryvar <= retry_limit)); \
746 bus->regfails += (retryvar-1); \
747 if (retryvar > retry_limit) \
748 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
749 __func__, __LINE__)); \
753 #define DHD_BUS SDIO_BUS
755 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
757 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
760 static void brcmf_sdbrcm_checkdied(dhd_bus_t *bus, void *pkt, uint seq);
761 static void brcmf_sdbrcm_sdtest_set(dhd_bus_t *bus, bool start);
765 static int brcmf_sdbrcm_checkdied(dhd_bus_t *bus, u8 *data, uint size);
766 static int brcmf_sdbrcm_mem_dump(dhd_bus_t *bus);
767 #endif /* DHD_DEBUG */
768 static int brcmf_sdbrcm_download_state(dhd_bus_t *bus, bool enter);
770 static void brcmf_sdbrcm_release(dhd_bus_t *bus);
771 static void brcmf_sdbrcm_release_malloc(dhd_bus_t *bus);
772 static void brcmf_sdbrcm_disconnect(void *ptr);
773 static bool brcmf_sdbrcm_chipmatch(u16 chipid);
774 static bool brcmf_sdbrcm_probe_attach(dhd_bus_t *bus, void *sdh,
775 void *regsva, u16 devid);
776 static bool brcmf_sdbrcm_probe_malloc(dhd_bus_t *bus, void *sdh);
777 static bool brcmf_sdbrcm_probe_init(dhd_bus_t *bus, void *sdh);
778 static void brcmf_sdbrcm_release_dongle(dhd_bus_t *bus);
780 static uint brcmf_process_nvram_vars(char *varbuf, uint len);
782 static void brcmf_sdbrcm_setmemsize(struct dhd_bus *bus, int mem_size);
783 static int brcmf_sdbrcm_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
784 uint flags, u8 *buf, uint nbytes,
785 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
788 static bool brcmf_sdbrcm_download_firmware(struct dhd_bus *bus, void *sdh);
789 static int _brcmf_sdbrcm_download_firmware(struct dhd_bus *bus);
792 brcmf_sdbrcm_download_code_file(struct dhd_bus *bus, char *image_path);
793 static int brcmf_sdbrcm_download_nvram(struct dhd_bus *bus);
794 static void brcmf_sdbrcm_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
795 static int brcmf_sdbrcm_chip_attach(struct dhd_bus *bus, void *regs);
796 static void brcmf_sdbrcm_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
797 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct dhd_bus *bus,
799 static void brcmf_sdbrcm_chip_detach(struct dhd_bus *bus);
801 /* Packet free applicable unconditionally for sdio and sdspi.
802 * Conditional if bufpool was present for gspi bus.
804 static void brcmf_sdbrcm_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
806 if ((bus->bus != SPI_BUS) || bus->usebufpool)
807 brcmu_pkt_buf_free_skb(pkt);
810 static void brcmf_sdbrcm_setmemsize(struct dhd_bus *bus, int mem_size)
812 s32 min_size = DONGLE_MIN_MEMSIZE;
813 /* Restrict the memsize to user specified limit */
814 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
815 dhd_dongle_memsize, min_size));
816 if ((dhd_dongle_memsize > min_size) &&
817 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
818 bus->ramsize = dhd_dongle_memsize;
821 static int brcmf_sdbrcm_set_siaddr_window(dhd_bus_t *bus, u32 address)
824 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
825 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
827 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
828 SBSDIO_FUNC1_SBADDRMID,
829 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
831 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
832 SBSDIO_FUNC1_SBADDRHIGH,
833 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
838 /* Turn backplane clock on or off */
839 static int brcmf_sdbrcm_htclk(dhd_bus_t *bus, bool on, bool pendok)
842 u8 clkctl, clkreq, devctl;
845 DHD_TRACE(("%s: Enter\n", __func__));
847 #if defined(OOB_INTR_ONLY)
854 /* Request HT Avail */
856 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
858 if ((bus->ci->chip == BCM4329_CHIP_ID)
859 && (bus->ci->chiprev == 0))
860 clkreq |= SBSDIO_FORCE_ALP;
862 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
863 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
865 DHD_ERROR(("%s: HT Avail request error: %d\n",
870 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
871 && (bus->ci->buscorerev == 9))) {
873 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
876 /* Check current status */
877 clkctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
878 SBSDIO_FUNC1_CHIPCLKCSR, &err);
880 DHD_ERROR(("%s: HT Avail read error: %d\n",
885 /* Go to pending and await interrupt if appropriate */
886 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
887 /* Allow only clock-available interrupt */
888 devctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
889 SBSDIO_DEVICE_CTL, &err);
891 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
896 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
897 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
898 SBSDIO_DEVICE_CTL, devctl, &err);
899 DHD_INFO(("CLKCTL: set PENDING\n"));
900 bus->clkstate = CLK_PENDING;
903 } else if (bus->clkstate == CLK_PENDING) {
904 /* Cancel CA-only interrupt filter */
906 brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
907 SBSDIO_DEVICE_CTL, &err);
908 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
909 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
910 SBSDIO_DEVICE_CTL, devctl, &err);
913 /* Otherwise, wait here (polling) for HT Avail */
914 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
915 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
917 brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
918 SBSDIO_FUNC1_CHIPCLKCSR,
920 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
921 PMU_MAX_TRANSITION_DLY);
924 DHD_ERROR(("%s: HT Avail request error: %d\n",
928 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
929 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
930 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
934 /* Mark clock available */
935 bus->clkstate = CLK_AVAIL;
936 DHD_INFO(("CLKCTL: turned ON\n"));
938 #if defined(DHD_DEBUG)
939 if (bus->alp_only == true) {
940 #if !defined(BCMLXSDMMC)
941 if (!SBSDIO_ALPONLY(clkctl)) {
942 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
945 #endif /* !defined(BCMLXSDMMC) */
947 if (SBSDIO_ALPONLY(clkctl)) {
948 DHD_ERROR(("%s: HT Clock should be on.\n",
952 #endif /* defined (DHD_DEBUG) */
954 bus->activity = true;
958 if (bus->clkstate == CLK_PENDING) {
959 /* Cancel CA-only interrupt filter */
960 devctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
961 SBSDIO_DEVICE_CTL, &err);
962 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
963 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
964 SBSDIO_DEVICE_CTL, devctl, &err);
967 bus->clkstate = CLK_SDONLY;
968 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
969 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
970 DHD_INFO(("CLKCTL: turned OFF\n"));
972 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
980 /* Change idle/active SD state */
981 static int brcmf_sdbrcm_sdclk(dhd_bus_t *bus, bool on)
983 DHD_TRACE(("%s: Enter\n", __func__));
986 bus->clkstate = CLK_SDONLY;
988 bus->clkstate = CLK_NONE;
993 /* Transition SD and backplane clock readiness */
994 static int brcmf_sdbrcm_clkctl(dhd_bus_t *bus, uint target, bool pendok)
997 uint oldstate = bus->clkstate;
998 #endif /* DHD_DEBUG */
1000 DHD_TRACE(("%s: Enter\n", __func__));
1002 /* Early exit if we're already there */
1003 if (bus->clkstate == target) {
1004 if (target == CLK_AVAIL) {
1005 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1006 bus->activity = true;
1013 /* Make sure SD clock is available */
1014 if (bus->clkstate == CLK_NONE)
1015 brcmf_sdbrcm_sdclk(bus, true);
1016 /* Now request HT Avail on the backplane */
1017 brcmf_sdbrcm_htclk(bus, true, pendok);
1018 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1019 bus->activity = true;
1023 /* Remove HT request, or bring up SD clock */
1024 if (bus->clkstate == CLK_NONE)
1025 brcmf_sdbrcm_sdclk(bus, true);
1026 else if (bus->clkstate == CLK_AVAIL)
1027 brcmf_sdbrcm_htclk(bus, false, false);
1029 DHD_ERROR(("brcmf_sdbrcm_clkctl: request for %d -> %d"
1030 "\n", bus->clkstate, target));
1031 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1035 /* Make sure to remove HT request */
1036 if (bus->clkstate == CLK_AVAIL)
1037 brcmf_sdbrcm_htclk(bus, false, false);
1038 /* Now remove the SD clock */
1039 brcmf_sdbrcm_sdclk(bus, false);
1040 dhd_os_wd_timer(bus->dhd, 0);
1044 DHD_INFO(("brcmf_sdbrcm_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1045 #endif /* DHD_DEBUG */
1050 int brcmf_sdbrcm_bussleep(dhd_bus_t *bus, bool sleep)
1052 bcmsdh_info_t *sdh = bus->sdh;
1053 struct sdpcmd_regs *regs = bus->regs;
1056 DHD_INFO(("brcmf_sdbrcm_bussleep: request %s (currently %s)\n",
1057 (sleep ? "SLEEP" : "WAKE"),
1058 (bus->sleeping ? "SLEEP" : "WAKE")));
1060 /* Done if we're already in the requested state */
1061 if (sleep == bus->sleeping)
1064 /* Going to sleep: set the alarm and turn off the lights... */
1066 /* Don't sleep if something is pending */
1067 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1070 /* Disable SDIO interrupts (no longer interested) */
1071 brcmf_sdcard_intr_disable(bus->sdh);
1073 /* Make sure the controller has the bus up */
1074 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1076 /* Tell device to start using OOB wakeup */
1077 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1078 if (retries > retry_limit)
1079 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1081 /* Turn off our contribution to the HT clock request */
1082 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1084 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1085 SBSDIO_FUNC1_CHIPCLKCSR,
1086 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1088 /* Isolate the bus */
1089 if (bus->ci->chip != BCM4329_CHIP_ID
1090 && bus->ci->chip != BCM4319_CHIP_ID) {
1091 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1093 SBSDIO_DEVCTL_PADS_ISO, NULL);
1097 bus->sleeping = true;
1100 /* Waking up: bus power up is ok, set local state */
1102 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1103 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1105 /* Force pad isolation off if possible
1106 (in case power never toggled) */
1107 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1108 && (bus->ci->buscorerev >= 10))
1109 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1110 SBSDIO_DEVICE_CTL, 0, NULL);
1112 /* Make sure the controller has the bus up */
1113 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1115 /* Send misc interrupt to indicate OOB not needed */
1116 W_SDREG(0, ®s->tosbmailboxdata, retries);
1117 if (retries <= retry_limit)
1118 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1120 if (retries > retry_limit)
1121 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1123 /* Make sure we have SD bus access */
1124 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1127 bus->sleeping = false;
1129 /* Enable interrupts again */
1130 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
1131 bus->intdis = false;
1132 brcmf_sdcard_intr_enable(bus->sdh);
1139 #if defined(OOB_INTR_ONLY)
1140 void brcmf_sdbrcm_enable_oob_intr(struct dhd_bus *bus, bool enable)
1143 brcmf_sdcard_enable_hw_oob_intr(bus->sdh, enable);
1145 sdpcmd_regs_t *regs = bus->regs;
1148 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1149 if (enable == true) {
1151 /* Tell device to start using OOB wakeup */
1152 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1153 if (retries > retry_limit)
1154 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1157 /* Send misc interrupt to indicate OOB not needed */
1158 W_SDREG(0, ®s->tosbmailboxdata, retries);
1159 if (retries <= retry_limit)
1160 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1163 /* Turn off our contribution to the HT clock request */
1164 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1165 #endif /* !defined(HW_OOB) */
1167 #endif /* defined(OOB_INTR_ONLY) */
1169 #define BUS_WAKE(bus) \
1171 if ((bus)->sleeping) \
1172 brcmf_sdbrcm_bussleep((bus), false); \
1175 /* Writes a HW/SW header into the packet and sends it. */
1176 /* Assumes: (a) header space already there, (b) caller holds lock */
1177 static int brcmf_sdbrcm_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1186 struct sk_buff *new;
1189 DHD_TRACE(("%s: Enter\n", __func__));
1193 if (bus->dhd->dongle_reset) {
1198 frame = (u8 *) (pkt->data);
1200 /* Add alignment padding, allocate new packet if needed */
1201 pad = ((unsigned long)frame % DHD_SDALIGN);
1203 if (skb_headroom(pkt) < pad) {
1204 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1205 __func__, skb_headroom(pkt), pad));
1206 bus->dhd->tx_realloc++;
1207 new = brcmu_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1209 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1211 __func__, pkt->len + DHD_SDALIGN));
1216 PKTALIGN(new, pkt->len, DHD_SDALIGN);
1217 memcpy(new->data, pkt->data, pkt->len);
1219 brcmu_pkt_buf_free_skb(pkt);
1220 /* free the pkt if canned one is not used */
1223 frame = (u8 *) (pkt->data);
1224 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1228 frame = (u8 *) (pkt->data);
1230 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1231 memset(frame, 0, pad + SDPCM_HDRLEN);
1234 ASSERT(pad < DHD_SDALIGN);
1236 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1237 len = (u16) (pkt->len);
1238 *(u16 *) frame = cpu_to_le16(len);
1239 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1241 /* Software tag: channel, sequence number, data offset */
1243 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1245 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1247 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1248 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1251 tx_packets[pkt->priority]++;
1252 if (DHD_BYTES_ON() &&
1253 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1254 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1255 printk(KERN_DEBUG "Tx Frame:\n");
1256 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1257 } else if (DHD_HDRS_ON()) {
1258 printk(KERN_DEBUG "TxHdr:\n");
1259 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1260 frame, min_t(u16, len, 16));
1264 /* Raise len to next SDIO block to eliminate tail command */
1265 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1266 u16 pad = bus->blocksize - (len % bus->blocksize);
1267 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1269 if (pad <= skb_tailroom(pkt))
1270 #endif /* NOTUSED */
1272 } else if (len % DHD_SDALIGN) {
1273 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1276 /* Some controllers have trouble with odd bytes -- round to even */
1277 if (forcealign && (len & (ALIGNMENT - 1))) {
1279 if (skb_tailroom(pkt))
1281 len = roundup(len, ALIGNMENT);
1284 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1290 ret = brcmf_sdbrcm_send_buf(bus, brcmf_sdcard_cur_sbwad(sdh),
1291 SDIO_FUNC_2, F2SYNC, frame, len, pkt, NULL, NULL);
1293 ASSERT(ret != -BCME_PENDING);
1296 /* On failure, abort the command
1297 and terminate the frame */
1298 DHD_INFO(("%s: sdio error %d, abort command and "
1299 "terminate frame.\n", __func__, ret));
1302 brcmf_sdcard_abort(sdh, SDIO_FUNC_2);
1303 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1304 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1308 for (i = 0; i < 3; i++) {
1310 hi = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
1311 SBSDIO_FUNC1_WFRAMEBCHI,
1313 lo = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
1314 SBSDIO_FUNC1_WFRAMEBCLO,
1316 bus->f1regdata += 2;
1317 if ((hi == 0) && (lo == 0))
1323 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1325 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1328 /* restore pkt buffer pointer before calling tx complete routine */
1329 skb_pull(pkt, SDPCM_HDRLEN + pad);
1330 dhd_os_sdunlock(bus->dhd);
1331 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1332 dhd_os_sdlock(bus->dhd);
1335 brcmu_pkt_buf_free_skb(pkt);
1340 int brcmf_sdbrcm_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1345 DHD_TRACE(("%s: Enter\n", __func__));
1350 /* Push the test header if doing loopback */
1351 if (bus->ext_loop) {
1353 skb_push(pkt, SDPCM_TEST_HDRLEN);
1355 *data++ = SDPCM_TEST_ECHOREQ;
1356 *data++ = (u8) bus->loopid++;
1357 *data++ = (datalen >> 0);
1358 *data++ = (datalen >> 8);
1359 datalen += SDPCM_TEST_HDRLEN;
1363 /* Add space for the header */
1364 skb_push(pkt, SDPCM_HDRLEN);
1365 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1367 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1369 /* Check for existing queue, current flow-control,
1370 pending event, or pending clock */
1371 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1372 || bus->dpc_sched || (!DATAOK(bus))
1373 || (bus->flowcontrol & NBITVAL(prec))
1374 || (bus->clkstate != CLK_AVAIL)) {
1375 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1376 pktq_len(&bus->txq)));
1379 /* Priority based enq */
1380 spin_lock_bh(&bus->txqlock);
1381 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1382 skb_pull(pkt, SDPCM_HDRLEN);
1383 dhd_txcomplete(bus->dhd, pkt, false);
1384 brcmu_pkt_buf_free_skb(pkt);
1385 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1390 spin_unlock_bh(&bus->txqlock);
1392 if (pktq_len(&bus->txq) >= TXHI)
1393 dhd_txflowcontrol(bus->dhd, 0, ON);
1396 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1397 qcount[prec] = pktq_plen(&bus->txq, prec);
1399 /* Schedule DPC if needed to send queued packet(s) */
1400 if (dhd_deferred_tx && !bus->dpc_sched) {
1401 bus->dpc_sched = true;
1402 dhd_sched_dpc(bus->dhd);
1405 /* Lock: we're about to use shared data/code (and SDIO) */
1406 dhd_os_sdlock(bus->dhd);
1408 /* Otherwise, send it now */
1410 /* Make sure back plane ht clk is on, no pending allowed */
1411 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
1414 DHD_TRACE(("%s: calling txpkt\n", __func__));
1415 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1417 ret = brcmf_sdbrcm_txpkt(bus, pkt,
1418 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1419 SDPCM_DATA_CHANNEL), true);
1422 bus->dhd->tx_errors++;
1424 bus->dhd->dstats.tx_bytes += datalen;
1426 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1427 bus->activity = false;
1428 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1431 dhd_os_sdunlock(bus->dhd);
1437 static uint brcmf_sdbrcm_sendfromq(dhd_bus_t *bus, uint maxframes)
1439 struct sk_buff *pkt;
1442 int ret = 0, prec_out;
1447 dhd_pub_t *dhd = bus->dhd;
1448 struct sdpcmd_regs *regs = bus->regs;
1450 DHD_TRACE(("%s: Enter\n", __func__));
1452 tx_prec_map = ~bus->flowcontrol;
1454 /* Send frames until the limit or some other event */
1455 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1456 spin_lock_bh(&bus->txqlock);
1457 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1459 spin_unlock_bh(&bus->txqlock);
1462 spin_unlock_bh(&bus->txqlock);
1463 datalen = pkt->len - SDPCM_HDRLEN;
1466 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1468 ret = brcmf_sdbrcm_txpkt(bus, pkt,
1469 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1470 SDPCM_DATA_CHANNEL), true);
1473 bus->dhd->tx_errors++;
1475 bus->dhd->dstats.tx_bytes += datalen;
1477 /* In poll mode, need to check for other events */
1478 if (!bus->intr && cnt) {
1479 /* Check device status, signal pending interrupt */
1480 R_SDREG(intstatus, ®s->intstatus, retries);
1482 if (brcmf_sdcard_regfail(bus->sdh))
1484 if (intstatus & bus->hostintmask)
1489 /* Deflow-control stack if needed */
1490 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1491 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1492 dhd_txflowcontrol(dhd, 0, OFF);
1498 brcmf_sdbrcm_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1504 bcmsdh_info_t *sdh = bus->sdh;
1509 DHD_TRACE(("%s: Enter\n", __func__));
1511 if (bus->dhd->dongle_reset)
1514 /* Back the pointer to make a room for bus header */
1515 frame = msg - SDPCM_HDRLEN;
1516 len = (msglen += SDPCM_HDRLEN);
1518 /* Add alignment padding (optional for ctl frames) */
1520 doff = ((unsigned long)frame % DHD_SDALIGN);
1525 memset(frame, 0, doff + SDPCM_HDRLEN);
1527 ASSERT(doff < DHD_SDALIGN);
1529 doff += SDPCM_HDRLEN;
1531 /* Round send length to next SDIO block */
1532 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1533 u16 pad = bus->blocksize - (len % bus->blocksize);
1534 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1536 } else if (len % DHD_SDALIGN) {
1537 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1540 /* Satisfy length-alignment requirements */
1541 if (forcealign && (len & (ALIGNMENT - 1)))
1542 len = roundup(len, ALIGNMENT);
1544 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1546 /* Need to lock here to protect txseq and SDIO tx calls */
1547 dhd_os_sdlock(bus->dhd);
1551 /* Make sure backplane clock is on */
1552 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1554 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1555 *(u16 *) frame = cpu_to_le16((u16) msglen);
1556 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1558 /* Software tag: channel, sequence number, data offset */
1560 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1562 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1563 SDPCM_DOFFSET_MASK);
1564 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1565 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1568 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1569 __func__, bus->tx_max, bus->tx_seq));
1570 bus->ctrl_frame_stat = true;
1572 bus->ctrl_frame_buf = frame;
1573 bus->ctrl_frame_len = len;
1575 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1577 if (bus->ctrl_frame_stat == false) {
1578 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1581 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1588 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1589 printk(KERN_DEBUG "Tx Frame:\n");
1590 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1592 } else if (DHD_HDRS_ON()) {
1593 printk(KERN_DEBUG "TxHdr:\n");
1594 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1595 frame, min_t(u16, len, 16));
1600 bus->ctrl_frame_stat = false;
1601 ret = brcmf_sdbrcm_send_buf(bus,
1602 brcmf_sdcard_cur_sbwad(sdh), SDIO_FUNC_2,
1603 F2SYNC, frame, len, NULL, NULL, NULL);
1605 ASSERT(ret != -BCME_PENDING);
1608 /* On failure, abort the command and
1609 terminate the frame */
1610 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1614 brcmf_sdcard_abort(sdh, SDIO_FUNC_2);
1616 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1617 SBSDIO_FUNC1_FRAMECTRL,
1621 for (i = 0; i < 3; i++) {
1623 hi = brcmf_sdcard_cfg_read(sdh,
1625 SBSDIO_FUNC1_WFRAMEBCHI,
1627 lo = brcmf_sdcard_cfg_read(sdh,
1629 SBSDIO_FUNC1_WFRAMEBCLO,
1631 bus->f1regdata += 2;
1632 if ((hi == 0) && (lo == 0))
1639 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1641 } while ((ret < 0) && retries++ < TXRETRIES);
1644 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1645 bus->activity = false;
1646 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1649 dhd_os_sdunlock(bus->dhd);
1652 bus->dhd->tx_ctlerrs++;
1654 bus->dhd->tx_ctlpkts++;
1656 return ret ? -EIO : 0;
1659 int brcmf_sdbrcm_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1665 DHD_TRACE(("%s: Enter\n", __func__));
1667 if (bus->dhd->dongle_reset)
1670 /* Wait until control frame is available */
1671 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1673 dhd_os_sdlock(bus->dhd);
1675 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1677 dhd_os_sdunlock(bus->dhd);
1680 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1681 __func__, rxlen, msglen));
1682 } else if (timeleft == 0) {
1683 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1685 dhd_os_sdlock(bus->dhd);
1686 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1687 dhd_os_sdunlock(bus->dhd);
1688 #endif /* DHD_DEBUG */
1689 } else if (pending == true) {
1690 DHD_CTL(("%s: cancelled\n", __func__));
1691 return -ERESTARTSYS;
1693 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1695 dhd_os_sdlock(bus->dhd);
1696 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1697 dhd_os_sdunlock(bus->dhd);
1698 #endif /* DHD_DEBUG */
1702 bus->dhd->rx_ctlpkts++;
1704 bus->dhd->rx_ctlerrs++;
1706 return rxlen ? (int)rxlen : -ETIMEDOUT;
1745 const struct brcmu_iovar dhdsdio_iovars[] = {
1746 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1747 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1748 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1749 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1750 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1751 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1752 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1753 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1754 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1755 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1756 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1757 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1758 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1759 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1760 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1761 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1763 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1765 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1767 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1769 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1771 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1773 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1775 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1777 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1780 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1782 #endif /* DHD_DEBUG */
1783 #endif /* DHD_DEBUG */
1785 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1787 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1795 dhd_dump_pct(struct brcmu_strbuf *strbuf, char *desc, uint num, uint div)
1800 brcmu_bprintf(strbuf, "%s N/A", desc);
1803 q2 = (100 * (num - (q1 * div))) / div;
1804 brcmu_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1808 void brcmf_sdbrcm_bus_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf)
1810 dhd_bus_t *bus = dhdp->bus;
1812 brcmu_bprintf(strbuf, "Bus SDIO structure:\n");
1813 brcmu_bprintf(strbuf,
1814 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1815 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1816 brcmu_bprintf(strbuf,
1817 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1818 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1819 bus->rxskip, bus->rxlen, bus->rx_seq);
1820 brcmu_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1821 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1822 brcmu_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1823 bus->pollrate, bus->pollcnt, bus->regfails);
1825 brcmu_bprintf(strbuf, "\nAdditional counters:\n");
1826 brcmu_bprintf(strbuf,
1827 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1828 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1830 brcmu_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1831 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1832 brcmu_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1833 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1834 brcmu_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1835 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1836 brcmu_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs"
1838 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1839 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1841 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1842 (bus->f2rxhdrs + bus->f2rxdata));
1843 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1845 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1846 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1847 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1849 brcmu_bprintf(strbuf, "\n");
1851 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1852 bus->dhd->rx_packets);
1853 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1855 brcmu_bprintf(strbuf, "\n");
1857 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1859 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1861 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1862 (bus->f2txdata + bus->f1regdata));
1863 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1865 brcmu_bprintf(strbuf, "\n");
1867 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1868 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1869 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1870 dhd_dump_pct(strbuf, ", pkts/f1sd",
1871 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1873 dhd_dump_pct(strbuf, ", pkts/sd",
1874 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1875 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1877 dhd_dump_pct(strbuf, ", pkts/int",
1878 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1880 brcmu_bprintf(strbuf, "\n\n");
1884 if (bus->pktgen_count) {
1885 brcmu_bprintf(strbuf, "pktgen config and count:\n");
1886 brcmu_bprintf(strbuf,
1887 "freq %d count %d print %d total %d min %d len %d\n",
1888 bus->pktgen_freq, bus->pktgen_count,
1889 bus->pktgen_print, bus->pktgen_total,
1890 bus->pktgen_minlen, bus->pktgen_maxlen);
1891 brcmu_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1892 bus->pktgen_sent, bus->pktgen_rcvd,
1897 brcmu_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1899 (brcmf_sdcard_intr_pending(bus->sdh) ? " " : " not "));
1900 brcmu_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1902 #endif /* DHD_DEBUG */
1903 brcmu_bprintf(strbuf,
1904 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1905 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1909 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1911 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1913 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1914 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1915 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1916 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1917 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1918 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1922 static int brcmf_sdbrcm_pktgen_get(dhd_bus_t *bus, u8 *arg)
1924 dhd_pktgen_t pktgen;
1926 pktgen.version = DHD_PKTGEN_VERSION;
1927 pktgen.freq = bus->pktgen_freq;
1928 pktgen.count = bus->pktgen_count;
1929 pktgen.print = bus->pktgen_print;
1930 pktgen.total = bus->pktgen_total;
1931 pktgen.minlen = bus->pktgen_minlen;
1932 pktgen.maxlen = bus->pktgen_maxlen;
1933 pktgen.numsent = bus->pktgen_sent;
1934 pktgen.numrcvd = bus->pktgen_rcvd;
1935 pktgen.numfail = bus->pktgen_fail;
1936 pktgen.mode = bus->pktgen_mode;
1937 pktgen.stop = bus->pktgen_stop;
1939 memcpy(arg, &pktgen, sizeof(pktgen));
1944 static int brcmf_sdbrcm_pktgen_set(dhd_bus_t *bus, u8 *arg)
1946 dhd_pktgen_t pktgen;
1947 uint oldcnt, oldmode;
1949 memcpy(&pktgen, arg, sizeof(pktgen));
1950 if (pktgen.version != DHD_PKTGEN_VERSION)
1953 oldcnt = bus->pktgen_count;
1954 oldmode = bus->pktgen_mode;
1956 bus->pktgen_freq = pktgen.freq;
1957 bus->pktgen_count = pktgen.count;
1958 bus->pktgen_print = pktgen.print;
1959 bus->pktgen_total = pktgen.total;
1960 bus->pktgen_minlen = pktgen.minlen;
1961 bus->pktgen_maxlen = pktgen.maxlen;
1962 bus->pktgen_mode = pktgen.mode;
1963 bus->pktgen_stop = pktgen.stop;
1965 bus->pktgen_tick = bus->pktgen_ptick = 0;
1966 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1967 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1969 /* Clear counts for a new pktgen (mode change, or was stopped) */
1970 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1971 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1978 brcmf_sdbrcm_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1985 /* Determine initial transfer parameters */
1986 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1987 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1988 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1992 /* Set the backplane window to include the start address */
1993 bcmerror = brcmf_sdbrcm_set_siaddr_window(bus, address);
1995 DHD_ERROR(("%s: window change failed\n", __func__));
1999 /* Do the transfer(s) */
2001 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
2002 __func__, (write ? "write" : "read"), dsize,
2003 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
2005 brcmf_sdcard_rwdata(bus->sdh, write, sdaddr, data, dsize);
2007 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
2011 /* Adjust for next transfer (if any) */
2016 bcmerror = brcmf_sdbrcm_set_siaddr_window(bus, address);
2018 DHD_ERROR(("%s: window change failed\n",
2023 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2028 /* Return the window to backplane enumeration space for core access */
2029 if (brcmf_sdbrcm_set_siaddr_window(bus,
2030 brcmf_sdcard_cur_sbwad(bus->sdh))) {
2031 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
2032 __func__, brcmf_sdcard_cur_sbwad(bus->sdh)));
2039 static int brcmf_sdbrcm_readshared(dhd_bus_t *bus, struct sdpcm_shared *sh)
2044 /* Read last word in memory to determine address of
2045 sdpcm_shared structure */
2046 rv = brcmf_sdbrcm_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr,
2051 addr = le32_to_cpu(addr);
2053 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
2056 * Check if addr is valid.
2057 * NVRAM length at the end of memory should have been overwritten.
2059 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2060 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
2065 /* Read rte_shared structure */
2066 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *) sh,
2067 sizeof(struct sdpcm_shared));
2072 sh->flags = le32_to_cpu(sh->flags);
2073 sh->trap_addr = le32_to_cpu(sh->trap_addr);
2074 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2075 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2076 sh->assert_line = le32_to_cpu(sh->assert_line);
2077 sh->console_addr = le32_to_cpu(sh->console_addr);
2078 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2080 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2081 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
2082 "is different than sdpcm_shared version %d in dongle\n",
2083 __func__, SDPCM_SHARED_VERSION,
2084 sh->flags & SDPCM_SHARED_VERSION_MASK));
2091 static int brcmf_sdbrcm_checkdied(dhd_bus_t *bus, u8 *data, uint size)
2095 char *mbuffer = NULL;
2096 uint maxstrlen = 256;
2099 struct sdpcm_shared sdpcm_shared;
2100 struct brcmu_strbuf strbuf;
2102 DHD_TRACE(("%s: Enter\n", __func__));
2106 * Called after a rx ctrl timeout. "data" is NULL.
2107 * allocate memory to trace the trap or assert.
2110 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2111 if (mbuffer == NULL) {
2112 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
2119 str = kmalloc(maxstrlen, GFP_ATOMIC);
2121 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
2126 bcmerror = brcmf_sdbrcm_readshared(bus, &sdpcm_shared);
2130 brcmu_binit(&strbuf, data, size);
2132 brcmu_bprintf(&strbuf,
2133 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
2134 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2136 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2137 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2138 * (Avoids conflict with real asserts for programmatic
2139 * parsing of output.)
2141 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
2144 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2146 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2147 * (Avoids conflict with real asserts for programmatic
2148 * parsing of output.)
2150 brcmu_bprintf(&strbuf, "No trap%s in dongle",
2151 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2154 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2155 /* Download assert */
2156 brcmu_bprintf(&strbuf, "Dongle assert");
2157 if (sdpcm_shared.assert_exp_addr != 0) {
2159 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2160 sdpcm_shared.assert_exp_addr,
2161 (u8 *) str, maxstrlen);
2165 str[maxstrlen - 1] = '\0';
2166 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
2169 if (sdpcm_shared.assert_file_addr != 0) {
2171 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2172 sdpcm_shared.assert_file_addr,
2173 (u8 *) str, maxstrlen);
2177 str[maxstrlen - 1] = '\0';
2178 brcmu_bprintf(&strbuf, " file \"%s\"", str);
2181 brcmu_bprintf(&strbuf, " line %d ",
2182 sdpcm_shared.assert_line);
2185 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2186 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2187 sdpcm_shared.trap_addr, (u8 *)&tr,
2192 brcmu_bprintf(&strbuf,
2193 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2194 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2195 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2196 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2197 tr.r14, tr.pc, sdpcm_shared.trap_addr,
2198 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2203 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2204 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2207 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2208 /* Mem dump to a file on device */
2209 brcmf_sdbrcm_mem_dump(bus);
2211 #endif /* DHD_DEBUG */
2220 static int brcmf_sdbrcm_mem_dump(dhd_bus_t *bus)
2223 int size; /* Full mem size */
2224 int start = 0; /* Start address */
2225 int read_size = 0; /* Read size of each iteration */
2226 u8 *buf = NULL, *databuf = NULL;
2228 /* Get full mem size */
2229 size = bus->ramsize;
2230 buf = kmalloc(size, GFP_ATOMIC);
2232 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2236 /* Read mem content */
2237 printk(KERN_DEBUG "Dump dongle memory");
2240 read_size = min(MEMBLOCK, size);
2241 ret = brcmf_sdbrcm_membytes(bus, false, start, databuf,
2244 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2250 /* Decrement size and increment start address */
2253 databuf += read_size;
2255 printk(KERN_DEBUG "Done\n");
2257 /* free buf before return !!! */
2258 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
2259 DHD_ERROR(("%s: Error writing to files\n", __func__));
2263 /* buf free handled in write_to_file, not here */
2267 #define CONSOLE_LINE_MAX 192
2269 static int brcmf_sdbrcm_readconsole(dhd_bus_t *bus)
2271 dhd_console_t *c = &bus->console;
2272 u8 line[CONSOLE_LINE_MAX], ch;
2276 /* Don't do anything until FWREADY updates console address */
2277 if (bus->console_addr == 0)
2280 /* Read console log struct */
2281 addr = bus->console_addr + offsetof(rte_cons_t, log);
2282 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log,
2287 /* Allocate console buffer (one time only) */
2288 if (c->buf == NULL) {
2289 c->bufsize = le32_to_cpu(c->log.buf_size);
2290 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2295 idx = le32_to_cpu(c->log.idx);
2297 /* Protect against corrupt value */
2298 if (idx > c->bufsize)
2301 /* Skip reading the console buffer if the index pointer
2306 /* Read the console buffer */
2307 addr = le32_to_cpu(c->log.buf);
2308 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2312 while (c->last != idx) {
2313 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2314 if (c->last == idx) {
2315 /* This would output a partial line.
2317 * the buffer pointer and output this
2318 * line next time around.
2323 c->last = c->bufsize - n;
2326 ch = c->buf[c->last];
2327 c->last = (c->last + 1) % c->bufsize;
2334 if (line[n - 1] == '\r')
2337 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2344 #endif /* DHD_DEBUG */
2346 int brcmf_sdbrcm_downloadvars(dhd_bus_t *bus, void *arg, int len)
2350 DHD_TRACE(("%s: Enter\n", __func__));
2352 /* Basic sanity checks */
2354 bcmerror = -EISCONN;
2358 bcmerror = -EOVERFLOW;
2362 /* Free the old ones and replace with passed variables */
2365 bus->vars = kmalloc(len, GFP_ATOMIC);
2366 bus->varsz = bus->vars ? len : 0;
2367 if (bus->vars == NULL) {
2372 /* Copy the passed variables, which should include the
2373 terminating double-null */
2374 memcpy(bus->vars, arg, bus->varsz);
2380 brcmf_sdbrcm_doiovar(dhd_bus_t *bus, const struct brcmu_iovar *vi, u32 actionid,
2381 const char *name, void *params, int plen, void *arg, int len,
2388 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2389 "len %d val_size %d\n",
2390 __func__, actionid, name, params, plen, arg, len, val_size));
2392 bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2396 if (plen >= (int)sizeof(int_val))
2397 memcpy(&int_val, params, sizeof(int_val));
2399 bool_val = (int_val != 0) ? true : false;
2401 /* Some ioctls use the bus */
2402 dhd_os_sdlock(bus->dhd);
2404 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2405 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2406 actionid == IOV_GVAL(IOV_DEVRESET))) {
2411 /* Handle sleep stuff before any clock mucking */
2412 if (vi->varid == IOV_SLEEP) {
2413 if (IOV_ISSET(actionid)) {
2414 bcmerror = brcmf_sdbrcm_bussleep(bus, bool_val);
2416 int_val = (s32) bus->sleeping;
2417 memcpy(arg, &int_val, val_size);
2422 /* Request clock to allow SDIO accesses */
2423 if (!bus->dhd->dongle_reset) {
2425 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2429 case IOV_GVAL(IOV_INTR):
2430 int_val = (s32) bus->intr;
2431 memcpy(arg, &int_val, val_size);
2434 case IOV_SVAL(IOV_INTR):
2435 bus->intr = bool_val;
2436 bus->intdis = false;
2439 DHD_INTR(("%s: enable SDIO device interrupts\n",
2441 brcmf_sdcard_intr_enable(bus->sdh);
2443 DHD_INTR(("%s: disable SDIO interrupts\n",
2445 brcmf_sdcard_intr_disable(bus->sdh);
2450 case IOV_GVAL(IOV_POLLRATE):
2451 int_val = (s32) bus->pollrate;
2452 memcpy(arg, &int_val, val_size);
2455 case IOV_SVAL(IOV_POLLRATE):
2456 bus->pollrate = (uint) int_val;
2457 bus->poll = (bus->pollrate != 0);
2460 case IOV_GVAL(IOV_IDLETIME):
2461 int_val = bus->idletime;
2462 memcpy(arg, &int_val, val_size);
2465 case IOV_SVAL(IOV_IDLETIME):
2466 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2469 bus->idletime = int_val;
2472 case IOV_GVAL(IOV_IDLECLOCK):
2473 int_val = (s32) bus->idleclock;
2474 memcpy(arg, &int_val, val_size);
2477 case IOV_SVAL(IOV_IDLECLOCK):
2478 bus->idleclock = int_val;
2481 case IOV_GVAL(IOV_SD1IDLE):
2482 int_val = (s32) sd1idle;
2483 memcpy(arg, &int_val, val_size);
2486 case IOV_SVAL(IOV_SD1IDLE):
2490 case IOV_SVAL(IOV_MEMBYTES):
2491 case IOV_GVAL(IOV_MEMBYTES):
2497 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2499 ASSERT(plen >= 2 * sizeof(int));
2501 address = (u32) int_val;
2502 memcpy(&int_val, (char *)params + sizeof(int_val),
2504 size = (uint) int_val;
2506 /* Do some validation */
2507 dsize = set ? plen - (2 * sizeof(int)) : len;
2509 DHD_ERROR(("%s: error on %s membytes, addr "
2510 "0x%08x size %d dsize %d\n",
2511 __func__, (set ? "set" : "get"),
2512 address, size, dsize));
2517 DHD_INFO(("%s: Request to %s %d bytes at address "
2519 __func__, (set ? "write" : "read"), size, address));
2521 /* If we know about SOCRAM, check for a fit */
2522 if ((bus->orig_ramsize) &&
2523 ((address > bus->orig_ramsize)
2524 || (address + size > bus->orig_ramsize))) {
2525 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2526 "bytes at 0x%08x\n",
2527 __func__, bus->orig_ramsize, size, address));
2532 /* Generate the actual data pointer */
2534 set ? (u8 *) params +
2535 2 * sizeof(int) : (u8 *) arg;
2537 /* Call to do the transfer */
2538 bcmerror = brcmf_sdbrcm_membytes(bus, set, address,
2544 case IOV_GVAL(IOV_MEMSIZE):
2545 int_val = (s32) bus->ramsize;
2546 memcpy(arg, &int_val, val_size);
2549 case IOV_GVAL(IOV_SDIOD_DRIVE):
2550 int_val = (s32) dhd_sdiod_drive_strength;
2551 memcpy(arg, &int_val, val_size);
2554 case IOV_SVAL(IOV_SDIOD_DRIVE):
2555 dhd_sdiod_drive_strength = int_val;
2556 brcmf_sdbrcm_sdiod_drive_strength_init(bus,
2557 dhd_sdiod_drive_strength);
2560 case IOV_SVAL(IOV_DOWNLOAD):
2561 bcmerror = brcmf_sdbrcm_download_state(bus, bool_val);
2564 case IOV_SVAL(IOV_VARS):
2565 bcmerror = brcmf_sdbrcm_downloadvars(bus, arg, len);
2568 case IOV_GVAL(IOV_READAHEAD):
2569 int_val = (s32) dhd_readahead;
2570 memcpy(arg, &int_val, val_size);
2573 case IOV_SVAL(IOV_READAHEAD):
2574 if (bool_val && !dhd_readahead)
2576 dhd_readahead = bool_val;
2579 case IOV_GVAL(IOV_SDRXCHAIN):
2580 int_val = (s32) bus->use_rxchain;
2581 memcpy(arg, &int_val, val_size);
2584 case IOV_SVAL(IOV_SDRXCHAIN):
2585 if (bool_val && !bus->sd_rxchain)
2586 bcmerror = -ENOTSUPP;
2588 bus->use_rxchain = bool_val;
2590 case IOV_GVAL(IOV_ALIGNCTL):
2591 int_val = (s32) dhd_alignctl;
2592 memcpy(arg, &int_val, val_size);
2595 case IOV_SVAL(IOV_ALIGNCTL):
2596 dhd_alignctl = bool_val;
2599 case IOV_GVAL(IOV_SDALIGN):
2600 int_val = DHD_SDALIGN;
2601 memcpy(arg, &int_val, val_size);
2605 case IOV_GVAL(IOV_VARS):
2606 if (bus->varsz < (uint) len)
2607 memcpy(arg, bus->vars, bus->varsz);
2609 bcmerror = -EOVERFLOW;
2611 #endif /* DHD_DEBUG */
2614 case IOV_GVAL(IOV_SDREG):
2619 sd_ptr = (sdreg_t *) params;
2621 addr = (unsigned long)bus->regs + sd_ptr->offset;
2622 size = sd_ptr->func;
2623 int_val = (s32) brcmf_sdcard_reg_read(bus->sdh, addr,
2625 if (brcmf_sdcard_regfail(bus->sdh))
2627 memcpy(arg, &int_val, sizeof(s32));
2631 case IOV_SVAL(IOV_SDREG):
2636 sd_ptr = (sdreg_t *) params;
2638 addr = (unsigned long)bus->regs + sd_ptr->offset;
2639 size = sd_ptr->func;
2640 brcmf_sdcard_reg_write(bus->sdh, addr, size,
2642 if (brcmf_sdcard_regfail(bus->sdh))
2647 /* Same as above, but offset is not backplane
2649 case IOV_GVAL(IOV_SBREG):
2654 memcpy(&sdreg, params, sizeof(sdreg));
2656 addr = SI_ENUM_BASE + sdreg.offset;
2658 int_val = (s32) brcmf_sdcard_reg_read(bus->sdh, addr,
2660 if (brcmf_sdcard_regfail(bus->sdh))
2662 memcpy(arg, &int_val, sizeof(s32));
2666 case IOV_SVAL(IOV_SBREG):
2671 memcpy(&sdreg, params, sizeof(sdreg));
2673 addr = SI_ENUM_BASE + sdreg.offset;
2675 brcmf_sdcard_reg_write(bus->sdh, addr, size,
2677 if (brcmf_sdcard_regfail(bus->sdh))
2682 case IOV_GVAL(IOV_SDCIS):
2686 strcat(arg, "\nFunc 0\n");
2687 brcmf_sdcard_cis_read(bus->sdh, 0x10,
2688 (u8 *) arg + strlen(arg),
2689 SBSDIO_CIS_SIZE_LIMIT);
2690 strcat(arg, "\nFunc 1\n");
2691 brcmf_sdcard_cis_read(bus->sdh, 0x11,
2692 (u8 *) arg + strlen(arg),
2693 SBSDIO_CIS_SIZE_LIMIT);
2694 strcat(arg, "\nFunc 2\n");
2695 brcmf_sdcard_cis_read(bus->sdh, 0x12,
2696 (u8 *) arg + strlen(arg),
2697 SBSDIO_CIS_SIZE_LIMIT);
2701 case IOV_GVAL(IOV_FORCEEVEN):
2702 int_val = (s32) forcealign;
2703 memcpy(arg, &int_val, val_size);
2706 case IOV_SVAL(IOV_FORCEEVEN):
2707 forcealign = bool_val;
2710 case IOV_GVAL(IOV_TXBOUND):
2711 int_val = (s32) dhd_txbound;
2712 memcpy(arg, &int_val, val_size);
2715 case IOV_SVAL(IOV_TXBOUND):
2716 dhd_txbound = (uint) int_val;
2719 case IOV_GVAL(IOV_RXBOUND):
2720 int_val = (s32) dhd_rxbound;
2721 memcpy(arg, &int_val, val_size);
2724 case IOV_SVAL(IOV_RXBOUND):
2725 dhd_rxbound = (uint) int_val;
2728 case IOV_GVAL(IOV_TXMINMAX):
2729 int_val = (s32) dhd_txminmax;
2730 memcpy(arg, &int_val, val_size);
2733 case IOV_SVAL(IOV_TXMINMAX):
2734 dhd_txminmax = (uint) int_val;
2736 #endif /* DHD_DEBUG */
2739 case IOV_GVAL(IOV_EXTLOOP):
2740 int_val = (s32) bus->ext_loop;
2741 memcpy(arg, &int_val, val_size);
2744 case IOV_SVAL(IOV_EXTLOOP):
2745 bus->ext_loop = bool_val;
2748 case IOV_GVAL(IOV_PKTGEN):
2749 bcmerror = brcmf_sdbrcm_pktgen_get(bus, arg);
2752 case IOV_SVAL(IOV_PKTGEN):
2753 bcmerror = brcmf_sdbrcm_pktgen_set(bus, arg);
2757 case IOV_SVAL(IOV_DEVRESET):
2758 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2760 __func__, bool_val, bus->dhd->dongle_reset,
2761 bus->dhd->busstate));
2763 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2767 case IOV_GVAL(IOV_DEVRESET):
2768 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2770 /* Get its status */
2771 int_val = (bool) bus->dhd->dongle_reset;
2772 memcpy(arg, &int_val, val_size);
2777 bcmerror = -ENOTSUPP;
2782 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2783 bus->activity = false;
2784 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2787 dhd_os_sdunlock(bus->dhd);
2789 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2790 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2795 static int brcmf_sdbrcm_write_vars(dhd_bus_t *bus)
2803 char *nvram_ularray;
2804 #endif /* DHD_DEBUG */
2806 /* Even if there are no vars are to be written, we still
2807 need to set the ramsize. */
2808 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2809 varaddr = (bus->ramsize - 4) - varsize;
2812 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2816 memcpy(vbuffer, bus->vars, bus->varsz);
2818 /* Write the vars list */
2820 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
2822 /* Verify NVRAM bytes */
2823 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2824 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2828 /* Upload image to verify downloaded contents. */
2829 memset(nvram_ularray, 0xaa, varsize);
2831 /* Read the vars list to temp buffer for comparison */
2833 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
2836 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2837 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2839 /* Compare the org NVRAM with the one read from RAM */
2840 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2841 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2844 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2847 kfree(nvram_ularray);
2848 #endif /* DHD_DEBUG */
2853 /* adjust to the user specified RAM */
2854 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2855 bus->orig_ramsize, bus->ramsize));
2856 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2857 varsize = ((bus->orig_ramsize - 4) - varaddr);
2860 * Determine the length token:
2861 * Varsize, converted to words, in lower 16-bits, checksum
2867 varsizew = varsize / 4;
2868 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2869 varsizew = cpu_to_le32(varsizew);
2872 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2875 /* Write the length token to the last word */
2876 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->orig_ramsize - 4),
2877 (u8 *)&varsizew, 4);
2882 static int brcmf_sdbrcm_download_state(dhd_bus_t *bus, bool enter)
2888 /* To enter download state, disable ARM and reset SOCRAM.
2889 * To exit download state, simply reset ARM (default is RAM boot).
2892 bus->alp_only = true;
2894 brcmf_sdbrcm_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2896 brcmf_sdbrcm_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2898 /* Clear the top bit of memory */
2901 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
2905 regdata = brcmf_sdcard_reg_read(bus->sdh,
2906 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2907 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2908 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2909 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2910 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2916 bcmerror = brcmf_sdbrcm_write_vars(bus);
2918 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2922 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2924 brcmf_sdbrcm_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2926 /* Allow HT Clock now that the ARM is running. */
2927 bus->alp_only = false;
2929 bus->dhd->busstate = DHD_BUS_LOAD;
2936 brcmf_sdbrcm_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2937 void *params, int plen, void *arg, int len, bool set)
2939 dhd_bus_t *bus = dhdp->bus;
2940 const struct brcmu_iovar *vi = NULL;
2945 DHD_TRACE(("%s: Enter\n", __func__));
2950 /* Get MUST have return space */
2951 ASSERT(set || (arg && len));
2953 /* Set does NOT take qualifiers */
2954 ASSERT(!set || (!params && !plen));
2956 /* Look up var locally; if not found pass to host driver */
2957 vi = brcmu_iovar_lookup(dhdsdio_iovars, name);
2959 dhd_os_sdlock(bus->dhd);
2963 /* Turn on clock in case SD command needs backplane */
2964 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2966 bcmerror = brcmf_sdcard_iovar_op(bus->sdh, name, params, plen,
2969 /* Similar check for blocksize change */
2970 if (set && strcmp(name, "sd_blocksize") == 0) {
2972 if (brcmf_sdcard_iovar_op
2973 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2974 &bus->blocksize, sizeof(s32),
2977 DHD_ERROR(("%s: fail on %s get\n", __func__,
2980 DHD_INFO(("%s: noted %s update, value now %d\n",
2981 __func__, "sd_blocksize",
2985 bus->roundup = min(max_roundup, bus->blocksize);
2987 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2988 bus->activity = false;
2989 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2992 dhd_os_sdunlock(bus->dhd);
2996 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2997 name, (set ? "set" : "get"), len, plen));
2999 /* set up 'params' pointer in case this is a set command so that
3000 * the convenience int and bool code can be common to set and get
3002 if (params == NULL) {
3007 if (vi->type == IOVT_VOID)
3009 else if (vi->type == IOVT_BUFFER)
3012 /* all other types are integer sized */
3013 val_size = sizeof(int);
3015 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
3016 bcmerror = brcmf_sdbrcm_doiovar(bus, vi, actionid, name, params, plen,
3017 arg, len, val_size);
3023 void brcmf_sdbrcm_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
3025 u32 local_hostintmask;
3030 DHD_TRACE(("%s: Enter\n", __func__));
3033 dhd_os_sdlock(bus->dhd);
3037 /* Enable clock for device interrupts */
3038 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3040 /* Disable and clear interrupts at the chip level also */
3041 W_SDREG(0, &bus->regs->hostintmask, retries);
3042 local_hostintmask = bus->hostintmask;
3043 bus->hostintmask = 0;
3045 /* Change our idea of bus state */
3046 bus->dhd->busstate = DHD_BUS_DOWN;
3048 /* Force clocks on backplane to be sure F2 interrupt propagates */
3049 saveclk = brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
3050 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3052 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
3053 SBSDIO_FUNC1_CHIPCLKCSR,
3054 (saveclk | SBSDIO_FORCE_HT), &err);
3057 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3061 /* Turn off the bus (F2), free any pending packets */
3062 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3063 brcmf_sdcard_intr_disable(bus->sdh);
3064 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3065 SDIO_FUNC_ENABLE_1, NULL);
3067 /* Clear any pending interrupts now that F2 is disabled */
3068 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
3070 /* Turn off the backplane clock (only) */
3071 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3073 /* Clear the data packet queues */
3074 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3076 /* Clear any held glomming stuff */
3078 brcmu_pkt_buf_free_skb(bus->glomd);
3081 brcmu_pkt_buf_free_skb(bus->glom);
3083 bus->glom = bus->glomd = NULL;
3085 /* Clear rx control and wake any waiters */
3087 dhd_os_ioctl_resp_wake(bus->dhd);
3089 /* Reset some F2 state stuff */
3090 bus->rxskip = false;
3091 bus->tx_seq = bus->rx_seq = 0;
3094 dhd_os_sdunlock(bus->dhd);
3097 int brcmf_sdbrcm_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
3099 dhd_bus_t *bus = dhdp->bus;
3106 DHD_TRACE(("%s: Enter\n", __func__));
3113 dhd_os_sdlock(bus->dhd);
3115 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3116 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3117 if (bus->clkstate != CLK_AVAIL)
3120 /* Force clocks on backplane to be sure F2 interrupt propagates */
3122 brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
3123 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3125 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
3126 SBSDIO_FUNC1_CHIPCLKCSR,
3127 (saveclk | SBSDIO_FORCE_HT), &err);
3130 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3135 /* Enable function 2 (frame transfers) */
3136 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
3137 &bus->regs->tosbmailboxdata, retries);
3138 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3140 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable,
3143 /* Give the dongle some time to do its thing and set IOR2 */
3144 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3147 while (ready != enable && !dhd_timeout_expired(&tmo))
3149 brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IORx,
3152 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3153 __func__, enable, ready, tmo.elapsed));
3155 /* If F2 successfully enabled, set core and enable interrupts */
3156 if (ready == enable) {
3157 /* Set up the interrupt mask and enable interrupts */
3158 bus->hostintmask = HOSTINTMASK;
3159 W_SDREG(bus->hostintmask,
3160 (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
3161 hostintmask), retries);
3163 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3164 (u8) watermark, &err);
3166 /* Set bus state according to enable result */
3167 dhdp->busstate = DHD_BUS_DATA;
3169 /* bcmsdh_intr_unmask(bus->sdh); */
3171 bus->intdis = false;
3173 DHD_INTR(("%s: enable SDIO device interrupts\n",
3175 brcmf_sdcard_intr_enable(bus->sdh);
3177 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3178 brcmf_sdcard_intr_disable(bus->sdh);
3184 /* Disable F2 again */
3185 enable = SDIO_FUNC_ENABLE_1;
3186 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3190 /* Restore previous clock setting */
3191 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3194 /* If we didn't come up, turn off backplane clock */
3195 if (dhdp->busstate != DHD_BUS_DATA)
3196 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3200 dhd_os_sdunlock(bus->dhd);
3205 static void brcmf_sdbrcm_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3207 bcmsdh_info_t *sdh = bus->sdh;
3208 struct sdpcmd_regs *regs = bus->regs;
3214 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3215 (abort ? "abort command, " : ""),
3216 (rtx ? ", send NAK" : "")));
3219 brcmf_sdcard_abort(sdh, SDIO_FUNC_2);
3221 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
3225 /* Wait until the packet has been flushed (device/FIFO stable) */
3226 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3227 hi = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
3228 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
3229 lo = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
3230 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
3231 bus->f1regdata += 2;
3233 if ((hi == 0) && (lo == 0))
3236 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3237 DHD_ERROR(("%s: count growing: last 0x%04x now "
3239 __func__, lastrbc, ((hi << 8) + lo)));
3241 lastrbc = (hi << 8) + lo;
3245 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3246 __func__, lastrbc));
3248 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3249 (0xffff - retries)));
3254 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3256 if (retries <= retry_limit)
3260 /* Clear partial in any case */
3263 /* If we can't reach the device, signal failure */
3264 if (err || brcmf_sdcard_regfail(sdh))
3265 bus->dhd->busstate = DHD_BUS_DOWN;
3269 brcmf_sdbrcm_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3271 bcmsdh_info_t *sdh = bus->sdh;
3276 DHD_TRACE(("%s: Enter\n", __func__));
3278 /* Control data already received in aligned rxctl */
3279 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3283 /* Set rxctl for frame (w/optional alignment) */
3284 bus->rxctl = bus->rxbuf;
3286 bus->rxctl += firstread;
3287 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3289 bus->rxctl += (DHD_SDALIGN - pad);
3290 bus->rxctl -= firstread;
3292 ASSERT(bus->rxctl >= bus->rxbuf);
3294 /* Copy the already-read portion over */
3295 memcpy(bus->rxctl, hdr, firstread);
3296 if (len <= firstread)
3299 /* Copy the full data pkt in gSPI case and process ioctl. */
3300 if (bus->bus == SPI_BUS) {
3301 memcpy(bus->rxctl, hdr, len);
3305 /* Raise rdlen to next SDIO block to avoid tail command */
3306 rdlen = len - firstread;
3307 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3308 pad = bus->blocksize - (rdlen % bus->blocksize);
3309 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3310 ((len + pad) < bus->dhd->maxctl))
3312 } else if (rdlen % DHD_SDALIGN) {
3313 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3316 /* Satisfy length-alignment requirements */
3317 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3318 rdlen = roundup(rdlen, ALIGNMENT);
3320 /* Drop if the read is too big or it exceeds our maximum */
3321 if ((rdlen + firstread) > bus->dhd->maxctl) {
3322 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3323 __func__, rdlen, bus->dhd->maxctl));
3324 bus->dhd->rx_errors++;
3325 brcmf_sdbrcm_rxfail(bus, false, false);
3329 if ((len - doff) > bus->dhd->maxctl) {
3330 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3332 __func__, len, (len - doff), bus->dhd->maxctl));
3333 bus->dhd->rx_errors++;
3335 brcmf_sdbrcm_rxfail(bus, false, false);
3339 /* Read remainder of frame body into the rxctl buffer */
3340 sdret = brcmf_sdcard_recv_buf(sdh, brcmf_sdcard_cur_sbwad(sdh),
3342 F2SYNC, (bus->rxctl + firstread), rdlen,
3345 ASSERT(sdret != -BCME_PENDING);
3347 /* Control frame failures need retransmission */
3349 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3350 __func__, rdlen, sdret));
3351 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3352 brcmf_sdbrcm_rxfail(bus, true, true);
3359 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3360 printk(KERN_DEBUG "RxCtrl:\n");
3361 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3365 /* Point to valid data and indicate its length */
3367 bus->rxlen = len - doff;
3370 /* Awake any waiters */
3371 dhd_os_ioctl_resp_wake(bus->dhd);
3374 static u8 brcmf_sdbrcm_rxglom(dhd_bus_t *bus, u8 rxseq)
3380 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3383 u8 chan, seq, doff, sfdoff;
3387 bool usechain = bus->use_rxchain;
3389 /* If packets, issue read(s) and send up packet chain */
3390 /* Return sequence numbers consumed? */
3392 DHD_TRACE(("brcmf_sdbrcm_rxglom: start: glomd %p glom %p\n", bus->glomd,
3395 /* If there's a descriptor, generate the packet chain */
3397 pfirst = plast = pnext = NULL;
3398 dlen = (u16) (bus->glomd->len);
3399 dptr = bus->glomd->data;
3400 if (!dlen || (dlen & 1)) {
3401 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3406 for (totlen = num = 0; dlen; num++) {
3407 /* Get (and move past) next length */
3408 sublen = get_unaligned_le16(dptr);
3409 dlen -= sizeof(u16);
3410 dptr += sizeof(u16);
3411 if ((sublen < SDPCM_HDRLEN) ||
3412 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3413 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3414 __func__, num, sublen));
3418 if (sublen % DHD_SDALIGN) {
3419 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3420 __func__, sublen, DHD_SDALIGN));
3425 /* For last frame, adjust read len so total
3426 is a block multiple */
3429 (roundup(totlen, bus->blocksize) - totlen);
3430 totlen = roundup(totlen, bus->blocksize);
3433 /* Allocate/chain packet for next subframe */
3434 pnext = brcmu_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3435 if (pnext == NULL) {
3436 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3437 "num %d len %d\n", __func__,
3441 ASSERT(!(pnext->prev));
3444 pfirst = plast = pnext;
3447 plast->next = pnext;
3451 /* Adhere to start alignment requirements */
3452 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3455 /* If all allocations succeeded, save packet chain
3458 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3459 "subframes\n", __func__, totlen, num));
3460 if (DHD_GLOM_ON() && bus->nextlen) {
3461 if (totlen != bus->nextlen) {
3462 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3463 __func__, bus->nextlen,
3468 pfirst = pnext = NULL;
3471 brcmu_pkt_buf_free_skb(pfirst);
3476 /* Done with descriptor packet */
3477 brcmu_pkt_buf_free_skb(bus->glomd);
3482 /* Ok -- either we just generated a packet chain,
3483 or had one from before */
3485 if (DHD_GLOM_ON()) {
3486 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3488 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3489 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3490 pnext, (u8 *) (pnext->data),
3491 pnext->len, pnext->len));
3496 dlen = (u16) brcmu_pkttotlen(pfirst);
3498 /* Do an SDIO read for the superframe. Configurable iovar to
3499 * read directly into the chained packet, or allocate a large
3500 * packet and and copy into the chain.
3503 errcode = brcmf_sdcard_recv_buf(bus->sdh,
3504 brcmf_sdcard_cur_sbwad(bus->sdh),
3506 F2SYNC, (u8 *) pfirst->data, dlen,
3507 pfirst, NULL, NULL);
3508 } else if (bus->dataptr) {
3509 errcode = brcmf_sdcard_recv_buf(bus->sdh,
3510 brcmf_sdcard_cur_sbwad(bus->sdh),
3512 F2SYNC, bus->dataptr, dlen,
3514 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
3516 if (sublen != dlen) {
3517 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3518 __func__, dlen, sublen));
3523 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3528 ASSERT(errcode != -BCME_PENDING);
3530 /* On failure, kill the superframe, allow a couple retries */
3532 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3533 __func__, dlen, errcode));
3534 bus->dhd->rx_errors++;
3536 if (bus->glomerr++ < 3) {
3537 brcmf_sdbrcm_rxfail(bus, true, true);
3540 brcmf_sdbrcm_rxfail(bus, true, false);
3541 brcmu_pkt_buf_free_skb(bus->glom);
3548 if (DHD_GLOM_ON()) {
3549 printk(KERN_DEBUG "SUPERFRAME:\n");
3550 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3551 pfirst->data, min_t(int, pfirst->len, 48));
3555 /* Validate the superframe header */
3556 dptr = (u8 *) (pfirst->data);
3557 sublen = get_unaligned_le16(dptr);
3558 check = get_unaligned_le16(dptr + sizeof(u16));
3560 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3561 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3562 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3563 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3564 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3565 __func__, bus->nextlen, seq));
3568 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3569 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3572 if ((u16)~(sublen ^ check)) {
3573 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3574 "0x%04x/0x%04x\n", __func__, sublen, check));
3576 } else if (roundup(sublen, bus->blocksize) != dlen) {
3577 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3578 "0x%04x, expect 0x%04x\n",
3580 roundup(sublen, bus->blocksize), dlen));
3582 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3583 SDPCM_GLOM_CHANNEL) {
3584 DHD_ERROR(("%s (superframe): bad channel %d\n",
3586 SDPCM_PACKET_CHANNEL(&dptr
3587 [SDPCM_FRAMETAG_LEN])));
3589 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3590 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3593 } else if ((doff < SDPCM_HDRLEN) ||
3594 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3595 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3597 __func__, doff, sublen,
3598 pfirst->len, SDPCM_HDRLEN));
3602 /* Check sequence number of superframe SW header */
3604 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3605 __func__, seq, rxseq));
3610 /* Check window for sanity */
3611 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3612 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3613 __func__, txmax, bus->tx_seq));
3614 txmax = bus->tx_seq + 2;
3616 bus->tx_max = txmax;
3618 /* Remove superframe header, remember offset */
3619 skb_pull(pfirst, doff);
3622 /* Validate all the subframe headers */
3623 for (num = 0, pnext = pfirst; pnext && !errcode;
3624 num++, pnext = pnext->next) {
3625 dptr = (u8 *) (pnext->data);
3626 dlen = (u16) (pnext->len);
3627 sublen = get_unaligned_le16(dptr);
3628 check = get_unaligned_le16(dptr + sizeof(u16));
3629 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3630 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3632 if (DHD_GLOM_ON()) {
3633 printk(KERN_DEBUG "subframe:\n");
3634 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3639 if ((u16)~(sublen ^ check)) {
3640 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3641 "len/check 0x%04x/0x%04x\n",
3642 __func__, num, sublen, check));
3644 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3645 DHD_ERROR(("%s (subframe %d): length mismatch: "
3646 "len 0x%04x, expect 0x%04x\n",
3647 __func__, num, sublen, dlen));
3649 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3650 (chan != SDPCM_EVENT_CHANNEL)) {
3651 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3652 __func__, num, chan));
3654 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3655 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3656 __func__, num, doff, sublen,
3663 /* Terminate frame on error, request
3665 if (bus->glomerr++ < 3) {
3666 /* Restore superframe header space */
3667 skb_push(pfirst, sfdoff);
3668 brcmf_sdbrcm_rxfail(bus, true, true);
3671 brcmf_sdbrcm_rxfail(bus, true, false);
3672 brcmu_pkt_buf_free_skb(bus->glom);
3680 /* Basic SD framing looks ok - process each packet (header) */
3681 save_pfirst = pfirst;
3685 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3686 pnext = pfirst->next;
3687 pfirst->next = NULL;
3689 dptr = (u8 *) (pfirst->data);
3690 sublen = get_unaligned_le16(dptr);
3691 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3692 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3693 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3695 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3697 __func__, num, pfirst, pfirst->data,
3698 pfirst->len, sublen, chan, seq));
3700 ASSERT((chan == SDPCM_DATA_CHANNEL)
3701 || (chan == SDPCM_EVENT_CHANNEL));
3704 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3705 __func__, seq, rxseq));
3710 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3711 printk(KERN_DEBUG "Rx Subframe Data:\n");
3712 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3717 __skb_trim(pfirst, sublen);
3718 skb_pull(pfirst, doff);
3720 if (pfirst->len == 0) {
3721 brcmu_pkt_buf_free_skb(pfirst);
3723 plast->next = pnext;
3725 ASSERT(save_pfirst == pfirst);
3726 save_pfirst = pnext;
3729 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3731 DHD_ERROR(("%s: rx protocol error\n",
3733 bus->dhd->rx_errors++;
3734 brcmu_pkt_buf_free_skb(pfirst);
3736 plast->next = pnext;
3738 ASSERT(save_pfirst == pfirst);
3739 save_pfirst = pnext;
3744 /* this packet will go up, link back into
3745 chain and count it */
3746 pfirst->next = pnext;
3751 if (DHD_GLOM_ON()) {
3752 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3754 __func__, num, pfirst, pfirst->data,
3755 pfirst->len, pfirst->next,
3757 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3759 min_t(int, pfirst->len, 32));
3761 #endif /* DHD_DEBUG */
3764 dhd_os_sdunlock(bus->dhd);
3765 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3766 dhd_os_sdlock(bus->dhd);
3769 bus->rxglomframes++;
3770 bus->rxglompkts += num;
3775 /* Return true if there may be more frames to read */
3777 brcmf_sdbrcm_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3779 bcmsdh_info_t *sdh = bus->sdh;
3781 u16 len, check; /* Extracted hardware header fields */
3782 u8 chan, seq, doff; /* Extracted software header fields */
3783 u8 fcbits; /* Extracted fcbits from software header */
3785 struct sk_buff *pkt; /* Packet for event or data frames */
3786 u16 pad; /* Number of pad bytes to read */
3787 u16 rdlen; /* Total number of bytes to read */
3788 u8 rxseq; /* Next sequence number to expect */
3789 uint rxleft = 0; /* Remaining number of frames allowed */
3790 int sdret; /* Return code from bcmsdh calls */
3791 u8 txmax; /* Maximum tx sequence offered */
3792 bool len_consistent; /* Result of comparing readahead len and
3796 uint rxcount = 0; /* Total frames read */
3798 #if defined(DHD_DEBUG) || defined(SDTEST)
3799 bool sdtest = false; /* To limit message spew from test mode */
3802 DHD_TRACE(("%s: Enter\n", __func__));
3807 /* Allow pktgen to override maxframes */
3808 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3809 maxframes = bus->pktgen_count;
3814 /* Not finished unless we encounter no more frames indication */
3817 for (rxseq = bus->rx_seq, rxleft = maxframes;
3818 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3819 rxseq++, rxleft--) {
3821 /* Handle glomming separately */
3822 if (bus->glom || bus->glomd) {
3824 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3825 __func__, bus->glomd, bus->glom));
3826 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
3827 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3829 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3833 /* Try doing single read if we can */
3834 if (dhd_readahead && bus->nextlen) {
3835 u16 nextlen = bus->nextlen;
3838 if (bus->bus == SPI_BUS) {
3839 rdlen = len = nextlen;
3841 rdlen = len = nextlen << 4;
3843 /* Pad read to blocksize for efficiency */
3844 if (bus->roundup && bus->blocksize
3845 && (rdlen > bus->blocksize)) {
3848 (rdlen % bus->blocksize);
3849 if ((pad <= bus->roundup)
3850 && (pad < bus->blocksize)
3851 && ((rdlen + pad + firstread) <
3854 } else if (rdlen % DHD_SDALIGN) {
3856 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3860 /* We use bus->rxctl buffer in WinXP for initial
3861 * control pkt receives.
3862 * Later we use buffer-poll for data as well
3863 * as control packets.
3864 * This is required because dhd receives full
3865 * frame in gSPI unlike SDIO.
3866 * After the frame is received we have to
3867 * distinguish whether it is data
3868 * or non-data frame.
3870 /* Allocate a packet buffer */
3871 pkt = brcmu_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3873 if (bus->bus == SPI_BUS) {
3874 bus->usebufpool = false;
3875 bus->rxctl = bus->rxbuf;
3877 bus->rxctl += firstread;
3878 pad = ((unsigned long)bus->rxctl %
3882 (DHD_SDALIGN - pad);
3883 bus->rxctl -= firstread;
3885 ASSERT(bus->rxctl >= bus->rxbuf);
3887 /* Read the entire frame */
3888 sdret = brcmf_sdcard_recv_buf(sdh,
3889 brcmf_sdcard_cur_sbwad(sdh),
3890 SDIO_FUNC_2, F2SYNC,
3894 ASSERT(sdret != -BCME_PENDING);
3896 /* Control frame failures need
3899 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3902 /* dhd.rx_ctlerrs is higher */
3904 brcmf_sdbrcm_rxfail(bus, true,
3912 request rtx of events */
3913 DHD_ERROR(("%s (nextlen): "
3914 "brcmu_pkt_buf_get_skb "
3916 " len %d rdlen %d expected"
3917 " rxseq %d\n", __func__,
3918 len, rdlen, rxseq));
3922 if (bus->bus == SPI_BUS)
3923 bus->usebufpool = true;
3925 ASSERT(!(pkt->prev));
3926 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3927 rxbuf = (u8 *) (pkt->data);
3928 /* Read the entire frame */
3929 sdret = brcmf_sdcard_recv_buf(sdh,
3930 brcmf_sdcard_cur_sbwad(sdh),
3931 SDIO_FUNC_2, F2SYNC,
3935 ASSERT(sdret != -BCME_PENDING);
3938 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3939 __func__, rdlen, sdret));
3940 brcmu_pkt_buf_free_skb(pkt);
3941 bus->dhd->rx_errors++;
3942 /* Force retry w/normal header read.
3943 * Don't attempt NAK for
3946 brcmf_sdbrcm_rxfail(bus, true,
3954 /* Now check the header */
3955 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3957 /* Extract hardware header fields */
3958 len = get_unaligned_le16(bus->rxhdr);
3959 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3961 /* All zeros means readahead info was bad */
3962 if (!(len | check)) {
3963 DHD_INFO(("%s (nextlen): read zeros in HW "
3964 "header???\n", __func__));
3965 brcmf_sdbrcm_pktfree2(bus, pkt);
3969 /* Validate check bytes */
3970 if ((u16)~(len ^ check)) {
3971 DHD_ERROR(("%s (nextlen): HW hdr error:"
3972 " nextlen/len/check"
3973 " 0x%04x/0x%04x/0x%04x\n",
3974 __func__, nextlen, len, check));
3976 brcmf_sdbrcm_rxfail(bus, false, false);
3977 brcmf_sdbrcm_pktfree2(bus, pkt);
3981 /* Validate frame length */
3982 if (len < SDPCM_HDRLEN) {
3983 DHD_ERROR(("%s (nextlen): HW hdr length "
3984 "invalid: %d\n", __func__, len));
3985 brcmf_sdbrcm_pktfree2(bus, pkt);
3989 /* Check for consistency withreadahead info */
3990 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3991 if (len_consistent) {
3992 /* Mismatch, force retry w/normal
3993 header (may be >4K) */
3994 DHD_ERROR(("%s (nextlen): mismatch, "
3995 "nextlen %d len %d rnd %d; "
3996 "expected rxseq %d\n",
3998 len, roundup(len, 16), rxseq));
3999 brcmf_sdbrcm_rxfail(bus, true,
4000 bus->bus != SPI_BUS);
4001 brcmf_sdbrcm_pktfree2(bus, pkt);
4005 /* Extract software header fields */
4006 chan = SDPCM_PACKET_CHANNEL(
4007 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4008 seq = SDPCM_PACKET_SEQUENCE(
4009 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4010 doff = SDPCM_DOFFSET_VALUE(
4011 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4012 txmax = SDPCM_WINDOW_VALUE(
4013 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4016 bus->rxhdr[SDPCM_FRAMETAG_LEN +
4017 SDPCM_NEXTLEN_OFFSET];
4018 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4019 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
4020 __func__, bus->nextlen, seq));
4024 bus->dhd->rx_readahead_cnt++;
4026 /* Handle Flow Control */
4027 fcbits = SDPCM_FCMASK_VALUE(
4028 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4030 if (bus->flowcontrol != fcbits) {
4031 if (~bus->flowcontrol & fcbits)
4034 if (bus->flowcontrol & ~fcbits)
4038 bus->flowcontrol = fcbits;
4041 /* Check and update sequence number */
4043 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
4044 "%d\n", __func__, seq, rxseq));
4049 /* Check window for sanity */
4050 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4051 DHD_ERROR(("%s: got unlikely tx max %d with "
4053 __func__, txmax, bus->tx_seq));
4054 txmax = bus->tx_seq + 2;
4056 bus->tx_max = txmax;
4059 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4060 printk(KERN_DEBUG "Rx Data:\n");
4061 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4063 } else if (DHD_HDRS_ON()) {
4064 printk(KERN_DEBUG "RxHdr:\n");
4065 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4066 bus->rxhdr, SDPCM_HDRLEN);
4070 if (chan == SDPCM_CONTROL_CHANNEL) {
4071 if (bus->bus == SPI_BUS) {
4072 brcmf_sdbrcm_read_control(bus, rxbuf,
4075 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
4077 /* Force retry w/normal header read */
4079 brcmf_sdbrcm_rxfail(bus, false, true);
4081 brcmf_sdbrcm_pktfree2(bus, pkt);
4085 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4086 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
4091 /* Validate data offset */
4092 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4093 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4094 __func__, doff, len, SDPCM_HDRLEN));
4095 brcmf_sdbrcm_rxfail(bus, false, false);
4096 brcmf_sdbrcm_pktfree2(bus, pkt);
4100 /* All done with this one -- now deliver the packet */
4103 /* gSPI frames should not be handled in fractions */
4104 if (bus->bus == SPI_BUS)
4107 /* Read frame header (hardware and software) */
4108 sdret = brcmf_sdcard_recv_buf(sdh, brcmf_sdcard_cur_sbwad(sdh),
4109 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
4112 ASSERT(sdret != -BCME_PENDING);
4115 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
4118 brcmf_sdbrcm_rxfail(bus, true, true);
4122 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4123 printk(KERN_DEBUG "RxHdr:\n");
4124 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4125 bus->rxhdr, SDPCM_HDRLEN);
4129 /* Extract hardware header fields */
4130 len = get_unaligned_le16(bus->rxhdr);
4131 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4133 /* All zeros means no more frames */
4134 if (!(len | check)) {
4139 /* Validate check bytes */
4140 if ((u16) ~(len ^ check)) {
4141 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4142 __func__, len, check));
4144 brcmf_sdbrcm_rxfail(bus, false, false);
4148 /* Validate frame length */
4149 if (len < SDPCM_HDRLEN) {
4150 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4155 /* Extract software header fields */
4156 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4157 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4158 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4159 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4161 /* Validate data offset */
4162 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4163 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4165 __func__, doff, len, SDPCM_HDRLEN, seq));
4168 brcmf_sdbrcm_rxfail(bus, false, false);
4172 /* Save the readahead length if there is one */
4174 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4175 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4176 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4178 __func__, bus->nextlen, seq));
4182 /* Handle Flow Control */
4183 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4185 if (bus->flowcontrol != fcbits) {
4186 if (~bus->flowcontrol & fcbits)
4189 if (bus->flowcontrol & ~fcbits)
4193 bus->flowcontrol = fcbits;
4196 /* Check and update sequence number */
4198 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4204 /* Check window for sanity */
4205 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4206 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4207 __func__, txmax, bus->tx_seq));
4208 txmax = bus->tx_seq + 2;
4210 bus->tx_max = txmax;
4212 /* Call a separate function for control frames */
4213 if (chan == SDPCM_CONTROL_CHANNEL) {
4214 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
4218 ASSERT((chan == SDPCM_DATA_CHANNEL)
4219 || (chan == SDPCM_EVENT_CHANNEL)
4220 || (chan == SDPCM_TEST_CHANNEL)
4221 || (chan == SDPCM_GLOM_CHANNEL));
4223 /* Length to read */
4224 rdlen = (len > firstread) ? (len - firstread) : 0;
4226 /* May pad read to blocksize for efficiency */
4227 if (bus->roundup && bus->blocksize &&
4228 (rdlen > bus->blocksize)) {
4229 pad = bus->blocksize - (rdlen % bus->blocksize);
4230 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4231 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4233 } else if (rdlen % DHD_SDALIGN) {
4234 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4237 /* Satisfy length-alignment requirements */
4238 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4239 rdlen = roundup(rdlen, ALIGNMENT);
4241 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4242 /* Too long -- skip this frame */
4243 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4244 __func__, len, rdlen));
4245 bus->dhd->rx_errors++;
4247 brcmf_sdbrcm_rxfail(bus, false, false);
4251 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4253 /* Give up on data, request rtx of events */
4254 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed: rdlen %d"
4255 " chan %d\n", __func__, rdlen, chan));
4256 bus->dhd->rx_dropped++;
4257 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
4261 ASSERT(!(pkt->prev));
4263 /* Leave room for what we already read, and align remainder */
4264 ASSERT(firstread < pkt->len);
4265 skb_pull(pkt, firstread);
4266 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4268 /* Read the remaining frame data */
4269 sdret = brcmf_sdcard_recv_buf(sdh, brcmf_sdcard_cur_sbwad(sdh),
4270 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
4271 rdlen, pkt, NULL, NULL);
4273 ASSERT(sdret != -BCME_PENDING);
4276 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4279 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4281 ? "data" : "test")),
4283 brcmu_pkt_buf_free_skb(pkt);
4284 bus->dhd->rx_errors++;
4285 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
4289 /* Copy the already-read portion */
4290 skb_push(pkt, firstread);
4291 memcpy(pkt->data, bus->rxhdr, firstread);
4294 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4295 printk(KERN_DEBUG "Rx Data:\n");
4296 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4302 /* Save superframe descriptor and allocate packet frame */
4303 if (chan == SDPCM_GLOM_CHANNEL) {
4304 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4305 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4308 if (DHD_GLOM_ON()) {
4309 printk(KERN_DEBUG "Glom Data:\n");
4310 print_hex_dump_bytes("",
4315 __skb_trim(pkt, len);
4316 ASSERT(doff == SDPCM_HDRLEN);
4317 skb_pull(pkt, SDPCM_HDRLEN);
4320 DHD_ERROR(("%s: glom superframe w/o "
4321 "descriptor!\n", __func__));
4322 brcmf_sdbrcm_rxfail(bus, false, false);
4327 /* Fill in packet len and prio, deliver upward */
4328 __skb_trim(pkt, len);
4329 skb_pull(pkt, doff);
4332 /* Test channel packets are processed separately */
4333 if (chan == SDPCM_TEST_CHANNEL) {
4334 brcmf_sdbrcm_checkdied(bus, pkt, seq);
4339 if (pkt->len == 0) {
4340 brcmu_pkt_buf_free_skb(pkt);
4342 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4343 DHD_ERROR(("%s: rx protocol error\n", __func__));
4344 brcmu_pkt_buf_free_skb(pkt);
4345 bus->dhd->rx_errors++;
4349 /* Unlock during rx call */
4350 dhd_os_sdunlock(bus->dhd);
4351 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4352 dhd_os_sdlock(bus->dhd);
4354 rxcount = maxframes - rxleft;
4356 /* Message if we hit the limit */
4357 if (!rxleft && !sdtest)
4358 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4361 #endif /* DHD_DEBUG */
4362 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4363 /* Back off rxseq if awaiting rtx, update rx_seq */
4366 bus->rx_seq = rxseq;
4371 static u32 brcmf_sdbrcm_hostmail(dhd_bus_t *bus)
4373 struct sdpcmd_regs *regs = bus->regs;
4379 DHD_TRACE(("%s: Enter\n", __func__));
4381 /* Read mailbox data and ack that we did so */
4382 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4383 if (retries <= retry_limit)
4384 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4385 bus->f1regdata += 2;
4387 /* Dongle recomposed rx frames, accept them again */
4388 if (hmb_data & HMB_DATA_NAKHANDLED) {
4389 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4392 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4394 bus->rxskip = false;
4395 intstatus |= I_HMB_FRAME_IND;
4399 * DEVREADY does not occur with gSPI.
4401 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4403 (hmb_data & HMB_DATA_VERSION_MASK) >>
4404 HMB_DATA_VERSION_SHIFT;
4405 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4406 DHD_ERROR(("Version mismatch, dongle reports %d, "
4408 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4410 DHD_INFO(("Dongle ready, protocol version %d\n",
4415 * Flow Control has been moved into the RX headers and this out of band
4416 * method isn't used any more.
4417 * remaining backward compatible with older dongles.
4419 if (hmb_data & HMB_DATA_FC) {
4420 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4421 HMB_DATA_FCDATA_SHIFT;
4423 if (fcbits & ~bus->flowcontrol)
4426 if (bus->flowcontrol & ~fcbits)
4430 bus->flowcontrol = fcbits;
4433 /* Shouldn't be any others */
4434 if (hmb_data & ~(HMB_DATA_DEVREADY |
4435 HMB_DATA_NAKHANDLED |
4438 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4439 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4445 bool brcmf_sdbrcm_dpc(dhd_bus_t *bus)
4447 bcmsdh_info_t *sdh = bus->sdh;
4448 struct sdpcmd_regs *regs = bus->regs;
4449 u32 intstatus, newstatus = 0;
4451 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4452 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4453 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4454 bool rxdone = true; /* Flag for no more read data */
4455 bool resched = false; /* Flag indicating resched wanted */
4457 DHD_TRACE(("%s: Enter\n", __func__));
4459 /* Start with leftover status bits */
4460 intstatus = bus->intstatus;
4462 dhd_os_sdlock(bus->dhd);
4464 /* If waiting for HTAVAIL, check status */
4465 if (bus->clkstate == CLK_PENDING) {
4467 u8 clkctl, devctl = 0;
4470 /* Check for inconsistent device control */
4471 devctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4472 SBSDIO_DEVICE_CTL, &err);
4474 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4476 bus->dhd->busstate = DHD_BUS_DOWN;
4478 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4480 #endif /* DHD_DEBUG */
4482 /* Read CSR, if clock on switch to AVAIL, else ignore */
4483 clkctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4484 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4486 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4488 bus->dhd->busstate = DHD_BUS_DOWN;
4491 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4494 if (SBSDIO_HTAV(clkctl)) {
4495 devctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4496 SBSDIO_DEVICE_CTL, &err);
4498 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4500 bus->dhd->busstate = DHD_BUS_DOWN;
4502 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4503 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
4504 SBSDIO_DEVICE_CTL, devctl, &err);
4506 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4508 bus->dhd->busstate = DHD_BUS_DOWN;
4510 bus->clkstate = CLK_AVAIL;
4518 /* Make sure backplane clock is on */
4519 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
4520 if (bus->clkstate == CLK_PENDING)
4523 /* Pending interrupt indicates new device status */
4526 R_SDREG(newstatus, ®s->intstatus, retries);
4528 if (brcmf_sdcard_regfail(bus->sdh))
4530 newstatus &= bus->hostintmask;
4531 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4533 W_SDREG(newstatus, ®s->intstatus, retries);
4538 /* Merge new bits with previous */
4539 intstatus |= newstatus;
4542 /* Handle flow-control change: read new state in case our ack
4543 * crossed another change interrupt. If change still set, assume
4544 * FC ON for safety, let next loop through do the debounce.
4546 if (intstatus & I_HMB_FC_CHANGE) {
4547 intstatus &= ~I_HMB_FC_CHANGE;
4548 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4549 R_SDREG(newstatus, ®s->intstatus, retries);
4550 bus->f1regdata += 2;
4552 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4553 intstatus |= (newstatus & bus->hostintmask);
4556 /* Handle host mailbox indication */
4557 if (intstatus & I_HMB_HOST_INT) {
4558 intstatus &= ~I_HMB_HOST_INT;
4559 intstatus |= brcmf_sdbrcm_hostmail(bus);
4562 /* Generally don't ask for these, can get CRC errors... */
4563 if (intstatus & I_WR_OOSYNC) {
4564 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4565 intstatus &= ~I_WR_OOSYNC;
4568 if (intstatus & I_RD_OOSYNC) {
4569 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4570 intstatus &= ~I_RD_OOSYNC;
4573 if (intstatus & I_SBINT) {
4574 DHD_ERROR(("Dongle reports SBINT\n"));
4575 intstatus &= ~I_SBINT;
4578 /* Would be active due to wake-wlan in gSPI */
4579 if (intstatus & I_CHIPACTIVE) {
4580 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4581 intstatus &= ~I_CHIPACTIVE;
4584 /* Ignore frame indications if rxskip is set */
4586 intstatus &= ~I_HMB_FRAME_IND;
4588 /* On frame indication, read available frames */
4589 if (PKT_AVAILABLE()) {
4590 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
4591 if (rxdone || bus->rxskip)
4592 intstatus &= ~I_HMB_FRAME_IND;
4593 rxlimit -= min(framecnt, rxlimit);
4596 /* Keep still-pending events for next scheduling */
4597 bus->intstatus = intstatus;
4600 #if defined(OOB_INTR_ONLY)
4601 brcmf_sdio_oob_intr_set(1);
4602 #endif /* (OOB_INTR_ONLY) */
4603 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4604 * or clock availability. (Allows tx loop to check ipend if desired.)
4605 * (Unless register access seems hosed, as we may not be able to ACK...)
4607 if (bus->intr && bus->intdis && !brcmf_sdcard_regfail(sdh)) {
4608 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4609 __func__, rxdone, framecnt));
4610 bus->intdis = false;
4611 brcmf_sdcard_intr_enable(sdh);
4614 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4615 (bus->clkstate == CLK_AVAIL)) {
4618 ret = brcmf_sdbrcm_send_buf(bus, brcmf_sdcard_cur_sbwad(sdh),
4619 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
4620 (u32) bus->ctrl_frame_len, NULL, NULL, NULL);
4621 ASSERT(ret != -BCME_PENDING);
4624 /* On failure, abort the command and
4625 terminate the frame */
4626 DHD_INFO(("%s: sdio error %d, abort command and "
4627 "terminate frame.\n", __func__, ret));
4630 brcmf_sdcard_abort(sdh, SDIO_FUNC_2);
4632 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
4633 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4637 for (i = 0; i < 3; i++) {
4639 hi = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4640 SBSDIO_FUNC1_WFRAMEBCHI,
4642 lo = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4643 SBSDIO_FUNC1_WFRAMEBCLO,
4645 bus->f1regdata += 2;
4646 if ((hi == 0) && (lo == 0))
4652 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4654 DHD_INFO(("Return_dpc value is : %d\n", ret));
4655 bus->ctrl_frame_stat = false;
4656 dhd_wait_event_wakeup(bus->dhd);
4658 /* Send queued frames (limit 1 if rx may still be pending) */
4659 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4660 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4662 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4663 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
4664 txlimit -= framecnt;
4667 /* Resched if events or tx frames are pending,
4668 else await next interrupt */
4669 /* On failed register access, all bets are off:
4670 no resched or interrupts */
4671 if ((bus->dhd->busstate == DHD_BUS_DOWN) || brcmf_sdcard_regfail(sdh)) {
4672 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4673 "operation %d\n", __func__, brcmf_sdcard_regfail(sdh)));
4674 bus->dhd->busstate = DHD_BUS_DOWN;
4676 } else if (bus->clkstate == CLK_PENDING) {
4677 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4678 "I_CHIPACTIVE interrupt\n", __func__));
4680 } else if (bus->intstatus || bus->ipend ||
4681 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
4682 && DATAOK(bus)) || PKT_AVAILABLE()) {
4686 bus->dpc_sched = resched;
4688 /* If we're done for now, turn off clock request. */
4689 if ((bus->clkstate != CLK_PENDING)
4690 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4691 bus->activity = false;
4692 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4695 dhd_os_sdunlock(bus->dhd);
4700 bool dhd_bus_dpc(struct dhd_bus *bus)
4704 /* Call the DPC directly. */
4705 DHD_TRACE(("Calling brcmf_sdbrcm_dpc() from %s\n", __func__));
4706 resched = brcmf_sdbrcm_dpc(bus);
4711 void brcmf_sdbrcm_isr(void *arg)
4713 dhd_bus_t *bus = (dhd_bus_t *) arg;
4716 DHD_TRACE(("%s: Enter\n", __func__));
4719 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4724 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4725 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4729 /* Count the interrupt call */
4733 /* Shouldn't get this interrupt if we're sleeping? */
4734 if (bus->sleeping) {
4735 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4739 /* Disable additional interrupts (is this needed now)? */
4741 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4743 DHD_ERROR(("brcmf_sdbrcm_isr() w/o interrupt configured!\n"));
4745 brcmf_sdcard_intr_disable(sdh);
4748 #if defined(SDIO_ISR_THREAD)
4749 DHD_TRACE(("Calling brcmf_sdbrcm_dpc() from %s\n", __func__));
4750 while (brcmf_sdbrcm_dpc(bus))
4753 bus->dpc_sched = true;
4754 dhd_sched_dpc(bus->dhd);
4760 static void brcmf_sdbrcm_pktgen_init(dhd_bus_t *bus)
4762 /* Default to specified length, or full range */
4763 if (dhd_pktgen_len) {
4764 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4765 bus->pktgen_minlen = bus->pktgen_maxlen;
4767 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4768 bus->pktgen_minlen = 0;
4770 bus->pktgen_len = (u16) bus->pktgen_minlen;
4772 /* Default to per-watchdog burst with 10s print time */
4773 bus->pktgen_freq = 1;
4774 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4775 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4777 /* Default to echo mode */
4778 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4779 bus->pktgen_stop = 1;
4782 static void brcmf_sdbrcm_pktgen(dhd_bus_t *bus)
4784 struct sk_buff *pkt;
4790 /* Display current count if appropriate */
4791 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4792 bus->pktgen_ptick = 0;
4793 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4794 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4797 /* For recv mode, just make sure dongle has started sending */
4798 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4799 if (!bus->pktgen_rcvd)
4800 brcmf_sdbrcm_sdtest_set(bus, true);
4804 /* Otherwise, generate or request the specified number of packets */
4805 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4806 /* Stop if total has been reached */
4807 if (bus->pktgen_total
4808 && (bus->pktgen_sent >= bus->pktgen_total)) {
4809 bus->pktgen_count = 0;
4813 /* Allocate an appropriate-sized packet */
4814 len = bus->pktgen_len;
4815 pkt = brcmu_pkt_buf_get_skb(
4816 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4819 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n",
4823 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4825 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4827 /* Write test header cmd and extra based on mode */
4828 switch (bus->pktgen_mode) {
4829 case DHD_PKTGEN_ECHO:
4830 *data++ = SDPCM_TEST_ECHOREQ;
4831 *data++ = (u8) bus->pktgen_sent;
4834 case DHD_PKTGEN_SEND:
4835 *data++ = SDPCM_TEST_DISCARD;
4836 *data++ = (u8) bus->pktgen_sent;
4839 case DHD_PKTGEN_RXBURST:
4840 *data++ = SDPCM_TEST_BURST;
4841 *data++ = (u8) bus->pktgen_count;
4845 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4847 brcmu_pkt_buf_free_skb(pkt, true);
4848 bus->pktgen_count = 0;
4852 /* Write test header length field */
4853 *data++ = (len >> 0);
4854 *data++ = (len >> 8);
4856 /* Then fill in the remainder -- N/A for burst,
4858 for (fillbyte = 0; fillbyte < len; fillbyte++)
4860 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4863 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4864 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4865 printk(KERN_DEBUG "brcmf_sdbrcm_pktgen: Tx Data:\n");
4866 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4867 pkt->len - SDPCM_HDRLEN);
4872 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4874 if (bus->pktgen_stop
4875 && bus->pktgen_stop == bus->pktgen_fail)
4876 bus->pktgen_count = 0;
4880 /* Bump length if not fixed, wrap at max */
4881 if (++bus->pktgen_len > bus->pktgen_maxlen)
4882 bus->pktgen_len = (u16) bus->pktgen_minlen;
4884 /* Special case for burst mode: just send one request! */
4885 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4890 static void brcmf_sdbrcm_sdtest_set(dhd_bus_t *bus, bool start)
4892 struct sk_buff *pkt;
4895 /* Allocate the packet */
4896 pkt = brcmu_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4899 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n", __func__));
4902 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4903 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4905 /* Fill in the test header */
4906 *data++ = SDPCM_TEST_SEND;
4908 *data++ = (bus->pktgen_maxlen >> 0);
4909 *data++ = (bus->pktgen_maxlen >> 8);
4912 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4917 brcmf_sdbrcm_checkdied(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4927 /* Check for min length */
4929 if (pktlen < SDPCM_TEST_HDRLEN) {
4930 DHD_ERROR(("brcmf_sdbrcm_checkdied: toss runt frame, pktlen "
4932 brcmu_pkt_buf_free_skb(pkt, false);
4936 /* Extract header fields */
4941 len += *data++ << 8;
4943 /* Check length for relevant commands */
4944 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4945 || cmd == SDPCM_TEST_ECHORSP) {
4946 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4947 DHD_ERROR(("brcmf_sdbrcm_checkdied: frame length "
4948 "mismatch, pktlen %d seq %d" " cmd %d extra %d "
4950 pktlen, seq, cmd, extra, len));
4951 brcmu_pkt_buf_free_skb(pkt, false);
4956 /* Process as per command */
4958 case SDPCM_TEST_ECHOREQ:
4959 /* Rx->Tx turnaround ok (even on NDIS w/current
4961 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4962 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0)
4966 brcmu_pkt_buf_free_skb(pkt, false);
4971 case SDPCM_TEST_ECHORSP:
4972 if (bus->ext_loop) {
4973 brcmu_pkt_buf_free_skb(pkt, false);
4978 for (offset = 0; offset < len; offset++, data++) {
4979 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4980 DHD_ERROR(("brcmf_sdbrcm_checkdied: echo data "
4981 "mismatch: " "offset %d (len %d) "
4982 "expect 0x%02x rcvd 0x%02x\n",
4984 SDPCM_TEST_FILL(offset, extra),
4989 brcmu_pkt_buf_free_skb(pkt, false);
4993 case SDPCM_TEST_DISCARD:
4994 brcmu_pkt_buf_free_skb(pkt, false);
4998 case SDPCM_TEST_BURST:
4999 case SDPCM_TEST_SEND:
5001 DHD_INFO(("brcmf_sdbrcm_checkdied: unsupported or unknown "
5002 "command, pktlen %d seq %d" " cmd %d extra %d len %d\n",
5003 pktlen, seq, cmd, extra, len));
5004 brcmu_pkt_buf_free_skb(pkt, false);
5008 /* For recv mode, stop at limie (and tell dongle to stop sending) */
5009 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
5010 if (bus->pktgen_total
5011 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
5012 bus->pktgen_count = 0;
5013 brcmf_sdbrcm_sdtest_set(bus, false);
5019 extern bool brcmf_sdbrcm_bus_watchdog(dhd_pub_t *dhdp)
5023 DHD_TIMER(("%s: Enter\n", __func__));
5027 if (bus->dhd->dongle_reset)
5030 /* Ignore the timer if simulating bus down */
5034 dhd_os_sdlock(bus->dhd);
5036 /* Poll period: check device if appropriate. */
5037 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5040 /* Reset poll tick */
5043 /* Check device if no interrupts */
5044 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5046 if (!bus->dpc_sched) {
5048 devpend = brcmf_sdcard_cfg_read(bus->sdh,
5049 SDIO_FUNC_0, SDIO_CCCR_INTx,
5052 devpend & (INTR_STATUS_FUNC1 |
5056 /* If there is something, make like the ISR and
5062 brcmf_sdcard_intr_disable(bus->sdh);
5064 bus->dpc_sched = true;
5065 dhd_sched_dpc(bus->dhd);
5070 /* Update interrupt tracking */
5071 bus->lastintrs = bus->intrcount;
5074 /* Poll for console output periodically */
5075 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
5076 bus->console.count += dhd_watchdog_ms;
5077 if (bus->console.count >= dhd_console_ms) {
5078 bus->console.count -= dhd_console_ms;
5079 /* Make sure backplane clock is on */
5080 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5081 if (brcmf_sdbrcm_readconsole(bus) < 0)
5082 dhd_console_ms = 0; /* On error,
5086 #endif /* DHD_DEBUG */
5089 /* Generate packets if configured */
5090 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5091 /* Make sure backplane clock is on */
5092 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5093 bus->pktgen_tick = 0;
5094 brcmf_sdbrcm_pktgen(bus);
5098 /* On idle timeout clear activity flag and/or turn off clock */
5099 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5100 if (++bus->idlecount >= bus->idletime) {
5102 if (bus->activity) {
5103 bus->activity = false;
5104 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
5106 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
5111 dhd_os_sdunlock(bus->dhd);
5117 extern int brcmf_sdbrcm_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg,
5120 dhd_bus_t *bus = dhdp->bus;
5123 struct sk_buff *pkt;
5125 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5126 if (bus->console_addr == 0)
5129 /* Exclusive bus access */
5130 dhd_os_sdlock(bus->dhd);
5132 /* Don't allow input if dongle is in reset */
5133 if (bus->dhd->dongle_reset) {
5134 dhd_os_sdunlock(bus->dhd);
5138 /* Request clock to allow SDIO accesses */
5140 /* No pend allowed since txpkt is called later, ht clk has to be on */
5141 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5143 /* Zero cbuf_index */
5144 addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5145 val = cpu_to_le32(0);
5146 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5150 /* Write message into cbuf */
5151 addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5152 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)msg, msglen);
5156 /* Write length into vcons_in */
5157 addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5158 val = cpu_to_le32(msglen);
5159 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5163 /* Bump dongle by sending an empty event pkt.
5164 * sdpcm_sendup (RX) checks for virtual console input.
5166 pkt = brcmu_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5167 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5168 brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5171 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5172 bus->activity = false;
5173 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
5176 dhd_os_sdunlock(bus->dhd);
5180 #endif /* DHD_DEBUG */
5182 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
5184 if (chipid == BCM4325_CHIP_ID)
5186 if (chipid == BCM4329_CHIP_ID)
5188 if (chipid == BCM4319_CHIP_ID)
5193 static void *brcmf_sdbrcm_probe(u16 venid, u16 devid, u16 bus_no,
5194 u16 slot, u16 func, uint bustype, void *regsva,
5200 /* Init global variables at run-time, not as part of the declaration.
5201 * This is required to support init/de-init of the driver.
5203 * of globals as part of the declaration results in non-deterministic
5204 * behavior since the value of the globals may be different on the
5205 * first time that the driver is initialized vs subsequent
5208 dhd_txbound = DHD_TXBOUND;
5209 dhd_rxbound = DHD_RXBOUND;
5210 dhd_alignctl = true;
5212 dhd_readahead = true;
5214 dhd_dongle_memsize = 0;
5215 dhd_txminmax = DHD_TXMINMAX;
5221 DHD_TRACE(("%s: Enter\n", __func__));
5222 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5224 /* We make assumptions about address window mappings */
5225 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5227 /* BCMSDH passes venid and devid based on CIS parsing -- but
5229 * means early parse could fail, so here we should get either an ID
5230 * we recognize OR (-1) indicating we must request power first.
5232 /* Check the Vendor ID */
5235 case PCI_VENDOR_ID_BROADCOM:
5238 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5242 /* Check the Device ID and make sure it's one that we support */
5244 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5245 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5246 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5247 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5249 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5250 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5251 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5253 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5255 case BCM4319_D11N_ID: /* 4319 802.11n id */
5256 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5257 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5258 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5261 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5266 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5267 __func__, venid, devid));
5271 /* Allocate private bus interface state */
5272 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5274 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5278 bus->cl_devid = (u16) devid;
5280 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5281 bus->usebufpool = false; /* Use bufpool if allocated,
5282 else use locally malloced rxbuf */
5284 /* attempt to attach to the dongle */
5285 if (!(brcmf_sdbrcm_probe_attach(bus, sdh, regsva, devid))) {
5286 DHD_ERROR(("%s: brcmf_sdbrcm_probe_attach failed\n", __func__));
5290 spin_lock_init(&bus->txqlock);
5292 /* Attach to the dhd/OS/network interface */
5293 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5295 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5299 /* Allocate buffers */
5300 if (!(brcmf_sdbrcm_probe_malloc(bus, sdh))) {
5301 DHD_ERROR(("%s: brcmf_sdbrcm_probe_malloc failed\n", __func__));
5305 if (!(brcmf_sdbrcm_probe_init(bus, sdh))) {
5306 DHD_ERROR(("%s: brcmf_sdbrcm_probe_init failed\n", __func__));
5310 /* Register interrupt callback, but mask it (not operational yet). */
5311 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5313 brcmf_sdcard_intr_disable(sdh);
5314 ret = brcmf_sdcard_intr_reg(sdh, brcmf_sdbrcm_isr, bus);
5316 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5320 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5322 DHD_INFO(("%s: completed!!\n", __func__));
5324 /* if firmware path present try to download and bring up bus */
5325 ret = dhd_bus_start(bus->dhd);
5327 if (ret == -ENOLINK) {
5328 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5332 /* Ok, have the per-port tell the stack we're open for business */
5333 if (dhd_net_attach(bus->dhd, 0) != 0) {
5334 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5341 brcmf_sdbrcm_release(bus);
5346 brcmf_sdbrcm_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva,
5352 bus->alp_only = true;
5354 /* Return the window to backplane enumeration space for core access */
5355 if (brcmf_sdbrcm_set_siaddr_window(bus, SI_ENUM_BASE))
5356 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5359 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5360 brcmf_sdcard_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5362 #endif /* DHD_DEBUG */
5365 * Force PLL off until brcmf_sdbrcm_chip_attach()
5366 * programs PLL control regs
5369 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5370 DHD_INIT_CLKCTL1, &err);
5373 brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
5374 SBSDIO_FUNC1_CHIPCLKCSR, &err);
5376 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5377 DHD_ERROR(("brcmf_sdbrcm_probe: ChipClkCSR access: err %d wrote"
5378 " 0x%02x read 0x%02x\n",
5379 err, DHD_INIT_CLKCTL1, clkctl));
5383 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
5384 DHD_ERROR(("%s: brcmf_sdbrcm_chip_attach failed!\n", __func__));
5388 brcmf_sdcard_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5390 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
5391 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5392 __func__, bus->ci->chip));
5396 brcmf_sdbrcm_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5398 /* Get info on the ARM and SOCRAM cores... */
5399 if (!DHD_NOPMU(bus)) {
5400 bus->armrev = SBCOREREV(brcmf_sdcard_reg_read(bus->sdh,
5401 CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5402 bus->orig_ramsize = bus->ci->ramsize;
5403 if (!(bus->orig_ramsize)) {
5404 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5408 bus->ramsize = bus->orig_ramsize;
5409 if (dhd_dongle_memsize)
5410 brcmf_sdbrcm_setmemsize(bus, dhd_dongle_memsize);
5412 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5413 bus->ramsize, bus->orig_ramsize));
5416 bus->regs = (void *)bus->ci->buscorebase;
5418 /* Set core control so an SDIO reset does a backplane reset */
5419 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5421 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5423 /* Locate an appropriately-aligned portion of hdrbuf */
5424 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5426 /* Set the poll and/or interrupt flags */
5427 bus->intr = (bool) dhd_intr;
5428 bus->poll = (bool) dhd_poll;
5438 static bool brcmf_sdbrcm_probe_malloc(dhd_bus_t *bus, void *sdh)
5440 DHD_TRACE(("%s: Enter\n", __func__));
5442 if (bus->dhd->maxctl) {
5444 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5445 ALIGNMENT) + DHD_SDALIGN;
5446 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5447 if (!(bus->rxbuf)) {
5448 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5449 __func__, bus->rxblen));
5454 /* Allocate buffer to receive glomed packet */
5455 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5456 if (!(bus->databuf)) {
5457 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5458 __func__, MAX_DATA_BUF));
5459 /* release rxbuf which was already located as above */
5465 /* Align the buffer */
5466 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5468 bus->databuf + (DHD_SDALIGN -
5469 ((unsigned long)bus->databuf % DHD_SDALIGN));
5471 bus->dataptr = bus->databuf;
5479 static bool brcmf_sdbrcm_probe_init(dhd_bus_t *bus, void *sdh)
5483 DHD_TRACE(("%s: Enter\n", __func__));
5486 brcmf_sdbrcm_pktgen_init(bus);
5489 /* Disable F2 to clear any intermediate frame state on the dongle */
5490 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
5491 SDIO_FUNC_ENABLE_1, NULL);
5493 bus->dhd->busstate = DHD_BUS_DOWN;
5494 bus->sleeping = false;
5495 bus->rxflow = false;
5496 bus->prev_rxlim_hit = 0;
5498 /* Done with backplane-dependent accesses, can drop clock... */
5499 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
5502 /* ...and initialize clock/power states */
5503 bus->clkstate = CLK_SDONLY;
5504 bus->idletime = (s32) dhd_idletime;
5505 bus->idleclock = DHD_IDLE_ACTIVE;
5507 /* Query the F2 block size, set roundup accordingly */
5509 if (brcmf_sdcard_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5510 &bus->blocksize, sizeof(s32), false) != 0) {
5512 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5514 DHD_INFO(("%s: Initial value for %s is %d\n",
5515 __func__, "sd_blocksize", bus->blocksize));
5517 bus->roundup = min(max_roundup, bus->blocksize);
5519 /* Query if bus module supports packet chaining,
5520 default to use if supported */
5521 if (brcmf_sdcard_iovar_op(sdh, "sd_rxchain", NULL, 0,
5522 &bus->sd_rxchain, sizeof(s32),
5524 bus->sd_rxchain = false;
5526 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5528 (bus->sd_rxchain ? "supports" : "does not support")));
5530 bus->use_rxchain = (bool) bus->sd_rxchain;
5536 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5539 bus->fw_path = fw_path;
5540 bus->nv_path = nv_path;
5542 ret = brcmf_sdbrcm_download_firmware(bus, bus->sdh);
5548 brcmf_sdbrcm_download_firmware(struct dhd_bus *bus, void *sdh)
5552 /* Download the firmware */
5553 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5555 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
5557 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
5562 /* Detach and free everything */
5563 static void brcmf_sdbrcm_release(dhd_bus_t *bus)
5565 DHD_TRACE(("%s: Enter\n", __func__));
5568 /* De-register interrupt handler */
5569 brcmf_sdcard_intr_disable(bus->sdh);
5570 brcmf_sdcard_intr_dereg(bus->sdh);
5573 dhd_detach(bus->dhd);
5574 brcmf_sdbrcm_release_dongle(bus);
5578 brcmf_sdbrcm_release_malloc(bus);
5583 DHD_TRACE(("%s: Disconnected\n", __func__));
5586 static void brcmf_sdbrcm_release_malloc(dhd_bus_t *bus)
5588 DHD_TRACE(("%s: Enter\n", __func__));
5590 if (bus->dhd && bus->dhd->dongle_reset)
5594 bus->rxctl = bus->rxbuf = NULL;
5597 kfree(bus->databuf);
5598 bus->databuf = NULL;
5601 static void brcmf_sdbrcm_release_dongle(dhd_bus_t *bus)
5603 DHD_TRACE(("%s: Enter\n", __func__));
5605 if (bus->dhd && bus->dhd->dongle_reset)
5609 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5610 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
5611 brcmf_sdbrcm_chip_detach(bus);
5612 if (bus->vars && bus->varsz)
5617 DHD_TRACE(("%s: Disconnected\n", __func__));
5620 static void brcmf_sdbrcm_disconnect(void *ptr)
5622 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5624 DHD_TRACE(("%s: Enter\n", __func__));
5628 brcmf_sdbrcm_release(bus);
5631 DHD_TRACE(("%s: Disconnected\n", __func__));
5634 /* Register/Unregister functions are called by the main DHD entry
5635 * point (e.g. module insertion) to link with the bus driver, in
5636 * order to look for or await the device.
5639 static bcmsdh_driver_t dhd_sdio = {
5641 brcmf_sdbrcm_disconnect
5644 int dhd_bus_register(void)
5646 DHD_TRACE(("%s: Enter\n", __func__));
5648 return brcmf_sdio_register(&dhd_sdio);
5651 void dhd_bus_unregister(void)
5653 DHD_TRACE(("%s: Enter\n", __func__));
5655 brcmf_sdio_unregister();
5658 static int brcmf_sdbrcm_download_code_file(struct dhd_bus *bus, char *fw_path)
5664 u8 *memblock = NULL, *memptr;
5666 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5668 image = dhd_os_open_image(fw_path);
5672 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5673 if (memblock == NULL) {
5674 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5675 __func__, MEMBLOCK));
5678 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5680 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5682 /* Download image */
5684 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5685 bcmerror = brcmf_sdbrcm_membytes(bus, true, offset, memptr,
5688 DHD_ERROR(("%s: error %d on writing %d membytes at "
5689 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5700 dhd_os_close_image(image);
5706 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5707 * and ending in a NUL.
5708 * Removes carriage returns, empty lines, comment lines, and converts
5710 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5714 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
5723 findNewline = false;
5726 for (n = 0; n < len; n++) {
5729 if (varbuf[n] == '\r')
5731 if (findNewline && varbuf[n] != '\n')
5733 findNewline = false;
5734 if (varbuf[n] == '#') {
5738 if (varbuf[n] == '\n') {
5748 buf_len = dp - varbuf;
5750 while (dp < varbuf + n)
5757 EXAMPLE: nvram_array
5760 Use carriage return at the end of each assignment,
5761 and an empty string with
5762 carriage return at the end of array.
5765 unsigned char nvram_array[] = {"name1=value1\n",
5766 "name2=value2\n", "\n"};
5767 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5769 Search "EXAMPLE: nvram_array" to see how the array is activated.
5772 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5774 bus->nvram_params = nvram_params;
5777 static int brcmf_sdbrcm_download_nvram(struct dhd_bus *bus)
5782 char *memblock = NULL;
5785 bool nvram_file_exists;
5787 nv_path = bus->nv_path;
5789 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5790 if (!nvram_file_exists && (bus->nvram_params == NULL))
5793 if (nvram_file_exists) {
5794 image = dhd_os_open_image(nv_path);
5799 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5800 if (memblock == NULL) {
5801 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5802 __func__, MEMBLOCK));
5806 /* Download variables */
5807 if (nvram_file_exists) {
5808 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5810 len = strlen(bus->nvram_params);
5811 ASSERT(len <= MEMBLOCK);
5814 memcpy(memblock, bus->nvram_params, len);
5817 if (len > 0 && len < MEMBLOCK) {
5818 bufp = (char *)memblock;
5820 len = brcmf_process_nvram_vars(bufp, len);
5824 bcmerror = brcmf_sdbrcm_downloadvars(bus, memblock,
5827 DHD_ERROR(("%s: error downloading vars: %d\n",
5828 __func__, bcmerror));
5831 DHD_ERROR(("%s: error reading nvram file: %d\n",
5840 dhd_os_close_image(image);
5845 static int _brcmf_sdbrcm_download_firmware(struct dhd_bus *bus)
5849 bool embed = false; /* download embedded firmware */
5850 bool dlok = false; /* download firmware succeeded */
5852 /* Out immediately if no image to download */
5853 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0'))
5856 /* Keep arm in reset */
5857 if (brcmf_sdbrcm_download_state(bus, true)) {
5858 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5862 /* External image takes precedence if specified */
5863 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5864 if (brcmf_sdbrcm_download_code_file(bus, bus->fw_path)) {
5865 DHD_ERROR(("%s: dongle image file download failed\n",
5874 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5878 /* EXAMPLE: nvram_array */
5879 /* If a valid nvram_arry is specified as above, it can be passed
5881 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5883 /* External nvram takes precedence if specified */
5884 if (brcmf_sdbrcm_download_nvram(bus)) {
5885 DHD_ERROR(("%s: dongle nvram file download failed\n",
5889 /* Take arm out of reset */
5890 if (brcmf_sdbrcm_download_state(bus, false)) {
5891 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5904 brcmf_sdbrcm_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5905 u8 *buf, uint nbytes, struct sk_buff *pkt,
5906 bcmsdh_cmplt_fn_t complete, void *handle)
5908 return brcmf_sdcard_send_buf
5909 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5913 uint dhd_bus_chip(struct dhd_bus *bus)
5915 ASSERT(bus->ci != NULL);
5916 return bus->ci->chip;
5919 void *dhd_bus_pub(struct dhd_bus *bus)
5924 void *dhd_bus_txq(struct dhd_bus *bus)
5929 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5931 return SDPCM_HDRLEN;
5934 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5942 if (!bus->dhd->dongle_reset) {
5943 /* Expect app to have torn down any
5944 connection before calling */
5945 /* Stop the bus, disable F2 */
5946 brcmf_sdbrcm_bus_stop(bus, false);
5948 /* Clean tx/rx buffer pointers,
5949 detach from the dongle */
5950 brcmf_sdbrcm_release_dongle(bus);
5952 bus->dhd->dongle_reset = true;
5953 bus->dhd->up = false;
5955 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
5956 /* App can now remove power from device */
5960 /* App must have restored power to device before calling */
5962 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
5964 if (bus->dhd->dongle_reset) {
5966 /* Reset SD client */
5967 brcmf_sdcard_reset(bus->sdh);
5969 /* Attempt to re-attach & download */
5970 if (brcmf_sdbrcm_probe_attach(bus, bus->sdh,
5971 (u32 *) SI_ENUM_BASE,
5973 /* Attempt to download binary to the dongle */
5974 if (brcmf_sdbrcm_probe_init
5976 && brcmf_sdbrcm_download_firmware(bus,
5979 /* Re-init bus, enable F2 transfer */
5980 brcmf_sdbrcm_bus_init(
5981 (dhd_pub_t *) bus->dhd, false);
5983 #if defined(OOB_INTR_ONLY)
5984 brcmf_sdbrcm_enable_oob_intr(bus, true);
5985 #endif /* defined(OOB_INTR_ONLY) */
5987 bus->dhd->dongle_reset = false;
5988 bus->dhd->up = true;
5990 DHD_TRACE(("%s: WLAN ON DONE\n",
5997 bcmerror = -EISCONN;
5998 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
5999 "is on\n", __func__));
6007 brcmf_sdbrcm_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci,
6014 * Chipid is assume to be at offset 0 from regs arg
6015 * For different chiptypes or old sdio hosts w/o chipcommon,
6016 * other ways of recognition should be added here.
6018 ci->cccorebase = (u32)regs;
6019 regdata = brcmf_sdcard_reg_read(sdh,
6020 CORE_CC_REG(ci->cccorebase, chipid), 4);
6021 ci->chip = regdata & CID_ID_MASK;
6022 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
6024 DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
6025 __func__, ci->chip, ci->chiprev));
6027 /* Address of cores for new chips should be added here */
6029 case BCM4329_CHIP_ID:
6030 ci->buscorebase = BCM4329_CORE_BUS_BASE;
6031 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
6032 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6033 ci->ramsize = BCM4329_RAMSIZE;
6036 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6037 __func__, ci->chip));
6041 regdata = brcmf_sdcard_reg_read(sdh,
6042 CORE_SB(ci->cccorebase, sbidhigh), 4);
6043 ci->ccrev = SBCOREREV(regdata);
6045 regdata = brcmf_sdcard_reg_read(sdh,
6046 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6047 ci->pmurev = regdata & PCAP_REV_MASK;
6049 regdata = brcmf_sdcard_reg_read(sdh,
6050 CORE_SB(ci->buscorebase, sbidhigh), 4);
6051 ci->buscorerev = SBCOREREV(regdata);
6052 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6054 DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6055 __func__, ci->ccrev, ci->pmurev,
6056 ci->buscorerev, ci->buscoretype));
6058 /* get chipcommon capabilites */
6059 ci->cccaps = brcmf_sdcard_reg_read(sdh,
6060 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6066 brcmf_sdbrcm_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
6070 regdata = brcmf_sdcard_reg_read(sdh,
6071 CORE_SB(corebase, sbtmstatelow), 4);
6072 if (regdata & SBTML_RESET)
6075 regdata = brcmf_sdcard_reg_read(sdh,
6076 CORE_SB(corebase, sbtmstatelow), 4);
6077 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6079 * set target reject and spin until busy is clear
6080 * (preserve core-specific bits)
6082 regdata = brcmf_sdcard_reg_read(sdh,
6083 CORE_SB(corebase, sbtmstatelow), 4);
6084 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6085 regdata | SBTML_REJ);
6087 regdata = brcmf_sdcard_reg_read(sdh,
6088 CORE_SB(corebase, sbtmstatelow), 4);
6090 SPINWAIT((brcmf_sdcard_reg_read(sdh,
6091 CORE_SB(corebase, sbtmstatehigh), 4) &
6092 SBTMH_BUSY), 100000);
6094 regdata = brcmf_sdcard_reg_read(sdh,
6095 CORE_SB(corebase, sbtmstatehigh), 4);
6096 if (regdata & SBTMH_BUSY)
6097 DHD_ERROR(("%s: ARM core still busy\n", __func__));
6099 regdata = brcmf_sdcard_reg_read(sdh,
6100 CORE_SB(corebase, sbidlow), 4);
6101 if (regdata & SBIDL_INIT) {
6102 regdata = brcmf_sdcard_reg_read(sdh,
6103 CORE_SB(corebase, sbimstate), 4) |
6105 brcmf_sdcard_reg_write(sdh,
6106 CORE_SB(corebase, sbimstate), 4,
6108 regdata = brcmf_sdcard_reg_read(sdh,
6109 CORE_SB(corebase, sbimstate), 4);
6111 SPINWAIT((brcmf_sdcard_reg_read(sdh,
6112 CORE_SB(corebase, sbimstate), 4) &
6116 /* set reset and reject while enabling the clocks */
6117 brcmf_sdcard_reg_write(sdh,
6118 CORE_SB(corebase, sbtmstatelow), 4,
6119 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6120 SBTML_REJ | SBTML_RESET));
6121 regdata = brcmf_sdcard_reg_read(sdh,
6122 CORE_SB(corebase, sbtmstatelow), 4);
6125 /* clear the initiator reject bit */
6126 regdata = brcmf_sdcard_reg_read(sdh,
6127 CORE_SB(corebase, sbidlow), 4);
6128 if (regdata & SBIDL_INIT) {
6129 regdata = brcmf_sdcard_reg_read(sdh,
6130 CORE_SB(corebase, sbimstate), 4) &
6132 brcmf_sdcard_reg_write(sdh,
6133 CORE_SB(corebase, sbimstate), 4,
6138 /* leave reset and reject asserted */
6139 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6140 (SBTML_REJ | SBTML_RESET));
6145 brcmf_sdbrcm_chip_attach(struct dhd_bus *bus, void *regs)
6147 struct chip_info *ci;
6151 DHD_TRACE(("%s: Enter\n", __func__));
6153 /* alloc chip_info_t */
6154 ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6156 DHD_ERROR(("%s: malloc failed!\n", __func__));
6160 memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6162 /* bus/core/clk setup for register access */
6163 /* Try forcing SDIO core to do ALPAvail request only */
6164 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6165 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6168 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6172 /* If register supported, wait for ALPAvail and then force ALP */
6173 /* This may take up to 15 milliseconds */
6174 clkval = brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
6175 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6176 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6178 brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
6179 SBSDIO_FUNC1_CHIPCLKCSR,
6181 !SBSDIO_ALPAV(clkval)),
6182 PMU_MAX_TRANSITION_DLY);
6183 if (!SBSDIO_ALPAV(clkval)) {
6184 DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6189 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6191 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
6192 SBSDIO_FUNC1_CHIPCLKCSR,
6196 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6197 __func__, clkset, clkval));
6202 /* Also, disable the extra SDIO pull-ups */
6203 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP,
6206 err = brcmf_sdbrcm_chip_recognition(bus->sdh, ci, regs);
6211 * Make sure any on-chip ARM is off (in case strapping is wrong),
6212 * or downloaded code was already running.
6214 brcmf_sdbrcm_chip_disablecore(bus->sdh, ci->armcorebase);
6216 brcmf_sdcard_reg_write(bus->sdh,
6217 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6218 brcmf_sdcard_reg_write(bus->sdh,
6219 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6221 /* Disable F2 to clear any intermediate frame state on the dongle */
6222 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
6223 SDIO_FUNC_ENABLE_1, NULL);
6225 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6226 clkval = brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
6229 /* Done with backplane-dependent accesses, can drop clock... */
6230 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6242 brcmf_sdbrcm_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
6247 * Must do the disable sequence first to work for
6248 * arbitrary current core state.
6250 brcmf_sdbrcm_chip_disablecore(sdh, corebase);
6253 * Now do the initialization sequence.
6254 * set reset while enabling the clock and
6255 * forcing them on throughout the core
6257 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6258 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6262 regdata = brcmf_sdcard_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh),
6264 if (regdata & SBTMH_SERR)
6265 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh),
6268 regdata = brcmf_sdcard_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6269 if (regdata & (SBIM_IBE | SBIM_TO))
6270 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6271 regdata & ~(SBIM_IBE | SBIM_TO));
6273 /* clear reset and allow it to propagate throughout the core */
6274 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6275 (SICF_FGC << SBTML_SICF_SHIFT) |
6276 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6279 /* leave clock enabled */
6280 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6281 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6285 /* SDIO Pad drive strength to select value mappings */
6286 struct sdiod_drive_str {
6287 u8 strength; /* Pad Drive Strength in mA */
6288 u8 sel; /* Chip-specific select value */
6291 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6292 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6300 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6301 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6312 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6313 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6325 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
6328 brcmf_sdbrcm_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6329 struct sdiod_drive_str *str_tab = NULL;
6334 if (!(bus->ci->cccaps & CC_CAP_PMU))
6337 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6338 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6339 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6340 str_mask = 0x30000000;
6343 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6344 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6345 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6346 str_mask = 0x00003800;
6349 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6350 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6351 str_mask = 0x00003800;
6355 DHD_ERROR(("No SDIO Drive strength init"
6356 "done for chip %s rev %d pmurev %d\n",
6357 brcmu_chipname(bus->ci->chip, chn, 8),
6358 bus->ci->chiprev, bus->ci->pmurev));
6362 if (str_tab != NULL) {
6363 u32 drivestrength_sel = 0;
6367 for (i = 0; str_tab[i].strength != 0; i++) {
6368 if (drivestrength >= str_tab[i].strength) {
6369 drivestrength_sel = str_tab[i].sel;
6374 brcmf_sdcard_reg_write(bus->sdh,
6375 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6377 cc_data_temp = brcmf_sdcard_reg_read(bus->sdh,
6378 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6379 cc_data_temp &= ~str_mask;
6380 drivestrength_sel <<= str_shift;
6381 cc_data_temp |= drivestrength_sel;
6382 brcmf_sdcard_reg_write(bus->sdh,
6383 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6386 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6387 drivestrength, cc_data_temp));
6392 brcmf_sdbrcm_chip_detach(struct dhd_bus *bus)
6394 DHD_TRACE(("%s: Enter\n", __func__));