2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _sbsdpcmdev_h_
18 #define _sbsdpcmdev_h_
21 typedef volatile struct {
22 u32 corecontrol; /* CoreControl, 0x000, rev8 */
23 u32 corestatus; /* CoreStatus, 0x004, rev8 */
25 u32 biststatus; /* BistStatus, 0x00c, rev8 */
28 u16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */
30 u16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */
32 u16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */
34 u16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */
38 u32 intstatus; /* IntStatus, 0x020, rev8 */
39 u32 hostintmask; /* IntHostMask, 0x024, rev8 */
40 u32 intmask; /* IntSbMask, 0x028, rev8 */
41 u32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */
42 u32 sbintmask; /* SBIntMask, 0x030, rev8 */
43 u32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */
45 u32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */
46 u32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */
47 u32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */
48 u32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */
50 /* synchronized access to registers in SDIO clock domain */
51 u32 sdioaccess; /* SdioAccess, 0x050, rev8 */
54 /* PCMCIA frame control */
55 u8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */
57 u8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */
60 /* interrupt batching control */
61 u32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */
65 u32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
66 u32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
67 u32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
68 u32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
69 u32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */
70 u32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
71 u32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
72 u32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
73 u32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
74 u32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
75 u32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
76 u32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
78 u32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */
80 u32 PAD[128]; /* DMA engines */
82 /* SDIO/PCMCIA CIS region */
83 char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */
85 /* PCMCIA function control registers */
86 char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */
89 /* PCMCIA backplane access */
90 u16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */
91 u16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */
92 u16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */
93 u16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */
94 u16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */
95 u16 backplanedata0; /* BackplaneData0, 0x778, rev6 */
96 u16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */
97 u16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */
98 u16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */
101 /* sprom "size" & "blank" info */
102 u16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */
105 /* Sonics SiliconBackplane registers */
106 u16 PAD[0x80]; /* SbConfig Regs, 0xf00-0xfff, rev8 */
110 #define CC_CISRDY (1 << 0) /* CIS Ready */
111 #define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */
112 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
113 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */
114 #define CC_XMTDATAAVAIL_MODE (1 << 4) /* data avail generates an interrupt */
115 #define CC_XMTDATAAVAIL_CTRL (1 << 5) /* data avail interrupt ctrl */
118 #define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
119 #define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */
120 #define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */
122 #define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */
123 #define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */
124 #define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */
125 #define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */
128 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
129 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
130 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
131 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
132 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
133 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
134 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
135 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
136 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
137 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
138 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
139 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
140 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
141 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
142 #define I_PC (1 << 10) /* descriptor error */
143 #define I_PD (1 << 11) /* data error */
144 #define I_DE (1 << 12) /* Descriptor protocol Error */
145 #define I_RU (1 << 13) /* Receive descriptor Underflow */
146 #define I_RO (1 << 14) /* Receive fifo Overflow */
147 #define I_XU (1 << 15) /* Transmit fifo Underflow */
148 #define I_RI (1 << 16) /* Receive Interrupt */
149 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
150 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
151 #define I_XI (1 << 24) /* Transmit Interrupt */
152 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
153 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
154 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
155 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
156 #define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */
157 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
158 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
159 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */
160 #define I_DMA (I_RI | I_XI | I_ERRORS)
163 #define I_SB_SERR (1 << 8) /* Backplane SError (write) */
164 #define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */
165 #define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */
168 #define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */
169 #define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */
170 #define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */
171 #define SDA_WRITE 0x01000000 /* Write bit */
172 #define SDA_READ 0x00000000 /* Write bit cleared for Read */
173 #define SDA_BUSY 0x80000000 /* Busy bit */
175 /* sdioaccess-accessible register address spaces */
176 #define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */
177 #define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */
178 #define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */
179 #define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */
181 /* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
182 #define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */
183 #define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */
184 #define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */
185 #define SDA_DEVICECONTROL 0x009 /* DeviceControl */
186 #define SDA_SBADDRLOW 0x00a /* SbAddrLow */
187 #define SDA_SBADDRMID 0x00b /* SbAddrMid */
188 #define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */
189 #define SDA_FRAMECTRL 0x00d /* FrameCtrl */
190 #define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */
191 #define SDA_SDIOPULLUP 0x00f /* SdioPullUp */
192 #define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */
193 #define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */
194 #define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */
195 #define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */
197 /* SDA_F2WATERMARK */
198 #define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */
201 #define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */
204 #define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */
207 #define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */
210 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
211 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
212 #define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */
213 #define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */
215 /* pcmciaframectrl */
216 #define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */
217 #define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */
220 #define IRL_TO_MASK 0x00ffffff /* timeout */
221 #define IRL_FC_MASK 0xff000000 /* frame count */
222 #define IRL_FC_SHIFT 24 /* frame count */
225 typedef volatile struct {
230 /* rx header flags */
231 #define RXF_CRC 0x0001 /* CRC error detected */
232 #define RXF_WOOS 0x0002 /* write frame out of sync */
233 #define RXF_WF_TERM 0x0004 /* write frame terminated */
234 #define RXF_ABORT 0x0008 /* write frame aborted */
235 #define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */
238 #define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */
240 #endif /* _sbsdpcmdev_h_ */