2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/delay.h>
18 #include <linux/kernel.h>
19 #include <linux/string.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
29 /* ********** from siutils.c *********** */
36 #define SCC_SS_MASK 0x00000007 /* slow clock source mask */
37 #define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
38 #define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
39 #define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
40 #define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
41 #define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
44 #define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
45 * 0: power logic control
47 #define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
48 * PLL clock disable requests from core
50 #define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
51 * disable crystal when appropriate
53 #define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
54 #define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
55 #define SCC_CD_SHIFT 16
58 #define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
59 #define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
60 #define SYCC_FP 0x00000004 /* ForcePLLOn */
61 #define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
62 #define SYCC_HR 0x00000010 /* Force HT */
63 #define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
64 #define SYCC_CD_SHIFT 16
66 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003
67 #define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
68 #define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
69 #define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */
70 #define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
71 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004
72 #define CST4329_SPI_SDIO_MODE_SHIFT 2
74 /* 43224 chip-specific ChipControl register bits */
75 #define CCTRL43224_GPIO_TOGGLE 0x8000
76 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
77 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
79 /* 43236 Chip specific ChipStatus register bits */
80 #define CST43236_SFLASH_MASK 0x00000040
81 #define CST43236_OTP_MASK 0x00000080
82 #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
83 #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
84 #define CST43236_BOOT_MASK 0x00001800
85 #define CST43236_BOOT_SHIFT 11
86 #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
87 #define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
88 #define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
89 #define CST43236_BOOT_FROM_INVALID 3
91 /* 4331 chip-specific ChipControl register bits */
92 #define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */
93 #define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
94 #define CCTRL4331_EXT_LNA (1<<2) /* 0 disable */
95 #define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */
96 #define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */
97 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */
98 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */
99 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */
100 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */
101 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */
102 #define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */
103 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */
104 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */
105 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */
107 /* 4331 Chip specific ChipStatus register bits */
108 #define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */
109 #define CST4331_SPROM_PRESENT 0x00000002
110 #define CST4331_OTP_PRESENT 0x00000004
111 #define CST4331_LDO_RF 0x00000008
112 #define CST4331_LDO_PAR 0x00000010
114 /* 4319 chip-specific ChipStatus register bits */
115 #define CST4319_SPI_CPULESSUSB 0x00000001
116 #define CST4319_SPI_CLK_POL 0x00000002
117 #define CST4319_SPI_CLK_PH 0x00000008
118 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */
119 #define CST4319_SPROM_OTP_SEL_SHIFT 6
120 #define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */
121 #define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */
122 #define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */
123 #define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */
124 #define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */
125 #define CST4319_REMAP_SEL_MASK 0x00000600
126 #define CST4319_ILPDIV_EN 0x00000800
127 #define CST4319_XTAL_PD_POL 0x00001000
128 #define CST4319_LPO_SEL 0x00002000
129 #define CST4319_RES_INIT_MODE 0x0000c000
130 #define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */
131 #define CST4319_CBUCK_MODE_MASK 0x00060000
132 #define CST4319_CBUCK_MODE_BURST 0x00020000
133 #define CST4319_CBUCK_MODE_LPBURST 0x00060000
134 #define CST4319_RCAL_VALID 0x01000000
135 #define CST4319_RCAL_VALUE_MASK 0x3e000000
136 #define CST4319_RCAL_VALUE_SHIFT 25
138 /* 4336 chip-specific ChipStatus register bits */
139 #define CST4336_SPI_MODE_MASK 0x00000001
140 #define CST4336_SPROM_PRESENT 0x00000002
141 #define CST4336_OTP_PRESENT 0x00000004
142 #define CST4336_ARMREMAP_0 0x00000008
143 #define CST4336_ILPDIV_EN_MASK 0x00000010
144 #define CST4336_ILPDIV_EN_SHIFT 4
145 #define CST4336_XTAL_PD_POL_MASK 0x00000020
146 #define CST4336_XTAL_PD_POL_SHIFT 5
147 #define CST4336_LPO_SEL_MASK 0x00000040
148 #define CST4336_LPO_SEL_SHIFT 6
149 #define CST4336_RES_INIT_MODE_MASK 0x00000180
150 #define CST4336_RES_INIT_MODE_SHIFT 7
151 #define CST4336_CBUCK_MODE_MASK 0x00000600
152 #define CST4336_CBUCK_MODE_SHIFT 9
154 /* 4313 chip-specific ChipStatus register bits */
155 #define CST4313_SPROM_PRESENT 1
156 #define CST4313_OTP_PRESENT 2
157 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002
158 #define CST4313_SPROM_OTP_SEL_SHIFT 0
160 /* 4313 Chip specific ChipControl register bits */
161 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
163 #define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \
164 (sih->chiprev == 0) && \
165 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
170 get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
173 uint inv = 0, nom = 0;
176 ent = R_REG(*eromptr);
182 if ((ent & ER_VALID) == 0) {
187 if (ent == (ER_END | ER_VALID))
190 if ((ent & mask) == match)
196 SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
198 SI_VMSG((" after %d invalid and %d non-matching entries\n",
205 get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
206 u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
210 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
211 if (((asd & ER_TAG1) != ER_ADD) ||
212 (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
213 ((asd & AD_ST_MASK) != st)) {
214 /* This is not what we want, "push" it back */
218 *addrl = asd & AD_ADDR_MASK;
220 *addrh = get_erom_ent(sih, eromptr, 0, 0);
224 sz = asd & AD_SZ_MASK;
225 if (sz == AD_SZ_SZD) {
226 szd = get_erom_ent(sih, eromptr, 0, 0);
227 *sizel = szd & SD_SZ_MASK;
229 *sizeh = get_erom_ent(sih, eromptr, 0, 0);
231 *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
233 SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
234 sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
239 static void ai_hwfixup(si_info_t *sii)
243 /* parse the enumeration rom to identify all cores */
244 void ai_scan(si_t *sih, void *regs, uint devid)
246 si_info_t *sii = SI_INFO(sih);
247 chipcregs_t *cc = (chipcregs_t *) regs;
248 u32 erombase, *eromptr, *eromlim;
250 erombase = R_REG(&cc->eromptr);
252 switch (sih->bustype) {
254 eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
258 /* Set wrappers address */
259 sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);
261 /* Now point the window at the erom */
262 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, erombase);
268 eromptr = (u32 *)(unsigned long)erombase;
272 SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
276 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
278 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
279 while (eromptr < eromlim) {
280 u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
281 u32 mpd, asd, addrl, addrh, sizel, sizeh;
288 /* Grok a component */
289 cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
290 if (cia == (ER_END | ER_VALID)) {
291 SI_VMSG(("Found END of erom after %d cores\n",
297 cib = get_erom_ent(sih, &eromptr, 0, 0);
299 if ((cib & ER_TAG) != ER_CI) {
300 SI_ERROR(("CIA not followed by CIB\n"));
304 cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
305 mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
306 crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
307 nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
308 nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
309 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
310 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
312 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));
314 if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
316 if ((nmw + nsw == 0)) {
317 /* A component which is not a core */
318 if (cid == OOB_ROUTER_CORE_ID) {
319 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
320 &addrl, &addrh, &sizel, &sizeh);
322 sii->oob_router = addrl;
329 /* sii->eromptr[idx] = base; */
332 sii->coreid[idx] = cid;
334 for (i = 0; i < nmp; i++) {
335 mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
336 if ((mpd & ER_TAG) != ER_MP) {
337 SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
340 SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
341 (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
342 (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
345 /* First Slave Address Descriptor should be port 0:
346 * the main register space for the core
349 get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
352 /* Try again to see if it is a bridge */
354 get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
355 &addrh, &sizel, &sizeh);
358 else if ((addrh != 0) || (sizeh != 0)
359 || (sizel != SI_CORE_SIZE)) {
360 SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
364 sii->coresba[idx] = addrl;
365 sii->coresba_size[idx] = sizel;
366 /* Get any more ASDs in port 0 */
370 get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
371 &addrh, &sizel, &sizeh);
372 if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
373 sii->coresba2[idx] = addrl;
374 sii->coresba2_size[idx] = sizel;
379 /* Go through the ASDs for other slave ports */
380 for (i = 1; i < nsp; i++) {
384 get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
385 &addrl, &addrh, &sizel, &sizeh);
388 SI_ERROR((" SP %d has no address descriptors\n",
394 /* Now get master wrappers */
395 for (i = 0; i < nmw; i++) {
397 get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
398 &addrh, &sizel, &sizeh);
400 SI_ERROR(("Missing descriptor for MW %d\n", i));
403 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
404 SI_ERROR(("Master wrapper %d is not 4KB\n", i));
408 sii->wrapba[idx] = addrl;
411 /* And finally slave wrappers */
412 for (i = 0; i < nsw; i++) {
413 uint fwp = (nsp == 1) ? 0 : 1;
415 get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
416 &addrl, &addrh, &sizel, &sizeh);
418 SI_ERROR(("Missing descriptor for SW %d\n", i));
421 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
422 SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
425 if ((nmw == 0) && (i == 0))
426 sii->wrapba[idx] = addrl;
429 /* Don't record bridges */
437 SI_ERROR(("Reached end of erom without finding END"));
444 /* This function changes the logical "focus" to the indicated core.
445 * Return the current core's virtual address.
447 void *ai_setcoreidx(si_t *sih, uint coreidx)
449 si_info_t *sii = SI_INFO(sih);
450 u32 addr = sii->coresba[coreidx];
451 u32 wrap = sii->wrapba[coreidx];
454 if (coreidx >= sii->numcores)
457 switch (sih->bustype) {
460 if (!sii->regs[coreidx]) {
461 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
463 sii->curmap = regs = sii->regs[coreidx];
464 if (!sii->wrappers[coreidx]) {
465 sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
467 sii->curwrap = sii->wrappers[coreidx];
471 /* point bar0 window */
472 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, addr);
474 /* point bar0 2nd 4KB window */
475 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN2, wrap);
480 sii->curmap = regs = (void *)(unsigned long)addr;
481 sii->curwrap = (void *)(unsigned long)wrap;
490 sii->curidx = coreidx;
495 /* Return the number of address spaces in current core */
496 int ai_numaddrspaces(si_t *sih)
501 /* Return the address of the nth address space in the current core */
502 u32 ai_addrspace(si_t *sih, uint asidx)
511 return sii->coresba[cidx];
513 return sii->coresba2[cidx];
515 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
520 /* Return the size of the nth address space in the current core */
521 u32 ai_addrspacesize(si_t *sih, uint asidx)
530 return sii->coresba_size[cidx];
532 return sii->coresba2_size[cidx];
534 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
539 uint ai_flag(si_t *sih)
545 if (BCM47162_DMP()) {
546 SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
551 return R_REG(&ai->oobselouta30) & 0x1f;
554 void ai_setint(si_t *sih, int siflag)
558 uint ai_corevendor(si_t *sih)
564 cia = sii->cia[sii->curidx];
565 return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
568 uint ai_corerev(si_t *sih)
574 cib = sii->cib[sii->curidx];
575 return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
578 bool ai_iscoreup(si_t *sih)
586 return (((R_REG(&ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
588 && ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0));
591 void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
599 if (BCM47162_DMP()) {
600 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
608 w = ((R_REG(&ai->ioctrl) & ~mask) | val);
609 W_REG(&ai->ioctrl, w);
613 u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
620 if (BCM47162_DMP()) {
621 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
629 w = ((R_REG(&ai->ioctrl) & ~mask) | val);
630 W_REG(&ai->ioctrl, w);
633 return R_REG(&ai->ioctrl);
636 u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
643 if (BCM47162_DMP()) {
644 SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
651 w = ((R_REG(&ai->iostatus) & ~mask) | val);
652 W_REG(&ai->iostatus, w);
655 return R_REG(&ai->iostatus);
658 /* *************** from siutils.c ************** */
659 /* local prototypes */
660 static si_info_t *ai_doattach(si_info_t *sii, uint devid, void *regs,
661 uint bustype, void *sdh, char **vars,
663 static bool ai_buscore_prep(si_info_t *sii, uint bustype, uint devid,
665 static bool ai_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
666 u32 savewin, uint *origidx, void *regs);
667 static void ai_nvram_process(si_info_t *sii, char *pvars);
669 /* dev path concatenation util */
670 static char *ai_devpathvar(si_t *sih, char *var, int len, const char *name);
671 static bool _ai_clkctl_cc(si_info_t *sii, uint mode);
672 static bool ai_ispcie(si_info_t *sii);
674 /* global variable to indicate reservation/release of gpio's */
675 static u32 ai_gpioreservation;
678 * Allocate a si handle.
679 * devid - pci device id (used to determine chip#)
680 * osh - opaque OS handle
681 * regs - virtual address of initial core registers
682 * bustype - pci/sb/sdio/etc
683 * vars - pointer to a pointer area for "environment" variables
684 * varsz - pointer to int to return the size of the vars
686 si_t *ai_attach(uint devid, void *regs, uint bustype,
687 void *sdh, char **vars, uint *varsz)
691 /* alloc si_info_t */
692 sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC);
694 SI_ERROR(("si_attach: malloc failed!\n"));
698 if (ai_doattach(sii, devid, regs, bustype, sdh, vars, varsz) ==
703 sii->vars = vars ? *vars : NULL;
704 sii->varsz = varsz ? *varsz : 0;
709 /* global kernel resource */
710 static si_info_t ksii;
712 static bool ai_buscore_prep(si_info_t *sii, uint bustype, uint devid,
715 /* kludge to enable the clock on the 4306 which lacks a slowclock */
716 if (bustype == PCI_BUS && !ai_ispcie(sii))
717 ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
721 static bool ai_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
722 u32 savewin, uint *origidx, void *regs)
726 uint pciidx, pcieidx, pcirev, pcierev;
728 cc = ai_setcoreidx(&sii->pub, SI_CC_IDX);
730 /* get chipcommon rev */
731 sii->pub.ccrev = (int)ai_corerev(&sii->pub);
733 /* get chipcommon chipstatus */
734 if (sii->pub.ccrev >= 11)
735 sii->pub.chipst = R_REG(&cc->chipstatus);
737 /* get chipcommon capabilites */
738 sii->pub.cccaps = R_REG(&cc->capabilities);
739 /* get chipcommon extended capabilities */
741 if (sii->pub.ccrev >= 35)
742 sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext);
744 /* get pmu rev and caps */
745 if (sii->pub.cccaps & CC_CAP_PMU) {
746 sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
747 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
750 /* figure out bus/orignal core idx */
751 sii->pub.buscoretype = NODEV_CORE_ID;
752 sii->pub.buscorerev = NOREV;
753 sii->pub.buscoreidx = BADIDX;
756 pcirev = pcierev = NOREV;
757 pciidx = pcieidx = BADIDX;
759 for (i = 0; i < sii->numcores; i++) {
762 ai_setcoreidx(&sii->pub, i);
763 cid = ai_coreid(&sii->pub);
764 crev = ai_corerev(&sii->pub);
766 /* Display cores found */
767 SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
768 i, cid, crev, sii->coresba[i], sii->regs[i]));
770 if (bustype == PCI_BUS) {
771 if (cid == PCI_CORE_ID) {
775 } else if (cid == PCIE_CORE_ID) {
782 /* find the core idx before entering this func. */
783 if ((savewin && (savewin == sii->coresba[i])) ||
784 (regs == sii->regs[i]))
795 sii->pub.buscoretype = PCI_CORE_ID;
796 sii->pub.buscorerev = pcirev;
797 sii->pub.buscoreidx = pciidx;
799 sii->pub.buscoretype = PCIE_CORE_ID;
800 sii->pub.buscorerev = pcierev;
801 sii->pub.buscoreidx = pcieidx;
804 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
805 sii->pub.buscoretype, sii->pub.buscorerev));
807 /* fixup necessary chip/core configurations */
808 if (sii->pub.bustype == PCI_BUS) {
811 sii->pch = (void *)pcicore_init(
812 &sii->pub, sii->pbus,
813 (void *)PCIEREGS(sii));
814 if (sii->pch == NULL)
818 if (ai_pci_fixcfg(&sii->pub)) {
819 SI_ERROR(("si_doattach: si_pci_fixcfg failed\n"));
824 /* return to the original core */
825 ai_setcoreidx(&sii->pub, *origidx);
830 static __used void ai_nvram_process(si_info_t *sii, char *pvars)
834 /* get boardtype and boardrev */
835 switch (sii->pub.bustype) {
837 /* do a pci config read to get subsystem id and subvendor id */
838 pci_read_config_dword(sii->pbus, PCI_SUBSYSTEM_VENDOR_ID, &w);
839 /* Let nvram variables override subsystem Vend/ID */
840 sii->pub.boardvendor = (u16)ai_getdevpathintvar(&sii->pub,
842 if (sii->pub.boardvendor == 0)
843 sii->pub.boardvendor = w & 0xffff;
845 SI_ERROR(("Overriding boardvendor: 0x%x instead of "
846 "0x%x\n", sii->pub.boardvendor, w & 0xffff));
847 sii->pub.boardtype = (u16)ai_getdevpathintvar(&sii->pub,
849 if (sii->pub.boardtype == 0)
850 sii->pub.boardtype = (w >> 16) & 0xffff;
852 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n"
853 , sii->pub.boardtype, (w >> 16) & 0xffff));
856 sii->pub.boardvendor = getintvar(pvars, "manfid");
857 sii->pub.boardtype = getintvar(pvars, "prodid");
862 sii->pub.boardvendor = PCI_VENDOR_ID_BROADCOM;
863 sii->pub.boardtype = getintvar(pvars, "prodid");
864 if (pvars == NULL || (sii->pub.boardtype == 0)) {
865 sii->pub.boardtype = getintvar(NULL, "boardtype");
866 if (sii->pub.boardtype == 0)
867 sii->pub.boardtype = 0xffff;
872 if (sii->pub.boardtype == 0) {
873 SI_ERROR(("si_doattach: unknown board type\n"));
876 sii->pub.boardflags = getintvar(pvars, "boardflags");
879 static si_info_t *ai_doattach(si_info_t *sii, uint devid,
880 void *regs, uint bustype, void *pbus,
881 char **vars, uint *varsz)
883 struct si_pub *sih = &sii->pub;
890 memset((unsigned char *) sii, 0, sizeof(si_info_t));
894 sih->buscoreidx = BADIDX;
899 /* check to see if we are a si core mimic'ing a pci core */
900 if (bustype == PCI_BUS) {
901 pci_read_config_dword(sii->pbus, PCI_SPROM_CONTROL, &w);
902 if (w == 0xffffffff) {
903 SI_ERROR(("%s: incoming bus is PCI but it's a lie, "
904 " switching to SI devid:0x%x\n",
910 /* find Chipcommon address */
911 if (bustype == PCI_BUS) {
912 pci_read_config_dword(sii->pbus, PCI_BAR0_WIN, &savewin);
913 if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
914 savewin = SI_ENUM_BASE;
915 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN,
917 cc = (chipcregs_t *) regs;
919 cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
922 sih->bustype = bustype;
924 /* bus/core/clk setup for register access */
925 if (!ai_buscore_prep(sii, bustype, devid, pbus)) {
926 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
932 * ChipID recognition.
933 * We assume we can read chipid at offset 0 from the regs arg.
934 * If we add other chiptypes (or if we need to support old sdio
935 * hosts w/o chipcommon), some way of recognizing them needs to
938 w = R_REG(&cc->chipid);
939 socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
940 /* Might as wll fill in chip id rev & pkg */
941 sih->chip = w & CID_ID_MASK;
942 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
943 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
945 sih->issim = IS_SIM(sih->chippkg);
948 if (socitype == SOCI_AI) {
949 SI_MSG(("Found chip type AI (0x%08x)\n", w));
950 /* pass chipc address instead of original core base */
951 ai_scan(&sii->pub, (void *)cc, devid);
953 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
956 /* no cores found, bail out */
957 if (sii->numcores == 0) {
958 SI_ERROR(("si_doattach: could not find any cores\n"));
961 /* bus/core/clk setup */
963 if (!ai_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
964 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
968 /* assume current core is CC */
969 if ((sii->pub.ccrev == 0x25)
971 ((sih->chip == BCM43236_CHIP_ID
972 || sih->chip == BCM43235_CHIP_ID
973 || sih->chip == BCM43238_CHIP_ID)
974 && (sii->pub.chiprev <= 2))) {
976 if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
978 clkdiv = R_REG(&cc->clkdiv);
979 /* otp_clk_div is even number, 120/14 < 9mhz */
980 clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
981 W_REG(&cc->clkdiv, clkdiv);
982 SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
987 /* Init nvram from flash if it exists */
990 /* Init nvram from sprom/otp if they exist */
992 (&sii->pub, bustype, regs, vars, varsz)) {
993 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
996 pvars = vars ? *vars : NULL;
997 ai_nvram_process(sii, pvars);
999 /* === NVRAM, clock is ready === */
1000 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
1001 W_REG(&cc->gpiopullup, 0);
1002 W_REG(&cc->gpiopulldown, 0);
1003 ai_setcoreidx(sih, origidx);
1005 /* PMU specific initializations */
1006 if (PMUCTL_ENAB(sih)) {
1009 si_pmu_chip_init(sih);
1010 xtalfreq = getintvar(pvars, "xtalfreq");
1011 /* If xtalfreq var not available, try to measure it */
1013 xtalfreq = si_pmu_measure_alpclk(sih);
1014 si_pmu_pll_init(sih, xtalfreq);
1015 si_pmu_res_init(sih);
1016 si_pmu_swreg_init(sih);
1019 /* setup the GPIO based LED powersave register */
1020 w = getintvar(pvars, "leddc");
1022 w = DEFAULT_GPIOTIMERVAL;
1023 ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
1026 pcicore_attach(sii->pch, pvars, SI_DOATTACH);
1029 if ((sih->chip == BCM43224_CHIP_ID) ||
1030 (sih->chip == BCM43421_CHIP_ID)) {
1032 * enable 12 mA drive strenth for 43224 and
1033 * set chipControl register bit 15
1035 if (sih->chiprev == 0) {
1036 SI_MSG(("Applying 43224A0 WARs\n"));
1037 ai_corereg(sih, SI_CC_IDX,
1038 offsetof(chipcregs_t, chipcontrol),
1039 CCTRL43224_GPIO_TOGGLE,
1040 CCTRL43224_GPIO_TOGGLE);
1041 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
1042 CCTRL_43224A0_12MA_LED_DRIVE);
1044 if (sih->chiprev >= 1) {
1045 SI_MSG(("Applying 43224B0+ WARs\n"));
1046 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
1047 CCTRL_43224B0_12MA_LED_DRIVE);
1051 if (sih->chip == BCM4313_CHIP_ID) {
1053 * enable 12 mA drive strenth for 4313 and
1054 * set chipControl register bit 1
1056 SI_MSG(("Applying 4313 WARs\n"));
1057 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
1058 CCTRL_4313_12MA_LED_DRIVE);
1061 if (sih->chip == BCM4331_CHIP_ID) {
1062 /* Enable Ext PA lines depending on chip package option */
1063 ai_chipcontrl_epa4331(sih, true);
1068 if (sih->bustype == PCI_BUS) {
1070 pcicore_deinit(sii->pch);
1077 /* may be called with core in reset */
1078 void ai_detach(si_t *sih)
1083 struct si_pub *si_local = NULL;
1084 bcopy(&sih, &si_local, sizeof(si_t **));
1091 if (sih->bustype == SI_BUS)
1092 for (idx = 0; idx < SI_MAXCORES; idx++)
1093 if (sii->regs[idx]) {
1094 iounmap(sii->regs[idx]);
1095 sii->regs[idx] = NULL;
1098 nvram_exit(); /* free up nvram buffers */
1100 if (sih->bustype == PCI_BUS) {
1102 pcicore_deinit(sii->pch);
1110 /* register driver interrupt disabling and restoring callback functions */
1112 ai_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
1113 void *intrsenabled_fn, void *intr_arg)
1118 sii->intr_arg = intr_arg;
1119 sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn;
1120 sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn;
1121 sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn;
1122 /* save current core id. when this function called, the current core
1123 * must be the core which provides driver functions(il, et, wl, etc.)
1125 sii->dev_coreid = sii->coreid[sii->curidx];
1128 void ai_deregister_intr_callback(si_t *sih)
1133 sii->intrsoff_fn = NULL;
1136 uint ai_coreid(si_t *sih)
1141 return sii->coreid[sii->curidx];
1144 uint ai_coreidx(si_t *sih)
1152 bool ai_backplane64(si_t *sih)
1154 return (sih->cccaps & CC_CAP_BKPLN64) != 0;
1157 /* return index of coreid or BADIDX if not found */
1158 uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit)
1168 for (i = 0; i < sii->numcores; i++)
1169 if (sii->coreid[i] == coreid) {
1170 if (found == coreunit)
1179 * This function changes logical "focus" to the indicated core;
1180 * must be called with interrupts off.
1181 * Moreover, callers should keep interrupts off during switching
1182 * out of and back to d11 core.
1184 void *ai_setcore(si_t *sih, uint coreid, uint coreunit)
1188 idx = ai_findcoreidx(sih, coreid, coreunit);
1192 return ai_setcoreidx(sih, idx);
1195 /* Turn off interrupt as required by ai_setcore, before switch core */
1196 void *ai_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
1204 /* Overloading the origidx variable to remember the coreid,
1205 * this works because the core ids cannot be confused with
1209 if (coreid == CC_CORE_ID)
1210 return (void *)CCREGS_FAST(sii);
1211 else if (coreid == sih->buscoretype)
1212 return (void *)PCIEREGS(sii);
1214 INTR_OFF(sii, *intr_val);
1215 *origidx = sii->curidx;
1216 cc = ai_setcore(sih, coreid, 0);
1220 /* restore coreidx and restore interrupt */
1221 void ai_restore_core(si_t *sih, uint coreid, uint intr_val)
1227 && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
1230 ai_setcoreidx(sih, coreid);
1231 INTR_RESTORE(sii, intr_val);
1234 void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val)
1236 si_info_t *sii = SI_INFO(sih);
1237 u32 *w = (u32 *) sii->curwrap;
1238 W_REG(w + (offset / 4), val);
1243 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set
1244 * operation, switch back to the original core, and return the new value.
1246 * When using the silicon backplane, no fiddling with interrupts or core
1247 * switches is needed.
1249 * Also, when using pci/pcie, we can optimize away the core switching for pci
1250 * registers and (on newer pci cores) chipcommon registers.
1252 uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
1263 if (coreidx >= SI_MAXCORES)
1266 if (sih->bustype == SI_BUS) {
1267 /* If internal bus, we can always get at everything */
1269 /* map if does not exist */
1270 if (!sii->regs[coreidx]) {
1271 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
1274 r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
1275 } else if (sih->bustype == PCI_BUS) {
1277 * If pci/pcie, we can get at pci/pcie regs
1278 * and on newer cores to chipc
1280 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
1281 /* Chipc registers are mapped at 12KB */
1284 r = (u32 *) ((char *)sii->curmap +
1285 PCI_16KB0_CCREGS_OFFSET + regoff);
1286 } else if (sii->pub.buscoreidx == coreidx) {
1288 * pci registers are at either in the last 2KB of
1289 * an 8KB window or, in pcie and pci rev 13 at 8KB
1293 r = (u32 *) ((char *)sii->curmap +
1294 PCI_16KB0_PCIREGS_OFFSET +
1297 r = (u32 *) ((char *)sii->curmap +
1298 ((regoff >= SBCONFIGOFF) ?
1299 PCI_BAR0_PCISBR_OFFSET :
1300 PCI_BAR0_PCIREGS_OFFSET) +
1306 INTR_OFF(sii, intr_val);
1308 /* save current core index */
1309 origidx = ai_coreidx(&sii->pub);
1312 r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx)
1318 w = (R_REG(r) & ~mask) | val;
1326 /* restore core index */
1327 if (origidx != coreidx)
1328 ai_setcoreidx(&sii->pub, origidx);
1330 INTR_RESTORE(sii, intr_val);
1336 void ai_core_disable(si_t *sih, u32 bits)
1346 /* if core is already in reset, just return */
1347 if (R_REG(&ai->resetctrl) & AIRC_RESET)
1350 W_REG(&ai->ioctrl, bits);
1351 dummy = R_REG(&ai->ioctrl);
1354 W_REG(&ai->resetctrl, AIRC_RESET);
1358 /* reset and re-enable a core
1360 * bits - core specific bits that are set during and after reset sequence
1361 * resetbits - core specific bits that are set only during reset sequence
1363 void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
1373 * Must do the disable sequence first to work
1374 * for arbitrary current core state.
1376 ai_core_disable(sih, (bits | resetbits));
1379 * Now do the initialization sequence.
1381 W_REG(&ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
1382 dummy = R_REG(&ai->ioctrl);
1383 W_REG(&ai->resetctrl, 0);
1386 W_REG(&ai->ioctrl, (bits | SICF_CLOCK_EN));
1387 dummy = R_REG(&ai->ioctrl);
1391 /* return the slow clock source - LPO, XTAL, or PCI */
1392 static uint ai_slowclk_src(si_info_t *sii)
1397 if (sii->pub.ccrev < 6) {
1398 if (sii->pub.bustype == PCI_BUS) {
1399 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,
1401 if (val & PCI_CFG_GPIO_SCS)
1405 } else if (sii->pub.ccrev < 10) {
1406 cc = (chipcregs_t *) ai_setcoreidx(&sii->pub, sii->curidx);
1407 return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
1408 } else /* Insta-clock */
1413 * return the ILP (slowclock) min or max frequency
1414 * precondition: we've established the chip has dynamic clk control
1416 static uint ai_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
1421 slowclk = ai_slowclk_src(sii);
1422 if (sii->pub.ccrev < 6) {
1423 if (slowclk == SCC_SS_PCI)
1424 return max_freq ? (PCIMAXFREQ / 64)
1425 : (PCIMINFREQ / 64);
1427 return max_freq ? (XTALMAXFREQ / 32)
1428 : (XTALMINFREQ / 32);
1429 } else if (sii->pub.ccrev < 10) {
1431 (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
1433 if (slowclk == SCC_SS_LPO)
1434 return max_freq ? LPOMAXFREQ : LPOMINFREQ;
1435 else if (slowclk == SCC_SS_XTAL)
1436 return max_freq ? (XTALMAXFREQ / div)
1437 : (XTALMINFREQ / div);
1438 else if (slowclk == SCC_SS_PCI)
1439 return max_freq ? (PCIMAXFREQ / div)
1440 : (PCIMINFREQ / div);
1442 /* Chipc rev 10 is InstaClock */
1443 div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
1444 div = 4 * (div + 1);
1445 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
1450 static void ai_clkctl_setdelay(si_info_t *sii, void *chipcregs)
1452 chipcregs_t *cc = (chipcregs_t *) chipcregs;
1453 uint slowmaxfreq, pll_delay, slowclk;
1454 uint pll_on_delay, fref_sel_delay;
1456 pll_delay = PLL_DELAY;
1459 * If the slow clock is not sourced by the xtal then
1460 * add the xtal_on_delay since the xtal will also be
1461 * powered down by dynamic clk control logic.
1464 slowclk = ai_slowclk_src(sii);
1465 if (slowclk != SCC_SS_XTAL)
1466 pll_delay += XTAL_ON_DELAY;
1468 /* Starting with 4318 it is ILP that is used for the delays */
1470 ai_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc);
1472 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
1473 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
1475 W_REG(&cc->pll_on_delay, pll_on_delay);
1476 W_REG(&cc->fref_sel_delay, fref_sel_delay);
1479 /* initialize power control delay registers */
1480 void ai_clkctl_init(si_t *sih)
1487 if (!CCCTL_ENAB(sih))
1491 fast = SI_FAST(sii);
1493 origidx = sii->curidx;
1494 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
1498 cc = (chipcregs_t *) CCREGS_FAST(sii);
1503 /* set all Instaclk chip ILP to 1 MHz */
1504 if (sih->ccrev >= 10)
1505 SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
1506 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
1508 ai_clkctl_setdelay(sii, (void *)cc);
1511 ai_setcoreidx(sih, origidx);
1515 * return the value suitable for writing to the
1516 * dot11 core FAST_PWRUP_DELAY register
1518 u16 ai_clkctl_fast_pwrup_delay(si_t *sih)
1529 if (PMUCTL_ENAB(sih)) {
1530 INTR_OFF(sii, intr_val);
1531 fpdelay = si_pmu_fast_pwrup_delay(sih);
1532 INTR_RESTORE(sii, intr_val);
1536 if (!CCCTL_ENAB(sih))
1539 fast = SI_FAST(sii);
1542 origidx = sii->curidx;
1543 INTR_OFF(sii, intr_val);
1544 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
1548 cc = (chipcregs_t *) CCREGS_FAST(sii);
1553 slowminfreq = ai_slowclk_freq(sii, false, cc);
1554 fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
1555 (slowminfreq - 1)) / slowminfreq;
1559 ai_setcoreidx(sih, origidx);
1560 INTR_RESTORE(sii, intr_val);
1565 /* turn primary xtal and/or pll off/on */
1566 int ai_clkctl_xtal(si_t *sih, uint what, bool on)
1573 switch (sih->bustype) {
1576 /* pcie core doesn't have any mapping to control the xtal pu */
1580 pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in);
1581 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, &out);
1582 pci_read_config_dword(sii->pbus, PCI_GPIO_OUTEN, &outen);
1585 * Avoid glitching the clock if GPRS is already using it.
1586 * We can't actually read the state of the PLLPD so we infer it
1587 * by the value of XTAL_PU which *is* readable via gpioin.
1589 if (on && (in & PCI_CFG_GPIO_XTAL))
1593 outen |= PCI_CFG_GPIO_XTAL;
1595 outen |= PCI_CFG_GPIO_PLL;
1598 /* turn primary xtal on */
1600 out |= PCI_CFG_GPIO_XTAL;
1602 out |= PCI_CFG_GPIO_PLL;
1603 pci_write_config_dword(sii->pbus,
1605 pci_write_config_dword(sii->pbus,
1606 PCI_GPIO_OUTEN, outen);
1607 udelay(XTAL_ON_DELAY);
1612 out &= ~PCI_CFG_GPIO_PLL;
1613 pci_write_config_dword(sii->pbus,
1619 out &= ~PCI_CFG_GPIO_XTAL;
1621 out |= PCI_CFG_GPIO_PLL;
1622 pci_write_config_dword(sii->pbus,
1624 pci_write_config_dword(sii->pbus,
1625 PCI_GPIO_OUTEN, outen);
1636 * clock control policy function throught chipcommon
1638 * set dynamic clk control mode (forceslow, forcefast, dynamic)
1639 * returns true if we are forcing fast clock
1640 * this is a wrapper over the next internal function
1641 * to allow flexible policy settings for outside caller
1643 bool ai_clkctl_cc(si_t *sih, uint mode)
1649 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1653 if (PCI_FORCEHT(sii))
1654 return mode == CLK_FAST;
1656 return _ai_clkctl_cc(sii, mode);
1659 /* clk control mechanism through chipcommon, no policy checking */
1660 static bool _ai_clkctl_cc(si_info_t *sii, uint mode)
1666 bool fast = SI_FAST(sii);
1668 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1669 if (sii->pub.ccrev < 6)
1673 INTR_OFF(sii, intr_val);
1674 origidx = sii->curidx;
1676 if ((sii->pub.bustype == SI_BUS) &&
1677 ai_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&
1678 (ai_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
1681 cc = (chipcregs_t *) ai_setcore(&sii->pub, CC_CORE_ID, 0);
1683 cc = (chipcregs_t *) CCREGS_FAST(sii);
1688 if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
1692 case CLK_FAST: /* FORCEHT, fast (pll) clock */
1693 if (sii->pub.ccrev < 10) {
1695 * don't forget to force xtal back
1696 * on before we clear SCC_DYN_XTAL..
1698 ai_clkctl_xtal(&sii->pub, XTAL, ON);
1699 SET_REG(&cc->slow_clk_ctl,
1700 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
1701 } else if (sii->pub.ccrev < 20) {
1702 OR_REG(&cc->system_clk_ctl, SYCC_HR);
1704 OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
1707 /* wait for the PLL */
1708 if (PMUCTL_ENAB(&sii->pub)) {
1709 u32 htavail = CCS_HTAVAIL;
1710 SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
1711 == 0), PMU_MAX_TRANSITION_DLY);
1717 case CLK_DYNAMIC: /* enable dynamic clock control */
1718 if (sii->pub.ccrev < 10) {
1719 scc = R_REG(&cc->slow_clk_ctl);
1720 scc &= ~(SCC_FS | SCC_IP | SCC_XC);
1721 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
1723 W_REG(&cc->slow_clk_ctl, scc);
1726 * for dynamic control, we have to
1727 * release our xtal_pu "force on"
1730 ai_clkctl_xtal(&sii->pub, XTAL, OFF);
1731 } else if (sii->pub.ccrev < 20) {
1733 AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
1735 AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);
1745 ai_setcoreidx(&sii->pub, origidx);
1746 INTR_RESTORE(sii, intr_val);
1748 return mode == CLK_FAST;
1751 /* Build device path. Support SI, PCI, and JTAG for now. */
1752 int ai_devpath(si_t *sih, char *path, int size)
1756 if (!path || size <= 0)
1759 switch (sih->bustype) {
1762 slen = snprintf(path, (size_t) size, "sb/%u/", ai_coreidx(sih));
1765 slen = snprintf(path, (size_t) size, "pci/%u/%u/",
1766 ((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number,
1768 ((struct pci_dev *)((SI_INFO(sih))->pbus))->devfn));
1776 if (slen < 0 || slen >= size) {
1784 /* Get a variable, but only if it has a devpath prefix */
1785 char *ai_getdevpathvar(si_t *sih, const char *name)
1787 char varname[SI_DEVPATH_BUFSZ + 32];
1789 ai_devpathvar(sih, varname, sizeof(varname), name);
1791 return getvar(NULL, varname);
1794 /* Get a variable, but only if it has a devpath prefix */
1795 int ai_getdevpathintvar(si_t *sih, const char *name)
1797 #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
1798 return getintvar(NULL, name);
1800 char varname[SI_DEVPATH_BUFSZ + 32];
1802 ai_devpathvar(sih, varname, sizeof(varname), name);
1804 return getintvar(NULL, varname);
1808 char *ai_getnvramflvar(si_t *sih, const char *name)
1810 return getvar(NULL, name);
1813 /* Concatenate the dev path with a varname into the given 'var' buffer
1814 * and return the 'var' pointer. Nothing is done to the arguments if
1815 * len == 0 or var is NULL, var is still returned. On overflow, the
1816 * first char will be set to '\0'.
1818 static char *ai_devpathvar(si_t *sih, char *var, int len, const char *name)
1822 if (!var || len <= 0)
1825 if (ai_devpath(sih, var, len) == 0) {
1826 path_len = strlen(var);
1828 if (strlen(name) + 1 > (uint) (len - path_len))
1831 strncpy(var + path_len, name, len - path_len - 1);
1837 /* return true if PCIE capability exists in the pci config space */
1838 static __used bool ai_ispcie(si_info_t *sii)
1842 if (sii->pub.bustype != PCI_BUS)
1846 pcicore_find_pci_capability(sii->pbus, PCI_CAP_ID_EXP, NULL,
1854 bool ai_pci_war16165(si_t *sih)
1860 return PCI(sii) && (sih->buscorerev <= 10);
1863 void ai_pci_up(si_t *sih)
1869 /* if not pci bus, we're done */
1870 if (sih->bustype != PCI_BUS)
1873 if (PCI_FORCEHT(sii))
1874 _ai_clkctl_cc(sii, CLK_FAST);
1877 pcicore_up(sii->pch, SI_PCIUP);
1881 /* Unconfigure and/or apply various WARs when system is going to sleep mode */
1882 void ai_pci_sleep(si_t *sih)
1888 pcicore_sleep(sii->pch);
1891 /* Unconfigure and/or apply various WARs when going down */
1892 void ai_pci_down(si_t *sih)
1898 /* if not pci bus, we're done */
1899 if (sih->bustype != PCI_BUS)
1902 /* release FORCEHT since chip is going to "down" state */
1903 if (PCI_FORCEHT(sii))
1904 _ai_clkctl_cc(sii, CLK_DYNAMIC);
1906 pcicore_down(sii->pch, SI_PCIDOWN);
1910 * Configure the pci core for pci client (NIC) action
1911 * coremask is the bitvec of cores by index to be enabled.
1913 void ai_pci_setup(si_t *sih, uint coremask)
1922 if (sii->pub.bustype != PCI_BUS)
1926 /* get current core index */
1929 /* we interrupt on this backplane flag number */
1930 siflag = ai_flag(sih);
1932 /* switch over to pci core */
1933 regs = ai_setcoreidx(sih, sii->pub.buscoreidx);
1937 * Enable sb->pci interrupts. Assume
1938 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1940 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
1941 /* pci config write to set this core bit in PCIIntMask */
1942 pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w);
1943 w |= (coremask << PCI_SBIM_SHIFT);
1944 pci_write_config_dword(sii->pbus, PCI_INT_MASK, w);
1946 /* set sbintvec bit for our flag number */
1947 ai_setint(sih, siflag);
1951 pcicore_pci_setup(sii->pch, regs);
1953 /* switch back to previous core */
1954 ai_setcoreidx(sih, idx);
1959 * Fixup SROMless PCI device's configuration.
1960 * The current core may be changed upon return.
1962 int ai_pci_fixcfg(si_t *sih)
1967 si_info_t *sii = SI_INFO(sih);
1969 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
1970 /* save the current index */
1971 origidx = ai_coreidx(&sii->pub);
1973 /* check 'pi' is correct and fix it if not */
1974 regs = ai_setcore(&sii->pub, sii->pub.buscoretype, 0);
1975 pcicore_fixcfg(sii->pch, regs);
1977 /* restore the original index */
1978 ai_setcoreidx(&sii->pub, origidx);
1980 pcicore_hwup(sii->pch);
1984 /* mask&set gpiocontrol bits */
1985 u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
1991 /* gpios could be shared on router platforms
1992 * ignore reservation if it's high priority (e.g., test apps)
1994 if ((priority != GPIO_HI_PRIORITY) &&
1995 (sih->bustype == SI_BUS) && (val || mask)) {
1996 mask = priority ? (ai_gpioreservation & mask) :
1997 ((ai_gpioreservation | mask) & ~(ai_gpioreservation));
2001 regoff = offsetof(chipcregs_t, gpiocontrol);
2002 return ai_corereg(sih, SI_CC_IDX, regoff, mask, val);
2005 void ai_chipcontrl_epa4331(si_t *sih, bool on)
2013 origidx = ai_coreidx(sih);
2015 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
2017 val = R_REG(&cc->chipcontrol);
2020 if (sih->chippkg == 9 || sih->chippkg == 0xb) {
2021 /* Ext PA Controls for 4331 12x9 Package */
2022 W_REG(&cc->chipcontrol, val |
2023 (CCTRL4331_EXTPA_EN |
2024 CCTRL4331_EXTPA_ON_GPIO2_5));
2026 /* Ext PA Controls for 4331 12x12 Package */
2027 W_REG(&cc->chipcontrol,
2028 val | (CCTRL4331_EXTPA_EN));
2031 val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
2032 W_REG(&cc->chipcontrol, val);
2035 ai_setcoreidx(sih, origidx);
2038 /* Enable BT-COEX & Ex-PA for 4313 */
2039 void ai_epa_4313war(si_t *sih)
2046 origidx = ai_coreidx(sih);
2048 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
2051 W_REG(&cc->gpiocontrol,
2052 R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
2054 ai_setcoreidx(sih, origidx);
2057 /* check if the device is removed */
2058 bool ai_deviceremoved(si_t *sih)
2065 switch (sih->bustype) {
2067 pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
2068 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
2075 bool ai_is_sprom_available(si_t *sih)
2077 if (sih->ccrev >= 31) {
2083 if ((sih->cccaps & CC_CAP_SROM) == 0)
2087 origidx = sii->curidx;
2088 cc = ai_setcoreidx(sih, SI_CC_IDX);
2089 sromctrl = R_REG(&cc->sromcontrol);
2090 ai_setcoreidx(sih, origidx);
2091 return sromctrl & SRC_PRESENT;
2094 switch (sih->chip) {
2095 case BCM4329_CHIP_ID:
2096 return (sih->chipst & CST4329_SPROM_SEL) != 0;
2097 case BCM4319_CHIP_ID:
2098 return (sih->chipst & CST4319_SPROM_SEL) != 0;
2099 case BCM4336_CHIP_ID:
2100 return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
2101 case BCM4330_CHIP_ID:
2102 return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
2103 case BCM4313_CHIP_ID:
2104 return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
2105 case BCM4331_CHIP_ID:
2106 return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
2112 bool ai_is_otp_disabled(si_t *sih)
2114 switch (sih->chip) {
2115 case BCM4329_CHIP_ID:
2116 return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) ==
2118 case BCM4319_CHIP_ID:
2119 return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) ==
2121 case BCM4336_CHIP_ID:
2122 return (sih->chipst & CST4336_OTP_PRESENT) == 0;
2123 case BCM4330_CHIP_ID:
2124 return (sih->chipst & CST4330_OTP_PRESENT) == 0;
2125 case BCM4313_CHIP_ID:
2126 return (sih->chipst & CST4313_OTP_PRESENT) == 0;
2127 /* These chips always have their OTP on */
2128 case BCM43224_CHIP_ID:
2129 case BCM43225_CHIP_ID:
2130 case BCM43421_CHIP_ID:
2131 case BCM43235_CHIP_ID:
2132 case BCM43236_CHIP_ID:
2133 case BCM43238_CHIP_ID:
2134 case BCM4331_CHIP_ID:
2140 bool ai_is_otp_powered(si_t *sih)
2142 if (PMUCTL_ENAB(sih))
2143 return si_pmu_is_otp_powered(sih);
2147 void ai_otp_power(si_t *sih, bool on)
2149 if (PMUCTL_ENAB(sih))
2150 si_pmu_otp_power(sih, on);