2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/pci.h>
17 #include <net/mac80211.h>
19 #include <brcm_hw_ids.h>
21 #include <chipcommon.h>
24 #include "phy/phy_hal.h"
27 #include "ucode_loader.h"
28 #include "mac80211_if.h"
31 #define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
33 #define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
34 #define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
35 #define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
36 #define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
38 #define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
40 #ifndef BMAC_DUP_TO_REMOVE
41 #define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
43 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
45 #endif /* BMAC_DUP_TO_REMOVE */
47 #define DMAREG(wlc_hw, direction, fifonum) \
48 ((direction == DMA_TX) ? \
49 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
50 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
52 #define APHY_SLOT_TIME 9
53 #define BPHY_SLOT_TIME 20
56 * The following table lists the buffer memory allocated to xmt fifos in HW.
57 * the size is in units of 256bytes(one block), total size is HW dependent
58 * ucode has default fifo partition, sw can overwrite if necessary
60 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
61 * the twiki is updated before making changes.
64 #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
66 static u16 xmtfifo_sz[][NFIFO] = {
67 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
68 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
69 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
70 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
71 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
74 static void brcms_b_clkctl_clk(struct brcms_c_hw_info *wlc, uint mode);
75 static void brcms_b_coreinit(struct brcms_c_info *wlc);
77 /* used by wlc_wakeucode_init() */
78 static void wlc_write_inits(struct brcms_c_hw_info *wlc_hw,
79 const struct d11init *inits);
80 static void wlc_ucode_write(struct brcms_c_hw_info *wlc_hw, const u32 ucode[],
82 static void wlc_ucode_download(struct brcms_c_hw_info *wlc);
83 static void wlc_ucode_txant_set(struct brcms_c_hw_info *wlc_hw);
85 /* used by brcms_c_dpc() */
86 static bool brcms_b_dotxstatus(struct brcms_c_hw_info *wlc, tx_status_t *txs,
88 static bool brcms_b_txstatus(struct brcms_c_hw_info *wlc, bool bound,
90 static bool brcms_b_recv(struct brcms_c_hw_info *wlc_hw, uint fifo, bool bound);
92 /* used by brcms_c_down() */
93 static void wlc_flushqueues(struct brcms_c_info *wlc);
95 static void wlc_write_mhf(struct brcms_c_hw_info *wlc_hw, u16 *mhfs);
96 static void wlc_mctrl_reset(struct brcms_c_hw_info *wlc_hw);
97 static void brcms_b_corerev_fifofixup(struct brcms_c_hw_info *wlc_hw);
98 static bool brcms_b_tx_fifo_suspended(struct brcms_c_hw_info *wlc_hw,
100 static void brcms_b_tx_fifo_suspend(struct brcms_c_hw_info *wlc_hw,
102 static void brcms_b_tx_fifo_resume(struct brcms_c_hw_info *wlc_hw,
105 /* Low Level Prototypes */
106 static int brcms_b_bandtype(struct brcms_c_hw_info *wlc_hw);
107 static void brcms_b_info_init(struct brcms_c_hw_info *wlc_hw);
108 static void brcms_b_xtal(struct brcms_c_hw_info *wlc_hw, bool want);
109 static u16 brcms_b_read_objmem(struct brcms_c_hw_info *wlc_hw, uint offset,
111 static void brcms_b_write_objmem(struct brcms_c_hw_info *wlc_hw, uint offset,
113 static void brcms_b_core_phy_clk(struct brcms_c_hw_info *wlc_hw, bool clk);
114 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme);
115 static void brcms_b_detach_dmapio(struct brcms_c_hw_info *wlc_hw);
116 static void wlc_ucode_bsinit(struct brcms_c_hw_info *wlc_hw);
117 static bool wlc_validboardtype(struct brcms_c_hw_info *wlc);
118 static bool wlc_isgoodchip(struct brcms_c_hw_info *wlc_hw);
119 static bool brcms_b_validate_chip_access(struct brcms_c_hw_info *wlc_hw);
120 static char *wlc_get_macaddr(struct brcms_c_hw_info *wlc_hw);
121 static void wlc_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init);
122 static void wlc_mctrl_write(struct brcms_c_hw_info *wlc_hw);
123 static void brcms_b_mute(struct brcms_c_hw_info *wlc_hw, bool want,
125 static void wlc_ucode_mute_override_set(struct brcms_c_hw_info *wlc_hw);
126 static void wlc_ucode_mute_override_clear(struct brcms_c_hw_info *wlc_hw);
127 static u32 wlc_wlintrsoff(struct brcms_c_info *wlc);
128 static void wlc_wlintrsrestore(struct brcms_c_info *wlc, u32 macintmask);
129 static void wlc_gpio_init(struct brcms_c_info *wlc);
130 static void wlc_write_hw_bcntemplate0(struct brcms_c_hw_info *wlc_hw, void *bcn,
132 static void wlc_write_hw_bcntemplate1(struct brcms_c_hw_info *wlc_hw, void *bcn,
134 static void brcms_b_bsinit(struct brcms_c_info *wlc, chanspec_t chanspec);
135 static u32 wlc_setband_inact(struct brcms_c_info *wlc, uint bandunit);
136 static void brcms_b_setband(struct brcms_c_hw_info *wlc_hw, uint bandunit,
137 chanspec_t chanspec);
138 static void brcms_b_update_slot_timing(struct brcms_c_hw_info *wlc_hw,
140 static void wlc_upd_ofdm_pctl1_table(struct brcms_c_hw_info *wlc_hw);
141 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_c_hw_info *wlc_hw,
144 /* === Low Level functions === */
146 void brcms_b_set_shortslot(struct brcms_c_hw_info *wlc_hw, bool shortslot)
148 wlc_hw->shortslot = shortslot;
150 if (BAND_2G(brcms_b_bandtype(wlc_hw)) && wlc_hw->up) {
151 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
152 brcms_b_update_slot_timing(wlc_hw, shortslot);
153 brcms_c_enable_mac(wlc_hw->wlc);
158 * Update the slot timing for standard 11b/g (20us slots)
159 * or shortslot 11g (9us slots)
160 * The PSM needs to be suspended for this call.
162 static void brcms_b_update_slot_timing(struct brcms_c_hw_info *wlc_hw,
170 /* 11g short slot: 11a timing */
171 W_REG(®s->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
172 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
174 /* 11g long slot: 11b timing */
175 W_REG(®s->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
176 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
180 static void WLBANDINITFN(wlc_ucode_bsinit) (struct brcms_c_hw_info *wlc_hw)
182 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
184 /* init microcode host flags */
185 wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
187 /* do band-specific ucode IHR, SHM, and SCR inits */
188 if (D11REV_IS(wlc_hw->corerev, 23)) {
189 if (WLCISNPHY(wlc_hw->band)) {
190 wlc_write_inits(wlc_hw, d11n0bsinitvals16);
192 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
193 " %d\n", __func__, wlc_hw->unit,
197 if (D11REV_IS(wlc_hw->corerev, 24)) {
198 if (WLCISLCNPHY(wlc_hw->band)) {
199 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
201 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
202 " core rev %d\n", __func__,
203 wlc_hw->unit, wlc_hw->corerev);
205 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
206 __func__, wlc_hw->unit, wlc_hw->corerev);
211 /* switch to new band but leave it inactive */
212 static u32 WLBANDINITFN(wlc_setband_inact) (struct brcms_c_info *wlc,
215 struct brcms_c_hw_info *wlc_hw = wlc->hw;
218 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
220 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
222 /* disable interrupts */
223 macintmask = brcms_intrsoff(wlc->wl);
226 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
228 brcms_b_core_phy_clk(wlc_hw, OFF);
230 brcms_c_setxband(wlc_hw, bandunit);
235 /* Process received frames */
237 * Return true if more frames need to be processed. false otherwise.
238 * Param 'bound' indicates max. # frames to process before break out.
241 brcms_b_recv(struct brcms_c_hw_info *wlc_hw, uint fifo, bool bound)
244 struct sk_buff *head = NULL;
245 struct sk_buff *tail = NULL;
247 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
248 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
250 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
251 /* gather received frames */
252 while ((p = dma_rx(wlc_hw->di[fifo]))) {
261 /* !give others some time to run! */
262 if (++n >= bound_limit)
266 /* post more rbufs */
267 dma_rxfill(wlc_hw->di[fifo]);
269 /* process each frame */
270 while ((p = head) != NULL) {
274 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
276 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
277 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
279 brcms_c_recv(wlc_hw->wlc, p);
282 return n >= bound_limit;
285 /* second-level interrupt processing
286 * Return true if another dpc needs to be re-scheduled. false otherwise.
287 * Param 'bounded' indicates if applicable loops should be bounded.
289 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
292 struct brcms_c_hw_info *wlc_hw = wlc->hw;
293 d11regs_t *regs = wlc_hw->regs;
295 struct wiphy *wiphy = wlc->wiphy;
297 if (DEVICEREMOVED(wlc)) {
298 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
304 /* grab and clear the saved software intstatus bits */
305 macintstatus = wlc->macintstatus;
306 wlc->macintstatus = 0;
308 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
309 wlc_hw->unit, macintstatus);
311 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
313 /* BCN template is available */
314 /* ZZZ: Use AP_ACTIVE ? */
315 if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
316 && (macintstatus & MI_BCNTPL)) {
317 brcms_c_update_beacon(wlc);
320 /* PMQ entry addition */
321 if (macintstatus & MI_PMQ) {
325 if (macintstatus & MI_TFS) {
326 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
327 wlc->macintstatus |= MI_TFS;
329 wiphy_err(wiphy, "MI_TFS: fatal\n");
334 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
337 /* ATIM window end */
338 if (macintstatus & MI_ATIMWINEND) {
339 BCMMSG(wlc->wiphy, "end of ATIM window\n");
340 OR_REG(®s->maccommand, wlc->qvalid);
344 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
345 if (macintstatus & MI_DMAINT)
346 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
347 wlc->macintstatus |= MI_DMAINT;
349 /* TX FIFO suspend/flush completion */
350 if (macintstatus & MI_TXSTOP)
351 if (brcms_b_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO));
353 /* noise sample collected */
354 if (macintstatus & MI_BG_NOISE) {
355 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
358 if (macintstatus & MI_GP0) {
359 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
360 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
362 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
363 __func__, wlc_hw->sih->chip,
364 wlc_hw->sih->chiprev);
369 /* gptimer timeout */
370 if (macintstatus & MI_TO) {
371 W_REG(®s->gptimer, 0);
374 if (macintstatus & MI_RFDISABLE) {
375 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
376 " RF Disable Input\n", wlc_hw->unit);
377 brcms_rfkill_set_hw_state(wlc->wl);
380 /* send any enq'd tx packets. Just makes sure to jump start tx */
381 if (!pktq_empty(&wlc->pkt_queue->q))
384 /* it isn't done and needs to be resched if macintstatus is non-zero */
385 return wlc->macintstatus != 0;
389 return wlc->macintstatus != 0;
392 /* common low-level watchdog code */
393 void brcms_b_watchdog(void *arg)
395 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
396 struct brcms_c_hw_info *wlc_hw = wlc->hw;
398 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
403 /* increment second count */
406 /* Check for FIFO error interrupts */
407 brcms_b_fifoerrors(wlc_hw);
409 /* make sure RX dma has buffers */
410 dma_rxfill(wlc->hw->di[RX_FIFO]);
412 wlc_phy_watchdog(wlc_hw->band->pi);
416 brcms_b_set_chanspec(struct brcms_c_hw_info *wlc_hw, chanspec_t chanspec,
417 bool mute, struct txpwr_limits *txpwr)
421 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
423 wlc_hw->chanspec = chanspec;
425 /* Switch bands if necessary */
426 if (NBANDS_HW(wlc_hw) > 1) {
427 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
428 if (wlc_hw->band->bandunit != bandunit) {
429 /* brcms_b_setband disables other bandunit,
430 * use light band switch if not up yet
433 wlc_phy_chanspec_radio_set(wlc_hw->
434 bandstate[bandunit]->
436 brcms_b_setband(wlc_hw, bandunit, chanspec);
438 brcms_c_setxband(wlc_hw, bandunit);
443 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
447 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
449 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
451 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
452 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
454 /* Update muting of the channel */
455 brcms_b_mute(wlc_hw, mute, 0);
459 int brcms_b_state_get(struct brcms_c_hw_info *wlc_hw, brcms_b_state_t *state)
461 state->machwcap = wlc_hw->machwcap;
466 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
470 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
472 struct brcms_c_hw_info *wlc_hw = wlc->hw;
473 uint unit = wlc_hw->unit;
474 wlc_tunables_t *tune = wlc->pub->tunables;
475 struct wiphy *wiphy = wlc->wiphy;
477 /* name and offsets for dma_attach */
478 snprintf(name, sizeof(name), "wl%d", unit);
480 if (wlc_hw->di[0] == 0) { /* Init FIFOs */
482 int dma_attach_err = 0;
483 /* Find out the DMA addressing capability and let OS know
484 * All the channels within one DMA core have 'common-minimum' same
488 dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
490 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
491 wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
492 "resources failed\n", unit);
498 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
499 * RX: RX_FIFO (RX data packets)
501 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
502 (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
503 NULL), DMAREG(wlc_hw, DMA_RX, 0),
504 (wme ? tune->ntxd : 0), tune->nrxd,
505 tune->rxbufsz, -1, tune->nrxbufpost,
506 WL_HWRXOFF, &brcm_msg_level);
507 dma_attach_err |= (NULL == wlc_hw->di[0]);
511 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
512 * (legacy) TX_DATA_FIFO (TX data packets)
515 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
516 DMAREG(wlc_hw, DMA_TX, 1), NULL,
517 tune->ntxd, 0, 0, -1, 0, 0,
519 dma_attach_err |= (NULL == wlc_hw->di[1]);
523 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
526 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
527 DMAREG(wlc_hw, DMA_TX, 2), NULL,
528 tune->ntxd, 0, 0, -1, 0, 0,
530 dma_attach_err |= (NULL == wlc_hw->di[2]);
533 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
534 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
536 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
537 DMAREG(wlc_hw, DMA_TX, 3),
538 NULL, tune->ntxd, 0, 0, -1,
539 0, 0, &brcm_msg_level);
540 dma_attach_err |= (NULL == wlc_hw->di[3]);
541 /* Cleaner to leave this as if with AP defined */
543 if (dma_attach_err) {
544 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
549 /* get pointer to dma engine tx flow control variable */
550 for (i = 0; i < NFIFO; i++)
553 (uint *) dma_getvar(wlc_hw->di[i],
557 /* initial ucode host flags */
558 wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
563 static void brcms_b_detach_dmapio(struct brcms_c_hw_info *wlc_hw)
567 for (j = 0; j < NFIFO; j++) {
569 dma_detach(wlc_hw->di[j]);
570 wlc_hw->di[j] = NULL;
576 * run backplane attach, init nvram
578 * initialize software state for each core and band
579 * put the whole chip in reset(driver down state), no clock
581 int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
582 bool piomode, void *regsva, uint bustype, void *btparam)
584 struct brcms_c_hw_info *wlc_hw;
586 char *macaddr = NULL;
591 shared_phy_params_t sha_params;
592 struct wiphy *wiphy = wlc->wiphy;
594 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
602 wlc_hw->band = wlc_hw->bandstate[0];
603 wlc_hw->_piomode = piomode;
605 /* populate struct brcms_c_hw_info with default values */
606 brcms_b_info_init(wlc_hw);
609 * Do the hardware portion of the attach.
610 * Also initialize software state that depends on the particular hardware
613 wlc_hw->sih = ai_attach(regsva, bustype, btparam,
614 &wlc_hw->vars, &wlc_hw->vars_size);
615 if (wlc_hw->sih == NULL) {
616 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
624 * Get vendid/devid nvram overwrites, which could be different
625 * than those the BIOS recognizes for devices on PCMCIA_BUS,
626 * SDIO_BUS, and SROMless devices on PCI_BUS.
629 bustype = BCMBUSTYPE;
631 if (bustype != SI_BUS) {
634 var = getvar(vars, "vendid");
636 vendor = (u16) simple_strtoul(var, NULL, 0);
637 wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
640 var = getvar(vars, "devid");
642 u16 devid = (u16) simple_strtoul(var, NULL, 0);
643 if (devid != 0xffff) {
645 wiphy_err(wiphy, "Overriding device id = 0x%x"
650 /* verify again the device is supported */
651 if (!brcms_c_chipmatch(vendor, device)) {
652 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
653 "vendor/device (0x%x/0x%x)\n",
654 unit, vendor, device);
660 wlc_hw->vendorid = vendor;
661 wlc_hw->deviceid = device;
663 /* set bar0 window to point at D11 core */
664 wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
665 wlc_hw->corerev = ai_corerev(wlc_hw->sih);
669 wlc->regs = wlc_hw->regs;
671 /* validate chip, chiprev and corerev */
672 if (!wlc_isgoodchip(wlc_hw)) {
677 /* initialize power control registers */
678 ai_clkctl_init(wlc_hw->sih);
680 /* request fastclock and force fastclock for the rest of attach
681 * bring the d11 core out of reset.
682 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
683 * But it will be called again inside wlc_corereset, after d11 is out of reset.
685 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
686 brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
688 if (!brcms_b_validate_chip_access(wlc_hw)) {
689 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
695 /* get the board rev, used just below */
696 j = getintvar(vars, "boardrev");
697 /* promote srom boardrev of 0xFF to 1 */
698 if (j == BOARDREV_PROMOTABLE)
699 j = BOARDREV_PROMOTED;
700 wlc_hw->boardrev = (u16) j;
701 if (!wlc_validboardtype(wlc_hw)) {
702 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
703 "board type (0x%x)" " or revision level (0x%x)\n",
704 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
708 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
709 wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
710 wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
712 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
713 brcms_b_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
715 if ((wlc_hw->sih->bustype == PCI_BUS)
716 && (ai_pci_war16165(wlc_hw->sih)))
717 wlc->war16165 = true;
719 /* check device id(srom, nvram etc.) to set bands */
720 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
721 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
722 /* Dualband boards */
727 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
730 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
731 * unconditionally does the init of these values
733 wlc->vendorid = wlc_hw->vendorid;
734 wlc->deviceid = wlc_hw->deviceid;
735 wlc->pub->sih = wlc_hw->sih;
736 wlc->pub->corerev = wlc_hw->corerev;
737 wlc->pub->sromrev = wlc_hw->sromrev;
738 wlc->pub->boardrev = wlc_hw->boardrev;
739 wlc->pub->boardflags = wlc_hw->boardflags;
740 wlc->pub->boardflags2 = wlc_hw->boardflags2;
741 wlc->pub->_nbands = wlc_hw->_nbands;
743 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
745 if (wlc_hw->physhim == NULL) {
746 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
752 /* pass all the parameters to wlc_phy_shared_attach in one struct */
753 sha_params.sih = wlc_hw->sih;
754 sha_params.physhim = wlc_hw->physhim;
755 sha_params.unit = unit;
756 sha_params.corerev = wlc_hw->corerev;
757 sha_params.vars = vars;
758 sha_params.vid = wlc_hw->vendorid;
759 sha_params.did = wlc_hw->deviceid;
760 sha_params.chip = wlc_hw->sih->chip;
761 sha_params.chiprev = wlc_hw->sih->chiprev;
762 sha_params.chippkg = wlc_hw->sih->chippkg;
763 sha_params.sromrev = wlc_hw->sromrev;
764 sha_params.boardtype = wlc_hw->sih->boardtype;
765 sha_params.boardrev = wlc_hw->boardrev;
766 sha_params.boardvendor = wlc_hw->sih->boardvendor;
767 sha_params.boardflags = wlc_hw->boardflags;
768 sha_params.boardflags2 = wlc_hw->boardflags2;
769 sha_params.bustype = wlc_hw->sih->bustype;
770 sha_params.buscorerev = wlc_hw->sih->buscorerev;
772 /* alloc and save pointer to shared phy state area */
773 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
774 if (!wlc_hw->phy_sh) {
779 /* initialize software state for each core and band */
780 for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
782 * band0 is always 2.4Ghz
783 * band1, if present, is 5Ghz
786 /* So if this is a single band 11a card, use band 1 */
787 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
790 brcms_c_setxband(wlc_hw, j);
792 wlc_hw->band->bandunit = j;
793 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
794 wlc->band->bandunit = j;
795 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
796 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
798 wlc_hw->machwcap = R_REG(®s->machwcap);
799 wlc_hw->machwcap_backup = wlc_hw->machwcap;
801 /* init tx fifo size */
803 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
805 /* Get a phy for this band */
806 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
807 (void *)regs, brcms_b_bandtype(wlc_hw), vars,
809 if (wlc_hw->band->pi == NULL) {
810 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
811 "attach failed\n", unit);
816 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
818 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
819 &wlc_hw->band->phyrev,
820 &wlc_hw->band->radioid,
821 &wlc_hw->band->radiorev);
822 wlc_hw->band->abgphy_encore =
823 wlc_phy_get_encore(wlc_hw->band->pi);
824 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
825 wlc_hw->band->core_flags =
826 wlc_phy_get_coreflags(wlc_hw->band->pi);
828 /* verify good phy_type & supported phy revision */
829 if (WLCISNPHY(wlc_hw->band)) {
830 if (NCONF_HAS(wlc_hw->band->phyrev))
834 } else if (WLCISLCNPHY(wlc_hw->band)) {
835 if (LCNCONF_HAS(wlc_hw->band->phyrev))
841 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
842 "phy type/rev (%d/%d)\n", unit,
843 wlc_hw->band->phytype, wlc_hw->band->phyrev);
849 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
850 * high level attach. However we can not make that change until all low level access
851 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
852 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
853 * low only init when all fns updated.
855 wlc->band->pi = wlc_hw->band->pi;
856 wlc->band->phytype = wlc_hw->band->phytype;
857 wlc->band->phyrev = wlc_hw->band->phyrev;
858 wlc->band->radioid = wlc_hw->band->radioid;
859 wlc->band->radiorev = wlc_hw->band->radiorev;
861 /* default contention windows size limits */
862 wlc_hw->band->CWmin = APHY_CWMIN;
863 wlc_hw->band->CWmax = PHY_CWMAX;
865 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
871 /* disable core to match driver "down" state */
872 brcms_c_coredisable(wlc_hw);
874 /* Match driver "down" state */
875 if (wlc_hw->sih->bustype == PCI_BUS)
876 ai_pci_down(wlc_hw->sih);
878 /* register sb interrupt callback functions */
879 ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
880 (void *)wlc_wlintrsrestore, NULL, wlc);
882 /* turn off pll and xtal to match driver "down" state */
883 brcms_b_xtal(wlc_hw, OFF);
885 /* *********************************************************************
886 * The hardware is in the DOWN state at this point. D11 core
887 * or cores are in reset with clocks off, and the board PLLs
888 * are off if possible.
890 * Beyond this point, wlc->sbclk == false and chip registers
891 * should not be touched.
892 *********************************************************************
895 /* init etheraddr state variables */
896 macaddr = wlc_get_macaddr(wlc_hw);
897 if (macaddr == NULL) {
898 wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
903 brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
904 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
905 is_zero_ether_addr(wlc_hw->etheraddr)) {
906 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
913 "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
914 wlc_hw->deviceid, wlc_hw->_nbands,
915 wlc_hw->sih->boardtype, macaddr);
920 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
926 * Initialize brcms_c_info default values ...
927 * may get overrides later in this function
928 * BMAC_NOTES, move low out and resolve the dangling ones
930 static void brcms_b_info_init(struct brcms_c_hw_info *wlc_hw)
932 struct brcms_c_info *wlc = wlc_hw->wlc;
934 /* set default sw macintmask value */
935 wlc->defmacintmask = DEF_MACINTMASK;
937 /* various 802.11g modes */
938 wlc_hw->shortslot = false;
940 wlc_hw->SFBL = RETRY_SHORT_FB;
941 wlc_hw->LFBL = RETRY_LONG_FB;
943 /* default mac retry limits */
944 wlc_hw->SRL = RETRY_SHORT_DEF;
945 wlc_hw->LRL = RETRY_LONG_DEF;
946 wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
952 int brcms_b_detach(struct brcms_c_info *wlc)
955 struct brcms_c_hwband *band;
956 struct brcms_c_hw_info *wlc_hw = wlc->hw;
962 /* detach interrupt sync mechanism since interrupt is disabled and per-port
963 * interrupt object may has been freed. this must be done before sb core switch
965 ai_deregister_intr_callback(wlc_hw->sih);
967 if (wlc_hw->sih->bustype == PCI_BUS)
968 ai_pci_sleep(wlc_hw->sih);
971 brcms_b_detach_dmapio(wlc_hw);
974 for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
976 /* Detach this band's phy */
977 wlc_phy_detach(band->pi);
980 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
983 /* Free shared phy state */
984 wlc_phy_shared_detach(wlc_hw->phy_sh);
986 wlc_phy_shim_detach(wlc_hw->physhim);
993 ai_detach(wlc_hw->sih);
1001 void brcms_b_reset(struct brcms_c_hw_info *wlc_hw)
1003 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1005 /* reset the core */
1006 if (!DEVICEREMOVED(wlc_hw->wlc))
1007 brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
1009 /* purge the dma rings */
1010 wlc_flushqueues(wlc_hw->wlc);
1012 brcms_c_reset_bmac_done(wlc_hw->wlc);
1016 brcms_b_init(struct brcms_c_hw_info *wlc_hw, chanspec_t chanspec,
1020 struct brcms_c_info *wlc = wlc_hw->wlc;
1022 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1024 /* request FAST clock if not on */
1025 fastclk = wlc_hw->forcefastclk;
1027 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1029 /* disable interrupts */
1030 macintmask = brcms_intrsoff(wlc->wl);
1032 /* set up the specified band and chanspec */
1033 brcms_c_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1034 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1036 /* do one-time phy inits and calibration */
1037 wlc_phy_cal_init(wlc_hw->band->pi);
1039 /* core-specific initialization */
1040 brcms_b_coreinit(wlc);
1042 /* suspend the tx fifos and mute the phy for preism cac time */
1044 brcms_b_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1046 /* band-specific inits */
1047 brcms_b_bsinit(wlc, chanspec);
1049 /* restore macintmask */
1050 brcms_intrsrestore(wlc->wl, macintmask);
1052 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1053 * and brcms_c_enable_mac() will clear this override bit.
1055 mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1058 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1060 wlc_hw->mac_suspend_depth = 1;
1062 /* restore the clk */
1064 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1067 int brcms_b_up_prep(struct brcms_c_hw_info *wlc_hw)
1071 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1074 * Enable pll and xtal, initialize the power control registers,
1075 * and force fastclock for the remainder of brcms_c_up().
1077 brcms_b_xtal(wlc_hw, ON);
1078 ai_clkctl_init(wlc_hw->sih);
1079 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1082 * Configure pci/pcmcia here instead of in brcms_c_attach()
1083 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1085 coremask = (1 << wlc_hw->wlc->core->coreidx);
1087 if (wlc_hw->sih->bustype == PCI_BUS)
1088 ai_pci_setup(wlc_hw->sih, coremask);
1091 * Need to read the hwradio status here to cover the case where the system
1092 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1094 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
1095 /* put SB PCI in down state again */
1096 if (wlc_hw->sih->bustype == PCI_BUS)
1097 ai_pci_down(wlc_hw->sih);
1098 brcms_b_xtal(wlc_hw, OFF);
1102 if (wlc_hw->sih->bustype == PCI_BUS)
1103 ai_pci_up(wlc_hw->sih);
1105 /* reset the d11 core */
1106 brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
1111 int brcms_b_up_finish(struct brcms_c_hw_info *wlc_hw)
1113 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1116 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1118 /* FULLY enable dynamic power control and d11 core interrupt */
1119 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1120 brcms_intrson(wlc_hw->wlc->wl);
1124 int brcms_b_bmac_down_prep(struct brcms_c_hw_info *wlc_hw)
1129 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1134 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1136 /* disable interrupts */
1138 wlc_hw->wlc->macintmask = 0;
1140 /* now disable interrupts */
1141 brcms_intrsoff(wlc_hw->wlc->wl);
1143 /* ensure we're running on the pll clock again */
1144 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1146 /* down phy at the last of this stage */
1147 callbacks += wlc_phy_down(wlc_hw->band->pi);
1152 int brcms_b_down_finish(struct brcms_c_hw_info *wlc_hw)
1157 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1163 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1165 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1168 wlc_hw->sbclk = false;
1169 wlc_hw->clk = false;
1170 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1172 /* reclaim any posted packets */
1173 wlc_flushqueues(wlc_hw->wlc);
1176 /* Reset and disable the core */
1177 if (ai_iscoreup(wlc_hw->sih)) {
1178 if (R_REG(&wlc_hw->regs->maccontrol) &
1180 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
1181 callbacks += brcms_reset(wlc_hw->wlc->wl);
1182 brcms_c_coredisable(wlc_hw);
1185 /* turn off primary xtal and pll */
1186 if (!wlc_hw->noreset) {
1187 if (wlc_hw->sih->bustype == PCI_BUS)
1188 ai_pci_down(wlc_hw->sih);
1189 brcms_b_xtal(wlc_hw, OFF);
1196 void brcms_b_wait_for_wake(struct brcms_c_hw_info *wlc_hw)
1198 /* delay before first read of ucode state */
1201 /* wait until ucode is no longer asleep */
1202 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1203 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1206 void brcms_b_hw_etheraddr(struct brcms_c_hw_info *wlc_hw, u8 *ea)
1208 memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1211 static int brcms_b_bandtype(struct brcms_c_hw_info *wlc_hw)
1213 return wlc_hw->band->bandtype;
1216 /* control chip clock to save power, enable dynamic clock or force fast clock */
1217 static void brcms_b_clkctl_clk(struct brcms_c_hw_info *wlc_hw, uint mode)
1219 if (PMUCTL_ENAB(wlc_hw->sih)) {
1220 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1221 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1222 * which means the FCA bit may not be set.
1223 * should wakeup mac if driver wants it to run on HT.
1227 if (mode == CLK_FAST) {
1228 OR_REG(&wlc_hw->regs->clk_ctl_st,
1235 clk_ctl_st) & CCS_HTAVAIL) == 0),
1236 PMU_MAX_TRANSITION_DLY);
1239 clk_ctl_st) & CCS_HTAVAIL));
1241 if ((wlc_hw->sih->pmurev == 0) &&
1244 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1247 clk_ctl_st) & CCS_HTAVAIL)
1249 PMU_MAX_TRANSITION_DLY);
1250 AND_REG(&wlc_hw->regs->clk_ctl_st,
1254 wlc_hw->forcefastclk = (mode == CLK_FAST);
1257 /* old chips w/o PMU, force HT through cc,
1258 * then use FCA to verify mac is running fast clock
1261 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1263 /* check fast clock is available (if core is not in reset) */
1264 if (wlc_hw->forcefastclk && wlc_hw->clk)
1265 WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1268 /* keep the ucode wake bit on if forcefastclk is on
1269 * since we do not want ucode to put us back to slow clock
1270 * when it dozes for PM mode.
1271 * Code below matches the wake override bit with current forcefastclk state
1272 * Only setting bit in wake_override instead of waking ucode immediately
1273 * since old code (wlc.c 1.4499) had this behavior. Older code set
1274 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1275 * (protected by an up check) was executed just below.
1277 if (wlc_hw->forcefastclk)
1278 mboolset(wlc_hw->wake_override,
1279 WLC_WAKE_OVERRIDE_FORCEFAST);
1281 mboolclr(wlc_hw->wake_override,
1282 WLC_WAKE_OVERRIDE_FORCEFAST);
1286 /* set initial host flags value */
1288 wlc_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1290 struct brcms_c_hw_info *wlc_hw = wlc->hw;
1292 memset(mhfs, 0, MHFMAX * sizeof(u16));
1294 mhfs[MHF2] |= mhf2_init;
1296 /* prohibit use of slowclock on multifunction boards */
1297 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1298 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1300 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1301 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1302 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1306 /* set or clear ucode host flag bits
1307 * it has an optimization for no-change write
1308 * it only writes through shared memory when the core has clock;
1309 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1312 * bands values are: WLC_BAND_AUTO <--- Current band only
1313 * WLC_BAND_5G <--- 5G band only
1314 * WLC_BAND_2G <--- 2G band only
1315 * WLC_BAND_ALL <--- All bands
1318 brcms_b_mhf(struct brcms_c_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1322 u16 addr[MHFMAX] = {
1323 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1326 struct brcms_c_hwband *band;
1328 if ((val & ~mask) || idx >= MHFMAX)
1329 return; /* error condition */
1332 /* Current band only or all bands,
1333 * then set the band to current band
1337 band = wlc_hw->band;
1340 band = wlc_hw->bandstate[BAND_5G_INDEX];
1343 band = wlc_hw->bandstate[BAND_2G_INDEX];
1346 band = NULL; /* error condition */
1350 save = band->mhfs[idx];
1351 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1353 /* optimization: only write through if changed, and
1354 * changed band is the current band
1356 if (wlc_hw->clk && (band->mhfs[idx] != save)
1357 && (band == wlc_hw->band))
1358 brcms_b_write_shm(wlc_hw, addr[idx],
1359 (u16) band->mhfs[idx]);
1362 if (bands == WLC_BAND_ALL) {
1363 wlc_hw->bandstate[0]->mhfs[idx] =
1364 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1365 wlc_hw->bandstate[1]->mhfs[idx] =
1366 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1370 u16 brcms_b_mhf_get(struct brcms_c_hw_info *wlc_hw, u8 idx, int bands)
1372 struct brcms_c_hwband *band;
1375 return 0; /* error condition */
1378 band = wlc_hw->band;
1381 band = wlc_hw->bandstate[BAND_5G_INDEX];
1384 band = wlc_hw->bandstate[BAND_2G_INDEX];
1387 band = NULL; /* error condition */
1393 return band->mhfs[idx];
1396 static void wlc_write_mhf(struct brcms_c_hw_info *wlc_hw, u16 *mhfs)
1400 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1404 for (idx = 0; idx < MHFMAX; idx++) {
1405 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1409 /* set the maccontrol register to desired reset state and
1410 * initialize the sw cache of the register
1412 static void wlc_mctrl_reset(struct brcms_c_hw_info *wlc_hw)
1414 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1415 wlc_hw->maccontrol = 0;
1416 wlc_hw->suspended_fifos = 0;
1417 wlc_hw->wake_override = 0;
1418 wlc_hw->mute_override = 0;
1419 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1422 /* set or clear maccontrol bits */
1423 void brcms_b_mctrl(struct brcms_c_hw_info *wlc_hw, u32 mask, u32 val)
1429 return; /* error condition */
1430 maccontrol = wlc_hw->maccontrol;
1431 new_maccontrol = (maccontrol & ~mask) | val;
1433 /* if the new maccontrol value is the same as the old, nothing to do */
1434 if (new_maccontrol == maccontrol)
1437 /* something changed, cache the new value */
1438 wlc_hw->maccontrol = new_maccontrol;
1440 /* write the new values with overrides applied */
1441 wlc_mctrl_write(wlc_hw);
1444 /* write the software state of maccontrol and overrides to the maccontrol register */
1445 static void wlc_mctrl_write(struct brcms_c_hw_info *wlc_hw)
1447 u32 maccontrol = wlc_hw->maccontrol;
1449 /* OR in the wake bit if overridden */
1450 if (wlc_hw->wake_override)
1451 maccontrol |= MCTL_WAKE;
1453 /* set AP and INFRA bits for mute if needed */
1454 if (wlc_hw->mute_override) {
1455 maccontrol &= ~(MCTL_AP);
1456 maccontrol |= MCTL_INFRA;
1459 W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1462 void wlc_ucode_wake_override_set(struct brcms_c_hw_info *wlc_hw,
1465 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1466 mboolset(wlc_hw->wake_override, override_bit);
1470 mboolset(wlc_hw->wake_override, override_bit);
1472 wlc_mctrl_write(wlc_hw);
1473 brcms_b_wait_for_wake(wlc_hw);
1478 void wlc_ucode_wake_override_clear(struct brcms_c_hw_info *wlc_hw,
1481 mboolclr(wlc_hw->wake_override, override_bit);
1483 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1486 wlc_mctrl_write(wlc_hw);
1491 /* When driver needs ucode to stop beaconing, it has to make sure that
1492 * MCTL_AP is clear and MCTL_INFRA is set
1493 * Mode MCTL_AP MCTL_INFRA
1495 * STA 0 1 <--- This will ensure no beacons
1498 static void wlc_ucode_mute_override_set(struct brcms_c_hw_info *wlc_hw)
1500 wlc_hw->mute_override = 1;
1502 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1503 * override, then there is no change to write
1505 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1508 wlc_mctrl_write(wlc_hw);
1513 /* Clear the override on AP and INFRA bits */
1514 static void wlc_ucode_mute_override_clear(struct brcms_c_hw_info *wlc_hw)
1516 if (wlc_hw->mute_override == 0)
1519 wlc_hw->mute_override = 0;
1521 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1522 * override, then there is no change to write
1524 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1527 wlc_mctrl_write(wlc_hw);
1531 * Write a MAC address to the given match reg offset in the RXE match engine.
1534 brcms_b_set_addrmatch(struct brcms_c_hw_info *wlc_hw, int match_reg_offset,
1542 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1545 regs = wlc_hw->regs;
1546 mac_l = addr[0] | (addr[1] << 8);
1547 mac_m = addr[2] | (addr[3] << 8);
1548 mac_h = addr[4] | (addr[5] << 8);
1550 /* enter the MAC addr into the RXE match registers */
1551 W_REG(®s->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1552 W_REG(®s->rcm_mat_data, mac_l);
1553 W_REG(®s->rcm_mat_data, mac_m);
1554 W_REG(®s->rcm_mat_data, mac_h);
1559 brcms_b_write_template_ram(struct brcms_c_hw_info *wlc_hw, int offset, int len,
1565 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1567 regs = wlc_hw->regs;
1568 W_REG(®s->tplatewrptr, offset);
1570 /* if MCTL_BIGEND bit set in mac control register,
1571 * the chip swaps data in fifo, as well as data in
1574 be_bit = (R_REG(®s->maccontrol) & MCTL_BIGEND) != 0;
1577 memcpy(&word, buf, sizeof(u32));
1580 word = cpu_to_be32(word);
1582 word = cpu_to_le32(word);
1584 W_REG(®s->tplatewrdata, word);
1586 buf = (u8 *) buf + sizeof(u32);
1591 void brcms_b_set_cwmin(struct brcms_c_hw_info *wlc_hw, u16 newmin)
1593 wlc_hw->band->CWmin = newmin;
1595 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1596 (void)R_REG(&wlc_hw->regs->objaddr);
1597 W_REG(&wlc_hw->regs->objdata, newmin);
1600 void brcms_b_set_cwmax(struct brcms_c_hw_info *wlc_hw, u16 newmax)
1602 wlc_hw->band->CWmax = newmax;
1604 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1605 (void)R_REG(&wlc_hw->regs->objaddr);
1606 W_REG(&wlc_hw->regs->objdata, newmax);
1609 void brcms_b_bw_set(struct brcms_c_hw_info *wlc_hw, u16 bw)
1613 /* request FAST clock if not on */
1614 fastclk = wlc_hw->forcefastclk;
1616 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1618 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1620 brcms_b_phy_reset(wlc_hw);
1621 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1623 /* restore the clk */
1625 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1629 wlc_write_hw_bcntemplate0(struct brcms_c_hw_info *wlc_hw, void *bcn, int len)
1631 d11regs_t *regs = wlc_hw->regs;
1633 brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1635 /* write beacon length to SCR */
1636 brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1637 /* mark beacon0 valid */
1638 OR_REG(®s->maccommand, MCMD_BCN0VLD);
1642 wlc_write_hw_bcntemplate1(struct brcms_c_hw_info *wlc_hw, void *bcn, int len)
1644 d11regs_t *regs = wlc_hw->regs;
1646 brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1648 /* write beacon length to SCR */
1649 brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1650 /* mark beacon1 valid */
1651 OR_REG(®s->maccommand, MCMD_BCN1VLD);
1654 /* mac is assumed to be suspended at this point */
1656 brcms_b_write_hw_bcntemplates(struct brcms_c_hw_info *wlc_hw, void *bcn,
1659 d11regs_t *regs = wlc_hw->regs;
1662 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1663 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1666 if (!(R_REG(®s->maccommand) & MCMD_BCN0VLD))
1667 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1670 (R_REG(®s->maccommand) & MCMD_BCN1VLD))
1671 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1675 static void WLBANDINITFN(brcms_b_upd_synthpu) (struct brcms_c_hw_info *wlc_hw)
1678 struct brcms_c_info *wlc = wlc_hw->wlc;
1679 /* update SYNTHPU_DLY */
1681 if (WLCISLCNPHY(wlc->band)) {
1682 v = SYNTHPU_DLY_LPPHY_US;
1683 } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1684 v = SYNTHPU_DLY_NPHY_US;
1686 v = SYNTHPU_DLY_BPHY_US;
1689 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1692 /* band-specific init */
1694 WLBANDINITFN(brcms_b_bsinit) (struct brcms_c_info *wlc, chanspec_t chanspec)
1696 struct brcms_c_hw_info *wlc_hw = wlc->hw;
1698 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1699 wlc_hw->band->bandunit);
1701 wlc_ucode_bsinit(wlc_hw);
1703 wlc_phy_init(wlc_hw->band->pi, chanspec);
1705 wlc_ucode_txant_set(wlc_hw);
1707 /* cwmin is band-specific, update hardware with value for current band */
1708 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1709 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1711 brcms_b_update_slot_timing(wlc_hw,
1712 BAND_5G(wlc_hw->band->
1713 bandtype) ? true : wlc_hw->
1716 /* write phytype and phyvers */
1717 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1718 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1720 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1721 wlc_upd_ofdm_pctl1_table(wlc_hw);
1723 brcms_b_upd_synthpu(wlc_hw);
1726 static void brcms_b_core_phy_clk(struct brcms_c_hw_info *wlc_hw, bool clk)
1728 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1730 wlc_hw->phyclk = clk;
1732 if (OFF == clk) { /* clear gmode bit, put phy into reset */
1734 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1735 (SICF_PRST | SICF_FGC));
1737 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1740 } else { /* take phy out of reset */
1742 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1744 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1750 /* Perform a soft reset of the PHY PLL */
1751 void brcms_b_core_phypll_reset(struct brcms_c_hw_info *wlc_hw)
1753 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1755 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1756 offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1758 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1759 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1761 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1762 offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1764 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1765 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1769 /* light way to turn on phy clock without reset for NPHY only
1770 * refer to brcms_b_core_phy_clk for full version
1772 void brcms_b_phyclk_fgc(struct brcms_c_hw_info *wlc_hw, bool clk)
1774 /* support(necessary for NPHY and HYPHY) only */
1775 if (!WLCISNPHY(wlc_hw->band))
1779 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1781 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1785 void brcms_b_macphyclk_set(struct brcms_c_hw_info *wlc_hw, bool clk)
1788 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1790 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1793 void brcms_b_phy_reset(struct brcms_c_hw_info *wlc_hw)
1795 wlc_phy_t *pih = wlc_hw->band->pi;
1797 bool phy_in_reset = false;
1799 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1804 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1806 /* Specific reset sequence required for NPHY rev 3 and 4 */
1807 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1808 NREV_LE(wlc_hw->band->phyrev, 4)) {
1809 /* Set the PHY bandwidth */
1810 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1814 /* Perform a soft reset of the PHY PLL */
1815 brcms_b_core_phypll_reset(wlc_hw);
1818 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1819 (SICF_PRST | SICF_PCLKE));
1820 phy_in_reset = true;
1823 ai_core_cflags(wlc_hw->sih,
1824 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1825 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1829 brcms_b_core_phy_clk(wlc_hw, ON);
1832 wlc_phy_anacore(pih, ON);
1835 /* switch to and initialize new band */
1837 WLBANDINITFN(brcms_b_setband) (struct brcms_c_hw_info *wlc_hw, uint bandunit,
1838 chanspec_t chanspec) {
1839 struct brcms_c_info *wlc = wlc_hw->wlc;
1842 /* Enable the d11 core before accessing it */
1843 if (!ai_iscoreup(wlc_hw->sih)) {
1844 ai_core_reset(wlc_hw->sih, 0, 0);
1845 wlc_mctrl_reset(wlc_hw);
1848 macintmask = wlc_setband_inact(wlc, bandunit);
1853 brcms_b_core_phy_clk(wlc_hw, ON);
1855 /* band-specific initializations */
1856 brcms_b_bsinit(wlc, chanspec);
1859 * If there are any pending software interrupt bits,
1860 * then replace these with a harmless nonzero value
1861 * so brcms_c_dpc() will re-enable interrupts when done.
1863 if (wlc->macintstatus)
1864 wlc->macintstatus = MI_DMAINT;
1866 /* restore macintmask */
1867 brcms_intrsrestore(wlc->wl, macintmask);
1869 /* ucode should still be suspended.. */
1870 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1873 /* low-level band switch utility routine */
1874 void WLBANDINITFN(brcms_c_setxband) (struct brcms_c_hw_info *wlc_hw,
1877 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1880 wlc_hw->band = wlc_hw->bandstate[bandunit];
1882 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1883 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1885 /* set gmode core flag */
1886 if (wlc_hw->sbclk && !wlc_hw->noreset) {
1887 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1888 ((bandunit == 0) ? SICF_GMODE : 0));
1892 static bool wlc_isgoodchip(struct brcms_c_hw_info *wlc_hw)
1895 /* reject unsupported corerev */
1896 if (!VALID_COREREV(wlc_hw->corerev)) {
1897 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1905 static bool wlc_validboardtype(struct brcms_c_hw_info *wlc_hw)
1907 bool goodboard = true;
1908 uint boardrev = wlc_hw->boardrev;
1912 else if (boardrev > 0xff) {
1913 uint brt = (boardrev & 0xf000) >> 12;
1914 uint b0 = (boardrev & 0xf00) >> 8;
1915 uint b1 = (boardrev & 0xf0) >> 4;
1916 uint b2 = boardrev & 0xf;
1918 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1923 if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1929 static char *wlc_get_macaddr(struct brcms_c_hw_info *wlc_hw)
1931 const char *varname = "macaddr";
1934 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1935 macaddr = getvar(wlc_hw->vars, varname);
1936 if (macaddr != NULL)
1939 if (NBANDS_HW(wlc_hw) > 1)
1940 varname = "et1macaddr";
1942 varname = "il0macaddr";
1944 macaddr = getvar(wlc_hw->vars, varname);
1945 if (macaddr == NULL) {
1946 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1947 "getvar(%s) not found\n", wlc_hw->unit, varname);
1954 * Return true if radio is disabled, otherwise false.
1955 * hw radio disable signal is an external pin, users activate it asynchronously
1956 * this function could be called when driver is down and w/o clock
1957 * it operates on different registers depending on corerev and boardflag.
1959 bool brcms_b_radio_read_hwdisabled(struct brcms_c_hw_info *wlc_hw)
1962 u32 resetbits = 0, flags = 0;
1964 xtal = wlc_hw->sbclk;
1966 brcms_b_xtal(wlc_hw, ON);
1968 /* may need to take core out of reset first */
1972 * mac no longer enables phyclk automatically when driver
1973 * accesses phyreg throughput mac. This can be skipped since
1974 * only mac reg is accessed below
1976 flags |= SICF_PCLKE;
1978 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1979 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
1980 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
1981 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
1983 (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
1985 ai_core_reset(wlc_hw->sih, flags, resetbits);
1986 wlc_mctrl_reset(wlc_hw);
1989 v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
1991 /* put core back into reset */
1993 ai_core_disable(wlc_hw->sih, 0);
1996 brcms_b_xtal(wlc_hw, OFF);
2001 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2002 void brcms_b_hw_up(struct brcms_c_hw_info *wlc_hw)
2004 if (wlc_hw->wlc->pub->hw_up)
2007 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2010 * Enable pll and xtal, initialize the power control registers,
2011 * and force fastclock for the remainder of brcms_c_up().
2013 brcms_b_xtal(wlc_hw, ON);
2014 ai_clkctl_init(wlc_hw->sih);
2015 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2017 if (wlc_hw->sih->bustype == PCI_BUS) {
2018 ai_pci_fixcfg(wlc_hw->sih);
2020 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2021 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2022 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2023 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2025 (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2029 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2030 wlc_phy_por_inform(wlc_hw->band->pi);
2032 wlc_hw->ucode_loaded = false;
2033 wlc_hw->wlc->pub->hw_up = true;
2035 if ((wlc_hw->boardflags & BFL_FEM)
2036 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2038 (wlc_hw->boardrev >= 0x1250
2039 && (wlc_hw->boardflags & BFL_FEM_BT)))
2040 ai_epa_4313war(wlc_hw->sih);
2044 static bool wlc_dma_rxreset(struct brcms_c_hw_info *wlc_hw, uint fifo)
2046 struct dma_pub *di = wlc_hw->di[fifo];
2047 return dma_rxreset(di);
2051 * ensure fask clock during reset
2053 * reset d11(out of reset)
2054 * reset phy(out of reset)
2055 * clear software macintstatus for fresh new start
2056 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2058 void brcms_b_corereset(struct brcms_c_hw_info *wlc_hw, u32 flags)
2065 if (flags == WLC_USE_COREFLAGS)
2066 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2068 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2070 regs = wlc_hw->regs;
2072 /* request FAST clock if not on */
2073 fastclk = wlc_hw->forcefastclk;
2075 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2077 /* reset the dma engines except first time thru */
2078 if (ai_iscoreup(wlc_hw->sih)) {
2079 for (i = 0; i < NFIFO; i++)
2080 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2081 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2082 "dma_txreset[%d]: cannot stop dma\n",
2083 wlc_hw->unit, __func__, i);
2086 if ((wlc_hw->di[RX_FIFO])
2087 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2088 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2089 "[%d]: cannot stop dma\n",
2090 wlc_hw->unit, __func__, RX_FIFO);
2093 /* if noreset, just stop the psm and return */
2094 if (wlc_hw->noreset) {
2095 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2096 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2101 * mac no longer enables phyclk automatically when driver accesses
2102 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2103 * band->pi is invalid. need to enable PHY CLK
2105 flags |= SICF_PCLKE;
2108 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2109 * is cleared by the core_reset. have to re-request it.
2110 * This adds some delay and we can optimize it by also requesting fastclk through
2111 * chipcommon during this period if necessary. But that has to work coordinate
2112 * with other driver like mips/arm since they may touch chipcommon as well.
2114 wlc_hw->clk = false;
2115 ai_core_reset(wlc_hw->sih, flags, resetbits);
2117 if (wlc_hw->band && wlc_hw->band->pi)
2118 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2120 wlc_mctrl_reset(wlc_hw);
2122 if (PMUCTL_ENAB(wlc_hw->sih))
2123 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2125 brcms_b_phy_reset(wlc_hw);
2127 /* turn on PHY_PLL */
2128 brcms_b_core_phypll_ctl(wlc_hw, true);
2130 /* clear sw intstatus */
2131 wlc_hw->wlc->macintstatus = 0;
2133 /* restore the clk setting */
2135 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2138 /* txfifo sizes needs to be modified(increased) since the newer cores
2141 static void brcms_b_corerev_fifofixup(struct brcms_c_hw_info *wlc_hw)
2143 d11regs_t *regs = wlc_hw->regs;
2145 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2146 u16 txfifo_def, txfifo_def1;
2149 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2150 txfifo_startblk = TXFIFO_START_BLK;
2152 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2153 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2155 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2156 txfifo_def = (txfifo_startblk & 0xff) |
2157 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2158 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2160 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2162 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2164 W_REG(®s->xmtfifocmd, txfifo_cmd);
2165 W_REG(®s->xmtfifodef, txfifo_def);
2166 W_REG(®s->xmtfifodef1, txfifo_def1);
2168 W_REG(®s->xmtfifocmd, txfifo_cmd);
2170 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2173 * need to propagate to shm location to be in sync since ucode/hw won't
2176 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2177 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2178 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2179 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2180 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2181 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2182 xmtfifo_sz[TX_AC_BK_FIFO]));
2183 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2184 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2185 xmtfifo_sz[TX_BCMC_FIFO]));
2190 * download ucode/PCM
2191 * let ucode run to suspended
2192 * download ucode inits
2193 * config other core registers
2196 static void brcms_b_coreinit(struct brcms_c_info *wlc)
2198 struct brcms_c_hw_info *wlc_hw = wlc->hw;
2203 bool fifosz_fixup = false;
2206 struct wiphy *wiphy = wlc->wiphy;
2208 regs = wlc_hw->regs;
2210 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2213 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2215 wlc_ucode_download(wlc_hw);
2217 * FIFOSZ fixup. driver wants to controls the fifo allocation.
2219 fifosz_fixup = true;
2221 /* let the PSM run to the suspended state, set mode to BSS STA */
2222 W_REG(®s->macintstatus, -1);
2223 brcms_b_mctrl(wlc_hw, ~0,
2224 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2226 /* wait for ucode to self-suspend after auto-init */
2227 SPINWAIT(((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0),
2229 if ((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0)
2230 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2231 "suspend!\n", wlc_hw->unit);
2235 sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2237 if (D11REV_IS(wlc_hw->corerev, 23)) {
2238 if (WLCISNPHY(wlc_hw->band))
2239 wlc_write_inits(wlc_hw, d11n0initvals16);
2241 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2242 " %d\n", __func__, wlc_hw->unit,
2244 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2245 if (WLCISLCNPHY(wlc_hw->band)) {
2246 wlc_write_inits(wlc_hw, d11lcn0initvals24);
2248 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2249 " %d\n", __func__, wlc_hw->unit,
2253 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2254 __func__, wlc_hw->unit, wlc_hw->corerev);
2257 /* For old ucode, txfifo sizes needs to be modified(increased) */
2258 if (fifosz_fixup == true) {
2259 brcms_b_corerev_fifofixup(wlc_hw);
2262 /* check txfifo allocations match between ucode and driver */
2263 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
2264 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2268 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
2269 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2273 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
2274 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2275 buf[TX_AC_BK_FIFO] &= 0xff;
2276 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2280 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2284 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
2285 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2286 buf[TX_BCMC_FIFO] &= 0xff;
2287 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2291 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2296 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2297 " driver size %d index %d\n", buf[i],
2298 wlc_hw->xmtfifo_sz[i], i);
2301 /* make sure we can still talk to the mac */
2302 WARN_ON(R_REG(®s->maccontrol) == 0xffffffff);
2304 /* band-specific inits done by wlc_bsinit() */
2306 /* Set up frame burst size and antenna swap threshold init values */
2307 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2308 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2310 /* enable one rx interrupt per received frame */
2311 W_REG(®s->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2313 /* set the station mode (BSS STA) */
2314 brcms_b_mctrl(wlc_hw,
2315 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2316 (MCTL_INFRA | MCTL_DISCARD_PMQ));
2318 /* set up Beacon interval */
2319 bcnint_us = 0x8000 << 10;
2320 W_REG(®s->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2321 W_REG(®s->tsf_cfpstart, bcnint_us);
2322 W_REG(®s->macintstatus, MI_GP1);
2324 /* write interrupt mask */
2325 W_REG(®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2327 /* allow the MAC to control the PHY clock (dynamic on/off) */
2328 brcms_b_macphyclk_set(wlc_hw, ON);
2330 /* program dynamic clock control fast powerup delay register */
2331 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2332 W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2334 /* tell the ucode the corerev */
2335 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2337 /* tell the ucode MAC capabilities */
2338 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
2339 (u16) (wlc_hw->machwcap & 0xffff));
2340 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
2342 machwcap >> 16) & 0xffff));
2344 /* write retry limits to SCR, this done after PSM init */
2345 W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2346 (void)R_REG(®s->objaddr);
2347 W_REG(®s->objdata, wlc_hw->SRL);
2348 W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2349 (void)R_REG(®s->objaddr);
2350 W_REG(®s->objdata, wlc_hw->LRL);
2352 /* write rate fallback retry limits */
2353 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2354 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2356 AND_REG(®s->ifs_ctl, 0x0FFF);
2357 W_REG(®s->ifs_aifsn, EDCF_AIFSN_MIN);
2359 /* dma initializations */
2360 wlc->txpend16165war = 0;
2362 /* init the tx dma engines */
2363 for (i = 0; i < NFIFO; i++) {
2365 dma_txinit(wlc_hw->di[i]);
2368 /* init the rx dma engine(s) and post receive buffers */
2369 dma_rxinit(wlc_hw->di[RX_FIFO]);
2370 dma_rxfill(wlc_hw->di[RX_FIFO]);
2373 /* This function is used for changing the tsf frac register
2374 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2375 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2376 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2377 * HTPHY Formula is 2^26/freq(MHz) e.g.
2378 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2379 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2380 * For spuron: 123MHz -> 2^26/123 = 545600.5
2381 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2382 * For spur off: 120MHz -> 2^26/120 = 559240.5
2383 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2386 void brcms_b_switch_macfreq(struct brcms_c_hw_info *wlc_hw, u8 spurmode)
2389 regs = wlc_hw->regs;
2391 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2392 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2393 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2394 W_REG(®s->tsf_clk_frac_l, 0x2082);
2395 W_REG(®s->tsf_clk_frac_h, 0x8);
2396 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2397 W_REG(®s->tsf_clk_frac_l, 0x5341);
2398 W_REG(®s->tsf_clk_frac_h, 0x8);
2399 } else { /* 120Mhz */
2400 W_REG(®s->tsf_clk_frac_l, 0x8889);
2401 W_REG(®s->tsf_clk_frac_h, 0x8);
2403 } else if (WLCISLCNPHY(wlc_hw->band)) {
2404 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2405 W_REG(®s->tsf_clk_frac_l, 0x7CE0);
2406 W_REG(®s->tsf_clk_frac_h, 0xC);
2407 } else { /* 80Mhz */
2408 W_REG(®s->tsf_clk_frac_l, 0xCCCD);
2409 W_REG(®s->tsf_clk_frac_h, 0xC);
2414 /* Initialize GPIOs that are controlled by D11 core */
2415 static void wlc_gpio_init(struct brcms_c_info *wlc)
2417 struct brcms_c_hw_info *wlc_hw = wlc->hw;
2421 regs = wlc_hw->regs;
2423 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2424 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2427 * Common GPIO setup:
2428 * G0 = LED 0 = WLAN Activity
2429 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2430 * G2 = LED 2 = WLAN 5 GHz Radio State
2431 * G4 = radio disable input (HI enabled, LO disabled)
2436 /* Allocate GPIOs for mimo antenna diversity feature */
2437 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2438 /* Enable antenna diversity, use 2x3 mode */
2439 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2440 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2441 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2442 MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2444 /* init superswitch control */
2445 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2447 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2448 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2450 * The board itself is powered by these GPIOs
2451 * (when not sending pattern) so set them high
2453 OR_REG(®s->psm_gpio_oe,
2454 (BOARD_GPIO_12 | BOARD_GPIO_13));
2455 OR_REG(®s->psm_gpio_out,
2456 (BOARD_GPIO_12 | BOARD_GPIO_13));
2458 /* Enable antenna diversity, use 2x4 mode */
2459 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2460 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2461 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2464 /* Configure the desired clock to be 4Mhz */
2465 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2466 ANTSEL_CLKDIV_4MHZ);
2469 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2470 if (wlc_hw->boardflags & BFL_PACTRL)
2471 gm |= gc |= BOARD_GPIO_PACTRL;
2473 /* apply to gpiocontrol register */
2474 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2477 static void wlc_ucode_download(struct brcms_c_hw_info *wlc_hw)
2479 struct brcms_c_info *wlc;
2482 if (wlc_hw->ucode_loaded)
2485 if (D11REV_IS(wlc_hw->corerev, 23)) {
2486 if (WLCISNPHY(wlc_hw->band)) {
2487 wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2489 wlc_hw->ucode_loaded = true;
2491 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2493 __func__, wlc_hw->unit, wlc_hw->corerev);
2494 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2495 if (WLCISLCNPHY(wlc_hw->band)) {
2496 wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2498 wlc_hw->ucode_loaded = true;
2500 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2502 __func__, wlc_hw->unit, wlc_hw->corerev);
2507 static void wlc_ucode_write(struct brcms_c_hw_info *wlc_hw, const u32 ucode[],
2508 const uint nbytes) {
2509 d11regs_t *regs = wlc_hw->regs;
2513 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2515 count = (nbytes / sizeof(u32));
2517 W_REG(®s->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2518 (void)R_REG(®s->objaddr);
2519 for (i = 0; i < count; i++)
2520 W_REG(®s->objdata, ucode[i]);
2523 static void wlc_write_inits(struct brcms_c_hw_info *wlc_hw,
2524 const struct d11init *inits)
2529 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2531 base = (volatile u8 *)wlc_hw->regs;
2533 for (i = 0; inits[i].addr != 0xffff; i++) {
2534 if (inits[i].size == 2)
2535 W_REG((u16 *)(base + inits[i].addr),
2537 else if (inits[i].size == 4)
2538 W_REG((u32 *)(base + inits[i].addr),
2543 static void wlc_ucode_txant_set(struct brcms_c_hw_info *wlc_hw)
2546 u16 phytxant = wlc_hw->bmac_phytxant;
2547 u16 mask = PHY_TXC_ANT_MASK;
2549 /* set the Probe Response frame phy control word */
2550 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2551 phyctl = (phyctl & ~mask) | phytxant;
2552 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2554 /* set the Response (ACK/CTS) frame phy control word */
2555 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
2556 phyctl = (phyctl & ~mask) | phytxant;
2557 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2560 void brcms_b_txant_set(struct brcms_c_hw_info *wlc_hw, u16 phytxant)
2562 /* update sw state */
2563 wlc_hw->bmac_phytxant = phytxant;
2565 /* push to ucode if up */
2568 wlc_ucode_txant_set(wlc_hw);
2572 u16 brcms_b_get_txant(struct brcms_c_hw_info *wlc_hw)
2574 return (u16) wlc_hw->wlc->stf->txant;
2577 void brcms_b_antsel_type_set(struct brcms_c_hw_info *wlc_hw, u8 antsel_type)
2579 wlc_hw->antsel_type = antsel_type;
2581 /* Update the antsel type for phy module to use */
2582 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2585 void brcms_b_fifoerrors(struct brcms_c_hw_info *wlc_hw)
2589 uint intstatus, idx;
2590 d11regs_t *regs = wlc_hw->regs;
2591 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2593 unit = wlc_hw->unit;
2595 for (idx = 0; idx < NFIFO; idx++) {
2596 /* read intstatus register and ignore any non-error bits */
2598 R_REG(®s->intctrlregs[idx].intstatus) & I_ERRORS;
2602 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2603 unit, idx, intstatus);
2605 if (intstatus & I_RO) {
2606 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2607 "overflow\n", unit, idx);
2611 if (intstatus & I_PC) {
2612 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2617 if (intstatus & I_PD) {
2618 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2623 if (intstatus & I_DE) {
2624 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2625 "error\n", unit, idx);
2629 if (intstatus & I_RU) {
2630 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2631 "underflow\n", idx, unit);
2634 if (intstatus & I_XU) {
2635 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2636 "underflow\n", idx, unit);
2641 brcms_c_fatal_error(wlc_hw->wlc); /* big hammer */
2644 W_REG(®s->intctrlregs[idx].intstatus,
2649 void brcms_c_intrson(struct brcms_c_info *wlc)
2651 struct brcms_c_hw_info *wlc_hw = wlc->hw;
2652 wlc->macintmask = wlc->defmacintmask;
2653 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2656 /* callback for siutils.c, which has only wlc handler, no wl
2657 * they both check up, not only because there is no need to off/restore d11 interrupt
2658 * but also because per-port code may require sync with valid interrupt.
2661 static u32 wlc_wlintrsoff(struct brcms_c_info *wlc)
2666 return brcms_intrsoff(wlc->wl);
2669 static void wlc_wlintrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2674 brcms_intrsrestore(wlc->wl, macintmask);
2677 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2679 struct brcms_c_hw_info *wlc_hw = wlc->hw;
2685 macintmask = wlc->macintmask; /* isr can still happen */
2687 W_REG(&wlc_hw->regs->macintmask, 0);
2688 (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2689 udelay(1); /* ensure int line is no longer driven */
2690 wlc->macintmask = 0;
2692 /* return previous macintmask; resolve race between us and our isr */
2693 return wlc->macintstatus ? 0 : macintmask;
2696 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2698 struct brcms_c_hw_info *wlc_hw = wlc->hw;
2702 wlc->macintmask = macintmask;
2703 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2706 static void brcms_b_mute(struct brcms_c_hw_info *wlc_hw, bool on, mbool flags)
2708 u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2711 /* suspend tx fifos */
2712 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2713 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2714 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2715 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2717 /* zero the address match register so we do not send ACKs */
2718 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2721 /* resume tx fifos */
2722 if (!wlc_hw->wlc->tx_suspended) {
2723 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2725 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2726 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2727 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2729 /* Restore address */
2730 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2734 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2737 wlc_ucode_mute_override_set(wlc_hw);
2739 wlc_ucode_mute_override_clear(wlc_hw);
2742 int brcms_b_xmtfifo_sz_get(struct brcms_c_hw_info *wlc_hw, uint fifo,
2748 *blocks = wlc_hw->xmtfifo_sz[fifo];
2753 /* brcms_b_tx_fifo_suspended:
2754 * Check the MAC's tx suspend status for a tx fifo.
2756 * When the MAC acknowledges a tx suspend, it indicates that no more
2757 * packets will be transmitted out the radio. This is independent of
2758 * DMA channel suspension---the DMA may have finished suspending, or may still
2759 * be pulling data into a tx fifo, by the time the MAC acks the suspend
2762 static bool brcms_b_tx_fifo_suspended(struct brcms_c_hw_info *wlc_hw,
2765 /* check that a suspend has been requested and is no longer pending */
2768 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2769 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2770 * chnstatus register.
2771 * The tx fifo suspend completion is independent of the DMA suspend completion and
2772 * may be acked before or after the DMA is suspended.
2774 if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2775 (R_REG(&wlc_hw->regs->chnstatus) &
2776 (1 << tx_fifo)) == 0)
2782 static void brcms_b_tx_fifo_suspend(struct brcms_c_hw_info *wlc_hw,
2785 u8 fifo = 1 << tx_fifo;
2787 /* Two clients of this code, 11h Quiet period and scanning. */
2789 /* only suspend if not already suspended */
2790 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2793 /* force the core awake only if not already */
2794 if (wlc_hw->suspended_fifos == 0)
2795 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2797 wlc_hw->suspended_fifos |= fifo;
2799 if (wlc_hw->di[tx_fifo]) {
2800 /* Suspending AMPDU transmissions in the middle can cause underflow
2801 * which may result in mismatch between ucode and driver
2802 * so suspend the mac before suspending the FIFO
2804 if (WLC_PHY_11N_CAP(wlc_hw->band))
2805 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2807 dma_txsuspend(wlc_hw->di[tx_fifo]);
2809 if (WLC_PHY_11N_CAP(wlc_hw->band))
2810 brcms_c_enable_mac(wlc_hw->wlc);
2814 static void brcms_b_tx_fifo_resume(struct brcms_c_hw_info *wlc_hw,
2817 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2818 * but need to be done here for PIO otherwise the watchdog will catch
2819 * the inconsistency and fire
2821 /* Two clients of this code, 11h Quiet period and scanning. */
2822 if (wlc_hw->di[tx_fifo])
2823 dma_txresume(wlc_hw->di[tx_fifo]);
2825 /* allow core to sleep again */
2826 if (wlc_hw->suspended_fifos == 0)
2829 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2830 if (wlc_hw->suspended_fifos == 0)
2831 wlc_ucode_wake_override_clear(wlc_hw,
2832 WLC_WAKE_OVERRIDE_TXFIFO);
2837 * Read and clear macintmask and macintstatus and intstatus registers.
2838 * This routine should be called with interrupts off
2840 * -1 if DEVICEREMOVED(wlc) evaluates to true;
2841 * 0 if the interrupt is not for us, or we are in some special cases;
2842 * device interrupt status bits otherwise.
2844 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2846 struct brcms_c_hw_info *wlc_hw = wlc->hw;
2847 d11regs_t *regs = wlc_hw->regs;
2850 /* macintstatus includes a DMA interrupt summary bit */
2851 macintstatus = R_REG(®s->macintstatus);
2853 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2856 /* detect cardbus removed, in power down(suspend) and in reset */
2857 if (DEVICEREMOVED(wlc))
2860 /* DEVICEREMOVED succeeds even when the core is still resetting,
2861 * handle that case here.
2863 if (macintstatus == 0xffffffff)
2866 /* defer unsolicited interrupts */
2867 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2870 if (macintstatus == 0)
2873 /* interrupts are already turned off for CFE build
2874 * Caution: For CFE Turning off the interrupts again has some undesired
2877 /* turn off the interrupts */
2878 W_REG(®s->macintmask, 0);
2879 (void)R_REG(®s->macintmask); /* sync readback */
2880 wlc->macintmask = 0;
2882 /* clear device interrupts */
2883 W_REG(®s->macintstatus, macintstatus);
2885 /* MI_DMAINT is indication of non-zero intstatus */
2886 if (macintstatus & MI_DMAINT) {
2888 * only fifo interrupt enabled is I_RI in
2889 * RX_FIFO. If MI_DMAINT is set, assume it
2890 * is set and clear the interrupt.
2892 W_REG(®s->intctrlregs[RX_FIFO].intstatus,
2896 return macintstatus;
2899 /* Update wlc->macintstatus and wlc->intstatus[]. */
2900 /* Return true if they are updated successfully. false otherwise */
2901 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2905 /* read and clear macintstatus and intstatus registers */
2906 macintstatus = wlc_intstatus(wlc, false);
2908 /* device is removed */
2909 if (macintstatus == 0xffffffff)
2912 /* update interrupt status in software */
2913 wlc->macintstatus |= macintstatus;
2919 * First-level interrupt processing.
2920 * Return true if this was our interrupt, false otherwise.
2921 * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2924 bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2926 struct brcms_c_hw_info *wlc_hw = wlc->hw;
2931 if (!wlc_hw->up || !wlc->macintmask)
2934 /* read and clear macintstatus and intstatus registers */
2935 macintstatus = wlc_intstatus(wlc, true);
2937 if (macintstatus == 0xffffffff)
2938 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2941 /* it is not for us */
2942 if (macintstatus == 0)
2947 /* save interrupt status bits */
2948 wlc->macintstatus = macintstatus;
2955 brcms_b_dotxstatus(struct brcms_c_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2957 /* discard intermediate indications for ucode with one legitimate case:
2958 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2959 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2960 * transmission count)
2962 if (!(txs->status & TX_STATUS_AMPDU)
2963 && (txs->status & TX_STATUS_INTERMEDIATE)) {
2967 return brcms_c_dotxstatus(wlc_hw->wlc, txs, s2);
2970 /* process tx completion events in BMAC
2971 * Return true if more tx status need to be processed. false otherwise.
2974 brcms_b_txstatus(struct brcms_c_hw_info *wlc_hw, bool bound, bool *fatal)
2976 bool morepending = false;
2977 struct brcms_c_info *wlc = wlc_hw->wlc;
2979 tx_status_t txstatus, *txs;
2983 * Param 'max_tx_num' indicates max. # tx status to process before
2986 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
2988 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2991 regs = wlc_hw->regs;
2993 && (s1 = R_REG(®s->frmtxstatus)) & TXS_V) {
2995 if (s1 == 0xffffffff) {
2996 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
2997 wlc_hw->unit, __func__);
3001 s2 = R_REG(®s->frmtxstatus2);
3003 txs->status = s1 & TXS_STATUS_MASK;
3004 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3005 txs->sequence = s2 & TXS_SEQ_MASK;
3006 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3007 txs->lasttxtime = 0;
3009 *fatal = brcms_b_dotxstatus(wlc_hw, txs, s2);
3011 /* !give others some time to run! */
3012 if (++n >= max_tx_num)
3019 if (n >= max_tx_num)
3022 if (!pktq_empty(&wlc->pkt_queue->q))
3023 brcms_c_send_q(wlc);
3028 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
3030 struct brcms_c_hw_info *wlc_hw = wlc->hw;
3031 d11regs_t *regs = wlc_hw->regs;
3033 struct wiphy *wiphy = wlc->wiphy;
3035 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3036 wlc_hw->band->bandunit);
3039 * Track overlapping suspend requests
3041 wlc_hw->mac_suspend_depth++;
3042 if (wlc_hw->mac_suspend_depth > 1)
3045 /* force the core awake */
3046 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3048 mc = R_REG(®s->maccontrol);
3050 if (mc == 0xffffffff) {
3051 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3053 brcms_down(wlc->wl);
3056 WARN_ON(mc & MCTL_PSM_JMP_0);
3057 WARN_ON(!(mc & MCTL_PSM_RUN));
3058 WARN_ON(!(mc & MCTL_EN_MAC));
3060 mi = R_REG(®s->macintstatus);
3061 if (mi == 0xffffffff) {
3062 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3064 brcms_down(wlc->wl);
3067 WARN_ON(mi & MI_MACSSPNDD);
3069 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3071 SPINWAIT(!(R_REG(®s->macintstatus) & MI_MACSSPNDD),
3072 WLC_MAX_MAC_SUSPEND);
3074 if (!(R_REG(®s->macintstatus) & MI_MACSSPNDD)) {
3075 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3076 " and MI_MACSSPNDD is still not on.\n",
3077 wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3078 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3079 "psm_brc 0x%04x\n", wlc_hw->unit,
3080 R_REG(®s->psmdebug),
3081 R_REG(®s->phydebug),
3082 R_REG(®s->psm_brc));
3085 mc = R_REG(®s->maccontrol);
3086 if (mc == 0xffffffff) {
3087 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3089 brcms_down(wlc->wl);
3092 WARN_ON(mc & MCTL_PSM_JMP_0);
3093 WARN_ON(!(mc & MCTL_PSM_RUN));
3094 WARN_ON(mc & MCTL_EN_MAC);
3097 void brcms_c_enable_mac(struct brcms_c_info *wlc)
3099 struct brcms_c_hw_info *wlc_hw = wlc->hw;
3100 d11regs_t *regs = wlc_hw->regs;
3103 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3104 wlc->band->bandunit);
3107 * Track overlapping suspend requests
3109 wlc_hw->mac_suspend_depth--;
3110 if (wlc_hw->mac_suspend_depth > 0)
3113 mc = R_REG(®s->maccontrol);
3114 WARN_ON(mc & MCTL_PSM_JMP_0);
3115 WARN_ON(mc & MCTL_EN_MAC);
3116 WARN_ON(!(mc & MCTL_PSM_RUN));
3118 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3119 W_REG(®s->macintstatus, MI_MACSSPNDD);
3121 mc = R_REG(®s->maccontrol);
3122 WARN_ON(mc & MCTL_PSM_JMP_0);
3123 WARN_ON(!(mc & MCTL_EN_MAC));
3124 WARN_ON(!(mc & MCTL_PSM_RUN));
3126 mi = R_REG(®s->macintstatus);
3127 WARN_ON(mi & MI_MACSSPNDD);
3129 wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3132 static void wlc_upd_ofdm_pctl1_table(struct brcms_c_hw_info *wlc_hw)
3136 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3137 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3143 if (!WLC_PHY_11N_CAP(wlc_hw->band))
3146 /* walk the phy rate table and update the entries */
3147 for (i = 0; i < ARRAY_SIZE(rates); i++) {
3150 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
3152 /* read the SHM Rate Table entry OFDM PCTL1 values */
3154 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3156 /* modify the value */
3157 pctl1 &= ~PHY_TXC1_MODE_MASK;
3158 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3160 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3161 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3166 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_c_hw_info *wlc_hw,
3171 struct plcp_signal_rate_lookup {
3175 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3176 const struct plcp_signal_rate_lookup rate_lookup[] = {
3179 {WLC_RATE_12M, 0xA},
3180 {WLC_RATE_18M, 0xE},
3181 {WLC_RATE_24M, 0x9},
3182 {WLC_RATE_36M, 0xD},
3183 {WLC_RATE_48M, 0x8},
3187 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3188 if (rate == rate_lookup[i].rate) {
3189 plcp_rate = rate_lookup[i].signal_rate;
3194 /* Find the SHM pointer to the rate table entry by looking in the
3197 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3200 void brcms_b_band_stf_ss_set(struct brcms_c_hw_info *wlc_hw, u8 stf_mode)
3202 wlc_hw->hw_stf_ss_opmode = stf_mode;
3205 wlc_upd_ofdm_pctl1_table(wlc_hw);
3209 brcms_b_read_tsf(struct brcms_c_hw_info *wlc_hw, u32 *tsf_l_ptr,
3212 d11regs_t *regs = wlc_hw->regs;
3214 /* read the tsf timer low, then high to get an atomic read */
3215 *tsf_l_ptr = R_REG(®s->tsf_timerlow);
3216 *tsf_h_ptr = R_REG(®s->tsf_timerhigh);
3221 static bool brcms_b_validate_chip_access(struct brcms_c_hw_info *wlc_hw)
3225 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3227 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3229 regs = wlc_hw->regs;
3231 /* Validate dchip register access */
3233 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3234 (void)R_REG(®s->objaddr);
3235 w = R_REG(®s->objdata);
3237 /* Can we write and read back a 32bit register? */
3238 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3239 (void)R_REG(®s->objaddr);
3240 W_REG(®s->objdata, (u32) 0xaa5555aa);
3242 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3243 (void)R_REG(®s->objaddr);
3244 val = R_REG(®s->objdata);
3245 if (val != (u32) 0xaa5555aa) {
3246 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3247 "expected 0xaa5555aa\n", wlc_hw->unit, val);
3251 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3252 (void)R_REG(®s->objaddr);
3253 W_REG(®s->objdata, (u32) 0x55aaaa55);
3255 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3256 (void)R_REG(®s->objaddr);
3257 val = R_REG(®s->objdata);
3258 if (val != (u32) 0x55aaaa55) {
3259 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3260 "expected 0x55aaaa55\n", wlc_hw->unit, val);
3264 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3265 (void)R_REG(®s->objaddr);
3266 W_REG(®s->objdata, w);
3268 /* clear CFPStart */
3269 W_REG(®s->tsf_cfpstart, 0);
3271 w = R_REG(®s->maccontrol);
3272 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3273 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3274 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3275 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3276 (MCTL_IHR_EN | MCTL_WAKE),
3277 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3284 #define PHYPLL_WAIT_US 100000
3286 void brcms_b_core_phypll_ctl(struct brcms_c_hw_info *wlc_hw, bool on)
3291 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3294 regs = wlc_hw->regs;
3297 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3298 OR_REG(®s->clk_ctl_st,
3299 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3300 CCS_ERSRC_REQ_PHYPLL));
3301 SPINWAIT((R_REG(®s->clk_ctl_st) &
3302 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3305 tmp = R_REG(®s->clk_ctl_st);
3306 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3307 (CCS_ERSRC_AVAIL_HT)) {
3308 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3309 " PLL failed\n", __func__);
3312 OR_REG(®s->clk_ctl_st,
3313 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3314 SPINWAIT((R_REG(®s->clk_ctl_st) &
3315 (CCS_ERSRC_AVAIL_D11PLL |
3316 CCS_ERSRC_AVAIL_PHYPLL)) !=
3317 (CCS_ERSRC_AVAIL_D11PLL |
3318 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3320 tmp = R_REG(®s->clk_ctl_st);
3322 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3324 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3325 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3326 "PHY PLL failed\n", __func__);
3330 /* Since the PLL may be shared, other cores can still be requesting it;
3331 * so we'll deassert the request but not wait for status to comply.
3333 AND_REG(®s->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3334 tmp = R_REG(®s->clk_ctl_st);
3338 void brcms_c_coredisable(struct brcms_c_hw_info *wlc_hw)
3342 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3344 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3349 if (wlc_hw->noreset)
3353 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3355 /* turn off analog core */
3356 wlc_phy_anacore(wlc_hw->band->pi, OFF);
3358 /* turn off PHYPLL to save power */
3359 brcms_b_core_phypll_ctl(wlc_hw, false);
3361 /* No need to set wlc->pub->radio_active = OFF
3362 * because this function needs down capability and
3363 * radio_active is designed for BCMNODOWN.
3366 /* remove gpio controls */
3367 if (wlc_hw->ucode_dbgsel)
3368 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3370 wlc_hw->clk = false;
3371 ai_core_disable(wlc_hw->sih, 0);
3372 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3375 /* power both the pll and external oscillator on/off */
3376 static void brcms_b_xtal(struct brcms_c_hw_info *wlc_hw, bool want)
3378 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3380 /* dont power down if plldown is false or we must poll hw radio disable */
3381 if (!want && wlc_hw->pllreq)
3385 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3387 wlc_hw->sbclk = want;
3388 if (!wlc_hw->sbclk) {
3389 wlc_hw->clk = false;
3390 if (wlc_hw->band && wlc_hw->band->pi)
3391 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3395 static void wlc_flushqueues(struct brcms_c_info *wlc)
3397 struct brcms_c_hw_info *wlc_hw = wlc->hw;
3400 wlc->txpend16165war = 0;
3402 /* free any posted tx packets */
3403 for (i = 0; i < NFIFO; i++)
3404 if (wlc_hw->di[i]) {
3405 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
3406 TXPKTPENDCLR(wlc, i);
3407 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3410 /* free any posted rx packets */
3411 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3414 u16 brcms_b_read_shm(struct brcms_c_hw_info *wlc_hw, uint offset)
3416 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3419 void brcms_b_write_shm(struct brcms_c_hw_info *wlc_hw, uint offset, u16 v)
3421 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3425 brcms_b_read_objmem(struct brcms_c_hw_info *wlc_hw, uint offset, u32 sel)
3427 d11regs_t *regs = wlc_hw->regs;
3428 volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
3429 volatile u16 *objdata_hi = objdata_lo + 1;
3432 W_REG(®s->objaddr, sel | (offset >> 2));
3433 (void)R_REG(®s->objaddr);
3435 v = R_REG(objdata_hi);
3437 v = R_REG(objdata_lo);
3444 brcms_b_write_objmem(struct brcms_c_hw_info *wlc_hw, uint offset, u16 v,
3447 d11regs_t *regs = wlc_hw->regs;
3448 volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
3449 volatile u16 *objdata_hi = objdata_lo + 1;
3451 W_REG(®s->objaddr, sel | (offset >> 2));
3452 (void)R_REG(®s->objaddr);
3454 W_REG(objdata_hi, v);
3456 W_REG(objdata_lo, v);
3460 /* Copy a buffer to shared memory of specified type .
3461 * SHM 'offset' needs to be an even address and
3462 * Buffer length 'len' must be an even number of bytes
3463 * 'sel' selects the type of memory
3466 brcms_b_copyto_objmem(struct brcms_c_hw_info *wlc_hw, uint offset,
3467 const void *buf, int len, u32 sel)
3470 const u8 *p = (const u8 *)buf;
3473 if (len <= 0 || (offset & 1) || (len & 1))
3476 for (i = 0; i < len; i += 2) {
3477 v = p[i] | (p[i + 1] << 8);
3478 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
3482 /* Copy a piece of shared memory of specified type to a buffer .
3483 * SHM 'offset' needs to be an even address and
3484 * Buffer length 'len' must be an even number of bytes
3485 * 'sel' selects the type of memory
3488 brcms_b_copyfrom_objmem(struct brcms_c_hw_info *wlc_hw, uint offset, void *buf,
3495 if (len <= 0 || (offset & 1) || (len & 1))
3498 for (i = 0; i < len; i += 2) {
3499 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
3501 p[i + 1] = (v >> 8) & 0xFF;
3505 void brcms_b_copyfrom_vars(struct brcms_c_hw_info *wlc_hw, char **buf,
3508 BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3511 *buf = wlc_hw->vars;
3512 *len = wlc_hw->vars_size;
3515 void brcms_b_retrylimit_upd(struct brcms_c_hw_info *wlc_hw, u16 SRL, u16 LRL)
3520 /* write retry limit to SCR, shouldn't need to suspend */
3522 W_REG(&wlc_hw->regs->objaddr,
3523 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3524 (void)R_REG(&wlc_hw->regs->objaddr);
3525 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3526 W_REG(&wlc_hw->regs->objaddr,
3527 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3528 (void)R_REG(&wlc_hw->regs->objaddr);
3529 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3533 void brcms_b_pllreq(struct brcms_c_hw_info *wlc_hw, bool set, mbool req_bit)
3536 if (mboolisset(wlc_hw->pllreq, req_bit))
3539 mboolset(wlc_hw->pllreq, req_bit);
3541 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3542 if (!wlc_hw->sbclk) {
3543 brcms_b_xtal(wlc_hw, ON);
3547 if (!mboolisset(wlc_hw->pllreq, req_bit))
3550 mboolclr(wlc_hw->pllreq, req_bit);
3552 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3553 if (wlc_hw->sbclk) {
3554 brcms_b_xtal(wlc_hw, OFF);
3562 u16 brcms_b_rate_shm_offset(struct brcms_c_hw_info *wlc_hw, u8 rate)
3567 /* get the phy specific rate encoding for the PLCP SIGNAL field */
3568 /* XXX4321 fixup needed ? */
3570 table_ptr = M_RT_DIRMAP_A;
3572 table_ptr = M_RT_DIRMAP_B;
3574 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3575 * the index into the rate table.
3577 phy_rate = rate_info[rate] & WLC_RATE_MASK;
3578 index = phy_rate & 0xf;
3580 /* Find the SHM pointer to the rate table entry by looking in the
3583 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
3586 void brcms_b_antsel_set(struct brcms_c_hw_info *wlc_hw, u32 antsel_avail)
3588 wlc_hw->antsel_avail = antsel_avail;