drivers/staging/brcm80211/brcmsmac/bottom_mac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23
  24 #include <defs.h>
  25 #include <brcm_hw_ids.h>
  26 #include <brcmu_wifi.h>
  27 #include <aiutils.h>
  28 #include "srom.h"
  29 #include "otp.h"
  30 #include <brcmu_utils.h>
  31 #include <chipcommon.h>
  32 #include <nicpci.h>
  33 #include "dma.h"
  34
  35 #include "types.h"
  36 #include "pmu.h"
  37 #include "d11.h"
  38 #include "rate.h"
  39 #include "scb.h"
  40 #include "pub.h"
  41 #include "phy/phy_hal.h"
  42 #include "channel.h"
  43 #include "main.h"
  44 #include "ucode_loader.h"
  45 #include "antsel.h"
  46 #include "alloc.h"
  47 #include "bottom_mac.h"
  48 #include "mac80211_if.h"
  49
  50 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  51
  52 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  53 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  54 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  55 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  56
  57 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  58
  59 #ifndef BMAC_DUP_TO_REMOVE
  60 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  61
  62 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  63
  64 #endif                          /* BMAC_DUP_TO_REMOVE */
  65
  66 #define DMAREG(wlc_hw, direction, fifonum) \
  67         ((direction == DMA_TX) ? \
  68                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
  69                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
  70
  71 #define APHY_SLOT_TIME          9
  72 #define BPHY_SLOT_TIME          20
  73
  74 /*
  75  * The following table lists the buffer memory allocated to xmt fifos in HW.
  76  * the size is in units of 256bytes(one block), total size is HW dependent
  77  * ucode has default fifo partition, sw can overwrite if necessary
  78  *
  79  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  80  * the twiki is updated before making changes.
  81  */
  82
  83 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
  84
  85 static u16 xmtfifo_sz[][NFIFO] = {
  86         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  87         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  88         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  89         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  90         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  91 };
  92
  93 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
  94 static void wlc_coreinit(struct wlc_info *wlc);
  95
  96 /* used by wlc_wakeucode_init() */
  97 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
  98                             const struct d11init *inits);
  99 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 100                             const uint nbytes);
 101 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 102 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 103
 104 /* used by wlc_dpc() */
 105 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 106                                 u32 s2);
 107 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 108 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 109
 110 /* used by wlc_down() */
 111 static void wlc_flushqueues(struct wlc_info *wlc);
 112
 113 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 114 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 115 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 116 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
 117                                        uint tx_fifo);
 118 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 119 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 120
 121 /* Low Level Prototypes */
 122 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
 123 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
 124 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
 125 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 126                                    u32 sel);
 127 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 128                                   u16 v, u32 sel);
 129 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
 130 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 131 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 132 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 133 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 134 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 135 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
 136 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 137 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 138 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 139 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
 140 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 141 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 142 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 143 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 144 static void wlc_gpio_init(struct wlc_info *wlc);
 145 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 146                                       int len);
 147 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 148                                       int len);
 149 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 150 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 151 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 152                              chanspec_t chanspec);
 153 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 154                                         bool shortslot);
 155 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 156 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 157                                              u8 rate);
 158
 159 /* === Low Level functions === */
 160
 161 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 162 {
 163         wlc_hw->shortslot = shortslot;
 164
 165         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 166                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 167                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 168                 wlc_enable_mac(wlc_hw->wlc);
 169         }
 170 }
 171
 172 /*
 173  * Update the slot timing for standard 11b/g (20us slots)
 174  * or shortslot 11g (9us slots)
 175  * The PSM needs to be suspended for this call.
 176  */
 177 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 178                                         bool shortslot)
 179 {
 180         d11regs_t *regs;
 181
 182         regs = wlc_hw->regs;
 183
 184         if (shortslot) {
 185                 /* 11g short slot: 11a timing */
 186                 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
 187                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 188         } else {
 189                 /* 11g long slot: 11b timing */
 190                 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
 191                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 192         }
 193 }
 194
 195 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 196 {
 197         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
 198
 199         /* init microcode host flags */
 200         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 201
 202         /* do band-specific ucode IHR, SHM, and SCR inits */
 203         if (D11REV_IS(wlc_hw->corerev, 23)) {
 204                 if (WLCISNPHY(wlc_hw->band)) {
 205                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 206                 } else {
 207                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
 208                                   " %d\n", __func__, wlc_hw->unit,
 209                                   wlc_hw->corerev);
 210                 }
 211         } else {
 212                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 213                         if (WLCISLCNPHY(wlc_hw->band)) {
 214                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 215                         } else
 216                                 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
 217                                           " core rev %d\n", __func__,
 218                                           wlc_hw->unit, wlc_hw->corerev);
 219                 } else {
 220                         wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
 221                                 __func__, wlc_hw->unit, wlc_hw->corerev);
 222                 }
 223         }
 224 }
 225
 226 /* switch to new band but leave it inactive */
 227 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 228 {
 229         struct wlc_hw_info *wlc_hw = wlc->hw;
 230         u32 macintmask;
 231
 232         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 233
 234         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
 235
 236         /* disable interrupts */
 237         macintmask = brcms_intrsoff(wlc->wl);
 238
 239         /* radio off */
 240         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 241
 242         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 243
 244         wlc_setxband(wlc_hw, bandunit);
 245
 246         return macintmask;
 247 }
 248
 249 /* Process received frames */
 250 /*
 251  * Return true if more frames need to be processed. false otherwise.
 252  * Param 'bound' indicates max. # frames to process before break out.
 253  */
 254 static bool
 255 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 256 {
 257         struct sk_buff *p;
 258         struct sk_buff *head = NULL;
 259         struct sk_buff *tail = NULL;
 260         uint n = 0;
 261         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 262         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 263
 264         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
 265         /* gather received frames */
 266         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 267
 268                 if (!tail)
 269                         head = tail = p;
 270                 else {
 271                         tail->prev = p;
 272                         tail = p;
 273                 }
 274
 275                 /* !give others some time to run! */
 276                 if (++n >= bound_limit)
 277                         break;
 278         }
 279
 280         /* post more rbufs */
 281         dma_rxfill(wlc_hw->di[fifo]);
 282
 283         /* process each frame */
 284         while ((p = head) != NULL) {
 285                 head = head->prev;
 286                 p->prev = NULL;
 287
 288                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 289
 290                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 291                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 292
 293                 wlc_recv(wlc_hw->wlc, p);
 294         }
 295
 296         return n >= bound_limit;
 297 }
 298
 299 /* second-level interrupt processing
 300  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 301  *   Param 'bounded' indicates if applicable loops should be bounded.
 302  */
 303 bool wlc_dpc(struct wlc_info *wlc, bool bounded)
 304 {
 305         u32 macintstatus;
 306         struct wlc_hw_info *wlc_hw = wlc->hw;
 307         d11regs_t *regs = wlc_hw->regs;
 308         bool fatal = false;
 309         struct wiphy *wiphy = wlc->wiphy;
 310
 311         if (DEVICEREMOVED(wlc)) {
 312                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
 313                           __func__);
 314                 brcms_down(wlc->wl);
 315                 return false;
 316         }
 317
 318         /* grab and clear the saved software intstatus bits */
 319         macintstatus = wlc->macintstatus;
 320         wlc->macintstatus = 0;
 321
 322         BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
 323                wlc_hw->unit, macintstatus);
 324
 325         WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
 326
 327         /* BCN template is available */
 328         /* ZZZ: Use AP_ACTIVE ? */
 329         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
 330             && (macintstatus & MI_BCNTPL)) {
 331                 wlc_update_beacon(wlc);
 332         }
 333
 334         /* PMQ entry addition */
 335         if (macintstatus & MI_PMQ) {
 336         }
 337
 338         /* tx status */
 339         if (macintstatus & MI_TFS) {
 340                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 341                         wlc->macintstatus |= MI_TFS;
 342                 if (fatal) {
 343                         wiphy_err(wiphy, "MI_TFS: fatal\n");
 344                         goto fatal;
 345                 }
 346         }
 347
 348         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 349                 wlc_tbtt(wlc, regs);
 350
 351         /* ATIM window end */
 352         if (macintstatus & MI_ATIMWINEND) {
 353                 BCMMSG(wlc->wiphy, "end of ATIM window\n");
 354                 OR_REG(&regs->maccommand, wlc->qvalid);
 355                 wlc->qvalid = 0;
 356         }
 357
 358         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 359         if (macintstatus & MI_DMAINT) {
 360                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 361                         wlc->macintstatus |= MI_DMAINT;
 362                 }
 363         }
 364
 365         /* TX FIFO suspend/flush completion */
 366         if (macintstatus & MI_TXSTOP) {
 367                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 368                         /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
 369                 }
 370         }
 371
 372         /* noise sample collected */
 373         if (macintstatus & MI_BG_NOISE) {
 374                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 375         }
 376
 377         if (macintstatus & MI_GP0) {
 378                 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
 379                         "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
 380
 381                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 382                                         __func__, wlc_hw->sih->chip,
 383                                         wlc_hw->sih->chiprev);
 384                 /* big hammer */
 385                 brcms_init(wlc->wl);
 386         }
 387
 388         /* gptimer timeout */
 389         if (macintstatus & MI_TO) {
 390                 W_REG(&regs->gptimer, 0);
 391         }
 392
 393         if (macintstatus & MI_RFDISABLE) {
 394                 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
 395                        " RF Disable Input\n", wlc_hw->unit);
 396                 brcms_rfkill_set_hw_state(wlc->wl);
 397         }
 398
 399         /* send any enq'd tx packets. Just makes sure to jump start tx */
 400         if (!pktq_empty(&wlc->pkt_queue->q))
 401                 wlc_send_q(wlc);
 402
 403         /* it isn't done and needs to be resched if macintstatus is non-zero */
 404         return wlc->macintstatus != 0;
 405
 406  fatal:
 407         brcms_init(wlc->wl);
 408         return wlc->macintstatus != 0;
 409 }
 410
 411 /* common low-level watchdog code */
 412 void wlc_bmac_watchdog(void *arg)
 413 {
 414         struct wlc_info *wlc = (struct wlc_info *) arg;
 415         struct wlc_hw_info *wlc_hw = wlc->hw;
 416
 417         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 418
 419         if (!wlc_hw->up)
 420                 return;
 421
 422         /* increment second count */
 423         wlc_hw->now++;
 424
 425         /* Check for FIFO error interrupts */
 426         wlc_bmac_fifoerrors(wlc_hw);
 427
 428         /* make sure RX dma has buffers */
 429         dma_rxfill(wlc->hw->di[RX_FIFO]);
 430
 431         wlc_phy_watchdog(wlc_hw->band->pi);
 432 }
 433
 434 void
 435 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 436                       bool mute, struct txpwr_limits *txpwr)
 437 {
 438         uint bandunit;
 439
 440         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
 441
 442         wlc_hw->chanspec = chanspec;
 443
 444         /* Switch bands if necessary */
 445         if (NBANDS_HW(wlc_hw) > 1) {
 446                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 447                 if (wlc_hw->band->bandunit != bandunit) {
 448                         /* wlc_bmac_setband disables other bandunit,
 449                          *  use light band switch if not up yet
 450                          */
 451                         if (wlc_hw->up) {
 452                                 wlc_phy_chanspec_radio_set(wlc_hw->
 453                                                            bandstate[bandunit]->
 454                                                            pi, chanspec);
 455                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 456                         } else {
 457                                 wlc_setxband(wlc_hw, bandunit);
 458                         }
 459                 }
 460         }
 461
 462         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 463
 464         if (!wlc_hw->up) {
 465                 if (wlc_hw->clk)
 466                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 467                                                   chanspec);
 468                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 469         } else {
 470                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 471                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 472
 473                 /* Update muting of the channel */
 474                 wlc_bmac_mute(wlc_hw, mute, 0);
 475         }
 476 }
 477
 478 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 479 {
 480         state->machwcap = wlc_hw->machwcap;
 481
 482         return 0;
 483 }
 484
 485 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 486 {
 487         uint i;
 488         char name[8];
 489         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 490         u16 pio_mhf2 = 0;
 491         struct wlc_hw_info *wlc_hw = wlc->hw;
 492         uint unit = wlc_hw->unit;
 493         wlc_tunables_t *tune = wlc->pub->tunables;
 494         struct wiphy *wiphy = wlc->wiphy;
 495
 496         /* name and offsets for dma_attach */
 497         snprintf(name, sizeof(name), "wl%d", unit);
 498
 499         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 500                 uint addrwidth;
 501                 int dma_attach_err = 0;
 502                 /* Find out the DMA addressing capability and let OS know
 503                  * All the channels within one DMA core have 'common-minimum' same
 504                  * capability
 505                  */
 506                 addrwidth =
 507                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 508
 509                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 510                         wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
 511                                   "resources failed\n", unit);
 512                         return false;
 513                 }
 514
 515                 /*
 516                  * FIFO 0
 517                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 518                  * RX: RX_FIFO (RX data packets)
 519                  */
 520                 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
 521                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 522                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 523                                            (wme ? tune->ntxd : 0), tune->nrxd,
 524                                            tune->rxbufsz, -1, tune->nrxbufpost,
 525                                            WL_HWRXOFF, &brcm_msg_level);
 526                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 527
 528                 /*
 529                  * FIFO 1
 530                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 531                  *   (legacy) TX_DATA_FIFO (TX data packets)
 532                  * RX: UNUSED
 533                  */
 534                 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
 535                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 536                                            tune->ntxd, 0, 0, -1, 0, 0,
 537                                            &brcm_msg_level);
 538                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 539
 540                 /*
 541                  * FIFO 2
 542                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 543                  * RX: UNUSED
 544                  */
 545                 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
 546                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 547                                            tune->ntxd, 0, 0, -1, 0, 0,
 548                                            &brcm_msg_level);
 549                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 550                 /*
 551                  * FIFO 3
 552                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 553                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 554                  */
 555                 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
 556                                            DMAREG(wlc_hw, DMA_TX, 3),
 557                                            NULL, tune->ntxd, 0, 0, -1,
 558                                            0, 0, &brcm_msg_level);
 559                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 560 /* Cleaner to leave this as if with AP defined */
 561
 562                 if (dma_attach_err) {
 563                         wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
 564                                   "\n", unit);
 565                         return false;
 566                 }
 567
 568                 /* get pointer to dma engine tx flow control variable */
 569                 for (i = 0; i < NFIFO; i++)
 570                         if (wlc_hw->di[i])
 571                                 wlc_hw->txavail[i] =
 572                                     (uint *) dma_getvar(wlc_hw->di[i],
 573                                                         "&txavail");
 574         }
 575
 576         /* initial ucode host flags */
 577         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 578
 579         return true;
 580 }
 581
 582 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 583 {
 584         uint j;
 585
 586         for (j = 0; j < NFIFO; j++) {
 587                 if (wlc_hw->di[j]) {
 588                         dma_detach(wlc_hw->di[j]);
 589                         wlc_hw->di[j] = NULL;
 590                 }
 591         }
 592 }
 593
 594 /* low level attach
 595  *    run backplane attach, init nvram
 596  *    run phy attach
 597  *    initialize software state for each core and band
 598  *    put the whole chip in reset(driver down state), no clock
 599  */
 600 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 601                     bool piomode, void *regsva, uint bustype, void *btparam)
 602 {
 603         struct wlc_hw_info *wlc_hw;
 604         d11regs_t *regs;
 605         char *macaddr = NULL;
 606         char *vars;
 607         uint err = 0;
 608         uint j;
 609         bool wme = false;
 610         shared_phy_params_t sha_params;
 611         struct wiphy *wiphy = wlc->wiphy;
 612
 613         BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
 614                 device);
 615
 616         wme = true;
 617
 618         wlc_hw = wlc->hw;
 619         wlc_hw->wlc = wlc;
 620         wlc_hw->unit = unit;
 621         wlc_hw->band = wlc_hw->bandstate[0];
 622         wlc_hw->_piomode = piomode;
 623
 624         /* populate struct wlc_hw_info with default values  */
 625         wlc_bmac_info_init(wlc_hw);
 626
 627         /*
 628          * Do the hardware portion of the attach.
 629          * Also initialize software state that depends on the particular hardware
 630          * we are running.
 631          */
 632         wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
 633                                 &wlc_hw->vars, &wlc_hw->vars_size);
 634         if (wlc_hw->sih == NULL) {
 635                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
 636                           unit);
 637                 err = 11;
 638                 goto fail;
 639         }
 640         vars = wlc_hw->vars;
 641
 642         /*
 643          * Get vendid/devid nvram overwrites, which could be different
 644          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 645          * SDIO_BUS, and SROMless devices on PCI_BUS.
 646          */
 647 #ifdef BCMBUSTYPE
 648         bustype = BCMBUSTYPE;
 649 #endif
 650         if (bustype != SI_BUS) {
 651                 char *var;
 652
 653                 var = getvar(vars, "vendid");
 654                 if (var) {
 655                         vendor = (u16) simple_strtoul(var, NULL, 0);
 656                         wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
 657                                   vendor);
 658                 }
 659                 var = getvar(vars, "devid");
 660                 if (var) {
 661                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 662                         if (devid != 0xffff) {
 663                                 device = devid;
 664                                 wiphy_err(wiphy, "Overriding device id = 0x%x"
 665                                           "\n", device);
 666                         }
 667                 }
 668
 669                 /* verify again the device is supported */
 670                 if (!wlc_chipmatch(vendor, device)) {
 671                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
 672                                 "vendor/device (0x%x/0x%x)\n",
 673                                  unit, vendor, device);
 674                         err = 12;
 675                         goto fail;
 676                 }
 677         }
 678
 679         wlc_hw->vendorid = vendor;
 680         wlc_hw->deviceid = device;
 681
 682         /* set bar0 window to point at D11 core */
 683         wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 684         wlc_hw->corerev = ai_corerev(wlc_hw->sih);
 685
 686         regs = wlc_hw->regs;
 687
 688         wlc->regs = wlc_hw->regs;
 689
 690         /* validate chip, chiprev and corerev */
 691         if (!wlc_isgoodchip(wlc_hw)) {
 692                 err = 13;
 693                 goto fail;
 694         }
 695
 696         /* initialize power control registers */
 697         ai_clkctl_init(wlc_hw->sih);
 698
 699         /* request fastclock and force fastclock for the rest of attach
 700          * bring the d11 core out of reset.
 701          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 702          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 703          */
 704         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 705         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 706
 707         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 708                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
 709                         "failed\n", unit);
 710                 err = 14;
 711                 goto fail;
 712         }
 713
 714         /* get the board rev, used just below */
 715         j = getintvar(vars, "boardrev");
 716         /* promote srom boardrev of 0xFF to 1 */
 717         if (j == BOARDREV_PROMOTABLE)
 718                 j = BOARDREV_PROMOTED;
 719         wlc_hw->boardrev = (u16) j;
 720         if (!wlc_validboardtype(wlc_hw)) {
 721                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
 722                         "board type (0x%x)" " or revision level (0x%x)\n",
 723                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 724                 err = 15;
 725                 goto fail;
 726         }
 727         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 728         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 729         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 730
 731         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 732                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 733
 734         if ((wlc_hw->sih->bustype == PCI_BUS)
 735             && (ai_pci_war16165(wlc_hw->sih)))
 736                 wlc->war16165 = true;
 737
 738         /* check device id(srom, nvram etc.) to set bands */
 739         if (wlc_hw->deviceid == BCM43224_D11N_ID ||
 740             wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
 741                 /* Dualband boards */
 742                 wlc_hw->_nbands = 2;
 743         } else
 744                 wlc_hw->_nbands = 1;
 745
 746         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 747                 wlc_hw->_nbands = 1;
 748
 749         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 750          * init of these values
 751          */
 752         wlc->vendorid = wlc_hw->vendorid;
 753         wlc->deviceid = wlc_hw->deviceid;
 754         wlc->pub->sih = wlc_hw->sih;
 755         wlc->pub->corerev = wlc_hw->corerev;
 756         wlc->pub->sromrev = wlc_hw->sromrev;
 757         wlc->pub->boardrev = wlc_hw->boardrev;
 758         wlc->pub->boardflags = wlc_hw->boardflags;
 759         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 760         wlc->pub->_nbands = wlc_hw->_nbands;
 761
 762         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 763
 764         if (wlc_hw->physhim == NULL) {
 765                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
 766                         "failed\n", unit);
 767                 err = 25;
 768                 goto fail;
 769         }
 770
 771         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 772         sha_params.sih = wlc_hw->sih;
 773         sha_params.physhim = wlc_hw->physhim;
 774         sha_params.unit = unit;
 775         sha_params.corerev = wlc_hw->corerev;
 776         sha_params.vars = vars;
 777         sha_params.vid = wlc_hw->vendorid;
 778         sha_params.did = wlc_hw->deviceid;
 779         sha_params.chip = wlc_hw->sih->chip;
 780         sha_params.chiprev = wlc_hw->sih->chiprev;
 781         sha_params.chippkg = wlc_hw->sih->chippkg;
 782         sha_params.sromrev = wlc_hw->sromrev;
 783         sha_params.boardtype = wlc_hw->sih->boardtype;
 784         sha_params.boardrev = wlc_hw->boardrev;
 785         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 786         sha_params.boardflags = wlc_hw->boardflags;
 787         sha_params.boardflags2 = wlc_hw->boardflags2;
 788         sha_params.bustype = wlc_hw->sih->bustype;
 789         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 790
 791         /* alloc and save pointer to shared phy state area */
 792         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 793         if (!wlc_hw->phy_sh) {
 794                 err = 16;
 795                 goto fail;
 796         }
 797
 798         /* initialize software state for each core and band */
 799         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 800                 /*
 801                  * band0 is always 2.4Ghz
 802                  * band1, if present, is 5Ghz
 803                  */
 804
 805                 /* So if this is a single band 11a card, use band 1 */
 806                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 807                         j = BAND_5G_INDEX;
 808
 809                 wlc_setxband(wlc_hw, j);
 810
 811                 wlc_hw->band->bandunit = j;
 812                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 813                 wlc->band->bandunit = j;
 814                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 815                 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
 816
 817                 wlc_hw->machwcap = R_REG(&regs->machwcap);
 818                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 819
 820                 /* init tx fifo size */
 821                 wlc_hw->xmtfifo_sz =
 822                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 823
 824                 /* Get a phy for this band */
 825                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 826                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
 827                         wlc->wiphy);
 828                 if (wlc_hw->band->pi == NULL) {
 829                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
 830                                   "attach failed\n", unit);
 831                         err = 17;
 832                         goto fail;
 833                 }
 834
 835                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 836
 837                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 838                                        &wlc_hw->band->phyrev,
 839                                        &wlc_hw->band->radioid,
 840                                        &wlc_hw->band->radiorev);
 841                 wlc_hw->band->abgphy_encore =
 842                     wlc_phy_get_encore(wlc_hw->band->pi);
 843                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 844                 wlc_hw->band->core_flags =
 845                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 846
 847                 /* verify good phy_type & supported phy revision */
 848                 if (WLCISNPHY(wlc_hw->band)) {
 849                         if (NCONF_HAS(wlc_hw->band->phyrev))
 850                                 goto good_phy;
 851                         else
 852                                 goto bad_phy;
 853                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 854                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 855                                 goto good_phy;
 856                         else
 857                                 goto bad_phy;
 858                 } else {
 859  bad_phy:
 860                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
 861                                   "phy type/rev (%d/%d)\n", unit,
 862                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
 863                         err = 18;
 864                         goto fail;
 865                 }
 866
 867  good_phy:
 868                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 869                  * high level attach. However we can not make that change until all low level access
 870                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 871                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 872                  * low only init when all fns updated.
 873                  */
 874                 wlc->band->pi = wlc_hw->band->pi;
 875                 wlc->band->phytype = wlc_hw->band->phytype;
 876                 wlc->band->phyrev = wlc_hw->band->phyrev;
 877                 wlc->band->radioid = wlc_hw->band->radioid;
 878                 wlc->band->radiorev = wlc_hw->band->radiorev;
 879
 880                 /* default contention windows size limits */
 881                 wlc_hw->band->CWmin = APHY_CWMIN;
 882                 wlc_hw->band->CWmax = PHY_CWMAX;
 883
 884                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 885                         err = 19;
 886                         goto fail;
 887                 }
 888         }
 889
 890         /* disable core to match driver "down" state */
 891         wlc_coredisable(wlc_hw);
 892
 893         /* Match driver "down" state */
 894         if (wlc_hw->sih->bustype == PCI_BUS)
 895                 ai_pci_down(wlc_hw->sih);
 896
 897         /* register sb interrupt callback functions */
 898         ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 899                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 900
 901         /* turn off pll and xtal to match driver "down" state */
 902         wlc_bmac_xtal(wlc_hw, OFF);
 903
 904         /* *********************************************************************
 905          * The hardware is in the DOWN state at this point. D11 core
 906          * or cores are in reset with clocks off, and the board PLLs
 907          * are off if possible.
 908          *
 909          * Beyond this point, wlc->sbclk == false and chip registers
 910          * should not be touched.
 911          *********************************************************************
 912          */
 913
 914         /* init etheraddr state variables */
 915         macaddr = wlc_get_macaddr(wlc_hw);
 916         if (macaddr == NULL) {
 917                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
 918                           unit);
 919                 err = 21;
 920                 goto fail;
 921         }
 922         brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
 923         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 924             is_zero_ether_addr(wlc_hw->etheraddr)) {
 925                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
 926                           unit, macaddr);
 927                 err = 22;
 928                 goto fail;
 929         }
 930
 931         BCMMSG(wlc->wiphy,
 932                  "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 933                  wlc_hw->deviceid, wlc_hw->_nbands,
 934                  wlc_hw->sih->boardtype, macaddr);
 935
 936         return err;
 937
 938  fail:
 939         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
 940                   err);
 941         return err;
 942 }
 943
 944 /*
 945  * Initialize wlc_info default values ...
 946  * may get overrides later in this function
 947  *  BMAC_NOTES, move low out and resolve the dangling ones
 948  */
 949 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
 950 {
 951         struct wlc_info *wlc = wlc_hw->wlc;
 952
 953         /* set default sw macintmask value */
 954         wlc->defmacintmask = DEF_MACINTMASK;
 955
 956         /* various 802.11g modes */
 957         wlc_hw->shortslot = false;
 958
 959         wlc_hw->SFBL = RETRY_SHORT_FB;
 960         wlc_hw->LFBL = RETRY_LONG_FB;
 961
 962         /* default mac retry limits */
 963         wlc_hw->SRL = RETRY_SHORT_DEF;
 964         wlc_hw->LRL = RETRY_LONG_DEF;
 965         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
 966 }
 967
 968 /*
 969  * low level detach
 970  */
 971 int wlc_bmac_detach(struct wlc_info *wlc)
 972 {
 973         uint i;
 974         struct wlc_hwband *band;
 975         struct wlc_hw_info *wlc_hw = wlc->hw;
 976         int callbacks;
 977
 978         callbacks = 0;
 979
 980         if (wlc_hw->sih) {
 981                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
 982                  * interrupt object may has been freed. this must be done before sb core switch
 983                  */
 984                 ai_deregister_intr_callback(wlc_hw->sih);
 985
 986                 if (wlc_hw->sih->bustype == PCI_BUS)
 987                         ai_pci_sleep(wlc_hw->sih);
 988         }
 989
 990         wlc_bmac_detach_dmapio(wlc_hw);
 991
 992         band = wlc_hw->band;
 993         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
 994                 if (band->pi) {
 995                         /* Detach this band's phy */
 996                         wlc_phy_detach(band->pi);
 997                         band->pi = NULL;
 998                 }
 999                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1000         }
1001
1002         /* Free shared phy state */
1003         wlc_phy_shared_detach(wlc_hw->phy_sh);
1004
1005         wlc_phy_shim_detach(wlc_hw->physhim);
1006
1007         /* free vars */
1008         kfree(wlc_hw->vars);
1009         wlc_hw->vars = NULL;
1010
1011         if (wlc_hw->sih) {
1012                 ai_detach(wlc_hw->sih);
1013                 wlc_hw->sih = NULL;
1014         }
1015
1016         return callbacks;
1017
1018 }
1019
1020 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1021 {
1022         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1023
1024         /* reset the core */
1025         if (!DEVICEREMOVED(wlc_hw->wlc))
1026                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1027
1028         /* purge the dma rings */
1029         wlc_flushqueues(wlc_hw->wlc);
1030
1031         wlc_reset_bmac_done(wlc_hw->wlc);
1032 }
1033
1034 void
1035 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1036                           bool mute) {
1037         u32 macintmask;
1038         bool fastclk;
1039         struct wlc_info *wlc = wlc_hw->wlc;
1040
1041         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1042
1043         /* request FAST clock if not on */
1044         fastclk = wlc_hw->forcefastclk;
1045         if (!fastclk)
1046                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1047
1048         /* disable interrupts */
1049         macintmask = brcms_intrsoff(wlc->wl);
1050
1051         /* set up the specified band and chanspec */
1052         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1053         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1054
1055         /* do one-time phy inits and calibration */
1056         wlc_phy_cal_init(wlc_hw->band->pi);
1057
1058         /* core-specific initialization */
1059         wlc_coreinit(wlc);
1060
1061         /* suspend the tx fifos and mute the phy for preism cac time */
1062         if (mute)
1063                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1064
1065         /* band-specific inits */
1066         wlc_bmac_bsinit(wlc, chanspec);
1067
1068         /* restore macintmask */
1069         brcms_intrsrestore(wlc->wl, macintmask);
1070
1071         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1072          * and wlc_enable_mac() will clear this override bit.
1073          */
1074         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1075
1076         /*
1077          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1078          */
1079         wlc_hw->mac_suspend_depth = 1;
1080
1081         /* restore the clk */
1082         if (!fastclk)
1083                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1084 }
1085
1086 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1087 {
1088         uint coremask;
1089
1090         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1091
1092         /*
1093          * Enable pll and xtal, initialize the power control registers,
1094          * and force fastclock for the remainder of wlc_up().
1095          */
1096         wlc_bmac_xtal(wlc_hw, ON);
1097         ai_clkctl_init(wlc_hw->sih);
1098         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1099
1100         /*
1101          * Configure pci/pcmcia here instead of in wlc_attach()
1102          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1103          */
1104         coremask = (1 << wlc_hw->wlc->core->coreidx);
1105
1106         if (wlc_hw->sih->bustype == PCI_BUS)
1107                 ai_pci_setup(wlc_hw->sih, coremask);
1108
1109         /*
1110          * Need to read the hwradio status here to cover the case where the system
1111          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1112          */
1113         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1114                 /* put SB PCI in down state again */
1115                 if (wlc_hw->sih->bustype == PCI_BUS)
1116                         ai_pci_down(wlc_hw->sih);
1117                 wlc_bmac_xtal(wlc_hw, OFF);
1118                 return -ENOMEDIUM;
1119         }
1120
1121         if (wlc_hw->sih->bustype == PCI_BUS)
1122                 ai_pci_up(wlc_hw->sih);
1123
1124         /* reset the d11 core */
1125         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1126
1127         return 0;
1128 }
1129
1130 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1131 {
1132         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1133
1134         wlc_hw->up = true;
1135         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1136
1137         /* FULLY enable dynamic power control and d11 core interrupt */
1138         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1139         brcms_intrson(wlc_hw->wlc->wl);
1140         return 0;
1141 }
1142
1143 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1144 {
1145         bool dev_gone;
1146         uint callbacks = 0;
1147
1148         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1149
1150         if (!wlc_hw->up)
1151                 return callbacks;
1152
1153         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1154
1155         /* disable interrupts */
1156         if (dev_gone)
1157                 wlc_hw->wlc->macintmask = 0;
1158         else {
1159                 /* now disable interrupts */
1160                 brcms_intrsoff(wlc_hw->wlc->wl);
1161
1162                 /* ensure we're running on the pll clock again */
1163                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1164         }
1165         /* down phy at the last of this stage */
1166         callbacks += wlc_phy_down(wlc_hw->band->pi);
1167
1168         return callbacks;
1169 }
1170
1171 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1172 {
1173         uint callbacks = 0;
1174         bool dev_gone;
1175
1176         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1177
1178         if (!wlc_hw->up)
1179                 return callbacks;
1180
1181         wlc_hw->up = false;
1182         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1183
1184         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1185
1186         if (dev_gone) {
1187                 wlc_hw->sbclk = false;
1188                 wlc_hw->clk = false;
1189                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1190
1191                 /* reclaim any posted packets */
1192                 wlc_flushqueues(wlc_hw->wlc);
1193         } else {
1194
1195                 /* Reset and disable the core */
1196                 if (ai_iscoreup(wlc_hw->sih)) {
1197                         if (R_REG(&wlc_hw->regs->maccontrol) &
1198                             MCTL_EN_MAC)
1199                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1200                         callbacks += brcms_reset(wlc_hw->wlc->wl);
1201                         wlc_coredisable(wlc_hw);
1202                 }
1203
1204                 /* turn off primary xtal and pll */
1205                 if (!wlc_hw->noreset) {
1206                         if (wlc_hw->sih->bustype == PCI_BUS)
1207                                 ai_pci_down(wlc_hw->sih);
1208                         wlc_bmac_xtal(wlc_hw, OFF);
1209                 }
1210         }
1211
1212         return callbacks;
1213 }
1214
1215 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1216 {
1217         /* delay before first read of ucode state */
1218         udelay(40);
1219
1220         /* wait until ucode is no longer asleep */
1221         SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1222                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1223 }
1224
1225 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1226 {
1227         memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1228 }
1229
1230 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1231 {
1232         return wlc_hw->band->bandtype;
1233 }
1234
1235 /* control chip clock to save power, enable dynamic clock or force fast clock */
1236 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1237 {
1238         if (PMUCTL_ENAB(wlc_hw->sih)) {
1239                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1240                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1241                  *      which means the FCA bit may not be set.
1242                  *      should wakeup mac if driver wants it to run on HT.
1243                  */
1244
1245                 if (wlc_hw->clk) {
1246                         if (mode == CLK_FAST) {
1247                                 OR_REG(&wlc_hw->regs->clk_ctl_st,
1248                                        CCS_FORCEHT);
1249
1250                                 udelay(64);
1251
1252                                 SPINWAIT(((R_REG
1253                                            (&wlc_hw->regs->
1254                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1255                                          PMU_MAX_TRANSITION_DLY);
1256                                 WARN_ON(!(R_REG
1257                                           (&wlc_hw->regs->
1258                                            clk_ctl_st) & CCS_HTAVAIL));
1259                         } else {
1260                                 if ((wlc_hw->sih->pmurev == 0) &&
1261                                     (R_REG
1262                                      (&wlc_hw->regs->
1263                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1264                                         SPINWAIT(((R_REG
1265                                                    (&wlc_hw->regs->
1266                                                     clk_ctl_st) & CCS_HTAVAIL)
1267                                                   == 0),
1268                                                  PMU_MAX_TRANSITION_DLY);
1269                                 AND_REG(&wlc_hw->regs->clk_ctl_st,
1270                                         ~CCS_FORCEHT);
1271                         }
1272                 }
1273                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1274         } else {
1275
1276                 /* old chips w/o PMU, force HT through cc,
1277                  * then use FCA to verify mac is running fast clock
1278                  */
1279
1280                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1281
1282                 /* check fast clock is available (if core is not in reset) */
1283                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1284                         WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1285                                   SISF_FCLKA));
1286
1287                 /* keep the ucode wake bit on if forcefastclk is on
1288                  * since we do not want ucode to put us back to slow clock
1289                  * when it dozes for PM mode.
1290                  * Code below matches the wake override bit with current forcefastclk state
1291                  * Only setting bit in wake_override instead of waking ucode immediately
1292                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1293                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1294                  * (protected by an up check) was executed just below.
1295                  */
1296                 if (wlc_hw->forcefastclk)
1297                         mboolset(wlc_hw->wake_override,
1298                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1299                 else
1300                         mboolclr(wlc_hw->wake_override,
1301                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1302         }
1303 }
1304
1305 /* set initial host flags value */
1306 static void
1307 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1308 {
1309         struct wlc_hw_info *wlc_hw = wlc->hw;
1310
1311         memset(mhfs, 0, MHFMAX * sizeof(u16));
1312
1313         mhfs[MHF2] |= mhf2_init;
1314
1315         /* prohibit use of slowclock on multifunction boards */
1316         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1317                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1318
1319         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1320                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1321                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1322         }
1323 }
1324
1325 /* set or clear ucode host flag bits
1326  * it has an optimization for no-change write
1327  * it only writes through shared memory when the core has clock;
1328  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1329  *
1330  *
1331  * bands values are: WLC_BAND_AUTO <--- Current band only
1332  *                   WLC_BAND_5G   <--- 5G band only
1333  *                   WLC_BAND_2G   <--- 2G band only
1334  *                   WLC_BAND_ALL  <--- All bands
1335  */
1336 void
1337 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1338              int bands)
1339 {
1340         u16 save;
1341         u16 addr[MHFMAX] = {
1342                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1343                 M_HOST_FLAGS5
1344         };
1345         struct wlc_hwband *band;
1346
1347         if ((val & ~mask) || idx >= MHFMAX)
1348                 return; /* error condition */
1349
1350         switch (bands) {
1351                 /* Current band only or all bands,
1352                  * then set the band to current band
1353                  */
1354         case WLC_BAND_AUTO:
1355         case WLC_BAND_ALL:
1356                 band = wlc_hw->band;
1357                 break;
1358         case WLC_BAND_5G:
1359                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1360                 break;
1361         case WLC_BAND_2G:
1362                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1363                 break;
1364         default:
1365                 band = NULL;    /* error condition */
1366         }
1367
1368         if (band) {
1369                 save = band->mhfs[idx];
1370                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1371
1372                 /* optimization: only write through if changed, and
1373                  * changed band is the current band
1374                  */
1375                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1376                     && (band == wlc_hw->band))
1377                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1378                                            (u16) band->mhfs[idx]);
1379         }
1380
1381         if (bands == WLC_BAND_ALL) {
1382                 wlc_hw->bandstate[0]->mhfs[idx] =
1383                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1384                 wlc_hw->bandstate[1]->mhfs[idx] =
1385                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1386         }
1387 }
1388
1389 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1390 {
1391         struct wlc_hwband *band;
1392
1393         if (idx >= MHFMAX)
1394                 return 0; /* error condition */
1395         switch (bands) {
1396         case WLC_BAND_AUTO:
1397                 band = wlc_hw->band;
1398                 break;
1399         case WLC_BAND_5G:
1400                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1401                 break;
1402         case WLC_BAND_2G:
1403                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1404                 break;
1405         default:
1406                 band = NULL;            /* error condition */
1407         }
1408
1409         if (!band)
1410                 return 0;
1411
1412         return band->mhfs[idx];
1413 }
1414
1415 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1416 {
1417         u8 idx;
1418         u16 addr[] = {
1419                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1420                 M_HOST_FLAGS5
1421         };
1422
1423         for (idx = 0; idx < MHFMAX; idx++) {
1424                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1425         }
1426 }
1427
1428 /* set the maccontrol register to desired reset state and
1429  * initialize the sw cache of the register
1430  */
1431 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1432 {
1433         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1434         wlc_hw->maccontrol = 0;
1435         wlc_hw->suspended_fifos = 0;
1436         wlc_hw->wake_override = 0;
1437         wlc_hw->mute_override = 0;
1438         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1439 }
1440
1441 /* set or clear maccontrol bits */
1442 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1443 {
1444         u32 maccontrol;
1445         u32 new_maccontrol;
1446
1447         if (val & ~mask)
1448                 return; /* error condition */
1449         maccontrol = wlc_hw->maccontrol;
1450         new_maccontrol = (maccontrol & ~mask) | val;
1451
1452         /* if the new maccontrol value is the same as the old, nothing to do */
1453         if (new_maccontrol == maccontrol)
1454                 return;
1455
1456         /* something changed, cache the new value */
1457         wlc_hw->maccontrol = new_maccontrol;
1458
1459         /* write the new values with overrides applied */
1460         wlc_mctrl_write(wlc_hw);
1461 }
1462
1463 /* write the software state of maccontrol and overrides to the maccontrol register */
1464 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1465 {
1466         u32 maccontrol = wlc_hw->maccontrol;
1467
1468         /* OR in the wake bit if overridden */
1469         if (wlc_hw->wake_override)
1470                 maccontrol |= MCTL_WAKE;
1471
1472         /* set AP and INFRA bits for mute if needed */
1473         if (wlc_hw->mute_override) {
1474                 maccontrol &= ~(MCTL_AP);
1475                 maccontrol |= MCTL_INFRA;
1476         }
1477
1478         W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1479 }
1480
1481 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1482 {
1483         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1484                 mboolset(wlc_hw->wake_override, override_bit);
1485                 return;
1486         }
1487
1488         mboolset(wlc_hw->wake_override, override_bit);
1489
1490         wlc_mctrl_write(wlc_hw);
1491         wlc_bmac_wait_for_wake(wlc_hw);
1492
1493         return;
1494 }
1495
1496 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1497 {
1498         mboolclr(wlc_hw->wake_override, override_bit);
1499
1500         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1501                 return;
1502
1503         wlc_mctrl_write(wlc_hw);
1504
1505         return;
1506 }
1507
1508 /* When driver needs ucode to stop beaconing, it has to make sure that
1509  * MCTL_AP is clear and MCTL_INFRA is set
1510  * Mode           MCTL_AP        MCTL_INFRA
1511  * AP                1              1
1512  * STA               0              1 <--- This will ensure no beacons
1513  * IBSS              0              0
1514  */
1515 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1516 {
1517         wlc_hw->mute_override = 1;
1518
1519         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1520          * override, then there is no change to write
1521          */
1522         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1523                 return;
1524
1525         wlc_mctrl_write(wlc_hw);
1526
1527         return;
1528 }
1529
1530 /* Clear the override on AP and INFRA bits */
1531 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1532 {
1533         if (wlc_hw->mute_override == 0)
1534                 return;
1535
1536         wlc_hw->mute_override = 0;
1537
1538         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1539          * override, then there is no change to write
1540          */
1541         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1542                 return;
1543
1544         wlc_mctrl_write(wlc_hw);
1545 }
1546
1547 /*
1548  * Write a MAC address to the given match reg offset in the RXE match engine.
1549  */
1550 void
1551 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1552                        const u8 *addr)
1553 {
1554         d11regs_t *regs;
1555         u16 mac_l;
1556         u16 mac_m;
1557         u16 mac_h;
1558
1559         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
1560                  wlc_hw->unit);
1561
1562         regs = wlc_hw->regs;
1563         mac_l = addr[0] | (addr[1] << 8);
1564         mac_m = addr[2] | (addr[3] << 8);
1565         mac_h = addr[4] | (addr[5] << 8);
1566
1567         /* enter the MAC addr into the RXE match registers */
1568         W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1569         W_REG(&regs->rcm_mat_data, mac_l);
1570         W_REG(&regs->rcm_mat_data, mac_m);
1571         W_REG(&regs->rcm_mat_data, mac_h);
1572
1573 }
1574
1575 void
1576 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1577                             void *buf)
1578 {
1579         d11regs_t *regs;
1580         u32 word;
1581         bool be_bit;
1582         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1583
1584         regs = wlc_hw->regs;
1585         W_REG(&regs->tplatewrptr, offset);
1586
1587         /* if MCTL_BIGEND bit set in mac control register,
1588          * the chip swaps data in fifo, as well as data in
1589          * template ram
1590          */
1591         be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1592
1593         while (len > 0) {
1594                 memcpy(&word, buf, sizeof(u32));
1595
1596                 if (be_bit)
1597                         word = cpu_to_be32(word);
1598                 else
1599                         word = cpu_to_le32(word);
1600
1601                 W_REG(&regs->tplatewrdata, word);
1602
1603                 buf = (u8 *) buf + sizeof(u32);
1604                 len -= sizeof(u32);
1605         }
1606 }
1607
1608 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1609 {
1610         wlc_hw->band->CWmin = newmin;
1611
1612         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1613         (void)R_REG(&wlc_hw->regs->objaddr);
1614         W_REG(&wlc_hw->regs->objdata, newmin);
1615 }
1616
1617 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1618 {
1619         wlc_hw->band->CWmax = newmax;
1620
1621         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1622         (void)R_REG(&wlc_hw->regs->objaddr);
1623         W_REG(&wlc_hw->regs->objdata, newmax);
1624 }
1625
1626 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1627 {
1628         bool fastclk;
1629
1630         /* request FAST clock if not on */
1631         fastclk = wlc_hw->forcefastclk;
1632         if (!fastclk)
1633                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1634
1635         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1636
1637         wlc_bmac_phy_reset(wlc_hw);
1638         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1639
1640         /* restore the clk */
1641         if (!fastclk)
1642                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1643 }
1644
1645 static void
1646 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1647 {
1648         d11regs_t *regs = wlc_hw->regs;
1649
1650         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1651                                     bcn);
1652         /* write beacon length to SCR */
1653         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1654         /* mark beacon0 valid */
1655         OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1656 }
1657
1658 static void
1659 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1660 {
1661         d11regs_t *regs = wlc_hw->regs;
1662
1663         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1664                                     bcn);
1665         /* write beacon length to SCR */
1666         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1667         /* mark beacon1 valid */
1668         OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1669 }
1670
1671 /* mac is assumed to be suspended at this point */
1672 void
1673 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1674                                bool both)
1675 {
1676         d11regs_t *regs = wlc_hw->regs;
1677
1678         if (both) {
1679                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1680                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1681         } else {
1682                 /* bcn 0 */
1683                 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1684                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1685                 /* bcn 1 */
1686                 else if (!
1687                          (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1688                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1689         }
1690 }
1691
1692 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1693 {
1694         u16 v;
1695         struct wlc_info *wlc = wlc_hw->wlc;
1696         /* update SYNTHPU_DLY */
1697
1698         if (WLCISLCNPHY(wlc->band)) {
1699                 v = SYNTHPU_DLY_LPPHY_US;
1700         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1701                 v = SYNTHPU_DLY_NPHY_US;
1702         } else {
1703                 v = SYNTHPU_DLY_BPHY_US;
1704         }
1705
1706         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1707 }
1708
1709 /* band-specific init */
1710 static void
1711 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1712 {
1713         struct wlc_hw_info *wlc_hw = wlc->hw;
1714
1715         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1716                 wlc_hw->band->bandunit);
1717
1718         wlc_ucode_bsinit(wlc_hw);
1719
1720         wlc_phy_init(wlc_hw->band->pi, chanspec);
1721
1722         wlc_ucode_txant_set(wlc_hw);
1723
1724         /* cwmin is band-specific, update hardware with value for current band */
1725         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1726         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1727
1728         wlc_bmac_update_slot_timing(wlc_hw,
1729                                     BAND_5G(wlc_hw->band->
1730                                             bandtype) ? true : wlc_hw->
1731                                     shortslot);
1732
1733         /* write phytype and phyvers */
1734         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1735         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1736
1737         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1738         wlc_upd_ofdm_pctl1_table(wlc_hw);
1739
1740         wlc_bmac_upd_synthpu(wlc_hw);
1741 }
1742
1743 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1744 {
1745         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1746
1747         wlc_hw->phyclk = clk;
1748
1749         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1750
1751                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1752                                (SICF_PRST | SICF_FGC));
1753                 udelay(1);
1754                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1755                 udelay(1);
1756
1757         } else {                /* take phy out of reset */
1758
1759                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1760                 udelay(1);
1761                 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1762                 udelay(1);
1763
1764         }
1765 }
1766
1767 /* Perform a soft reset of the PHY PLL */
1768 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1769 {
1770         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1771
1772         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1773                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1774         udelay(1);
1775         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1776                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1777         udelay(1);
1778         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1779                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1780         udelay(1);
1781         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1782                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1783         udelay(1);
1784 }
1785
1786 /* light way to turn on phy clock without reset for NPHY only
1787  *  refer to wlc_bmac_core_phy_clk for full version
1788  */
1789 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1790 {
1791         /* support(necessary for NPHY and HYPHY) only */
1792         if (!WLCISNPHY(wlc_hw->band))
1793                 return;
1794
1795         if (ON == clk)
1796                 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1797         else
1798                 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1799
1800 }
1801
1802 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1803 {
1804         if (ON == clk)
1805                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1806         else
1807                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1808 }
1809
1810 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1811 {
1812         wlc_phy_t *pih = wlc_hw->band->pi;
1813         u32 phy_bw_clkbits;
1814         bool phy_in_reset = false;
1815
1816         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1817
1818         if (pih == NULL)
1819                 return;
1820
1821         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1822
1823         /* Specific reset sequence required for NPHY rev 3 and 4 */
1824         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1825             NREV_LE(wlc_hw->band->phyrev, 4)) {
1826                 /* Set the PHY bandwidth */
1827                 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1828
1829                 udelay(1);
1830
1831                 /* Perform a soft reset of the PHY PLL */
1832                 wlc_bmac_core_phypll_reset(wlc_hw);
1833
1834                 /* reset the PHY */
1835                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1836                                (SICF_PRST | SICF_PCLKE));
1837                 phy_in_reset = true;
1838         } else {
1839
1840                 ai_core_cflags(wlc_hw->sih,
1841                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1842                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1843         }
1844
1845         udelay(2);
1846         wlc_bmac_core_phy_clk(wlc_hw, ON);
1847
1848         if (pih)
1849                 wlc_phy_anacore(pih, ON);
1850 }
1851
1852 /* switch to and initialize new band */
1853 static void
1854 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1855                                 chanspec_t chanspec) {
1856         struct wlc_info *wlc = wlc_hw->wlc;
1857         u32 macintmask;
1858
1859         /* Enable the d11 core before accessing it */
1860         if (!ai_iscoreup(wlc_hw->sih)) {
1861                 ai_core_reset(wlc_hw->sih, 0, 0);
1862                 wlc_mctrl_reset(wlc_hw);
1863         }
1864
1865         macintmask = wlc_setband_inact(wlc, bandunit);
1866
1867         if (!wlc_hw->up)
1868                 return;
1869
1870         wlc_bmac_core_phy_clk(wlc_hw, ON);
1871
1872         /* band-specific initializations */
1873         wlc_bmac_bsinit(wlc, chanspec);
1874
1875         /*
1876          * If there are any pending software interrupt bits,
1877          * then replace these with a harmless nonzero value
1878          * so wlc_dpc() will re-enable interrupts when done.
1879          */
1880         if (wlc->macintstatus)
1881                 wlc->macintstatus = MI_DMAINT;
1882
1883         /* restore macintmask */
1884         brcms_intrsrestore(wlc->wl, macintmask);
1885
1886         /* ucode should still be suspended.. */
1887         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1888 }
1889
1890 /* low-level band switch utility routine */
1891 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1892 {
1893         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1894                 bandunit);
1895
1896         wlc_hw->band = wlc_hw->bandstate[bandunit];
1897
1898         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1899         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1900
1901         /* set gmode core flag */
1902         if (wlc_hw->sbclk && !wlc_hw->noreset) {
1903                 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1904                                ((bandunit == 0) ? SICF_GMODE : 0));
1905         }
1906 }
1907
1908 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1909 {
1910
1911         /* reject unsupported corerev */
1912         if (!VALID_COREREV(wlc_hw->corerev)) {
1913                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1914                           wlc_hw->corerev);
1915                 return false;
1916         }
1917
1918         return true;
1919 }
1920
1921 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1922 {
1923         bool goodboard = true;
1924         uint boardrev = wlc_hw->boardrev;
1925
1926         if (boardrev == 0)
1927                 goodboard = false;
1928         else if (boardrev > 0xff) {
1929                 uint brt = (boardrev & 0xf000) >> 12;
1930                 uint b0 = (boardrev & 0xf00) >> 8;
1931                 uint b1 = (boardrev & 0xf0) >> 4;
1932                 uint b2 = boardrev & 0xf;
1933
1934                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1935                     || (b2 > 9))
1936                         goodboard = false;
1937         }
1938
1939         if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1940                 return goodboard;
1941
1942         return goodboard;
1943 }
1944
1945 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1946 {
1947         const char *varname = "macaddr";
1948         char *macaddr;
1949
1950         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1951         macaddr = getvar(wlc_hw->vars, varname);
1952         if (macaddr != NULL)
1953                 return macaddr;
1954
1955         if (NBANDS_HW(wlc_hw) > 1)
1956                 varname = "et1macaddr";
1957         else
1958                 varname = "il0macaddr";
1959
1960         macaddr = getvar(wlc_hw->vars, varname);
1961         if (macaddr == NULL) {
1962                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1963                           "getvar(%s) not found\n", wlc_hw->unit, varname);
1964         }
1965
1966         return macaddr;
1967 }
1968
1969 /*
1970  * Return true if radio is disabled, otherwise false.
1971  * hw radio disable signal is an external pin, users activate it asynchronously
1972  * this function could be called when driver is down and w/o clock
1973  * it operates on different registers depending on corerev and boardflag.
1974  */
1975 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
1976 {
1977         bool v, clk, xtal;
1978         u32 resetbits = 0, flags = 0;
1979
1980         xtal = wlc_hw->sbclk;
1981         if (!xtal)
1982                 wlc_bmac_xtal(wlc_hw, ON);
1983
1984         /* may need to take core out of reset first */
1985         clk = wlc_hw->clk;
1986         if (!clk) {
1987                 /*
1988                  * mac no longer enables phyclk automatically when driver
1989                  * accesses phyreg throughput mac. This can be skipped since
1990                  * only mac reg is accessed below
1991                  */
1992                 flags |= SICF_PCLKE;
1993
1994                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1995                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
1996                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
1997                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
1998                         wlc_hw->regs =
1999                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2000                                                      0);
2001                 ai_core_reset(wlc_hw->sih, flags, resetbits);
2002                 wlc_mctrl_reset(wlc_hw);
2003         }
2004
2005         v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2006
2007         /* put core back into reset */
2008         if (!clk)
2009                 ai_core_disable(wlc_hw->sih, 0);
2010
2011         if (!xtal)
2012                 wlc_bmac_xtal(wlc_hw, OFF);
2013
2014         return v;
2015 }
2016
2017 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2018 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2019 {
2020         if (wlc_hw->wlc->pub->hw_up)
2021                 return;
2022
2023         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2024
2025         /*
2026          * Enable pll and xtal, initialize the power control registers,
2027          * and force fastclock for the remainder of wlc_up().
2028          */
2029         wlc_bmac_xtal(wlc_hw, ON);
2030         ai_clkctl_init(wlc_hw->sih);
2031         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2032
2033         if (wlc_hw->sih->bustype == PCI_BUS) {
2034                 ai_pci_fixcfg(wlc_hw->sih);
2035
2036                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2037                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2038                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2039                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2040                         wlc_hw->regs =
2041                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2042                                                      0);
2043         }
2044
2045         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2046         wlc_phy_por_inform(wlc_hw->band->pi);
2047
2048         wlc_hw->ucode_loaded = false;
2049         wlc_hw->wlc->pub->hw_up = true;
2050
2051         if ((wlc_hw->boardflags & BFL_FEM)
2052             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2053                 if (!
2054                     (wlc_hw->boardrev >= 0x1250
2055                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2056                         ai_epa_4313war(wlc_hw->sih);
2057         }
2058 }
2059
2060 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2061 {
2062         struct dma_pub *di = wlc_hw->di[fifo];
2063         return dma_rxreset(di);
2064 }
2065
2066 /* d11 core reset
2067  *   ensure fask clock during reset
2068  *   reset dma
2069  *   reset d11(out of reset)
2070  *   reset phy(out of reset)
2071  *   clear software macintstatus for fresh new start
2072  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2073  */
2074 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2075 {
2076         d11regs_t *regs;
2077         uint i;
2078         bool fastclk;
2079         u32 resetbits = 0;
2080
2081         if (flags == WLC_USE_COREFLAGS)
2082                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2083
2084         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2085
2086         regs = wlc_hw->regs;
2087
2088         /* request FAST clock if not on  */
2089         fastclk = wlc_hw->forcefastclk;
2090         if (!fastclk)
2091                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2092
2093         /* reset the dma engines except first time thru */
2094         if (ai_iscoreup(wlc_hw->sih)) {
2095                 for (i = 0; i < NFIFO; i++)
2096                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2097                                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2098                                           "dma_txreset[%d]: cannot stop dma\n",
2099                                            wlc_hw->unit, __func__, i);
2100                         }
2101
2102                 if ((wlc_hw->di[RX_FIFO])
2103                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2104                         wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2105                                   "[%d]: cannot stop dma\n",
2106                                   wlc_hw->unit, __func__, RX_FIFO);
2107                 }
2108         }
2109         /* if noreset, just stop the psm and return */
2110         if (wlc_hw->noreset) {
2111                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2112                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2113                 return;
2114         }
2115
2116         /*
2117          * mac no longer enables phyclk automatically when driver accesses
2118          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2119          * band->pi is invalid. need to enable PHY CLK
2120          */
2121         flags |= SICF_PCLKE;
2122
2123         /* reset the core
2124          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2125          *  is cleared by the core_reset. have to re-request it.
2126          *  This adds some delay and we can optimize it by also requesting fastclk through
2127          *  chipcommon during this period if necessary. But that has to work coordinate
2128          *  with other driver like mips/arm since they may touch chipcommon as well.
2129          */
2130         wlc_hw->clk = false;
2131         ai_core_reset(wlc_hw->sih, flags, resetbits);
2132         wlc_hw->clk = true;
2133         if (wlc_hw->band && wlc_hw->band->pi)
2134                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2135
2136         wlc_mctrl_reset(wlc_hw);
2137
2138         if (PMUCTL_ENAB(wlc_hw->sih))
2139                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2140
2141         wlc_bmac_phy_reset(wlc_hw);
2142
2143         /* turn on PHY_PLL */
2144         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2145
2146         /* clear sw intstatus */
2147         wlc_hw->wlc->macintstatus = 0;
2148
2149         /* restore the clk setting */
2150         if (!fastclk)
2151                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2152 }
2153
2154 /* txfifo sizes needs to be modified(increased) since the newer cores
2155  * have more memory.
2156  */
2157 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2158 {
2159         d11regs_t *regs = wlc_hw->regs;
2160         u16 fifo_nu;
2161         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2162         u16 txfifo_def, txfifo_def1;
2163         u16 txfifo_cmd;
2164
2165         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2166         txfifo_startblk = TXFIFO_START_BLK;
2167
2168         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2169         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2170
2171                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2172                 txfifo_def = (txfifo_startblk & 0xff) |
2173                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2174                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2175                     ((((txfifo_endblk -
2176                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2177                 txfifo_cmd =
2178                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2179
2180                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2181                 W_REG(&regs->xmtfifodef, txfifo_def);
2182                 W_REG(&regs->xmtfifodef1, txfifo_def1);
2183
2184                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2185
2186                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2187         }
2188         /*
2189          * need to propagate to shm location to be in sync since ucode/hw won't
2190          * do this
2191          */
2192         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2193                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2194         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2195                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2196         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2197                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2198                             xmtfifo_sz[TX_AC_BK_FIFO]));
2199         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2200                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2201                             xmtfifo_sz[TX_BCMC_FIFO]));
2202 }
2203
2204 /* d11 core init
2205  *   reset PSM
2206  *   download ucode/PCM
2207  *   let ucode run to suspended
2208  *   download ucode inits
2209  *   config other core registers
2210  *   init dma
2211  */
2212 static void wlc_coreinit(struct wlc_info *wlc)
2213 {
2214         struct wlc_hw_info *wlc_hw = wlc->hw;
2215         d11regs_t *regs;
2216         u32 sflags;
2217         uint bcnint_us;
2218         uint i = 0;
2219         bool fifosz_fixup = false;
2220         int err = 0;
2221         u16 buf[NFIFO];
2222         struct wiphy *wiphy = wlc->wiphy;
2223
2224         regs = wlc_hw->regs;
2225
2226         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2227
2228         /* reset PSM */
2229         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2230
2231         wlc_ucode_download(wlc_hw);
2232         /*
2233          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2234          */
2235         fifosz_fixup = true;
2236
2237         /* let the PSM run to the suspended state, set mode to BSS STA */
2238         W_REG(&regs->macintstatus, -1);
2239         wlc_bmac_mctrl(wlc_hw, ~0,
2240                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2241
2242         /* wait for ucode to self-suspend after auto-init */
2243         SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2244                  1000 * 1000);
2245         if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2246                 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2247                           "suspend!\n", wlc_hw->unit);
2248
2249         wlc_gpio_init(wlc);
2250
2251         sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2252
2253         if (D11REV_IS(wlc_hw->corerev, 23)) {
2254                 if (WLCISNPHY(wlc_hw->band))
2255                         wlc_write_inits(wlc_hw, d11n0initvals16);
2256                 else
2257                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2258                                   " %d\n", __func__, wlc_hw->unit,
2259                                   wlc_hw->corerev);
2260         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2261                 if (WLCISLCNPHY(wlc_hw->band)) {
2262                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2263                 } else {
2264                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2265                                   " %d\n", __func__, wlc_hw->unit,
2266                                   wlc_hw->corerev);
2267                 }
2268         } else {
2269                 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2270                           __func__, wlc_hw->unit, wlc_hw->corerev);
2271         }
2272
2273         /* For old ucode, txfifo sizes needs to be modified(increased) */
2274         if (fifosz_fixup == true) {
2275                 wlc_corerev_fifofixup(wlc_hw);
2276         }
2277
2278         /* check txfifo allocations match between ucode and driver */
2279         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2280         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2281                 i = TX_AC_BE_FIFO;
2282                 err = -1;
2283         }
2284         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2285         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2286                 i = TX_AC_VI_FIFO;
2287                 err = -1;
2288         }
2289         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2290         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2291         buf[TX_AC_BK_FIFO] &= 0xff;
2292         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2293                 i = TX_AC_BK_FIFO;
2294                 err = -1;
2295         }
2296         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2297                 i = TX_AC_VO_FIFO;
2298                 err = -1;
2299         }
2300         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2301         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2302         buf[TX_BCMC_FIFO] &= 0xff;
2303         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2304                 i = TX_BCMC_FIFO;
2305                 err = -1;
2306         }
2307         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2308                 i = TX_ATIM_FIFO;
2309                 err = -1;
2310         }
2311         if (err != 0) {
2312                 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2313                           " driver size %d index %d\n", buf[i],
2314                           wlc_hw->xmtfifo_sz[i], i);
2315         }
2316
2317         /* make sure we can still talk to the mac */
2318         WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
2319
2320         /* band-specific inits done by wlc_bsinit() */
2321
2322         /* Set up frame burst size and antenna swap threshold init values */
2323         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2324         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2325
2326         /* enable one rx interrupt per received frame */
2327         W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2328
2329         /* set the station mode (BSS STA) */
2330         wlc_bmac_mctrl(wlc_hw,
2331                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2332                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2333
2334         /* set up Beacon interval */
2335         bcnint_us = 0x8000 << 10;
2336         W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2337         W_REG(&regs->tsf_cfpstart, bcnint_us);
2338         W_REG(&regs->macintstatus, MI_GP1);
2339
2340         /* write interrupt mask */
2341         W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2342
2343         /* allow the MAC to control the PHY clock (dynamic on/off) */
2344         wlc_bmac_macphyclk_set(wlc_hw, ON);
2345
2346         /* program dynamic clock control fast powerup delay register */
2347         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2348         W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2349
2350         /* tell the ucode the corerev */
2351         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2352
2353         /* tell the ucode MAC capabilities */
2354         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2355                            (u16) (wlc_hw->machwcap & 0xffff));
2356         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2357                            (u16) ((wlc_hw->
2358                                       machwcap >> 16) & 0xffff));
2359
2360         /* write retry limits to SCR, this done after PSM init */
2361         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2362         (void)R_REG(&regs->objaddr);
2363         W_REG(&regs->objdata, wlc_hw->SRL);
2364         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2365         (void)R_REG(&regs->objaddr);
2366         W_REG(&regs->objdata, wlc_hw->LRL);
2367
2368         /* write rate fallback retry limits */
2369         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2370         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2371
2372         AND_REG(&regs->ifs_ctl, 0x0FFF);
2373         W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2374
2375         /* dma initializations */
2376         wlc->txpend16165war = 0;
2377
2378         /* init the tx dma engines */
2379         for (i = 0; i < NFIFO; i++) {
2380                 if (wlc_hw->di[i])
2381                         dma_txinit(wlc_hw->di[i]);
2382         }
2383
2384         /* init the rx dma engine(s) and post receive buffers */
2385         dma_rxinit(wlc_hw->di[RX_FIFO]);
2386         dma_rxfill(wlc_hw->di[RX_FIFO]);
2387 }
2388
2389 /* This function is used for changing the tsf frac register
2390  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2391  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2392  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2393  * HTPHY Formula is 2^26/freq(MHz) e.g.
2394  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2395  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2396  * For spuron: 123MHz -> 2^26/123    = 545600.5
2397  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2398  * For spur off: 120MHz -> 2^26/120    = 559240.5
2399  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2400  */
2401
2402 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2403 {
2404         d11regs_t *regs;
2405         regs = wlc_hw->regs;
2406
2407         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2408             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2409                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2410                         W_REG(&regs->tsf_clk_frac_l, 0x2082);
2411                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2412                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2413                         W_REG(&regs->tsf_clk_frac_l, 0x5341);
2414                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2415                 } else {        /* 120Mhz */
2416                         W_REG(&regs->tsf_clk_frac_l, 0x8889);
2417                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2418                 }
2419         } else if (WLCISLCNPHY(wlc_hw->band)) {
2420                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2421                         W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2422                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2423                 } else {        /* 80Mhz */
2424                         W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2425                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2426                 }
2427         }
2428 }
2429
2430 /* Initialize GPIOs that are controlled by D11 core */
2431 static void wlc_gpio_init(struct wlc_info *wlc)
2432 {
2433         struct wlc_hw_info *wlc_hw = wlc->hw;
2434         d11regs_t *regs;
2435         u32 gc, gm;
2436
2437         regs = wlc_hw->regs;
2438
2439         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2440         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2441
2442         /*
2443          * Common GPIO setup:
2444          *      G0 = LED 0 = WLAN Activity
2445          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2446          *      G2 = LED 2 = WLAN 5 GHz Radio State
2447          *      G4 = radio disable input (HI enabled, LO disabled)
2448          */
2449
2450         gc = gm = 0;
2451
2452         /* Allocate GPIOs for mimo antenna diversity feature */
2453         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2454                 /* Enable antenna diversity, use 2x3 mode */
2455                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2456                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2457                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2458                              MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2459
2460                 /* init superswitch control */
2461                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2462
2463         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2464                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2465                 /*
2466                  * The board itself is powered by these GPIOs
2467                  * (when not sending pattern) so set them high
2468                  */
2469                 OR_REG(&regs->psm_gpio_oe,
2470                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2471                 OR_REG(&regs->psm_gpio_out,
2472                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2473
2474                 /* Enable antenna diversity, use 2x4 mode */
2475                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2476                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2477                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2478                              WLC_BAND_ALL);
2479
2480                 /* Configure the desired clock to be 4Mhz */
2481                 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2482                                    ANTSEL_CLKDIV_4MHZ);
2483         }
2484
2485         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2486         if (wlc_hw->boardflags & BFL_PACTRL)
2487                 gm |= gc |= BOARD_GPIO_PACTRL;
2488
2489         /* apply to gpiocontrol register */
2490         ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2491 }
2492
2493 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2494 {
2495         struct wlc_info *wlc;
2496         wlc = wlc_hw->wlc;
2497
2498         if (wlc_hw->ucode_loaded)
2499                 return;
2500
2501         if (D11REV_IS(wlc_hw->corerev, 23)) {
2502                 if (WLCISNPHY(wlc_hw->band)) {
2503                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2504                                         bcm43xx_16_mimosz);
2505                         wlc_hw->ucode_loaded = true;
2506                 } else
2507                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2508                                   "corerev %d\n",
2509                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2510         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2511                 if (WLCISLCNPHY(wlc_hw->band)) {
2512                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2513                                         bcm43xx_24_lcnsz);
2514                         wlc_hw->ucode_loaded = true;
2515                 } else {
2516                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2517                                   "corerev %d\n",
2518                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2519                 }
2520         }
2521 }
2522
2523 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2524                               const uint nbytes) {
2525         d11regs_t *regs = wlc_hw->regs;
2526         uint i;
2527         uint count;
2528
2529         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2530
2531         count = (nbytes / sizeof(u32));
2532
2533         W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2534         (void)R_REG(&regs->objaddr);
2535         for (i = 0; i < count; i++)
2536                 W_REG(&regs->objdata, ucode[i]);
2537 }
2538
2539 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2540                             const struct d11init *inits)
2541 {
2542         int i;
2543         volatile u8 *base;
2544
2545         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2546
2547         base = (volatile u8 *)wlc_hw->regs;
2548
2549         for (i = 0; inits[i].addr != 0xffff; i++) {
2550                 if (inits[i].size == 2)
2551                         W_REG((u16 *)(base + inits[i].addr),
2552                               inits[i].value);
2553                 else if (inits[i].size == 4)
2554                         W_REG((u32 *)(base + inits[i].addr),
2555                               inits[i].value);
2556         }
2557 }
2558
2559 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2560 {
2561         u16 phyctl;
2562         u16 phytxant = wlc_hw->bmac_phytxant;
2563         u16 mask = PHY_TXC_ANT_MASK;
2564
2565         /* set the Probe Response frame phy control word */
2566         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2567         phyctl = (phyctl & ~mask) | phytxant;
2568         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2569
2570         /* set the Response (ACK/CTS) frame phy control word */
2571         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2572         phyctl = (phyctl & ~mask) | phytxant;
2573         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2574 }
2575
2576 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2577 {
2578         /* update sw state */
2579         wlc_hw->bmac_phytxant = phytxant;
2580
2581         /* push to ucode if up */
2582         if (!wlc_hw->up)
2583                 return;
2584         wlc_ucode_txant_set(wlc_hw);
2585
2586 }
2587
2588 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2589 {
2590         return (u16) wlc_hw->wlc->stf->txant;
2591 }
2592
2593 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2594 {
2595         wlc_hw->antsel_type = antsel_type;
2596
2597         /* Update the antsel type for phy module to use */
2598         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2599 }
2600
2601 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2602 {
2603         bool fatal = false;
2604         uint unit;
2605         uint intstatus, idx;
2606         d11regs_t *regs = wlc_hw->regs;
2607         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2608
2609         unit = wlc_hw->unit;
2610
2611         for (idx = 0; idx < NFIFO; idx++) {
2612                 /* read intstatus register and ignore any non-error bits */
2613                 intstatus =
2614                     R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2615                 if (!intstatus)
2616                         continue;
2617
2618                 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2619                         unit, idx, intstatus);
2620
2621                 if (intstatus & I_RO) {
2622                         wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2623                                   "overflow\n", unit, idx);
2624                         fatal = true;
2625                 }
2626
2627                 if (intstatus & I_PC) {
2628                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2629                                  unit, idx);
2630                         fatal = true;
2631                 }
2632
2633                 if (intstatus & I_PD) {
2634                         wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2635                                   idx);
2636                         fatal = true;
2637                 }
2638
2639                 if (intstatus & I_DE) {
2640                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2641                                   "error\n", unit, idx);
2642                         fatal = true;
2643                 }
2644
2645                 if (intstatus & I_RU) {
2646                         wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2647                                   "underflow\n", idx, unit);
2648                 }
2649
2650                 if (intstatus & I_XU) {
2651                         wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2652                                   "underflow\n", idx, unit);
2653                         fatal = true;
2654                 }
2655
2656                 if (fatal) {
2657                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2658                         break;
2659                 } else
2660                         W_REG(&regs->intctrlregs[idx].intstatus,
2661                               intstatus);
2662         }
2663 }
2664
2665 void wlc_intrson(struct wlc_info *wlc)
2666 {
2667         struct wlc_hw_info *wlc_hw = wlc->hw;
2668         wlc->macintmask = wlc->defmacintmask;
2669         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2670 }
2671
2672 /* callback for siutils.c, which has only wlc handler, no wl
2673  * they both check up, not only because there is no need to off/restore d11 interrupt
2674  *  but also because per-port code may require sync with valid interrupt.
2675  */
2676
2677 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2678 {
2679         if (!wlc->hw->up)
2680                 return 0;
2681
2682         return brcms_intrsoff(wlc->wl);
2683 }
2684
2685 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2686 {
2687         if (!wlc->hw->up)
2688                 return;
2689
2690         brcms_intrsrestore(wlc->wl, macintmask);
2691 }
2692
2693 u32 wlc_intrsoff(struct wlc_info *wlc)
2694 {
2695         struct wlc_hw_info *wlc_hw = wlc->hw;
2696         u32 macintmask;
2697
2698         if (!wlc_hw->clk)
2699                 return 0;
2700
2701         macintmask = wlc->macintmask;   /* isr can still happen */
2702
2703         W_REG(&wlc_hw->regs->macintmask, 0);
2704         (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2705         udelay(1);              /* ensure int line is no longer driven */
2706         wlc->macintmask = 0;
2707
2708         /* return previous macintmask; resolve race between us and our isr */
2709         return wlc->macintstatus ? 0 : macintmask;
2710 }
2711
2712 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2713 {
2714         struct wlc_hw_info *wlc_hw = wlc->hw;
2715         if (!wlc_hw->clk)
2716                 return;
2717
2718         wlc->macintmask = macintmask;
2719         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2720 }
2721
2722 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2723 {
2724         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2725
2726         if (on) {
2727                 /* suspend tx fifos */
2728                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2729                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2730                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2731                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2732
2733                 /* zero the address match register so we do not send ACKs */
2734                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2735                                        null_ether_addr);
2736         } else {
2737                 /* resume tx fifos */
2738                 if (!wlc_hw->wlc->tx_suspended) {
2739                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2740                 }
2741                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2742                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2743                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2744
2745                 /* Restore address */
2746                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2747                                        wlc_hw->etheraddr);
2748         }
2749
2750         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2751
2752         if (on)
2753                 wlc_ucode_mute_override_set(wlc_hw);
2754         else
2755                 wlc_ucode_mute_override_clear(wlc_hw);
2756 }
2757
2758 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2759 {
2760         if (fifo >= NFIFO)
2761                 return -EINVAL;
2762
2763         *blocks = wlc_hw->xmtfifo_sz[fifo];
2764
2765         return 0;
2766 }
2767
2768 /* wlc_bmac_tx_fifo_suspended:
2769  * Check the MAC's tx suspend status for a tx fifo.
2770  *
2771  * When the MAC acknowledges a tx suspend, it indicates that no more
2772  * packets will be transmitted out the radio. This is independent of
2773  * DMA channel suspension---the DMA may have finished suspending, or may still
2774  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2775  * request.
2776  */
2777 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2778 {
2779         /* check that a suspend has been requested and is no longer pending */
2780
2781         /*
2782          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2783          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2784          * chnstatus register.
2785          * The tx fifo suspend completion is independent of the DMA suspend completion and
2786          *   may be acked before or after the DMA is suspended.
2787          */
2788         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2789             (R_REG(&wlc_hw->regs->chnstatus) &
2790              (1 << tx_fifo)) == 0)
2791                 return true;
2792
2793         return false;
2794 }
2795
2796 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2797 {
2798         u8 fifo = 1 << tx_fifo;
2799
2800         /* Two clients of this code, 11h Quiet period and scanning. */
2801
2802         /* only suspend if not already suspended */
2803         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2804                 return;
2805
2806         /* force the core awake only if not already */
2807         if (wlc_hw->suspended_fifos == 0)
2808                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2809
2810         wlc_hw->suspended_fifos |= fifo;
2811
2812         if (wlc_hw->di[tx_fifo]) {
2813                 /* Suspending AMPDU transmissions in the middle can cause underflow
2814                  * which may result in mismatch between ucode and driver
2815                  * so suspend the mac before suspending the FIFO
2816                  */
2817                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2818                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
2819
2820                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2821
2822                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2823                         wlc_enable_mac(wlc_hw->wlc);
2824         }
2825 }
2826
2827 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2828 {
2829         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2830          * here for PIO otherwise the watchdog will catch the inconsistency and fire
2831          */
2832         /* Two clients of this code, 11h Quiet period and scanning. */
2833         if (wlc_hw->di[tx_fifo])
2834                 dma_txresume(wlc_hw->di[tx_fifo]);
2835
2836         /* allow core to sleep again */
2837         if (wlc_hw->suspended_fifos == 0)
2838                 return;
2839         else {
2840                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2841                 if (wlc_hw->suspended_fifos == 0)
2842                         wlc_ucode_wake_override_clear(wlc_hw,
2843                                                       WLC_WAKE_OVERRIDE_TXFIFO);
2844         }
2845 }
2846
2847 /*
2848  * Read and clear macintmask and macintstatus and intstatus registers.
2849  * This routine should be called with interrupts off
2850  * Return:
2851  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
2852  *   0 if the interrupt is not for us, or we are in some special cases;
2853  *   device interrupt status bits otherwise.
2854  */
2855 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2856 {
2857         struct wlc_hw_info *wlc_hw = wlc->hw;
2858         d11regs_t *regs = wlc_hw->regs;
2859         u32 macintstatus;
2860
2861         /* macintstatus includes a DMA interrupt summary bit */
2862         macintstatus = R_REG(&regs->macintstatus);
2863
2864         BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2865                  macintstatus);
2866
2867         /* detect cardbus removed, in power down(suspend) and in reset */
2868         if (DEVICEREMOVED(wlc))
2869                 return -1;
2870
2871         /* DEVICEREMOVED succeeds even when the core is still resetting,
2872          * handle that case here.
2873          */
2874         if (macintstatus == 0xffffffff)
2875                 return 0;
2876
2877         /* defer unsolicited interrupts */
2878         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2879
2880         /* if not for us */
2881         if (macintstatus == 0)
2882                 return 0;
2883
2884         /* interrupts are already turned off for CFE build
2885          * Caution: For CFE Turning off the interrupts again has some undesired
2886          * consequences
2887          */
2888         /* turn off the interrupts */
2889         W_REG(&regs->macintmask, 0);
2890         (void)R_REG(&regs->macintmask); /* sync readback */
2891         wlc->macintmask = 0;
2892
2893         /* clear device interrupts */
2894         W_REG(&regs->macintstatus, macintstatus);
2895
2896         /* MI_DMAINT is indication of non-zero intstatus */
2897         if (macintstatus & MI_DMAINT) {
2898                 /*
2899                  * only fifo interrupt enabled is I_RI in
2900                  * RX_FIFO. If MI_DMAINT is set, assume it
2901                  * is set and clear the interrupt.
2902                  */
2903                 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
2904                       DEF_RXINTMASK);
2905         }
2906
2907         return macintstatus;
2908 }
2909
2910 /* Update wlc->macintstatus and wlc->intstatus[]. */
2911 /* Return true if they are updated successfully. false otherwise */
2912 bool wlc_intrsupd(struct wlc_info *wlc)
2913 {
2914         u32 macintstatus;
2915
2916         /* read and clear macintstatus and intstatus registers */
2917         macintstatus = wlc_intstatus(wlc, false);
2918
2919         /* device is removed */
2920         if (macintstatus == 0xffffffff)
2921                 return false;
2922
2923         /* update interrupt status in software */
2924         wlc->macintstatus |= macintstatus;
2925
2926         return true;
2927 }
2928
2929 /*
2930  * First-level interrupt processing.
2931  * Return true if this was our interrupt, false otherwise.
2932  * *wantdpc will be set to true if further wlc_dpc() processing is required,
2933  * false otherwise.
2934  */
2935 bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2936 {
2937         struct wlc_hw_info *wlc_hw = wlc->hw;
2938         u32 macintstatus;
2939
2940         *wantdpc = false;
2941
2942         if (!wlc_hw->up || !wlc->macintmask)
2943                 return false;
2944
2945         /* read and clear macintstatus and intstatus registers */
2946         macintstatus = wlc_intstatus(wlc, true);
2947
2948         if (macintstatus == 0xffffffff)
2949                 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2950                           " path\n");
2951
2952         /* it is not for us */
2953         if (macintstatus == 0)
2954                 return false;
2955
2956         *wantdpc = true;
2957
2958         /* save interrupt status bits */
2959         wlc->macintstatus = macintstatus;
2960
2961         return true;
2962
2963 }
2964
2965 static bool
2966 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2967 {
2968         /* discard intermediate indications for ucode with one legitimate case:
2969          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2970          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2971          *   transmission count)
2972          */
2973         if (!(txs->status & TX_STATUS_AMPDU)
2974             && (txs->status & TX_STATUS_INTERMEDIATE)) {
2975                 return false;
2976         }
2977
2978         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
2979 }
2980
2981 /* process tx completion events in BMAC
2982  * Return true if more tx status need to be processed. false otherwise.
2983  */
2984 static bool
2985 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
2986 {
2987         bool morepending = false;
2988         struct wlc_info *wlc = wlc_hw->wlc;
2989         d11regs_t *regs;
2990         tx_status_t txstatus, *txs;
2991         u32 s1, s2;
2992         uint n = 0;
2993         /*
2994          * Param 'max_tx_num' indicates max. # tx status to process before
2995          * break out.
2996          */
2997         uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
2998
2999         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3000
3001         txs = &txstatus;
3002         regs = wlc_hw->regs;
3003         while (!(*fatal)
3004                && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
3005
3006                 if (s1 == 0xffffffff) {
3007                         wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
3008                                 wlc_hw->unit, __func__);
3009                         return morepending;
3010                 }
3011
3012                         s2 = R_REG(&regs->frmtxstatus2);
3013
3014                 txs->status = s1 & TXS_STATUS_MASK;
3015                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3016                 txs->sequence = s2 & TXS_SEQ_MASK;
3017                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3018                 txs->lasttxtime = 0;
3019
3020                 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3021
3022                 /* !give others some time to run! */
3023                 if (++n >= max_tx_num)
3024                         break;
3025         }
3026
3027         if (*fatal)
3028                 return 0;
3029
3030         if (n >= max_tx_num)
3031                 morepending = true;
3032
3033         if (!pktq_empty(&wlc->pkt_queue->q))
3034                 wlc_send_q(wlc);
3035
3036         return morepending;
3037 }
3038
3039 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3040 {
3041         struct wlc_hw_info *wlc_hw = wlc->hw;
3042         d11regs_t *regs = wlc_hw->regs;
3043         u32 mc, mi;
3044         struct wiphy *wiphy = wlc->wiphy;
3045
3046         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3047                 wlc_hw->band->bandunit);
3048
3049         /*
3050          * Track overlapping suspend requests
3051          */
3052         wlc_hw->mac_suspend_depth++;
3053         if (wlc_hw->mac_suspend_depth > 1)
3054                 return;
3055
3056         /* force the core awake */
3057         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3058
3059         mc = R_REG(&regs->maccontrol);
3060
3061         if (mc == 0xffffffff) {
3062                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3063                           __func__);
3064                 brcms_down(wlc->wl);
3065                 return;
3066         }
3067         WARN_ON(mc & MCTL_PSM_JMP_0);
3068         WARN_ON(!(mc & MCTL_PSM_RUN));
3069         WARN_ON(!(mc & MCTL_EN_MAC));
3070
3071         mi = R_REG(&regs->macintstatus);
3072         if (mi == 0xffffffff) {
3073                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3074                           __func__);
3075                 brcms_down(wlc->wl);
3076                 return;
3077         }
3078         WARN_ON(mi & MI_MACSSPNDD);
3079
3080         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3081
3082         SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3083                  WLC_MAX_MAC_SUSPEND);
3084
3085         if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3086                 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3087                           " and MI_MACSSPNDD is still not on.\n",
3088                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3089                 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3090                           "psm_brc 0x%04x\n", wlc_hw->unit,
3091                           R_REG(&regs->psmdebug),
3092                           R_REG(&regs->phydebug),
3093                           R_REG(&regs->psm_brc));
3094         }
3095
3096         mc = R_REG(&regs->maccontrol);
3097         if (mc == 0xffffffff) {
3098                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3099                           __func__);
3100                 brcms_down(wlc->wl);
3101                 return;
3102         }
3103         WARN_ON(mc & MCTL_PSM_JMP_0);
3104         WARN_ON(!(mc & MCTL_PSM_RUN));
3105         WARN_ON(mc & MCTL_EN_MAC);
3106 }
3107
3108 void wlc_enable_mac(struct wlc_info *wlc)
3109 {
3110         struct wlc_hw_info *wlc_hw = wlc->hw;
3111         d11regs_t *regs = wlc_hw->regs;
3112         u32 mc, mi;
3113
3114         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3115                 wlc->band->bandunit);
3116
3117         /*
3118          * Track overlapping suspend requests
3119          */
3120         wlc_hw->mac_suspend_depth--;
3121         if (wlc_hw->mac_suspend_depth > 0)
3122                 return;
3123
3124         mc = R_REG(&regs->maccontrol);
3125         WARN_ON(mc & MCTL_PSM_JMP_0);
3126         WARN_ON(mc & MCTL_EN_MAC);
3127         WARN_ON(!(mc & MCTL_PSM_RUN));
3128
3129         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3130         W_REG(&regs->macintstatus, MI_MACSSPNDD);
3131
3132         mc = R_REG(&regs->maccontrol);
3133         WARN_ON(mc & MCTL_PSM_JMP_0);
3134         WARN_ON(!(mc & MCTL_EN_MAC));
3135         WARN_ON(!(mc & MCTL_PSM_RUN));
3136
3137         mi = R_REG(&regs->macintstatus);
3138         WARN_ON(mi & MI_MACSSPNDD);
3139
3140         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3141 }
3142
3143 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3144 {
3145         u8 rate;
3146         u8 rates[8] = {
3147                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3148                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3149         };
3150         u16 entry_ptr;
3151         u16 pctl1;
3152         uint i;
3153
3154         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3155                 return;
3156
3157         /* walk the phy rate table and update the entries */
3158         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3159                 rate = rates[i];
3160
3161                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3162
3163                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3164                 pctl1 =
3165                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3166
3167                 /* modify the value */
3168                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3169                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3170
3171                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3172                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3173                                    pctl1);
3174         }
3175 }
3176
3177 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3178 {
3179         uint i;
3180         u8 plcp_rate = 0;
3181         struct plcp_signal_rate_lookup {
3182                 u8 rate;
3183                 u8 signal_rate;
3184         };
3185         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3186         const struct plcp_signal_rate_lookup rate_lookup[] = {
3187                 {WLC_RATE_6M, 0xB},
3188                 {WLC_RATE_9M, 0xF},
3189                 {WLC_RATE_12M, 0xA},
3190                 {WLC_RATE_18M, 0xE},
3191                 {WLC_RATE_24M, 0x9},
3192                 {WLC_RATE_36M, 0xD},
3193                 {WLC_RATE_48M, 0x8},
3194                 {WLC_RATE_54M, 0xC}
3195         };
3196
3197         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3198                 if (rate == rate_lookup[i].rate) {
3199                         plcp_rate = rate_lookup[i].signal_rate;
3200                         break;
3201                 }
3202         }
3203
3204         /* Find the SHM pointer to the rate table entry by looking in the
3205          * Direct-map Table
3206          */
3207         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3208 }
3209
3210 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3211 {
3212         wlc_hw->hw_stf_ss_opmode = stf_mode;
3213
3214         if (wlc_hw->clk)
3215                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3216 }
3217
3218 void
3219 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3220                   u32 *tsf_h_ptr)
3221 {
3222         d11regs_t *regs = wlc_hw->regs;
3223
3224         /* read the tsf timer low, then high to get an atomic read */
3225         *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3226         *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3227
3228         return;
3229 }
3230
3231 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3232 {
3233         d11regs_t *regs;
3234         u32 w, val;
3235         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3236
3237         BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3238
3239         regs = wlc_hw->regs;
3240
3241         /* Validate dchip register access */
3242
3243         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3244         (void)R_REG(&regs->objaddr);
3245         w = R_REG(&regs->objdata);
3246
3247         /* Can we write and read back a 32bit register? */
3248         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3249         (void)R_REG(&regs->objaddr);
3250         W_REG(&regs->objdata, (u32) 0xaa5555aa);
3251
3252         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3253         (void)R_REG(&regs->objaddr);
3254         val = R_REG(&regs->objdata);
3255         if (val != (u32) 0xaa5555aa) {
3256                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3257                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
3258                 return false;
3259         }
3260
3261         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3262         (void)R_REG(&regs->objaddr);
3263         W_REG(&regs->objdata, (u32) 0x55aaaa55);
3264
3265         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3266         (void)R_REG(&regs->objaddr);
3267         val = R_REG(&regs->objdata);
3268         if (val != (u32) 0x55aaaa55) {
3269                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3270                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
3271                 return false;
3272         }
3273
3274         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3275         (void)R_REG(&regs->objaddr);
3276         W_REG(&regs->objdata, w);
3277
3278         /* clear CFPStart */
3279         W_REG(&regs->tsf_cfpstart, 0);
3280
3281         w = R_REG(&regs->maccontrol);
3282         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3283             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3284                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3285                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3286                           (MCTL_IHR_EN | MCTL_WAKE),
3287                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3288                 return false;
3289         }
3290
3291         return true;
3292 }
3293
3294 #define PHYPLL_WAIT_US  100000
3295
3296 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3297 {
3298         d11regs_t *regs;
3299         u32 tmp;
3300
3301         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3302
3303         tmp = 0;
3304         regs = wlc_hw->regs;
3305
3306         if (on) {
3307                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3308                         OR_REG(&regs->clk_ctl_st,
3309                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3310                                 CCS_ERSRC_REQ_PHYPLL));
3311                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3312                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3313                                  PHYPLL_WAIT_US);
3314
3315                         tmp = R_REG(&regs->clk_ctl_st);
3316                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3317                             (CCS_ERSRC_AVAIL_HT)) {
3318                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3319                                           " PLL failed\n", __func__);
3320                         }
3321                 } else {
3322                         OR_REG(&regs->clk_ctl_st,
3323                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3324                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3325                                   (CCS_ERSRC_AVAIL_D11PLL |
3326                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3327                                  (CCS_ERSRC_AVAIL_D11PLL |
3328                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3329
3330                         tmp = R_REG(&regs->clk_ctl_st);
3331                         if ((tmp &
3332                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3333                             !=
3334                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3335                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3336                                           "PHY PLL failed\n", __func__);
3337                         }
3338                 }
3339         } else {
3340                 /* Since the PLL may be shared, other cores can still be requesting it;
3341                  * so we'll deassert the request but not wait for status to comply.
3342                  */
3343                 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3344                 tmp = R_REG(&regs->clk_ctl_st);
3345         }
3346 }
3347
3348 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3349 {
3350         bool dev_gone;
3351
3352         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3353
3354         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3355
3356         if (dev_gone)
3357                 return;
3358
3359         if (wlc_hw->noreset)
3360                 return;
3361
3362         /* radio off */
3363         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3364
3365         /* turn off analog core */
3366         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3367
3368         /* turn off PHYPLL to save power */
3369         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3370
3371         /* No need to set wlc->pub->radio_active = OFF
3372          * because this function needs down capability and
3373          * radio_active is designed for BCMNODOWN.
3374          */
3375
3376         /* remove gpio controls */
3377         if (wlc_hw->ucode_dbgsel)
3378                 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3379
3380         wlc_hw->clk = false;
3381         ai_core_disable(wlc_hw->sih, 0);
3382         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3383 }
3384
3385 /* power both the pll and external oscillator on/off */
3386 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3387 {
3388         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3389
3390         /* dont power down if plldown is false or we must poll hw radio disable */
3391         if (!want && wlc_hw->pllreq)
3392                 return;
3393
3394         if (wlc_hw->sih)
3395                 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3396
3397         wlc_hw->sbclk = want;
3398         if (!wlc_hw->sbclk) {
3399                 wlc_hw->clk = false;
3400                 if (wlc_hw->band && wlc_hw->band->pi)
3401                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3402         }
3403 }
3404
3405 static void wlc_flushqueues(struct wlc_info *wlc)
3406 {
3407         struct wlc_hw_info *wlc_hw = wlc->hw;
3408         uint i;
3409
3410         wlc->txpend16165war = 0;
3411
3412         /* free any posted tx packets */
3413         for (i = 0; i < NFIFO; i++)
3414                 if (wlc_hw->di[i]) {
3415                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
3416                         TXPKTPENDCLR(wlc, i);
3417                         BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3418                 }
3419
3420         /* free any posted rx packets */
3421         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3422 }
3423
3424 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3425 {
3426         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3427 }
3428
3429 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3430 {
3431         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3432 }
3433
3434 static u16
3435 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3436 {
3437         d11regs_t *regs = wlc_hw->regs;
3438         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3439         volatile u16 *objdata_hi = objdata_lo + 1;
3440         u16 v;
3441
3442         W_REG(&regs->objaddr, sel | (offset >> 2));
3443         (void)R_REG(&regs->objaddr);
3444         if (offset & 2) {
3445                 v = R_REG(objdata_hi);
3446         } else {
3447                 v = R_REG(objdata_lo);
3448         }
3449
3450         return v;
3451 }
3452
3453 static void
3454 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3455 {
3456         d11regs_t *regs = wlc_hw->regs;
3457         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3458         volatile u16 *objdata_hi = objdata_lo + 1;
3459
3460         W_REG(&regs->objaddr, sel | (offset >> 2));
3461         (void)R_REG(&regs->objaddr);
3462         if (offset & 2) {
3463                 W_REG(objdata_hi, v);
3464         } else {
3465                 W_REG(objdata_lo, v);
3466         }
3467 }
3468
3469 /* Copy a buffer to shared memory of specified type .
3470  * SHM 'offset' needs to be an even address and
3471  * Buffer length 'len' must be an even number of bytes
3472  * 'sel' selects the type of memory
3473  */
3474 void
3475 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3476                        int len, u32 sel)
3477 {
3478         u16 v;
3479         const u8 *p = (const u8 *)buf;
3480         int i;
3481
3482         if (len <= 0 || (offset & 1) || (len & 1))
3483                 return;
3484
3485         for (i = 0; i < len; i += 2) {
3486                 v = p[i] | (p[i + 1] << 8);
3487                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3488         }
3489 }
3490
3491 /* Copy a piece of shared memory of specified type to a buffer .
3492  * SHM 'offset' needs to be an even address and
3493  * Buffer length 'len' must be an even number of bytes
3494  * 'sel' selects the type of memory
3495  */
3496 void
3497 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3498                          int len, u32 sel)
3499 {
3500         u16 v;
3501         u8 *p = (u8 *) buf;
3502         int i;
3503
3504         if (len <= 0 || (offset & 1) || (len & 1))
3505                 return;
3506
3507         for (i = 0; i < len; i += 2) {
3508                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3509                 p[i] = v & 0xFF;
3510                 p[i + 1] = (v >> 8) & 0xFF;
3511         }
3512 }
3513
3514 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3515 {
3516         BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3517                 wlc_hw->vars_size);
3518
3519         *buf = wlc_hw->vars;
3520         *len = wlc_hw->vars_size;
3521 }
3522
3523 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3524 {
3525         wlc_hw->SRL = SRL;
3526         wlc_hw->LRL = LRL;
3527
3528         /* write retry limit to SCR, shouldn't need to suspend */
3529         if (wlc_hw->up) {
3530                 W_REG(&wlc_hw->regs->objaddr,
3531                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3532                 (void)R_REG(&wlc_hw->regs->objaddr);
3533                 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3534                 W_REG(&wlc_hw->regs->objaddr,
3535                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3536                 (void)R_REG(&wlc_hw->regs->objaddr);
3537                 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3538         }
3539 }
3540
3541 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3542 {
3543         if (set) {
3544                 if (mboolisset(wlc_hw->pllreq, req_bit))
3545                         return;
3546
3547                 mboolset(wlc_hw->pllreq, req_bit);
3548
3549                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3550                         if (!wlc_hw->sbclk) {
3551                                 wlc_bmac_xtal(wlc_hw, ON);
3552                         }
3553                 }
3554         } else {
3555                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3556                         return;
3557
3558                 mboolclr(wlc_hw->pllreq, req_bit);
3559
3560                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3561                         if (wlc_hw->sbclk) {
3562                                 wlc_bmac_xtal(wlc_hw, OFF);
3563                         }
3564                 }
3565         }
3566
3567         return;
3568 }
3569
3570 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3571 {
3572         u16 table_ptr;
3573         u8 phy_rate, index;
3574
3575         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3576         /* XXX4321 fixup needed ? */
3577         if (IS_OFDM(rate))
3578                 table_ptr = M_RT_DIRMAP_A;
3579         else
3580                 table_ptr = M_RT_DIRMAP_B;
3581
3582         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3583          * the index into the rate table.
3584          */
3585         phy_rate = rate_info[rate] & WLC_RATE_MASK;
3586         index = phy_rate & 0xf;
3587
3588         /* Find the SHM pointer to the rate table entry by looking in the
3589          * Direct-map Table
3590          */
3591         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3592 }
3593
3594 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3595 {
3596         wlc_hw->antsel_avail = antsel_avail;
3597 }