drivers/staging/brcm80211/brcmsmac/bottom_mac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23
  24 #include <defs.h>
  25 #include <brcm_hw_ids.h>
  26 #include <brcmu_wifi.h>
  27 #include <aiutils.h>
  28 #include "srom.h"
  29 #include "otp.h"
  30 #include <brcmu_utils.h>
  31 #include <chipcommon.h>
  32 #include <nicpci.h>
  33 #include "dma.h"
  34
  35 #include "types.h"
  36 #include "pmu.h"
  37 #include "d11.h"
  38 #include "rate.h"
  39 #include "scb.h"
  40 #include "pub.h"
  41 #include "key.h"
  42 #include "phy/phy_hal.h"
  43 #include "channel.h"
  44 #include "main.h"
  45 #include "ucode_loader.h"
  46 #include "antsel.h"
  47 #include "alloc.h"
  48 #include "bottom_mac.h"
  49 #include "mac80211_if.h"
  50
  51 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  52
  53 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  54 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  55 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  56 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  57
  58 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  59
  60 #ifndef BMAC_DUP_TO_REMOVE
  61 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  62
  63 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  64
  65 #endif                          /* BMAC_DUP_TO_REMOVE */
  66
  67 #define DMAREG(wlc_hw, direction, fifonum) \
  68         ((direction == DMA_TX) ? \
  69                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
  70                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
  71
  72 #define APHY_SLOT_TIME          9
  73 #define BPHY_SLOT_TIME          20
  74
  75 /*
  76  * The following table lists the buffer memory allocated to xmt fifos in HW.
  77  * the size is in units of 256bytes(one block), total size is HW dependent
  78  * ucode has default fifo partition, sw can overwrite if necessary
  79  *
  80  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  81  * the twiki is updated before making changes.
  82  */
  83
  84 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
  85
  86 static u16 xmtfifo_sz[][NFIFO] = {
  87         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  88         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  89         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  90         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  91         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  92 };
  93
  94 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
  95 static void wlc_coreinit(struct wlc_info *wlc);
  96
  97 /* used by wlc_wakeucode_init() */
  98 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
  99                             const struct d11init *inits);
 100 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 101                             const uint nbytes);
 102 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 103 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 104
 105 /* used by wlc_dpc() */
 106 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 107                                 u32 s2);
 108 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 109 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 110
 111 /* used by wlc_down() */
 112 static void wlc_flushqueues(struct wlc_info *wlc);
 113
 114 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 115 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 116 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 117 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
 118                                        uint tx_fifo);
 119 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 120 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 121
 122 /* Low Level Prototypes */
 123 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
 124 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
 125 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
 126 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 127                                    u32 sel);
 128 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 129                                   u16 v, u32 sel);
 130 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
 131 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 132 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 133 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 134 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 135 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 136 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
 137 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 138 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 139 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 140 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
 141 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 142 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 143 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 144 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 145 static void wlc_gpio_init(struct wlc_info *wlc);
 146 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 147                                       int len);
 148 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 149                                       int len);
 150 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 151 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 152 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 153                              chanspec_t chanspec);
 154 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 155                                         bool shortslot);
 156 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 157 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 158                                              u8 rate);
 159
 160 /* === Low Level functions === */
 161
 162 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 163 {
 164         wlc_hw->shortslot = shortslot;
 165
 166         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 167                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 168                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 169                 wlc_enable_mac(wlc_hw->wlc);
 170         }
 171 }
 172
 173 /*
 174  * Update the slot timing for standard 11b/g (20us slots)
 175  * or shortslot 11g (9us slots)
 176  * The PSM needs to be suspended for this call.
 177  */
 178 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 179                                         bool shortslot)
 180 {
 181         d11regs_t *regs;
 182
 183         regs = wlc_hw->regs;
 184
 185         if (shortslot) {
 186                 /* 11g short slot: 11a timing */
 187                 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
 188                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 189         } else {
 190                 /* 11g long slot: 11b timing */
 191                 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
 192                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 193         }
 194 }
 195
 196 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 197 {
 198         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
 199
 200         /* init microcode host flags */
 201         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 202
 203         /* do band-specific ucode IHR, SHM, and SCR inits */
 204         if (D11REV_IS(wlc_hw->corerev, 23)) {
 205                 if (WLCISNPHY(wlc_hw->band)) {
 206                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 207                 } else {
 208                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
 209                                   " %d\n", __func__, wlc_hw->unit,
 210                                   wlc_hw->corerev);
 211                 }
 212         } else {
 213                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 214                         if (WLCISLCNPHY(wlc_hw->band)) {
 215                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 216                         } else
 217                                 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
 218                                           " core rev %d\n", __func__,
 219                                           wlc_hw->unit, wlc_hw->corerev);
 220                 } else {
 221                         wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
 222                                 __func__, wlc_hw->unit, wlc_hw->corerev);
 223                 }
 224         }
 225 }
 226
 227 /* switch to new band but leave it inactive */
 228 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 229 {
 230         struct wlc_hw_info *wlc_hw = wlc->hw;
 231         u32 macintmask;
 232
 233         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 234
 235         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
 236
 237         /* disable interrupts */
 238         macintmask = brcms_intrsoff(wlc->wl);
 239
 240         /* radio off */
 241         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 242
 243         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 244
 245         wlc_setxband(wlc_hw, bandunit);
 246
 247         return macintmask;
 248 }
 249
 250 /* Process received frames */
 251 /*
 252  * Return true if more frames need to be processed. false otherwise.
 253  * Param 'bound' indicates max. # frames to process before break out.
 254  */
 255 static bool
 256 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 257 {
 258         struct sk_buff *p;
 259         struct sk_buff *head = NULL;
 260         struct sk_buff *tail = NULL;
 261         uint n = 0;
 262         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 263         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 264
 265         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
 266         /* gather received frames */
 267         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 268
 269                 if (!tail)
 270                         head = tail = p;
 271                 else {
 272                         tail->prev = p;
 273                         tail = p;
 274                 }
 275
 276                 /* !give others some time to run! */
 277                 if (++n >= bound_limit)
 278                         break;
 279         }
 280
 281         /* post more rbufs */
 282         dma_rxfill(wlc_hw->di[fifo]);
 283
 284         /* process each frame */
 285         while ((p = head) != NULL) {
 286                 head = head->prev;
 287                 p->prev = NULL;
 288
 289                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 290
 291                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 292                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 293
 294                 wlc_recv(wlc_hw->wlc, p);
 295         }
 296
 297         return n >= bound_limit;
 298 }
 299
 300 /* second-level interrupt processing
 301  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 302  *   Param 'bounded' indicates if applicable loops should be bounded.
 303  */
 304 bool wlc_dpc(struct wlc_info *wlc, bool bounded)
 305 {
 306         u32 macintstatus;
 307         struct wlc_hw_info *wlc_hw = wlc->hw;
 308         d11regs_t *regs = wlc_hw->regs;
 309         bool fatal = false;
 310         struct wiphy *wiphy = wlc->wiphy;
 311
 312         if (DEVICEREMOVED(wlc)) {
 313                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
 314                           __func__);
 315                 brcms_down(wlc->wl);
 316                 return false;
 317         }
 318
 319         /* grab and clear the saved software intstatus bits */
 320         macintstatus = wlc->macintstatus;
 321         wlc->macintstatus = 0;
 322
 323         BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
 324                wlc_hw->unit, macintstatus);
 325
 326         WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
 327
 328         /* BCN template is available */
 329         /* ZZZ: Use AP_ACTIVE ? */
 330         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
 331             && (macintstatus & MI_BCNTPL)) {
 332                 wlc_update_beacon(wlc);
 333         }
 334
 335         /* PMQ entry addition */
 336         if (macintstatus & MI_PMQ) {
 337         }
 338
 339         /* tx status */
 340         if (macintstatus & MI_TFS) {
 341                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 342                         wlc->macintstatus |= MI_TFS;
 343                 if (fatal) {
 344                         wiphy_err(wiphy, "MI_TFS: fatal\n");
 345                         goto fatal;
 346                 }
 347         }
 348
 349         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 350                 wlc_tbtt(wlc, regs);
 351
 352         /* ATIM window end */
 353         if (macintstatus & MI_ATIMWINEND) {
 354                 BCMMSG(wlc->wiphy, "end of ATIM window\n");
 355                 OR_REG(&regs->maccommand, wlc->qvalid);
 356                 wlc->qvalid = 0;
 357         }
 358
 359         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 360         if (macintstatus & MI_DMAINT) {
 361                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 362                         wlc->macintstatus |= MI_DMAINT;
 363                 }
 364         }
 365
 366         /* TX FIFO suspend/flush completion */
 367         if (macintstatus & MI_TXSTOP) {
 368                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 369                         /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
 370                 }
 371         }
 372
 373         /* noise sample collected */
 374         if (macintstatus & MI_BG_NOISE) {
 375                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 376         }
 377
 378         if (macintstatus & MI_GP0) {
 379                 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
 380                         "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
 381
 382                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 383                                         __func__, wlc_hw->sih->chip,
 384                                         wlc_hw->sih->chiprev);
 385                 /* big hammer */
 386                 brcms_init(wlc->wl);
 387         }
 388
 389         /* gptimer timeout */
 390         if (macintstatus & MI_TO) {
 391                 W_REG(&regs->gptimer, 0);
 392         }
 393
 394         if (macintstatus & MI_RFDISABLE) {
 395                 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
 396                        " RF Disable Input\n", wlc_hw->unit);
 397                 brcms_rfkill_set_hw_state(wlc->wl);
 398         }
 399
 400         /* send any enq'd tx packets. Just makes sure to jump start tx */
 401         if (!pktq_empty(&wlc->pkt_queue->q))
 402                 wlc_send_q(wlc);
 403
 404         /* it isn't done and needs to be resched if macintstatus is non-zero */
 405         return wlc->macintstatus != 0;
 406
 407  fatal:
 408         brcms_init(wlc->wl);
 409         return wlc->macintstatus != 0;
 410 }
 411
 412 /* common low-level watchdog code */
 413 void wlc_bmac_watchdog(void *arg)
 414 {
 415         struct wlc_info *wlc = (struct wlc_info *) arg;
 416         struct wlc_hw_info *wlc_hw = wlc->hw;
 417
 418         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 419
 420         if (!wlc_hw->up)
 421                 return;
 422
 423         /* increment second count */
 424         wlc_hw->now++;
 425
 426         /* Check for FIFO error interrupts */
 427         wlc_bmac_fifoerrors(wlc_hw);
 428
 429         /* make sure RX dma has buffers */
 430         dma_rxfill(wlc->hw->di[RX_FIFO]);
 431
 432         wlc_phy_watchdog(wlc_hw->band->pi);
 433 }
 434
 435 void
 436 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 437                       bool mute, struct txpwr_limits *txpwr)
 438 {
 439         uint bandunit;
 440
 441         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
 442
 443         wlc_hw->chanspec = chanspec;
 444
 445         /* Switch bands if necessary */
 446         if (NBANDS_HW(wlc_hw) > 1) {
 447                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 448                 if (wlc_hw->band->bandunit != bandunit) {
 449                         /* wlc_bmac_setband disables other bandunit,
 450                          *  use light band switch if not up yet
 451                          */
 452                         if (wlc_hw->up) {
 453                                 wlc_phy_chanspec_radio_set(wlc_hw->
 454                                                            bandstate[bandunit]->
 455                                                            pi, chanspec);
 456                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 457                         } else {
 458                                 wlc_setxband(wlc_hw, bandunit);
 459                         }
 460                 }
 461         }
 462
 463         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 464
 465         if (!wlc_hw->up) {
 466                 if (wlc_hw->clk)
 467                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 468                                                   chanspec);
 469                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 470         } else {
 471                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 472                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 473
 474                 /* Update muting of the channel */
 475                 wlc_bmac_mute(wlc_hw, mute, 0);
 476         }
 477 }
 478
 479 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 480 {
 481         state->machwcap = wlc_hw->machwcap;
 482
 483         return 0;
 484 }
 485
 486 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 487 {
 488         uint i;
 489         char name[8];
 490         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 491         u16 pio_mhf2 = 0;
 492         struct wlc_hw_info *wlc_hw = wlc->hw;
 493         uint unit = wlc_hw->unit;
 494         wlc_tunables_t *tune = wlc->pub->tunables;
 495         struct wiphy *wiphy = wlc->wiphy;
 496
 497         /* name and offsets for dma_attach */
 498         snprintf(name, sizeof(name), "wl%d", unit);
 499
 500         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 501                 uint addrwidth;
 502                 int dma_attach_err = 0;
 503                 /* Find out the DMA addressing capability and let OS know
 504                  * All the channels within one DMA core have 'common-minimum' same
 505                  * capability
 506                  */
 507                 addrwidth =
 508                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 509
 510                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 511                         wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
 512                                   "resources failed\n", unit);
 513                         return false;
 514                 }
 515
 516                 /*
 517                  * FIFO 0
 518                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 519                  * RX: RX_FIFO (RX data packets)
 520                  */
 521                 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
 522                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 523                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 524                                            (wme ? tune->ntxd : 0), tune->nrxd,
 525                                            tune->rxbufsz, -1, tune->nrxbufpost,
 526                                            WL_HWRXOFF, &brcm_msg_level);
 527                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 528
 529                 /*
 530                  * FIFO 1
 531                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 532                  *   (legacy) TX_DATA_FIFO (TX data packets)
 533                  * RX: UNUSED
 534                  */
 535                 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
 536                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 537                                            tune->ntxd, 0, 0, -1, 0, 0,
 538                                            &brcm_msg_level);
 539                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 540
 541                 /*
 542                  * FIFO 2
 543                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 544                  * RX: UNUSED
 545                  */
 546                 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
 547                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 548                                            tune->ntxd, 0, 0, -1, 0, 0,
 549                                            &brcm_msg_level);
 550                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 551                 /*
 552                  * FIFO 3
 553                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 554                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 555                  */
 556                 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
 557                                            DMAREG(wlc_hw, DMA_TX, 3),
 558                                            NULL, tune->ntxd, 0, 0, -1,
 559                                            0, 0, &brcm_msg_level);
 560                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 561 /* Cleaner to leave this as if with AP defined */
 562
 563                 if (dma_attach_err) {
 564                         wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
 565                                   "\n", unit);
 566                         return false;
 567                 }
 568
 569                 /* get pointer to dma engine tx flow control variable */
 570                 for (i = 0; i < NFIFO; i++)
 571                         if (wlc_hw->di[i])
 572                                 wlc_hw->txavail[i] =
 573                                     (uint *) dma_getvar(wlc_hw->di[i],
 574                                                         "&txavail");
 575         }
 576
 577         /* initial ucode host flags */
 578         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 579
 580         return true;
 581 }
 582
 583 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 584 {
 585         uint j;
 586
 587         for (j = 0; j < NFIFO; j++) {
 588                 if (wlc_hw->di[j]) {
 589                         dma_detach(wlc_hw->di[j]);
 590                         wlc_hw->di[j] = NULL;
 591                 }
 592         }
 593 }
 594
 595 /* low level attach
 596  *    run backplane attach, init nvram
 597  *    run phy attach
 598  *    initialize software state for each core and band
 599  *    put the whole chip in reset(driver down state), no clock
 600  */
 601 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 602                     bool piomode, void *regsva, uint bustype, void *btparam)
 603 {
 604         struct wlc_hw_info *wlc_hw;
 605         d11regs_t *regs;
 606         char *macaddr = NULL;
 607         char *vars;
 608         uint err = 0;
 609         uint j;
 610         bool wme = false;
 611         shared_phy_params_t sha_params;
 612         struct wiphy *wiphy = wlc->wiphy;
 613
 614         BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
 615                 device);
 616
 617         wme = true;
 618
 619         wlc_hw = wlc->hw;
 620         wlc_hw->wlc = wlc;
 621         wlc_hw->unit = unit;
 622         wlc_hw->band = wlc_hw->bandstate[0];
 623         wlc_hw->_piomode = piomode;
 624
 625         /* populate struct wlc_hw_info with default values  */
 626         wlc_bmac_info_init(wlc_hw);
 627
 628         /*
 629          * Do the hardware portion of the attach.
 630          * Also initialize software state that depends on the particular hardware
 631          * we are running.
 632          */
 633         wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
 634                                 &wlc_hw->vars, &wlc_hw->vars_size);
 635         if (wlc_hw->sih == NULL) {
 636                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
 637                           unit);
 638                 err = 11;
 639                 goto fail;
 640         }
 641         vars = wlc_hw->vars;
 642
 643         /*
 644          * Get vendid/devid nvram overwrites, which could be different
 645          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 646          * SDIO_BUS, and SROMless devices on PCI_BUS.
 647          */
 648 #ifdef BCMBUSTYPE
 649         bustype = BCMBUSTYPE;
 650 #endif
 651         if (bustype != SI_BUS) {
 652                 char *var;
 653
 654                 var = getvar(vars, "vendid");
 655                 if (var) {
 656                         vendor = (u16) simple_strtoul(var, NULL, 0);
 657                         wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
 658                                   vendor);
 659                 }
 660                 var = getvar(vars, "devid");
 661                 if (var) {
 662                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 663                         if (devid != 0xffff) {
 664                                 device = devid;
 665                                 wiphy_err(wiphy, "Overriding device id = 0x%x"
 666                                           "\n", device);
 667                         }
 668                 }
 669
 670                 /* verify again the device is supported */
 671                 if (!wlc_chipmatch(vendor, device)) {
 672                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
 673                                 "vendor/device (0x%x/0x%x)\n",
 674                                  unit, vendor, device);
 675                         err = 12;
 676                         goto fail;
 677                 }
 678         }
 679
 680         wlc_hw->vendorid = vendor;
 681         wlc_hw->deviceid = device;
 682
 683         /* set bar0 window to point at D11 core */
 684         wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 685         wlc_hw->corerev = ai_corerev(wlc_hw->sih);
 686
 687         regs = wlc_hw->regs;
 688
 689         wlc->regs = wlc_hw->regs;
 690
 691         /* validate chip, chiprev and corerev */
 692         if (!wlc_isgoodchip(wlc_hw)) {
 693                 err = 13;
 694                 goto fail;
 695         }
 696
 697         /* initialize power control registers */
 698         ai_clkctl_init(wlc_hw->sih);
 699
 700         /* request fastclock and force fastclock for the rest of attach
 701          * bring the d11 core out of reset.
 702          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 703          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 704          */
 705         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 706         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 707
 708         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 709                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
 710                         "failed\n", unit);
 711                 err = 14;
 712                 goto fail;
 713         }
 714
 715         /* get the board rev, used just below */
 716         j = getintvar(vars, "boardrev");
 717         /* promote srom boardrev of 0xFF to 1 */
 718         if (j == BOARDREV_PROMOTABLE)
 719                 j = BOARDREV_PROMOTED;
 720         wlc_hw->boardrev = (u16) j;
 721         if (!wlc_validboardtype(wlc_hw)) {
 722                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
 723                         "board type (0x%x)" " or revision level (0x%x)\n",
 724                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 725                 err = 15;
 726                 goto fail;
 727         }
 728         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 729         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 730         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 731
 732         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 733                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 734
 735         if ((wlc_hw->sih->bustype == PCI_BUS)
 736             && (ai_pci_war16165(wlc_hw->sih)))
 737                 wlc->war16165 = true;
 738
 739         /* check device id(srom, nvram etc.) to set bands */
 740         if (wlc_hw->deviceid == BCM43224_D11N_ID ||
 741             wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
 742                 /* Dualband boards */
 743                 wlc_hw->_nbands = 2;
 744         } else
 745                 wlc_hw->_nbands = 1;
 746
 747         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 748                 wlc_hw->_nbands = 1;
 749
 750         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 751          * init of these values
 752          */
 753         wlc->vendorid = wlc_hw->vendorid;
 754         wlc->deviceid = wlc_hw->deviceid;
 755         wlc->pub->sih = wlc_hw->sih;
 756         wlc->pub->corerev = wlc_hw->corerev;
 757         wlc->pub->sromrev = wlc_hw->sromrev;
 758         wlc->pub->boardrev = wlc_hw->boardrev;
 759         wlc->pub->boardflags = wlc_hw->boardflags;
 760         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 761         wlc->pub->_nbands = wlc_hw->_nbands;
 762
 763         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 764
 765         if (wlc_hw->physhim == NULL) {
 766                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
 767                         "failed\n", unit);
 768                 err = 25;
 769                 goto fail;
 770         }
 771
 772         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 773         sha_params.sih = wlc_hw->sih;
 774         sha_params.physhim = wlc_hw->physhim;
 775         sha_params.unit = unit;
 776         sha_params.corerev = wlc_hw->corerev;
 777         sha_params.vars = vars;
 778         sha_params.vid = wlc_hw->vendorid;
 779         sha_params.did = wlc_hw->deviceid;
 780         sha_params.chip = wlc_hw->sih->chip;
 781         sha_params.chiprev = wlc_hw->sih->chiprev;
 782         sha_params.chippkg = wlc_hw->sih->chippkg;
 783         sha_params.sromrev = wlc_hw->sromrev;
 784         sha_params.boardtype = wlc_hw->sih->boardtype;
 785         sha_params.boardrev = wlc_hw->boardrev;
 786         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 787         sha_params.boardflags = wlc_hw->boardflags;
 788         sha_params.boardflags2 = wlc_hw->boardflags2;
 789         sha_params.bustype = wlc_hw->sih->bustype;
 790         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 791
 792         /* alloc and save pointer to shared phy state area */
 793         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 794         if (!wlc_hw->phy_sh) {
 795                 err = 16;
 796                 goto fail;
 797         }
 798
 799         /* initialize software state for each core and band */
 800         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 801                 /*
 802                  * band0 is always 2.4Ghz
 803                  * band1, if present, is 5Ghz
 804                  */
 805
 806                 /* So if this is a single band 11a card, use band 1 */
 807                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 808                         j = BAND_5G_INDEX;
 809
 810                 wlc_setxband(wlc_hw, j);
 811
 812                 wlc_hw->band->bandunit = j;
 813                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 814                 wlc->band->bandunit = j;
 815                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 816                 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
 817
 818                 wlc_hw->machwcap = R_REG(&regs->machwcap);
 819                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 820
 821                 /* init tx fifo size */
 822                 wlc_hw->xmtfifo_sz =
 823                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 824
 825                 /* Get a phy for this band */
 826                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 827                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
 828                         wlc->wiphy);
 829                 if (wlc_hw->band->pi == NULL) {
 830                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
 831                                   "attach failed\n", unit);
 832                         err = 17;
 833                         goto fail;
 834                 }
 835
 836                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 837
 838                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 839                                        &wlc_hw->band->phyrev,
 840                                        &wlc_hw->band->radioid,
 841                                        &wlc_hw->band->radiorev);
 842                 wlc_hw->band->abgphy_encore =
 843                     wlc_phy_get_encore(wlc_hw->band->pi);
 844                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 845                 wlc_hw->band->core_flags =
 846                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 847
 848                 /* verify good phy_type & supported phy revision */
 849                 if (WLCISNPHY(wlc_hw->band)) {
 850                         if (NCONF_HAS(wlc_hw->band->phyrev))
 851                                 goto good_phy;
 852                         else
 853                                 goto bad_phy;
 854                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 855                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 856                                 goto good_phy;
 857                         else
 858                                 goto bad_phy;
 859                 } else {
 860  bad_phy:
 861                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
 862                                   "phy type/rev (%d/%d)\n", unit,
 863                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
 864                         err = 18;
 865                         goto fail;
 866                 }
 867
 868  good_phy:
 869                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 870                  * high level attach. However we can not make that change until all low level access
 871                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 872                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 873                  * low only init when all fns updated.
 874                  */
 875                 wlc->band->pi = wlc_hw->band->pi;
 876                 wlc->band->phytype = wlc_hw->band->phytype;
 877                 wlc->band->phyrev = wlc_hw->band->phyrev;
 878                 wlc->band->radioid = wlc_hw->band->radioid;
 879                 wlc->band->radiorev = wlc_hw->band->radiorev;
 880
 881                 /* default contention windows size limits */
 882                 wlc_hw->band->CWmin = APHY_CWMIN;
 883                 wlc_hw->band->CWmax = PHY_CWMAX;
 884
 885                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 886                         err = 19;
 887                         goto fail;
 888                 }
 889         }
 890
 891         /* disable core to match driver "down" state */
 892         wlc_coredisable(wlc_hw);
 893
 894         /* Match driver "down" state */
 895         if (wlc_hw->sih->bustype == PCI_BUS)
 896                 ai_pci_down(wlc_hw->sih);
 897
 898         /* register sb interrupt callback functions */
 899         ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 900                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 901
 902         /* turn off pll and xtal to match driver "down" state */
 903         wlc_bmac_xtal(wlc_hw, OFF);
 904
 905         /* *********************************************************************
 906          * The hardware is in the DOWN state at this point. D11 core
 907          * or cores are in reset with clocks off, and the board PLLs
 908          * are off if possible.
 909          *
 910          * Beyond this point, wlc->sbclk == false and chip registers
 911          * should not be touched.
 912          *********************************************************************
 913          */
 914
 915         /* init etheraddr state variables */
 916         macaddr = wlc_get_macaddr(wlc_hw);
 917         if (macaddr == NULL) {
 918                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
 919                           unit);
 920                 err = 21;
 921                 goto fail;
 922         }
 923         brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
 924         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 925             is_zero_ether_addr(wlc_hw->etheraddr)) {
 926                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
 927                           unit, macaddr);
 928                 err = 22;
 929                 goto fail;
 930         }
 931
 932         BCMMSG(wlc->wiphy,
 933                  "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 934                  wlc_hw->deviceid, wlc_hw->_nbands,
 935                  wlc_hw->sih->boardtype, macaddr);
 936
 937         return err;
 938
 939  fail:
 940         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
 941                   err);
 942         return err;
 943 }
 944
 945 /*
 946  * Initialize wlc_info default values ...
 947  * may get overrides later in this function
 948  *  BMAC_NOTES, move low out and resolve the dangling ones
 949  */
 950 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
 951 {
 952         struct wlc_info *wlc = wlc_hw->wlc;
 953
 954         /* set default sw macintmask value */
 955         wlc->defmacintmask = DEF_MACINTMASK;
 956
 957         /* various 802.11g modes */
 958         wlc_hw->shortslot = false;
 959
 960         wlc_hw->SFBL = RETRY_SHORT_FB;
 961         wlc_hw->LFBL = RETRY_LONG_FB;
 962
 963         /* default mac retry limits */
 964         wlc_hw->SRL = RETRY_SHORT_DEF;
 965         wlc_hw->LRL = RETRY_LONG_DEF;
 966         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
 967 }
 968
 969 /*
 970  * low level detach
 971  */
 972 int wlc_bmac_detach(struct wlc_info *wlc)
 973 {
 974         uint i;
 975         struct wlc_hwband *band;
 976         struct wlc_hw_info *wlc_hw = wlc->hw;
 977         int callbacks;
 978
 979         callbacks = 0;
 980
 981         if (wlc_hw->sih) {
 982                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
 983                  * interrupt object may has been freed. this must be done before sb core switch
 984                  */
 985                 ai_deregister_intr_callback(wlc_hw->sih);
 986
 987                 if (wlc_hw->sih->bustype == PCI_BUS)
 988                         ai_pci_sleep(wlc_hw->sih);
 989         }
 990
 991         wlc_bmac_detach_dmapio(wlc_hw);
 992
 993         band = wlc_hw->band;
 994         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
 995                 if (band->pi) {
 996                         /* Detach this band's phy */
 997                         wlc_phy_detach(band->pi);
 998                         band->pi = NULL;
 999                 }
1000                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1001         }
1002
1003         /* Free shared phy state */
1004         wlc_phy_shared_detach(wlc_hw->phy_sh);
1005
1006         wlc_phy_shim_detach(wlc_hw->physhim);
1007
1008         /* free vars */
1009         kfree(wlc_hw->vars);
1010         wlc_hw->vars = NULL;
1011
1012         if (wlc_hw->sih) {
1013                 ai_detach(wlc_hw->sih);
1014                 wlc_hw->sih = NULL;
1015         }
1016
1017         return callbacks;
1018
1019 }
1020
1021 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1022 {
1023         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1024
1025         /* reset the core */
1026         if (!DEVICEREMOVED(wlc_hw->wlc))
1027                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1028
1029         /* purge the dma rings */
1030         wlc_flushqueues(wlc_hw->wlc);
1031
1032         wlc_reset_bmac_done(wlc_hw->wlc);
1033 }
1034
1035 void
1036 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1037                           bool mute) {
1038         u32 macintmask;
1039         bool fastclk;
1040         struct wlc_info *wlc = wlc_hw->wlc;
1041
1042         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1043
1044         /* request FAST clock if not on */
1045         fastclk = wlc_hw->forcefastclk;
1046         if (!fastclk)
1047                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1048
1049         /* disable interrupts */
1050         macintmask = brcms_intrsoff(wlc->wl);
1051
1052         /* set up the specified band and chanspec */
1053         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1054         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1055
1056         /* do one-time phy inits and calibration */
1057         wlc_phy_cal_init(wlc_hw->band->pi);
1058
1059         /* core-specific initialization */
1060         wlc_coreinit(wlc);
1061
1062         /* suspend the tx fifos and mute the phy for preism cac time */
1063         if (mute)
1064                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1065
1066         /* band-specific inits */
1067         wlc_bmac_bsinit(wlc, chanspec);
1068
1069         /* restore macintmask */
1070         brcms_intrsrestore(wlc->wl, macintmask);
1071
1072         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1073          * and wlc_enable_mac() will clear this override bit.
1074          */
1075         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1076
1077         /*
1078          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1079          */
1080         wlc_hw->mac_suspend_depth = 1;
1081
1082         /* restore the clk */
1083         if (!fastclk)
1084                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1085 }
1086
1087 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1088 {
1089         uint coremask;
1090
1091         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1092
1093         /*
1094          * Enable pll and xtal, initialize the power control registers,
1095          * and force fastclock for the remainder of wlc_up().
1096          */
1097         wlc_bmac_xtal(wlc_hw, ON);
1098         ai_clkctl_init(wlc_hw->sih);
1099         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1100
1101         /*
1102          * Configure pci/pcmcia here instead of in wlc_attach()
1103          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1104          */
1105         coremask = (1 << wlc_hw->wlc->core->coreidx);
1106
1107         if (wlc_hw->sih->bustype == PCI_BUS)
1108                 ai_pci_setup(wlc_hw->sih, coremask);
1109
1110         /*
1111          * Need to read the hwradio status here to cover the case where the system
1112          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1113          */
1114         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1115                 /* put SB PCI in down state again */
1116                 if (wlc_hw->sih->bustype == PCI_BUS)
1117                         ai_pci_down(wlc_hw->sih);
1118                 wlc_bmac_xtal(wlc_hw, OFF);
1119                 return -ENOMEDIUM;
1120         }
1121
1122         if (wlc_hw->sih->bustype == PCI_BUS)
1123                 ai_pci_up(wlc_hw->sih);
1124
1125         /* reset the d11 core */
1126         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1127
1128         return 0;
1129 }
1130
1131 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1132 {
1133         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1134
1135         wlc_hw->up = true;
1136         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1137
1138         /* FULLY enable dynamic power control and d11 core interrupt */
1139         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1140         brcms_intrson(wlc_hw->wlc->wl);
1141         return 0;
1142 }
1143
1144 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1145 {
1146         bool dev_gone;
1147         uint callbacks = 0;
1148
1149         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1150
1151         if (!wlc_hw->up)
1152                 return callbacks;
1153
1154         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1155
1156         /* disable interrupts */
1157         if (dev_gone)
1158                 wlc_hw->wlc->macintmask = 0;
1159         else {
1160                 /* now disable interrupts */
1161                 brcms_intrsoff(wlc_hw->wlc->wl);
1162
1163                 /* ensure we're running on the pll clock again */
1164                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1165         }
1166         /* down phy at the last of this stage */
1167         callbacks += wlc_phy_down(wlc_hw->band->pi);
1168
1169         return callbacks;
1170 }
1171
1172 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1173 {
1174         uint callbacks = 0;
1175         bool dev_gone;
1176
1177         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1178
1179         if (!wlc_hw->up)
1180                 return callbacks;
1181
1182         wlc_hw->up = false;
1183         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1184
1185         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1186
1187         if (dev_gone) {
1188                 wlc_hw->sbclk = false;
1189                 wlc_hw->clk = false;
1190                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1191
1192                 /* reclaim any posted packets */
1193                 wlc_flushqueues(wlc_hw->wlc);
1194         } else {
1195
1196                 /* Reset and disable the core */
1197                 if (ai_iscoreup(wlc_hw->sih)) {
1198                         if (R_REG(&wlc_hw->regs->maccontrol) &
1199                             MCTL_EN_MAC)
1200                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1201                         callbacks += brcms_reset(wlc_hw->wlc->wl);
1202                         wlc_coredisable(wlc_hw);
1203                 }
1204
1205                 /* turn off primary xtal and pll */
1206                 if (!wlc_hw->noreset) {
1207                         if (wlc_hw->sih->bustype == PCI_BUS)
1208                                 ai_pci_down(wlc_hw->sih);
1209                         wlc_bmac_xtal(wlc_hw, OFF);
1210                 }
1211         }
1212
1213         return callbacks;
1214 }
1215
1216 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1217 {
1218         /* delay before first read of ucode state */
1219         udelay(40);
1220
1221         /* wait until ucode is no longer asleep */
1222         SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1223                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1224 }
1225
1226 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1227 {
1228         memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1229 }
1230
1231 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1232 {
1233         return wlc_hw->band->bandtype;
1234 }
1235
1236 /* control chip clock to save power, enable dynamic clock or force fast clock */
1237 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1238 {
1239         if (PMUCTL_ENAB(wlc_hw->sih)) {
1240                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1241                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1242                  *      which means the FCA bit may not be set.
1243                  *      should wakeup mac if driver wants it to run on HT.
1244                  */
1245
1246                 if (wlc_hw->clk) {
1247                         if (mode == CLK_FAST) {
1248                                 OR_REG(&wlc_hw->regs->clk_ctl_st,
1249                                        CCS_FORCEHT);
1250
1251                                 udelay(64);
1252
1253                                 SPINWAIT(((R_REG
1254                                            (&wlc_hw->regs->
1255                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1256                                          PMU_MAX_TRANSITION_DLY);
1257                                 WARN_ON(!(R_REG
1258                                           (&wlc_hw->regs->
1259                                            clk_ctl_st) & CCS_HTAVAIL));
1260                         } else {
1261                                 if ((wlc_hw->sih->pmurev == 0) &&
1262                                     (R_REG
1263                                      (&wlc_hw->regs->
1264                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1265                                         SPINWAIT(((R_REG
1266                                                    (&wlc_hw->regs->
1267                                                     clk_ctl_st) & CCS_HTAVAIL)
1268                                                   == 0),
1269                                                  PMU_MAX_TRANSITION_DLY);
1270                                 AND_REG(&wlc_hw->regs->clk_ctl_st,
1271                                         ~CCS_FORCEHT);
1272                         }
1273                 }
1274                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1275         } else {
1276
1277                 /* old chips w/o PMU, force HT through cc,
1278                  * then use FCA to verify mac is running fast clock
1279                  */
1280
1281                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1282
1283                 /* check fast clock is available (if core is not in reset) */
1284                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1285                         WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1286                                   SISF_FCLKA));
1287
1288                 /* keep the ucode wake bit on if forcefastclk is on
1289                  * since we do not want ucode to put us back to slow clock
1290                  * when it dozes for PM mode.
1291                  * Code below matches the wake override bit with current forcefastclk state
1292                  * Only setting bit in wake_override instead of waking ucode immediately
1293                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1294                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1295                  * (protected by an up check) was executed just below.
1296                  */
1297                 if (wlc_hw->forcefastclk)
1298                         mboolset(wlc_hw->wake_override,
1299                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1300                 else
1301                         mboolclr(wlc_hw->wake_override,
1302                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1303         }
1304 }
1305
1306 /* set initial host flags value */
1307 static void
1308 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1309 {
1310         struct wlc_hw_info *wlc_hw = wlc->hw;
1311
1312         memset(mhfs, 0, MHFMAX * sizeof(u16));
1313
1314         mhfs[MHF2] |= mhf2_init;
1315
1316         /* prohibit use of slowclock on multifunction boards */
1317         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1318                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1319
1320         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1321                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1322                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1323         }
1324 }
1325
1326 /* set or clear ucode host flag bits
1327  * it has an optimization for no-change write
1328  * it only writes through shared memory when the core has clock;
1329  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1330  *
1331  *
1332  * bands values are: WLC_BAND_AUTO <--- Current band only
1333  *                   WLC_BAND_5G   <--- 5G band only
1334  *                   WLC_BAND_2G   <--- 2G band only
1335  *                   WLC_BAND_ALL  <--- All bands
1336  */
1337 void
1338 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1339              int bands)
1340 {
1341         u16 save;
1342         u16 addr[MHFMAX] = {
1343                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1344                 M_HOST_FLAGS5
1345         };
1346         struct wlc_hwband *band;
1347
1348         if ((val & ~mask) || idx >= MHFMAX)
1349                 return; /* error condition */
1350
1351         switch (bands) {
1352                 /* Current band only or all bands,
1353                  * then set the band to current band
1354                  */
1355         case WLC_BAND_AUTO:
1356         case WLC_BAND_ALL:
1357                 band = wlc_hw->band;
1358                 break;
1359         case WLC_BAND_5G:
1360                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1361                 break;
1362         case WLC_BAND_2G:
1363                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1364                 break;
1365         default:
1366                 band = NULL;    /* error condition */
1367         }
1368
1369         if (band) {
1370                 save = band->mhfs[idx];
1371                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1372
1373                 /* optimization: only write through if changed, and
1374                  * changed band is the current band
1375                  */
1376                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1377                     && (band == wlc_hw->band))
1378                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1379                                            (u16) band->mhfs[idx]);
1380         }
1381
1382         if (bands == WLC_BAND_ALL) {
1383                 wlc_hw->bandstate[0]->mhfs[idx] =
1384                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1385                 wlc_hw->bandstate[1]->mhfs[idx] =
1386                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1387         }
1388 }
1389
1390 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1391 {
1392         struct wlc_hwband *band;
1393
1394         if (idx >= MHFMAX)
1395                 return 0; /* error condition */
1396         switch (bands) {
1397         case WLC_BAND_AUTO:
1398                 band = wlc_hw->band;
1399                 break;
1400         case WLC_BAND_5G:
1401                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1402                 break;
1403         case WLC_BAND_2G:
1404                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1405                 break;
1406         default:
1407                 band = NULL;            /* error condition */
1408         }
1409
1410         if (!band)
1411                 return 0;
1412
1413         return band->mhfs[idx];
1414 }
1415
1416 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1417 {
1418         u8 idx;
1419         u16 addr[] = {
1420                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1421                 M_HOST_FLAGS5
1422         };
1423
1424         for (idx = 0; idx < MHFMAX; idx++) {
1425                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1426         }
1427 }
1428
1429 /* set the maccontrol register to desired reset state and
1430  * initialize the sw cache of the register
1431  */
1432 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1433 {
1434         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1435         wlc_hw->maccontrol = 0;
1436         wlc_hw->suspended_fifos = 0;
1437         wlc_hw->wake_override = 0;
1438         wlc_hw->mute_override = 0;
1439         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1440 }
1441
1442 /* set or clear maccontrol bits */
1443 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1444 {
1445         u32 maccontrol;
1446         u32 new_maccontrol;
1447
1448         if (val & ~mask)
1449                 return; /* error condition */
1450         maccontrol = wlc_hw->maccontrol;
1451         new_maccontrol = (maccontrol & ~mask) | val;
1452
1453         /* if the new maccontrol value is the same as the old, nothing to do */
1454         if (new_maccontrol == maccontrol)
1455                 return;
1456
1457         /* something changed, cache the new value */
1458         wlc_hw->maccontrol = new_maccontrol;
1459
1460         /* write the new values with overrides applied */
1461         wlc_mctrl_write(wlc_hw);
1462 }
1463
1464 /* write the software state of maccontrol and overrides to the maccontrol register */
1465 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1466 {
1467         u32 maccontrol = wlc_hw->maccontrol;
1468
1469         /* OR in the wake bit if overridden */
1470         if (wlc_hw->wake_override)
1471                 maccontrol |= MCTL_WAKE;
1472
1473         /* set AP and INFRA bits for mute if needed */
1474         if (wlc_hw->mute_override) {
1475                 maccontrol &= ~(MCTL_AP);
1476                 maccontrol |= MCTL_INFRA;
1477         }
1478
1479         W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1480 }
1481
1482 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1483 {
1484         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1485                 mboolset(wlc_hw->wake_override, override_bit);
1486                 return;
1487         }
1488
1489         mboolset(wlc_hw->wake_override, override_bit);
1490
1491         wlc_mctrl_write(wlc_hw);
1492         wlc_bmac_wait_for_wake(wlc_hw);
1493
1494         return;
1495 }
1496
1497 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1498 {
1499         mboolclr(wlc_hw->wake_override, override_bit);
1500
1501         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1502                 return;
1503
1504         wlc_mctrl_write(wlc_hw);
1505
1506         return;
1507 }
1508
1509 /* When driver needs ucode to stop beaconing, it has to make sure that
1510  * MCTL_AP is clear and MCTL_INFRA is set
1511  * Mode           MCTL_AP        MCTL_INFRA
1512  * AP                1              1
1513  * STA               0              1 <--- This will ensure no beacons
1514  * IBSS              0              0
1515  */
1516 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1517 {
1518         wlc_hw->mute_override = 1;
1519
1520         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1521          * override, then there is no change to write
1522          */
1523         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1524                 return;
1525
1526         wlc_mctrl_write(wlc_hw);
1527
1528         return;
1529 }
1530
1531 /* Clear the override on AP and INFRA bits */
1532 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1533 {
1534         if (wlc_hw->mute_override == 0)
1535                 return;
1536
1537         wlc_hw->mute_override = 0;
1538
1539         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1540          * override, then there is no change to write
1541          */
1542         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1543                 return;
1544
1545         wlc_mctrl_write(wlc_hw);
1546 }
1547
1548 /*
1549  * Write a MAC address to the given match reg offset in the RXE match engine.
1550  */
1551 void
1552 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1553                        const u8 *addr)
1554 {
1555         d11regs_t *regs;
1556         u16 mac_l;
1557         u16 mac_m;
1558         u16 mac_h;
1559
1560         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
1561                  wlc_hw->unit);
1562
1563         regs = wlc_hw->regs;
1564         mac_l = addr[0] | (addr[1] << 8);
1565         mac_m = addr[2] | (addr[3] << 8);
1566         mac_h = addr[4] | (addr[5] << 8);
1567
1568         /* enter the MAC addr into the RXE match registers */
1569         W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1570         W_REG(&regs->rcm_mat_data, mac_l);
1571         W_REG(&regs->rcm_mat_data, mac_m);
1572         W_REG(&regs->rcm_mat_data, mac_h);
1573
1574 }
1575
1576 void
1577 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1578                             void *buf)
1579 {
1580         d11regs_t *regs;
1581         u32 word;
1582         bool be_bit;
1583         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1584
1585         regs = wlc_hw->regs;
1586         W_REG(&regs->tplatewrptr, offset);
1587
1588         /* if MCTL_BIGEND bit set in mac control register,
1589          * the chip swaps data in fifo, as well as data in
1590          * template ram
1591          */
1592         be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1593
1594         while (len > 0) {
1595                 memcpy(&word, buf, sizeof(u32));
1596
1597                 if (be_bit)
1598                         word = cpu_to_be32(word);
1599                 else
1600                         word = cpu_to_le32(word);
1601
1602                 W_REG(&regs->tplatewrdata, word);
1603
1604                 buf = (u8 *) buf + sizeof(u32);
1605                 len -= sizeof(u32);
1606         }
1607 }
1608
1609 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1610 {
1611         wlc_hw->band->CWmin = newmin;
1612
1613         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1614         (void)R_REG(&wlc_hw->regs->objaddr);
1615         W_REG(&wlc_hw->regs->objdata, newmin);
1616 }
1617
1618 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1619 {
1620         wlc_hw->band->CWmax = newmax;
1621
1622         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1623         (void)R_REG(&wlc_hw->regs->objaddr);
1624         W_REG(&wlc_hw->regs->objdata, newmax);
1625 }
1626
1627 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1628 {
1629         bool fastclk;
1630
1631         /* request FAST clock if not on */
1632         fastclk = wlc_hw->forcefastclk;
1633         if (!fastclk)
1634                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1635
1636         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1637
1638         wlc_bmac_phy_reset(wlc_hw);
1639         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1640
1641         /* restore the clk */
1642         if (!fastclk)
1643                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1644 }
1645
1646 static void
1647 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1648 {
1649         d11regs_t *regs = wlc_hw->regs;
1650
1651         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1652                                     bcn);
1653         /* write beacon length to SCR */
1654         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1655         /* mark beacon0 valid */
1656         OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1657 }
1658
1659 static void
1660 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1661 {
1662         d11regs_t *regs = wlc_hw->regs;
1663
1664         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1665                                     bcn);
1666         /* write beacon length to SCR */
1667         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1668         /* mark beacon1 valid */
1669         OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1670 }
1671
1672 /* mac is assumed to be suspended at this point */
1673 void
1674 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1675                                bool both)
1676 {
1677         d11regs_t *regs = wlc_hw->regs;
1678
1679         if (both) {
1680                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1681                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1682         } else {
1683                 /* bcn 0 */
1684                 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1685                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1686                 /* bcn 1 */
1687                 else if (!
1688                          (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1689                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1690         }
1691 }
1692
1693 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1694 {
1695         u16 v;
1696         struct wlc_info *wlc = wlc_hw->wlc;
1697         /* update SYNTHPU_DLY */
1698
1699         if (WLCISLCNPHY(wlc->band)) {
1700                 v = SYNTHPU_DLY_LPPHY_US;
1701         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1702                 v = SYNTHPU_DLY_NPHY_US;
1703         } else {
1704                 v = SYNTHPU_DLY_BPHY_US;
1705         }
1706
1707         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1708 }
1709
1710 /* band-specific init */
1711 static void
1712 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1713 {
1714         struct wlc_hw_info *wlc_hw = wlc->hw;
1715
1716         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1717                 wlc_hw->band->bandunit);
1718
1719         wlc_ucode_bsinit(wlc_hw);
1720
1721         wlc_phy_init(wlc_hw->band->pi, chanspec);
1722
1723         wlc_ucode_txant_set(wlc_hw);
1724
1725         /* cwmin is band-specific, update hardware with value for current band */
1726         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1727         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1728
1729         wlc_bmac_update_slot_timing(wlc_hw,
1730                                     BAND_5G(wlc_hw->band->
1731                                             bandtype) ? true : wlc_hw->
1732                                     shortslot);
1733
1734         /* write phytype and phyvers */
1735         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1736         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1737
1738         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1739         wlc_upd_ofdm_pctl1_table(wlc_hw);
1740
1741         wlc_bmac_upd_synthpu(wlc_hw);
1742 }
1743
1744 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1745 {
1746         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1747
1748         wlc_hw->phyclk = clk;
1749
1750         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1751
1752                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1753                                (SICF_PRST | SICF_FGC));
1754                 udelay(1);
1755                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1756                 udelay(1);
1757
1758         } else {                /* take phy out of reset */
1759
1760                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1761                 udelay(1);
1762                 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1763                 udelay(1);
1764
1765         }
1766 }
1767
1768 /* Perform a soft reset of the PHY PLL */
1769 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1770 {
1771         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1772
1773         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1774                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1775         udelay(1);
1776         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1777                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1778         udelay(1);
1779         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1780                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1781         udelay(1);
1782         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1783                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1784         udelay(1);
1785 }
1786
1787 /* light way to turn on phy clock without reset for NPHY only
1788  *  refer to wlc_bmac_core_phy_clk for full version
1789  */
1790 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1791 {
1792         /* support(necessary for NPHY and HYPHY) only */
1793         if (!WLCISNPHY(wlc_hw->band))
1794                 return;
1795
1796         if (ON == clk)
1797                 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1798         else
1799                 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1800
1801 }
1802
1803 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1804 {
1805         if (ON == clk)
1806                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1807         else
1808                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1809 }
1810
1811 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1812 {
1813         wlc_phy_t *pih = wlc_hw->band->pi;
1814         u32 phy_bw_clkbits;
1815         bool phy_in_reset = false;
1816
1817         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1818
1819         if (pih == NULL)
1820                 return;
1821
1822         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1823
1824         /* Specific reset sequence required for NPHY rev 3 and 4 */
1825         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1826             NREV_LE(wlc_hw->band->phyrev, 4)) {
1827                 /* Set the PHY bandwidth */
1828                 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1829
1830                 udelay(1);
1831
1832                 /* Perform a soft reset of the PHY PLL */
1833                 wlc_bmac_core_phypll_reset(wlc_hw);
1834
1835                 /* reset the PHY */
1836                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1837                                (SICF_PRST | SICF_PCLKE));
1838                 phy_in_reset = true;
1839         } else {
1840
1841                 ai_core_cflags(wlc_hw->sih,
1842                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1843                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1844         }
1845
1846         udelay(2);
1847         wlc_bmac_core_phy_clk(wlc_hw, ON);
1848
1849         if (pih)
1850                 wlc_phy_anacore(pih, ON);
1851 }
1852
1853 /* switch to and initialize new band */
1854 static void
1855 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1856                                 chanspec_t chanspec) {
1857         struct wlc_info *wlc = wlc_hw->wlc;
1858         u32 macintmask;
1859
1860         /* Enable the d11 core before accessing it */
1861         if (!ai_iscoreup(wlc_hw->sih)) {
1862                 ai_core_reset(wlc_hw->sih, 0, 0);
1863                 wlc_mctrl_reset(wlc_hw);
1864         }
1865
1866         macintmask = wlc_setband_inact(wlc, bandunit);
1867
1868         if (!wlc_hw->up)
1869                 return;
1870
1871         wlc_bmac_core_phy_clk(wlc_hw, ON);
1872
1873         /* band-specific initializations */
1874         wlc_bmac_bsinit(wlc, chanspec);
1875
1876         /*
1877          * If there are any pending software interrupt bits,
1878          * then replace these with a harmless nonzero value
1879          * so wlc_dpc() will re-enable interrupts when done.
1880          */
1881         if (wlc->macintstatus)
1882                 wlc->macintstatus = MI_DMAINT;
1883
1884         /* restore macintmask */
1885         brcms_intrsrestore(wlc->wl, macintmask);
1886
1887         /* ucode should still be suspended.. */
1888         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1889 }
1890
1891 /* low-level band switch utility routine */
1892 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1893 {
1894         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1895                 bandunit);
1896
1897         wlc_hw->band = wlc_hw->bandstate[bandunit];
1898
1899         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1900         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1901
1902         /* set gmode core flag */
1903         if (wlc_hw->sbclk && !wlc_hw->noreset) {
1904                 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1905                                ((bandunit == 0) ? SICF_GMODE : 0));
1906         }
1907 }
1908
1909 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1910 {
1911
1912         /* reject unsupported corerev */
1913         if (!VALID_COREREV(wlc_hw->corerev)) {
1914                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1915                           wlc_hw->corerev);
1916                 return false;
1917         }
1918
1919         return true;
1920 }
1921
1922 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1923 {
1924         bool goodboard = true;
1925         uint boardrev = wlc_hw->boardrev;
1926
1927         if (boardrev == 0)
1928                 goodboard = false;
1929         else if (boardrev > 0xff) {
1930                 uint brt = (boardrev & 0xf000) >> 12;
1931                 uint b0 = (boardrev & 0xf00) >> 8;
1932                 uint b1 = (boardrev & 0xf0) >> 4;
1933                 uint b2 = boardrev & 0xf;
1934
1935                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1936                     || (b2 > 9))
1937                         goodboard = false;
1938         }
1939
1940         if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1941                 return goodboard;
1942
1943         return goodboard;
1944 }
1945
1946 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1947 {
1948         const char *varname = "macaddr";
1949         char *macaddr;
1950
1951         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1952         macaddr = getvar(wlc_hw->vars, varname);
1953         if (macaddr != NULL)
1954                 return macaddr;
1955
1956         if (NBANDS_HW(wlc_hw) > 1)
1957                 varname = "et1macaddr";
1958         else
1959                 varname = "il0macaddr";
1960
1961         macaddr = getvar(wlc_hw->vars, varname);
1962         if (macaddr == NULL) {
1963                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1964                           "getvar(%s) not found\n", wlc_hw->unit, varname);
1965         }
1966
1967         return macaddr;
1968 }
1969
1970 /*
1971  * Return true if radio is disabled, otherwise false.
1972  * hw radio disable signal is an external pin, users activate it asynchronously
1973  * this function could be called when driver is down and w/o clock
1974  * it operates on different registers depending on corerev and boardflag.
1975  */
1976 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
1977 {
1978         bool v, clk, xtal;
1979         u32 resetbits = 0, flags = 0;
1980
1981         xtal = wlc_hw->sbclk;
1982         if (!xtal)
1983                 wlc_bmac_xtal(wlc_hw, ON);
1984
1985         /* may need to take core out of reset first */
1986         clk = wlc_hw->clk;
1987         if (!clk) {
1988                 /*
1989                  * mac no longer enables phyclk automatically when driver
1990                  * accesses phyreg throughput mac. This can be skipped since
1991                  * only mac reg is accessed below
1992                  */
1993                 flags |= SICF_PCLKE;
1994
1995                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1996                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
1997                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
1998                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
1999                         wlc_hw->regs =
2000                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2001                                                      0);
2002                 ai_core_reset(wlc_hw->sih, flags, resetbits);
2003                 wlc_mctrl_reset(wlc_hw);
2004         }
2005
2006         v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2007
2008         /* put core back into reset */
2009         if (!clk)
2010                 ai_core_disable(wlc_hw->sih, 0);
2011
2012         if (!xtal)
2013                 wlc_bmac_xtal(wlc_hw, OFF);
2014
2015         return v;
2016 }
2017
2018 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2019 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2020 {
2021         if (wlc_hw->wlc->pub->hw_up)
2022                 return;
2023
2024         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2025
2026         /*
2027          * Enable pll and xtal, initialize the power control registers,
2028          * and force fastclock for the remainder of wlc_up().
2029          */
2030         wlc_bmac_xtal(wlc_hw, ON);
2031         ai_clkctl_init(wlc_hw->sih);
2032         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2033
2034         if (wlc_hw->sih->bustype == PCI_BUS) {
2035                 ai_pci_fixcfg(wlc_hw->sih);
2036
2037                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2038                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2039                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2040                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2041                         wlc_hw->regs =
2042                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2043                                                      0);
2044         }
2045
2046         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2047         wlc_phy_por_inform(wlc_hw->band->pi);
2048
2049         wlc_hw->ucode_loaded = false;
2050         wlc_hw->wlc->pub->hw_up = true;
2051
2052         if ((wlc_hw->boardflags & BFL_FEM)
2053             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2054                 if (!
2055                     (wlc_hw->boardrev >= 0x1250
2056                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2057                         ai_epa_4313war(wlc_hw->sih);
2058         }
2059 }
2060
2061 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2062 {
2063         struct dma_pub *di = wlc_hw->di[fifo];
2064         return dma_rxreset(di);
2065 }
2066
2067 /* d11 core reset
2068  *   ensure fask clock during reset
2069  *   reset dma
2070  *   reset d11(out of reset)
2071  *   reset phy(out of reset)
2072  *   clear software macintstatus for fresh new start
2073  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2074  */
2075 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2076 {
2077         d11regs_t *regs;
2078         uint i;
2079         bool fastclk;
2080         u32 resetbits = 0;
2081
2082         if (flags == WLC_USE_COREFLAGS)
2083                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2084
2085         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2086
2087         regs = wlc_hw->regs;
2088
2089         /* request FAST clock if not on  */
2090         fastclk = wlc_hw->forcefastclk;
2091         if (!fastclk)
2092                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2093
2094         /* reset the dma engines except first time thru */
2095         if (ai_iscoreup(wlc_hw->sih)) {
2096                 for (i = 0; i < NFIFO; i++)
2097                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2098                                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2099                                           "dma_txreset[%d]: cannot stop dma\n",
2100                                            wlc_hw->unit, __func__, i);
2101                         }
2102
2103                 if ((wlc_hw->di[RX_FIFO])
2104                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2105                         wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2106                                   "[%d]: cannot stop dma\n",
2107                                   wlc_hw->unit, __func__, RX_FIFO);
2108                 }
2109         }
2110         /* if noreset, just stop the psm and return */
2111         if (wlc_hw->noreset) {
2112                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2113                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2114                 return;
2115         }
2116
2117         /*
2118          * mac no longer enables phyclk automatically when driver accesses
2119          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2120          * band->pi is invalid. need to enable PHY CLK
2121          */
2122         flags |= SICF_PCLKE;
2123
2124         /* reset the core
2125          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2126          *  is cleared by the core_reset. have to re-request it.
2127          *  This adds some delay and we can optimize it by also requesting fastclk through
2128          *  chipcommon during this period if necessary. But that has to work coordinate
2129          *  with other driver like mips/arm since they may touch chipcommon as well.
2130          */
2131         wlc_hw->clk = false;
2132         ai_core_reset(wlc_hw->sih, flags, resetbits);
2133         wlc_hw->clk = true;
2134         if (wlc_hw->band && wlc_hw->band->pi)
2135                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2136
2137         wlc_mctrl_reset(wlc_hw);
2138
2139         if (PMUCTL_ENAB(wlc_hw->sih))
2140                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2141
2142         wlc_bmac_phy_reset(wlc_hw);
2143
2144         /* turn on PHY_PLL */
2145         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2146
2147         /* clear sw intstatus */
2148         wlc_hw->wlc->macintstatus = 0;
2149
2150         /* restore the clk setting */
2151         if (!fastclk)
2152                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2153 }
2154
2155 /* txfifo sizes needs to be modified(increased) since the newer cores
2156  * have more memory.
2157  */
2158 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2159 {
2160         d11regs_t *regs = wlc_hw->regs;
2161         u16 fifo_nu;
2162         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2163         u16 txfifo_def, txfifo_def1;
2164         u16 txfifo_cmd;
2165
2166         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2167         txfifo_startblk = TXFIFO_START_BLK;
2168
2169         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2170         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2171
2172                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2173                 txfifo_def = (txfifo_startblk & 0xff) |
2174                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2175                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2176                     ((((txfifo_endblk -
2177                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2178                 txfifo_cmd =
2179                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2180
2181                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2182                 W_REG(&regs->xmtfifodef, txfifo_def);
2183                 W_REG(&regs->xmtfifodef1, txfifo_def1);
2184
2185                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2186
2187                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2188         }
2189         /*
2190          * need to propagate to shm location to be in sync since ucode/hw won't
2191          * do this
2192          */
2193         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2194                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2195         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2196                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2197         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2198                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2199                             xmtfifo_sz[TX_AC_BK_FIFO]));
2200         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2201                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2202                             xmtfifo_sz[TX_BCMC_FIFO]));
2203 }
2204
2205 /* d11 core init
2206  *   reset PSM
2207  *   download ucode/PCM
2208  *   let ucode run to suspended
2209  *   download ucode inits
2210  *   config other core registers
2211  *   init dma
2212  */
2213 static void wlc_coreinit(struct wlc_info *wlc)
2214 {
2215         struct wlc_hw_info *wlc_hw = wlc->hw;
2216         d11regs_t *regs;
2217         u32 sflags;
2218         uint bcnint_us;
2219         uint i = 0;
2220         bool fifosz_fixup = false;
2221         int err = 0;
2222         u16 buf[NFIFO];
2223         struct wiphy *wiphy = wlc->wiphy;
2224
2225         regs = wlc_hw->regs;
2226
2227         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2228
2229         /* reset PSM */
2230         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2231
2232         wlc_ucode_download(wlc_hw);
2233         /*
2234          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2235          */
2236         fifosz_fixup = true;
2237
2238         /* let the PSM run to the suspended state, set mode to BSS STA */
2239         W_REG(&regs->macintstatus, -1);
2240         wlc_bmac_mctrl(wlc_hw, ~0,
2241                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2242
2243         /* wait for ucode to self-suspend after auto-init */
2244         SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2245                  1000 * 1000);
2246         if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2247                 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2248                           "suspend!\n", wlc_hw->unit);
2249
2250         wlc_gpio_init(wlc);
2251
2252         sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2253
2254         if (D11REV_IS(wlc_hw->corerev, 23)) {
2255                 if (WLCISNPHY(wlc_hw->band))
2256                         wlc_write_inits(wlc_hw, d11n0initvals16);
2257                 else
2258                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2259                                   " %d\n", __func__, wlc_hw->unit,
2260                                   wlc_hw->corerev);
2261         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2262                 if (WLCISLCNPHY(wlc_hw->band)) {
2263                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2264                 } else {
2265                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2266                                   " %d\n", __func__, wlc_hw->unit,
2267                                   wlc_hw->corerev);
2268                 }
2269         } else {
2270                 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2271                           __func__, wlc_hw->unit, wlc_hw->corerev);
2272         }
2273
2274         /* For old ucode, txfifo sizes needs to be modified(increased) */
2275         if (fifosz_fixup == true) {
2276                 wlc_corerev_fifofixup(wlc_hw);
2277         }
2278
2279         /* check txfifo allocations match between ucode and driver */
2280         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2281         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2282                 i = TX_AC_BE_FIFO;
2283                 err = -1;
2284         }
2285         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2286         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2287                 i = TX_AC_VI_FIFO;
2288                 err = -1;
2289         }
2290         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2291         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2292         buf[TX_AC_BK_FIFO] &= 0xff;
2293         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2294                 i = TX_AC_BK_FIFO;
2295                 err = -1;
2296         }
2297         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2298                 i = TX_AC_VO_FIFO;
2299                 err = -1;
2300         }
2301         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2302         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2303         buf[TX_BCMC_FIFO] &= 0xff;
2304         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2305                 i = TX_BCMC_FIFO;
2306                 err = -1;
2307         }
2308         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2309                 i = TX_ATIM_FIFO;
2310                 err = -1;
2311         }
2312         if (err != 0) {
2313                 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2314                           " driver size %d index %d\n", buf[i],
2315                           wlc_hw->xmtfifo_sz[i], i);
2316         }
2317
2318         /* make sure we can still talk to the mac */
2319         WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
2320
2321         /* band-specific inits done by wlc_bsinit() */
2322
2323         /* Set up frame burst size and antenna swap threshold init values */
2324         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2325         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2326
2327         /* enable one rx interrupt per received frame */
2328         W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2329
2330         /* set the station mode (BSS STA) */
2331         wlc_bmac_mctrl(wlc_hw,
2332                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2333                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2334
2335         /* set up Beacon interval */
2336         bcnint_us = 0x8000 << 10;
2337         W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2338         W_REG(&regs->tsf_cfpstart, bcnint_us);
2339         W_REG(&regs->macintstatus, MI_GP1);
2340
2341         /* write interrupt mask */
2342         W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2343
2344         /* allow the MAC to control the PHY clock (dynamic on/off) */
2345         wlc_bmac_macphyclk_set(wlc_hw, ON);
2346
2347         /* program dynamic clock control fast powerup delay register */
2348         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2349         W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2350
2351         /* tell the ucode the corerev */
2352         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2353
2354         /* tell the ucode MAC capabilities */
2355         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2356                            (u16) (wlc_hw->machwcap & 0xffff));
2357         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2358                            (u16) ((wlc_hw->
2359                                       machwcap >> 16) & 0xffff));
2360
2361         /* write retry limits to SCR, this done after PSM init */
2362         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2363         (void)R_REG(&regs->objaddr);
2364         W_REG(&regs->objdata, wlc_hw->SRL);
2365         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2366         (void)R_REG(&regs->objaddr);
2367         W_REG(&regs->objdata, wlc_hw->LRL);
2368
2369         /* write rate fallback retry limits */
2370         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2371         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2372
2373         AND_REG(&regs->ifs_ctl, 0x0FFF);
2374         W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2375
2376         /* dma initializations */
2377         wlc->txpend16165war = 0;
2378
2379         /* init the tx dma engines */
2380         for (i = 0; i < NFIFO; i++) {
2381                 if (wlc_hw->di[i])
2382                         dma_txinit(wlc_hw->di[i]);
2383         }
2384
2385         /* init the rx dma engine(s) and post receive buffers */
2386         dma_rxinit(wlc_hw->di[RX_FIFO]);
2387         dma_rxfill(wlc_hw->di[RX_FIFO]);
2388 }
2389
2390 /* This function is used for changing the tsf frac register
2391  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2392  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2393  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2394  * HTPHY Formula is 2^26/freq(MHz) e.g.
2395  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2396  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2397  * For spuron: 123MHz -> 2^26/123    = 545600.5
2398  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2399  * For spur off: 120MHz -> 2^26/120    = 559240.5
2400  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2401  */
2402
2403 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2404 {
2405         d11regs_t *regs;
2406         regs = wlc_hw->regs;
2407
2408         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2409             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2410                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2411                         W_REG(&regs->tsf_clk_frac_l, 0x2082);
2412                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2413                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2414                         W_REG(&regs->tsf_clk_frac_l, 0x5341);
2415                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2416                 } else {        /* 120Mhz */
2417                         W_REG(&regs->tsf_clk_frac_l, 0x8889);
2418                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2419                 }
2420         } else if (WLCISLCNPHY(wlc_hw->band)) {
2421                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2422                         W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2423                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2424                 } else {        /* 80Mhz */
2425                         W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2426                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2427                 }
2428         }
2429 }
2430
2431 /* Initialize GPIOs that are controlled by D11 core */
2432 static void wlc_gpio_init(struct wlc_info *wlc)
2433 {
2434         struct wlc_hw_info *wlc_hw = wlc->hw;
2435         d11regs_t *regs;
2436         u32 gc, gm;
2437
2438         regs = wlc_hw->regs;
2439
2440         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2441         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2442
2443         /*
2444          * Common GPIO setup:
2445          *      G0 = LED 0 = WLAN Activity
2446          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2447          *      G2 = LED 2 = WLAN 5 GHz Radio State
2448          *      G4 = radio disable input (HI enabled, LO disabled)
2449          */
2450
2451         gc = gm = 0;
2452
2453         /* Allocate GPIOs for mimo antenna diversity feature */
2454         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2455                 /* Enable antenna diversity, use 2x3 mode */
2456                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2457                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2458                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2459                              MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2460
2461                 /* init superswitch control */
2462                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2463
2464         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2465                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2466                 /*
2467                  * The board itself is powered by these GPIOs
2468                  * (when not sending pattern) so set them high
2469                  */
2470                 OR_REG(&regs->psm_gpio_oe,
2471                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2472                 OR_REG(&regs->psm_gpio_out,
2473                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2474
2475                 /* Enable antenna diversity, use 2x4 mode */
2476                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2477                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2478                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2479                              WLC_BAND_ALL);
2480
2481                 /* Configure the desired clock to be 4Mhz */
2482                 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2483                                    ANTSEL_CLKDIV_4MHZ);
2484         }
2485
2486         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2487         if (wlc_hw->boardflags & BFL_PACTRL)
2488                 gm |= gc |= BOARD_GPIO_PACTRL;
2489
2490         /* apply to gpiocontrol register */
2491         ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2492 }
2493
2494 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2495 {
2496         struct wlc_info *wlc;
2497         wlc = wlc_hw->wlc;
2498
2499         if (wlc_hw->ucode_loaded)
2500                 return;
2501
2502         if (D11REV_IS(wlc_hw->corerev, 23)) {
2503                 if (WLCISNPHY(wlc_hw->band)) {
2504                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2505                                         bcm43xx_16_mimosz);
2506                         wlc_hw->ucode_loaded = true;
2507                 } else
2508                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2509                                   "corerev %d\n",
2510                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2511         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2512                 if (WLCISLCNPHY(wlc_hw->band)) {
2513                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2514                                         bcm43xx_24_lcnsz);
2515                         wlc_hw->ucode_loaded = true;
2516                 } else {
2517                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2518                                   "corerev %d\n",
2519                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2520                 }
2521         }
2522 }
2523
2524 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2525                               const uint nbytes) {
2526         d11regs_t *regs = wlc_hw->regs;
2527         uint i;
2528         uint count;
2529
2530         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2531
2532         count = (nbytes / sizeof(u32));
2533
2534         W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2535         (void)R_REG(&regs->objaddr);
2536         for (i = 0; i < count; i++)
2537                 W_REG(&regs->objdata, ucode[i]);
2538 }
2539
2540 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2541                             const struct d11init *inits)
2542 {
2543         int i;
2544         volatile u8 *base;
2545
2546         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2547
2548         base = (volatile u8 *)wlc_hw->regs;
2549
2550         for (i = 0; inits[i].addr != 0xffff; i++) {
2551                 if (inits[i].size == 2)
2552                         W_REG((u16 *)(base + inits[i].addr),
2553                               inits[i].value);
2554                 else if (inits[i].size == 4)
2555                         W_REG((u32 *)(base + inits[i].addr),
2556                               inits[i].value);
2557         }
2558 }
2559
2560 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2561 {
2562         u16 phyctl;
2563         u16 phytxant = wlc_hw->bmac_phytxant;
2564         u16 mask = PHY_TXC_ANT_MASK;
2565
2566         /* set the Probe Response frame phy control word */
2567         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2568         phyctl = (phyctl & ~mask) | phytxant;
2569         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2570
2571         /* set the Response (ACK/CTS) frame phy control word */
2572         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2573         phyctl = (phyctl & ~mask) | phytxant;
2574         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2575 }
2576
2577 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2578 {
2579         /* update sw state */
2580         wlc_hw->bmac_phytxant = phytxant;
2581
2582         /* push to ucode if up */
2583         if (!wlc_hw->up)
2584                 return;
2585         wlc_ucode_txant_set(wlc_hw);
2586
2587 }
2588
2589 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2590 {
2591         return (u16) wlc_hw->wlc->stf->txant;
2592 }
2593
2594 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2595 {
2596         wlc_hw->antsel_type = antsel_type;
2597
2598         /* Update the antsel type for phy module to use */
2599         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2600 }
2601
2602 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2603 {
2604         bool fatal = false;
2605         uint unit;
2606         uint intstatus, idx;
2607         d11regs_t *regs = wlc_hw->regs;
2608         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2609
2610         unit = wlc_hw->unit;
2611
2612         for (idx = 0; idx < NFIFO; idx++) {
2613                 /* read intstatus register and ignore any non-error bits */
2614                 intstatus =
2615                     R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2616                 if (!intstatus)
2617                         continue;
2618
2619                 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2620                         unit, idx, intstatus);
2621
2622                 if (intstatus & I_RO) {
2623                         wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2624                                   "overflow\n", unit, idx);
2625                         fatal = true;
2626                 }
2627
2628                 if (intstatus & I_PC) {
2629                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2630                                  unit, idx);
2631                         fatal = true;
2632                 }
2633
2634                 if (intstatus & I_PD) {
2635                         wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2636                                   idx);
2637                         fatal = true;
2638                 }
2639
2640                 if (intstatus & I_DE) {
2641                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2642                                   "error\n", unit, idx);
2643                         fatal = true;
2644                 }
2645
2646                 if (intstatus & I_RU) {
2647                         wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2648                                   "underflow\n", idx, unit);
2649                 }
2650
2651                 if (intstatus & I_XU) {
2652                         wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2653                                   "underflow\n", idx, unit);
2654                         fatal = true;
2655                 }
2656
2657                 if (fatal) {
2658                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2659                         break;
2660                 } else
2661                         W_REG(&regs->intctrlregs[idx].intstatus,
2662                               intstatus);
2663         }
2664 }
2665
2666 void wlc_intrson(struct wlc_info *wlc)
2667 {
2668         struct wlc_hw_info *wlc_hw = wlc->hw;
2669         wlc->macintmask = wlc->defmacintmask;
2670         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2671 }
2672
2673 /* callback for siutils.c, which has only wlc handler, no wl
2674  * they both check up, not only because there is no need to off/restore d11 interrupt
2675  *  but also because per-port code may require sync with valid interrupt.
2676  */
2677
2678 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2679 {
2680         if (!wlc->hw->up)
2681                 return 0;
2682
2683         return brcms_intrsoff(wlc->wl);
2684 }
2685
2686 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2687 {
2688         if (!wlc->hw->up)
2689                 return;
2690
2691         brcms_intrsrestore(wlc->wl, macintmask);
2692 }
2693
2694 u32 wlc_intrsoff(struct wlc_info *wlc)
2695 {
2696         struct wlc_hw_info *wlc_hw = wlc->hw;
2697         u32 macintmask;
2698
2699         if (!wlc_hw->clk)
2700                 return 0;
2701
2702         macintmask = wlc->macintmask;   /* isr can still happen */
2703
2704         W_REG(&wlc_hw->regs->macintmask, 0);
2705         (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2706         udelay(1);              /* ensure int line is no longer driven */
2707         wlc->macintmask = 0;
2708
2709         /* return previous macintmask; resolve race between us and our isr */
2710         return wlc->macintstatus ? 0 : macintmask;
2711 }
2712
2713 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2714 {
2715         struct wlc_hw_info *wlc_hw = wlc->hw;
2716         if (!wlc_hw->clk)
2717                 return;
2718
2719         wlc->macintmask = macintmask;
2720         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2721 }
2722
2723 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2724 {
2725         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2726
2727         if (on) {
2728                 /* suspend tx fifos */
2729                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2730                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2731                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2732                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2733
2734                 /* zero the address match register so we do not send ACKs */
2735                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2736                                        null_ether_addr);
2737         } else {
2738                 /* resume tx fifos */
2739                 if (!wlc_hw->wlc->tx_suspended) {
2740                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2741                 }
2742                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2743                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2744                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2745
2746                 /* Restore address */
2747                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2748                                        wlc_hw->etheraddr);
2749         }
2750
2751         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2752
2753         if (on)
2754                 wlc_ucode_mute_override_set(wlc_hw);
2755         else
2756                 wlc_ucode_mute_override_clear(wlc_hw);
2757 }
2758
2759 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2760 {
2761         if (fifo >= NFIFO)
2762                 return -EINVAL;
2763
2764         *blocks = wlc_hw->xmtfifo_sz[fifo];
2765
2766         return 0;
2767 }
2768
2769 /* wlc_bmac_tx_fifo_suspended:
2770  * Check the MAC's tx suspend status for a tx fifo.
2771  *
2772  * When the MAC acknowledges a tx suspend, it indicates that no more
2773  * packets will be transmitted out the radio. This is independent of
2774  * DMA channel suspension---the DMA may have finished suspending, or may still
2775  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2776  * request.
2777  */
2778 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2779 {
2780         /* check that a suspend has been requested and is no longer pending */
2781
2782         /*
2783          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2784          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2785          * chnstatus register.
2786          * The tx fifo suspend completion is independent of the DMA suspend completion and
2787          *   may be acked before or after the DMA is suspended.
2788          */
2789         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2790             (R_REG(&wlc_hw->regs->chnstatus) &
2791              (1 << tx_fifo)) == 0)
2792                 return true;
2793
2794         return false;
2795 }
2796
2797 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2798 {
2799         u8 fifo = 1 << tx_fifo;
2800
2801         /* Two clients of this code, 11h Quiet period and scanning. */
2802
2803         /* only suspend if not already suspended */
2804         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2805                 return;
2806
2807         /* force the core awake only if not already */
2808         if (wlc_hw->suspended_fifos == 0)
2809                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2810
2811         wlc_hw->suspended_fifos |= fifo;
2812
2813         if (wlc_hw->di[tx_fifo]) {
2814                 /* Suspending AMPDU transmissions in the middle can cause underflow
2815                  * which may result in mismatch between ucode and driver
2816                  * so suspend the mac before suspending the FIFO
2817                  */
2818                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2819                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
2820
2821                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2822
2823                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2824                         wlc_enable_mac(wlc_hw->wlc);
2825         }
2826 }
2827
2828 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2829 {
2830         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2831          * here for PIO otherwise the watchdog will catch the inconsistency and fire
2832          */
2833         /* Two clients of this code, 11h Quiet period and scanning. */
2834         if (wlc_hw->di[tx_fifo])
2835                 dma_txresume(wlc_hw->di[tx_fifo]);
2836
2837         /* allow core to sleep again */
2838         if (wlc_hw->suspended_fifos == 0)
2839                 return;
2840         else {
2841                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2842                 if (wlc_hw->suspended_fifos == 0)
2843                         wlc_ucode_wake_override_clear(wlc_hw,
2844                                                       WLC_WAKE_OVERRIDE_TXFIFO);
2845         }
2846 }
2847
2848 /*
2849  * Read and clear macintmask and macintstatus and intstatus registers.
2850  * This routine should be called with interrupts off
2851  * Return:
2852  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
2853  *   0 if the interrupt is not for us, or we are in some special cases;
2854  *   device interrupt status bits otherwise.
2855  */
2856 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2857 {
2858         struct wlc_hw_info *wlc_hw = wlc->hw;
2859         d11regs_t *regs = wlc_hw->regs;
2860         u32 macintstatus;
2861
2862         /* macintstatus includes a DMA interrupt summary bit */
2863         macintstatus = R_REG(&regs->macintstatus);
2864
2865         BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2866                  macintstatus);
2867
2868         /* detect cardbus removed, in power down(suspend) and in reset */
2869         if (DEVICEREMOVED(wlc))
2870                 return -1;
2871
2872         /* DEVICEREMOVED succeeds even when the core is still resetting,
2873          * handle that case here.
2874          */
2875         if (macintstatus == 0xffffffff)
2876                 return 0;
2877
2878         /* defer unsolicited interrupts */
2879         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2880
2881         /* if not for us */
2882         if (macintstatus == 0)
2883                 return 0;
2884
2885         /* interrupts are already turned off for CFE build
2886          * Caution: For CFE Turning off the interrupts again has some undesired
2887          * consequences
2888          */
2889         /* turn off the interrupts */
2890         W_REG(&regs->macintmask, 0);
2891         (void)R_REG(&regs->macintmask); /* sync readback */
2892         wlc->macintmask = 0;
2893
2894         /* clear device interrupts */
2895         W_REG(&regs->macintstatus, macintstatus);
2896
2897         /* MI_DMAINT is indication of non-zero intstatus */
2898         if (macintstatus & MI_DMAINT) {
2899                 /*
2900                  * only fifo interrupt enabled is I_RI in
2901                  * RX_FIFO. If MI_DMAINT is set, assume it
2902                  * is set and clear the interrupt.
2903                  */
2904                 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
2905                       DEF_RXINTMASK);
2906         }
2907
2908         return macintstatus;
2909 }
2910
2911 /* Update wlc->macintstatus and wlc->intstatus[]. */
2912 /* Return true if they are updated successfully. false otherwise */
2913 bool wlc_intrsupd(struct wlc_info *wlc)
2914 {
2915         u32 macintstatus;
2916
2917         /* read and clear macintstatus and intstatus registers */
2918         macintstatus = wlc_intstatus(wlc, false);
2919
2920         /* device is removed */
2921         if (macintstatus == 0xffffffff)
2922                 return false;
2923
2924         /* update interrupt status in software */
2925         wlc->macintstatus |= macintstatus;
2926
2927         return true;
2928 }
2929
2930 /*
2931  * First-level interrupt processing.
2932  * Return true if this was our interrupt, false otherwise.
2933  * *wantdpc will be set to true if further wlc_dpc() processing is required,
2934  * false otherwise.
2935  */
2936 bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2937 {
2938         struct wlc_hw_info *wlc_hw = wlc->hw;
2939         u32 macintstatus;
2940
2941         *wantdpc = false;
2942
2943         if (!wlc_hw->up || !wlc->macintmask)
2944                 return false;
2945
2946         /* read and clear macintstatus and intstatus registers */
2947         macintstatus = wlc_intstatus(wlc, true);
2948
2949         if (macintstatus == 0xffffffff)
2950                 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2951                           " path\n");
2952
2953         /* it is not for us */
2954         if (macintstatus == 0)
2955                 return false;
2956
2957         *wantdpc = true;
2958
2959         /* save interrupt status bits */
2960         wlc->macintstatus = macintstatus;
2961
2962         return true;
2963
2964 }
2965
2966 static bool
2967 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2968 {
2969         /* discard intermediate indications for ucode with one legitimate case:
2970          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2971          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2972          *   transmission count)
2973          */
2974         if (!(txs->status & TX_STATUS_AMPDU)
2975             && (txs->status & TX_STATUS_INTERMEDIATE)) {
2976                 return false;
2977         }
2978
2979         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
2980 }
2981
2982 /* process tx completion events in BMAC
2983  * Return true if more tx status need to be processed. false otherwise.
2984  */
2985 static bool
2986 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
2987 {
2988         bool morepending = false;
2989         struct wlc_info *wlc = wlc_hw->wlc;
2990         d11regs_t *regs;
2991         tx_status_t txstatus, *txs;
2992         u32 s1, s2;
2993         uint n = 0;
2994         /*
2995          * Param 'max_tx_num' indicates max. # tx status to process before
2996          * break out.
2997          */
2998         uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
2999
3000         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3001
3002         txs = &txstatus;
3003         regs = wlc_hw->regs;
3004         while (!(*fatal)
3005                && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
3006
3007                 if (s1 == 0xffffffff) {
3008                         wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
3009                                 wlc_hw->unit, __func__);
3010                         return morepending;
3011                 }
3012
3013                         s2 = R_REG(&regs->frmtxstatus2);
3014
3015                 txs->status = s1 & TXS_STATUS_MASK;
3016                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3017                 txs->sequence = s2 & TXS_SEQ_MASK;
3018                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3019                 txs->lasttxtime = 0;
3020
3021                 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3022
3023                 /* !give others some time to run! */
3024                 if (++n >= max_tx_num)
3025                         break;
3026         }
3027
3028         if (*fatal)
3029                 return 0;
3030
3031         if (n >= max_tx_num)
3032                 morepending = true;
3033
3034         if (!pktq_empty(&wlc->pkt_queue->q))
3035                 wlc_send_q(wlc);
3036
3037         return morepending;
3038 }
3039
3040 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3041 {
3042         struct wlc_hw_info *wlc_hw = wlc->hw;
3043         d11regs_t *regs = wlc_hw->regs;
3044         u32 mc, mi;
3045         struct wiphy *wiphy = wlc->wiphy;
3046
3047         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3048                 wlc_hw->band->bandunit);
3049
3050         /*
3051          * Track overlapping suspend requests
3052          */
3053         wlc_hw->mac_suspend_depth++;
3054         if (wlc_hw->mac_suspend_depth > 1)
3055                 return;
3056
3057         /* force the core awake */
3058         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3059
3060         mc = R_REG(&regs->maccontrol);
3061
3062         if (mc == 0xffffffff) {
3063                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3064                           __func__);
3065                 brcms_down(wlc->wl);
3066                 return;
3067         }
3068         WARN_ON(mc & MCTL_PSM_JMP_0);
3069         WARN_ON(!(mc & MCTL_PSM_RUN));
3070         WARN_ON(!(mc & MCTL_EN_MAC));
3071
3072         mi = R_REG(&regs->macintstatus);
3073         if (mi == 0xffffffff) {
3074                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3075                           __func__);
3076                 brcms_down(wlc->wl);
3077                 return;
3078         }
3079         WARN_ON(mi & MI_MACSSPNDD);
3080
3081         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3082
3083         SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3084                  WLC_MAX_MAC_SUSPEND);
3085
3086         if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3087                 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3088                           " and MI_MACSSPNDD is still not on.\n",
3089                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3090                 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3091                           "psm_brc 0x%04x\n", wlc_hw->unit,
3092                           R_REG(&regs->psmdebug),
3093                           R_REG(&regs->phydebug),
3094                           R_REG(&regs->psm_brc));
3095         }
3096
3097         mc = R_REG(&regs->maccontrol);
3098         if (mc == 0xffffffff) {
3099                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3100                           __func__);
3101                 brcms_down(wlc->wl);
3102                 return;
3103         }
3104         WARN_ON(mc & MCTL_PSM_JMP_0);
3105         WARN_ON(!(mc & MCTL_PSM_RUN));
3106         WARN_ON(mc & MCTL_EN_MAC);
3107 }
3108
3109 void wlc_enable_mac(struct wlc_info *wlc)
3110 {
3111         struct wlc_hw_info *wlc_hw = wlc->hw;
3112         d11regs_t *regs = wlc_hw->regs;
3113         u32 mc, mi;
3114
3115         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3116                 wlc->band->bandunit);
3117
3118         /*
3119          * Track overlapping suspend requests
3120          */
3121         wlc_hw->mac_suspend_depth--;
3122         if (wlc_hw->mac_suspend_depth > 0)
3123                 return;
3124
3125         mc = R_REG(&regs->maccontrol);
3126         WARN_ON(mc & MCTL_PSM_JMP_0);
3127         WARN_ON(mc & MCTL_EN_MAC);
3128         WARN_ON(!(mc & MCTL_PSM_RUN));
3129
3130         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3131         W_REG(&regs->macintstatus, MI_MACSSPNDD);
3132
3133         mc = R_REG(&regs->maccontrol);
3134         WARN_ON(mc & MCTL_PSM_JMP_0);
3135         WARN_ON(!(mc & MCTL_EN_MAC));
3136         WARN_ON(!(mc & MCTL_PSM_RUN));
3137
3138         mi = R_REG(&regs->macintstatus);
3139         WARN_ON(mi & MI_MACSSPNDD);
3140
3141         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3142 }
3143
3144 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3145 {
3146         u8 rate;
3147         u8 rates[8] = {
3148                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3149                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3150         };
3151         u16 entry_ptr;
3152         u16 pctl1;
3153         uint i;
3154
3155         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3156                 return;
3157
3158         /* walk the phy rate table and update the entries */
3159         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3160                 rate = rates[i];
3161
3162                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3163
3164                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3165                 pctl1 =
3166                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3167
3168                 /* modify the value */
3169                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3170                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3171
3172                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3173                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3174                                    pctl1);
3175         }
3176 }
3177
3178 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3179 {
3180         uint i;
3181         u8 plcp_rate = 0;
3182         struct plcp_signal_rate_lookup {
3183                 u8 rate;
3184                 u8 signal_rate;
3185         };
3186         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3187         const struct plcp_signal_rate_lookup rate_lookup[] = {
3188                 {WLC_RATE_6M, 0xB},
3189                 {WLC_RATE_9M, 0xF},
3190                 {WLC_RATE_12M, 0xA},
3191                 {WLC_RATE_18M, 0xE},
3192                 {WLC_RATE_24M, 0x9},
3193                 {WLC_RATE_36M, 0xD},
3194                 {WLC_RATE_48M, 0x8},
3195                 {WLC_RATE_54M, 0xC}
3196         };
3197
3198         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3199                 if (rate == rate_lookup[i].rate) {
3200                         plcp_rate = rate_lookup[i].signal_rate;
3201                         break;
3202                 }
3203         }
3204
3205         /* Find the SHM pointer to the rate table entry by looking in the
3206          * Direct-map Table
3207          */
3208         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3209 }
3210
3211 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3212 {
3213         wlc_hw->hw_stf_ss_opmode = stf_mode;
3214
3215         if (wlc_hw->clk)
3216                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3217 }
3218
3219 void
3220 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3221                   u32 *tsf_h_ptr)
3222 {
3223         d11regs_t *regs = wlc_hw->regs;
3224
3225         /* read the tsf timer low, then high to get an atomic read */
3226         *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3227         *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3228
3229         return;
3230 }
3231
3232 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3233 {
3234         d11regs_t *regs;
3235         u32 w, val;
3236         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3237
3238         BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3239
3240         regs = wlc_hw->regs;
3241
3242         /* Validate dchip register access */
3243
3244         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3245         (void)R_REG(&regs->objaddr);
3246         w = R_REG(&regs->objdata);
3247
3248         /* Can we write and read back a 32bit register? */
3249         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3250         (void)R_REG(&regs->objaddr);
3251         W_REG(&regs->objdata, (u32) 0xaa5555aa);
3252
3253         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3254         (void)R_REG(&regs->objaddr);
3255         val = R_REG(&regs->objdata);
3256         if (val != (u32) 0xaa5555aa) {
3257                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3258                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
3259                 return false;
3260         }
3261
3262         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3263         (void)R_REG(&regs->objaddr);
3264         W_REG(&regs->objdata, (u32) 0x55aaaa55);
3265
3266         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3267         (void)R_REG(&regs->objaddr);
3268         val = R_REG(&regs->objdata);
3269         if (val != (u32) 0x55aaaa55) {
3270                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3271                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
3272                 return false;
3273         }
3274
3275         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3276         (void)R_REG(&regs->objaddr);
3277         W_REG(&regs->objdata, w);
3278
3279         /* clear CFPStart */
3280         W_REG(&regs->tsf_cfpstart, 0);
3281
3282         w = R_REG(&regs->maccontrol);
3283         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3284             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3285                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3286                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3287                           (MCTL_IHR_EN | MCTL_WAKE),
3288                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3289                 return false;
3290         }
3291
3292         return true;
3293 }
3294
3295 #define PHYPLL_WAIT_US  100000
3296
3297 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3298 {
3299         d11regs_t *regs;
3300         u32 tmp;
3301
3302         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3303
3304         tmp = 0;
3305         regs = wlc_hw->regs;
3306
3307         if (on) {
3308                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3309                         OR_REG(&regs->clk_ctl_st,
3310                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3311                                 CCS_ERSRC_REQ_PHYPLL));
3312                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3313                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3314                                  PHYPLL_WAIT_US);
3315
3316                         tmp = R_REG(&regs->clk_ctl_st);
3317                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3318                             (CCS_ERSRC_AVAIL_HT)) {
3319                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3320                                           " PLL failed\n", __func__);
3321                         }
3322                 } else {
3323                         OR_REG(&regs->clk_ctl_st,
3324                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3325                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3326                                   (CCS_ERSRC_AVAIL_D11PLL |
3327                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3328                                  (CCS_ERSRC_AVAIL_D11PLL |
3329                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3330
3331                         tmp = R_REG(&regs->clk_ctl_st);
3332                         if ((tmp &
3333                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3334                             !=
3335                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3336                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3337                                           "PHY PLL failed\n", __func__);
3338                         }
3339                 }
3340         } else {
3341                 /* Since the PLL may be shared, other cores can still be requesting it;
3342                  * so we'll deassert the request but not wait for status to comply.
3343                  */
3344                 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3345                 tmp = R_REG(&regs->clk_ctl_st);
3346         }
3347 }
3348
3349 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3350 {
3351         bool dev_gone;
3352
3353         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3354
3355         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3356
3357         if (dev_gone)
3358                 return;
3359
3360         if (wlc_hw->noreset)
3361                 return;
3362
3363         /* radio off */
3364         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3365
3366         /* turn off analog core */
3367         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3368
3369         /* turn off PHYPLL to save power */
3370         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3371
3372         /* No need to set wlc->pub->radio_active = OFF
3373          * because this function needs down capability and
3374          * radio_active is designed for BCMNODOWN.
3375          */
3376
3377         /* remove gpio controls */
3378         if (wlc_hw->ucode_dbgsel)
3379                 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3380
3381         wlc_hw->clk = false;
3382         ai_core_disable(wlc_hw->sih, 0);
3383         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3384 }
3385
3386 /* power both the pll and external oscillator on/off */
3387 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3388 {
3389         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3390
3391         /* dont power down if plldown is false or we must poll hw radio disable */
3392         if (!want && wlc_hw->pllreq)
3393                 return;
3394
3395         if (wlc_hw->sih)
3396                 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3397
3398         wlc_hw->sbclk = want;
3399         if (!wlc_hw->sbclk) {
3400                 wlc_hw->clk = false;
3401                 if (wlc_hw->band && wlc_hw->band->pi)
3402                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3403         }
3404 }
3405
3406 static void wlc_flushqueues(struct wlc_info *wlc)
3407 {
3408         struct wlc_hw_info *wlc_hw = wlc->hw;
3409         uint i;
3410
3411         wlc->txpend16165war = 0;
3412
3413         /* free any posted tx packets */
3414         for (i = 0; i < NFIFO; i++)
3415                 if (wlc_hw->di[i]) {
3416                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
3417                         TXPKTPENDCLR(wlc, i);
3418                         BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3419                 }
3420
3421         /* free any posted rx packets */
3422         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3423 }
3424
3425 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3426 {
3427         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3428 }
3429
3430 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3431 {
3432         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3433 }
3434
3435 static u16
3436 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3437 {
3438         d11regs_t *regs = wlc_hw->regs;
3439         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3440         volatile u16 *objdata_hi = objdata_lo + 1;
3441         u16 v;
3442
3443         W_REG(&regs->objaddr, sel | (offset >> 2));
3444         (void)R_REG(&regs->objaddr);
3445         if (offset & 2) {
3446                 v = R_REG(objdata_hi);
3447         } else {
3448                 v = R_REG(objdata_lo);
3449         }
3450
3451         return v;
3452 }
3453
3454 static void
3455 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3456 {
3457         d11regs_t *regs = wlc_hw->regs;
3458         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3459         volatile u16 *objdata_hi = objdata_lo + 1;
3460
3461         W_REG(&regs->objaddr, sel | (offset >> 2));
3462         (void)R_REG(&regs->objaddr);
3463         if (offset & 2) {
3464                 W_REG(objdata_hi, v);
3465         } else {
3466                 W_REG(objdata_lo, v);
3467         }
3468 }
3469
3470 /* Copy a buffer to shared memory of specified type .
3471  * SHM 'offset' needs to be an even address and
3472  * Buffer length 'len' must be an even number of bytes
3473  * 'sel' selects the type of memory
3474  */
3475 void
3476 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3477                        int len, u32 sel)
3478 {
3479         u16 v;
3480         const u8 *p = (const u8 *)buf;
3481         int i;
3482
3483         if (len <= 0 || (offset & 1) || (len & 1))
3484                 return;
3485
3486         for (i = 0; i < len; i += 2) {
3487                 v = p[i] | (p[i + 1] << 8);
3488                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3489         }
3490 }
3491
3492 /* Copy a piece of shared memory of specified type to a buffer .
3493  * SHM 'offset' needs to be an even address and
3494  * Buffer length 'len' must be an even number of bytes
3495  * 'sel' selects the type of memory
3496  */
3497 void
3498 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3499                          int len, u32 sel)
3500 {
3501         u16 v;
3502         u8 *p = (u8 *) buf;
3503         int i;
3504
3505         if (len <= 0 || (offset & 1) || (len & 1))
3506                 return;
3507
3508         for (i = 0; i < len; i += 2) {
3509                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3510                 p[i] = v & 0xFF;
3511                 p[i + 1] = (v >> 8) & 0xFF;
3512         }
3513 }
3514
3515 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3516 {
3517         BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3518                 wlc_hw->vars_size);
3519
3520         *buf = wlc_hw->vars;
3521         *len = wlc_hw->vars_size;
3522 }
3523
3524 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3525 {
3526         wlc_hw->SRL = SRL;
3527         wlc_hw->LRL = LRL;
3528
3529         /* write retry limit to SCR, shouldn't need to suspend */
3530         if (wlc_hw->up) {
3531                 W_REG(&wlc_hw->regs->objaddr,
3532                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3533                 (void)R_REG(&wlc_hw->regs->objaddr);
3534                 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3535                 W_REG(&wlc_hw->regs->objaddr,
3536                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3537                 (void)R_REG(&wlc_hw->regs->objaddr);
3538                 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3539         }
3540 }
3541
3542 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3543 {
3544         if (set) {
3545                 if (mboolisset(wlc_hw->pllreq, req_bit))
3546                         return;
3547
3548                 mboolset(wlc_hw->pllreq, req_bit);
3549
3550                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3551                         if (!wlc_hw->sbclk) {
3552                                 wlc_bmac_xtal(wlc_hw, ON);
3553                         }
3554                 }
3555         } else {
3556                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3557                         return;
3558
3559                 mboolclr(wlc_hw->pllreq, req_bit);
3560
3561                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3562                         if (wlc_hw->sbclk) {
3563                                 wlc_bmac_xtal(wlc_hw, OFF);
3564                         }
3565                 }
3566         }
3567
3568         return;
3569 }
3570
3571 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3572 {
3573         u16 table_ptr;
3574         u8 phy_rate, index;
3575
3576         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3577         /* XXX4321 fixup needed ? */
3578         if (IS_OFDM(rate))
3579                 table_ptr = M_RT_DIRMAP_A;
3580         else
3581                 table_ptr = M_RT_DIRMAP_B;
3582
3583         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3584          * the index into the rate table.
3585          */
3586         phy_rate = rate_info[rate] & WLC_RATE_MASK;
3587         index = phy_rate & 0xf;
3588
3589         /* Find the SHM pointer to the rate table entry by looking in the
3590          * Direct-map Table
3591          */
3592         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3593 }
3594
3595 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3596 {
3597         wlc_hw->antsel_avail = antsel_avail;
3598 }