2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/delay.h>
18 #include <linux/cordic.h>
23 #include "phy_qmath.h"
25 #include "phy_radio.h"
26 #include "phytbl_lcn.h"
29 #define PLL_2064_NDIV 90
30 #define PLL_2064_LOW_END_VCO 3000
31 #define PLL_2064_LOW_END_KVCO 27
32 #define PLL_2064_HIGH_END_VCO 4200
33 #define PLL_2064_HIGH_END_KVCO 68
34 #define PLL_2064_LOOP_BW_DOUBLER 200
35 #define PLL_2064_D30_DOUBLER 10500
36 #define PLL_2064_LOOP_BW 260
37 #define PLL_2064_D30 8000
38 #define PLL_2064_CAL_REF_TO 8
39 #define PLL_2064_MHZ 1000000
40 #define PLL_2064_OPEN_LOOP_DELAY 5
45 #define NOISE_IF_UPD_CHK_INTERVAL 1
46 #define NOISE_IF_UPD_RST_INTERVAL 60
47 #define NOISE_IF_UPD_THRESHOLD_CNT 1
48 #define NOISE_IF_UPD_TRHRESHOLD 50
49 #define NOISE_IF_UPD_TIMEOUT 1000
50 #define NOISE_IF_OFF 0
51 #define NOISE_IF_CHK 1
54 #define PAPD_BLANKING_PROFILE 3
56 #define PAPD_CORR_NORM 0
57 #define PAPD_BLANKING_THRESHOLD 0
58 #define PAPD_STOP_AFTER_LAST_UPDATE 0
60 #define LCN_TARGET_PWR 60
62 #define LCN_VBAT_OFFSET_433X 34649679
63 #define LCN_VBAT_SLOPE_433X 8258032
65 #define LCN_VBAT_SCALE_NOM 53
66 #define LCN_VBAT_SCALE_DEN 432
68 #define LCN_TEMPSENSE_OFFSET 80812
69 #define LCN_TEMPSENSE_DEN 2647
71 #define LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT \
73 #define LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK \
74 (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT)
76 #define LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT \
78 #define LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_MASK \
79 (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT)
81 #define wlc_lcnphy_enable_tx_gain_override(pi) \
82 wlc_lcnphy_set_tx_gain_override(pi, true)
83 #define wlc_lcnphy_disable_tx_gain_override(pi) \
84 wlc_lcnphy_set_tx_gain_override(pi, false)
86 #define wlc_lcnphy_iqcal_active(pi) \
87 (read_phy_reg((pi), 0x451) & \
88 ((0x1 << 15) | (0x1 << 14)))
90 #define txpwrctrl_off(pi) (0x7 != ((read_phy_reg(pi, 0x4a4) & 0xE000) >> 13))
91 #define wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) \
92 (pi->temppwrctrl_capable)
93 #define wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) \
94 (pi->hwpwrctrl_capable)
96 #define SWCTRL_BT_TX 0x18
97 #define SWCTRL_OVR_DISABLE 0x40
99 #define AFE_CLK_INIT_MODE_TXRX2X 1
100 #define AFE_CLK_INIT_MODE_PAPD 0
102 #define LCNPHY_TBL_ID_IQLOCAL 0x00
104 #define LCNPHY_TBL_ID_RFSEQ 0x08
105 #define LCNPHY_TBL_ID_GAIN_IDX 0x0d
106 #define LCNPHY_TBL_ID_SW_CTRL 0x0f
107 #define LCNPHY_TBL_ID_GAIN_TBL 0x12
108 #define LCNPHY_TBL_ID_SPUR 0x14
109 #define LCNPHY_TBL_ID_SAMPLEPLAY 0x15
110 #define LCNPHY_TBL_ID_SAMPLEPLAY1 0x16
112 #define LCNPHY_TX_PWR_CTRL_RATE_OFFSET 832
113 #define LCNPHY_TX_PWR_CTRL_MAC_OFFSET 128
114 #define LCNPHY_TX_PWR_CTRL_GAIN_OFFSET 192
115 #define LCNPHY_TX_PWR_CTRL_IQ_OFFSET 320
116 #define LCNPHY_TX_PWR_CTRL_LO_OFFSET 448
117 #define LCNPHY_TX_PWR_CTRL_PWR_OFFSET 576
119 #define LCNPHY_TX_PWR_CTRL_START_INDEX_2G_4313 140
121 #define LCNPHY_TX_PWR_CTRL_START_NPT 1
122 #define LCNPHY_TX_PWR_CTRL_MAX_NPT 7
124 #define LCNPHY_NOISE_SAMPLES_DEFAULT 5000
126 #define LCNPHY_ACI_DETECT_START 1
127 #define LCNPHY_ACI_DETECT_PROGRESS 2
128 #define LCNPHY_ACI_DETECT_STOP 3
130 #define LCNPHY_ACI_CRSHIFRMLO_TRSH 100
131 #define LCNPHY_ACI_GLITCH_TRSH 2000
132 #define LCNPHY_ACI_TMOUT 250
133 #define LCNPHY_ACI_DETECT_TIMEOUT 2
134 #define LCNPHY_ACI_START_DELAY 0
136 #define wlc_lcnphy_tx_gain_override_enabled(pi) \
137 (0 != (read_phy_reg((pi), 0x43b) & (0x1 << 6)))
139 #define wlc_lcnphy_total_tx_frames(pi) \
140 wlapi_bmac_read_shm((pi)->sh->physhim, M_UCODE_MACSTAT + \
141 offsetof(struct macstat, txallfrm))
143 struct lcnphy_txgains {
150 enum lcnphy_cal_mode {
158 struct lcnphy_rx_iqcomp {
164 struct lcnphy_spb_tone {
169 struct lcnphy_unsign16_struct {
174 struct lcnphy_iq_est {
180 struct lcnphy_sfo_cfg {
185 enum lcnphy_papd_cal_type {
190 typedef u16 iqcal_gain_params_lcnphy[9];
192 static const iqcal_gain_params_lcnphy tbl_iqcal_gainparams_lcnphy_2G[] = {
193 {0, 0, 0, 0, 0, 0, 0, 0, 0},
196 static const iqcal_gain_params_lcnphy *tbl_iqcal_gainparams_lcnphy[1] = {
197 tbl_iqcal_gainparams_lcnphy_2G,
200 static const u16 iqcal_gainparams_numgains_lcnphy[1] = {
201 sizeof(tbl_iqcal_gainparams_lcnphy_2G) /
202 sizeof(*tbl_iqcal_gainparams_lcnphy_2G),
205 static const struct lcnphy_sfo_cfg lcnphy_sfo_cfg[] = {
223 u16 lcnphy_iqcal_loft_gainladder[] = {
247 u16 lcnphy_iqcal_ir_gainladder[] = {
271 struct lcnphy_spb_tone lcnphy_spb_tone_3750[] = {
307 u16 iqlo_loopback_rf_regs[20] = {
331 u16 tempsense_phy_regs[14] = {
349 u16 rxiq_cal_rf_reg[11] = {
364 struct lcnphy_rx_iqcomp lcnphy_rx_iqcomp_table_rev0[] = {
418 static const u32 lcnphy_23bitgaincode_table[] = {
458 static const s8 lcnphy_gain_table[] = {
498 static const s8 lcnphy_gain_index_offset_for_rssi[] = {
539 struct chan_info_2064_lcnphy {
544 u8 txrf_mix_tune_ctrl;
547 u8 pa_rxrf_lna1_freq_tune;
548 u8 pa_rxrf_lna2_freq_tune;
552 static struct chan_info_2064_lcnphy chan_info_2064_lcnphy[] = {
553 {1, 2412, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
554 {2, 2417, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
555 {3, 2422, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
556 {4, 2427, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
557 {5, 2432, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
558 {6, 2437, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
559 {7, 2442, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
560 {8, 2447, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
561 {9, 2452, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
562 {10, 2457, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
563 {11, 2462, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
564 {12, 2467, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
565 {13, 2472, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
566 {14, 2484, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
569 struct lcnphy_radio_regs lcnphy_radio_regs_2064[] = {
571 {0x01, 0x64, 0x64, 0, 0},
572 {0x02, 0x20, 0x20, 0, 0},
573 {0x03, 0x66, 0x66, 0, 0},
574 {0x04, 0xf8, 0xf8, 0, 0},
576 {0x06, 0x10, 0x10, 0, 0},
580 {0x0A, 0x37, 0x37, 0, 0},
581 {0x0B, 0x6, 0x6, 0, 0},
582 {0x0C, 0x55, 0x55, 0, 0},
583 {0x0D, 0x8b, 0x8b, 0, 0},
585 {0x0F, 0x5, 0x5, 0, 0},
587 {0x11, 0xe, 0xe, 0, 0},
589 {0x13, 0xb, 0xb, 0, 0},
590 {0x14, 0x2, 0x2, 0, 0},
591 {0x15, 0x12, 0x12, 0, 0},
592 {0x16, 0x12, 0x12, 0, 0},
593 {0x17, 0xc, 0xc, 0, 0},
594 {0x18, 0xc, 0xc, 0, 0},
595 {0x19, 0xc, 0xc, 0, 0},
596 {0x1A, 0x8, 0x8, 0, 0},
597 {0x1B, 0x2, 0x2, 0, 0},
599 {0x1D, 0x1, 0x1, 0, 0},
600 {0x1E, 0x12, 0x12, 0, 0},
601 {0x1F, 0x6e, 0x6e, 0, 0},
602 {0x20, 0x2, 0x2, 0, 0},
603 {0x21, 0x23, 0x23, 0, 0},
604 {0x22, 0x8, 0x8, 0, 0},
607 {0x25, 0xc, 0xc, 0, 0},
608 {0x26, 0x33, 0x33, 0, 0},
609 {0x27, 0x55, 0x55, 0, 0},
611 {0x29, 0x30, 0x30, 0, 0},
612 {0x2A, 0xb, 0xb, 0, 0},
613 {0x2B, 0x1b, 0x1b, 0, 0},
614 {0x2C, 0x3, 0x3, 0, 0},
615 {0x2D, 0x1b, 0x1b, 0, 0},
617 {0x2F, 0x20, 0x20, 0, 0},
618 {0x30, 0xa, 0xa, 0, 0},
620 {0x32, 0x62, 0x62, 0, 0},
621 {0x33, 0x19, 0x19, 0, 0},
622 {0x34, 0x33, 0x33, 0, 0},
623 {0x35, 0x77, 0x77, 0, 0},
625 {0x37, 0x70, 0x70, 0, 0},
626 {0x38, 0x3, 0x3, 0, 0},
627 {0x39, 0xf, 0xf, 0, 0},
628 {0x3A, 0x6, 0x6, 0, 0},
629 {0x3B, 0xcf, 0xcf, 0, 0},
630 {0x3C, 0x1a, 0x1a, 0, 0},
631 {0x3D, 0x6, 0x6, 0, 0},
632 {0x3E, 0x42, 0x42, 0, 0},
634 {0x40, 0xfb, 0xfb, 0, 0},
635 {0x41, 0x9a, 0x9a, 0, 0},
636 {0x42, 0x7a, 0x7a, 0, 0},
637 {0x43, 0x29, 0x29, 0, 0},
639 {0x45, 0x8, 0x8, 0, 0},
640 {0x46, 0xce, 0xce, 0, 0},
641 {0x47, 0x27, 0x27, 0, 0},
642 {0x48, 0x62, 0x62, 0, 0},
643 {0x49, 0x6, 0x6, 0, 0},
644 {0x4A, 0x58, 0x58, 0, 0},
645 {0x4B, 0xf7, 0xf7, 0, 0},
647 {0x4D, 0xb3, 0xb3, 0, 0},
649 {0x4F, 0x2, 0x2, 0, 0},
651 {0x51, 0x9, 0x9, 0, 0},
652 {0x52, 0x5, 0x5, 0, 0},
653 {0x53, 0x17, 0x17, 0, 0},
654 {0x54, 0x38, 0x38, 0, 0},
657 {0x57, 0xb, 0xb, 0, 0},
664 {0x5E, 0x88, 0x88, 0, 0},
665 {0x5F, 0xcc, 0xcc, 0, 0},
666 {0x60, 0x74, 0x74, 0, 0},
667 {0x61, 0x74, 0x74, 0, 0},
668 {0x62, 0x74, 0x74, 0, 0},
669 {0x63, 0x44, 0x44, 0, 0},
670 {0x64, 0x77, 0x77, 0, 0},
671 {0x65, 0x44, 0x44, 0, 0},
672 {0x66, 0x77, 0x77, 0, 0},
673 {0x67, 0x55, 0x55, 0, 0},
674 {0x68, 0x77, 0x77, 0, 0},
675 {0x69, 0x77, 0x77, 0, 0},
677 {0x6B, 0x7f, 0x7f, 0, 0},
678 {0x6C, 0x8, 0x8, 0, 0},
680 {0x6E, 0x88, 0x88, 0, 0},
681 {0x6F, 0x66, 0x66, 0, 0},
682 {0x70, 0x66, 0x66, 0, 0},
683 {0x71, 0x28, 0x28, 0, 0},
684 {0x72, 0x55, 0x55, 0, 0},
685 {0x73, 0x4, 0x4, 0, 0},
689 {0x77, 0x1, 0x1, 0, 0},
690 {0x78, 0xd6, 0xd6, 0, 0},
701 {0x83, 0xb4, 0xb4, 0, 0},
702 {0x84, 0x1, 0x1, 0, 0},
703 {0x85, 0x20, 0x20, 0, 0},
704 {0x86, 0x5, 0x5, 0, 0},
705 {0x87, 0xff, 0xff, 0, 0},
706 {0x88, 0x7, 0x7, 0, 0},
707 {0x89, 0x77, 0x77, 0, 0},
708 {0x8A, 0x77, 0x77, 0, 0},
709 {0x8B, 0x77, 0x77, 0, 0},
710 {0x8C, 0x77, 0x77, 0, 0},
711 {0x8D, 0x8, 0x8, 0, 0},
712 {0x8E, 0xa, 0xa, 0, 0},
713 {0x8F, 0x8, 0x8, 0, 0},
714 {0x90, 0x18, 0x18, 0, 0},
715 {0x91, 0x5, 0x5, 0, 0},
716 {0x92, 0x1f, 0x1f, 0, 0},
717 {0x93, 0x10, 0x10, 0, 0},
718 {0x94, 0x3, 0x3, 0, 0},
721 {0x97, 0xaa, 0xaa, 0, 0},
723 {0x99, 0x23, 0x23, 0, 0},
724 {0x9A, 0x7, 0x7, 0, 0},
725 {0x9B, 0xf, 0xf, 0, 0},
726 {0x9C, 0x10, 0x10, 0, 0},
727 {0x9D, 0x3, 0x3, 0, 0},
728 {0x9E, 0x4, 0x4, 0, 0},
729 {0x9F, 0x20, 0x20, 0, 0},
734 {0xA4, 0x1, 0x1, 0, 0},
735 {0xA5, 0x77, 0x77, 0, 0},
736 {0xA6, 0x77, 0x77, 0, 0},
737 {0xA7, 0x77, 0x77, 0, 0},
738 {0xA8, 0x77, 0x77, 0, 0},
739 {0xA9, 0x8c, 0x8c, 0, 0},
740 {0xAA, 0x88, 0x88, 0, 0},
741 {0xAB, 0x78, 0x78, 0, 0},
742 {0xAC, 0x57, 0x57, 0, 0},
743 {0xAD, 0x88, 0x88, 0, 0},
745 {0xAF, 0x8, 0x8, 0, 0},
746 {0xB0, 0x88, 0x88, 0, 0},
748 {0xB2, 0x1b, 0x1b, 0, 0},
749 {0xB3, 0x3, 0x3, 0, 0},
750 {0xB4, 0x24, 0x24, 0, 0},
751 {0xB5, 0x3, 0x3, 0, 0},
752 {0xB6, 0x1b, 0x1b, 0, 0},
753 {0xB7, 0x24, 0x24, 0, 0},
754 {0xB8, 0x3, 0x3, 0, 0},
756 {0xBA, 0xaa, 0xaa, 0, 0},
758 {0xBC, 0x4, 0x4, 0, 0},
760 {0xBE, 0x8, 0x8, 0, 0},
761 {0xBF, 0x11, 0x11, 0, 0},
764 {0xC2, 0x62, 0x62, 0, 0},
765 {0xC3, 0x1e, 0x1e, 0, 0},
766 {0xC4, 0x33, 0x33, 0, 0},
767 {0xC5, 0x37, 0x37, 0, 0},
769 {0xC7, 0x70, 0x70, 0, 0},
770 {0xC8, 0x1e, 0x1e, 0, 0},
771 {0xC9, 0x6, 0x6, 0, 0},
772 {0xCA, 0x4, 0x4, 0, 0},
773 {0xCB, 0x2f, 0x2f, 0, 0},
774 {0xCC, 0xf, 0xf, 0, 0},
776 {0xCE, 0xff, 0xff, 0, 0},
777 {0xCF, 0x8, 0x8, 0, 0},
778 {0xD0, 0x3f, 0x3f, 0, 0},
779 {0xD1, 0x3f, 0x3f, 0, 0},
780 {0xD2, 0x3f, 0x3f, 0, 0},
784 {0xD6, 0xcc, 0xcc, 0, 0},
786 {0xD8, 0x8, 0x8, 0, 0},
787 {0xD9, 0x8, 0x8, 0, 0},
788 {0xDA, 0x8, 0x8, 0, 0},
789 {0xDB, 0x11, 0x11, 0, 0},
791 {0xDD, 0x87, 0x87, 0, 0},
792 {0xDE, 0x88, 0x88, 0, 0},
793 {0xDF, 0x8, 0x8, 0, 0},
794 {0xE0, 0x8, 0x8, 0, 0},
795 {0xE1, 0x8, 0x8, 0, 0},
799 {0xE5, 0xf5, 0xf5, 0, 0},
800 {0xE6, 0x30, 0x30, 0, 0},
801 {0xE7, 0x1, 0x1, 0, 0},
803 {0xE9, 0xff, 0xff, 0, 0},
806 {0xEC, 0x22, 0x22, 0, 0},
810 {0xF0, 0x3, 0x3, 0, 0},
811 {0xF1, 0x1, 0x1, 0, 0},
817 {0xF7, 0x6, 0x6, 0, 0},
820 {0xFA, 0x40, 0x40, 0, 0},
822 {0xFC, 0x1, 0x1, 0, 0},
823 {0xFD, 0x80, 0x80, 0, 0},
824 {0xFE, 0x2, 0x2, 0, 0},
825 {0xFF, 0x10, 0x10, 0, 0},
826 {0x100, 0x2, 0x2, 0, 0},
827 {0x101, 0x1e, 0x1e, 0, 0},
828 {0x102, 0x1e, 0x1e, 0, 0},
830 {0x104, 0x1f, 0x1f, 0, 0},
831 {0x105, 0, 0x8, 0, 1},
832 {0x106, 0x2a, 0x2a, 0, 0},
833 {0x107, 0xf, 0xf, 0, 0},
854 {0x11C, 0x1, 0x1, 0, 0},
860 {0x122, 0x80, 0x80, 0, 0},
862 {0x124, 0xf8, 0xf8, 0, 0},
878 #define LCNPHY_NUM_DIG_FILT_COEFFS 16
879 #define LCNPHY_NUM_TX_DIG_FILTERS_CCK 13
881 u16 LCNPHY_txdigfiltcoeffs_cck[LCNPHY_NUM_TX_DIG_FILTERS_CCK]
882 [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = {
883 {0, 1, 415, 1874, 64, 128, 64, 792, 1656, 64, 128, 64, 778, 1582, 64,
885 {1, 1, 402, 1847, 259, 59, 259, 671, 1794, 68, 54, 68, 608, 1863, 93,
887 {2, 1, 415, 1874, 64, 128, 64, 792, 1656, 192, 384, 192, 778, 1582, 64,
889 {3, 1, 302, 1841, 129, 258, 129, 658, 1720, 205, 410, 205, 754, 1760,
891 {20, 1, 360, 1884, 242, 1734, 242, 752, 1720, 205, 1845, 205, 767, 1760,
893 {21, 1, 360, 1884, 149, 1874, 149, 752, 1720, 205, 1883, 205, 767, 1760,
895 {22, 1, 360, 1884, 98, 1948, 98, 752, 1720, 205, 1924, 205, 767, 1760,
897 {23, 1, 350, 1884, 116, 1966, 116, 752, 1720, 205, 2008, 205, 767, 1760,
899 {24, 1, 325, 1884, 32, 40, 32, 756, 1720, 256, 471, 256, 766, 1760, 256,
901 {25, 1, 299, 1884, 51, 64, 51, 736, 1720, 256, 471, 256, 765, 1760, 256,
903 {26, 1, 277, 1943, 39, 117, 88, 637, 1838, 64, 192, 144, 614, 1864, 128,
905 {27, 1, 245, 1943, 49, 147, 110, 626, 1838, 256, 768, 576, 613, 1864,
907 {30, 1, 302, 1841, 61, 122, 61, 658, 1720, 205, 410, 205, 754, 1760,
911 #define LCNPHY_NUM_TX_DIG_FILTERS_OFDM 3
912 u16 LCNPHY_txdigfiltcoeffs_ofdm[LCNPHY_NUM_TX_DIG_FILTERS_OFDM]
913 [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = {
914 {0, 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0, 0x0,
915 0x278, 0xfea0, 0x80, 0x100, 0x80,},
916 {1, 0, 374, 0xFF79, 16, 32, 16, 799, 0xFE74, 50, 32, 50,
917 750, 0xFE2B, 212, 0xFFCE, 212,},
918 {2, 0, 375, 0xFF16, 37, 76, 37, 799, 0xFE74, 32, 20, 32, 748,
919 0xFEF2, 128, 0xFFE2, 128}
922 #define wlc_lcnphy_set_start_tx_pwr_idx(pi, idx) \
923 mod_phy_reg(pi, 0x4a4, \
927 #define wlc_lcnphy_set_tx_pwr_npt(pi, npt) \
928 mod_phy_reg(pi, 0x4a5, \
932 #define wlc_lcnphy_get_tx_pwr_ctrl(pi) \
933 (read_phy_reg((pi), 0x4a4) & \
938 #define wlc_lcnphy_get_tx_pwr_npt(pi) \
939 ((read_phy_reg(pi, 0x4a5) & \
943 #define wlc_lcnphy_get_current_tx_pwr_idx_if_pwrctrl_on(pi) \
944 (read_phy_reg(pi, 0x473) & 0x1ff)
946 #define wlc_lcnphy_get_target_tx_pwr(pi) \
947 ((read_phy_reg(pi, 0x4a7) & \
951 #define wlc_lcnphy_set_target_tx_pwr(pi, target) \
952 mod_phy_reg(pi, 0x4a7, \
956 #define wlc_radio_2064_rcal_done(pi) \
957 (0 != (read_radio_reg(pi, RADIO_2064_REG05C) & 0x20))
959 #define tempsense_done(pi) \
960 (0x8000 == (read_phy_reg(pi, 0x476) & 0x8000))
962 #define LCNPHY_IQLOCC_READ(val) \
963 ((u8)(-(s8)(((val) & 0xf0) >> 4) + (s8)((val) & 0x0f)))
965 #define FIXED_TXPWR 78
966 #define LCNPHY_TEMPSENSE(val) ((s16)((val > 255) ? (val - 512) : val))
968 static u32 wlc_lcnphy_qdiv_roundup(u32 divident, u32 divisor,
970 static void wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi,
971 u16 ext_lna, u16 trsw,
975 static void wlc_lcnphy_clear_tx_power_offsets(struct brcms_phy *pi);
976 static void wlc_lcnphy_set_pa_gain(struct brcms_phy *pi, u16 gain);
977 static void wlc_lcnphy_set_trsw_override(struct brcms_phy *pi, bool tx,
979 static void wlc_lcnphy_set_bbmult(struct brcms_phy *pi, u8 m0);
980 static u8 wlc_lcnphy_get_bbmult(struct brcms_phy *pi);
981 static void wlc_lcnphy_get_tx_gain(struct brcms_phy *pi,
982 struct lcnphy_txgains *gains);
983 static void wlc_lcnphy_set_tx_gain_override(struct brcms_phy *pi, bool bEnable);
984 static void wlc_lcnphy_toggle_afe_pwdn(struct brcms_phy *pi);
985 static void wlc_lcnphy_rx_gain_override_enable(struct brcms_phy *pi,
987 static void wlc_lcnphy_set_tx_gain(struct brcms_phy *pi,
988 struct lcnphy_txgains *target_gains);
989 static bool wlc_lcnphy_rx_iq_est(struct brcms_phy *pi, u16 num_samps,
990 u8 wait_time, struct lcnphy_iq_est *iq_est);
991 static bool wlc_lcnphy_calc_rx_iq_comp(struct brcms_phy *pi, u16 num_samps);
992 static u16 wlc_lcnphy_get_pa_gain(struct brcms_phy *pi);
993 static void wlc_lcnphy_afe_clk_init(struct brcms_phy *pi, u8 mode);
994 static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi);
995 static void wlc_lcnphy_radio_2064_channel_tune_4313(struct brcms_phy *pi,
998 static void wlc_lcnphy_load_tx_gain_table(
999 struct brcms_phy *pi,
1000 const struct lcnphy_tx_gain_tbl_entry
1003 static void wlc_lcnphy_samp_cap(struct brcms_phy *pi, int clip_detect_algo,
1004 u16 thresh, s16 *ptr, int mode);
1005 static int wlc_lcnphy_calc_floor(s16 coeff, int type);
1006 static void wlc_lcnphy_tx_iqlo_loopback(struct brcms_phy *pi,
1007 u16 *values_to_save);
1008 static void wlc_lcnphy_tx_iqlo_loopback_cleanup(struct brcms_phy *pi,
1009 u16 *values_to_save);
1010 static void wlc_lcnphy_set_cc(struct brcms_phy *pi, int cal_type, s16 coeff_x,
1012 static struct lcnphy_unsign16_struct wlc_lcnphy_get_cc(struct brcms_phy *pi,
1014 static void wlc_lcnphy_a1(struct brcms_phy *pi, int cal_type,
1015 int num_levels, int step_size_lg2);
1016 static void wlc_lcnphy_tx_iqlo_soft_cal_full(struct brcms_phy *pi);
1018 static void wlc_lcnphy_set_chanspec_tweaks(struct brcms_phy *pi,
1020 static void wlc_lcnphy_agc_temp_init(struct brcms_phy *pi);
1021 static void wlc_lcnphy_temp_adj(struct brcms_phy *pi);
1022 static void wlc_lcnphy_clear_papd_comptable(struct brcms_phy *pi);
1023 static void wlc_lcnphy_baseband_init(struct brcms_phy *pi);
1024 static void wlc_lcnphy_radio_init(struct brcms_phy *pi);
1025 static void wlc_lcnphy_rc_cal(struct brcms_phy *pi);
1026 static void wlc_lcnphy_rcal(struct brcms_phy *pi);
1027 static void wlc_lcnphy_txrx_spur_avoidance_mode(struct brcms_phy *pi,
1029 static int wlc_lcnphy_load_tx_iir_filter(struct brcms_phy *pi, bool is_ofdm,
1031 static void wlc_lcnphy_set_rx_iq_comp(struct brcms_phy *pi, u16 a, u16 b);
1033 void wlc_lcnphy_write_table(struct brcms_phy *pi, const struct phytbl_info *pti)
1035 wlc_phy_write_table(pi, pti, 0x455, 0x457, 0x456);
1038 void wlc_lcnphy_read_table(struct brcms_phy *pi, struct phytbl_info *pti)
1040 wlc_phy_read_table(pi, pti, 0x455, 0x457, 0x456);
1044 wlc_lcnphy_common_read_table(struct brcms_phy *pi, u32 tbl_id,
1045 const u16 *tbl_ptr, u32 tbl_len,
1046 u32 tbl_width, u32 tbl_offset)
1048 struct phytbl_info tab;
1049 tab.tbl_id = tbl_id;
1050 tab.tbl_ptr = tbl_ptr;
1051 tab.tbl_len = tbl_len;
1052 tab.tbl_width = tbl_width;
1053 tab.tbl_offset = tbl_offset;
1054 wlc_lcnphy_read_table(pi, &tab);
1058 wlc_lcnphy_common_write_table(struct brcms_phy *pi, u32 tbl_id,
1059 const u16 *tbl_ptr, u32 tbl_len,
1060 u32 tbl_width, u32 tbl_offset)
1063 struct phytbl_info tab;
1064 tab.tbl_id = tbl_id;
1065 tab.tbl_ptr = tbl_ptr;
1066 tab.tbl_len = tbl_len;
1067 tab.tbl_width = tbl_width;
1068 tab.tbl_offset = tbl_offset;
1069 wlc_lcnphy_write_table(pi, &tab);
1073 wlc_lcnphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1075 u32 quotient, remainder, roundup, rbit;
1077 quotient = dividend / divisor;
1078 remainder = dividend % divisor;
1080 roundup = (divisor >> 1) + rbit;
1082 while (precision--) {
1084 if (remainder >= roundup) {
1086 remainder = ((remainder - roundup) << 1) + rbit;
1092 if (remainder >= roundup)
1098 static int wlc_lcnphy_calc_floor(s16 coeff_x, int type)
1104 k = (coeff_x - 1) / 2;
1110 if ((coeff_x + 1) < 0)
1113 k = (coeff_x + 1) / 2;
1118 s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi)
1121 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1123 if (txpwrctrl_off(pi))
1124 index = pi_lcn->lcnphy_current_index;
1125 else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
1126 index = (s8) (wlc_lcnphy_get_current_tx_pwr_idx_if_pwrctrl_on(
1129 index = pi_lcn->lcnphy_current_index;
1133 static u32 wlc_lcnphy_measure_digital_power(struct brcms_phy *pi, u16 nsamples)
1135 struct lcnphy_iq_est iq_est = { 0, 0, 0 };
1137 if (!wlc_lcnphy_rx_iq_est(pi, nsamples, 32, &iq_est))
1139 return (iq_est.i_pwr + iq_est.q_pwr) / nsamples;
1142 void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel)
1144 u16 afectrlovr, afectrlovrval;
1145 afectrlovr = read_phy_reg(pi, 0x43b);
1146 afectrlovrval = read_phy_reg(pi, 0x43c);
1148 mod_phy_reg(pi, 0x43b, (0x1 << 1), (1) << 1);
1150 mod_phy_reg(pi, 0x43c, (0x1 << 1), (0) << 1);
1152 mod_phy_reg(pi, 0x43b, (0x1 << 4), (1) << 4);
1154 mod_phy_reg(pi, 0x43c, (0x1 << 6), (0) << 6);
1156 write_phy_reg(pi, 0x44b, 0xffff);
1157 wlc_lcnphy_tx_pu(pi, 1);
1159 mod_phy_reg(pi, 0x634, (0xff << 8), (0) << 8);
1161 or_phy_reg(pi, 0x6da, 0x0080);
1163 or_phy_reg(pi, 0x00a, 0x228);
1165 and_phy_reg(pi, 0x00a, ~(0x228));
1167 and_phy_reg(pi, 0x6da, 0xFF7F);
1168 write_phy_reg(pi, 0x43b, afectrlovr);
1169 write_phy_reg(pi, 0x43c, afectrlovrval);
1173 static void wlc_lcnphy_toggle_afe_pwdn(struct brcms_phy *pi)
1175 u16 save_AfeCtrlOvrVal, save_AfeCtrlOvr;
1177 save_AfeCtrlOvrVal = read_phy_reg(pi, 0x43c);
1178 save_AfeCtrlOvr = read_phy_reg(pi, 0x43b);
1180 write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal | 0x1);
1181 write_phy_reg(pi, 0x43b, save_AfeCtrlOvr | 0x1);
1183 write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal & 0xfffe);
1184 write_phy_reg(pi, 0x43b, save_AfeCtrlOvr & 0xfffe);
1186 write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal);
1187 write_phy_reg(pi, 0x43b, save_AfeCtrlOvr);
1191 wlc_lcnphy_txrx_spur_avoidance_mode(struct brcms_phy *pi, bool enable)
1194 write_phy_reg(pi, 0x942, 0x7);
1195 write_phy_reg(pi, 0x93b, ((1 << 13) + 23));
1196 write_phy_reg(pi, 0x93c, ((1 << 13) + 1989));
1198 write_phy_reg(pi, 0x44a, 0x084);
1199 write_phy_reg(pi, 0x44a, 0x080);
1200 write_phy_reg(pi, 0x6d3, 0x2222);
1201 write_phy_reg(pi, 0x6d3, 0x2220);
1203 write_phy_reg(pi, 0x942, 0x0);
1204 write_phy_reg(pi, 0x93b, ((0 << 13) + 23));
1205 write_phy_reg(pi, 0x93c, ((0 << 13) + 1989));
1207 wlapi_switch_macfreq(pi->sh->physhim, enable);
1210 void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec)
1212 u8 channel = CHSPEC_CHANNEL(chanspec);
1214 wlc_phy_chanspec_radio_set((struct brcms_phy_pub *) pi, chanspec);
1216 wlc_lcnphy_set_chanspec_tweaks(pi, pi->radio_chanspec);
1218 or_phy_reg(pi, 0x44a, 0x44);
1219 write_phy_reg(pi, 0x44a, 0x80);
1221 wlc_lcnphy_radio_2064_channel_tune_4313(pi, channel);
1224 wlc_lcnphy_toggle_afe_pwdn(pi);
1226 write_phy_reg(pi, 0x657, lcnphy_sfo_cfg[channel - 1].ptcentreTs20);
1227 write_phy_reg(pi, 0x658, lcnphy_sfo_cfg[channel - 1].ptcentreFactor);
1229 if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
1230 mod_phy_reg(pi, 0x448, (0x3 << 8), (2) << 8);
1232 wlc_lcnphy_load_tx_iir_filter(pi, false, 3);
1234 mod_phy_reg(pi, 0x448, (0x3 << 8), (1) << 8);
1236 wlc_lcnphy_load_tx_iir_filter(pi, false, 2);
1239 wlc_lcnphy_load_tx_iir_filter(pi, true, 0);
1241 mod_phy_reg(pi, 0x4eb, (0x7 << 3), (1) << 3);
1245 static void wlc_lcnphy_set_dac_gain(struct brcms_phy *pi, u16 dac_gain)
1249 dac_ctrl = (read_phy_reg(pi, 0x439) >> 0);
1250 dac_ctrl = dac_ctrl & 0xc7f;
1251 dac_ctrl = dac_ctrl | (dac_gain << 7);
1252 mod_phy_reg(pi, 0x439, (0xfff << 0), (dac_ctrl) << 0);
1256 static void wlc_lcnphy_set_tx_gain_override(struct brcms_phy *pi, bool bEnable)
1258 u16 bit = bEnable ? 1 : 0;
1260 mod_phy_reg(pi, 0x4b0, (0x1 << 7), bit << 7);
1262 mod_phy_reg(pi, 0x4b0, (0x1 << 14), bit << 14);
1264 mod_phy_reg(pi, 0x43b, (0x1 << 6), bit << 6);
1267 static u16 wlc_lcnphy_get_pa_gain(struct brcms_phy *pi)
1271 pa_gain = (read_phy_reg(pi, 0x4fb) &
1272 LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK) >>
1273 LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT;
1278 static void wlc_lcnphy_set_tx_gain(struct brcms_phy *pi,
1279 struct lcnphy_txgains *target_gains)
1281 u16 pa_gain = wlc_lcnphy_get_pa_gain(pi);
1286 ((target_gains->gm_gain) |
1287 (target_gains->pga_gain << 8)) <<
1289 mod_phy_reg(pi, 0x4fb,
1291 ((target_gains->pad_gain) | (pa_gain << 8)) << 0);
1296 ((target_gains->gm_gain) |
1297 (target_gains->pga_gain << 8)) <<
1299 mod_phy_reg(pi, 0x4fd,
1301 ((target_gains->pad_gain) | (pa_gain << 8)) << 0);
1303 wlc_lcnphy_set_dac_gain(pi, target_gains->dac_gain);
1305 wlc_lcnphy_enable_tx_gain_override(pi);
1308 static void wlc_lcnphy_set_bbmult(struct brcms_phy *pi, u8 m0)
1310 u16 m0m1 = (u16) m0 << 8;
1311 struct phytbl_info tab;
1313 tab.tbl_ptr = &m0m1;
1315 tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
1316 tab.tbl_offset = 87;
1318 wlc_lcnphy_write_table(pi, &tab);
1321 static void wlc_lcnphy_clear_tx_power_offsets(struct brcms_phy *pi)
1324 struct phytbl_info tab;
1326 memset(data_buf, 0, sizeof(data_buf));
1328 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
1330 tab.tbl_ptr = data_buf;
1332 if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
1335 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
1336 wlc_lcnphy_write_table(pi, &tab);
1340 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_MAC_OFFSET;
1341 wlc_lcnphy_write_table(pi, &tab);
1344 enum lcnphy_tssi_mode {
1346 LCNPHY_TSSI_POST_PA,
1351 wlc_lcnphy_set_tssi_mux(struct brcms_phy *pi, enum lcnphy_tssi_mode pos)
1353 mod_phy_reg(pi, 0x4d7, (0x1 << 0), (0x1) << 0);
1355 mod_phy_reg(pi, 0x4d7, (0x1 << 6), (1) << 6);
1357 if (LCNPHY_TSSI_POST_PA == pos) {
1358 mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0) << 2);
1360 mod_phy_reg(pi, 0x4d9, (0x1 << 3), (1) << 3);
1362 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
1363 mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
1365 mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1);
1366 mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
1369 mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2);
1371 mod_phy_reg(pi, 0x4d9, (0x1 << 3), (0) << 3);
1373 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
1374 mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
1376 mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0);
1377 mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
1380 mod_phy_reg(pi, 0x637, (0x3 << 14), (0) << 14);
1382 if (LCNPHY_TSSI_EXT == pos) {
1383 write_radio_reg(pi, RADIO_2064_REG07F, 1);
1384 mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 0x2);
1385 mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 0x1 << 7);
1386 mod_radio_reg(pi, RADIO_2064_REG028, 0x1f, 0x3);
1390 static u16 wlc_lcnphy_rfseq_tbl_adc_pwrup(struct brcms_phy *pi)
1392 u16 N1, N2, N3, N4, N5, N6, N;
1393 N1 = ((read_phy_reg(pi, 0x4a5) & (0xff << 0))
1395 N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12))
1397 N3 = ((read_phy_reg(pi, 0x40d) & (0xff << 0))
1399 N4 = 1 << ((read_phy_reg(pi, 0x40d) & (0x7 << 8))
1401 N5 = ((read_phy_reg(pi, 0x4a2) & (0xff << 0))
1403 N6 = 1 << ((read_phy_reg(pi, 0x4a2) & (0x7 << 8))
1405 N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80;
1411 static void wlc_lcnphy_pwrctrl_rssiparams(struct brcms_phy *pi)
1413 u16 auxpga_vmid, auxpga_vmid_temp, auxpga_gain_temp;
1414 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1416 auxpga_vmid = (2 << 8) |
1417 (pi_lcn->lcnphy_rssi_vc << 4) | pi_lcn->lcnphy_rssi_vf;
1418 auxpga_vmid_temp = (2 << 8) | (8 << 4) | 4;
1419 auxpga_gain_temp = 2;
1421 mod_phy_reg(pi, 0x4d8, (0x1 << 0), (0) << 0);
1423 mod_phy_reg(pi, 0x4d8, (0x1 << 1), (0) << 1);
1425 mod_phy_reg(pi, 0x4d7, (0x1 << 3), (0) << 3);
1427 mod_phy_reg(pi, 0x4db,
1430 (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
1432 mod_phy_reg(pi, 0x4dc,
1435 (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
1437 mod_phy_reg(pi, 0x40a,
1440 (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
1442 mod_phy_reg(pi, 0x40b,
1445 (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
1447 mod_phy_reg(pi, 0x40c,
1450 (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
1452 mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5));
1455 static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
1457 struct phytbl_info tab;
1460 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
1465 for (ind = 0; ind < 128; ind++) {
1466 wlc_lcnphy_write_table(pi, &tab);
1469 tab.tbl_offset = 704;
1470 for (ind = 0; ind < 128; ind++) {
1471 wlc_lcnphy_write_table(pi, &tab);
1474 mod_phy_reg(pi, 0x503, (0x1 << 0), (0) << 0);
1476 mod_phy_reg(pi, 0x503, (0x1 << 2), (0) << 2);
1478 mod_phy_reg(pi, 0x503, (0x1 << 4), (1) << 4);
1480 wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
1481 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
1483 mod_phy_reg(pi, 0x4a4, (0x1 << 15), (1) << 15);
1485 mod_phy_reg(pi, 0x4d0, (0x1 << 5), (0) << 5);
1487 mod_phy_reg(pi, 0x4a4, (0x1ff << 0), (0) << 0);
1489 mod_phy_reg(pi, 0x4a5, (0xff << 0), (255) << 0);
1491 mod_phy_reg(pi, 0x4a5, (0x7 << 12), (5) << 12);
1493 mod_phy_reg(pi, 0x4a5, (0x7 << 8), (0) << 8);
1495 mod_phy_reg(pi, 0x40d, (0xff << 0), (64) << 0);
1497 mod_phy_reg(pi, 0x40d, (0x7 << 8), (4) << 8);
1499 mod_phy_reg(pi, 0x4a2, (0xff << 0), (64) << 0);
1501 mod_phy_reg(pi, 0x4a2, (0x7 << 8), (4) << 8);
1503 mod_phy_reg(pi, 0x4d0, (0x1ff << 6), (0) << 6);
1505 mod_phy_reg(pi, 0x4a8, (0xff << 0), (0x1) << 0);
1507 wlc_lcnphy_clear_tx_power_offsets(pi);
1509 mod_phy_reg(pi, 0x4a6, (0x1 << 15), (1) << 15);
1511 mod_phy_reg(pi, 0x4a6, (0x1ff << 0), (0xff) << 0);
1513 mod_phy_reg(pi, 0x49a, (0x1ff << 0), (0xff) << 0);
1515 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
1516 mod_radio_reg(pi, RADIO_2064_REG028, 0xf, 0xe);
1517 mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
1519 mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
1520 mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 1 << 3);
1523 write_radio_reg(pi, RADIO_2064_REG025, 0xc);
1525 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
1526 mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
1528 if (CHSPEC_IS2G(pi->radio_chanspec))
1529 mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 1 << 1);
1531 mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 0 << 1);
1534 if (LCNREV_IS(pi->pubpi.phy_rev, 2))
1535 mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 1 << 1);
1537 mod_radio_reg(pi, RADIO_2064_REG03A, 0x4, 1 << 2);
1539 mod_radio_reg(pi, RADIO_2064_REG11A, 0x1, 1 << 0);
1541 mod_radio_reg(pi, RADIO_2064_REG005, 0x8, 1 << 3);
1543 if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
1544 mod_phy_reg(pi, 0x4d7,
1545 (0x1 << 3) | (0x7 << 12), 0 << 3 | 2 << 12);
1547 rfseq = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi);
1548 tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
1550 tab.tbl_ptr = &rfseq;
1553 wlc_lcnphy_write_table(pi, &tab);
1555 mod_phy_reg(pi, 0x938, (0x1 << 2), (1) << 2);
1557 mod_phy_reg(pi, 0x939, (0x1 << 2), (1) << 2);
1559 mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
1561 mod_phy_reg(pi, 0x4d7, (0x1 << 2), (1) << 2);
1563 mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8);
1565 wlc_lcnphy_pwrctrl_rssiparams(pi);
1568 void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi)
1570 u16 tx_cnt, tx_total, npt;
1571 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1573 tx_total = wlc_lcnphy_total_tx_frames(pi);
1574 tx_cnt = tx_total - pi_lcn->lcnphy_tssi_tx_cnt;
1575 npt = wlc_lcnphy_get_tx_pwr_npt(pi);
1577 if (tx_cnt > (1 << npt)) {
1579 pi_lcn->lcnphy_tssi_tx_cnt = tx_total;
1581 pi_lcn->lcnphy_tssi_idx = wlc_lcnphy_get_current_tx_pwr_idx(pi);
1582 pi_lcn->lcnphy_tssi_npt = npt;
1587 s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1)
1591 a = 32768 + (a1 * tssi);
1592 b = (1024 * b0) + (64 * b1 * tssi);
1593 p = ((2 * b) + a) / (2 * a);
1598 static void wlc_lcnphy_txpower_reset_npt(struct brcms_phy *pi)
1600 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1601 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
1604 pi_lcn->lcnphy_tssi_idx = LCNPHY_TX_PWR_CTRL_START_INDEX_2G_4313;
1605 pi_lcn->lcnphy_tssi_npt = LCNPHY_TX_PWR_CTRL_START_NPT;
1608 void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi)
1610 struct phytbl_info tab;
1611 u32 rate_table[BRCMS_NUM_RATES_CCK + BRCMS_NUM_RATES_OFDM +
1612 BRCMS_NUM_RATES_MCS_1_STREAM];
1614 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
1617 for (i = 0, j = 0; i < ARRAY_SIZE(rate_table); i++, j++) {
1619 if (i == BRCMS_NUM_RATES_CCK + BRCMS_NUM_RATES_OFDM)
1620 j = TXP_FIRST_MCS_20_SISO;
1622 rate_table[i] = (u32) ((s32) (-pi->tx_power_offset[j]));
1625 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
1627 tab.tbl_len = ARRAY_SIZE(rate_table);
1628 tab.tbl_ptr = rate_table;
1629 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
1630 wlc_lcnphy_write_table(pi, &tab);
1632 if (wlc_lcnphy_get_target_tx_pwr(pi) != pi->tx_power_min) {
1633 wlc_lcnphy_set_target_tx_pwr(pi, pi->tx_power_min);
1635 wlc_lcnphy_txpower_reset_npt(pi);
1639 static void wlc_lcnphy_set_tx_pwr_soft_ctrl(struct brcms_phy *pi, s8 index)
1641 u32 cck_offset[4] = { 22, 22, 22, 22 };
1642 u32 ofdm_offset, reg_offset_cck;
1645 struct phytbl_info tab;
1647 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
1650 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x1) << 14);
1652 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x0) << 14);
1654 or_phy_reg(pi, 0x6da, 0x0040);
1657 for (i = 0; i < 4; i++)
1658 cck_offset[i] -= reg_offset_cck;
1659 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
1662 tab.tbl_ptr = cck_offset;
1663 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
1664 wlc_lcnphy_write_table(pi, &tab);
1667 tab.tbl_ptr = &ofdm_offset;
1668 for (i = 836; i < 862; i++) {
1670 wlc_lcnphy_write_table(pi, &tab);
1673 mod_phy_reg(pi, 0x4a4, (0x1 << 15), (0x1) << 15);
1675 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x1) << 14);
1677 mod_phy_reg(pi, 0x4a4, (0x1 << 13), (0x1) << 13);
1679 mod_phy_reg(pi, 0x4b0, (0x1 << 7), (0) << 7);
1681 mod_phy_reg(pi, 0x43b, (0x1 << 6), (0) << 6);
1683 mod_phy_reg(pi, 0x4a9, (0x1 << 15), (1) << 15);
1685 index2 = (u16) (index * 2);
1686 mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0);
1688 mod_phy_reg(pi, 0x6a3, (0x1 << 4), (0) << 4);
1692 static s8 wlc_lcnphy_tempcompensated_txpwrctrl(struct brcms_phy *pi)
1694 s8 index, delta_brd, delta_temp, new_index, tempcorrx;
1695 s16 manp, meas_temp, temp_diff;
1698 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1700 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
1701 return pi_lcn->lcnphy_current_index;
1703 index = FIXED_TXPWR;
1705 if (pi_lcn->lcnphy_tempsense_slope == 0)
1708 temp = (u16) wlc_lcnphy_tempsense(pi, 0);
1709 meas_temp = LCNPHY_TEMPSENSE(temp);
1711 if (pi->tx_power_min != 0)
1712 delta_brd = (pi_lcn->lcnphy_measPower - pi->tx_power_min);
1716 manp = LCNPHY_TEMPSENSE(pi_lcn->lcnphy_rawtempsense);
1717 temp_diff = manp - meas_temp;
1718 if (temp_diff < 0) {
1720 temp_diff = -temp_diff;
1723 delta_temp = (s8) wlc_lcnphy_qdiv_roundup((u32) (temp_diff * 192),
1725 lcnphy_tempsense_slope
1728 delta_temp = -delta_temp;
1730 if (pi_lcn->lcnphy_tempsense_option == 3
1731 && LCNREV_IS(pi->pubpi.phy_rev, 0))
1733 if (pi_lcn->lcnphy_tempcorrx > 31)
1734 tempcorrx = (s8) (pi_lcn->lcnphy_tempcorrx - 64);
1736 tempcorrx = (s8) pi_lcn->lcnphy_tempcorrx;
1737 if (LCNREV_IS(pi->pubpi.phy_rev, 1))
1740 index + delta_brd + delta_temp - pi_lcn->lcnphy_bandedge_corr;
1741 new_index += tempcorrx;
1743 if (LCNREV_IS(pi->pubpi.phy_rev, 1))
1746 if (new_index < 0 || new_index > 126)
1752 static u16 wlc_lcnphy_set_tx_pwr_ctrl_mode(struct brcms_phy *pi, u16 mode)
1755 u16 current_mode = mode;
1756 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) &&
1757 mode == LCNPHY_TX_PWR_CTRL_HW)
1758 current_mode = LCNPHY_TX_PWR_CTRL_TEMPBASED;
1759 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) &&
1760 mode == LCNPHY_TX_PWR_CTRL_TEMPBASED)
1761 current_mode = LCNPHY_TX_PWR_CTRL_HW;
1762 return current_mode;
1765 void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode)
1767 u16 old_mode = wlc_lcnphy_get_tx_pwr_ctrl(pi);
1769 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1771 mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, mode);
1772 old_mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, old_mode);
1774 mod_phy_reg(pi, 0x6da, (0x1 << 6),
1775 ((LCNPHY_TX_PWR_CTRL_HW == mode) ? 1 : 0) << 6);
1777 mod_phy_reg(pi, 0x6a3, (0x1 << 4),
1778 ((LCNPHY_TX_PWR_CTRL_HW == mode) ? 0 : 1) << 4);
1780 if (old_mode != mode) {
1781 if (LCNPHY_TX_PWR_CTRL_HW == old_mode) {
1783 wlc_lcnphy_tx_pwr_update_npt(pi);
1785 wlc_lcnphy_clear_tx_power_offsets(pi);
1787 if (LCNPHY_TX_PWR_CTRL_HW == mode) {
1789 wlc_lcnphy_txpower_recalc_target(pi);
1791 wlc_lcnphy_set_start_tx_pwr_idx(pi,
1794 wlc_lcnphy_set_tx_pwr_npt(pi, pi_lcn->lcnphy_tssi_npt);
1795 mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 0);
1797 pi_lcn->lcnphy_tssi_tx_cnt =
1798 wlc_lcnphy_total_tx_frames(pi);
1800 wlc_lcnphy_disable_tx_gain_override(pi);
1801 pi_lcn->lcnphy_tx_power_idx_override = -1;
1803 wlc_lcnphy_enable_tx_gain_override(pi);
1805 mod_phy_reg(pi, 0x4a4,
1806 ((0x1 << 15) | (0x1 << 14) | (0x1 << 13)), mode);
1807 if (mode == LCNPHY_TX_PWR_CTRL_TEMPBASED) {
1808 index = wlc_lcnphy_tempcompensated_txpwrctrl(pi);
1809 wlc_lcnphy_set_tx_pwr_soft_ctrl(pi, index);
1810 pi_lcn->lcnphy_current_index = (s8)
1818 static bool wlc_lcnphy_iqcal_wait(struct brcms_phy *pi)
1820 uint delay_count = 0;
1822 while (wlc_lcnphy_iqcal_active(pi)) {
1826 if (delay_count > (10 * 500))
1830 return (0 == wlc_lcnphy_iqcal_active(pi));
1834 wlc_lcnphy_tx_iqlo_cal(struct brcms_phy *pi,
1835 struct lcnphy_txgains *target_gains,
1836 enum lcnphy_cal_mode cal_mode, bool keep_tone)
1839 struct lcnphy_txgains cal_gains, temp_gains;
1843 u16 ncorr_override[5];
1844 u16 syst_coeffs[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
1845 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
1847 u16 commands_fullcal[] = {
1848 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234
1851 u16 commands_recal[] = {
1852 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234
1855 u16 command_nums_fullcal[] = {
1856 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97
1859 u16 command_nums_recal[] = {
1860 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97
1862 u16 *command_nums = command_nums_fullcal;
1864 u16 *start_coeffs = NULL, *cal_cmds = NULL, cal_type, diq_start;
1865 u16 tx_pwr_ctrl_old, save_txpwrctrlrfctrl2;
1866 u16 save_sslpnCalibClkEnCtrl, save_sslpnRxFeClkEnCtrl;
1867 bool tx_gain_override_old;
1868 struct lcnphy_txgains old_gains;
1869 uint i, n_cal_cmds = 0, n_cal_start = 0;
1870 u16 *values_to_save;
1871 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
1873 values_to_save = kmalloc(sizeof(u16) * 20, GFP_ATOMIC);
1874 if (NULL == values_to_save)
1877 save_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
1878 save_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
1880 or_phy_reg(pi, 0x6da, 0x40);
1881 or_phy_reg(pi, 0x6db, 0x3);
1884 case LCNPHY_CAL_FULL:
1885 start_coeffs = syst_coeffs;
1886 cal_cmds = commands_fullcal;
1887 n_cal_cmds = ARRAY_SIZE(commands_fullcal);
1890 case LCNPHY_CAL_RECAL:
1891 start_coeffs = syst_coeffs;
1892 cal_cmds = commands_recal;
1893 n_cal_cmds = ARRAY_SIZE(commands_recal);
1894 command_nums = command_nums_recal;
1901 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
1902 start_coeffs, 11, 16, 64);
1904 write_phy_reg(pi, 0x6da, 0xffff);
1905 mod_phy_reg(pi, 0x503, (0x1 << 3), (1) << 3);
1907 tx_pwr_ctrl_old = wlc_lcnphy_get_tx_pwr_ctrl(pi);
1909 mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
1911 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
1913 save_txpwrctrlrfctrl2 = read_phy_reg(pi, 0x4db);
1915 mod_phy_reg(pi, 0x4db, (0x3ff << 0), (0x2a6) << 0);
1917 mod_phy_reg(pi, 0x4db, (0x7 << 12), (2) << 12);
1919 wlc_lcnphy_tx_iqlo_loopback(pi, values_to_save);
1921 tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
1922 if (tx_gain_override_old)
1923 wlc_lcnphy_get_tx_gain(pi, &old_gains);
1925 if (!target_gains) {
1926 if (!tx_gain_override_old)
1927 wlc_lcnphy_set_tx_pwr_by_index(pi,
1928 pi_lcn->lcnphy_tssi_idx);
1929 wlc_lcnphy_get_tx_gain(pi, &temp_gains);
1930 target_gains = &temp_gains;
1933 hash = (target_gains->gm_gain << 8) |
1934 (target_gains->pga_gain << 4) | (target_gains->pad_gain);
1936 band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0);
1938 cal_gains = *target_gains;
1939 memset(ncorr_override, 0, sizeof(ncorr_override));
1940 for (j = 0; j < iqcal_gainparams_numgains_lcnphy[band_idx]; j++) {
1941 if (hash == tbl_iqcal_gainparams_lcnphy[band_idx][j][0]) {
1943 tbl_iqcal_gainparams_lcnphy[band_idx][j][1];
1944 cal_gains.pga_gain =
1945 tbl_iqcal_gainparams_lcnphy[band_idx][j][2];
1946 cal_gains.pad_gain =
1947 tbl_iqcal_gainparams_lcnphy[band_idx][j][3];
1948 memcpy(ncorr_override,
1949 &tbl_iqcal_gainparams_lcnphy[band_idx][j][3],
1950 sizeof(ncorr_override));
1955 wlc_lcnphy_set_tx_gain(pi, &cal_gains);
1957 write_phy_reg(pi, 0x453, 0xaa9);
1958 write_phy_reg(pi, 0x93d, 0xc0);
1960 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
1961 lcnphy_iqcal_loft_gainladder,
1962 ARRAY_SIZE(lcnphy_iqcal_loft_gainladder),
1965 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
1966 lcnphy_iqcal_ir_gainladder,
1968 lcnphy_iqcal_ir_gainladder), 16,
1971 if (pi->phy_tx_tone_freq) {
1973 wlc_lcnphy_stop_tx_tone(pi);
1975 wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
1977 wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
1980 write_phy_reg(pi, 0x6da, 0xffff);
1982 for (i = n_cal_start; i < n_cal_cmds; i++) {
1984 u16 best_coeffs[11];
1987 cal_type = (cal_cmds[i] & 0x0f00) >> 8;
1989 command_num = command_nums[i];
1990 if (ncorr_override[cal_type])
1992 ncorr_override[cal_type] << 8 | (command_num &
1995 write_phy_reg(pi, 0x452, command_num);
1997 if ((cal_type == 3) || (cal_type == 4)) {
1998 wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
1999 &diq_start, 1, 16, 69);
2001 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2002 &zero_diq, 1, 16, 69);
2005 write_phy_reg(pi, 0x451, cal_cmds[i]);
2007 if (!wlc_lcnphy_iqcal_wait(pi))
2010 wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2012 ARRAY_SIZE(best_coeffs), 16, 96);
2013 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2015 ARRAY_SIZE(best_coeffs), 16, 64);
2017 if ((cal_type == 3) || (cal_type == 4))
2018 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2019 &diq_start, 1, 16, 69);
2020 wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2021 pi_lcn->lcnphy_cal_results.
2022 txiqlocal_bestcoeffs,
2025 txiqlocal_bestcoeffs),
2029 wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2030 pi_lcn->lcnphy_cal_results.
2031 txiqlocal_bestcoeffs,
2032 ARRAY_SIZE(pi_lcn->lcnphy_cal_results.
2033 txiqlocal_bestcoeffs), 16, 96);
2034 pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs_valid = true;
2036 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2037 &pi_lcn->lcnphy_cal_results.
2038 txiqlocal_bestcoeffs[0], 4, 16, 80);
2040 wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
2041 &pi_lcn->lcnphy_cal_results.
2042 txiqlocal_bestcoeffs[5], 2, 16, 85);
2045 wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, values_to_save);
2046 kfree(values_to_save);
2049 wlc_lcnphy_stop_tx_tone(pi);
2051 write_phy_reg(pi, 0x4db, save_txpwrctrlrfctrl2);
2053 write_phy_reg(pi, 0x453, 0);
2055 if (tx_gain_override_old)
2056 wlc_lcnphy_set_tx_gain(pi, &old_gains);
2057 wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl_old);
2059 write_phy_reg(pi, 0x6da, save_sslpnCalibClkEnCtrl);
2060 write_phy_reg(pi, 0x6db, save_sslpnRxFeClkEnCtrl);
2064 static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi)
2066 bool suspend, tx_gain_override_old;
2067 struct lcnphy_txgains old_gains;
2068 struct brcms_phy *pi = (struct brcms_phy *) ppi;
2069 u16 idleTssi, idleTssi0_2C, idleTssi0_OB, idleTssi0_regvalue_OB,
2070 idleTssi0_regvalue_2C;
2071 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
2072 u16 SAVE_lpfgain = read_radio_reg(pi, RADIO_2064_REG112);
2073 u16 SAVE_jtag_bb_afe_switch =
2074 read_radio_reg(pi, RADIO_2064_REG007) & 1;
2075 u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10;
2076 u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4;
2077 idleTssi = read_phy_reg(pi, 0x4ab);
2080 (R_REG(&((struct brcms_phy *) pi)->regs->maccontrol) &
2083 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2084 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
2086 tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
2087 wlc_lcnphy_get_tx_gain(pi, &old_gains);
2089 wlc_lcnphy_enable_tx_gain_override(pi);
2090 wlc_lcnphy_set_tx_pwr_by_index(pi, 127);
2091 write_radio_reg(pi, RADIO_2064_REG112, 0x6);
2092 mod_radio_reg(pi, RADIO_2064_REG007, 0x1, 1);
2093 mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 1 << 4);
2094 mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 1 << 2);
2095 wlc_lcnphy_tssi_setup(pi);
2096 wlc_phy_do_dummy_tx(pi, true, OFF);
2097 idleTssi = ((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
2100 idleTssi0_2C = ((read_phy_reg(pi, 0x63e) & (0x1ff << 0))
2103 if (idleTssi0_2C >= 256)
2104 idleTssi0_OB = idleTssi0_2C - 256;
2106 idleTssi0_OB = idleTssi0_2C + 256;
2108 idleTssi0_regvalue_OB = idleTssi0_OB;
2109 if (idleTssi0_regvalue_OB >= 256)
2110 idleTssi0_regvalue_2C = idleTssi0_regvalue_OB - 256;
2112 idleTssi0_regvalue_2C = idleTssi0_regvalue_OB + 256;
2113 mod_phy_reg(pi, 0x4a6, (0x1ff << 0), (idleTssi0_regvalue_2C) << 0);
2115 mod_phy_reg(pi, 0x44c, (0x1 << 12), (0) << 12);
2117 wlc_lcnphy_set_tx_gain_override(pi, tx_gain_override_old);
2118 wlc_lcnphy_set_tx_gain(pi, &old_gains);
2119 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
2121 write_radio_reg(pi, RADIO_2064_REG112, SAVE_lpfgain);
2122 mod_radio_reg(pi, RADIO_2064_REG007, 0x1, SAVE_jtag_bb_afe_switch);
2123 mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, SAVE_jtag_auxpga);
2124 mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, SAVE_iqadc_aux_en);
2125 mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1 << 7);
2127 wlapi_enable_mac(pi->sh->physhim);
2130 static void wlc_lcnphy_vbat_temp_sense_setup(struct brcms_phy *pi, u8 mode)
2133 u16 save_txpwrCtrlEn;
2134 u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain;
2136 struct phytbl_info tab;
2138 u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025,
2140 u16 values_to_save[14];
2143 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2146 save_reg007 = (u8) read_radio_reg(pi, RADIO_2064_REG007);
2147 save_reg0FF = (u8) read_radio_reg(pi, RADIO_2064_REG0FF);
2148 save_reg11F = (u8) read_radio_reg(pi, RADIO_2064_REG11F);
2149 save_reg005 = (u8) read_radio_reg(pi, RADIO_2064_REG005);
2150 save_reg025 = (u8) read_radio_reg(pi, RADIO_2064_REG025);
2151 save_reg112 = (u8) read_radio_reg(pi, RADIO_2064_REG112);
2153 for (i = 0; i < 14; i++)
2154 values_to_save[i] = read_phy_reg(pi, tempsense_phy_regs[i]);
2155 suspend = (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
2157 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2158 save_txpwrCtrlEn = read_radio_reg(pi, 0x4a4);
2160 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
2161 index = pi_lcn->lcnphy_current_index;
2162 wlc_lcnphy_set_tx_pwr_by_index(pi, 127);
2163 mod_radio_reg(pi, RADIO_2064_REG007, 0x1, 0x1);
2164 mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 0x1 << 4);
2165 mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 0x1 << 2);
2166 mod_phy_reg(pi, 0x503, (0x1 << 0), (0) << 0);
2168 mod_phy_reg(pi, 0x503, (0x1 << 2), (0) << 2);
2170 mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
2172 mod_phy_reg(pi, 0x4a4, (0x1 << 15), (0) << 15);
2174 mod_phy_reg(pi, 0x4d0, (0x1 << 5), (0) << 5);
2176 mod_phy_reg(pi, 0x4a5, (0xff << 0), (255) << 0);
2178 mod_phy_reg(pi, 0x4a5, (0x7 << 12), (5) << 12);
2180 mod_phy_reg(pi, 0x4a5, (0x7 << 8), (0) << 8);
2182 mod_phy_reg(pi, 0x40d, (0xff << 0), (64) << 0);
2184 mod_phy_reg(pi, 0x40d, (0x7 << 8), (6) << 8);
2186 mod_phy_reg(pi, 0x4a2, (0xff << 0), (64) << 0);
2188 mod_phy_reg(pi, 0x4a2, (0x7 << 8), (6) << 8);
2190 mod_phy_reg(pi, 0x4d9, (0x7 << 4), (2) << 4);
2192 mod_phy_reg(pi, 0x4d9, (0x7 << 8), (3) << 8);
2194 mod_phy_reg(pi, 0x4d9, (0x7 << 12), (1) << 12);
2196 mod_phy_reg(pi, 0x4da, (0x1 << 12), (0) << 12);
2198 mod_phy_reg(pi, 0x4da, (0x1 << 13), (1) << 13);
2200 mod_phy_reg(pi, 0x4a6, (0x1 << 15), (1) << 15);
2202 write_radio_reg(pi, RADIO_2064_REG025, 0xC);
2204 mod_radio_reg(pi, RADIO_2064_REG005, 0x8, 0x1 << 3);
2206 mod_phy_reg(pi, 0x938, (0x1 << 2), (1) << 2);
2208 mod_phy_reg(pi, 0x939, (0x1 << 2), (1) << 2);
2210 mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
2212 val = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi);
2213 tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
2218 wlc_lcnphy_write_table(pi, &tab);
2219 if (mode == TEMPSENSE) {
2220 mod_phy_reg(pi, 0x4d7, (0x1 << 3), (1) << 3);
2222 mod_phy_reg(pi, 0x4d7, (0x7 << 12), (1) << 12);
2224 auxpga_vmidcourse = 8;
2225 auxpga_vmidfine = 0x4;
2227 mod_radio_reg(pi, RADIO_2064_REG082, 0x20, 1 << 5);
2229 mod_phy_reg(pi, 0x4d7, (0x1 << 3), (1) << 3);
2231 mod_phy_reg(pi, 0x4d7, (0x7 << 12), (3) << 12);
2233 auxpga_vmidcourse = 7;
2234 auxpga_vmidfine = 0xa;
2238 (u16) ((2 << 8) | (auxpga_vmidcourse << 4) | auxpga_vmidfine);
2239 mod_phy_reg(pi, 0x4d8, (0x1 << 0), (1) << 0);
2241 mod_phy_reg(pi, 0x4d8, (0x3ff << 2), (auxpga_vmid) << 2);
2243 mod_phy_reg(pi, 0x4d8, (0x1 << 1), (1) << 1);
2245 mod_phy_reg(pi, 0x4d8, (0x7 << 12), (auxpga_gain) << 12);
2247 mod_phy_reg(pi, 0x4d0, (0x1 << 5), (1) << 5);
2249 write_radio_reg(pi, RADIO_2064_REG112, 0x6);
2251 wlc_phy_do_dummy_tx(pi, true, OFF);
2252 if (!tempsense_done(pi))
2255 write_radio_reg(pi, RADIO_2064_REG007, (u16) save_reg007);
2256 write_radio_reg(pi, RADIO_2064_REG0FF, (u16) save_reg0FF);
2257 write_radio_reg(pi, RADIO_2064_REG11F, (u16) save_reg11F);
2258 write_radio_reg(pi, RADIO_2064_REG005, (u16) save_reg005);
2259 write_radio_reg(pi, RADIO_2064_REG025, (u16) save_reg025);
2260 write_radio_reg(pi, RADIO_2064_REG112, (u16) save_reg112);
2261 for (i = 0; i < 14; i++)
2262 write_phy_reg(pi, tempsense_phy_regs[i], values_to_save[i]);
2263 wlc_lcnphy_set_tx_pwr_by_index(pi, (int)index);
2265 write_radio_reg(pi, 0x4a4, save_txpwrCtrlEn);
2267 wlapi_enable_mac(pi->sh->physhim);
2271 static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi)
2273 struct lcnphy_txgains tx_gains;
2275 struct phytbl_info tab;
2277 s32 tssi, pwr, maxtargetpwr, mintargetpwr;
2279 struct brcms_phy *pi = (struct brcms_phy *) ppi;
2282 (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
2284 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2286 if (!pi->hwpwrctrl_capable) {
2287 if (CHSPEC_IS2G(pi->radio_chanspec)) {
2288 tx_gains.gm_gain = 4;
2289 tx_gains.pga_gain = 12;
2290 tx_gains.pad_gain = 12;
2291 tx_gains.dac_gain = 0;
2295 tx_gains.gm_gain = 7;
2296 tx_gains.pga_gain = 15;
2297 tx_gains.pad_gain = 14;
2298 tx_gains.dac_gain = 0;
2302 wlc_lcnphy_set_tx_gain(pi, &tx_gains);
2303 wlc_lcnphy_set_bbmult(pi, bbmult);
2304 wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
2307 wlc_lcnphy_idle_tssi_est(ppi);
2309 wlc_lcnphy_clear_tx_power_offsets(pi);
2311 b0 = pi->txpa_2g[0];
2312 b1 = pi->txpa_2g[1];
2313 a1 = pi->txpa_2g[2];
2314 maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1);
2315 mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1);
2317 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
2322 for (tssi = 0; tssi < 128; tssi++) {
2323 pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1);
2325 pwr = (pwr < mintargetpwr) ? mintargetpwr : pwr;
2326 wlc_lcnphy_write_table(pi, &tab);
2330 mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7);
2332 write_phy_reg(pi, 0x4a8, 10);
2334 wlc_lcnphy_set_target_tx_pwr(pi, LCN_TARGET_PWR);
2336 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
2339 wlapi_enable_mac(pi->sh->physhim);
2342 static u8 wlc_lcnphy_get_bbmult(struct brcms_phy *pi)
2345 struct phytbl_info tab;
2347 tab.tbl_ptr = &m0m1;
2349 tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
2350 tab.tbl_offset = 87;
2352 wlc_lcnphy_read_table(pi, &tab);
2354 return (u8) ((m0m1 & 0xff00) >> 8);
2357 static void wlc_lcnphy_set_pa_gain(struct brcms_phy *pi, u16 gain)
2359 mod_phy_reg(pi, 0x4fb,
2360 LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK,
2361 gain << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT);
2362 mod_phy_reg(pi, 0x4fd,
2363 LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_MASK,
2364 gain << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT);
2368 wlc_lcnphy_get_radio_loft(struct brcms_phy *pi,
2369 u8 *ei0, u8 *eq0, u8 *fi0, u8 *fq0)
2371 *ei0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG089));
2372 *eq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08A));
2373 *fi0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08B));
2374 *fq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08C));
2378 wlc_lcnphy_get_tx_gain(struct brcms_phy *pi, struct lcnphy_txgains *gains)
2382 dac_gain = read_phy_reg(pi, 0x439) >> 0;
2383 gains->dac_gain = (dac_gain & 0x380) >> 7;
2386 u16 rfgain0, rfgain1;
2388 rfgain0 = (read_phy_reg(pi, 0x4b5) & (0xffff << 0)) >> 0;
2389 rfgain1 = (read_phy_reg(pi, 0x4fb) & (0x7fff << 0)) >> 0;
2391 gains->gm_gain = rfgain0 & 0xff;
2392 gains->pga_gain = (rfgain0 >> 8) & 0xff;
2393 gains->pad_gain = rfgain1 & 0xff;
2397 void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b)
2399 struct phytbl_info tab;
2405 tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
2409 tab.tbl_offset = 80;
2410 wlc_lcnphy_write_table(pi, &tab);
2413 void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq)
2415 struct phytbl_info tab;
2417 tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
2419 tab.tbl_ptr = &didq;
2421 tab.tbl_offset = 85;
2422 wlc_lcnphy_write_table(pi, &tab);
2425 void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index)
2427 struct phytbl_info tab;
2430 u32 bbmultiqcomp, txgain, locoeffs, rfpower;
2431 struct lcnphy_txgains gains;
2432 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2434 pi_lcn->lcnphy_tx_power_idx_override = (s8) index;
2435 pi_lcn->lcnphy_current_index = (u8) index;
2437 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
2441 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
2443 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + index;
2444 tab.tbl_ptr = &bbmultiqcomp;
2445 wlc_lcnphy_read_table(pi, &tab);
2447 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + index;
2449 tab.tbl_ptr = &txgain;
2450 wlc_lcnphy_read_table(pi, &tab);
2452 gains.gm_gain = (u16) (txgain & 0xff);
2453 gains.pga_gain = (u16) (txgain >> 8) & 0xff;
2454 gains.pad_gain = (u16) (txgain >> 16) & 0xff;
2455 gains.dac_gain = (u16) (bbmultiqcomp >> 28) & 0x07;
2456 wlc_lcnphy_set_tx_gain(pi, &gains);
2457 wlc_lcnphy_set_pa_gain(pi, (u16) (txgain >> 24) & 0x7f);
2459 bb_mult = (u8) ((bbmultiqcomp >> 20) & 0xff);
2460 wlc_lcnphy_set_bbmult(pi, bb_mult);
2462 wlc_lcnphy_enable_tx_gain_override(pi);
2464 if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
2466 a = (u16) ((bbmultiqcomp >> 10) & 0x3ff);
2467 b = (u16) (bbmultiqcomp & 0x3ff);
2468 wlc_lcnphy_set_tx_iqcc(pi, a, b);
2470 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + index;
2471 tab.tbl_ptr = &locoeffs;
2472 wlc_lcnphy_read_table(pi, &tab);
2474 wlc_lcnphy_set_tx_locc(pi, (u16) locoeffs);
2476 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index;
2477 tab.tbl_ptr = &rfpower;
2478 wlc_lcnphy_read_table(pi, &tab);
2479 mod_phy_reg(pi, 0x6a6, (0x1fff << 0), (rfpower * 8) << 0);
2484 static void wlc_lcnphy_set_trsw_override(struct brcms_phy *pi, bool tx, bool rx)
2487 mod_phy_reg(pi, 0x44d,
2489 (0x1 << 0), (tx ? (0x1 << 1) : 0) | (rx ? (0x1 << 0) : 0));
2491 or_phy_reg(pi, 0x44c, (0x1 << 1) | (0x1 << 0));
2494 static void wlc_lcnphy_clear_papd_comptable(struct brcms_phy *pi)
2497 struct phytbl_info tab;
2498 u32 temp_offset[128];
2499 tab.tbl_ptr = temp_offset;
2501 tab.tbl_id = LCNPHY_TBL_ID_PAPDCOMPDELTATBL;
2505 memset(temp_offset, 0, sizeof(temp_offset));
2506 for (j = 1; j < 128; j += 2)
2507 temp_offset[j] = 0x80000;
2509 wlc_lcnphy_write_table(pi, &tab);
2514 wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi,
2519 u16 tia, u16 lna2, u16 lna1)
2521 u16 gain0_15, gain16_19;
2523 gain16_19 = biq2 & 0xf;
2524 gain0_15 = ((biq1 & 0xf) << 12) |
2525 ((tia & 0xf) << 8) |
2526 ((lna2 & 0x3) << 6) |
2528 0x3) << 4) | ((lna1 & 0x3) << 2) | ((lna1 & 0x3) << 0);
2530 mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
2531 mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
2532 mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
2534 if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
2535 mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
2536 mod_phy_reg(pi, 0x4b1, (0x1 << 10), ext_lna << 10);
2538 mod_phy_reg(pi, 0x4b1, (0x1 << 10), 0 << 10);
2540 mod_phy_reg(pi, 0x4b1, (0x1 << 15), 0 << 15);
2542 mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
2545 mod_phy_reg(pi, 0x44d, (0x1 << 0), (!trsw) << 0);
2550 wlc_lcnphy_rx_gain_override_enable(struct brcms_phy *pi, bool enable)
2552 u16 ebit = enable ? 1 : 0;
2554 mod_phy_reg(pi, 0x4b0, (0x1 << 8), ebit << 8);
2556 mod_phy_reg(pi, 0x44c, (0x1 << 0), ebit << 0);
2558 if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
2559 mod_phy_reg(pi, 0x44c, (0x1 << 4), ebit << 4);
2560 mod_phy_reg(pi, 0x44c, (0x1 << 6), ebit << 6);
2561 mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5);
2562 mod_phy_reg(pi, 0x4b0, (0x1 << 6), ebit << 6);
2564 mod_phy_reg(pi, 0x4b0, (0x1 << 12), ebit << 12);
2565 mod_phy_reg(pi, 0x4b0, (0x1 << 13), ebit << 13);
2566 mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5);
2569 if (CHSPEC_IS2G(pi->radio_chanspec)) {
2570 mod_phy_reg(pi, 0x4b0, (0x1 << 10), ebit << 10);
2571 mod_phy_reg(pi, 0x4e5, (0x1 << 3), ebit << 3);
2575 void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable)
2579 and_phy_reg(pi, 0x43b, ~(u16) ((0x1 << 1) | (0x1 << 4)));
2581 mod_phy_reg(pi, 0x43c, (0x1 << 1), 1 << 1);
2583 and_phy_reg(pi, 0x44c,
2584 ~(u16) ((0x1 << 3) |
2587 (0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
2589 and_phy_reg(pi, 0x44d,
2590 ~(u16) ((0x1 << 3) | (0x1 << 5) | (0x1 << 14)));
2591 mod_phy_reg(pi, 0x44d, (0x1 << 2), 1 << 2);
2593 mod_phy_reg(pi, 0x44d, (0x1 << 1) | (0x1 << 0), (0x1 << 0));
2595 and_phy_reg(pi, 0x4f9,
2596 ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
2598 and_phy_reg(pi, 0x4fa,
2599 ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
2602 mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
2603 mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
2605 mod_phy_reg(pi, 0x43b, (0x1 << 4), 1 << 4);
2606 mod_phy_reg(pi, 0x43c, (0x1 << 6), 0 << 6);
2608 mod_phy_reg(pi, 0x44c, (0x1 << 12), 1 << 12);
2609 mod_phy_reg(pi, 0x44d, (0x1 << 14), 1 << 14);
2611 wlc_lcnphy_set_trsw_override(pi, true, false);
2613 mod_phy_reg(pi, 0x44d, (0x1 << 2), 0 << 2);
2614 mod_phy_reg(pi, 0x44c, (0x1 << 2), 1 << 2);
2616 if (CHSPEC_IS2G(pi->radio_chanspec)) {
2618 mod_phy_reg(pi, 0x44c, (0x1 << 3), 1 << 3);
2619 mod_phy_reg(pi, 0x44d, (0x1 << 3), 1 << 3);
2621 mod_phy_reg(pi, 0x44c, (0x1 << 5), 1 << 5);
2622 mod_phy_reg(pi, 0x44d, (0x1 << 5), 0 << 5);
2624 mod_phy_reg(pi, 0x4f9, (0x1 << 1), 1 << 1);
2625 mod_phy_reg(pi, 0x4fa, (0x1 << 1), 1 << 1);
2627 mod_phy_reg(pi, 0x4f9, (0x1 << 2), 1 << 2);
2628 mod_phy_reg(pi, 0x4fa, (0x1 << 2), 1 << 2);
2630 mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
2631 mod_phy_reg(pi, 0x4fa, (0x1 << 0), 1 << 0);
2634 mod_phy_reg(pi, 0x44c, (0x1 << 3), 1 << 3);
2635 mod_phy_reg(pi, 0x44d, (0x1 << 3), 0 << 3);
2637 mod_phy_reg(pi, 0x44c, (0x1 << 5), 1 << 5);
2638 mod_phy_reg(pi, 0x44d, (0x1 << 5), 1 << 5);
2640 mod_phy_reg(pi, 0x4f9, (0x1 << 1), 1 << 1);
2641 mod_phy_reg(pi, 0x4fa, (0x1 << 1), 0 << 1);
2643 mod_phy_reg(pi, 0x4f9, (0x1 << 2), 1 << 2);
2644 mod_phy_reg(pi, 0x4fa, (0x1 << 2), 0 << 2);
2646 mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
2647 mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
2653 wlc_lcnphy_run_samples(struct brcms_phy *pi,
2655 u16 num_loops, u16 wait, bool iqcalmode)
2658 or_phy_reg(pi, 0x6da, 0x8080);
2660 mod_phy_reg(pi, 0x642, (0x7f << 0), (num_samps - 1) << 0);
2661 if (num_loops != 0xffff)
2663 mod_phy_reg(pi, 0x640, (0xffff << 0), num_loops << 0);
2665 mod_phy_reg(pi, 0x641, (0xffff << 0), wait << 0);
2669 and_phy_reg(pi, 0x453, (u16) ~(0x1 << 15));
2670 or_phy_reg(pi, 0x453, (0x1 << 15));
2672 write_phy_reg(pi, 0x63f, 1);
2673 wlc_lcnphy_tx_pu(pi, 1);
2676 or_radio_reg(pi, RADIO_2064_REG112, 0x6);
2679 void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode)
2683 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
2685 if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
2686 mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
2687 mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
2689 mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
2690 mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
2694 mod_phy_reg((pi), 0x410,
2698 pi->radio_chanspec)) ? (!mode) : 0) <<
2700 mod_phy_reg(pi, 0x410, (0x1 << 7), (mode) << 7);
2705 wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz, u16 max_val,
2709 u16 num_samps, t, k;
2711 s32 theta = 0, rot = 0;
2712 struct cordic_iq tone_samp;
2715 struct phytbl_info tab;
2716 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2718 pi->phy_tx_tone_freq = f_kHz;
2720 wlc_lcnphy_deaf_mode(pi, true);
2723 if (pi_lcn->lcnphy_spurmod) {
2724 write_phy_reg(pi, 0x942, 0x2);
2725 write_phy_reg(pi, 0x93b, 0x0);
2726 write_phy_reg(pi, 0x93c, 0x0);
2727 wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
2733 bw = phy_bw * 1000 * k;
2734 num_samps = bw / ABS(f_kHz);
2736 } while ((num_samps * (u32) (ABS(f_kHz))) != bw);
2740 rot = ((f_kHz * 36) / phy_bw) / 100;
2743 for (t = 0; t < num_samps; t++) {
2745 tone_samp = cordic_calc_iq(theta);
2749 i_samp = (u16) (FLOAT(tone_samp.i * max_val) & 0x3ff);
2750 q_samp = (u16) (FLOAT(tone_samp.q * max_val) & 0x3ff);
2751 data_buf[t] = (i_samp << 10) | q_samp;
2754 mod_phy_reg(pi, 0x6d6, (0x3 << 0), 0 << 0);
2756 mod_phy_reg(pi, 0x6da, (0x1 << 3), 1 << 3);
2758 tab.tbl_ptr = data_buf;
2759 tab.tbl_len = num_samps;
2760 tab.tbl_id = LCNPHY_TBL_ID_SAMPLEPLAY;
2763 wlc_lcnphy_write_table(pi, &tab);
2765 wlc_lcnphy_run_samples(pi, num_samps, 0xffff, 0, iqcalmode);
2768 void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi)
2770 s16 playback_status;
2771 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2773 pi->phy_tx_tone_freq = 0;
2774 if (pi_lcn->lcnphy_spurmod) {
2775 write_phy_reg(pi, 0x942, 0x7);
2776 write_phy_reg(pi, 0x93b, 0x2017);
2777 write_phy_reg(pi, 0x93c, 0x27c5);
2778 wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
2781 playback_status = read_phy_reg(pi, 0x644);
2782 if (playback_status & (0x1 << 0)) {
2783 wlc_lcnphy_tx_pu(pi, 0);
2784 mod_phy_reg(pi, 0x63f, (0x1 << 1), 1 << 1);
2785 } else if (playback_status & (0x1 << 1))
2786 mod_phy_reg(pi, 0x453, (0x1 << 15), 0 << 15);
2788 mod_phy_reg(pi, 0x6d6, (0x3 << 0), 1 << 0);
2790 mod_phy_reg(pi, 0x6da, (0x1 << 3), 0 << 3);
2792 mod_phy_reg(pi, 0x6da, (0x1 << 7), 0 << 7);
2794 and_radio_reg(pi, RADIO_2064_REG112, 0xFFF9);
2796 wlc_lcnphy_deaf_mode(pi, false);
2799 static void wlc_lcnphy_clear_trsw_override(struct brcms_phy *pi)
2802 and_phy_reg(pi, 0x44c, (u16) ~((0x1 << 1) | (0x1 << 0)));
2805 void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b)
2808 struct phytbl_info tab;
2813 tab.tbl_offset = 80;
2815 wlc_lcnphy_read_table(pi, &tab);
2821 u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi)
2823 struct phytbl_info tab;
2828 tab.tbl_ptr = &didq;
2830 tab.tbl_offset = 85;
2831 wlc_lcnphy_read_table(pi, &tab);
2836 static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi)
2839 struct lcnphy_txgains target_gains, old_gains;
2841 u16 a, b, didq, save_pa_gain = 0;
2842 uint idx, SAVE_txpwrindex = 0xFF;
2844 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
2845 struct phytbl_info tab;
2846 u8 ei0, eq0, fi0, fq0;
2847 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2849 wlc_lcnphy_get_tx_gain(pi, &old_gains);
2850 save_pa_gain = wlc_lcnphy_get_pa_gain(pi);
2852 save_bb_mult = wlc_lcnphy_get_bbmult(pi);
2854 if (SAVE_txpwrctrl == LCNPHY_TX_PWR_CTRL_OFF)
2855 SAVE_txpwrindex = wlc_lcnphy_get_current_tx_pwr_idx(pi);
2857 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
2859 target_gains.gm_gain = 7;
2860 target_gains.pga_gain = 0;
2861 target_gains.pad_gain = 21;
2862 target_gains.dac_gain = 0;
2863 wlc_lcnphy_set_tx_gain(pi, &target_gains);
2864 wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
2866 if (LCNREV_IS(pi->pubpi.phy_rev, 1) || pi_lcn->lcnphy_hw_iqcal_en) {
2868 wlc_lcnphy_set_tx_pwr_by_index(pi, 30);
2870 wlc_lcnphy_tx_iqlo_cal(pi, &target_gains,
2872 lcnphy_recal ? LCNPHY_CAL_RECAL :
2873 LCNPHY_CAL_FULL), false);
2875 wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
2878 wlc_lcnphy_get_radio_loft(pi, &ei0, &eq0, &fi0, &fq0);
2879 if ((ABS((s8) fi0) == 15) && (ABS((s8) fq0) == 15)) {
2880 if (CHSPEC_IS5G(pi->radio_chanspec)) {
2881 target_gains.gm_gain = 255;
2882 target_gains.pga_gain = 255;
2883 target_gains.pad_gain = 0xf0;
2884 target_gains.dac_gain = 0;
2886 target_gains.gm_gain = 7;
2887 target_gains.pga_gain = 45;
2888 target_gains.pad_gain = 186;
2889 target_gains.dac_gain = 0;
2892 if (LCNREV_IS(pi->pubpi.phy_rev, 1)
2893 || pi_lcn->lcnphy_hw_iqcal_en) {
2895 target_gains.pga_gain = 0;
2896 target_gains.pad_gain = 30;
2897 wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
2898 wlc_lcnphy_tx_iqlo_cal(pi, &target_gains,
2899 LCNPHY_CAL_FULL, false);
2901 wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
2905 wlc_lcnphy_get_tx_iqcc(pi, &a, &b);
2907 didq = wlc_lcnphy_get_tx_locc(pi);
2909 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
2914 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
2916 for (idx = 0; idx < 128; idx++) {
2917 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + idx;
2919 wlc_lcnphy_read_table(pi, &tab);
2920 val = (val & 0xfff00000) |
2921 ((u32) (a & 0x3FF) << 10) | (b & 0x3ff);
2922 wlc_lcnphy_write_table(pi, &tab);
2925 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + idx;
2926 wlc_lcnphy_write_table(pi, &tab);
2929 pi_lcn->lcnphy_cal_results.txiqlocal_a = a;
2930 pi_lcn->lcnphy_cal_results.txiqlocal_b = b;
2931 pi_lcn->lcnphy_cal_results.txiqlocal_didq = didq;
2932 pi_lcn->lcnphy_cal_results.txiqlocal_ei0 = ei0;
2933 pi_lcn->lcnphy_cal_results.txiqlocal_eq0 = eq0;
2934 pi_lcn->lcnphy_cal_results.txiqlocal_fi0 = fi0;
2935 pi_lcn->lcnphy_cal_results.txiqlocal_fq0 = fq0;
2937 wlc_lcnphy_set_bbmult(pi, save_bb_mult);
2938 wlc_lcnphy_set_pa_gain(pi, save_pa_gain);
2939 wlc_lcnphy_set_tx_gain(pi, &old_gains);
2941 if (SAVE_txpwrctrl != LCNPHY_TX_PWR_CTRL_OFF)
2942 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
2944 wlc_lcnphy_set_tx_pwr_by_index(pi, SAVE_txpwrindex);
2947 s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode)
2949 u16 tempsenseval1, tempsenseval2;
2956 (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
2958 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2959 wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
2961 tempsenseval1 = read_phy_reg(pi, 0x476) & 0x1FF;
2962 tempsenseval2 = read_phy_reg(pi, 0x477) & 0x1FF;
2964 if (tempsenseval1 > 255)
2965 avg = (s16) (tempsenseval1 - 512);
2967 avg = (s16) tempsenseval1;
2969 if (tempsenseval2 > 255)
2970 avg += (s16) (tempsenseval2 - 512);
2972 avg += (s16) tempsenseval2;
2978 mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
2981 mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
2984 wlapi_enable_mac(pi->sh->physhim);
2989 u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode)
2991 u16 tempsenseval1, tempsenseval2;
2994 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
2995 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3000 (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
3002 wlapi_suspend_mac_and_wait(pi->sh->physhim);
3003 wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
3005 tempsenseval1 = read_phy_reg(pi, 0x476) & 0x1FF;
3006 tempsenseval2 = read_phy_reg(pi, 0x477) & 0x1FF;
3008 if (tempsenseval1 > 255)
3009 avg = (int)(tempsenseval1 - 512);
3011 avg = (int)tempsenseval1;
3013 if (pi_lcn->lcnphy_tempsense_option == 1 || pi->hwpwrctrl_capable) {
3014 if (tempsenseval2 > 255)
3015 avg = (int)(avg - tempsenseval2 + 512);
3017 avg = (int)(avg - tempsenseval2);
3019 if (tempsenseval2 > 255)
3020 avg = (int)(avg + tempsenseval2 - 512);
3022 avg = (int)(avg + tempsenseval2);
3028 if (pi_lcn->lcnphy_tempsense_option == 2)
3029 avg = tempsenseval1;
3032 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
3036 mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
3039 mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
3042 wlapi_enable_mac(pi->sh->physhim);
3047 s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode)
3049 s32 degree = wlc_lcnphy_tempsense_new(pi, mode);
3052 10) + LCN_TEMPSENSE_OFFSET + (LCN_TEMPSENSE_DEN >> 1))
3053 / LCN_TEMPSENSE_DEN;
3057 s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode)
3066 (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
3068 wlapi_suspend_mac_and_wait(pi->sh->physhim);
3069 wlc_lcnphy_vbat_temp_sense_setup(pi, VBATSENSE);
3072 vbatsenseval = read_phy_reg(pi, 0x475) & 0x1FF;
3074 if (vbatsenseval > 255)
3075 avg = (s32) (vbatsenseval - 512);
3077 avg = (s32) vbatsenseval;
3079 avg = (avg * LCN_VBAT_SCALE_NOM +
3080 (LCN_VBAT_SCALE_DEN >> 1)) / LCN_VBAT_SCALE_DEN;
3084 wlapi_enable_mac(pi->sh->physhim);
3089 static void wlc_lcnphy_afe_clk_init(struct brcms_phy *pi, u8 mode)
3092 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
3094 mod_phy_reg(pi, 0x6d1, (0x1 << 7), (1) << 7);
3096 if (((mode == AFE_CLK_INIT_MODE_PAPD) && (phybw40 == 0)) ||
3097 (mode == AFE_CLK_INIT_MODE_TXRX2X))
3098 write_phy_reg(pi, 0x6d0, 0x7);
3100 wlc_lcnphy_toggle_afe_pwdn(pi);
3104 wlc_lcnphy_rx_iq_est(struct brcms_phy *pi,
3106 u8 wait_time, struct lcnphy_iq_est *iq_est)
3111 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
3113 mod_phy_reg(pi, 0x6da, (0x1 << 5), (1) << 5);
3115 mod_phy_reg(pi, 0x410, (0x1 << 3), (0) << 3);
3117 mod_phy_reg(pi, 0x482, (0xffff << 0), (num_samps) << 0);
3119 mod_phy_reg(pi, 0x481, (0xff << 0), ((u16) wait_time) << 0);
3121 mod_phy_reg(pi, 0x481, (0x1 << 8), (0) << 8);
3123 mod_phy_reg(pi, 0x481, (0x1 << 9), (1) << 9);
3125 while (read_phy_reg(pi, 0x481) & (0x1 << 9)) {
3127 if (wait_count > (10 * 500)) {
3135 iq_est->iq_prod = ((u32) read_phy_reg(pi, 0x483) << 16) |
3136 (u32) read_phy_reg(pi, 0x484);
3137 iq_est->i_pwr = ((u32) read_phy_reg(pi, 0x485) << 16) |
3138 (u32) read_phy_reg(pi, 0x486);
3139 iq_est->q_pwr = ((u32) read_phy_reg(pi, 0x487) << 16) |
3140 (u32) read_phy_reg(pi, 0x488);
3143 mod_phy_reg(pi, 0x410, (0x1 << 3), (1) << 3);
3145 mod_phy_reg(pi, 0x6da, (0x1 << 5), (0) << 5);
3150 static bool wlc_lcnphy_calc_rx_iq_comp(struct brcms_phy *pi, u16 num_samps)
3152 #define LCNPHY_MIN_RXIQ_PWR 2
3155 struct lcnphy_iq_est iq_est = { 0, 0, 0 };
3157 s16 iq_nbits, qq_nbits, arsh, brsh;
3160 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3162 a0_new = ((read_phy_reg(pi, 0x645) & (0x3ff << 0)) >> 0);
3163 b0_new = ((read_phy_reg(pi, 0x646) & (0x3ff << 0)) >> 0);
3164 mod_phy_reg(pi, 0x6d1, (0x1 << 2), (0) << 2);
3166 mod_phy_reg(pi, 0x64b, (0x1 << 6), (1) << 6);
3168 wlc_lcnphy_set_rx_iq_comp(pi, 0, 0);
3170 result = wlc_lcnphy_rx_iq_est(pi, num_samps, 32, &iq_est);
3174 iq = (s32) iq_est.iq_prod;
3178 if ((ii + qq) < LCNPHY_MIN_RXIQ_PWR) {
3183 iq_nbits = wlc_phy_nbits(iq);
3184 qq_nbits = wlc_phy_nbits(qq);
3186 arsh = 10 - (30 - iq_nbits);
3188 a = (-(iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3189 temp = (s32) (ii >> arsh);
3193 a = (-(iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3194 temp = (s32) (ii << -arsh);
3199 brsh = qq_nbits - 31 + 20;
3201 b = (qq << (31 - qq_nbits));
3202 temp = (s32) (ii >> brsh);
3206 b = (qq << (31 - qq_nbits));
3207 temp = (s32) (ii << -brsh);
3213 b = (s32) int_sqrt((unsigned long) b);
3215 a0_new = (u16) (a & 0x3ff);
3216 b0_new = (u16) (b & 0x3ff);
3219 wlc_lcnphy_set_rx_iq_comp(pi, a0_new, b0_new);
3221 mod_phy_reg(pi, 0x64b, (0x1 << 0), (1) << 0);
3223 mod_phy_reg(pi, 0x64b, (0x1 << 3), (1) << 3);
3225 pi_lcn->lcnphy_cal_results.rxiqcal_coeff_a0 = a0_new;
3226 pi_lcn->lcnphy_cal_results.rxiqcal_coeff_b0 = b0_new;
3232 wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
3233 const struct lcnphy_rx_iqcomp *iqcomp,
3234 int iqcomp_sz, bool tx_switch, bool rx_switch, int module,
3237 struct lcnphy_txgains old_gains;
3239 u8 tx_gain_index_old = 0;
3240 bool result = false, tx_gain_override_old = false;
3241 u16 i, Core1TxControl_old, RFOverride0_old,
3242 RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old,
3243 rfoverride3_old, rfoverride3val_old, rfoverride4_old,
3244 rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
3246 u32 received_power, rx_pwr_threshold;
3247 u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
3248 u16 values_to_save[11];
3250 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3252 ptr = kmalloc(sizeof(s16) * 131, GFP_ATOMIC);
3256 while (iqcomp_sz--) {
3257 if (iqcomp[iqcomp_sz].chan ==
3258 CHSPEC_CHANNEL(pi->radio_chanspec)) {
3259 wlc_lcnphy_set_rx_iq_comp(pi,
3261 iqcomp[iqcomp_sz].a,
3263 iqcomp[iqcomp_sz].b);
3273 tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
3274 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
3276 for (i = 0; i < 11; i++)
3278 read_radio_reg(pi, rxiq_cal_rf_reg[i]);
3279 Core1TxControl_old = read_phy_reg(pi, 0x631);
3281 or_phy_reg(pi, 0x631, 0x0015);
3283 RFOverride0_old = read_phy_reg(pi, 0x44c);
3284 RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
3285 rfoverride2_old = read_phy_reg(pi, 0x4b0);
3286 rfoverride2val_old = read_phy_reg(pi, 0x4b1);
3287 rfoverride3_old = read_phy_reg(pi, 0x4f9);
3288 rfoverride3val_old = read_phy_reg(pi, 0x4fa);
3289 rfoverride4_old = read_phy_reg(pi, 0x938);
3290 rfoverride4val_old = read_phy_reg(pi, 0x939);
3291 afectrlovr_old = read_phy_reg(pi, 0x43b);
3292 afectrlovrval_old = read_phy_reg(pi, 0x43c);
3293 old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
3294 old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
3296 tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
3297 if (tx_gain_override_old) {
3298 wlc_lcnphy_get_tx_gain(pi, &old_gains);
3299 tx_gain_index_old = pi_lcn->lcnphy_current_index;
3302 wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
3304 mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
3305 mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
3307 mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
3308 mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
3310 write_radio_reg(pi, RADIO_2064_REG116, 0x06);
3311 write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
3312 write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
3313 write_radio_reg(pi, RADIO_2064_REG098, 0x03);
3314 write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
3315 mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
3316 write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
3317 write_radio_reg(pi, RADIO_2064_REG114, 0x01);
3318 write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
3319 write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
3321 mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
3322 mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
3323 mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
3324 mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
3325 mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
3326 mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
3327 mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
3328 mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
3329 mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
3330 mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
3332 mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
3333 mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
3335 wlc_lcnphy_start_tx_tone(pi, 2000, 120, 0);
3336 write_phy_reg(pi, 0x6da, 0xffff);
3337 or_phy_reg(pi, 0x6db, 0x3);
3338 wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
3339 wlc_lcnphy_rx_gain_override_enable(pi, true);
3342 rx_pwr_threshold = 950;
3343 while (tia_gain > 0) {
3345 wlc_lcnphy_set_rx_gain_by_distribution(pi,
3352 wlc_lcnphy_measure_digital_power(pi, 2000);
3353 if (received_power < rx_pwr_threshold)
3356 result = wlc_lcnphy_calc_rx_iq_comp(pi, 0xffff);
3358 wlc_lcnphy_stop_tx_tone(pi);
3360 write_phy_reg(pi, 0x631, Core1TxControl_old);
3362 write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
3363 write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
3364 write_phy_reg(pi, 0x4b0, rfoverride2_old);
3365 write_phy_reg(pi, 0x4b1, rfoverride2val_old);
3366 write_phy_reg(pi, 0x4f9, rfoverride3_old);
3367 write_phy_reg(pi, 0x4fa, rfoverride3val_old);
3368 write_phy_reg(pi, 0x938, rfoverride4_old);
3369 write_phy_reg(pi, 0x939, rfoverride4val_old);
3370 write_phy_reg(pi, 0x43b, afectrlovr_old);
3371 write_phy_reg(pi, 0x43c, afectrlovrval_old);
3372 write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
3373 write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
3375 wlc_lcnphy_clear_trsw_override(pi);
3377 mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
3379 for (i = 0; i < 11; i++)
3380 write_radio_reg(pi, rxiq_cal_rf_reg[i],
3383 if (tx_gain_override_old)
3384 wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
3386 wlc_lcnphy_disable_tx_gain_override(pi);
3388 wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
3389 wlc_lcnphy_rx_gain_override_enable(pi, false);
3397 static void wlc_lcnphy_temp_adj(struct brcms_phy *pi)
3401 static void wlc_lcnphy_glacial_timer_based_cal(struct brcms_phy *pi)
3405 u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
3406 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3408 (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
3410 wlapi_suspend_mac_and_wait(pi->sh->physhim);
3411 wlc_lcnphy_deaf_mode(pi, true);
3412 pi->phy_lastcal = pi->sh->now;
3413 pi->phy_forcecal = false;
3414 index = pi_lcn->lcnphy_current_index;
3416 wlc_lcnphy_txpwrtbl_iqlo_cal(pi);
3418 wlc_lcnphy_set_tx_pwr_by_index(pi, index);
3419 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_pwrctrl);
3420 wlc_lcnphy_deaf_mode(pi, false);
3422 wlapi_enable_mac(pi->sh->physhim);
3426 static void wlc_lcnphy_periodic_cal(struct brcms_phy *pi)
3428 bool suspend, full_cal;
3429 const struct lcnphy_rx_iqcomp *rx_iqcomp;
3431 u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
3433 struct phytbl_info tab;
3435 s32 tssi, pwr, maxtargetpwr, mintargetpwr;
3436 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3438 pi->phy_lastcal = pi->sh->now;
3439 pi->phy_forcecal = false;
3441 (pi_lcn->lcnphy_full_cal_channel !=
3442 CHSPEC_CHANNEL(pi->radio_chanspec));
3443 pi_lcn->lcnphy_full_cal_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
3444 index = pi_lcn->lcnphy_current_index;
3447 (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
3449 wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
3450 wlapi_suspend_mac_and_wait(pi->sh->physhim);
3453 wlc_lcnphy_deaf_mode(pi, true);
3455 wlc_lcnphy_txpwrtbl_iqlo_cal(pi);
3457 rx_iqcomp = lcnphy_rx_iqcomp_table_rev0;
3458 rx_iqcomp_sz = ARRAY_SIZE(lcnphy_rx_iqcomp_table_rev0);
3460 if (LCNREV_IS(pi->pubpi.phy_rev, 1))
3461 wlc_lcnphy_rx_iq_cal(pi, NULL, 0, true, false, 1, 40);
3463 wlc_lcnphy_rx_iq_cal(pi, NULL, 0, true, false, 1, 127);
3465 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) {
3467 wlc_lcnphy_idle_tssi_est((struct brcms_phy_pub *) pi);
3469 b0 = pi->txpa_2g[0];
3470 b1 = pi->txpa_2g[1];
3471 a1 = pi->txpa_2g[2];
3472 maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1);
3473 mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1);
3475 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
3480 for (tssi = 0; tssi < 128; tssi++) {
3481 pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1);
3482 pwr = (pwr < mintargetpwr) ? mintargetpwr : pwr;
3483 wlc_lcnphy_write_table(pi, &tab);
3488 wlc_lcnphy_set_tx_pwr_by_index(pi, index);
3489 wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_pwrctrl);
3490 wlc_lcnphy_deaf_mode(pi, false);
3492 wlapi_enable_mac(pi->sh->physhim);
3495 void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode)
3498 int temp1, temp2, temp_diff;
3499 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3502 case PHY_PERICAL_CHAN:
3505 wlc_lcnphy_periodic_cal(pi);
3507 case PHY_PERICAL_PHYINIT:
3508 wlc_lcnphy_periodic_cal(pi);
3510 case PHY_PERICAL_WATCHDOG:
3511 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
3512 temp_new = wlc_lcnphy_tempsense(pi, 0);
3513 temp1 = LCNPHY_TEMPSENSE(temp_new);
3514 temp2 = LCNPHY_TEMPSENSE(pi_lcn->lcnphy_cal_temper);
3515 temp_diff = temp1 - temp2;
3516 if ((pi_lcn->lcnphy_cal_counter > 90) ||
3517 (temp_diff > 60) || (temp_diff < -60)) {
3518 wlc_lcnphy_glacial_timer_based_cal(pi);
3519 wlc_2064_vco_cal(pi);
3520 pi_lcn->lcnphy_cal_temper = temp_new;
3521 pi_lcn->lcnphy_cal_counter = 0;
3523 pi_lcn->lcnphy_cal_counter++;
3526 case LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL:
3527 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
3528 wlc_lcnphy_tx_power_adjustment(
3529 (struct brcms_phy_pub *) pi);
3534 void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr, s8 *cck_pwr)
3538 status = (read_phy_reg(pi, 0x4ab));
3539 if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) &&
3540 (status & (0x1 << 15))) {
3541 *ofdm_pwr = (s8) (((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
3544 if (wlc_phy_tpc_isenabled_lcnphy(pi))
3545 cck_offset = pi->tx_power_offset[TXP_FIRST_CCK];
3549 *cck_pwr = *ofdm_pwr + cck_offset;
3556 void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi)
3563 wlc_lcnphy_set_chanspec_tweaks(struct brcms_phy *pi, u16 chanspec)
3565 u8 channel = CHSPEC_CHANNEL(chanspec);
3566 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3569 mod_phy_reg(pi, 0x448, (0x3 << 8), (2) << 8);
3571 mod_phy_reg(pi, 0x448, (0x3 << 8), (1) << 8);
3573 pi_lcn->lcnphy_bandedge_corr = 2;
3575 pi_lcn->lcnphy_bandedge_corr = 4;
3577 if (channel == 1 || channel == 2 || channel == 3 ||
3578 channel == 4 || channel == 9 ||
3579 channel == 10 || channel == 11 || channel == 12) {
3580 si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03000c04);
3581 si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x0);
3582 si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x200005c0);
3584 si_pmu_pllupd(pi->sh->sih);
3585 write_phy_reg(pi, 0x942, 0);
3586 wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
3587 pi_lcn->lcnphy_spurmod = 0;
3588 mod_phy_reg(pi, 0x424, (0xff << 8), (0x1b) << 8);
3590 write_phy_reg(pi, 0x425, 0x5907);
3592 si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03140c04);
3593 si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x333333);
3594 si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x202c2820);
3596 si_pmu_pllupd(pi->sh->sih);
3597 write_phy_reg(pi, 0x942, 0);
3598 wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
3600 pi_lcn->lcnphy_spurmod = 0;
3601 mod_phy_reg(pi, 0x424, (0xff << 8), (0x1f) << 8);
3603 write_phy_reg(pi, 0x425, 0x590a);
3606 or_phy_reg(pi, 0x44a, 0x44);
3607 write_phy_reg(pi, 0x44a, 0x80);
3610 void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi)
3614 struct brcms_phy *pi = (struct brcms_phy *) ppi;
3615 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3616 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
3617 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) &&
3619 index = wlc_lcnphy_tempcompensated_txpwrctrl(pi);
3620 index2 = (u16) (index * 2);
3621 mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0);
3623 pi_lcn->lcnphy_current_index =
3624 (s8)((read_phy_reg(pi, 0x4a9) & 0xFF) / 2);
3628 static void wlc_lcnphy_set_rx_iq_comp(struct brcms_phy *pi, u16 a, u16 b)
3630 mod_phy_reg(pi, 0x645, (0x3ff << 0), (a) << 0);
3632 mod_phy_reg(pi, 0x646, (0x3ff << 0), (b) << 0);
3634 mod_phy_reg(pi, 0x647, (0x3ff << 0), (a) << 0);
3636 mod_phy_reg(pi, 0x648, (0x3ff << 0), (b) << 0);
3638 mod_phy_reg(pi, 0x649, (0x3ff << 0), (a) << 0);
3640 mod_phy_reg(pi, 0x64a, (0x3ff << 0), (b) << 0);
3644 void wlc_phy_init_lcnphy(struct brcms_phy *pi)
3647 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3648 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
3650 pi_lcn->lcnphy_cal_counter = 0;
3651 pi_lcn->lcnphy_cal_temper = pi_lcn->lcnphy_rawtempsense;
3653 or_phy_reg(pi, 0x44a, 0x80);
3654 and_phy_reg(pi, 0x44a, 0x7f);
3656 wlc_lcnphy_afe_clk_init(pi, AFE_CLK_INIT_MODE_TXRX2X);
3658 write_phy_reg(pi, 0x60a, 160);
3660 write_phy_reg(pi, 0x46a, 25);
3662 wlc_lcnphy_baseband_init(pi);
3664 wlc_lcnphy_radio_init(pi);
3666 if (CHSPEC_IS2G(pi->radio_chanspec))
3667 wlc_lcnphy_tx_pwr_ctrl_init((struct brcms_phy_pub *) pi);
3669 wlc_phy_chanspec_set((struct brcms_phy_pub *) pi, pi->radio_chanspec);
3671 si_pmu_regcontrol(pi->sh->sih, 0, 0xf, 0x9);
3673 si_pmu_chipcontrol(pi->sh->sih, 0, 0xffffffff, 0x03CDDDDD);
3675 if ((pi->sh->boardflags & BFL_FEM)
3676 && wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
3677 wlc_lcnphy_set_tx_pwr_by_index(pi, FIXED_TXPWR);
3679 wlc_lcnphy_agc_temp_init(pi);
3681 wlc_lcnphy_temp_adj(pi);
3683 mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
3686 mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
3688 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
3689 pi_lcn->lcnphy_noise_samples = LCNPHY_NOISE_SAMPLES_DEFAULT;
3690 wlc_lcnphy_calib_modes(pi, PHY_PERICAL_PHYINIT);
3694 wlc_lcnphy_tx_iqlo_loopback(struct brcms_phy *pi, u16 *values_to_save)
3698 for (i = 0; i < 20; i++)
3700 read_radio_reg(pi, iqlo_loopback_rf_regs[i]);
3702 mod_phy_reg(pi, 0x44c, (0x1 << 12), 1 << 12);
3703 mod_phy_reg(pi, 0x44d, (0x1 << 14), 1 << 14);
3705 mod_phy_reg(pi, 0x44c, (0x1 << 11), 1 << 11);
3706 mod_phy_reg(pi, 0x44d, (0x1 << 13), 0 << 13);
3708 mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
3709 mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
3711 mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
3712 mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
3714 if (LCNREV_IS(pi->pubpi.phy_rev, 2))
3715 and_radio_reg(pi, RADIO_2064_REG03A, 0xFD);
3717 and_radio_reg(pi, RADIO_2064_REG03A, 0xF9);
3718 or_radio_reg(pi, RADIO_2064_REG11A, 0x1);
3720 or_radio_reg(pi, RADIO_2064_REG036, 0x01);
3721 or_radio_reg(pi, RADIO_2064_REG11A, 0x18);
3724 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
3725 if (CHSPEC_IS5G(pi->radio_chanspec))
3726 mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0);
3728 or_radio_reg(pi, RADIO_2064_REG03A, 1);
3730 if (CHSPEC_IS5G(pi->radio_chanspec))
3731 mod_radio_reg(pi, RADIO_2064_REG03A, 3, 1);
3733 or_radio_reg(pi, RADIO_2064_REG03A, 0x3);
3738 write_radio_reg(pi, RADIO_2064_REG025, 0xF);
3739 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
3740 if (CHSPEC_IS5G(pi->radio_chanspec))
3741 mod_radio_reg(pi, RADIO_2064_REG028, 0xF, 0x4);
3743 mod_radio_reg(pi, RADIO_2064_REG028, 0xF, 0x6);
3745 if (CHSPEC_IS5G(pi->radio_chanspec))
3746 mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x4 << 1);
3748 mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x6 << 1);
3753 write_radio_reg(pi, RADIO_2064_REG005, 0x8);
3754 or_radio_reg(pi, RADIO_2064_REG112, 0x80);
3757 or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
3758 or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
3761 or_radio_reg(pi, RADIO_2064_REG00B, 0x7);
3762 or_radio_reg(pi, RADIO_2064_REG113, 0x10);
3765 write_radio_reg(pi, RADIO_2064_REG007, 0x1);
3769 mod_radio_reg(pi, RADIO_2064_REG0FC, 0x3 << 0, (vmid >> 8) & 0x3);
3770 write_radio_reg(pi, RADIO_2064_REG0FD, (vmid & 0xff));
3771 or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
3774 or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
3776 write_radio_reg(pi, RADIO_2064_REG012, 0x02);
3777 or_radio_reg(pi, RADIO_2064_REG112, 0x06);
3778 write_radio_reg(pi, RADIO_2064_REG036, 0x11);
3779 write_radio_reg(pi, RADIO_2064_REG059, 0xcc);
3780 write_radio_reg(pi, RADIO_2064_REG05C, 0x2e);
3781 write_radio_reg(pi, RADIO_2064_REG078, 0xd7);
3782 write_radio_reg(pi, RADIO_2064_REG092, 0x15);
3786 wlc_lcnphy_samp_cap(struct brcms_phy *pi, int clip_detect_algo, u16 thresh,
3789 u32 curval1, curval2, stpptr, curptr, strptr, val;
3790 u16 sslpnCalibClkEnCtrl, timer;
3791 u16 old_sslpnCalibClkEnCtrl;
3793 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
3796 old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
3798 curval1 = R_REG(&pi->regs->psm_corectlsts);
3800 W_REG(&pi->regs->psm_corectlsts, ((1 << 6) | curval1));
3802 W_REG(&pi->regs->smpl_clct_strptr, 0x7E00);
3803 W_REG(&pi->regs->smpl_clct_stpptr, 0x8000);
3805 curval2 = R_REG(&pi->regs->psm_phy_hdr_param);
3806 W_REG(&pi->regs->psm_phy_hdr_param, curval2 | 0x30);
3808 write_phy_reg(pi, 0x555, 0x0);
3809 write_phy_reg(pi, 0x5a6, 0x5);
3811 write_phy_reg(pi, 0x5a2, (u16) (mode | mode << 6));
3812 write_phy_reg(pi, 0x5cf, 3);
3813 write_phy_reg(pi, 0x5a5, 0x3);
3814 write_phy_reg(pi, 0x583, 0x0);
3815 write_phy_reg(pi, 0x584, 0x0);
3816 write_phy_reg(pi, 0x585, 0x0fff);
3817 write_phy_reg(pi, 0x586, 0x0000);
3819 write_phy_reg(pi, 0x580, 0x4501);
3821 sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
3822 write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl | 0x2008));
3823 stpptr = R_REG(&pi->regs->smpl_clct_stpptr);
3824 curptr = R_REG(&pi->regs->smpl_clct_curptr);
3827 curptr = R_REG(&pi->regs->smpl_clct_curptr);
3829 } while ((curptr != stpptr) && (timer < 500));
3831 W_REG(&pi->regs->psm_phy_hdr_param, 0x2);
3833 W_REG(&pi->regs->tplatewrptr, strptr);
3834 while (strptr < 0x8000) {
3835 val = R_REG(&pi->regs->tplatewrdata);
3836 imag = ((val >> 16) & 0x3ff);
3837 real = ((val) & 0x3ff);
3844 if (pi_lcn->lcnphy_iqcal_swp_dis)
3845 ptr[(strptr - 0x7E00) / 4] = real;
3847 ptr[(strptr - 0x7E00) / 4] = imag;
3849 if (clip_detect_algo) {
3850 if (imag > thresh || imag < -thresh) {
3859 write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
3860 W_REG(&pi->regs->psm_phy_hdr_param, curval2);
3861 W_REG(&pi->regs->psm_corectlsts, curval1);
3864 static void wlc_lcnphy_tx_iqlo_soft_cal_full(struct brcms_phy *pi)
3866 struct lcnphy_unsign16_struct iqcc0, locc2, locc3, locc4;
3868 wlc_lcnphy_set_cc(pi, 0, 0, 0);
3869 wlc_lcnphy_set_cc(pi, 2, 0, 0);
3870 wlc_lcnphy_set_cc(pi, 3, 0, 0);
3871 wlc_lcnphy_set_cc(pi, 4, 0, 0);
3873 wlc_lcnphy_a1(pi, 4, 0, 0);
3874 wlc_lcnphy_a1(pi, 3, 0, 0);
3875 wlc_lcnphy_a1(pi, 2, 3, 2);
3876 wlc_lcnphy_a1(pi, 0, 5, 8);
3877 wlc_lcnphy_a1(pi, 2, 2, 1);
3878 wlc_lcnphy_a1(pi, 0, 4, 3);
3880 iqcc0 = wlc_lcnphy_get_cc(pi, 0);
3881 locc2 = wlc_lcnphy_get_cc(pi, 2);
3882 locc3 = wlc_lcnphy_get_cc(pi, 3);
3883 locc4 = wlc_lcnphy_get_cc(pi, 4);
3887 wlc_lcnphy_set_cc(struct brcms_phy *pi, int cal_type, s16 coeff_x, s16 coeff_y)
3894 wlc_lcnphy_set_tx_iqcc(pi, coeff_x, coeff_y);
3897 di0dq0 = (coeff_x & 0xff) << 8 | (coeff_y & 0xff);
3898 wlc_lcnphy_set_tx_locc(pi, di0dq0);
3901 k = wlc_lcnphy_calc_floor(coeff_x, 0);
3903 k = wlc_lcnphy_calc_floor(coeff_x, 1);
3905 data_rf = (x * 16 + y);
3906 write_radio_reg(pi, RADIO_2064_REG089, data_rf);
3907 k = wlc_lcnphy_calc_floor(coeff_y, 0);
3909 k = wlc_lcnphy_calc_floor(coeff_y, 1);
3911 data_rf = (x * 16 + y);
3912 write_radio_reg(pi, RADIO_2064_REG08A, data_rf);
3915 k = wlc_lcnphy_calc_floor(coeff_x, 0);
3917 k = wlc_lcnphy_calc_floor(coeff_x, 1);
3919 data_rf = (x * 16 + y);
3920 write_radio_reg(pi, RADIO_2064_REG08B, data_rf);
3921 k = wlc_lcnphy_calc_floor(coeff_y, 0);
3923 k = wlc_lcnphy_calc_floor(coeff_y, 1);
3925 data_rf = (x * 16 + y);
3926 write_radio_reg(pi, RADIO_2064_REG08C, data_rf);
3931 static struct lcnphy_unsign16_struct
3932 wlc_lcnphy_get_cc(struct brcms_phy *pi, int cal_type)
3935 u8 di0, dq0, ei, eq, fi, fq;
3936 struct lcnphy_unsign16_struct cc;
3941 wlc_lcnphy_get_tx_iqcc(pi, &a, &b);
3946 didq = wlc_lcnphy_get_tx_locc(pi);
3947 di0 = (((didq & 0xff00) << 16) >> 24);
3948 dq0 = (((didq & 0x00ff) << 24) >> 24);
3953 wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq);
3958 wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq);
3967 wlc_lcnphy_a1(struct brcms_phy *pi, int cal_type, int num_levels,
3970 const struct lcnphy_spb_tone *phy_c1;
3971 struct lcnphy_spb_tone phy_c2;
3972 struct lcnphy_unsign16_struct phy_c3;
3973 int phy_c4, phy_c5, k, l, j, phy_c6;
3974 u16 phy_c7, phy_c8, phy_c9;
3975 s16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16;
3977 s32 phy_c18, phy_c19;
3978 u32 phy_c20, phy_c21;
3979 bool phy_c22, phy_c23, phy_c24, phy_c25;
3980 u16 phy_c26, phy_c27;
3981 u16 phy_c28, phy_c29, phy_c30;
3985 phy_c10 = phy_c13 = phy_c14 = phy_c8 = 0;
3986 ptr = kmalloc(sizeof(s16) * 131, GFP_ATOMIC);
3990 phy_c32 = kmalloc(sizeof(u16) * 20, GFP_ATOMIC);
3991 if (NULL == phy_c32) {
3995 phy_c26 = read_phy_reg(pi, 0x6da);
3996 phy_c27 = read_phy_reg(pi, 0x6db);
3997 phy_c31 = read_radio_reg(pi, RADIO_2064_REG026);
3998 write_phy_reg(pi, 0x93d, 0xC0);
4000 wlc_lcnphy_start_tx_tone(pi, 3750, 88, 0);
4001 write_phy_reg(pi, 0x6da, 0xffff);
4002 or_phy_reg(pi, 0x6db, 0x3);
4004 wlc_lcnphy_tx_iqlo_loopback(pi, phy_c32);
4006 phy_c28 = read_phy_reg(pi, 0x938);
4007 phy_c29 = read_phy_reg(pi, 0x4d7);
4008 phy_c30 = read_phy_reg(pi, 0x4d8);
4009 or_phy_reg(pi, 0x938, 0x1 << 2);
4010 or_phy_reg(pi, 0x4d7, 0x1 << 2);
4011 or_phy_reg(pi, 0x4d7, 0x1 << 3);
4012 mod_phy_reg(pi, 0x4d7, (0x7 << 12), 0x2 << 12);
4013 or_phy_reg(pi, 0x4d8, 1 << 0);
4014 or_phy_reg(pi, 0x4d8, 1 << 1);
4015 mod_phy_reg(pi, 0x4d8, (0x3ff << 2), 0x23A << 2);
4016 mod_phy_reg(pi, 0x4d8, (0x7 << 12), 0x7 << 12);
4017 phy_c1 = &lcnphy_spb_tone_3750[0];
4020 if (num_levels == 0) {
4026 if (step_size_lg2 == 0) {
4033 phy_c7 = (1 << step_size_lg2);
4034 phy_c3 = wlc_lcnphy_get_cc(pi, cal_type);
4035 phy_c15 = (s16) phy_c3.re;
4036 phy_c16 = (s16) phy_c3.im;
4037 if (cal_type == 2) {
4038 if (phy_c3.re > 127)
4039 phy_c15 = phy_c3.re - 256;
4040 if (phy_c3.im > 127)
4041 phy_c16 = phy_c3.im - 256;
4043 wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
4045 for (phy_c8 = 0; phy_c7 != 0 && phy_c8 < num_levels; phy_c8++) {
4063 phy_c9 = read_phy_reg(pi, 0x93d);
4064 phy_c9 = 2 * phy_c9;
4069 write_radio_reg(pi, RADIO_2064_REG026,
4070 (phy_c5 & 0x7) | ((phy_c5 & 0x7) << 4));
4074 wlc_lcnphy_samp_cap(pi, 1, phy_c9, &ptr[0], 2);
4079 if ((phy_c22 != phy_c24) && (!phy_c25))
4083 if (phy_c5 <= 0 || phy_c5 >= 7)
4091 else if (phy_c5 > 7)
4094 for (k = -phy_c7; k <= phy_c7; k += phy_c7) {
4095 for (l = -phy_c7; l <= phy_c7; l += phy_c7) {
4096 phy_c11 = phy_c15 + k;
4097 phy_c12 = phy_c16 + l;
4099 if (phy_c11 < -phy_c10)
4101 else if (phy_c11 > phy_c10)
4103 if (phy_c12 < -phy_c10)
4105 else if (phy_c12 > phy_c10)
4107 wlc_lcnphy_set_cc(pi, cal_type, phy_c11,
4110 wlc_lcnphy_samp_cap(pi, 0, 0, ptr, 2);
4114 for (j = 0; j < 128; j++) {
4116 phy_c6 = j % phy_c4;
4118 phy_c6 = (2 * j) % phy_c4;
4120 phy_c2.re = phy_c1[phy_c6].re;
4121 phy_c2.im = phy_c1[phy_c6].im;
4123 phy_c18 = phy_c18 + phy_c17 * phy_c2.re;
4124 phy_c19 = phy_c19 + phy_c17 * phy_c2.im;
4127 phy_c18 = phy_c18 >> 10;
4128 phy_c19 = phy_c19 >> 10;
4129 phy_c20 = ((phy_c18 * phy_c18) +
4130 (phy_c19 * phy_c19));
4132 if (phy_c23 || phy_c20 < phy_c21) {
4143 phy_c7 = phy_c7 >> 1;
4144 wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
4149 wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, phy_c32);
4150 wlc_lcnphy_stop_tx_tone(pi);
4151 write_phy_reg(pi, 0x6da, phy_c26);
4152 write_phy_reg(pi, 0x6db, phy_c27);
4153 write_phy_reg(pi, 0x938, phy_c28);
4154 write_phy_reg(pi, 0x4d7, phy_c29);
4155 write_phy_reg(pi, 0x4d8, phy_c30);
4156 write_radio_reg(pi, RADIO_2064_REG026, phy_c31);
4163 wlc_lcnphy_tx_iqlo_loopback_cleanup(struct brcms_phy *pi, u16 *values_to_save)
4167 and_phy_reg(pi, 0x44c, 0x0 >> 11);
4169 and_phy_reg(pi, 0x43b, 0xC);
4171 for (i = 0; i < 20; i++)
4172 write_radio_reg(pi, iqlo_loopback_rf_regs[i],
4177 wlc_lcnphy_load_tx_gain_table(struct brcms_phy *pi,
4178 const struct lcnphy_tx_gain_tbl_entry *gain_table)
4181 struct phytbl_info tab;
4186 if (CHSPEC_IS5G(pi->radio_chanspec))
4191 if (pi->sh->boardflags & BFL_FEM)
4193 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
4198 for (j = 0; j < 128; j++) {
4199 gm_gain = gain_table[j].gm;
4200 val = (((u32) pa_gain << 24) |
4201 (gain_table[j].pad << 16) |
4202 (gain_table[j].pga << 8) | gm_gain);
4204 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + j;
4205 wlc_lcnphy_write_table(pi, &tab);
4207 val = (gain_table[j].dac << 28) | (gain_table[j].bb_mult << 20);
4208 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + j;
4209 wlc_lcnphy_write_table(pi, &tab);
4213 static void wlc_lcnphy_load_rfpower(struct brcms_phy *pi)
4215 struct phytbl_info tab;
4216 u32 val, bbmult, rfgain;
4218 u8 scale_factor = 1;
4219 s16 temp, temp1, temp2, qQ, qQ1, qQ2, shift;
4221 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
4225 for (index = 0; index < 128; index++) {
4226 tab.tbl_ptr = &bbmult;
4227 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + index;
4228 wlc_lcnphy_read_table(pi, &tab);
4229 bbmult = bbmult >> 20;
4231 tab.tbl_ptr = &rfgain;
4232 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + index;
4233 wlc_lcnphy_read_table(pi, &tab);
4235 qm_log10((s32) (bbmult), 0, &temp1, &qQ1);
4236 qm_log10((s32) (1 << 6), 0, &temp2, &qQ2);
4239 temp2 = qm_shr16(temp2, qQ2 - qQ1);
4242 temp1 = qm_shr16(temp1, qQ1 - qQ2);
4245 temp = qm_sub16(temp1, temp2);
4252 val = (((index << shift) + (5 * temp) +
4253 (1 << (scale_factor + shift - 3))) >> (scale_factor +
4257 tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index;
4258 wlc_lcnphy_write_table(pi, &tab);
4262 static void wlc_lcnphy_tbl_init(struct brcms_phy *pi)
4266 struct phytbl_info tab;
4269 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
4271 for (idx = 0; idx < dot11lcnphytbl_info_sz_rev0; idx++)
4272 wlc_lcnphy_write_table(pi, &dot11lcnphytbl_info_rev0[idx]);
4274 if (pi->sh->boardflags & BFL_FEM_BT) {
4275 tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
4281 wlc_lcnphy_write_table(pi, &tab);
4284 tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
4291 wlc_lcnphy_write_table(pi, &tab);
4295 wlc_lcnphy_write_table(pi, &tab);
4299 wlc_lcnphy_write_table(pi, &tab);
4301 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4302 if (pi->sh->boardflags & BFL_FEM)
4303 wlc_lcnphy_load_tx_gain_table(
4305 dot11lcnphy_2GHz_extPA_gaintable_rev0);
4307 wlc_lcnphy_load_tx_gain_table(
4309 dot11lcnphy_2GHz_gaintable_rev0);
4312 if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
4313 const struct phytbl_info *tb;
4316 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4317 l = dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
4318 if (pi->sh->boardflags & BFL_EXTLNA)
4319 tb = dot11lcnphytbl_rx_gain_info_extlna_2G_rev2;
4321 tb = dot11lcnphytbl_rx_gain_info_2G_rev2;
4323 l = dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
4324 if (pi->sh->boardflags & BFL_EXTLNA_5GHz)
4325 tb = dot11lcnphytbl_rx_gain_info_extlna_5G_rev2;
4327 tb = dot11lcnphytbl_rx_gain_info_5G_rev2;
4330 for (idx = 0; idx < l; idx++)
4331 wlc_lcnphy_write_table(pi, &tb[idx]);
4334 if ((pi->sh->boardflags & BFL_FEM)
4335 && !(pi->sh->boardflags & BFL_FEM_BT))
4336 wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313_epa);
4337 else if (pi->sh->boardflags & BFL_FEM_BT) {
4338 if (pi->sh->boardrev < 0x1250)
4339 wlc_lcnphy_write_table(
4341 &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa);
4343 wlc_lcnphy_write_table(
4345 &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250);
4347 wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313);
4349 wlc_lcnphy_load_rfpower(pi);
4351 wlc_lcnphy_clear_papd_comptable(pi);
4354 static void wlc_lcnphy_rev0_baseband_init(struct brcms_phy *pi)
4357 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4359 write_radio_reg(pi, RADIO_2064_REG11C, 0x0);
4361 write_phy_reg(pi, 0x43b, 0x0);
4362 write_phy_reg(pi, 0x43c, 0x0);
4363 write_phy_reg(pi, 0x44c, 0x0);
4364 write_phy_reg(pi, 0x4e6, 0x0);
4365 write_phy_reg(pi, 0x4f9, 0x0);
4366 write_phy_reg(pi, 0x4b0, 0x0);
4367 write_phy_reg(pi, 0x938, 0x0);
4368 write_phy_reg(pi, 0x4b0, 0x0);
4369 write_phy_reg(pi, 0x44e, 0);
4371 or_phy_reg(pi, 0x567, 0x03);
4373 or_phy_reg(pi, 0x44a, 0x44);
4374 write_phy_reg(pi, 0x44a, 0x80);
4376 if (!(pi->sh->boardflags & BFL_FEM))
4377 wlc_lcnphy_set_tx_pwr_by_index(pi, 52);
4381 afectrl1 = (u16) ((pi_lcn->lcnphy_rssi_vf) |
4382 (pi_lcn->lcnphy_rssi_vc << 4) |
4383 (pi_lcn->lcnphy_rssi_gs << 10));
4384 write_phy_reg(pi, 0x43e, afectrl1);
4387 mod_phy_reg(pi, 0x634, (0xff << 0), 0xC << 0);
4388 if (pi->sh->boardflags & BFL_FEM) {
4389 mod_phy_reg(pi, 0x634, (0xff << 0), 0xA << 0);
4391 write_phy_reg(pi, 0x910, 0x1);
4394 mod_phy_reg(pi, 0x448, (0x3 << 8), 1 << 8);
4395 mod_phy_reg(pi, 0x608, (0xff << 0), 0x17 << 0);
4396 mod_phy_reg(pi, 0x604, (0x7ff << 0), 0x3EA << 0);
4400 static void wlc_lcnphy_rev2_baseband_init(struct brcms_phy *pi)
4402 if (CHSPEC_IS5G(pi->radio_chanspec)) {
4403 mod_phy_reg(pi, 0x416, (0xff << 0), 80 << 0);
4404 mod_phy_reg(pi, 0x416, (0xff << 8), 80 << 8);
4408 static void wlc_lcnphy_agc_temp_init(struct brcms_phy *pi)
4411 struct phytbl_info tab;
4413 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4415 temp = (s16) read_phy_reg(pi, 0x4df);
4416 pi_lcn->lcnphy_ofdmgainidxtableoffset = (temp & (0xff << 0)) >> 0;
4418 if (pi_lcn->lcnphy_ofdmgainidxtableoffset > 127)
4419 pi_lcn->lcnphy_ofdmgainidxtableoffset -= 256;
4421 pi_lcn->lcnphy_dsssgainidxtableoffset = (temp & (0xff << 8)) >> 8;
4423 if (pi_lcn->lcnphy_dsssgainidxtableoffset > 127)
4424 pi_lcn->lcnphy_dsssgainidxtableoffset -= 256;
4426 tab.tbl_ptr = tableBuffer;
4429 tab.tbl_offset = 59;
4431 wlc_lcnphy_read_table(pi, &tab);
4433 if (tableBuffer[0] > 63)
4434 tableBuffer[0] -= 128;
4435 pi_lcn->lcnphy_tr_R_gain_val = tableBuffer[0];
4437 if (tableBuffer[1] > 63)
4438 tableBuffer[1] -= 128;
4439 pi_lcn->lcnphy_tr_T_gain_val = tableBuffer[1];
4441 temp = (s16) (read_phy_reg(pi, 0x434) & (0xff << 0));
4444 pi_lcn->lcnphy_input_pwr_offset_db = (s8) temp;
4446 pi_lcn->lcnphy_Med_Low_Gain_db =
4447 (read_phy_reg(pi, 0x424) & (0xff << 8)) >> 8;
4448 pi_lcn->lcnphy_Very_Low_Gain_db =
4449 (read_phy_reg(pi, 0x425) & (0xff << 0)) >> 0;
4451 tab.tbl_ptr = tableBuffer;
4453 tab.tbl_id = LCNPHY_TBL_ID_GAIN_IDX;
4454 tab.tbl_offset = 28;
4456 wlc_lcnphy_read_table(pi, &tab);
4458 pi_lcn->lcnphy_gain_idx_14_lowword = tableBuffer[0];
4459 pi_lcn->lcnphy_gain_idx_14_hiword = tableBuffer[1];
4463 static void wlc_lcnphy_bu_tweaks(struct brcms_phy *pi)
4465 or_phy_reg(pi, 0x805, 0x1);
4467 mod_phy_reg(pi, 0x42f, (0x7 << 0), (0x3) << 0);
4469 mod_phy_reg(pi, 0x030, (0x7 << 0), (0x3) << 0);
4471 write_phy_reg(pi, 0x414, 0x1e10);
4472 write_phy_reg(pi, 0x415, 0x0640);
4474 mod_phy_reg(pi, 0x4df, (0xff << 8), -9 << 8);
4476 or_phy_reg(pi, 0x44a, 0x44);
4477 write_phy_reg(pi, 0x44a, 0x80);
4478 mod_phy_reg(pi, 0x434, (0xff << 0), (0xFD) << 0);
4480 mod_phy_reg(pi, 0x420, (0xff << 0), (16) << 0);
4482 if (!(pi->sh->boardrev < 0x1204))
4483 mod_radio_reg(pi, RADIO_2064_REG09B, 0xF0, 0xF0);
4485 write_phy_reg(pi, 0x7d6, 0x0902);
4486 mod_phy_reg(pi, 0x429, (0xf << 0), (0x9) << 0);
4488 mod_phy_reg(pi, 0x429, (0x3f << 4), (0xe) << 4);
4490 if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
4491 mod_phy_reg(pi, 0x423, (0xff << 0), (0x46) << 0);
4493 mod_phy_reg(pi, 0x411, (0xff << 0), (1) << 0);
4495 mod_phy_reg(pi, 0x434, (0xff << 0), (0xFF) << 0);
4497 mod_phy_reg(pi, 0x656, (0xf << 0), (2) << 0);
4499 mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
4501 mod_radio_reg(pi, RADIO_2064_REG0F7, 0x4, 0x4);
4502 mod_radio_reg(pi, RADIO_2064_REG0F1, 0x3, 0);
4503 mod_radio_reg(pi, RADIO_2064_REG0F2, 0xF8, 0x90);
4504 mod_radio_reg(pi, RADIO_2064_REG0F3, 0x3, 0x2);
4505 mod_radio_reg(pi, RADIO_2064_REG0F3, 0xf0, 0xa0);
4507 mod_radio_reg(pi, RADIO_2064_REG11F, 0x2, 0x2);
4509 wlc_lcnphy_clear_tx_power_offsets(pi);
4510 mod_phy_reg(pi, 0x4d0, (0x1ff << 6), (10) << 6);
4515 static void wlc_lcnphy_baseband_init(struct brcms_phy *pi)
4518 wlc_lcnphy_tbl_init(pi);
4519 wlc_lcnphy_rev0_baseband_init(pi);
4520 if (LCNREV_IS(pi->pubpi.phy_rev, 2))
4521 wlc_lcnphy_rev2_baseband_init(pi);
4522 wlc_lcnphy_bu_tweaks(pi);
4525 static void wlc_radio_2064_init(struct brcms_phy *pi)
4528 struct lcnphy_radio_regs *lcnphyregs = NULL;
4530 lcnphyregs = lcnphy_radio_regs_2064;
4532 for (i = 0; lcnphyregs[i].address != 0xffff; i++)
4533 if (CHSPEC_IS5G(pi->radio_chanspec) && lcnphyregs[i].do_init_a)
4535 ((lcnphyregs[i].address & 0x3fff) |
4536 RADIO_DEFAULT_CORE),
4537 (u16) lcnphyregs[i].init_a);
4538 else if (lcnphyregs[i].do_init_g)
4540 ((lcnphyregs[i].address & 0x3fff) |
4541 RADIO_DEFAULT_CORE),
4542 (u16) lcnphyregs[i].init_g);
4544 write_radio_reg(pi, RADIO_2064_REG032, 0x62);
4545 write_radio_reg(pi, RADIO_2064_REG033, 0x19);
4547 write_radio_reg(pi, RADIO_2064_REG090, 0x10);
4549 write_radio_reg(pi, RADIO_2064_REG010, 0x00);
4551 if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
4553 write_radio_reg(pi, RADIO_2064_REG060, 0x7f);
4554 write_radio_reg(pi, RADIO_2064_REG061, 0x72);
4555 write_radio_reg(pi, RADIO_2064_REG062, 0x7f);
4558 write_radio_reg(pi, RADIO_2064_REG01D, 0x02);
4559 write_radio_reg(pi, RADIO_2064_REG01E, 0x06);
4561 mod_phy_reg(pi, 0x4ea, (0x7 << 0), 0 << 0);
4563 mod_phy_reg(pi, 0x4ea, (0x7 << 3), 1 << 3);
4565 mod_phy_reg(pi, 0x4ea, (0x7 << 6), 2 << 6);
4567 mod_phy_reg(pi, 0x4ea, (0x7 << 9), 3 << 9);
4569 mod_phy_reg(pi, 0x4ea, (0x7 << 12), 4 << 12);
4571 write_phy_reg(pi, 0x4ea, 0x4688);
4573 mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
4575 mod_phy_reg(pi, 0x4eb, (0x7 << 6), 0 << 6);
4577 mod_phy_reg(pi, 0x46a, (0xffff << 0), 25 << 0);
4579 wlc_lcnphy_set_tx_locc(pi, 0);
4581 wlc_lcnphy_rcal(pi);
4583 wlc_lcnphy_rc_cal(pi);
4586 static void wlc_lcnphy_radio_init(struct brcms_phy *pi)
4588 wlc_radio_2064_init(pi);
4591 static void wlc_lcnphy_rcal(struct brcms_phy *pi)
4595 and_radio_reg(pi, RADIO_2064_REG05B, 0xfD);
4597 or_radio_reg(pi, RADIO_2064_REG004, 0x40);
4598 or_radio_reg(pi, RADIO_2064_REG120, 0x10);
4600 or_radio_reg(pi, RADIO_2064_REG078, 0x80);
4601 or_radio_reg(pi, RADIO_2064_REG129, 0x02);
4603 or_radio_reg(pi, RADIO_2064_REG057, 0x01);
4605 or_radio_reg(pi, RADIO_2064_REG05B, 0x02);
4607 SPINWAIT(!wlc_radio_2064_rcal_done(pi), 10 * 1000 * 1000);
4609 if (wlc_radio_2064_rcal_done(pi)) {
4610 rcal_value = (u8) read_radio_reg(pi, RADIO_2064_REG05C);
4611 rcal_value = rcal_value & 0x1f;
4614 and_radio_reg(pi, RADIO_2064_REG05B, 0xfD);
4616 and_radio_reg(pi, RADIO_2064_REG057, 0xFE);
4619 static void wlc_lcnphy_rc_cal(struct brcms_phy *pi)
4624 dflt_rc_cal_val = 7;
4625 if (LCNREV_IS(pi->pubpi.phy_rev, 1))
4626 dflt_rc_cal_val = 11;
4628 (dflt_rc_cal_val << 10) | (dflt_rc_cal_val << 5) |
4630 write_phy_reg(pi, 0x933, flt_val);
4631 write_phy_reg(pi, 0x934, flt_val);
4632 write_phy_reg(pi, 0x935, flt_val);
4633 write_phy_reg(pi, 0x936, flt_val);
4634 write_phy_reg(pi, 0x937, (flt_val & 0x1FF));
4639 static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi)
4643 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4645 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4647 u32 offset_ofdm, offset_mcs;
4649 pi_lcn->lcnphy_tr_isolation_mid =
4650 (u8) PHY_GETINTVAR(pi, "triso2g");
4652 pi_lcn->lcnphy_rx_power_offset =
4653 (u8) PHY_GETINTVAR(pi, "rxpo2g");
4655 pi->txpa_2g[0] = (s16) PHY_GETINTVAR(pi, "pa0b0");
4656 pi->txpa_2g[1] = (s16) PHY_GETINTVAR(pi, "pa0b1");
4657 pi->txpa_2g[2] = (s16) PHY_GETINTVAR(pi, "pa0b2");
4659 pi_lcn->lcnphy_rssi_vf = (u8) PHY_GETINTVAR(pi, "rssismf2g");
4660 pi_lcn->lcnphy_rssi_vc = (u8) PHY_GETINTVAR(pi, "rssismc2g");
4661 pi_lcn->lcnphy_rssi_gs = (u8) PHY_GETINTVAR(pi, "rssisav2g");
4664 pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf;
4665 pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc;
4666 pi_lcn->lcnphy_rssi_gs_lowtemp = pi_lcn->lcnphy_rssi_gs;
4668 pi_lcn->lcnphy_rssi_vf_hightemp =
4669 pi_lcn->lcnphy_rssi_vf;
4670 pi_lcn->lcnphy_rssi_vc_hightemp =
4671 pi_lcn->lcnphy_rssi_vc;
4672 pi_lcn->lcnphy_rssi_gs_hightemp =
4673 pi_lcn->lcnphy_rssi_gs;
4676 txpwr = (s8) PHY_GETINTVAR(pi, "maxp2ga0");
4677 pi->tx_srom_max_2g = txpwr;
4679 for (i = 0; i < PWRTBL_NUM_COEFF; i++) {
4680 pi->txpa_2g_low_temp[i] = pi->txpa_2g[i];
4681 pi->txpa_2g_high_temp[i] = pi->txpa_2g[i];
4684 cckpo = (u16) PHY_GETINTVAR(pi, "cck2gpo");
4686 uint max_pwr_chan = txpwr;
4688 for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++) {
4689 pi->tx_srom_max_rate_2g[i] =
4690 max_pwr_chan - ((cckpo & 0xf) * 2);
4694 offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
4695 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
4696 pi->tx_srom_max_rate_2g[i] =
4698 ((offset_ofdm & 0xf) * 2);
4704 opo = (u8) PHY_GETINTVAR(pi, "opo");
4706 for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++)
4707 pi->tx_srom_max_rate_2g[i] = txpwr;
4709 offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
4711 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
4712 pi->tx_srom_max_rate_2g[i] = txpwr -
4713 ((offset_ofdm & 0xf) * 2);
4717 ((u16) PHY_GETINTVAR(pi, "mcs2gpo1") << 16) |
4718 (u16) PHY_GETINTVAR(pi, "mcs2gpo0");
4719 pi_lcn->lcnphy_mcs20_po = offset_mcs;
4720 for (i = TXP_FIRST_SISO_MCS_20;
4721 i <= TXP_LAST_SISO_MCS_20; i++) {
4722 pi->tx_srom_max_rate_2g[i] =
4723 txpwr - ((offset_mcs & 0xf) * 2);
4728 pi_lcn->lcnphy_rawtempsense =
4729 (u16) PHY_GETINTVAR(pi, "rawtempsense");
4730 pi_lcn->lcnphy_measPower =
4731 (u8) PHY_GETINTVAR(pi, "measpower");
4732 pi_lcn->lcnphy_tempsense_slope =
4733 (u8) PHY_GETINTVAR(pi, "tempsense_slope");
4734 pi_lcn->lcnphy_hw_iqcal_en =
4735 (bool) PHY_GETINTVAR(pi, "hw_iqcal_en");
4736 pi_lcn->lcnphy_iqcal_swp_dis =
4737 (bool) PHY_GETINTVAR(pi, "iqcal_swp_dis");
4738 pi_lcn->lcnphy_tempcorrx =
4739 (u8) PHY_GETINTVAR(pi, "tempcorrx");
4740 pi_lcn->lcnphy_tempsense_option =
4741 (u8) PHY_GETINTVAR(pi, "tempsense_option");
4742 pi_lcn->lcnphy_freqoffset_corr =
4743 (u8) PHY_GETINTVAR(pi, "freqoffset_corr");
4744 if ((u8) getintvar(pi->vars, "aa2g") > 1)
4745 wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi,
4746 (u8) getintvar(pi->vars,
4749 pi_lcn->lcnphy_cck_dig_filt_type = -1;
4750 if (PHY_GETVAR(pi, "cckdigfilttype")) {
4752 temp = (s16) PHY_GETINTVAR(pi, "cckdigfilttype");
4754 pi_lcn->lcnphy_cck_dig_filt_type = temp;
4760 void wlc_2064_vco_cal(struct brcms_phy *pi)
4764 mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 1 << 3);
4765 calnrst = (u8) read_radio_reg(pi, RADIO_2064_REG056) & 0xf8;
4766 write_radio_reg(pi, RADIO_2064_REG056, calnrst);
4768 write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x03);
4770 write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x07);
4772 mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 0);
4776 wlc_lcnphy_radio_2064_channel_tune_4313(struct brcms_phy *pi, u8 channel)
4779 const struct chan_info_2064_lcnphy *ci;
4780 u8 rfpll_doubler = 0;
4781 u8 pll_pwrup, pll_pwrup_ovr;
4782 s32 qFxtal, qFref, qFvco, qFcal;
4783 u8 d15, d16, f16, e44, e45;
4784 u32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div;
4785 u16 loop_bw, d30, setCount;
4787 ci = &chan_info_2064_lcnphy[0];
4790 mod_radio_reg(pi, RADIO_2064_REG09D, 0x4, 0x1 << 2);
4792 write_radio_reg(pi, RADIO_2064_REG09E, 0xf);
4793 if (!rfpll_doubler) {
4794 loop_bw = PLL_2064_LOOP_BW;
4797 loop_bw = PLL_2064_LOOP_BW_DOUBLER;
4798 d30 = PLL_2064_D30_DOUBLER;
4801 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4802 for (i = 0; i < ARRAY_SIZE(chan_info_2064_lcnphy); i++)
4803 if (chan_info_2064_lcnphy[i].chan == channel)
4806 if (i >= ARRAY_SIZE(chan_info_2064_lcnphy))
4809 ci = &chan_info_2064_lcnphy[i];
4812 write_radio_reg(pi, RADIO_2064_REG02A, ci->logen_buftune);
4814 mod_radio_reg(pi, RADIO_2064_REG030, 0x3, ci->logen_rccr_tx);
4816 mod_radio_reg(pi, RADIO_2064_REG091, 0x3, ci->txrf_mix_tune_ctrl);
4818 mod_radio_reg(pi, RADIO_2064_REG038, 0xf, ci->pa_input_tune_g);
4820 mod_radio_reg(pi, RADIO_2064_REG030, 0x3 << 2,
4821 (ci->logen_rccr_rx) << 2);
4823 mod_radio_reg(pi, RADIO_2064_REG05E, 0xf, ci->pa_rxrf_lna1_freq_tune);
4825 mod_radio_reg(pi, RADIO_2064_REG05E, (0xf) << 4,
4826 (ci->pa_rxrf_lna2_freq_tune) << 4);
4828 write_radio_reg(pi, RADIO_2064_REG06C, ci->rxrf_rxrf_spare1);
4830 pll_pwrup = (u8) read_radio_reg(pi, RADIO_2064_REG044);
4831 pll_pwrup_ovr = (u8) read_radio_reg(pi, RADIO_2064_REG12B);
4833 or_radio_reg(pi, RADIO_2064_REG044, 0x07);
4835 or_radio_reg(pi, RADIO_2064_REG12B, (0x07) << 1);
4839 fpfd = rfpll_doubler ? (pi->xtalfreq << 1) : (pi->xtalfreq);
4840 if (pi->xtalfreq > 26000000)
4842 if (pi->xtalfreq > 52000000)
4850 fvco3 = (ci->freq * 3);
4853 qFxtal = wlc_lcnphy_qdiv_roundup(pi->xtalfreq, PLL_2064_MHZ, 16);
4854 qFref = wlc_lcnphy_qdiv_roundup(fpfd, PLL_2064_MHZ, 16);
4855 qFcal = pi->xtalfreq * fcal_div / PLL_2064_MHZ;
4856 qFvco = wlc_lcnphy_qdiv_roundup(fvco3, 2, 16);
4858 write_radio_reg(pi, RADIO_2064_REG04F, 0x02);
4860 d15 = (pi->xtalfreq * fcal_div * 4 / 5) / PLL_2064_MHZ - 1;
4861 write_radio_reg(pi, RADIO_2064_REG052, (0x07 & (d15 >> 2)));
4862 write_radio_reg(pi, RADIO_2064_REG053, (d15 & 0x3) << 5);
4864 d16 = (qFcal * 8 / (d15 + 1)) - 1;
4865 write_radio_reg(pi, RADIO_2064_REG051, d16);
4867 f16 = ((d16 + 1) * (d15 + 1)) / qFcal;
4868 setCount = f16 * 3 * (ci->freq) / 32 - 1;
4869 mod_radio_reg(pi, RADIO_2064_REG053, (0x0f << 0),
4870 (u8) (setCount >> 8));
4872 or_radio_reg(pi, RADIO_2064_REG053, 0x10);
4873 write_radio_reg(pi, RADIO_2064_REG054, (u8) (setCount & 0xff));
4875 div_int = ((fvco3 * (PLL_2064_MHZ >> 4)) / fref3) << 4;
4877 div_frac = ((fvco3 * (PLL_2064_MHZ >> 4)) % fref3) << 4;
4878 while (div_frac >= fref3) {
4882 div_frac = wlc_lcnphy_qdiv_roundup(div_frac, fref3, 20);
4884 mod_radio_reg(pi, RADIO_2064_REG045, (0x1f << 0),
4885 (u8) (div_int >> 4));
4886 mod_radio_reg(pi, RADIO_2064_REG046, (0x1f << 4),
4887 (u8) (div_int << 4));
4888 mod_radio_reg(pi, RADIO_2064_REG046, (0x0f << 0),
4889 (u8) (div_frac >> 16));
4890 write_radio_reg(pi, RADIO_2064_REG047, (u8) (div_frac >> 8) & 0xff);
4891 write_radio_reg(pi, RADIO_2064_REG048, (u8) div_frac & 0xff);
4893 write_radio_reg(pi, RADIO_2064_REG040, 0xfb);
4895 write_radio_reg(pi, RADIO_2064_REG041, 0x9A);
4896 write_radio_reg(pi, RADIO_2064_REG042, 0xA3);
4897 write_radio_reg(pi, RADIO_2064_REG043, 0x0C);
4900 u8 h29, h23, c28, d29, h28_ten, e30, h30_ten, cp_current;
4901 u16 c29, c38, c30, g30, d28;
4908 d28 = (((PLL_2064_HIGH_END_KVCO - PLL_2064_LOW_END_KVCO) *
4909 (fvco3 / 2 - PLL_2064_LOW_END_VCO)) /
4910 (PLL_2064_HIGH_END_VCO - PLL_2064_LOW_END_VCO))
4911 + PLL_2064_LOW_END_KVCO;
4912 h28_ten = (d28 * 10) / c28;
4914 e30 = (d30 - 680) / 490;
4915 g30 = 680 + (e30 * 490);
4916 h30_ten = (g30 * 10) / c30;
4917 cp_current = ((c38 * h29 * h23 * 100) / h28_ten) / h30_ten;
4918 mod_radio_reg(pi, RADIO_2064_REG03C, 0x3f, cp_current);
4920 if (channel >= 1 && channel <= 5)
4921 write_radio_reg(pi, RADIO_2064_REG03C, 0x8);
4923 write_radio_reg(pi, RADIO_2064_REG03C, 0x7);
4924 write_radio_reg(pi, RADIO_2064_REG03D, 0x3);
4926 mod_radio_reg(pi, RADIO_2064_REG044, 0x0c, 0x0c);
4929 wlc_2064_vco_cal(pi);
4931 write_radio_reg(pi, RADIO_2064_REG044, pll_pwrup);
4932 write_radio_reg(pi, RADIO_2064_REG12B, pll_pwrup_ovr);
4933 if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
4934 write_radio_reg(pi, RADIO_2064_REG038, 3);
4935 write_radio_reg(pi, RADIO_2064_REG091, 7);
4939 bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi)
4941 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
4944 return (LCNPHY_TX_PWR_CTRL_HW ==
4945 wlc_lcnphy_get_tx_pwr_ctrl((pi)));
4948 void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi)
4951 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
4952 wlc_lcnphy_calib_modes(pi, LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
4953 } else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) {
4954 pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
4955 wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
4956 wlc_lcnphy_txpower_recalc_target(pi);
4957 wlc_lcnphy_set_tx_pwr_ctrl(pi, pwr_ctrl);
4961 void wlc_phy_detach_lcnphy(struct brcms_phy *pi)
4963 kfree(pi->u.pi_lcnphy);
4966 bool wlc_phy_attach_lcnphy(struct brcms_phy *pi)
4968 struct brcms_phy_lcnphy *pi_lcn;
4970 pi->u.pi_lcnphy = kzalloc(sizeof(struct brcms_phy_lcnphy), GFP_ATOMIC);
4971 if (pi->u.pi_lcnphy == NULL)
4974 pi_lcn = pi->u.pi_lcnphy;
4976 if (0 == (pi->sh->boardflags & BFL_NOPA)) {
4977 pi->hwpwrctrl = true;
4978 pi->hwpwrctrl_capable = true;
4981 pi->xtalfreq = si_pmu_alp_clock(pi->sh->sih);
4982 pi_lcn->lcnphy_papd_rxGnCtrl_init = 0;
4984 pi->pi_fptr.init = wlc_phy_init_lcnphy;
4985 pi->pi_fptr.calinit = wlc_phy_cal_init_lcnphy;
4986 pi->pi_fptr.chanset = wlc_phy_chanspec_set_lcnphy;
4987 pi->pi_fptr.txpwrrecalc = wlc_phy_txpower_recalc_target_lcnphy;
4988 pi->pi_fptr.txiqccget = wlc_lcnphy_get_tx_iqcc;
4989 pi->pi_fptr.txiqccset = wlc_lcnphy_set_tx_iqcc;
4990 pi->pi_fptr.txloccget = wlc_lcnphy_get_tx_locc;
4991 pi->pi_fptr.radioloftget = wlc_lcnphy_get_radio_loft;
4992 pi->pi_fptr.detach = wlc_phy_detach_lcnphy;
4994 if (!wlc_phy_txpwr_srom_read_lcnphy(pi))
4997 if ((pi->sh->boardflags & BFL_FEM) &&
4998 (LCNREV_IS(pi->pubpi.phy_rev, 1))) {
4999 if (pi_lcn->lcnphy_tempsense_option == 3) {
5000 pi->hwpwrctrl = true;
5001 pi->hwpwrctrl_capable = true;
5002 pi->temppwrctrl_capable = false;
5004 pi->hwpwrctrl = false;
5005 pi->hwpwrctrl_capable = false;
5006 pi->temppwrctrl_capable = true;
5013 static void wlc_lcnphy_set_rx_gain(struct brcms_phy *pi, u32 gain)
5015 u16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19;
5017 trsw = (gain & ((u32) 1 << 28)) ? 0 : 1;
5018 ext_lna = (u16) (gain >> 29) & 0x01;
5019 lna1 = (u16) (gain >> 0) & 0x0f;
5020 lna2 = (u16) (gain >> 4) & 0x0f;
5021 tia = (u16) (gain >> 8) & 0xf;
5022 biq0 = (u16) (gain >> 12) & 0xf;
5023 biq1 = (u16) (gain >> 16) & 0xf;
5025 gain0_15 = (u16) ((lna1 & 0x3) | ((lna1 & 0x3) << 2) |
5026 ((lna2 & 0x3) << 4) | ((lna2 & 0x3) << 6) |
5027 ((tia & 0xf) << 8) | ((biq0 & 0xf) << 12));
5030 mod_phy_reg(pi, 0x44d, (0x1 << 0), trsw << 0);
5031 mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
5032 mod_phy_reg(pi, 0x4b1, (0x1 << 10), ext_lna << 10);
5033 mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
5034 mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
5036 if (CHSPEC_IS2G(pi->radio_chanspec)) {
5037 mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
5038 mod_phy_reg(pi, 0x4e6, (0x3 << 3), lna1 << 3);
5040 wlc_lcnphy_rx_gain_override_enable(pi, true);
5043 static u32 wlc_lcnphy_get_receive_power(struct brcms_phy *pi, s32 *gain_index)
5045 u32 received_power = 0;
5048 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
5051 if (*gain_index >= 0)
5052 gain_code = lcnphy_23bitgaincode_table[*gain_index];
5054 if (-1 == *gain_index) {
5056 while ((*gain_index <= (s32) max_index)
5057 && (received_power < 700)) {
5058 wlc_lcnphy_set_rx_gain(pi,
5059 lcnphy_23bitgaincode_table
5062 wlc_lcnphy_measure_digital_power(
5065 lcnphy_noise_samples);
5070 wlc_lcnphy_set_rx_gain(pi, gain_code);
5072 wlc_lcnphy_measure_digital_power(pi,
5074 lcnphy_noise_samples);
5077 return received_power;
5080 s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index)
5083 s32 nominal_power_db;
5084 s32 log_val, gain_mismatch, desired_gain, input_power_offset_db,
5086 s32 received_power, temperature;
5088 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
5090 received_power = wlc_lcnphy_get_receive_power(pi, &gain_index);
5092 gain = lcnphy_gain_table[gain_index];
5094 nominal_power_db = read_phy_reg(pi, 0x425) >> 8;
5097 u32 power = (received_power * 16);
5098 u32 msb1, msb2, val1, val2, diff1, diff2;
5099 msb1 = ffs(power) - 1;
5103 diff1 = (power - val1);
5104 diff2 = (val2 - power);
5111 log_val = log_val * 3;
5113 gain_mismatch = (nominal_power_db / 2) - (log_val);
5115 desired_gain = gain + gain_mismatch;
5117 input_power_offset_db = read_phy_reg(pi, 0x434) & 0xFF;
5119 if (input_power_offset_db > 127)
5120 input_power_offset_db -= 256;
5122 input_power_db = input_power_offset_db - desired_gain;
5125 input_power_db + lcnphy_gain_index_offset_for_rssi[gain_index];
5127 freq = wlc_phy_channel2freq(CHSPEC_CHANNEL(pi->radio_chanspec));
5128 if ((freq > 2427) && (freq <= 2467))
5129 input_power_db = input_power_db - 1;
5131 temperature = pi_lcn->lcnphy_lastsensed_temperature;
5133 if ((temperature - 15) < -30)
5136 (((temperature - 10 - 25) * 286) >> 12) -
5138 else if ((temperature - 15) < 4)
5141 (((temperature - 10 - 25) * 286) >> 12) -
5144 input_power_db = input_power_db +
5145 (((temperature - 10 - 25) * 286) >> 12);
5147 wlc_lcnphy_rx_gain_override_enable(pi, 0);
5149 return input_power_db;
5153 wlc_lcnphy_load_tx_iir_filter(struct brcms_phy *pi, bool is_ofdm, s16 filt_type)
5155 s16 filt_index = -1;
5197 for (j = 0; j < LCNPHY_NUM_TX_DIG_FILTERS_CCK; j++) {
5198 if (filt_type == LCNPHY_txdigfiltcoeffs_cck[j][0]) {
5199 filt_index = (s16) j;
5204 if (filt_index != -1) {
5205 for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++)
5206 write_phy_reg(pi, addr[j],
5207 LCNPHY_txdigfiltcoeffs_cck
5208 [filt_index][j + 1]);
5211 for (j = 0; j < LCNPHY_NUM_TX_DIG_FILTERS_OFDM; j++) {
5212 if (filt_type == LCNPHY_txdigfiltcoeffs_ofdm[j][0]) {
5213 filt_index = (s16) j;
5218 if (filt_index != -1) {
5219 for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++)
5220 write_phy_reg(pi, addr_ofdm[j],
5221 LCNPHY_txdigfiltcoeffs_ofdm
5222 [filt_index][j + 1]);
5226 return (filt_index != -1) ? 0 : -1;