drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_int.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _wlc_phy_int_h_
  18 #define _wlc_phy_int_h_
  19
  20 #include <linux/kernel.h>
  21 #include <bcmdefs.h>
  22 #include <bcmutils.h>
  23
  24 #include <wlc_phy_hal.h>
  25
  26 #define PHYHAL_ERROR    0x0001
  27 #define PHYHAL_TRACE    0x0002
  28 #define PHYHAL_INFORM   0x0004
  29
  30 extern u32 phyhal_msg_level;
  31
  32 #define PHY_INFORM_ON()         (phyhal_msg_level & PHYHAL_INFORM)
  33 #define PHY_THERMAL_ON()        (phyhal_msg_level & PHYHAL_THERMAL)
  34 #define PHY_CAL_ON()            (phyhal_msg_level & PHYHAL_CAL)
  35
  36 #ifdef BOARD_TYPE
  37 #define BOARDTYPE(_type) BOARD_TYPE
  38 #else
  39 #define BOARDTYPE(_type) _type
  40 #endif
  41
  42 #define LCNXN_BASEREV           16
  43
  44 typedef struct {
  45         u8 tssipos;             /* TSSI positive slope, 1: positive, 0: negative */
  46         u8 extpagain;   /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
  47         u8 pdetrange;   /* support 32 combinations of different Pdet dynamic ranges */
  48         u8 triso;               /* TR switch isolation */
  49         u8 antswctrllut;        /* antswctrl lookup table configuration: 32 possible choices */
  50 } wlc_phy_srom_fem_t;
  51
  52 struct wlc_hw_info;
  53 typedef struct phy_info phy_info_t;
  54 typedef void (*initfn_t) (phy_info_t *);
  55 typedef void (*chansetfn_t) (phy_info_t *, chanspec_t);
  56 typedef int (*longtrnfn_t) (phy_info_t *, int);
  57 typedef void (*txiqccgetfn_t) (phy_info_t *, u16 *, u16 *);
  58 typedef void (*txiqccsetfn_t) (phy_info_t *, u16, u16);
  59 typedef u16(*txloccgetfn_t) (phy_info_t *);
  60 typedef void (*radioloftgetfn_t) (phy_info_t *, u8 *, u8 *, u8 *,
  61                                   u8 *);
  62 typedef s32(*rxsigpwrfn_t) (phy_info_t *, s32);
  63 typedef void (*detachfn_t) (phy_info_t *);
  64
  65 #undef ISNPHY
  66 #undef ISLCNPHY
  67 #define ISNPHY(pi)      PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
  68 #define ISLCNPHY(pi)    PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
  69
  70 #define ISPHY_11N_CAP(pi)       (ISNPHY(pi) || ISLCNPHY(pi))
  71
  72 #define IS20MHZ(pi)     ((pi)->bw == WL_CHANSPEC_BW_20)
  73 #define IS40MHZ(pi)     ((pi)->bw == WL_CHANSPEC_BW_40)
  74
  75 #define PHY_GET_RFATTN(rfgain)  ((rfgain) & 0x0f)
  76 #define PHY_GET_PADMIX(rfgain)  (((rfgain) & 0x10) >> 4)
  77 #define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
  78 #define PHY_SAT(x, n)           ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
  79                                 ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
  80 #define PHY_SHIFT_ROUND(x, n)   ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
  81 #define PHY_HW_ROUND(x, s)              ((x >> s) + ((x >> (s-1)) & (s != 0)))
  82
  83 #define CH_5G_GROUP     3
  84 #define A_LOW_CHANS     0
  85 #define A_MID_CHANS     1
  86 #define A_HIGH_CHANS    2
  87 #define CH_2G_GROUP     1
  88 #define G_ALL_CHANS     0
  89
  90 #define FIRST_REF5_CHANNUM      149
  91 #define LAST_REF5_CHANNUM       165
  92 #define FIRST_5G_CHAN           14
  93 #define LAST_5G_CHAN            50
  94 #define FIRST_MID_5G_CHAN       14
  95 #define LAST_MID_5G_CHAN        35
  96 #define FIRST_HIGH_5G_CHAN      36
  97 #define LAST_HIGH_5G_CHAN       41
  98 #define FIRST_LOW_5G_CHAN       42
  99 #define LAST_LOW_5G_CHAN        50
 100
 101 #define BASE_LOW_5G_CHAN        4900
 102 #define BASE_MID_5G_CHAN        5100
 103 #define BASE_HIGH_5G_CHAN       5500
 104
 105 #define CHAN5G_FREQ(chan)  (5000 + chan*5)
 106 #define CHAN2G_FREQ(chan)  (2407 + chan*5)
 107
 108 #define TXP_FIRST_CCK           0
 109 #define TXP_LAST_CCK            3
 110 #define TXP_FIRST_OFDM          4
 111 #define TXP_LAST_OFDM           11
 112 #define TXP_FIRST_OFDM_20_CDD   12
 113 #define TXP_LAST_OFDM_20_CDD    19
 114 #define TXP_FIRST_MCS_20_SISO   20
 115 #define TXP_LAST_MCS_20_SISO    27
 116 #define TXP_FIRST_MCS_20_CDD    28
 117 #define TXP_LAST_MCS_20_CDD     35
 118 #define TXP_FIRST_MCS_20_STBC   36
 119 #define TXP_LAST_MCS_20_STBC    43
 120 #define TXP_FIRST_MCS_20_SDM    44
 121 #define TXP_LAST_MCS_20_SDM     51
 122 #define TXP_FIRST_OFDM_40_SISO  52
 123 #define TXP_LAST_OFDM_40_SISO   59
 124 #define TXP_FIRST_OFDM_40_CDD   60
 125 #define TXP_LAST_OFDM_40_CDD    67
 126 #define TXP_FIRST_MCS_40_SISO   68
 127 #define TXP_LAST_MCS_40_SISO    75
 128 #define TXP_FIRST_MCS_40_CDD    76
 129 #define TXP_LAST_MCS_40_CDD     83
 130 #define TXP_FIRST_MCS_40_STBC   84
 131 #define TXP_LAST_MCS_40_STBC    91
 132 #define TXP_FIRST_MCS_40_SDM    92
 133 #define TXP_LAST_MCS_40_SDM     99
 134 #define TXP_MCS_32              100
 135 #define TXP_NUM_RATES           101
 136 #define ADJ_PWR_TBL_LEN         84
 137
 138 #define TXP_FIRST_SISO_MCS_20   20
 139 #define TXP_LAST_SISO_MCS_20    27
 140
 141 #define PHY_CORE_NUM_1  1
 142 #define PHY_CORE_NUM_2  2
 143 #define PHY_CORE_NUM_3  3
 144 #define PHY_CORE_NUM_4  4
 145 #define PHY_CORE_MAX    PHY_CORE_NUM_4
 146 #define PHY_CORE_0      0
 147 #define PHY_CORE_1      1
 148 #define PHY_CORE_2      2
 149 #define PHY_CORE_3      3
 150
 151 #define MA_WINDOW_SZ            8
 152
 153 #define PHY_NOISE_SAMPLE_MON            1
 154 #define PHY_NOISE_SAMPLE_EXTERNAL       2
 155 #define PHY_NOISE_WINDOW_SZ     16
 156 #define PHY_NOISE_GLITCH_INIT_MA 10
 157 #define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
 158 #define PHY_NOISE_STATE_MON             0x1
 159 #define PHY_NOISE_STATE_EXTERNAL        0x2
 160 #define PHY_NOISE_SAMPLE_LOG_NUM_NPHY   10
 161 #define PHY_NOISE_SAMPLE_LOG_NUM_UCODE  9
 162
 163 #define PHY_NOISE_OFFSETFACT_4322  (-103)
 164 #define PHY_NOISE_MA_WINDOW_SZ  2
 165
 166 #define PHY_RSSI_TABLE_SIZE     64
 167 #define RSSI_ANT_MERGE_MAX      0
 168 #define RSSI_ANT_MERGE_MIN      1
 169 #define RSSI_ANT_MERGE_AVG      2
 170
 171 #define PHY_TSSI_TABLE_SIZE     64
 172 #define APHY_TSSI_TABLE_SIZE    256
 173 #define TX_GAIN_TABLE_LENGTH    64
 174 #define DEFAULT_11A_TXP_IDX     24
 175 #define NUM_TSSI_FRAMES        4
 176 #define NULL_TSSI               0x7f
 177 #define NULL_TSSI_W             0x7f7f
 178
 179 #define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
 180
 181 #define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
 182
 183 #define PHY_TXPWR_MIN           10
 184 #define PHY_TXPWR_MIN_NPHY      8
 185 #define RADIOPWR_OVERRIDE_DEF   (-1)
 186
 187 #define PWRTBL_NUM_COEFF        3
 188
 189 #define SPURAVOID_DISABLE       0
 190 #define SPURAVOID_AUTO          1
 191 #define SPURAVOID_FORCEON       2
 192 #define SPURAVOID_FORCEON2      3
 193
 194 #define PHY_SW_TIMER_FAST               15
 195 #define PHY_SW_TIMER_SLOW               60
 196 #define PHY_SW_TIMER_GLACIAL    120
 197
 198 #define PHY_PERICAL_AUTO        0
 199 #define PHY_PERICAL_FULL        1
 200 #define PHY_PERICAL_PARTIAL     2
 201
 202 #define PHY_PERICAL_NODELAY     0
 203 #define PHY_PERICAL_INIT_DELAY  5
 204 #define PHY_PERICAL_ASSOC_DELAY 5
 205 #define PHY_PERICAL_WDOG_DELAY  5
 206
 207 #define MPHASE_TXCAL_NUMCMDS    2
 208 #define PHY_PERICAL_MPHASE_PENDING(pi)  (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
 209
 210 enum {
 211         MPHASE_CAL_STATE_IDLE = 0,
 212         MPHASE_CAL_STATE_INIT = 1,
 213         MPHASE_CAL_STATE_TXPHASE0,
 214         MPHASE_CAL_STATE_TXPHASE1,
 215         MPHASE_CAL_STATE_TXPHASE2,
 216         MPHASE_CAL_STATE_TXPHASE3,
 217         MPHASE_CAL_STATE_TXPHASE4,
 218         MPHASE_CAL_STATE_TXPHASE5,
 219         MPHASE_CAL_STATE_PAPDCAL,
 220         MPHASE_CAL_STATE_RXCAL,
 221         MPHASE_CAL_STATE_RSSICAL,
 222         MPHASE_CAL_STATE_IDLETSSI
 223 };
 224
 225 typedef enum {
 226         CAL_FULL,
 227         CAL_RECAL,
 228         CAL_CURRECAL,
 229         CAL_DIGCAL,
 230         CAL_GCTRL,
 231         CAL_SOFT,
 232         CAL_DIGLO
 233 } phy_cal_mode_t;
 234
 235 #define RDR_NTIERS  1
 236 #define RDR_TIER_SIZE 64
 237 #define RDR_LIST_SIZE (512/3)
 238 #define RDR_EPOCH_SIZE 40
 239 #define RDR_NANTENNAS 2
 240 #define RDR_NTIER_SIZE  RDR_LIST_SIZE
 241 #define RDR_LP_BUFFER_SIZE 64
 242 #define LP_LEN_HIS_SIZE 10
 243
 244 #define STATIC_NUM_RF 32
 245 #define STATIC_NUM_BB 9
 246
 247 #define BB_MULT_MASK            0x0000ffff
 248 #define BB_MULT_VALID_MASK      0x80000000
 249
 250 #define CORDIC_AG       39797
 251 #define CORDIC_NI       18
 252 #define FIXED(X)        ((s32)((X) << 16))
 253 #define FLOAT(X)        (((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
 254
 255 #define PHY_CHAIN_TX_DISABLE_TEMP       115
 256 #define PHY_HYSTERESIS_DELTATEMP        5
 257
 258 #define PHY_BITSCNT(x)  bcm_bitcount((u8 *)&(x), sizeof(u8))
 259
 260 #define MOD_PHY_REG(pi, phy_type, reg_name, field, value) \
 261         mod_phy_reg(pi, phy_type##_##reg_name, phy_type##_##reg_name##_##field##_MASK, \
 262         (value) << phy_type##_##reg_name##_##field##_##SHIFT);
 263 #define READ_PHY_REG(pi, phy_type, reg_name, field) \
 264         ((read_phy_reg(pi, phy_type##_##reg_name) & phy_type##_##reg_name##_##field##_##MASK)\
 265         >> phy_type##_##reg_name##_##field##_##SHIFT)
 266
 267 #define VALID_PHYTYPE(phytype)  (((uint)phytype == PHY_TYPE_N) || \
 268                                 ((uint)phytype == PHY_TYPE_LCN))
 269
 270 #define VALID_N_RADIO(radioid)  ((radioid == BCM2055_ID) || (radioid == BCM2056_ID) || \
 271                                 (radioid == BCM2057_ID))
 272 #define VALID_LCN_RADIO(radioid)        (radioid == BCM2064_ID)
 273
 274 #define VALID_RADIO(pi, radioid)        (\
 275         (ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
 276         (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
 277
 278 #define SCAN_INPROG_PHY(pi)     (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
 279 #define RM_INPROG_PHY(pi)       (mboolisset(pi->measure_hold, PHY_HOLD_FOR_RM))
 280 #define PLT_INPROG_PHY(pi)      (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
 281 #define ASSOC_INPROG_PHY(pi)    (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
 282 #define SCAN_RM_IN_PROGRESS(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
 283 #define PHY_MUTED(pi)           (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
 284 #define PUB_NOT_ASSOC(pi)       (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
 285
 286 #if defined(EXT_CBALL)
 287 #define NORADIO_ENAB(pub) ((pub).radioid == NORADIO_ID)
 288 #else
 289 #define NORADIO_ENAB(pub) 0
 290 #endif
 291
 292 #define PHY_LTRN_LIST_LEN       64
 293 extern u16 ltrn_list[PHY_LTRN_LIST_LEN];
 294
 295 typedef struct _phy_table_info {
 296         uint table;
 297         int q;
 298         uint max;
 299 } phy_table_info_t;
 300
 301 typedef struct phytbl_info {
 302         const void *tbl_ptr;
 303         u32 tbl_len;
 304         u32 tbl_id;
 305         u32 tbl_offset;
 306         u32 tbl_width;
 307 } phytbl_info_t;
 308
 309 typedef struct {
 310         u8 curr_home_channel;
 311         u16 crsminpwrthld_40_stored;
 312         u16 crsminpwrthld_20L_stored;
 313         u16 crsminpwrthld_20U_stored;
 314         u16 init_gain_code_core1_stored;
 315         u16 init_gain_code_core2_stored;
 316         u16 init_gain_codeb_core1_stored;
 317         u16 init_gain_codeb_core2_stored;
 318         u16 init_gain_table_stored[4];
 319
 320         u16 clip1_hi_gain_code_core1_stored;
 321         u16 clip1_hi_gain_code_core2_stored;
 322         u16 clip1_hi_gain_codeb_core1_stored;
 323         u16 clip1_hi_gain_codeb_core2_stored;
 324         u16 nb_clip_thresh_core1_stored;
 325         u16 nb_clip_thresh_core2_stored;
 326         u16 init_ofdmlna2gainchange_stored[4];
 327         u16 init_ccklna2gainchange_stored[4];
 328         u16 clip1_lo_gain_code_core1_stored;
 329         u16 clip1_lo_gain_code_core2_stored;
 330         u16 clip1_lo_gain_codeb_core1_stored;
 331         u16 clip1_lo_gain_codeb_core2_stored;
 332         u16 w1_clip_thresh_core1_stored;
 333         u16 w1_clip_thresh_core2_stored;
 334         u16 radio_2056_core1_rssi_gain_stored;
 335         u16 radio_2056_core2_rssi_gain_stored;
 336         u16 energy_drop_timeout_len_stored;
 337
 338         u16 ed_crs40_assertthld0_stored;
 339         u16 ed_crs40_assertthld1_stored;
 340         u16 ed_crs40_deassertthld0_stored;
 341         u16 ed_crs40_deassertthld1_stored;
 342         u16 ed_crs20L_assertthld0_stored;
 343         u16 ed_crs20L_assertthld1_stored;
 344         u16 ed_crs20L_deassertthld0_stored;
 345         u16 ed_crs20L_deassertthld1_stored;
 346         u16 ed_crs20U_assertthld0_stored;
 347         u16 ed_crs20U_assertthld1_stored;
 348         u16 ed_crs20U_deassertthld0_stored;
 349         u16 ed_crs20U_deassertthld1_stored;
 350
 351         u16 badplcp_ma;
 352         u16 badplcp_ma_previous;
 353         u16 badplcp_ma_total;
 354         u16 badplcp_ma_list[MA_WINDOW_SZ];
 355         int badplcp_ma_index;
 356         s16 pre_badplcp_cnt;
 357         s16 bphy_pre_badplcp_cnt;
 358
 359         u16 init_gain_core1;
 360         u16 init_gain_core2;
 361         u16 init_gainb_core1;
 362         u16 init_gainb_core2;
 363         u16 init_gain_rfseq[4];
 364
 365         u16 crsminpwr0;
 366         u16 crsminpwrl0;
 367         u16 crsminpwru0;
 368
 369         s16 crsminpwr_index;
 370
 371         u16 radio_2057_core1_rssi_wb1a_gc_stored;
 372         u16 radio_2057_core2_rssi_wb1a_gc_stored;
 373         u16 radio_2057_core1_rssi_wb1g_gc_stored;
 374         u16 radio_2057_core2_rssi_wb1g_gc_stored;
 375         u16 radio_2057_core1_rssi_wb2_gc_stored;
 376         u16 radio_2057_core2_rssi_wb2_gc_stored;
 377         u16 radio_2057_core1_rssi_nb_gc_stored;
 378         u16 radio_2057_core2_rssi_nb_gc_stored;
 379
 380 } interference_info_t;
 381
 382 typedef struct {
 383         u16 rc_cal_ovr;
 384         u16 phycrsth1;
 385         u16 phycrsth2;
 386         u16 init_n1p1_gain;
 387         u16 p1_p2_gain;
 388         u16 n1_n2_gain;
 389         u16 n1_p1_gain;
 390         u16 div_search_gain;
 391         u16 div_p1_p2_gain;
 392         u16 div_search_gn_change;
 393         u16 table_7_2;
 394         u16 table_7_3;
 395         u16 cckshbits_gnref;
 396         u16 clip_thresh;
 397         u16 clip2_thresh;
 398         u16 clip3_thresh;
 399         u16 clip_p2_thresh;
 400         u16 clip_pwdn_thresh;
 401         u16 clip_n1p1_thresh;
 402         u16 clip_n1_pwdn_thresh;
 403         u16 bbconfig;
 404         u16 cthr_sthr_shdin;
 405         u16 energy;
 406         u16 clip_p1_p2_thresh;
 407         u16 threshold;
 408         u16 reg15;
 409         u16 reg16;
 410         u16 reg17;
 411         u16 div_srch_idx;
 412         u16 div_srch_p1_p2;
 413         u16 div_srch_gn_back;
 414         u16 ant_dwell;
 415         u16 ant_wr_settle;
 416 } aci_save_gphy_t;
 417
 418 typedef struct _lo_complex_t {
 419         s8 i;
 420         s8 q;
 421 } lo_complex_abgphy_info_t;
 422
 423 typedef struct _nphy_iq_comp {
 424         s16 a0;
 425         s16 b0;
 426         s16 a1;
 427         s16 b1;
 428 } nphy_iq_comp_t;
 429
 430 typedef struct _nphy_txpwrindex {
 431         s8 index;
 432         s8 index_internal;
 433         s8 index_internal_save;
 434         u16 AfectrlOverride;
 435         u16 AfeCtrlDacGain;
 436         u16 rad_gain;
 437         u8 bbmult;
 438         u16 iqcomp_a;
 439         u16 iqcomp_b;
 440         u16 locomp;
 441 } phy_txpwrindex_t;
 442
 443 typedef struct {
 444
 445         u16 txcal_coeffs_2G[8];
 446         u16 txcal_radio_regs_2G[8];
 447         nphy_iq_comp_t rxcal_coeffs_2G;
 448
 449         u16 txcal_coeffs_5G[8];
 450         u16 txcal_radio_regs_5G[8];
 451         nphy_iq_comp_t rxcal_coeffs_5G;
 452 } txiqcal_cache_t;
 453
 454 typedef struct _nphy_pwrctrl {
 455         s8 max_pwr_2g;
 456         s8 idle_targ_2g;
 457         s16 pwrdet_2g_a1;
 458         s16 pwrdet_2g_b0;
 459         s16 pwrdet_2g_b1;
 460         s8 max_pwr_5gm;
 461         s8 idle_targ_5gm;
 462         s8 max_pwr_5gh;
 463         s8 max_pwr_5gl;
 464         s16 pwrdet_5gm_a1;
 465         s16 pwrdet_5gm_b0;
 466         s16 pwrdet_5gm_b1;
 467         s16 pwrdet_5gl_a1;
 468         s16 pwrdet_5gl_b0;
 469         s16 pwrdet_5gl_b1;
 470         s16 pwrdet_5gh_a1;
 471         s16 pwrdet_5gh_b0;
 472         s16 pwrdet_5gh_b1;
 473         s8 idle_targ_5gl;
 474         s8 idle_targ_5gh;
 475         s8 idle_tssi_2g;
 476         s8 idle_tssi_5g;
 477         s8 idle_tssi;
 478         s16 a1;
 479         s16 b0;
 480         s16 b1;
 481 } phy_pwrctrl_t;
 482
 483 typedef struct _nphy_txgains {
 484         u16 txlpf[2];
 485         u16 txgm[2];
 486         u16 pga[2];
 487         u16 pad[2];
 488         u16 ipa[2];
 489 } nphy_txgains_t;
 490
 491 #define PHY_NOISEVAR_BUFSIZE 10
 492
 493 typedef struct _nphy_noisevar_buf {
 494         int bufcount;
 495         int tone_id[PHY_NOISEVAR_BUFSIZE];
 496         u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
 497         u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
 498 } phy_noisevar_buf_t;
 499
 500 typedef struct {
 501         u16 rssical_radio_regs_2G[2];
 502         u16 rssical_phyregs_2G[12];
 503
 504         u16 rssical_radio_regs_5G[2];
 505         u16 rssical_phyregs_5G[12];
 506 } rssical_cache_t;
 507
 508 typedef struct {
 509
 510         u16 txiqlocal_a;
 511         u16 txiqlocal_b;
 512         u16 txiqlocal_didq;
 513         u8 txiqlocal_ei0;
 514         u8 txiqlocal_eq0;
 515         u8 txiqlocal_fi0;
 516         u8 txiqlocal_fq0;
 517
 518         u16 txiqlocal_bestcoeffs[11];
 519         u16 txiqlocal_bestcoeffs_valid;
 520
 521         u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
 522         u16 analog_gain_ref;
 523         u16 lut_begin;
 524         u16 lut_end;
 525         u16 lut_step;
 526         u16 rxcompdbm;
 527         u16 papdctrl;
 528         u16 sslpnCalibClkEnCtrl;
 529
 530         u16 rxiqcal_coeff_a0;
 531         u16 rxiqcal_coeff_b0;
 532 } lcnphy_cal_results_t;
 533
 534 struct shared_phy {
 535         struct phy_info *phy_head;
 536         uint unit;
 537         si_t *sih;
 538         void *physhim;
 539         uint corerev;
 540         u32 machwcap;
 541         bool up;
 542         bool clk;
 543         uint now;
 544         u16 vid;
 545         u16 did;
 546         uint chip;
 547         uint chiprev;
 548         uint chippkg;
 549         uint sromrev;
 550         uint boardtype;
 551         uint boardrev;
 552         uint boardvendor;
 553         u32 boardflags;
 554         u32 boardflags2;
 555         uint bustype;
 556         uint buscorerev;
 557         uint fast_timer;
 558         uint slow_timer;
 559         uint glacial_timer;
 560         u8 rx_antdiv;
 561         s8 phy_noise_window[MA_WINDOW_SZ];
 562         uint phy_noise_index;
 563         u8 hw_phytxchain;
 564         u8 hw_phyrxchain;
 565         u8 phytxchain;
 566         u8 phyrxchain;
 567         u8 rssi_mode;
 568         bool _rifs_phy;
 569 };
 570
 571 struct phy_pub {
 572         uint phy_type;
 573         uint phy_rev;
 574         u8 phy_corenum;
 575         u16 radioid;
 576         u8 radiorev;
 577         u8 radiover;
 578
 579         uint coreflags;
 580         uint ana_rev;
 581         bool abgphy_encore;
 582 };
 583
 584 struct phy_info_nphy;
 585 typedef struct phy_info_nphy phy_info_nphy_t;
 586
 587 struct phy_info_lcnphy;
 588 typedef struct phy_info_lcnphy phy_info_lcnphy_t;
 589
 590 struct phy_func_ptr {
 591         initfn_t init;
 592         initfn_t calinit;
 593         chansetfn_t chanset;
 594         initfn_t txpwrrecalc;
 595         longtrnfn_t longtrn;
 596         txiqccgetfn_t txiqccget;
 597         txiqccsetfn_t txiqccset;
 598         txloccgetfn_t txloccget;
 599         radioloftgetfn_t radioloftget;
 600         initfn_t carrsuppr;
 601         rxsigpwrfn_t rxsigpwr;
 602         detachfn_t detach;
 603 };
 604 typedef struct phy_func_ptr phy_func_ptr_t;
 605
 606 struct phy_info {
 607         wlc_phy_t pubpi_ro;
 608         shared_phy_t *sh;
 609         phy_func_ptr_t pi_fptr;
 610         void *pi_ptr;
 611
 612         union {
 613                 phy_info_lcnphy_t *pi_lcnphy;
 614         } u;
 615         bool user_txpwr_at_rfport;
 616
 617         d11regs_t *regs;
 618         struct phy_info *next;
 619         char *vars;
 620         wlc_phy_t pubpi;
 621
 622         bool do_initcal;
 623         bool phytest_on;
 624         bool ofdm_rateset_war;
 625         bool bf_preempt_4306;
 626         chanspec_t radio_chanspec;
 627         u8 antsel_type;
 628         u16 bw;
 629         u8 txpwr_percent;
 630         bool phy_init_por;
 631
 632         bool init_in_progress;
 633         bool initialized;
 634         bool sbtml_gm;
 635         uint refcnt;
 636         bool watchdog_override;
 637         u8 phynoise_state;
 638         uint phynoise_now;
 639         int phynoise_chan_watchdog;
 640         bool phynoise_polling;
 641         bool disable_percal;
 642         mbool measure_hold;
 643
 644         s16 txpa_2g[PWRTBL_NUM_COEFF];
 645         s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
 646         s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
 647         s16 txpa_5g_low[PWRTBL_NUM_COEFF];
 648         s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
 649         s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
 650
 651         u8 tx_srom_max_2g;
 652         u8 tx_srom_max_5g_low;
 653         u8 tx_srom_max_5g_mid;
 654         u8 tx_srom_max_5g_hi;
 655         u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
 656         u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
 657         u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
 658         u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
 659         u8 tx_user_target[TXP_NUM_RATES];
 660         s8 tx_power_offset[TXP_NUM_RATES];
 661         u8 tx_power_target[TXP_NUM_RATES];
 662
 663         wlc_phy_srom_fem_t srom_fem2g;
 664         wlc_phy_srom_fem_t srom_fem5g;
 665
 666         u8 tx_power_max;
 667         u8 tx_power_max_rate_ind;
 668         bool hwpwrctrl;
 669         u8 nphy_txpwrctrl;
 670         s8 nphy_txrx_chain;
 671         bool phy_5g_pwrgain;
 672
 673         u16 phy_wreg;
 674         u16 phy_wreg_limit;
 675
 676         s8 n_preamble_override;
 677         u8 antswitch;
 678         u8 aa2g, aa5g;
 679
 680         s8 idle_tssi[CH_5G_GROUP];
 681         s8 target_idle_tssi;
 682         s8 txpwr_est_Pout;
 683         u8 tx_power_min;
 684         u8 txpwr_limit[TXP_NUM_RATES];
 685         u8 txpwr_env_limit[TXP_NUM_RATES];
 686         u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
 687
 688         bool channel_14_wide_filter;
 689
 690         bool txpwroverride;
 691         bool txpwridx_override_aphy;
 692         s16 radiopwr_override;
 693         u16 hwpwr_txcur;
 694         u8 saved_txpwr_idx;
 695
 696         bool edcrs_threshold_lock;
 697
 698         u32 tr_R_gain_val;
 699         u32 tr_T_gain_val;
 700
 701         s16 ofdm_analog_filt_bw_override;
 702         s16 cck_analog_filt_bw_override;
 703         s16 ofdm_rccal_override;
 704         s16 cck_rccal_override;
 705         u16 extlna_type;
 706
 707         uint interference_mode_crs_time;
 708         u16 crsglitch_prev;
 709         bool interference_mode_crs;
 710
 711         u32 phy_tx_tone_freq;
 712         uint phy_lastcal;
 713         bool phy_forcecal;
 714         bool phy_fixed_noise;
 715         u32 xtalfreq;
 716         u8 pdiv;
 717         s8 carrier_suppr_disable;
 718
 719         bool phy_bphy_evm;
 720         bool phy_bphy_rfcs;
 721         s8 phy_scraminit;
 722         u8 phy_gpiosel;
 723
 724         s16 phy_txcore_disable_temp;
 725         s16 phy_txcore_enable_temp;
 726         s8 phy_tempsense_offset;
 727         bool phy_txcore_heatedup;
 728
 729         u16 radiopwr;
 730         u16 bb_atten;
 731         u16 txctl1;
 732
 733         u16 mintxbias;
 734         u16 mintxmag;
 735         lo_complex_abgphy_info_t gphy_locomp_iq[STATIC_NUM_RF][STATIC_NUM_BB];
 736         s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
 737         u16 gain_table[TX_GAIN_TABLE_LENGTH];
 738         bool loopback_gain;
 739         s16 max_lpback_gain_hdB;
 740         s16 trsw_rx_gain_hdB;
 741         u8 power_vec[8];
 742
 743         u16 rc_cal;
 744         int nrssi_table_delta;
 745         int nrssi_slope_scale;
 746         int nrssi_slope_offset;
 747         int min_rssi;
 748         int max_rssi;
 749
 750         s8 txpwridx;
 751         u8 min_txpower;
 752
 753         u8 a_band_high_disable;
 754
 755         u16 tx_vos;
 756         u16 global_tx_bb_dc_bias_loft;
 757
 758         int rf_max;
 759         int bb_max;
 760         int rf_list_size;
 761         int bb_list_size;
 762         u16 *rf_attn_list;
 763         u16 *bb_attn_list;
 764         u16 padmix_mask;
 765         u16 padmix_reg;
 766         u16 *txmag_list;
 767         uint txmag_len;
 768         bool txmag_enable;
 769
 770         s8 *a_tssi_to_dbm;
 771         s8 *m_tssi_to_dbm;
 772         s8 *l_tssi_to_dbm;
 773         s8 *h_tssi_to_dbm;
 774         u8 *hwtxpwr;
 775
 776         u16 freqtrack_saved_regs[2];
 777         int cur_interference_mode;
 778         bool hwpwrctrl_capable;
 779         bool temppwrctrl_capable;
 780
 781         uint phycal_nslope;
 782         uint phycal_noffset;
 783         uint phycal_mlo;
 784         uint phycal_txpower;
 785
 786         u8 phy_aa2g;
 787
 788         bool nphy_tableloaded;
 789         s8 nphy_rssisel;
 790         u32 nphy_bb_mult_save;
 791         u16 nphy_txiqlocal_bestc[11];
 792         bool nphy_txiqlocal_coeffsvalid;
 793         phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
 794         phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
 795         u16 cck2gpo;
 796         u32 ofdm2gpo;
 797         u32 ofdm5gpo;
 798         u32 ofdm5glpo;
 799         u32 ofdm5ghpo;
 800         u8 bw402gpo;
 801         u8 bw405gpo;
 802         u8 bw405glpo;
 803         u8 bw405ghpo;
 804         u8 cdd2gpo;
 805         u8 cdd5gpo;
 806         u8 cdd5glpo;
 807         u8 cdd5ghpo;
 808         u8 stbc2gpo;
 809         u8 stbc5gpo;
 810         u8 stbc5glpo;
 811         u8 stbc5ghpo;
 812         u8 bwdup2gpo;
 813         u8 bwdup5gpo;
 814         u8 bwdup5glpo;
 815         u8 bwdup5ghpo;
 816         u16 mcs2gpo[8];
 817         u16 mcs5gpo[8];
 818         u16 mcs5glpo[8];
 819         u16 mcs5ghpo[8];
 820         u32 nphy_rxcalparams;
 821
 822         u8 phy_spuravoid;
 823         bool phy_isspuravoid;
 824
 825         u8 phy_pabias;
 826         u8 nphy_papd_skip;
 827         u8 nphy_tssi_slope;
 828
 829         s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
 830         u8 nphy_noise_index;
 831
 832         u8 nphy_txpid2g[PHY_CORE_NUM_2];
 833         u8 nphy_txpid5g[PHY_CORE_NUM_2];
 834         u8 nphy_txpid5gl[PHY_CORE_NUM_2];
 835         u8 nphy_txpid5gh[PHY_CORE_NUM_2];
 836
 837         bool nphy_gain_boost;
 838         bool nphy_elna_gain_config;
 839         u16 old_bphy_test;
 840         u16 old_bphy_testcontrol;
 841
 842         bool phyhang_avoid;
 843
 844         bool rssical_nphy;
 845         u8 nphy_perical;
 846         uint nphy_perical_last;
 847         u8 cal_type_override;
 848         u8 mphase_cal_phase_id;
 849         u8 mphase_txcal_cmdidx;
 850         u8 mphase_txcal_numcmds;
 851         u16 mphase_txcal_bestcoeffs[11];
 852         chanspec_t nphy_txiqlocal_chanspec;
 853         chanspec_t nphy_iqcal_chanspec_2G;
 854         chanspec_t nphy_iqcal_chanspec_5G;
 855         chanspec_t nphy_rssical_chanspec_2G;
 856         chanspec_t nphy_rssical_chanspec_5G;
 857         struct wlapi_timer *phycal_timer;
 858         bool use_int_tx_iqlo_cal_nphy;
 859         bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
 860         s16 nphy_lastcal_temp;
 861
 862         txiqcal_cache_t calibration_cache;
 863         rssical_cache_t rssical_cache;
 864
 865         u8 nphy_txpwr_idx[2];
 866         u8 nphy_papd_cal_type;
 867         uint nphy_papd_last_cal;
 868         u16 nphy_papd_tx_gain_at_last_cal[2];
 869         u8 nphy_papd_cal_gain_index[2];
 870         s16 nphy_papd_epsilon_offset[2];
 871         bool nphy_papd_recal_enable;
 872         u32 nphy_papd_recal_counter;
 873         bool nphy_force_papd_cal;
 874         bool nphy_papdcomp;
 875         bool ipa2g_on;
 876         bool ipa5g_on;
 877
 878         u16 classifier_state;
 879         u16 clip_state[2];
 880         uint nphy_deaf_count;
 881         u8 rxiq_samps;
 882         u8 rxiq_antsel;
 883
 884         u16 rfctrlIntc1_save;
 885         u16 rfctrlIntc2_save;
 886         bool first_cal_after_assoc;
 887         u16 tx_rx_cal_radio_saveregs[22];
 888         u16 tx_rx_cal_phy_saveregs[15];
 889
 890         u8 nphy_cal_orig_pwr_idx[2];
 891         u8 nphy_txcal_pwr_idx[2];
 892         u8 nphy_rxcal_pwr_idx[2];
 893         u16 nphy_cal_orig_tx_gain[2];
 894         nphy_txgains_t nphy_cal_target_gain;
 895         u16 nphy_txcal_bbmult;
 896         u16 nphy_gmval;
 897
 898         u16 nphy_saved_bbconf;
 899
 900         bool nphy_gband_spurwar_en;
 901         bool nphy_gband_spurwar2_en;
 902         bool nphy_aband_spurwar_en;
 903         u16 nphy_rccal_value;
 904         u16 nphy_crsminpwr[3];
 905         phy_noisevar_buf_t nphy_saved_noisevars;
 906         bool nphy_anarxlpf_adjusted;
 907         bool nphy_crsminpwr_adjusted;
 908         bool nphy_noisevars_adjusted;
 909
 910         bool nphy_rxcal_active;
 911         u16 radar_percal_mask;
 912         bool dfs_lp_buffer_nphy;
 913
 914         u16 nphy_fineclockgatecontrol;
 915
 916         s8 rx2tx_biasentry;
 917
 918         u16 crsminpwr0;
 919         u16 crsminpwrl0;
 920         u16 crsminpwru0;
 921         s16 noise_crsminpwr_index;
 922         u16 init_gain_core1;
 923         u16 init_gain_core2;
 924         u16 init_gainb_core1;
 925         u16 init_gainb_core2;
 926         u8 aci_noise_curr_channel;
 927         u16 init_gain_rfseq[4];
 928
 929         bool radio_is_on;
 930
 931         bool nphy_sample_play_lpf_bw_ctl_ovr;
 932
 933         u16 tbl_data_hi;
 934         u16 tbl_data_lo;
 935         u16 tbl_addr;
 936
 937         uint tbl_save_id;
 938         uint tbl_save_offset;
 939
 940         u8 txpwrctrl;
 941         s8 txpwrindex[PHY_CORE_MAX];
 942
 943         u8 phycal_tempdelta;
 944         u32 mcs20_po;
 945         u32 mcs40_po;
 946         struct wiphy *wiphy;
 947 };
 948
 949 typedef s32 fixed;
 950
 951 typedef struct _cs32 {
 952         fixed q;
 953         fixed i;
 954 } cs32;
 955
 956 typedef struct radio_regs {
 957         u16 address;
 958         u32 init_a;
 959         u32 init_g;
 960         u8 do_init_a;
 961         u8 do_init_g;
 962 } radio_regs_t;
 963
 964 typedef struct radio_20xx_regs {
 965         u16 address;
 966         u8 init;
 967         u8 do_init;
 968 } radio_20xx_regs_t;
 969
 970 typedef struct lcnphy_radio_regs {
 971         u16 address;
 972         u8 init_a;
 973         u8 init_g;
 974         u8 do_init_a;
 975         u8 do_init_g;
 976 } lcnphy_radio_regs_t;
 977
 978 extern lcnphy_radio_regs_t lcnphy_radio_regs_2064[];
 979 extern lcnphy_radio_regs_t lcnphy_radio_regs_2066[];
 980 extern radio_regs_t regs_2055[], regs_SYN_2056[], regs_TX_2056[],
 981     regs_RX_2056[];
 982 extern radio_regs_t regs_SYN_2056_A1[], regs_TX_2056_A1[], regs_RX_2056_A1[];
 983 extern radio_regs_t regs_SYN_2056_rev5[], regs_TX_2056_rev5[],
 984     regs_RX_2056_rev5[];
 985 extern radio_regs_t regs_SYN_2056_rev6[], regs_TX_2056_rev6[],
 986     regs_RX_2056_rev6[];
 987 extern radio_regs_t regs_SYN_2056_rev7[], regs_TX_2056_rev7[],
 988     regs_RX_2056_rev7[];
 989 extern radio_regs_t regs_SYN_2056_rev8[], regs_TX_2056_rev8[],
 990     regs_RX_2056_rev8[];
 991 extern radio_20xx_regs_t regs_2057_rev4[], regs_2057_rev5[], regs_2057_rev5v1[];
 992 extern radio_20xx_regs_t regs_2057_rev7[], regs_2057_rev8[];
 993
 994 extern char *phy_getvar(phy_info_t *pi, const char *name);
 995 extern int phy_getintvar(phy_info_t *pi, const char *name);
 996 #define PHY_GETVAR(pi, name)    phy_getvar(pi, name)
 997 #define PHY_GETINTVAR(pi, name) phy_getintvar(pi, name)
 998
 999 extern u16 read_phy_reg(phy_info_t *pi, u16 addr);
1000 extern void write_phy_reg(phy_info_t *pi, u16 addr, u16 val);
1001 extern void and_phy_reg(phy_info_t *pi, u16 addr, u16 val);
1002 extern void or_phy_reg(phy_info_t *pi, u16 addr, u16 val);
1003 extern void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val);
1004
1005 extern u16 read_radio_reg(phy_info_t *pi, u16 addr);
1006 extern void or_radio_reg(phy_info_t *pi, u16 addr, u16 val);
1007 extern void and_radio_reg(phy_info_t *pi, u16 addr, u16 val);
1008 extern void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask,
1009                           u16 val);
1010 extern void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask);
1011
1012 extern void write_radio_reg(phy_info_t *pi, u16 addr, u16 val);
1013
1014 extern void wlc_phyreg_enter(wlc_phy_t *pih);
1015 extern void wlc_phyreg_exit(wlc_phy_t *pih);
1016 extern void wlc_radioreg_enter(wlc_phy_t *pih);
1017 extern void wlc_radioreg_exit(wlc_phy_t *pih);
1018
1019 extern void wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
1020                                u16 tblAddr, u16 tblDataHi,
1021                                u16 tblDatalo);
1022 extern void wlc_phy_write_table(phy_info_t *pi,
1023                                 const phytbl_info_t *ptbl_info, u16 tblAddr,
1024                                 u16 tblDataHi, u16 tblDatalo);
1025 extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
1026                                u16 tblAddr, u16 tblDataHi,
1027                                u16 tblDataLo);
1028 extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val);
1029
1030 extern void write_phy_channel_reg(phy_info_t *pi, uint val);
1031 extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
1032
1033 extern void wlc_phy_cordic(fixed theta, cs32 *val);
1034 extern u8 wlc_phy_nbits(s32 value);
1035 extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
1036
1037 extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
1038                                              radio_20xx_regs_t *radioregs);
1039 extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
1040                                     u16 core_offset);
1041
1042 extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
1043
1044 extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
1045 extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
1046                                         s32 *eps_imag);
1047
1048 extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
1049 extern void wlc_phy_cal_perical_mphase_restart(phy_info_t *pi);
1050
1051 extern bool wlc_phy_attach_nphy(phy_info_t *pi);
1052 extern bool wlc_phy_attach_lcnphy(phy_info_t *pi);
1053
1054 extern void wlc_phy_detach_lcnphy(phy_info_t *pi);
1055
1056 extern void wlc_phy_init_nphy(phy_info_t *pi);
1057 extern void wlc_phy_init_lcnphy(phy_info_t *pi);
1058
1059 extern void wlc_phy_cal_init_nphy(phy_info_t *pi);
1060 extern void wlc_phy_cal_init_lcnphy(phy_info_t *pi);
1061
1062 extern void wlc_phy_chanspec_set_nphy(phy_info_t *pi, chanspec_t chanspec);
1063 extern void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec);
1064 extern void wlc_phy_chanspec_set_fixup_lcnphy(phy_info_t *pi,
1065                                               chanspec_t chanspec);
1066 extern int wlc_phy_channel2freq(uint channel);
1067 extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
1068 extern int wlc_phy_chanspec_bandrange_get(phy_info_t *, chanspec_t);
1069
1070 extern void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode);
1071 extern s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi);
1072
1073 extern void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi);
1074 extern void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi);
1075 extern void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi);
1076
1077 extern void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index);
1078 extern void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable);
1079 extern void wlc_lcnphy_stop_tx_tone(phy_info_t *pi);
1080 extern void wlc_lcnphy_start_tx_tone(phy_info_t *pi, s32 f_kHz,
1081                                      u16 max_val, bool iqcalmode);
1082
1083 extern void wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan,
1084                                                u8 *max_pwr, u8 rate_id);
1085 extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
1086                                             u8 rate_mcs_end,
1087                                             u8 rate_ofdm_start);
1088 extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
1089                                             u8 rate_ofdm_start,
1090                                             u8 rate_ofdm_end,
1091                                             u8 rate_mcs_start);
1092
1093 extern u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode);
1094 extern s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode);
1095 extern s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode);
1096 extern s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode);
1097 extern void wlc_phy_carrier_suppress_lcnphy(phy_info_t *pi);
1098 extern void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel);
1099 extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
1100 extern void wlc_2064_vco_cal(phy_info_t *pi);
1101
1102 extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
1103
1104 #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL  0x18
1105 #define LCNPHY_TX_POWER_TABLE_SIZE      128
1106 #define LCNPHY_MAX_TX_POWER_INDEX       (LCNPHY_TX_POWER_TABLE_SIZE - 1)
1107 #define LCNPHY_TBL_ID_TXPWRCTL  0x07
1108 #define LCNPHY_TX_PWR_CTRL_OFF  0
1109 #define LCNPHY_TX_PWR_CTRL_SW           (0x1 << 15)
1110 #define LCNPHY_TX_PWR_CTRL_HW         ((0x1 << 15) | \
1111                                         (0x1 << 14) | \
1112                                         (0x1 << 13))
1113
1114 #define LCNPHY_TX_PWR_CTRL_TEMPBASED    0xE001
1115
1116 extern void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti);
1117 extern void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti);
1118 extern void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b);
1119 extern void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq);
1120 extern void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b);
1121 extern u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi);
1122 extern void wlc_lcnphy_get_radio_loft(phy_info_t *pi, u8 *ei0,
1123                                       u8 *eq0, u8 *fi0, u8 *fq0);
1124 extern void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode);
1125 extern void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode);
1126 extern bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi);
1127 extern void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi);
1128 extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
1129 extern void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr,
1130                                 s8 *cck_pwr);
1131 extern void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi);
1132
1133 extern s32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, s32 gain_index);
1134
1135 #define NPHY_MAX_HPVGA1_INDEX           10
1136 #define NPHY_DEF_HPVGA1_INDEXLIMIT      7
1137
1138 typedef struct _phy_iq_est {
1139         s32 iq_prod;
1140         u32 i_pwr;
1141         u32 q_pwr;
1142 } phy_iq_est_t;
1143
1144 extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
1145 extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
1146
1147 #define wlc_phy_write_table_nphy(pi, pti)       wlc_phy_write_table(pi, pti, 0x72, \
1148         0x74, 0x73)
1149 #define wlc_phy_read_table_nphy(pi, pti)        wlc_phy_read_table(pi, pti, 0x72, \
1150         0x74, 0x73)
1151 #define wlc_nphy_table_addr(pi, id, off)        wlc_phy_table_addr((pi), (id), (off), \
1152         0x72, 0x74, 0x73)
1153 #define wlc_nphy_table_data_write(pi, w, v)     wlc_phy_table_data_write((pi), (w), (v))
1154
1155 extern void wlc_phy_table_read_nphy(phy_info_t *pi, u32, u32 l, u32 o,
1156                                     u32 w, void *d);
1157 extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,
1158                                      u32, const void *);
1159
1160 #define PHY_IPA(pi) \
1161         ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1162          (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1163
1164 #define WLC_PHY_WAR_PR51571(pi) \
1165         if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
1166                 (void)R_REG(&(pi)->regs->maccontrol)
1167
1168 extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype);
1169 extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);
1170 extern void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en);
1171
1172 extern u8 wlc_phy_get_chan_freq_range_nphy(phy_info_t *pi, uint chan);
1173 extern void wlc_phy_switch_radio_nphy(phy_info_t *pi, bool on);
1174
1175 extern void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi);
1176
1177 extern void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd);
1178 extern s16 wlc_phy_tempsense_nphy(phy_info_t *pi);
1179
1180 extern u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val);
1181
1182 extern void wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est,
1183                                    u16 num_samps, u8 wait_time,
1184                                    u8 wait_for_crs);
1185
1186 extern void wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write,
1187                                       nphy_iq_comp_t *comp);
1188 extern void wlc_phy_aci_and_noise_reduction_nphy(phy_info_t *pi);
1189
1190 extern void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask);
1191 extern u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih);
1192
1193 extern void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type);
1194 extern void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi);
1195 extern void wlc_phy_txpwr_apply_nphy(phy_info_t *pi);
1196 extern void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi);
1197 extern u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi);
1198
1199 extern nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi);
1200 extern int wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
1201                                    bool full, bool m);
1202 extern int wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
1203                                  u8 type, bool d);
1204 extern void wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask,
1205                                      s8 txpwrindex, bool res);
1206 extern void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core, u8 rssi_type);
1207 extern int wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type,
1208                                   s32 *rssi_buf, u8 nsamps);
1209 extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
1210 extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
1211 extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower,
1212                                         bool debug);
1213 extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
1214                                 u8 mode, u8, bool);
1215 extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
1216 extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, s32 *qdBm_pwrbuf,
1217                                      u8 num_samps);
1218 extern void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi);
1219
1220 extern int wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh);
1221
1222 #define NPHY_TESTPATTERN_BPHY_EVM   0
1223 #define NPHY_TESTPATTERN_BPHY_RFCS  1
1224
1225 extern void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs);
1226
1227 void wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset,
1228                                 s8 *ofdmoffset);
1229 extern s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi,
1230                                     chanspec_t chanspec);
1231
1232 extern bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pih);
1233 #endif                          /* _wlc_phy_int_h_ */