2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _BRCM_TYPES_H_
18 #define _BRCM_TYPES_H_
21 #define SI_BUS 0 /* SOC Interconnect */
22 #define PCI_BUS 1 /* PCI target */
23 #define SDIO_BUS 3 /* SDIO target */
24 #define JTAG_BUS 4 /* JTAG */
25 #define USB_BUS 5 /* USB (does not support R/W REG) */
26 #define SPI_BUS 6 /* gSPI target */
27 #define RPC_BUS 7 /* RPC target */
29 #define WL_CHAN_FREQ_RANGE_2G 0
30 #define WL_CHAN_FREQ_RANGE_5GL 1
31 #define WL_CHAN_FREQ_RANGE_5GM 2
32 #define WL_CHAN_FREQ_RANGE_5GH 3
34 #define MAX_DMA_SEGS 4
37 #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
38 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
39 #define BFL_FEM 0x00000800 /* Board supports the Front End Module */
40 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
41 #define BFL_NOPA 0x00010000 /* Board has no PA */
42 #define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
43 #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
44 #define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
45 #define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
46 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
49 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
50 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
51 #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
52 #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
53 #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
54 #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
55 #define BFL2_LEGACY 0x00000080
56 #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
57 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
58 #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
59 #define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
60 #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
61 #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
62 #define BFL2_IPALVLSHIFT_3P3 0x00020000
63 #define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
64 #define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio "ON"
65 * Most drivers will turn it off without this flag
69 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
70 #define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
71 #define BOARD_GPIO_12 0x1000 /* gpio 12 */
72 #define BOARD_GPIO_13 0x2000 /* gpio 13 */
74 /* **** Core type/rev defaults **** */
75 #define D11CONF 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
76 * also need to update wlc.h MAXCOREREV
79 #define NCONF 0x000001ff /* Supported nphy revs:
91 #define LCNCONF 0x00000007 /* Supported lcnphy revs:
92 * 0 4313a0, 4336a0, 4330a0
97 #define SSLPNCONF 0x0000000f /* Supported sslpnphy revs:
104 /********************************************************************
105 * Phy/Core Configuration. Defines macros to to check core phy/rev *
106 * compile-time configuration. Defines default core support. *
107 * ******************************************************************
110 /* Basic macros to check a configuration bitmask */
112 #define CONF_HAS(config, val) ((config) & (1 << (val)))
113 #define CONF_MSK(config, mask) ((config) & (mask))
114 #define MSK_RANGE(low, hi) ((1 << ((hi)+1)) - (1 << (low)))
115 #define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
117 #define CONF_IS(config, val) ((config) == (1 << (val)))
118 #define CONF_GE(config, val) ((config) & (0-(1 << (val))))
119 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
120 #define CONF_LT(config, val) ((config) & ((1 << (val))-1))
121 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1))
123 /* Wrappers for some of the above, specific to config constants */
125 #define NCONF_HAS(val) CONF_HAS(NCONF, val)
126 #define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
127 #define NCONF_IS(val) CONF_IS(NCONF, val)
128 #define NCONF_GE(val) CONF_GE(NCONF, val)
129 #define NCONF_GT(val) CONF_GT(NCONF, val)
130 #define NCONF_LT(val) CONF_LT(NCONF, val)
131 #define NCONF_LE(val) CONF_LE(NCONF, val)
133 #define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val)
134 #define LCNCONF_MSK(mask) CONF_MSK(LCNCONF, mask)
135 #define LCNCONF_IS(val) CONF_IS(LCNCONF, val)
136 #define LCNCONF_GE(val) CONF_GE(LCNCONF, val)
137 #define LCNCONF_GT(val) CONF_GT(LCNCONF, val)
138 #define LCNCONF_LT(val) CONF_LT(LCNCONF, val)
139 #define LCNCONF_LE(val) CONF_LE(LCNCONF, val)
141 #define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
142 #define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
143 #define D11CONF_IS(val) CONF_IS(D11CONF, val)
144 #define D11CONF_GE(val) CONF_GE(D11CONF, val)
145 #define D11CONF_GT(val) CONF_GT(D11CONF, val)
146 #define D11CONF_LT(val) CONF_LT(D11CONF, val)
147 #define D11CONF_LE(val) CONF_LE(D11CONF, val)
149 #define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
150 #define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
152 #define NREV_IS(var, val) (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
153 #define NREV_GE(var, val) (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
154 #define NREV_GT(var, val) (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
155 #define NREV_LT(var, val) (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
156 #define NREV_LE(var, val) (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
158 #define LCNREV_IS(var, val) (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
159 #define LCNREV_GE(var, val) (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
160 #define LCNREV_GT(var, val) (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
161 #define LCNREV_LT(var, val) (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
162 #define LCNREV_LE(var, val) (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
164 #define D11REV_IS(var, val) (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
165 #define D11REV_GE(var, val) (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
166 #define D11REV_GT(var, val) (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
167 #define D11REV_LT(var, val) (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
168 #define D11REV_LE(var, val) (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
170 #define PHYTYPE_IS(var, val) (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
172 /* Finally, early-exit from switch case if anyone wants it... */
174 #define CASECHECK(config, val) if (!(CONF_HAS(config, val))) break
175 #define CASEMSK(config, mask) if (!(CONF_MSK(config, mask))) break
177 /* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
179 #define _PHYCONF_N (1 << PHY_TYPE_N)
180 #define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
181 #define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
183 #define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
185 /* Utility macro to identify 802.11n (HT) capable PHYs */
186 #define PHYTYPE_11N_CAP(phytype) \
187 (PHYTYPE_IS(phytype, PHY_TYPE_N) || \
188 PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
189 PHYTYPE_IS(phytype, PHY_TYPE_SSN))
191 /* Last but not least: shorter wlc-specific var checks */
192 #define WLCISNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
193 #define WLCISLCNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
194 #define WLCISSSLPNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
196 #define WLC_PHY_11N_CAP(band) PHYTYPE_11N_CAP((band)->phytype)
198 /**********************************************************************
199 * ------------- End of Core phy/rev configuration. ----------------- *
200 * ********************************************************************
203 /*************************************************
204 * Defaults for tunables (e.g. sizing constants)
206 * For each new tunable, add a member to the end
207 * of wlc_tunables_t in wlc_pub.h to enable
208 * runtime checks of tunable values. (Directly
209 * using the macros in code invalidates ROM code)
211 * ***********************************************
213 #define NTXD 256 /* Max # of entries in Tx FIFO based on 4kb page size */
214 #define NRXD 256 /* Max # of entries in Rx FIFO based on 4kb page size */
215 #define NRXBUFPOST 32 /* try to keep this # rbufs posted to the chip */
216 #define MAXSCB 32 /* Maximum SCBs in cache for STA */
217 #define AMPDU_NUM_MPDU 16 /* max allowed number of mpdus in an ampdu (2 streams) */
219 /* Count of packet callback structures. either of following
220 * 1. Set to the number of SCBs since a STA
221 * can queue up a rate callback for each IBSS STA it knows about, and an AP can
222 * queue up an "are you there?" Null Data callback for each associated STA
223 * 2. controlled by tunable config file
225 #define MAXPKTCB MAXSCB /* Max number of packet callbacks */
227 /* NetBSD also needs to keep track of this */
228 #define WLC_MAX_UCODE_BSS (16) /* Number of BSS handled in ucode bcn/prb */
229 #define WLC_MAX_UCODE_BSS4 (4) /* Number of BSS handled in sw bcn/prb */
230 #define WLC_MAXBSSCFG (1) /* max # BSS configs */
231 #define MAXBSS 64 /* max # available networks */
232 #define WLC_DATAHIWAT 50 /* data msg txq hiwat mark */
233 #define WLC_AMPDUDATAHIWAT 255
235 /* bounded rx loops */
236 #define RXBND 8 /* max # frames to process in wlc_recv() */
237 #define TXSBND 8 /* max # tx status to process in wlc_txstatus() */
239 #define WLBANDINITFN(_fn) _fn
241 #define BAND_5G(bt) ((bt) == WLC_BAND_5G)
242 #define BAND_2G(bt) ((bt) == WLC_BAND_2G)
244 #define BCMMSG(dev, fmt, args...) \
246 if (brcm_msg_level & LOG_TRACE_VAL) \
247 wiphy_err(dev, "%s: " fmt, __func__, ##args); \
250 #define WL_ERROR_ON() (brcm_msg_level & LOG_ERROR_VAL)
252 /* register access macros */
257 sizeof(*(r)) == sizeof(u8) ? \
258 readb((volatile u8*)(r)) : \
259 sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
260 readl((volatile u32*)(r)); \
265 __typeof(*(r)) __osl_v; \
266 __asm__ __volatile__("sync"); \
267 switch (sizeof(*(r))) { \
269 __osl_v = readb((volatile u8*)(r)); \
272 __osl_v = readw((volatile u16*)(r)); \
276 readl((volatile u32*)(r)); \
279 __asm__ __volatile__("sync"); \
282 #endif /* __mips__ */
284 #define W_REG(r, v) do { \
285 switch (sizeof(*(r))) { \
287 writeb((u8)(v), (volatile u8*)(r)); break; \
289 writew((u16)(v), (volatile u16*)(r)); break; \
291 writel((u32)(v), (volatile u32*)(r)); break; \
294 #else /* __BIG_ENDIAN */
297 __typeof(*(r)) __osl_v; \
298 switch (sizeof(*(r))) { \
301 readb((volatile u8*)((r)^3)); \
305 readw((volatile u16*)((r)^2)); \
308 __osl_v = readl((volatile u32*)(r)); \
314 #define W_REG(r, v) do { \
315 switch (sizeof(*(r))) { \
318 (volatile u8*)((r)^3)); break; \
321 (volatile u16*)((r)^2)); break; \
324 (volatile u32*)(r)); break; \
327 #endif /* __BIG_ENDIAN */
331 * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
332 * transactions. As a fix, a read after write is performed on certain places
333 * in the code. Older chips and the newer 5357 family don't require this fix.
335 #define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
337 #define W_REG_FLUSH(r, v) W_REG((r), (v))
338 #endif /* __mips__ */
340 #define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
341 #define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
343 #define SET_REG(r, mask, val) \
344 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
347 /* forward declarations */
363 /* brcm_msg_level is a bit vector with defs in defs.h */
364 extern u32 brcm_msg_level;
366 #endif /* _BRCM_TYPES_H_ */