2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
24 #include <proto/802.11.h>
39 #include "wlc_types.h"
47 #include "phy/wlc_phy_hal.h"
48 #include "wlc_channel.h"
50 #include "wl_export.h"
52 #include "wlc_antsel.h"
53 #include "pcie_core.h"
54 #include "wlc_alloc.h"
58 #define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
60 #define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
61 #define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
62 #define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
63 #define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
65 #define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
67 #ifndef BMAC_DUP_TO_REMOVE
68 #define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
70 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
72 #endif /* BMAC_DUP_TO_REMOVE */
74 #define DMAREG(wlc_hw, direction, fifonum) \
75 ((direction == DMA_TX) ? \
76 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
77 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
80 * The following table lists the buffer memory allocated to xmt fifos in HW.
81 * the size is in units of 256bytes(one block), total size is HW dependent
82 * ucode has default fifo partition, sw can overwrite if necessary
84 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
85 * the twiki is updated before making changes.
88 #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
90 static u16 xmtfifo_sz[][NFIFO] = {
91 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
92 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
93 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
94 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
95 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
98 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
99 static void wlc_coreinit(struct wlc_info *wlc);
101 /* used by wlc_wakeucode_init() */
102 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
103 const struct d11init *inits);
104 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
106 static void wlc_ucode_download(struct wlc_hw_info *wlc);
107 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
109 /* used by wlc_dpc() */
110 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
112 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
113 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
115 /* used by wlc_down() */
116 static void wlc_flushqueues(struct wlc_info *wlc);
118 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
119 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
120 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
121 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
123 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
124 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
126 /* Low Level Prototypes */
127 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
128 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
129 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
130 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
132 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
134 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
135 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
136 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
137 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
138 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
139 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
140 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
141 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
142 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
143 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
144 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
145 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
146 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
147 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
148 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
149 static void wlc_gpio_init(struct wlc_info *wlc);
150 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
152 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
154 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
155 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
156 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
157 chanspec_t chanspec);
158 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
160 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
161 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
164 /* === Low Level functions === */
166 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
168 wlc_hw->shortslot = shortslot;
170 if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
171 wlc_suspend_mac_and_wait(wlc_hw->wlc);
172 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
173 wlc_enable_mac(wlc_hw->wlc);
178 * Update the slot timing for standard 11b/g (20us slots)
179 * or shortslot 11g (9us slots)
180 * The PSM needs to be suspended for this call.
182 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
190 /* 11g short slot: 11a timing */
191 W_REG(®s->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
192 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
194 /* 11g long slot: 11b timing */
195 W_REG(®s->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
196 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
200 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
202 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
204 /* init microcode host flags */
205 wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
207 /* do band-specific ucode IHR, SHM, and SCR inits */
208 if (D11REV_IS(wlc_hw->corerev, 23)) {
209 if (WLCISNPHY(wlc_hw->band)) {
210 wlc_write_inits(wlc_hw, d11n0bsinitvals16);
212 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
213 " %d\n", __func__, wlc_hw->unit,
217 if (D11REV_IS(wlc_hw->corerev, 24)) {
218 if (WLCISLCNPHY(wlc_hw->band)) {
219 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
221 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
222 " core rev %d\n", __func__,
223 wlc_hw->unit, wlc_hw->corerev);
225 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
226 __func__, wlc_hw->unit, wlc_hw->corerev);
231 /* switch to new band but leave it inactive */
232 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
234 struct wlc_hw_info *wlc_hw = wlc->hw;
237 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
239 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
241 /* disable interrupts */
242 macintmask = wl_intrsoff(wlc->wl);
245 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
247 wlc_bmac_core_phy_clk(wlc_hw, OFF);
249 wlc_setxband(wlc_hw, bandunit);
254 /* Process received frames */
256 * Return true if more frames need to be processed. false otherwise.
257 * Param 'bound' indicates max. # frames to process before break out.
260 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
263 struct sk_buff *head = NULL;
264 struct sk_buff *tail = NULL;
266 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
267 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
269 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
270 /* gather received frames */
271 while ((p = dma_rx(wlc_hw->di[fifo]))) {
280 /* !give others some time to run! */
281 if (++n >= bound_limit)
285 /* post more rbufs */
286 dma_rxfill(wlc_hw->di[fifo]);
288 /* process each frame */
289 while ((p = head) != NULL) {
293 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
295 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
296 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
298 wlc_recv(wlc_hw->wlc, p);
301 return n >= bound_limit;
304 /* second-level interrupt processing
305 * Return true if another dpc needs to be re-scheduled. false otherwise.
306 * Param 'bounded' indicates if applicable loops should be bounded.
308 bool wlc_dpc(struct wlc_info *wlc, bool bounded)
311 struct wlc_hw_info *wlc_hw = wlc->hw;
312 d11regs_t *regs = wlc_hw->regs;
314 struct wiphy *wiphy = wlc->wiphy;
316 if (DEVICEREMOVED(wlc)) {
317 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
323 /* grab and clear the saved software intstatus bits */
324 macintstatus = wlc->macintstatus;
325 wlc->macintstatus = 0;
327 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
328 wlc_hw->unit, macintstatus);
330 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
332 /* BCN template is available */
333 /* ZZZ: Use AP_ACTIVE ? */
334 if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
335 && (macintstatus & MI_BCNTPL)) {
336 wlc_update_beacon(wlc);
339 /* PMQ entry addition */
340 if (macintstatus & MI_PMQ) {
344 if (macintstatus & MI_TFS) {
345 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
346 wlc->macintstatus |= MI_TFS;
348 wiphy_err(wiphy, "MI_TFS: fatal\n");
353 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
356 /* ATIM window end */
357 if (macintstatus & MI_ATIMWINEND) {
358 BCMMSG(wlc->wiphy, "end of ATIM window\n");
359 OR_REG(®s->maccommand, wlc->qvalid);
363 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
364 if (macintstatus & MI_DMAINT) {
365 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
366 wlc->macintstatus |= MI_DMAINT;
370 /* TX FIFO suspend/flush completion */
371 if (macintstatus & MI_TXSTOP) {
372 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
373 /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
377 /* noise sample collected */
378 if (macintstatus & MI_BG_NOISE) {
379 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
382 if (macintstatus & MI_GP0) {
383 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
384 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
386 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
387 __func__, wlc_hw->sih->chip,
388 wlc_hw->sih->chiprev);
393 /* gptimer timeout */
394 if (macintstatus & MI_TO) {
395 W_REG(®s->gptimer, 0);
398 if (macintstatus & MI_RFDISABLE) {
399 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
400 " RF Disable Input\n", wlc_hw->unit);
401 wl_rfkill_set_hw_state(wlc->wl);
404 /* send any enq'd tx packets. Just makes sure to jump start tx */
405 if (!pktq_empty(&wlc->pkt_queue->q))
408 /* it isn't done and needs to be resched if macintstatus is non-zero */
409 return wlc->macintstatus != 0;
413 return wlc->macintstatus != 0;
416 /* common low-level watchdog code */
417 void wlc_bmac_watchdog(void *arg)
419 struct wlc_info *wlc = (struct wlc_info *) arg;
420 struct wlc_hw_info *wlc_hw = wlc->hw;
422 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
427 /* increment second count */
430 /* Check for FIFO error interrupts */
431 wlc_bmac_fifoerrors(wlc_hw);
433 /* make sure RX dma has buffers */
434 dma_rxfill(wlc->hw->di[RX_FIFO]);
436 wlc_phy_watchdog(wlc_hw->band->pi);
440 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
441 bool mute, struct txpwr_limits *txpwr)
445 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
447 wlc_hw->chanspec = chanspec;
449 /* Switch bands if necessary */
450 if (NBANDS_HW(wlc_hw) > 1) {
451 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
452 if (wlc_hw->band->bandunit != bandunit) {
453 /* wlc_bmac_setband disables other bandunit,
454 * use light band switch if not up yet
457 wlc_phy_chanspec_radio_set(wlc_hw->
458 bandstate[bandunit]->
460 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
462 wlc_setxband(wlc_hw, bandunit);
467 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
471 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
473 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
475 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
476 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
478 /* Update muting of the channel */
479 wlc_bmac_mute(wlc_hw, mute, 0);
483 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
485 state->machwcap = wlc_hw->machwcap;
490 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
494 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
496 struct wlc_hw_info *wlc_hw = wlc->hw;
497 uint unit = wlc_hw->unit;
498 wlc_tunables_t *tune = wlc->pub->tunables;
499 struct wiphy *wiphy = wlc->wiphy;
501 /* name and offsets for dma_attach */
502 snprintf(name, sizeof(name), "wl%d", unit);
504 if (wlc_hw->di[0] == 0) { /* Init FIFOs */
506 int dma_attach_err = 0;
507 /* Find out the DMA addressing capability and let OS know
508 * All the channels within one DMA core have 'common-minimum' same
512 dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
514 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
515 wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
516 "resources failed\n", unit);
522 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
523 * RX: RX_FIFO (RX data packets)
525 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
526 (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
527 NULL), DMAREG(wlc_hw, DMA_RX, 0),
528 (wme ? tune->ntxd : 0), tune->nrxd,
529 tune->rxbufsz, -1, tune->nrxbufpost,
530 WL_HWRXOFF, &wl_msg_level);
531 dma_attach_err |= (NULL == wlc_hw->di[0]);
535 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
536 * (legacy) TX_DATA_FIFO (TX data packets)
539 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
540 DMAREG(wlc_hw, DMA_TX, 1), NULL,
541 tune->ntxd, 0, 0, -1, 0, 0,
543 dma_attach_err |= (NULL == wlc_hw->di[1]);
547 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
550 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
551 DMAREG(wlc_hw, DMA_TX, 2), NULL,
552 tune->ntxd, 0, 0, -1, 0, 0,
554 dma_attach_err |= (NULL == wlc_hw->di[2]);
557 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
558 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
560 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
561 DMAREG(wlc_hw, DMA_TX, 3),
562 NULL, tune->ntxd, 0, 0, -1,
563 0, 0, &wl_msg_level);
564 dma_attach_err |= (NULL == wlc_hw->di[3]);
565 /* Cleaner to leave this as if with AP defined */
567 if (dma_attach_err) {
568 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
573 /* get pointer to dma engine tx flow control variable */
574 for (i = 0; i < NFIFO; i++)
577 (uint *) dma_getvar(wlc_hw->di[i],
581 /* initial ucode host flags */
582 wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
587 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
591 for (j = 0; j < NFIFO; j++) {
593 dma_detach(wlc_hw->di[j]);
594 wlc_hw->di[j] = NULL;
600 * run backplane attach, init nvram
602 * initialize software state for each core and band
603 * put the whole chip in reset(driver down state), no clock
605 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
606 bool piomode, void *regsva, uint bustype, void *btparam)
608 struct wlc_hw_info *wlc_hw;
610 char *macaddr = NULL;
615 shared_phy_params_t sha_params;
616 struct wiphy *wiphy = wlc->wiphy;
618 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
626 wlc_hw->band = wlc_hw->bandstate[0];
627 wlc_hw->_piomode = piomode;
629 /* populate struct wlc_hw_info with default values */
630 wlc_bmac_info_init(wlc_hw);
633 * Do the hardware portion of the attach.
634 * Also initialize software state that depends on the particular hardware
637 wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
638 &wlc_hw->vars, &wlc_hw->vars_size);
639 if (wlc_hw->sih == NULL) {
640 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
648 * Get vendid/devid nvram overwrites, which could be different
649 * than those the BIOS recognizes for devices on PCMCIA_BUS,
650 * SDIO_BUS, and SROMless devices on PCI_BUS.
653 bustype = BCMBUSTYPE;
655 if (bustype != SI_BUS) {
658 var = getvar(vars, "vendid");
660 vendor = (u16) simple_strtoul(var, NULL, 0);
661 wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
664 var = getvar(vars, "devid");
666 u16 devid = (u16) simple_strtoul(var, NULL, 0);
667 if (devid != 0xffff) {
669 wiphy_err(wiphy, "Overriding device id = 0x%x"
674 /* verify again the device is supported */
675 if (!wlc_chipmatch(vendor, device)) {
676 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
677 "vendor/device (0x%x/0x%x)\n",
678 unit, vendor, device);
684 wlc_hw->vendorid = vendor;
685 wlc_hw->deviceid = device;
687 /* set bar0 window to point at D11 core */
688 wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
689 wlc_hw->corerev = ai_corerev(wlc_hw->sih);
693 wlc->regs = wlc_hw->regs;
695 /* validate chip, chiprev and corerev */
696 if (!wlc_isgoodchip(wlc_hw)) {
701 /* initialize power control registers */
702 ai_clkctl_init(wlc_hw->sih);
704 /* request fastclock and force fastclock for the rest of attach
705 * bring the d11 core out of reset.
706 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
707 * But it will be called again inside wlc_corereset, after d11 is out of reset.
709 wlc_clkctl_clk(wlc_hw, CLK_FAST);
710 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
712 if (!wlc_bmac_validate_chip_access(wlc_hw)) {
713 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
719 /* get the board rev, used just below */
720 j = getintvar(vars, "boardrev");
721 /* promote srom boardrev of 0xFF to 1 */
722 if (j == BOARDREV_PROMOTABLE)
723 j = BOARDREV_PROMOTED;
724 wlc_hw->boardrev = (u16) j;
725 if (!wlc_validboardtype(wlc_hw)) {
726 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
727 "board type (0x%x)" " or revision level (0x%x)\n",
728 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
732 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
733 wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
734 wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
736 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
737 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
739 if ((wlc_hw->sih->bustype == PCI_BUS)
740 && (ai_pci_war16165(wlc_hw->sih)))
741 wlc->war16165 = true;
743 /* check device id(srom, nvram etc.) to set bands */
744 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
745 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
746 /* Dualband boards */
751 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
754 /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
755 * init of these values
757 wlc->vendorid = wlc_hw->vendorid;
758 wlc->deviceid = wlc_hw->deviceid;
759 wlc->pub->sih = wlc_hw->sih;
760 wlc->pub->corerev = wlc_hw->corerev;
761 wlc->pub->sromrev = wlc_hw->sromrev;
762 wlc->pub->boardrev = wlc_hw->boardrev;
763 wlc->pub->boardflags = wlc_hw->boardflags;
764 wlc->pub->boardflags2 = wlc_hw->boardflags2;
765 wlc->pub->_nbands = wlc_hw->_nbands;
767 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
769 if (wlc_hw->physhim == NULL) {
770 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
776 /* pass all the parameters to wlc_phy_shared_attach in one struct */
777 sha_params.sih = wlc_hw->sih;
778 sha_params.physhim = wlc_hw->physhim;
779 sha_params.unit = unit;
780 sha_params.corerev = wlc_hw->corerev;
781 sha_params.vars = vars;
782 sha_params.vid = wlc_hw->vendorid;
783 sha_params.did = wlc_hw->deviceid;
784 sha_params.chip = wlc_hw->sih->chip;
785 sha_params.chiprev = wlc_hw->sih->chiprev;
786 sha_params.chippkg = wlc_hw->sih->chippkg;
787 sha_params.sromrev = wlc_hw->sromrev;
788 sha_params.boardtype = wlc_hw->sih->boardtype;
789 sha_params.boardrev = wlc_hw->boardrev;
790 sha_params.boardvendor = wlc_hw->sih->boardvendor;
791 sha_params.boardflags = wlc_hw->boardflags;
792 sha_params.boardflags2 = wlc_hw->boardflags2;
793 sha_params.bustype = wlc_hw->sih->bustype;
794 sha_params.buscorerev = wlc_hw->sih->buscorerev;
796 /* alloc and save pointer to shared phy state area */
797 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
798 if (!wlc_hw->phy_sh) {
803 /* initialize software state for each core and band */
804 for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
806 * band0 is always 2.4Ghz
807 * band1, if present, is 5Ghz
810 /* So if this is a single band 11a card, use band 1 */
811 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
814 wlc_setxband(wlc_hw, j);
816 wlc_hw->band->bandunit = j;
817 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
818 wlc->band->bandunit = j;
819 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
820 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
822 wlc_hw->machwcap = R_REG(®s->machwcap);
823 wlc_hw->machwcap_backup = wlc_hw->machwcap;
825 /* init tx fifo size */
827 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
829 /* Get a phy for this band */
830 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
831 (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
833 if (wlc_hw->band->pi == NULL) {
834 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
835 "attach failed\n", unit);
840 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
842 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
843 &wlc_hw->band->phyrev,
844 &wlc_hw->band->radioid,
845 &wlc_hw->band->radiorev);
846 wlc_hw->band->abgphy_encore =
847 wlc_phy_get_encore(wlc_hw->band->pi);
848 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
849 wlc_hw->band->core_flags =
850 wlc_phy_get_coreflags(wlc_hw->band->pi);
852 /* verify good phy_type & supported phy revision */
853 if (WLCISNPHY(wlc_hw->band)) {
854 if (NCONF_HAS(wlc_hw->band->phyrev))
858 } else if (WLCISLCNPHY(wlc_hw->band)) {
859 if (LCNCONF_HAS(wlc_hw->band->phyrev))
865 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
866 "phy type/rev (%d/%d)\n", unit,
867 wlc_hw->band->phytype, wlc_hw->band->phyrev);
873 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
874 * high level attach. However we can not make that change until all low level access
875 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
876 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
877 * low only init when all fns updated.
879 wlc->band->pi = wlc_hw->band->pi;
880 wlc->band->phytype = wlc_hw->band->phytype;
881 wlc->band->phyrev = wlc_hw->band->phyrev;
882 wlc->band->radioid = wlc_hw->band->radioid;
883 wlc->band->radiorev = wlc_hw->band->radiorev;
885 /* default contention windows size limits */
886 wlc_hw->band->CWmin = APHY_CWMIN;
887 wlc_hw->band->CWmax = PHY_CWMAX;
889 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
895 /* disable core to match driver "down" state */
896 wlc_coredisable(wlc_hw);
898 /* Match driver "down" state */
899 if (wlc_hw->sih->bustype == PCI_BUS)
900 ai_pci_down(wlc_hw->sih);
902 /* register sb interrupt callback functions */
903 ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
904 (void *)wlc_wlintrsrestore, NULL, wlc);
906 /* turn off pll and xtal to match driver "down" state */
907 wlc_bmac_xtal(wlc_hw, OFF);
909 /* *********************************************************************
910 * The hardware is in the DOWN state at this point. D11 core
911 * or cores are in reset with clocks off, and the board PLLs
912 * are off if possible.
914 * Beyond this point, wlc->sbclk == false and chip registers
915 * should not be touched.
916 *********************************************************************
919 /* init etheraddr state variables */
920 macaddr = wlc_get_macaddr(wlc_hw);
921 if (macaddr == NULL) {
922 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
927 bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
928 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
929 is_zero_ether_addr(wlc_hw->etheraddr)) {
930 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
937 "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
938 wlc_hw->deviceid, wlc_hw->_nbands,
939 wlc_hw->sih->boardtype, macaddr);
944 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
950 * Initialize wlc_info default values ...
951 * may get overrides later in this function
952 * BMAC_NOTES, move low out and resolve the dangling ones
954 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
956 struct wlc_info *wlc = wlc_hw->wlc;
958 /* set default sw macintmask value */
959 wlc->defmacintmask = DEF_MACINTMASK;
961 /* various 802.11g modes */
962 wlc_hw->shortslot = false;
964 wlc_hw->SFBL = RETRY_SHORT_FB;
965 wlc_hw->LFBL = RETRY_LONG_FB;
967 /* default mac retry limits */
968 wlc_hw->SRL = RETRY_SHORT_DEF;
969 wlc_hw->LRL = RETRY_LONG_DEF;
970 wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
976 int wlc_bmac_detach(struct wlc_info *wlc)
979 struct wlc_hwband *band;
980 struct wlc_hw_info *wlc_hw = wlc->hw;
986 /* detach interrupt sync mechanism since interrupt is disabled and per-port
987 * interrupt object may has been freed. this must be done before sb core switch
989 ai_deregister_intr_callback(wlc_hw->sih);
991 if (wlc_hw->sih->bustype == PCI_BUS)
992 ai_pci_sleep(wlc_hw->sih);
995 wlc_bmac_detach_dmapio(wlc_hw);
998 for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1000 /* Detach this band's phy */
1001 wlc_phy_detach(band->pi);
1004 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1007 /* Free shared phy state */
1008 wlc_phy_shared_detach(wlc_hw->phy_sh);
1010 wlc_phy_shim_detach(wlc_hw->physhim);
1013 kfree(wlc_hw->vars);
1014 wlc_hw->vars = NULL;
1017 ai_detach(wlc_hw->sih);
1025 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1027 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1029 /* reset the core */
1030 if (!DEVICEREMOVED(wlc_hw->wlc))
1031 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1033 /* purge the dma rings */
1034 wlc_flushqueues(wlc_hw->wlc);
1036 wlc_reset_bmac_done(wlc_hw->wlc);
1040 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1044 struct wlc_info *wlc = wlc_hw->wlc;
1046 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1048 /* request FAST clock if not on */
1049 fastclk = wlc_hw->forcefastclk;
1051 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1053 /* disable interrupts */
1054 macintmask = wl_intrsoff(wlc->wl);
1056 /* set up the specified band and chanspec */
1057 wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1058 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1060 /* do one-time phy inits and calibration */
1061 wlc_phy_cal_init(wlc_hw->band->pi);
1063 /* core-specific initialization */
1066 /* suspend the tx fifos and mute the phy for preism cac time */
1068 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1070 /* band-specific inits */
1071 wlc_bmac_bsinit(wlc, chanspec);
1073 /* restore macintmask */
1074 wl_intrsrestore(wlc->wl, macintmask);
1076 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1077 * and wlc_enable_mac() will clear this override bit.
1079 mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1082 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1084 wlc_hw->mac_suspend_depth = 1;
1086 /* restore the clk */
1088 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1091 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1095 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1098 * Enable pll and xtal, initialize the power control registers,
1099 * and force fastclock for the remainder of wlc_up().
1101 wlc_bmac_xtal(wlc_hw, ON);
1102 ai_clkctl_init(wlc_hw->sih);
1103 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1106 * Configure pci/pcmcia here instead of in wlc_attach()
1107 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1109 coremask = (1 << wlc_hw->wlc->core->coreidx);
1111 if (wlc_hw->sih->bustype == PCI_BUS)
1112 ai_pci_setup(wlc_hw->sih, coremask);
1115 * Need to read the hwradio status here to cover the case where the system
1116 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1118 if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1119 /* put SB PCI in down state again */
1120 if (wlc_hw->sih->bustype == PCI_BUS)
1121 ai_pci_down(wlc_hw->sih);
1122 wlc_bmac_xtal(wlc_hw, OFF);
1126 if (wlc_hw->sih->bustype == PCI_BUS)
1127 ai_pci_up(wlc_hw->sih);
1129 /* reset the d11 core */
1130 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1135 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1137 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1140 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1142 /* FULLY enable dynamic power control and d11 core interrupt */
1143 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1144 wl_intrson(wlc_hw->wlc->wl);
1148 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1153 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1158 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1160 /* disable interrupts */
1162 wlc_hw->wlc->macintmask = 0;
1164 /* now disable interrupts */
1165 wl_intrsoff(wlc_hw->wlc->wl);
1167 /* ensure we're running on the pll clock again */
1168 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1170 /* down phy at the last of this stage */
1171 callbacks += wlc_phy_down(wlc_hw->band->pi);
1176 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1181 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1187 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1189 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1192 wlc_hw->sbclk = false;
1193 wlc_hw->clk = false;
1194 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1196 /* reclaim any posted packets */
1197 wlc_flushqueues(wlc_hw->wlc);
1200 /* Reset and disable the core */
1201 if (ai_iscoreup(wlc_hw->sih)) {
1202 if (R_REG(&wlc_hw->regs->maccontrol) &
1204 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1205 callbacks += wl_reset(wlc_hw->wlc->wl);
1206 wlc_coredisable(wlc_hw);
1209 /* turn off primary xtal and pll */
1210 if (!wlc_hw->noreset) {
1211 if (wlc_hw->sih->bustype == PCI_BUS)
1212 ai_pci_down(wlc_hw->sih);
1213 wlc_bmac_xtal(wlc_hw, OFF);
1220 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1222 /* delay before first read of ucode state */
1225 /* wait until ucode is no longer asleep */
1226 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1227 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1230 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1232 memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1235 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1237 return wlc_hw->band->bandtype;
1240 /* control chip clock to save power, enable dynamic clock or force fast clock */
1241 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1243 if (PMUCTL_ENAB(wlc_hw->sih)) {
1244 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1245 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1246 * which means the FCA bit may not be set.
1247 * should wakeup mac if driver wants it to run on HT.
1251 if (mode == CLK_FAST) {
1252 OR_REG(&wlc_hw->regs->clk_ctl_st,
1259 clk_ctl_st) & CCS_HTAVAIL) == 0),
1260 PMU_MAX_TRANSITION_DLY);
1263 clk_ctl_st) & CCS_HTAVAIL));
1265 if ((wlc_hw->sih->pmurev == 0) &&
1268 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1271 clk_ctl_st) & CCS_HTAVAIL)
1273 PMU_MAX_TRANSITION_DLY);
1274 AND_REG(&wlc_hw->regs->clk_ctl_st,
1278 wlc_hw->forcefastclk = (mode == CLK_FAST);
1281 /* old chips w/o PMU, force HT through cc,
1282 * then use FCA to verify mac is running fast clock
1285 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1287 /* check fast clock is available (if core is not in reset) */
1288 if (wlc_hw->forcefastclk && wlc_hw->clk)
1289 WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1292 /* keep the ucode wake bit on if forcefastclk is on
1293 * since we do not want ucode to put us back to slow clock
1294 * when it dozes for PM mode.
1295 * Code below matches the wake override bit with current forcefastclk state
1296 * Only setting bit in wake_override instead of waking ucode immediately
1297 * since old code (wlc.c 1.4499) had this behavior. Older code set
1298 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1299 * (protected by an up check) was executed just below.
1301 if (wlc_hw->forcefastclk)
1302 mboolset(wlc_hw->wake_override,
1303 WLC_WAKE_OVERRIDE_FORCEFAST);
1305 mboolclr(wlc_hw->wake_override,
1306 WLC_WAKE_OVERRIDE_FORCEFAST);
1310 /* set initial host flags value */
1312 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1314 struct wlc_hw_info *wlc_hw = wlc->hw;
1316 memset(mhfs, 0, MHFMAX * sizeof(u16));
1318 mhfs[MHF2] |= mhf2_init;
1320 /* prohibit use of slowclock on multifunction boards */
1321 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1322 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1324 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1325 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1326 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1330 /* set or clear ucode host flag bits
1331 * it has an optimization for no-change write
1332 * it only writes through shared memory when the core has clock;
1333 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1336 * bands values are: WLC_BAND_AUTO <--- Current band only
1337 * WLC_BAND_5G <--- 5G band only
1338 * WLC_BAND_2G <--- 2G band only
1339 * WLC_BAND_ALL <--- All bands
1342 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1346 u16 addr[MHFMAX] = {
1347 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1350 struct wlc_hwband *band;
1352 if ((val & ~mask) || idx >= MHFMAX)
1353 return; /* error condition */
1356 /* Current band only or all bands,
1357 * then set the band to current band
1361 band = wlc_hw->band;
1364 band = wlc_hw->bandstate[BAND_5G_INDEX];
1367 band = wlc_hw->bandstate[BAND_2G_INDEX];
1370 band = NULL; /* error condition */
1374 save = band->mhfs[idx];
1375 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1377 /* optimization: only write through if changed, and
1378 * changed band is the current band
1380 if (wlc_hw->clk && (band->mhfs[idx] != save)
1381 && (band == wlc_hw->band))
1382 wlc_bmac_write_shm(wlc_hw, addr[idx],
1383 (u16) band->mhfs[idx]);
1386 if (bands == WLC_BAND_ALL) {
1387 wlc_hw->bandstate[0]->mhfs[idx] =
1388 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1389 wlc_hw->bandstate[1]->mhfs[idx] =
1390 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1394 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1396 struct wlc_hwband *band;
1399 return 0; /* error condition */
1402 band = wlc_hw->band;
1405 band = wlc_hw->bandstate[BAND_5G_INDEX];
1408 band = wlc_hw->bandstate[BAND_2G_INDEX];
1411 band = NULL; /* error condition */
1417 return band->mhfs[idx];
1420 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1424 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1428 for (idx = 0; idx < MHFMAX; idx++) {
1429 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1433 /* set the maccontrol register to desired reset state and
1434 * initialize the sw cache of the register
1436 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1438 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1439 wlc_hw->maccontrol = 0;
1440 wlc_hw->suspended_fifos = 0;
1441 wlc_hw->wake_override = 0;
1442 wlc_hw->mute_override = 0;
1443 wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1446 /* set or clear maccontrol bits */
1447 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1453 return; /* error condition */
1454 maccontrol = wlc_hw->maccontrol;
1455 new_maccontrol = (maccontrol & ~mask) | val;
1457 /* if the new maccontrol value is the same as the old, nothing to do */
1458 if (new_maccontrol == maccontrol)
1461 /* something changed, cache the new value */
1462 wlc_hw->maccontrol = new_maccontrol;
1464 /* write the new values with overrides applied */
1465 wlc_mctrl_write(wlc_hw);
1468 /* write the software state of maccontrol and overrides to the maccontrol register */
1469 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1471 u32 maccontrol = wlc_hw->maccontrol;
1473 /* OR in the wake bit if overridden */
1474 if (wlc_hw->wake_override)
1475 maccontrol |= MCTL_WAKE;
1477 /* set AP and INFRA bits for mute if needed */
1478 if (wlc_hw->mute_override) {
1479 maccontrol &= ~(MCTL_AP);
1480 maccontrol |= MCTL_INFRA;
1483 W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1486 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1488 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1489 mboolset(wlc_hw->wake_override, override_bit);
1493 mboolset(wlc_hw->wake_override, override_bit);
1495 wlc_mctrl_write(wlc_hw);
1496 wlc_bmac_wait_for_wake(wlc_hw);
1501 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1503 mboolclr(wlc_hw->wake_override, override_bit);
1505 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1508 wlc_mctrl_write(wlc_hw);
1513 /* When driver needs ucode to stop beaconing, it has to make sure that
1514 * MCTL_AP is clear and MCTL_INFRA is set
1515 * Mode MCTL_AP MCTL_INFRA
1517 * STA 0 1 <--- This will ensure no beacons
1520 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1522 wlc_hw->mute_override = 1;
1524 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1525 * override, then there is no change to write
1527 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1530 wlc_mctrl_write(wlc_hw);
1535 /* Clear the override on AP and INFRA bits */
1536 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1538 if (wlc_hw->mute_override == 0)
1541 wlc_hw->mute_override = 0;
1543 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1544 * override, then there is no change to write
1546 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1549 wlc_mctrl_write(wlc_hw);
1553 * Write a MAC address to the given match reg offset in the RXE match engine.
1556 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1564 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
1567 regs = wlc_hw->regs;
1568 mac_l = addr[0] | (addr[1] << 8);
1569 mac_m = addr[2] | (addr[3] << 8);
1570 mac_h = addr[4] | (addr[5] << 8);
1572 /* enter the MAC addr into the RXE match registers */
1573 W_REG(®s->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1574 W_REG(®s->rcm_mat_data, mac_l);
1575 W_REG(®s->rcm_mat_data, mac_m);
1576 W_REG(®s->rcm_mat_data, mac_h);
1581 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1587 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1589 regs = wlc_hw->regs;
1590 W_REG(®s->tplatewrptr, offset);
1592 /* if MCTL_BIGEND bit set in mac control register,
1593 * the chip swaps data in fifo, as well as data in
1596 be_bit = (R_REG(®s->maccontrol) & MCTL_BIGEND) != 0;
1599 memcpy(&word, buf, sizeof(u32));
1602 word = cpu_to_be32(word);
1604 word = cpu_to_le32(word);
1606 W_REG(®s->tplatewrdata, word);
1608 buf = (u8 *) buf + sizeof(u32);
1613 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1615 wlc_hw->band->CWmin = newmin;
1617 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1618 (void)R_REG(&wlc_hw->regs->objaddr);
1619 W_REG(&wlc_hw->regs->objdata, newmin);
1622 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1624 wlc_hw->band->CWmax = newmax;
1626 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1627 (void)R_REG(&wlc_hw->regs->objaddr);
1628 W_REG(&wlc_hw->regs->objdata, newmax);
1631 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1635 /* request FAST clock if not on */
1636 fastclk = wlc_hw->forcefastclk;
1638 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1640 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1642 wlc_bmac_phy_reset(wlc_hw);
1643 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1645 /* restore the clk */
1647 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1651 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1653 d11regs_t *regs = wlc_hw->regs;
1655 wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1657 /* write beacon length to SCR */
1658 wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1659 /* mark beacon0 valid */
1660 OR_REG(®s->maccommand, MCMD_BCN0VLD);
1664 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1666 d11regs_t *regs = wlc_hw->regs;
1668 wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1670 /* write beacon length to SCR */
1671 wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1672 /* mark beacon1 valid */
1673 OR_REG(®s->maccommand, MCMD_BCN1VLD);
1676 /* mac is assumed to be suspended at this point */
1678 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1681 d11regs_t *regs = wlc_hw->regs;
1684 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1685 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1688 if (!(R_REG(®s->maccommand) & MCMD_BCN0VLD))
1689 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1692 (R_REG(®s->maccommand) & MCMD_BCN1VLD))
1693 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1697 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1700 struct wlc_info *wlc = wlc_hw->wlc;
1701 /* update SYNTHPU_DLY */
1703 if (WLCISLCNPHY(wlc->band)) {
1704 v = SYNTHPU_DLY_LPPHY_US;
1705 } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1706 v = SYNTHPU_DLY_NPHY_US;
1708 v = SYNTHPU_DLY_BPHY_US;
1711 wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1714 /* band-specific init */
1716 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1718 struct wlc_hw_info *wlc_hw = wlc->hw;
1720 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1721 wlc_hw->band->bandunit);
1723 wlc_ucode_bsinit(wlc_hw);
1725 wlc_phy_init(wlc_hw->band->pi, chanspec);
1727 wlc_ucode_txant_set(wlc_hw);
1729 /* cwmin is band-specific, update hardware with value for current band */
1730 wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1731 wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1733 wlc_bmac_update_slot_timing(wlc_hw,
1734 BAND_5G(wlc_hw->band->
1735 bandtype) ? true : wlc_hw->
1738 /* write phytype and phyvers */
1739 wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1740 wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1742 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1743 wlc_upd_ofdm_pctl1_table(wlc_hw);
1745 wlc_bmac_upd_synthpu(wlc_hw);
1748 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1750 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1752 wlc_hw->phyclk = clk;
1754 if (OFF == clk) { /* clear gmode bit, put phy into reset */
1756 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1757 (SICF_PRST | SICF_FGC));
1759 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1762 } else { /* take phy out of reset */
1764 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1766 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1772 /* Perform a soft reset of the PHY PLL */
1773 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1775 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1777 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1778 offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1780 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1781 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1783 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1784 offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1786 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1787 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1791 /* light way to turn on phy clock without reset for NPHY only
1792 * refer to wlc_bmac_core_phy_clk for full version
1794 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1796 /* support(necessary for NPHY and HYPHY) only */
1797 if (!WLCISNPHY(wlc_hw->band))
1801 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1803 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1807 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1810 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1812 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1815 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1817 wlc_phy_t *pih = wlc_hw->band->pi;
1819 bool phy_in_reset = false;
1821 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1826 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1828 /* Specific reset sequence required for NPHY rev 3 and 4 */
1829 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1830 NREV_LE(wlc_hw->band->phyrev, 4)) {
1831 /* Set the PHY bandwidth */
1832 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1836 /* Perform a soft reset of the PHY PLL */
1837 wlc_bmac_core_phypll_reset(wlc_hw);
1840 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1841 (SICF_PRST | SICF_PCLKE));
1842 phy_in_reset = true;
1845 ai_core_cflags(wlc_hw->sih,
1846 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1847 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1851 wlc_bmac_core_phy_clk(wlc_hw, ON);
1854 wlc_phy_anacore(pih, ON);
1857 /* switch to and initialize new band */
1859 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1860 chanspec_t chanspec) {
1861 struct wlc_info *wlc = wlc_hw->wlc;
1864 /* Enable the d11 core before accessing it */
1865 if (!ai_iscoreup(wlc_hw->sih)) {
1866 ai_core_reset(wlc_hw->sih, 0, 0);
1867 wlc_mctrl_reset(wlc_hw);
1870 macintmask = wlc_setband_inact(wlc, bandunit);
1875 wlc_bmac_core_phy_clk(wlc_hw, ON);
1877 /* band-specific initializations */
1878 wlc_bmac_bsinit(wlc, chanspec);
1881 * If there are any pending software interrupt bits,
1882 * then replace these with a harmless nonzero value
1883 * so wlc_dpc() will re-enable interrupts when done.
1885 if (wlc->macintstatus)
1886 wlc->macintstatus = MI_DMAINT;
1888 /* restore macintmask */
1889 wl_intrsrestore(wlc->wl, macintmask);
1891 /* ucode should still be suspended.. */
1892 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1895 /* low-level band switch utility routine */
1896 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1898 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1901 wlc_hw->band = wlc_hw->bandstate[bandunit];
1903 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1904 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1906 /* set gmode core flag */
1907 if (wlc_hw->sbclk && !wlc_hw->noreset) {
1908 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1909 ((bandunit == 0) ? SICF_GMODE : 0));
1913 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1916 /* reject unsupported corerev */
1917 if (!VALID_COREREV(wlc_hw->corerev)) {
1918 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1926 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1928 bool goodboard = true;
1929 uint boardrev = wlc_hw->boardrev;
1933 else if (boardrev > 0xff) {
1934 uint brt = (boardrev & 0xf000) >> 12;
1935 uint b0 = (boardrev & 0xf00) >> 8;
1936 uint b1 = (boardrev & 0xf0) >> 4;
1937 uint b2 = boardrev & 0xf;
1939 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1944 if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1950 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1952 const char *varname = "macaddr";
1955 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1956 macaddr = getvar(wlc_hw->vars, varname);
1957 if (macaddr != NULL)
1960 if (NBANDS_HW(wlc_hw) > 1)
1961 varname = "et1macaddr";
1963 varname = "il0macaddr";
1965 macaddr = getvar(wlc_hw->vars, varname);
1966 if (macaddr == NULL) {
1967 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1968 "getvar(%s) not found\n", wlc_hw->unit, varname);
1975 * Return true if radio is disabled, otherwise false.
1976 * hw radio disable signal is an external pin, users activate it asynchronously
1977 * this function could be called when driver is down and w/o clock
1978 * it operates on different registers depending on corerev and boardflag.
1980 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
1983 u32 resetbits = 0, flags = 0;
1985 xtal = wlc_hw->sbclk;
1987 wlc_bmac_xtal(wlc_hw, ON);
1989 /* may need to take core out of reset first */
1993 * mac no longer enables phyclk automatically when driver
1994 * accesses phyreg throughput mac. This can be skipped since
1995 * only mac reg is accessed below
1997 flags |= SICF_PCLKE;
1999 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2000 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2001 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2002 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2004 (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2006 ai_core_reset(wlc_hw->sih, flags, resetbits);
2007 wlc_mctrl_reset(wlc_hw);
2010 v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2012 /* put core back into reset */
2014 ai_core_disable(wlc_hw->sih, 0);
2017 wlc_bmac_xtal(wlc_hw, OFF);
2022 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2023 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2025 if (wlc_hw->wlc->pub->hw_up)
2028 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2031 * Enable pll and xtal, initialize the power control registers,
2032 * and force fastclock for the remainder of wlc_up().
2034 wlc_bmac_xtal(wlc_hw, ON);
2035 ai_clkctl_init(wlc_hw->sih);
2036 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2038 if (wlc_hw->sih->bustype == PCI_BUS) {
2039 ai_pci_fixcfg(wlc_hw->sih);
2041 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2042 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2043 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2044 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2046 (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2050 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2051 wlc_phy_por_inform(wlc_hw->band->pi);
2053 wlc_hw->ucode_loaded = false;
2054 wlc_hw->wlc->pub->hw_up = true;
2056 if ((wlc_hw->boardflags & BFL_FEM)
2057 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2059 (wlc_hw->boardrev >= 0x1250
2060 && (wlc_hw->boardflags & BFL_FEM_BT)))
2061 ai_epa_4313war(wlc_hw->sih);
2065 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2067 struct hnddma_pub *di = wlc_hw->di[fifo];
2068 return dma_rxreset(di);
2072 * ensure fask clock during reset
2074 * reset d11(out of reset)
2075 * reset phy(out of reset)
2076 * clear software macintstatus for fresh new start
2077 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2079 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2086 if (flags == WLC_USE_COREFLAGS)
2087 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2089 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2091 regs = wlc_hw->regs;
2093 /* request FAST clock if not on */
2094 fastclk = wlc_hw->forcefastclk;
2096 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2098 /* reset the dma engines except first time thru */
2099 if (ai_iscoreup(wlc_hw->sih)) {
2100 for (i = 0; i < NFIFO; i++)
2101 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2102 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2103 "dma_txreset[%d]: cannot stop dma\n",
2104 wlc_hw->unit, __func__, i);
2107 if ((wlc_hw->di[RX_FIFO])
2108 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2109 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2110 "[%d]: cannot stop dma\n",
2111 wlc_hw->unit, __func__, RX_FIFO);
2114 /* if noreset, just stop the psm and return */
2115 if (wlc_hw->noreset) {
2116 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2117 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2122 * mac no longer enables phyclk automatically when driver accesses
2123 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2124 * band->pi is invalid. need to enable PHY CLK
2126 flags |= SICF_PCLKE;
2129 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2130 * is cleared by the core_reset. have to re-request it.
2131 * This adds some delay and we can optimize it by also requesting fastclk through
2132 * chipcommon during this period if necessary. But that has to work coordinate
2133 * with other driver like mips/arm since they may touch chipcommon as well.
2135 wlc_hw->clk = false;
2136 ai_core_reset(wlc_hw->sih, flags, resetbits);
2138 if (wlc_hw->band && wlc_hw->band->pi)
2139 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2141 wlc_mctrl_reset(wlc_hw);
2143 if (PMUCTL_ENAB(wlc_hw->sih))
2144 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2146 wlc_bmac_phy_reset(wlc_hw);
2148 /* turn on PHY_PLL */
2149 wlc_bmac_core_phypll_ctl(wlc_hw, true);
2151 /* clear sw intstatus */
2152 wlc_hw->wlc->macintstatus = 0;
2154 /* restore the clk setting */
2156 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2159 /* txfifo sizes needs to be modified(increased) since the newer cores
2162 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2164 d11regs_t *regs = wlc_hw->regs;
2166 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2167 u16 txfifo_def, txfifo_def1;
2170 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2171 txfifo_startblk = TXFIFO_START_BLK;
2173 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2174 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2176 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2177 txfifo_def = (txfifo_startblk & 0xff) |
2178 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2179 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2181 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2183 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2185 W_REG(®s->xmtfifocmd, txfifo_cmd);
2186 W_REG(®s->xmtfifodef, txfifo_def);
2187 W_REG(®s->xmtfifodef1, txfifo_def1);
2189 W_REG(®s->xmtfifocmd, txfifo_cmd);
2191 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2194 * need to propagate to shm location to be in sync since ucode/hw won't
2197 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2198 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2199 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2200 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2201 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2202 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2203 xmtfifo_sz[TX_AC_BK_FIFO]));
2204 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2205 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2206 xmtfifo_sz[TX_BCMC_FIFO]));
2211 * download ucode/PCM
2212 * let ucode run to suspended
2213 * download ucode inits
2214 * config other core registers
2217 static void wlc_coreinit(struct wlc_info *wlc)
2219 struct wlc_hw_info *wlc_hw = wlc->hw;
2224 bool fifosz_fixup = false;
2227 struct wiphy *wiphy = wlc->wiphy;
2229 regs = wlc_hw->regs;
2231 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2234 wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2236 wlc_ucode_download(wlc_hw);
2238 * FIFOSZ fixup. driver wants to controls the fifo allocation.
2240 fifosz_fixup = true;
2242 /* let the PSM run to the suspended state, set mode to BSS STA */
2243 W_REG(®s->macintstatus, -1);
2244 wlc_bmac_mctrl(wlc_hw, ~0,
2245 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2247 /* wait for ucode to self-suspend after auto-init */
2248 SPINWAIT(((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0),
2250 if ((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0)
2251 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2252 "suspend!\n", wlc_hw->unit);
2256 sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2258 if (D11REV_IS(wlc_hw->corerev, 23)) {
2259 if (WLCISNPHY(wlc_hw->band))
2260 wlc_write_inits(wlc_hw, d11n0initvals16);
2262 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2263 " %d\n", __func__, wlc_hw->unit,
2265 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2266 if (WLCISLCNPHY(wlc_hw->band)) {
2267 wlc_write_inits(wlc_hw, d11lcn0initvals24);
2269 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2270 " %d\n", __func__, wlc_hw->unit,
2274 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2275 __func__, wlc_hw->unit, wlc_hw->corerev);
2278 /* For old ucode, txfifo sizes needs to be modified(increased) */
2279 if (fifosz_fixup == true) {
2280 wlc_corerev_fifofixup(wlc_hw);
2283 /* check txfifo allocations match between ucode and driver */
2284 buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2285 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2289 buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2290 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2294 buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2295 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2296 buf[TX_AC_BK_FIFO] &= 0xff;
2297 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2301 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2305 buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2306 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2307 buf[TX_BCMC_FIFO] &= 0xff;
2308 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2312 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2317 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2318 " driver size %d index %d\n", buf[i],
2319 wlc_hw->xmtfifo_sz[i], i);
2322 /* make sure we can still talk to the mac */
2323 WARN_ON(R_REG(®s->maccontrol) == 0xffffffff);
2325 /* band-specific inits done by wlc_bsinit() */
2327 /* Set up frame burst size and antenna swap threshold init values */
2328 wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2329 wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2331 /* enable one rx interrupt per received frame */
2332 W_REG(®s->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2334 /* set the station mode (BSS STA) */
2335 wlc_bmac_mctrl(wlc_hw,
2336 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2337 (MCTL_INFRA | MCTL_DISCARD_PMQ));
2339 /* set up Beacon interval */
2340 bcnint_us = 0x8000 << 10;
2341 W_REG(®s->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2342 W_REG(®s->tsf_cfpstart, bcnint_us);
2343 W_REG(®s->macintstatus, MI_GP1);
2345 /* write interrupt mask */
2346 W_REG(®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2348 /* allow the MAC to control the PHY clock (dynamic on/off) */
2349 wlc_bmac_macphyclk_set(wlc_hw, ON);
2351 /* program dynamic clock control fast powerup delay register */
2352 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2353 W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2355 /* tell the ucode the corerev */
2356 wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2358 /* tell the ucode MAC capabilities */
2359 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2360 (u16) (wlc_hw->machwcap & 0xffff));
2361 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2363 machwcap >> 16) & 0xffff));
2365 /* write retry limits to SCR, this done after PSM init */
2366 W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2367 (void)R_REG(®s->objaddr);
2368 W_REG(®s->objdata, wlc_hw->SRL);
2369 W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2370 (void)R_REG(®s->objaddr);
2371 W_REG(®s->objdata, wlc_hw->LRL);
2373 /* write rate fallback retry limits */
2374 wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2375 wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2377 AND_REG(®s->ifs_ctl, 0x0FFF);
2378 W_REG(®s->ifs_aifsn, EDCF_AIFSN_MIN);
2380 /* dma initializations */
2381 wlc->txpend16165war = 0;
2383 /* init the tx dma engines */
2384 for (i = 0; i < NFIFO; i++) {
2386 dma_txinit(wlc_hw->di[i]);
2389 /* init the rx dma engine(s) and post receive buffers */
2390 dma_rxinit(wlc_hw->di[RX_FIFO]);
2391 dma_rxfill(wlc_hw->di[RX_FIFO]);
2394 /* This function is used for changing the tsf frac register
2395 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2396 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2397 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2398 * HTPHY Formula is 2^26/freq(MHz) e.g.
2399 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2400 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2401 * For spuron: 123MHz -> 2^26/123 = 545600.5
2402 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2403 * For spur off: 120MHz -> 2^26/120 = 559240.5
2404 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2407 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2410 regs = wlc_hw->regs;
2412 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2413 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2414 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2415 W_REG(®s->tsf_clk_frac_l, 0x2082);
2416 W_REG(®s->tsf_clk_frac_h, 0x8);
2417 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2418 W_REG(®s->tsf_clk_frac_l, 0x5341);
2419 W_REG(®s->tsf_clk_frac_h, 0x8);
2420 } else { /* 120Mhz */
2421 W_REG(®s->tsf_clk_frac_l, 0x8889);
2422 W_REG(®s->tsf_clk_frac_h, 0x8);
2424 } else if (WLCISLCNPHY(wlc_hw->band)) {
2425 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2426 W_REG(®s->tsf_clk_frac_l, 0x7CE0);
2427 W_REG(®s->tsf_clk_frac_h, 0xC);
2428 } else { /* 80Mhz */
2429 W_REG(®s->tsf_clk_frac_l, 0xCCCD);
2430 W_REG(®s->tsf_clk_frac_h, 0xC);
2435 /* Initialize GPIOs that are controlled by D11 core */
2436 static void wlc_gpio_init(struct wlc_info *wlc)
2438 struct wlc_hw_info *wlc_hw = wlc->hw;
2442 regs = wlc_hw->regs;
2444 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2445 wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2448 * Common GPIO setup:
2449 * G0 = LED 0 = WLAN Activity
2450 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2451 * G2 = LED 2 = WLAN 5 GHz Radio State
2452 * G4 = radio disable input (HI enabled, LO disabled)
2457 /* Allocate GPIOs for mimo antenna diversity feature */
2458 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2459 /* Enable antenna diversity, use 2x3 mode */
2460 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2461 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2462 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2463 MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2465 /* init superswitch control */
2466 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2468 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2469 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2471 * The board itself is powered by these GPIOs
2472 * (when not sending pattern) so set them high
2474 OR_REG(®s->psm_gpio_oe,
2475 (BOARD_GPIO_12 | BOARD_GPIO_13));
2476 OR_REG(®s->psm_gpio_out,
2477 (BOARD_GPIO_12 | BOARD_GPIO_13));
2479 /* Enable antenna diversity, use 2x4 mode */
2480 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2481 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2482 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2485 /* Configure the desired clock to be 4Mhz */
2486 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2487 ANTSEL_CLKDIV_4MHZ);
2490 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2491 if (wlc_hw->boardflags & BFL_PACTRL)
2492 gm |= gc |= BOARD_GPIO_PACTRL;
2494 /* apply to gpiocontrol register */
2495 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2498 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2500 struct wlc_info *wlc;
2503 if (wlc_hw->ucode_loaded)
2506 if (D11REV_IS(wlc_hw->corerev, 23)) {
2507 if (WLCISNPHY(wlc_hw->band)) {
2508 wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2510 wlc_hw->ucode_loaded = true;
2512 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2514 __func__, wlc_hw->unit, wlc_hw->corerev);
2515 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2516 if (WLCISLCNPHY(wlc_hw->band)) {
2517 wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2519 wlc_hw->ucode_loaded = true;
2521 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2523 __func__, wlc_hw->unit, wlc_hw->corerev);
2528 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2529 const uint nbytes) {
2530 d11regs_t *regs = wlc_hw->regs;
2534 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2536 count = (nbytes / sizeof(u32));
2538 W_REG(®s->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2539 (void)R_REG(®s->objaddr);
2540 for (i = 0; i < count; i++)
2541 W_REG(®s->objdata, ucode[i]);
2544 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2545 const struct d11init *inits)
2550 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2552 base = (volatile u8 *)wlc_hw->regs;
2554 for (i = 0; inits[i].addr != 0xffff; i++) {
2555 if (inits[i].size == 2)
2556 W_REG((u16 *)(base + inits[i].addr),
2558 else if (inits[i].size == 4)
2559 W_REG((u32 *)(base + inits[i].addr),
2564 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2567 u16 phytxant = wlc_hw->bmac_phytxant;
2568 u16 mask = PHY_TXC_ANT_MASK;
2570 /* set the Probe Response frame phy control word */
2571 phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2572 phyctl = (phyctl & ~mask) | phytxant;
2573 wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2575 /* set the Response (ACK/CTS) frame phy control word */
2576 phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2577 phyctl = (phyctl & ~mask) | phytxant;
2578 wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2581 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2583 /* update sw state */
2584 wlc_hw->bmac_phytxant = phytxant;
2586 /* push to ucode if up */
2589 wlc_ucode_txant_set(wlc_hw);
2593 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2595 return (u16) wlc_hw->wlc->stf->txant;
2598 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2600 wlc_hw->antsel_type = antsel_type;
2602 /* Update the antsel type for phy module to use */
2603 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2606 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2610 uint intstatus, idx;
2611 d11regs_t *regs = wlc_hw->regs;
2612 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2614 unit = wlc_hw->unit;
2616 for (idx = 0; idx < NFIFO; idx++) {
2617 /* read intstatus register and ignore any non-error bits */
2619 R_REG(®s->intctrlregs[idx].intstatus) & I_ERRORS;
2623 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2624 unit, idx, intstatus);
2626 if (intstatus & I_RO) {
2627 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2628 "overflow\n", unit, idx);
2632 if (intstatus & I_PC) {
2633 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2638 if (intstatus & I_PD) {
2639 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2644 if (intstatus & I_DE) {
2645 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2646 "error\n", unit, idx);
2650 if (intstatus & I_RU) {
2651 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2652 "underflow\n", idx, unit);
2655 if (intstatus & I_XU) {
2656 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2657 "underflow\n", idx, unit);
2662 wlc_fatal_error(wlc_hw->wlc); /* big hammer */
2665 W_REG(®s->intctrlregs[idx].intstatus,
2670 void wlc_intrson(struct wlc_info *wlc)
2672 struct wlc_hw_info *wlc_hw = wlc->hw;
2673 wlc->macintmask = wlc->defmacintmask;
2674 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2677 /* callback for siutils.c, which has only wlc handler, no wl
2678 * they both check up, not only because there is no need to off/restore d11 interrupt
2679 * but also because per-port code may require sync with valid interrupt.
2682 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2687 return wl_intrsoff(wlc->wl);
2690 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2695 wl_intrsrestore(wlc->wl, macintmask);
2698 u32 wlc_intrsoff(struct wlc_info *wlc)
2700 struct wlc_hw_info *wlc_hw = wlc->hw;
2706 macintmask = wlc->macintmask; /* isr can still happen */
2708 W_REG(&wlc_hw->regs->macintmask, 0);
2709 (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2710 udelay(1); /* ensure int line is no longer driven */
2711 wlc->macintmask = 0;
2713 /* return previous macintmask; resolve race between us and our isr */
2714 return wlc->macintstatus ? 0 : macintmask;
2717 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2719 struct wlc_hw_info *wlc_hw = wlc->hw;
2723 wlc->macintmask = macintmask;
2724 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2727 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2729 u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2732 /* suspend tx fifos */
2733 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2734 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2735 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2736 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2738 /* zero the address match register so we do not send ACKs */
2739 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2742 /* resume tx fifos */
2743 if (!wlc_hw->wlc->tx_suspended) {
2744 wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2746 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2747 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2748 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2750 /* Restore address */
2751 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2755 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2758 wlc_ucode_mute_override_set(wlc_hw);
2760 wlc_ucode_mute_override_clear(wlc_hw);
2763 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2768 *blocks = wlc_hw->xmtfifo_sz[fifo];
2773 /* wlc_bmac_tx_fifo_suspended:
2774 * Check the MAC's tx suspend status for a tx fifo.
2776 * When the MAC acknowledges a tx suspend, it indicates that no more
2777 * packets will be transmitted out the radio. This is independent of
2778 * DMA channel suspension---the DMA may have finished suspending, or may still
2779 * be pulling data into a tx fifo, by the time the MAC acks the suspend
2782 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2784 /* check that a suspend has been requested and is no longer pending */
2787 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2788 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2789 * chnstatus register.
2790 * The tx fifo suspend completion is independent of the DMA suspend completion and
2791 * may be acked before or after the DMA is suspended.
2793 if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2794 (R_REG(&wlc_hw->regs->chnstatus) &
2795 (1 << tx_fifo)) == 0)
2801 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2803 u8 fifo = 1 << tx_fifo;
2805 /* Two clients of this code, 11h Quiet period and scanning. */
2807 /* only suspend if not already suspended */
2808 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2811 /* force the core awake only if not already */
2812 if (wlc_hw->suspended_fifos == 0)
2813 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2815 wlc_hw->suspended_fifos |= fifo;
2817 if (wlc_hw->di[tx_fifo]) {
2818 /* Suspending AMPDU transmissions in the middle can cause underflow
2819 * which may result in mismatch between ucode and driver
2820 * so suspend the mac before suspending the FIFO
2822 if (WLC_PHY_11N_CAP(wlc_hw->band))
2823 wlc_suspend_mac_and_wait(wlc_hw->wlc);
2825 dma_txsuspend(wlc_hw->di[tx_fifo]);
2827 if (WLC_PHY_11N_CAP(wlc_hw->band))
2828 wlc_enable_mac(wlc_hw->wlc);
2832 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2834 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2835 * here for PIO otherwise the watchdog will catch the inconsistency and fire
2837 /* Two clients of this code, 11h Quiet period and scanning. */
2838 if (wlc_hw->di[tx_fifo])
2839 dma_txresume(wlc_hw->di[tx_fifo]);
2841 /* allow core to sleep again */
2842 if (wlc_hw->suspended_fifos == 0)
2845 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2846 if (wlc_hw->suspended_fifos == 0)
2847 wlc_ucode_wake_override_clear(wlc_hw,
2848 WLC_WAKE_OVERRIDE_TXFIFO);
2853 * Read and clear macintmask and macintstatus and intstatus registers.
2854 * This routine should be called with interrupts off
2856 * -1 if DEVICEREMOVED(wlc) evaluates to true;
2857 * 0 if the interrupt is not for us, or we are in some special cases;
2858 * device interrupt status bits otherwise.
2860 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2862 struct wlc_hw_info *wlc_hw = wlc->hw;
2863 d11regs_t *regs = wlc_hw->regs;
2866 /* macintstatus includes a DMA interrupt summary bit */
2867 macintstatus = R_REG(®s->macintstatus);
2869 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2872 /* detect cardbus removed, in power down(suspend) and in reset */
2873 if (DEVICEREMOVED(wlc))
2876 /* DEVICEREMOVED succeeds even when the core is still resetting,
2877 * handle that case here.
2879 if (macintstatus == 0xffffffff)
2882 /* defer unsolicited interrupts */
2883 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2886 if (macintstatus == 0)
2889 /* interrupts are already turned off for CFE build
2890 * Caution: For CFE Turning off the interrupts again has some undesired
2893 /* turn off the interrupts */
2894 W_REG(®s->macintmask, 0);
2895 (void)R_REG(®s->macintmask); /* sync readback */
2896 wlc->macintmask = 0;
2898 /* clear device interrupts */
2899 W_REG(®s->macintstatus, macintstatus);
2901 /* MI_DMAINT is indication of non-zero intstatus */
2902 if (macintstatus & MI_DMAINT) {
2904 * only fifo interrupt enabled is I_RI in
2905 * RX_FIFO. If MI_DMAINT is set, assume it
2906 * is set and clear the interrupt.
2908 W_REG(®s->intctrlregs[RX_FIFO].intstatus,
2912 return macintstatus;
2915 /* Update wlc->macintstatus and wlc->intstatus[]. */
2916 /* Return true if they are updated successfully. false otherwise */
2917 bool wlc_intrsupd(struct wlc_info *wlc)
2921 /* read and clear macintstatus and intstatus registers */
2922 macintstatus = wlc_intstatus(wlc, false);
2924 /* device is removed */
2925 if (macintstatus == 0xffffffff)
2928 /* update interrupt status in software */
2929 wlc->macintstatus |= macintstatus;
2935 * First-level interrupt processing.
2936 * Return true if this was our interrupt, false otherwise.
2937 * *wantdpc will be set to true if further wlc_dpc() processing is required,
2940 bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2942 struct wlc_hw_info *wlc_hw = wlc->hw;
2947 if (!wlc_hw->up || !wlc->macintmask)
2950 /* read and clear macintstatus and intstatus registers */
2951 macintstatus = wlc_intstatus(wlc, true);
2953 if (macintstatus == 0xffffffff)
2954 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2957 /* it is not for us */
2958 if (macintstatus == 0)
2963 /* save interrupt status bits */
2964 wlc->macintstatus = macintstatus;
2971 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2973 /* discard intermediate indications for ucode with one legitimate case:
2974 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2975 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2976 * transmission count)
2978 if (!(txs->status & TX_STATUS_AMPDU)
2979 && (txs->status & TX_STATUS_INTERMEDIATE)) {
2983 return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
2986 /* process tx completion events in BMAC
2987 * Return true if more tx status need to be processed. false otherwise.
2990 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
2992 bool morepending = false;
2993 struct wlc_info *wlc = wlc_hw->wlc;
2995 tx_status_t txstatus, *txs;
2999 * Param 'max_tx_num' indicates max. # tx status to process before
3002 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3004 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3007 regs = wlc_hw->regs;
3009 && (s1 = R_REG(®s->frmtxstatus)) & TXS_V) {
3011 if (s1 == 0xffffffff) {
3012 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
3013 wlc_hw->unit, __func__);
3017 s2 = R_REG(®s->frmtxstatus2);
3019 txs->status = s1 & TXS_STATUS_MASK;
3020 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3021 txs->sequence = s2 & TXS_SEQ_MASK;
3022 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3023 txs->lasttxtime = 0;
3025 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3027 /* !give others some time to run! */
3028 if (++n >= max_tx_num)
3035 if (n >= max_tx_num)
3038 if (!pktq_empty(&wlc->pkt_queue->q))
3044 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3046 struct wlc_hw_info *wlc_hw = wlc->hw;
3047 d11regs_t *regs = wlc_hw->regs;
3049 struct wiphy *wiphy = wlc->wiphy;
3051 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3052 wlc_hw->band->bandunit);
3055 * Track overlapping suspend requests
3057 wlc_hw->mac_suspend_depth++;
3058 if (wlc_hw->mac_suspend_depth > 1)
3061 /* force the core awake */
3062 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3064 mc = R_REG(®s->maccontrol);
3066 if (mc == 0xffffffff) {
3067 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3072 WARN_ON(mc & MCTL_PSM_JMP_0);
3073 WARN_ON(!(mc & MCTL_PSM_RUN));
3074 WARN_ON(!(mc & MCTL_EN_MAC));
3076 mi = R_REG(®s->macintstatus);
3077 if (mi == 0xffffffff) {
3078 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3083 WARN_ON(mi & MI_MACSSPNDD);
3085 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3087 SPINWAIT(!(R_REG(®s->macintstatus) & MI_MACSSPNDD),
3088 WLC_MAX_MAC_SUSPEND);
3090 if (!(R_REG(®s->macintstatus) & MI_MACSSPNDD)) {
3091 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3092 " and MI_MACSSPNDD is still not on.\n",
3093 wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3094 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3095 "psm_brc 0x%04x\n", wlc_hw->unit,
3096 R_REG(®s->psmdebug),
3097 R_REG(®s->phydebug),
3098 R_REG(®s->psm_brc));
3101 mc = R_REG(®s->maccontrol);
3102 if (mc == 0xffffffff) {
3103 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3108 WARN_ON(mc & MCTL_PSM_JMP_0);
3109 WARN_ON(!(mc & MCTL_PSM_RUN));
3110 WARN_ON(mc & MCTL_EN_MAC);
3113 void wlc_enable_mac(struct wlc_info *wlc)
3115 struct wlc_hw_info *wlc_hw = wlc->hw;
3116 d11regs_t *regs = wlc_hw->regs;
3119 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3120 wlc->band->bandunit);
3123 * Track overlapping suspend requests
3125 wlc_hw->mac_suspend_depth--;
3126 if (wlc_hw->mac_suspend_depth > 0)
3129 mc = R_REG(®s->maccontrol);
3130 WARN_ON(mc & MCTL_PSM_JMP_0);
3131 WARN_ON(mc & MCTL_EN_MAC);
3132 WARN_ON(!(mc & MCTL_PSM_RUN));
3134 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3135 W_REG(®s->macintstatus, MI_MACSSPNDD);
3137 mc = R_REG(®s->maccontrol);
3138 WARN_ON(mc & MCTL_PSM_JMP_0);
3139 WARN_ON(!(mc & MCTL_EN_MAC));
3140 WARN_ON(!(mc & MCTL_PSM_RUN));
3142 mi = R_REG(®s->macintstatus);
3143 WARN_ON(mi & MI_MACSSPNDD);
3145 wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3148 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3152 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3153 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3159 if (!WLC_PHY_11N_CAP(wlc_hw->band))
3162 /* walk the phy rate table and update the entries */
3163 for (i = 0; i < ARRAY_SIZE(rates); i++) {
3166 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3168 /* read the SHM Rate Table entry OFDM PCTL1 values */
3170 wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3172 /* modify the value */
3173 pctl1 &= ~PHY_TXC1_MODE_MASK;
3174 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3176 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3177 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3182 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3186 struct plcp_signal_rate_lookup {
3190 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3191 const struct plcp_signal_rate_lookup rate_lookup[] = {
3194 {WLC_RATE_12M, 0xA},
3195 {WLC_RATE_18M, 0xE},
3196 {WLC_RATE_24M, 0x9},
3197 {WLC_RATE_36M, 0xD},
3198 {WLC_RATE_48M, 0x8},
3202 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3203 if (rate == rate_lookup[i].rate) {
3204 plcp_rate = rate_lookup[i].signal_rate;
3209 /* Find the SHM pointer to the rate table entry by looking in the
3212 return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3215 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3217 wlc_hw->hw_stf_ss_opmode = stf_mode;
3220 wlc_upd_ofdm_pctl1_table(wlc_hw);
3224 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3227 d11regs_t *regs = wlc_hw->regs;
3229 /* read the tsf timer low, then high to get an atomic read */
3230 *tsf_l_ptr = R_REG(®s->tsf_timerlow);
3231 *tsf_h_ptr = R_REG(®s->tsf_timerhigh);
3236 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3240 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3242 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3244 regs = wlc_hw->regs;
3246 /* Validate dchip register access */
3248 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3249 (void)R_REG(®s->objaddr);
3250 w = R_REG(®s->objdata);
3252 /* Can we write and read back a 32bit register? */
3253 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3254 (void)R_REG(®s->objaddr);
3255 W_REG(®s->objdata, (u32) 0xaa5555aa);
3257 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3258 (void)R_REG(®s->objaddr);
3259 val = R_REG(®s->objdata);
3260 if (val != (u32) 0xaa5555aa) {
3261 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3262 "expected 0xaa5555aa\n", wlc_hw->unit, val);
3266 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3267 (void)R_REG(®s->objaddr);
3268 W_REG(®s->objdata, (u32) 0x55aaaa55);
3270 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3271 (void)R_REG(®s->objaddr);
3272 val = R_REG(®s->objdata);
3273 if (val != (u32) 0x55aaaa55) {
3274 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3275 "expected 0x55aaaa55\n", wlc_hw->unit, val);
3279 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3280 (void)R_REG(®s->objaddr);
3281 W_REG(®s->objdata, w);
3283 /* clear CFPStart */
3284 W_REG(®s->tsf_cfpstart, 0);
3286 w = R_REG(®s->maccontrol);
3287 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3288 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3289 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3290 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3291 (MCTL_IHR_EN | MCTL_WAKE),
3292 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3299 #define PHYPLL_WAIT_US 100000
3301 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3306 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3309 regs = wlc_hw->regs;
3312 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3313 OR_REG(®s->clk_ctl_st,
3314 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3315 CCS_ERSRC_REQ_PHYPLL));
3316 SPINWAIT((R_REG(®s->clk_ctl_st) &
3317 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3320 tmp = R_REG(®s->clk_ctl_st);
3321 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3322 (CCS_ERSRC_AVAIL_HT)) {
3323 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3324 " PLL failed\n", __func__);
3327 OR_REG(®s->clk_ctl_st,
3328 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3329 SPINWAIT((R_REG(®s->clk_ctl_st) &
3330 (CCS_ERSRC_AVAIL_D11PLL |
3331 CCS_ERSRC_AVAIL_PHYPLL)) !=
3332 (CCS_ERSRC_AVAIL_D11PLL |
3333 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3335 tmp = R_REG(®s->clk_ctl_st);
3337 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3339 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3340 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3341 "PHY PLL failed\n", __func__);
3345 /* Since the PLL may be shared, other cores can still be requesting it;
3346 * so we'll deassert the request but not wait for status to comply.
3348 AND_REG(®s->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3349 tmp = R_REG(®s->clk_ctl_st);
3353 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3357 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3359 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3364 if (wlc_hw->noreset)
3368 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3370 /* turn off analog core */
3371 wlc_phy_anacore(wlc_hw->band->pi, OFF);
3373 /* turn off PHYPLL to save power */
3374 wlc_bmac_core_phypll_ctl(wlc_hw, false);
3376 /* No need to set wlc->pub->radio_active = OFF
3377 * because this function needs down capability and
3378 * radio_active is designed for BCMNODOWN.
3381 /* remove gpio controls */
3382 if (wlc_hw->ucode_dbgsel)
3383 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3385 wlc_hw->clk = false;
3386 ai_core_disable(wlc_hw->sih, 0);
3387 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3390 /* power both the pll and external oscillator on/off */
3391 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3393 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3395 /* dont power down if plldown is false or we must poll hw radio disable */
3396 if (!want && wlc_hw->pllreq)
3400 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3402 wlc_hw->sbclk = want;
3403 if (!wlc_hw->sbclk) {
3404 wlc_hw->clk = false;
3405 if (wlc_hw->band && wlc_hw->band->pi)
3406 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3410 static void wlc_flushqueues(struct wlc_info *wlc)
3412 struct wlc_hw_info *wlc_hw = wlc->hw;
3415 wlc->txpend16165war = 0;
3417 /* free any posted tx packets */
3418 for (i = 0; i < NFIFO; i++)
3419 if (wlc_hw->di[i]) {
3420 dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3421 TXPKTPENDCLR(wlc, i);
3422 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3425 /* free any posted rx packets */
3426 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3429 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3431 return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3434 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3436 wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3440 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3442 d11regs_t *regs = wlc_hw->regs;
3443 volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
3444 volatile u16 *objdata_hi = objdata_lo + 1;
3447 W_REG(®s->objaddr, sel | (offset >> 2));
3448 (void)R_REG(®s->objaddr);
3450 v = R_REG(objdata_hi);
3452 v = R_REG(objdata_lo);
3459 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3461 d11regs_t *regs = wlc_hw->regs;
3462 volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
3463 volatile u16 *objdata_hi = objdata_lo + 1;
3465 W_REG(®s->objaddr, sel | (offset >> 2));
3466 (void)R_REG(®s->objaddr);
3468 W_REG(objdata_hi, v);
3470 W_REG(objdata_lo, v);
3474 /* Copy a buffer to shared memory of specified type .
3475 * SHM 'offset' needs to be an even address and
3476 * Buffer length 'len' must be an even number of bytes
3477 * 'sel' selects the type of memory
3480 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3484 const u8 *p = (const u8 *)buf;
3487 if (len <= 0 || (offset & 1) || (len & 1))
3490 for (i = 0; i < len; i += 2) {
3491 v = p[i] | (p[i + 1] << 8);
3492 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3496 /* Copy a piece of shared memory of specified type to a buffer .
3497 * SHM 'offset' needs to be an even address and
3498 * Buffer length 'len' must be an even number of bytes
3499 * 'sel' selects the type of memory
3502 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3509 if (len <= 0 || (offset & 1) || (len & 1))
3512 for (i = 0; i < len; i += 2) {
3513 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3515 p[i + 1] = (v >> 8) & 0xFF;
3519 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3521 BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3524 *buf = wlc_hw->vars;
3525 *len = wlc_hw->vars_size;
3528 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3533 /* write retry limit to SCR, shouldn't need to suspend */
3535 W_REG(&wlc_hw->regs->objaddr,
3536 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3537 (void)R_REG(&wlc_hw->regs->objaddr);
3538 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3539 W_REG(&wlc_hw->regs->objaddr,
3540 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3541 (void)R_REG(&wlc_hw->regs->objaddr);
3542 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3546 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3549 if (mboolisset(wlc_hw->pllreq, req_bit))
3552 mboolset(wlc_hw->pllreq, req_bit);
3554 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3555 if (!wlc_hw->sbclk) {
3556 wlc_bmac_xtal(wlc_hw, ON);
3560 if (!mboolisset(wlc_hw->pllreq, req_bit))
3563 mboolclr(wlc_hw->pllreq, req_bit);
3565 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3566 if (wlc_hw->sbclk) {
3567 wlc_bmac_xtal(wlc_hw, OFF);
3575 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3580 /* get the phy specific rate encoding for the PLCP SIGNAL field */
3581 /* XXX4321 fixup needed ? */
3583 table_ptr = M_RT_DIRMAP_A;
3585 table_ptr = M_RT_DIRMAP_B;
3587 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3588 * the index into the rate table.
3590 phy_rate = rate_info[rate] & WLC_RATE_MASK;
3591 index = phy_rate & 0xf;
3593 /* Find the SHM pointer to the rate table entry by looking in the
3596 return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3599 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3601 wlc_hw->antsel_avail = antsel_avail;