drivers/staging/brcm80211/brcmsmac/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23
  24 #include <proto/802.11.h>
  25 #include <bcmdefs.h>
  26 #include <bcmdevs.h>
  27 #include <bcmwifi.h>
  28 #include <aiutils.h>
  29 #include <bcmsrom.h>
  30 #include <bcmotp.h>
  31 #include <bcmutils.h>
  32 #include <bcmnvram.h>
  33 #include <sbconfig.h>
  34 #include <sbchipc.h>
  35 #include <pcicfg.h>
  36 #include <sbhnddma.h>
  37 #include <hnddma.h>
  38
  39 #include "wlc_types.h"
  40 #include "wlc_pmu.h"
  41 #include "d11.h"
  42 #include "wlc_cfg.h"
  43 #include "wlc_rate.h"
  44 #include "wlc_scb.h"
  45 #include "wlc_pub.h"
  46 #include "wlc_key.h"
  47 #include "phy/wlc_phy_hal.h"
  48 #include "wlc_channel.h"
  49 #include "wlc_main.h"
  50 #include "wl_export.h"
  51 #include "wl_ucode.h"
  52 #include "wlc_antsel.h"
  53 #include "pcie_core.h"
  54 #include "wlc_alloc.h"
  55 #include "wl_dbg.h"
  56 #include "wlc_bmac.h"
  57
  58 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  59
  60 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  61 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  62 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  63 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  64
  65 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  66
  67 #ifndef BMAC_DUP_TO_REMOVE
  68 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  69
  70 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  71
  72 #endif                          /* BMAC_DUP_TO_REMOVE */
  73
  74 #define DMAREG(wlc_hw, direction, fifonum) \
  75         ((direction == DMA_TX) ? \
  76                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
  77                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
  78
  79 /*
  80  * The following table lists the buffer memory allocated to xmt fifos in HW.
  81  * the size is in units of 256bytes(one block), total size is HW dependent
  82  * ucode has default fifo partition, sw can overwrite if necessary
  83  *
  84  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  85  * the twiki is updated before making changes.
  86  */
  87
  88 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
  89
  90 static u16 xmtfifo_sz[][NFIFO] = {
  91         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  92         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  93         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  94         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  95         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  96 };
  97
  98 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
  99 static void wlc_coreinit(struct wlc_info *wlc);
 100
 101 /* used by wlc_wakeucode_init() */
 102 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
 103                             const struct d11init *inits);
 104 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 105                             const uint nbytes);
 106 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 107 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 108
 109 /* used by wlc_dpc() */
 110 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 111                                 u32 s2);
 112 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 113 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 114
 115 /* used by wlc_down() */
 116 static void wlc_flushqueues(struct wlc_info *wlc);
 117
 118 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 119 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 120 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 121 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
 122                                        uint tx_fifo);
 123 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 124 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 125
 126 /* Low Level Prototypes */
 127 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
 128 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
 129 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
 130 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 131                                    u32 sel);
 132 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 133                                   u16 v, u32 sel);
 134 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
 135 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 136 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 137 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 138 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 139 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 140 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
 141 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 142 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 143 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 144 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
 145 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 146 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 147 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 148 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 149 static void wlc_gpio_init(struct wlc_info *wlc);
 150 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 151                                       int len);
 152 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 153                                       int len);
 154 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 155 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 156 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 157                              chanspec_t chanspec);
 158 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 159                                         bool shortslot);
 160 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 161 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 162                                              u8 rate);
 163
 164 /* === Low Level functions === */
 165
 166 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 167 {
 168         wlc_hw->shortslot = shortslot;
 169
 170         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 171                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 172                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 173                 wlc_enable_mac(wlc_hw->wlc);
 174         }
 175 }
 176
 177 /*
 178  * Update the slot timing for standard 11b/g (20us slots)
 179  * or shortslot 11g (9us slots)
 180  * The PSM needs to be suspended for this call.
 181  */
 182 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 183                                         bool shortslot)
 184 {
 185         d11regs_t *regs;
 186
 187         regs = wlc_hw->regs;
 188
 189         if (shortslot) {
 190                 /* 11g short slot: 11a timing */
 191                 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
 192                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 193         } else {
 194                 /* 11g long slot: 11b timing */
 195                 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
 196                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 197         }
 198 }
 199
 200 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 201 {
 202         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
 203
 204         /* init microcode host flags */
 205         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 206
 207         /* do band-specific ucode IHR, SHM, and SCR inits */
 208         if (D11REV_IS(wlc_hw->corerev, 23)) {
 209                 if (WLCISNPHY(wlc_hw->band)) {
 210                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 211                 } else {
 212                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
 213                                   " %d\n", __func__, wlc_hw->unit,
 214                                   wlc_hw->corerev);
 215                 }
 216         } else {
 217                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 218                         if (WLCISLCNPHY(wlc_hw->band)) {
 219                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 220                         } else
 221                                 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
 222                                           " core rev %d\n", __func__,
 223                                           wlc_hw->unit, wlc_hw->corerev);
 224                 } else {
 225                         wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
 226                                 __func__, wlc_hw->unit, wlc_hw->corerev);
 227                 }
 228         }
 229 }
 230
 231 /* switch to new band but leave it inactive */
 232 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 233 {
 234         struct wlc_hw_info *wlc_hw = wlc->hw;
 235         u32 macintmask;
 236
 237         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 238
 239         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
 240
 241         /* disable interrupts */
 242         macintmask = wl_intrsoff(wlc->wl);
 243
 244         /* radio off */
 245         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 246
 247         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 248
 249         wlc_setxband(wlc_hw, bandunit);
 250
 251         return macintmask;
 252 }
 253
 254 /* Process received frames */
 255 /*
 256  * Return true if more frames need to be processed. false otherwise.
 257  * Param 'bound' indicates max. # frames to process before break out.
 258  */
 259 static bool
 260 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 261 {
 262         struct sk_buff *p;
 263         struct sk_buff *head = NULL;
 264         struct sk_buff *tail = NULL;
 265         uint n = 0;
 266         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 267         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 268
 269         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
 270         /* gather received frames */
 271         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 272
 273                 if (!tail)
 274                         head = tail = p;
 275                 else {
 276                         tail->prev = p;
 277                         tail = p;
 278                 }
 279
 280                 /* !give others some time to run! */
 281                 if (++n >= bound_limit)
 282                         break;
 283         }
 284
 285         /* post more rbufs */
 286         dma_rxfill(wlc_hw->di[fifo]);
 287
 288         /* process each frame */
 289         while ((p = head) != NULL) {
 290                 head = head->prev;
 291                 p->prev = NULL;
 292
 293                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 294
 295                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 296                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 297
 298                 wlc_recv(wlc_hw->wlc, p);
 299         }
 300
 301         return n >= bound_limit;
 302 }
 303
 304 /* second-level interrupt processing
 305  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 306  *   Param 'bounded' indicates if applicable loops should be bounded.
 307  */
 308 bool wlc_dpc(struct wlc_info *wlc, bool bounded)
 309 {
 310         u32 macintstatus;
 311         struct wlc_hw_info *wlc_hw = wlc->hw;
 312         d11regs_t *regs = wlc_hw->regs;
 313         bool fatal = false;
 314         struct wiphy *wiphy = wlc->wiphy;
 315
 316         if (DEVICEREMOVED(wlc)) {
 317                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
 318                           __func__);
 319                 wl_down(wlc->wl);
 320                 return false;
 321         }
 322
 323         /* grab and clear the saved software intstatus bits */
 324         macintstatus = wlc->macintstatus;
 325         wlc->macintstatus = 0;
 326
 327         BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
 328                wlc_hw->unit, macintstatus);
 329
 330         WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
 331
 332         /* BCN template is available */
 333         /* ZZZ: Use AP_ACTIVE ? */
 334         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
 335             && (macintstatus & MI_BCNTPL)) {
 336                 wlc_update_beacon(wlc);
 337         }
 338
 339         /* PMQ entry addition */
 340         if (macintstatus & MI_PMQ) {
 341         }
 342
 343         /* tx status */
 344         if (macintstatus & MI_TFS) {
 345                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 346                         wlc->macintstatus |= MI_TFS;
 347                 if (fatal) {
 348                         wiphy_err(wiphy, "MI_TFS: fatal\n");
 349                         goto fatal;
 350                 }
 351         }
 352
 353         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 354                 wlc_tbtt(wlc, regs);
 355
 356         /* ATIM window end */
 357         if (macintstatus & MI_ATIMWINEND) {
 358                 BCMMSG(wlc->wiphy, "end of ATIM window\n");
 359                 OR_REG(&regs->maccommand, wlc->qvalid);
 360                 wlc->qvalid = 0;
 361         }
 362
 363         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 364         if (macintstatus & MI_DMAINT) {
 365                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 366                         wlc->macintstatus |= MI_DMAINT;
 367                 }
 368         }
 369
 370         /* TX FIFO suspend/flush completion */
 371         if (macintstatus & MI_TXSTOP) {
 372                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 373                         /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
 374                 }
 375         }
 376
 377         /* noise sample collected */
 378         if (macintstatus & MI_BG_NOISE) {
 379                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 380         }
 381
 382         if (macintstatus & MI_GP0) {
 383                 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
 384                         "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
 385
 386                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 387                                         __func__, wlc_hw->sih->chip,
 388                                         wlc_hw->sih->chiprev);
 389                 /* big hammer */
 390                 wl_init(wlc->wl);
 391         }
 392
 393         /* gptimer timeout */
 394         if (macintstatus & MI_TO) {
 395                 W_REG(&regs->gptimer, 0);
 396         }
 397
 398         if (macintstatus & MI_RFDISABLE) {
 399                 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
 400                        " RF Disable Input\n", wlc_hw->unit);
 401                 wl_rfkill_set_hw_state(wlc->wl);
 402         }
 403
 404         /* send any enq'd tx packets. Just makes sure to jump start tx */
 405         if (!pktq_empty(&wlc->pkt_queue->q))
 406                 wlc_send_q(wlc);
 407
 408         /* it isn't done and needs to be resched if macintstatus is non-zero */
 409         return wlc->macintstatus != 0;
 410
 411  fatal:
 412         wl_init(wlc->wl);
 413         return wlc->macintstatus != 0;
 414 }
 415
 416 /* common low-level watchdog code */
 417 void wlc_bmac_watchdog(void *arg)
 418 {
 419         struct wlc_info *wlc = (struct wlc_info *) arg;
 420         struct wlc_hw_info *wlc_hw = wlc->hw;
 421
 422         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 423
 424         if (!wlc_hw->up)
 425                 return;
 426
 427         /* increment second count */
 428         wlc_hw->now++;
 429
 430         /* Check for FIFO error interrupts */
 431         wlc_bmac_fifoerrors(wlc_hw);
 432
 433         /* make sure RX dma has buffers */
 434         dma_rxfill(wlc->hw->di[RX_FIFO]);
 435
 436         wlc_phy_watchdog(wlc_hw->band->pi);
 437 }
 438
 439 void
 440 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 441                       bool mute, struct txpwr_limits *txpwr)
 442 {
 443         uint bandunit;
 444
 445         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
 446
 447         wlc_hw->chanspec = chanspec;
 448
 449         /* Switch bands if necessary */
 450         if (NBANDS_HW(wlc_hw) > 1) {
 451                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 452                 if (wlc_hw->band->bandunit != bandunit) {
 453                         /* wlc_bmac_setband disables other bandunit,
 454                          *  use light band switch if not up yet
 455                          */
 456                         if (wlc_hw->up) {
 457                                 wlc_phy_chanspec_radio_set(wlc_hw->
 458                                                            bandstate[bandunit]->
 459                                                            pi, chanspec);
 460                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 461                         } else {
 462                                 wlc_setxband(wlc_hw, bandunit);
 463                         }
 464                 }
 465         }
 466
 467         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 468
 469         if (!wlc_hw->up) {
 470                 if (wlc_hw->clk)
 471                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 472                                                   chanspec);
 473                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 474         } else {
 475                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 476                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 477
 478                 /* Update muting of the channel */
 479                 wlc_bmac_mute(wlc_hw, mute, 0);
 480         }
 481 }
 482
 483 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 484 {
 485         state->machwcap = wlc_hw->machwcap;
 486
 487         return 0;
 488 }
 489
 490 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 491 {
 492         uint i;
 493         char name[8];
 494         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 495         u16 pio_mhf2 = 0;
 496         struct wlc_hw_info *wlc_hw = wlc->hw;
 497         uint unit = wlc_hw->unit;
 498         wlc_tunables_t *tune = wlc->pub->tunables;
 499         struct wiphy *wiphy = wlc->wiphy;
 500
 501         /* name and offsets for dma_attach */
 502         snprintf(name, sizeof(name), "wl%d", unit);
 503
 504         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 505                 uint addrwidth;
 506                 int dma_attach_err = 0;
 507                 /* Find out the DMA addressing capability and let OS know
 508                  * All the channels within one DMA core have 'common-minimum' same
 509                  * capability
 510                  */
 511                 addrwidth =
 512                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 513
 514                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 515                         wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
 516                                   "resources failed\n", unit);
 517                         return false;
 518                 }
 519
 520                 /*
 521                  * FIFO 0
 522                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 523                  * RX: RX_FIFO (RX data packets)
 524                  */
 525                 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
 526                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 527                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 528                                            (wme ? tune->ntxd : 0), tune->nrxd,
 529                                            tune->rxbufsz, -1, tune->nrxbufpost,
 530                                            WL_HWRXOFF, &wl_msg_level);
 531                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 532
 533                 /*
 534                  * FIFO 1
 535                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 536                  *   (legacy) TX_DATA_FIFO (TX data packets)
 537                  * RX: UNUSED
 538                  */
 539                 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
 540                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 541                                            tune->ntxd, 0, 0, -1, 0, 0,
 542                                            &wl_msg_level);
 543                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 544
 545                 /*
 546                  * FIFO 2
 547                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 548                  * RX: UNUSED
 549                  */
 550                 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
 551                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 552                                            tune->ntxd, 0, 0, -1, 0, 0,
 553                                            &wl_msg_level);
 554                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 555                 /*
 556                  * FIFO 3
 557                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 558                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 559                  */
 560                 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
 561                                            DMAREG(wlc_hw, DMA_TX, 3),
 562                                            NULL, tune->ntxd, 0, 0, -1,
 563                                            0, 0, &wl_msg_level);
 564                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 565 /* Cleaner to leave this as if with AP defined */
 566
 567                 if (dma_attach_err) {
 568                         wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
 569                                   "\n", unit);
 570                         return false;
 571                 }
 572
 573                 /* get pointer to dma engine tx flow control variable */
 574                 for (i = 0; i < NFIFO; i++)
 575                         if (wlc_hw->di[i])
 576                                 wlc_hw->txavail[i] =
 577                                     (uint *) dma_getvar(wlc_hw->di[i],
 578                                                         "&txavail");
 579         }
 580
 581         /* initial ucode host flags */
 582         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 583
 584         return true;
 585 }
 586
 587 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 588 {
 589         uint j;
 590
 591         for (j = 0; j < NFIFO; j++) {
 592                 if (wlc_hw->di[j]) {
 593                         dma_detach(wlc_hw->di[j]);
 594                         wlc_hw->di[j] = NULL;
 595                 }
 596         }
 597 }
 598
 599 /* low level attach
 600  *    run backplane attach, init nvram
 601  *    run phy attach
 602  *    initialize software state for each core and band
 603  *    put the whole chip in reset(driver down state), no clock
 604  */
 605 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 606                     bool piomode, void *regsva, uint bustype, void *btparam)
 607 {
 608         struct wlc_hw_info *wlc_hw;
 609         d11regs_t *regs;
 610         char *macaddr = NULL;
 611         char *vars;
 612         uint err = 0;
 613         uint j;
 614         bool wme = false;
 615         shared_phy_params_t sha_params;
 616         struct wiphy *wiphy = wlc->wiphy;
 617
 618         BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
 619                 device);
 620
 621         wme = true;
 622
 623         wlc_hw = wlc->hw;
 624         wlc_hw->wlc = wlc;
 625         wlc_hw->unit = unit;
 626         wlc_hw->band = wlc_hw->bandstate[0];
 627         wlc_hw->_piomode = piomode;
 628
 629         /* populate struct wlc_hw_info with default values  */
 630         wlc_bmac_info_init(wlc_hw);
 631
 632         /*
 633          * Do the hardware portion of the attach.
 634          * Also initialize software state that depends on the particular hardware
 635          * we are running.
 636          */
 637         wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
 638                                 &wlc_hw->vars, &wlc_hw->vars_size);
 639         if (wlc_hw->sih == NULL) {
 640                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
 641                           unit);
 642                 err = 11;
 643                 goto fail;
 644         }
 645         vars = wlc_hw->vars;
 646
 647         /*
 648          * Get vendid/devid nvram overwrites, which could be different
 649          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 650          * SDIO_BUS, and SROMless devices on PCI_BUS.
 651          */
 652 #ifdef BCMBUSTYPE
 653         bustype = BCMBUSTYPE;
 654 #endif
 655         if (bustype != SI_BUS) {
 656                 char *var;
 657
 658                 var = getvar(vars, "vendid");
 659                 if (var) {
 660                         vendor = (u16) simple_strtoul(var, NULL, 0);
 661                         wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
 662                                   vendor);
 663                 }
 664                 var = getvar(vars, "devid");
 665                 if (var) {
 666                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 667                         if (devid != 0xffff) {
 668                                 device = devid;
 669                                 wiphy_err(wiphy, "Overriding device id = 0x%x"
 670                                           "\n", device);
 671                         }
 672                 }
 673
 674                 /* verify again the device is supported */
 675                 if (!wlc_chipmatch(vendor, device)) {
 676                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
 677                                 "vendor/device (0x%x/0x%x)\n",
 678                                  unit, vendor, device);
 679                         err = 12;
 680                         goto fail;
 681                 }
 682         }
 683
 684         wlc_hw->vendorid = vendor;
 685         wlc_hw->deviceid = device;
 686
 687         /* set bar0 window to point at D11 core */
 688         wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 689         wlc_hw->corerev = ai_corerev(wlc_hw->sih);
 690
 691         regs = wlc_hw->regs;
 692
 693         wlc->regs = wlc_hw->regs;
 694
 695         /* validate chip, chiprev and corerev */
 696         if (!wlc_isgoodchip(wlc_hw)) {
 697                 err = 13;
 698                 goto fail;
 699         }
 700
 701         /* initialize power control registers */
 702         ai_clkctl_init(wlc_hw->sih);
 703
 704         /* request fastclock and force fastclock for the rest of attach
 705          * bring the d11 core out of reset.
 706          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 707          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 708          */
 709         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 710         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 711
 712         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 713                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
 714                         "failed\n", unit);
 715                 err = 14;
 716                 goto fail;
 717         }
 718
 719         /* get the board rev, used just below */
 720         j = getintvar(vars, "boardrev");
 721         /* promote srom boardrev of 0xFF to 1 */
 722         if (j == BOARDREV_PROMOTABLE)
 723                 j = BOARDREV_PROMOTED;
 724         wlc_hw->boardrev = (u16) j;
 725         if (!wlc_validboardtype(wlc_hw)) {
 726                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
 727                         "board type (0x%x)" " or revision level (0x%x)\n",
 728                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 729                 err = 15;
 730                 goto fail;
 731         }
 732         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 733         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 734         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 735
 736         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 737                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 738
 739         if ((wlc_hw->sih->bustype == PCI_BUS)
 740             && (ai_pci_war16165(wlc_hw->sih)))
 741                 wlc->war16165 = true;
 742
 743         /* check device id(srom, nvram etc.) to set bands */
 744         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 745                 /* Dualband boards */
 746                 wlc_hw->_nbands = 2;
 747         } else
 748                 wlc_hw->_nbands = 1;
 749
 750         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 751                 wlc_hw->_nbands = 1;
 752
 753         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 754          * init of these values
 755          */
 756         wlc->vendorid = wlc_hw->vendorid;
 757         wlc->deviceid = wlc_hw->deviceid;
 758         wlc->pub->sih = wlc_hw->sih;
 759         wlc->pub->corerev = wlc_hw->corerev;
 760         wlc->pub->sromrev = wlc_hw->sromrev;
 761         wlc->pub->boardrev = wlc_hw->boardrev;
 762         wlc->pub->boardflags = wlc_hw->boardflags;
 763         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 764         wlc->pub->_nbands = wlc_hw->_nbands;
 765
 766         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 767
 768         if (wlc_hw->physhim == NULL) {
 769                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
 770                         "failed\n", unit);
 771                 err = 25;
 772                 goto fail;
 773         }
 774
 775         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 776         sha_params.sih = wlc_hw->sih;
 777         sha_params.physhim = wlc_hw->physhim;
 778         sha_params.unit = unit;
 779         sha_params.corerev = wlc_hw->corerev;
 780         sha_params.vars = vars;
 781         sha_params.vid = wlc_hw->vendorid;
 782         sha_params.did = wlc_hw->deviceid;
 783         sha_params.chip = wlc_hw->sih->chip;
 784         sha_params.chiprev = wlc_hw->sih->chiprev;
 785         sha_params.chippkg = wlc_hw->sih->chippkg;
 786         sha_params.sromrev = wlc_hw->sromrev;
 787         sha_params.boardtype = wlc_hw->sih->boardtype;
 788         sha_params.boardrev = wlc_hw->boardrev;
 789         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 790         sha_params.boardflags = wlc_hw->boardflags;
 791         sha_params.boardflags2 = wlc_hw->boardflags2;
 792         sha_params.bustype = wlc_hw->sih->bustype;
 793         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 794
 795         /* alloc and save pointer to shared phy state area */
 796         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 797         if (!wlc_hw->phy_sh) {
 798                 err = 16;
 799                 goto fail;
 800         }
 801
 802         /* initialize software state for each core and band */
 803         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 804                 /*
 805                  * band0 is always 2.4Ghz
 806                  * band1, if present, is 5Ghz
 807                  */
 808
 809                 /* So if this is a single band 11a card, use band 1 */
 810                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 811                         j = BAND_5G_INDEX;
 812
 813                 wlc_setxband(wlc_hw, j);
 814
 815                 wlc_hw->band->bandunit = j;
 816                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 817                 wlc->band->bandunit = j;
 818                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 819                 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
 820
 821                 wlc_hw->machwcap = R_REG(&regs->machwcap);
 822                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 823
 824                 /* init tx fifo size */
 825                 wlc_hw->xmtfifo_sz =
 826                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 827
 828                 /* Get a phy for this band */
 829                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 830                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
 831                         wlc->wiphy);
 832                 if (wlc_hw->band->pi == NULL) {
 833                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
 834                                   "attach failed\n", unit);
 835                         err = 17;
 836                         goto fail;
 837                 }
 838
 839                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 840
 841                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 842                                        &wlc_hw->band->phyrev,
 843                                        &wlc_hw->band->radioid,
 844                                        &wlc_hw->band->radiorev);
 845                 wlc_hw->band->abgphy_encore =
 846                     wlc_phy_get_encore(wlc_hw->band->pi);
 847                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 848                 wlc_hw->band->core_flags =
 849                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 850
 851                 /* verify good phy_type & supported phy revision */
 852                 if (WLCISNPHY(wlc_hw->band)) {
 853                         if (NCONF_HAS(wlc_hw->band->phyrev))
 854                                 goto good_phy;
 855                         else
 856                                 goto bad_phy;
 857                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 858                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 859                                 goto good_phy;
 860                         else
 861                                 goto bad_phy;
 862                 } else {
 863  bad_phy:
 864                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
 865                                   "phy type/rev (%d/%d)\n", unit,
 866                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
 867                         err = 18;
 868                         goto fail;
 869                 }
 870
 871  good_phy:
 872                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 873                  * high level attach. However we can not make that change until all low level access
 874                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 875                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 876                  * low only init when all fns updated.
 877                  */
 878                 wlc->band->pi = wlc_hw->band->pi;
 879                 wlc->band->phytype = wlc_hw->band->phytype;
 880                 wlc->band->phyrev = wlc_hw->band->phyrev;
 881                 wlc->band->radioid = wlc_hw->band->radioid;
 882                 wlc->band->radiorev = wlc_hw->band->radiorev;
 883
 884                 /* default contention windows size limits */
 885                 wlc_hw->band->CWmin = APHY_CWMIN;
 886                 wlc_hw->band->CWmax = PHY_CWMAX;
 887
 888                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 889                         err = 19;
 890                         goto fail;
 891                 }
 892         }
 893
 894         /* disable core to match driver "down" state */
 895         wlc_coredisable(wlc_hw);
 896
 897         /* Match driver "down" state */
 898         if (wlc_hw->sih->bustype == PCI_BUS)
 899                 ai_pci_down(wlc_hw->sih);
 900
 901         /* register sb interrupt callback functions */
 902         ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 903                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 904
 905         /* turn off pll and xtal to match driver "down" state */
 906         wlc_bmac_xtal(wlc_hw, OFF);
 907
 908         /* *********************************************************************
 909          * The hardware is in the DOWN state at this point. D11 core
 910          * or cores are in reset with clocks off, and the board PLLs
 911          * are off if possible.
 912          *
 913          * Beyond this point, wlc->sbclk == false and chip registers
 914          * should not be touched.
 915          *********************************************************************
 916          */
 917
 918         /* init etheraddr state variables */
 919         macaddr = wlc_get_macaddr(wlc_hw);
 920         if (macaddr == NULL) {
 921                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
 922                           unit);
 923                 err = 21;
 924                 goto fail;
 925         }
 926         bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
 927         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 928             is_zero_ether_addr(wlc_hw->etheraddr)) {
 929                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
 930                           unit, macaddr);
 931                 err = 22;
 932                 goto fail;
 933         }
 934
 935         BCMMSG(wlc->wiphy,
 936                  "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 937                  wlc_hw->deviceid, wlc_hw->_nbands,
 938                  wlc_hw->sih->boardtype, macaddr);
 939
 940         return err;
 941
 942  fail:
 943         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
 944                   err);
 945         return err;
 946 }
 947
 948 /*
 949  * Initialize wlc_info default values ...
 950  * may get overrides later in this function
 951  *  BMAC_NOTES, move low out and resolve the dangling ones
 952  */
 953 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
 954 {
 955         struct wlc_info *wlc = wlc_hw->wlc;
 956
 957         /* set default sw macintmask value */
 958         wlc->defmacintmask = DEF_MACINTMASK;
 959
 960         /* various 802.11g modes */
 961         wlc_hw->shortslot = false;
 962
 963         wlc_hw->SFBL = RETRY_SHORT_FB;
 964         wlc_hw->LFBL = RETRY_LONG_FB;
 965
 966         /* default mac retry limits */
 967         wlc_hw->SRL = RETRY_SHORT_DEF;
 968         wlc_hw->LRL = RETRY_LONG_DEF;
 969         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
 970 }
 971
 972 /*
 973  * low level detach
 974  */
 975 int wlc_bmac_detach(struct wlc_info *wlc)
 976 {
 977         uint i;
 978         struct wlc_hwband *band;
 979         struct wlc_hw_info *wlc_hw = wlc->hw;
 980         int callbacks;
 981
 982         callbacks = 0;
 983
 984         if (wlc_hw->sih) {
 985                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
 986                  * interrupt object may has been freed. this must be done before sb core switch
 987                  */
 988                 ai_deregister_intr_callback(wlc_hw->sih);
 989
 990                 if (wlc_hw->sih->bustype == PCI_BUS)
 991                         ai_pci_sleep(wlc_hw->sih);
 992         }
 993
 994         wlc_bmac_detach_dmapio(wlc_hw);
 995
 996         band = wlc_hw->band;
 997         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
 998                 if (band->pi) {
 999                         /* Detach this band's phy */
1000                         wlc_phy_detach(band->pi);
1001                         band->pi = NULL;
1002                 }
1003                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1004         }
1005
1006         /* Free shared phy state */
1007         wlc_phy_shared_detach(wlc_hw->phy_sh);
1008
1009         wlc_phy_shim_detach(wlc_hw->physhim);
1010
1011         /* free vars */
1012         kfree(wlc_hw->vars);
1013         wlc_hw->vars = NULL;
1014
1015         if (wlc_hw->sih) {
1016                 ai_detach(wlc_hw->sih);
1017                 wlc_hw->sih = NULL;
1018         }
1019
1020         return callbacks;
1021
1022 }
1023
1024 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1025 {
1026         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1027
1028         /* reset the core */
1029         if (!DEVICEREMOVED(wlc_hw->wlc))
1030                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1031
1032         /* purge the dma rings */
1033         wlc_flushqueues(wlc_hw->wlc);
1034
1035         wlc_reset_bmac_done(wlc_hw->wlc);
1036 }
1037
1038 void
1039 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1040                           bool mute) {
1041         u32 macintmask;
1042         bool fastclk;
1043         struct wlc_info *wlc = wlc_hw->wlc;
1044
1045         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1046
1047         /* request FAST clock if not on */
1048         fastclk = wlc_hw->forcefastclk;
1049         if (!fastclk)
1050                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1051
1052         /* disable interrupts */
1053         macintmask = wl_intrsoff(wlc->wl);
1054
1055         /* set up the specified band and chanspec */
1056         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1057         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1058
1059         /* do one-time phy inits and calibration */
1060         wlc_phy_cal_init(wlc_hw->band->pi);
1061
1062         /* core-specific initialization */
1063         wlc_coreinit(wlc);
1064
1065         /* suspend the tx fifos and mute the phy for preism cac time */
1066         if (mute)
1067                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1068
1069         /* band-specific inits */
1070         wlc_bmac_bsinit(wlc, chanspec);
1071
1072         /* restore macintmask */
1073         wl_intrsrestore(wlc->wl, macintmask);
1074
1075         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1076          * and wlc_enable_mac() will clear this override bit.
1077          */
1078         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1079
1080         /*
1081          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1082          */
1083         wlc_hw->mac_suspend_depth = 1;
1084
1085         /* restore the clk */
1086         if (!fastclk)
1087                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1088 }
1089
1090 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1091 {
1092         uint coremask;
1093
1094         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1095
1096         /*
1097          * Enable pll and xtal, initialize the power control registers,
1098          * and force fastclock for the remainder of wlc_up().
1099          */
1100         wlc_bmac_xtal(wlc_hw, ON);
1101         ai_clkctl_init(wlc_hw->sih);
1102         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1103
1104         /*
1105          * Configure pci/pcmcia here instead of in wlc_attach()
1106          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1107          */
1108         coremask = (1 << wlc_hw->wlc->core->coreidx);
1109
1110         if (wlc_hw->sih->bustype == PCI_BUS)
1111                 ai_pci_setup(wlc_hw->sih, coremask);
1112
1113         /*
1114          * Need to read the hwradio status here to cover the case where the system
1115          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1116          */
1117         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1118                 /* put SB PCI in down state again */
1119                 if (wlc_hw->sih->bustype == PCI_BUS)
1120                         ai_pci_down(wlc_hw->sih);
1121                 wlc_bmac_xtal(wlc_hw, OFF);
1122                 return -ENOMEDIUM;
1123         }
1124
1125         if (wlc_hw->sih->bustype == PCI_BUS)
1126                 ai_pci_up(wlc_hw->sih);
1127
1128         /* reset the d11 core */
1129         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1130
1131         return 0;
1132 }
1133
1134 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1135 {
1136         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1137
1138         wlc_hw->up = true;
1139         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1140
1141         /* FULLY enable dynamic power control and d11 core interrupt */
1142         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1143         wl_intrson(wlc_hw->wlc->wl);
1144         return 0;
1145 }
1146
1147 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1148 {
1149         bool dev_gone;
1150         uint callbacks = 0;
1151
1152         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1153
1154         if (!wlc_hw->up)
1155                 return callbacks;
1156
1157         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1158
1159         /* disable interrupts */
1160         if (dev_gone)
1161                 wlc_hw->wlc->macintmask = 0;
1162         else {
1163                 /* now disable interrupts */
1164                 wl_intrsoff(wlc_hw->wlc->wl);
1165
1166                 /* ensure we're running on the pll clock again */
1167                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1168         }
1169         /* down phy at the last of this stage */
1170         callbacks += wlc_phy_down(wlc_hw->band->pi);
1171
1172         return callbacks;
1173 }
1174
1175 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1176 {
1177         uint callbacks = 0;
1178         bool dev_gone;
1179
1180         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1181
1182         if (!wlc_hw->up)
1183                 return callbacks;
1184
1185         wlc_hw->up = false;
1186         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1187
1188         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1189
1190         if (dev_gone) {
1191                 wlc_hw->sbclk = false;
1192                 wlc_hw->clk = false;
1193                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1194
1195                 /* reclaim any posted packets */
1196                 wlc_flushqueues(wlc_hw->wlc);
1197         } else {
1198
1199                 /* Reset and disable the core */
1200                 if (ai_iscoreup(wlc_hw->sih)) {
1201                         if (R_REG(&wlc_hw->regs->maccontrol) &
1202                             MCTL_EN_MAC)
1203                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1204                         callbacks += wl_reset(wlc_hw->wlc->wl);
1205                         wlc_coredisable(wlc_hw);
1206                 }
1207
1208                 /* turn off primary xtal and pll */
1209                 if (!wlc_hw->noreset) {
1210                         if (wlc_hw->sih->bustype == PCI_BUS)
1211                                 ai_pci_down(wlc_hw->sih);
1212                         wlc_bmac_xtal(wlc_hw, OFF);
1213                 }
1214         }
1215
1216         return callbacks;
1217 }
1218
1219 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1220 {
1221         /* delay before first read of ucode state */
1222         udelay(40);
1223
1224         /* wait until ucode is no longer asleep */
1225         SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1226                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1227 }
1228
1229 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1230 {
1231         memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1232 }
1233
1234 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1235 {
1236         return wlc_hw->band->bandtype;
1237 }
1238
1239 /* control chip clock to save power, enable dynamic clock or force fast clock */
1240 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1241 {
1242         if (PMUCTL_ENAB(wlc_hw->sih)) {
1243                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1244                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1245                  *      which means the FCA bit may not be set.
1246                  *      should wakeup mac if driver wants it to run on HT.
1247                  */
1248
1249                 if (wlc_hw->clk) {
1250                         if (mode == CLK_FAST) {
1251                                 OR_REG(&wlc_hw->regs->clk_ctl_st,
1252                                        CCS_FORCEHT);
1253
1254                                 udelay(64);
1255
1256                                 SPINWAIT(((R_REG
1257                                            (&wlc_hw->regs->
1258                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1259                                          PMU_MAX_TRANSITION_DLY);
1260                                 WARN_ON(!(R_REG
1261                                           (&wlc_hw->regs->
1262                                            clk_ctl_st) & CCS_HTAVAIL));
1263                         } else {
1264                                 if ((wlc_hw->sih->pmurev == 0) &&
1265                                     (R_REG
1266                                      (&wlc_hw->regs->
1267                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1268                                         SPINWAIT(((R_REG
1269                                                    (&wlc_hw->regs->
1270                                                     clk_ctl_st) & CCS_HTAVAIL)
1271                                                   == 0),
1272                                                  PMU_MAX_TRANSITION_DLY);
1273                                 AND_REG(&wlc_hw->regs->clk_ctl_st,
1274                                         ~CCS_FORCEHT);
1275                         }
1276                 }
1277                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1278         } else {
1279
1280                 /* old chips w/o PMU, force HT through cc,
1281                  * then use FCA to verify mac is running fast clock
1282                  */
1283
1284                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1285
1286                 /* check fast clock is available (if core is not in reset) */
1287                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1288                         WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1289                                   SISF_FCLKA));
1290
1291                 /* keep the ucode wake bit on if forcefastclk is on
1292                  * since we do not want ucode to put us back to slow clock
1293                  * when it dozes for PM mode.
1294                  * Code below matches the wake override bit with current forcefastclk state
1295                  * Only setting bit in wake_override instead of waking ucode immediately
1296                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1297                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1298                  * (protected by an up check) was executed just below.
1299                  */
1300                 if (wlc_hw->forcefastclk)
1301                         mboolset(wlc_hw->wake_override,
1302                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1303                 else
1304                         mboolclr(wlc_hw->wake_override,
1305                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1306         }
1307 }
1308
1309 /* set initial host flags value */
1310 static void
1311 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1312 {
1313         struct wlc_hw_info *wlc_hw = wlc->hw;
1314
1315         memset(mhfs, 0, MHFMAX * sizeof(u16));
1316
1317         mhfs[MHF2] |= mhf2_init;
1318
1319         /* prohibit use of slowclock on multifunction boards */
1320         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1321                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1322
1323         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1324                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1325                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1326         }
1327 }
1328
1329 /* set or clear ucode host flag bits
1330  * it has an optimization for no-change write
1331  * it only writes through shared memory when the core has clock;
1332  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1333  *
1334  *
1335  * bands values are: WLC_BAND_AUTO <--- Current band only
1336  *                   WLC_BAND_5G   <--- 5G band only
1337  *                   WLC_BAND_2G   <--- 2G band only
1338  *                   WLC_BAND_ALL  <--- All bands
1339  */
1340 void
1341 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1342              int bands)
1343 {
1344         u16 save;
1345         u16 addr[MHFMAX] = {
1346                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1347                 M_HOST_FLAGS5
1348         };
1349         struct wlc_hwband *band;
1350
1351         if ((val & ~mask) || idx >= MHFMAX)
1352                 return; /* error condition */
1353
1354         switch (bands) {
1355                 /* Current band only or all bands,
1356                  * then set the band to current band
1357                  */
1358         case WLC_BAND_AUTO:
1359         case WLC_BAND_ALL:
1360                 band = wlc_hw->band;
1361                 break;
1362         case WLC_BAND_5G:
1363                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1364                 break;
1365         case WLC_BAND_2G:
1366                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1367                 break;
1368         default:
1369                 band = NULL;    /* error condition */
1370         }
1371
1372         if (band) {
1373                 save = band->mhfs[idx];
1374                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1375
1376                 /* optimization: only write through if changed, and
1377                  * changed band is the current band
1378                  */
1379                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1380                     && (band == wlc_hw->band))
1381                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1382                                            (u16) band->mhfs[idx]);
1383         }
1384
1385         if (bands == WLC_BAND_ALL) {
1386                 wlc_hw->bandstate[0]->mhfs[idx] =
1387                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1388                 wlc_hw->bandstate[1]->mhfs[idx] =
1389                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1390         }
1391 }
1392
1393 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1394 {
1395         struct wlc_hwband *band;
1396
1397         if (idx >= MHFMAX)
1398                 return 0; /* error condition */
1399         switch (bands) {
1400         case WLC_BAND_AUTO:
1401                 band = wlc_hw->band;
1402                 break;
1403         case WLC_BAND_5G:
1404                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1405                 break;
1406         case WLC_BAND_2G:
1407                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1408                 break;
1409         default:
1410                 band = NULL;            /* error condition */
1411         }
1412
1413         if (!band)
1414                 return 0;
1415
1416         return band->mhfs[idx];
1417 }
1418
1419 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1420 {
1421         u8 idx;
1422         u16 addr[] = {
1423                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1424                 M_HOST_FLAGS5
1425         };
1426
1427         for (idx = 0; idx < MHFMAX; idx++) {
1428                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1429         }
1430 }
1431
1432 /* set the maccontrol register to desired reset state and
1433  * initialize the sw cache of the register
1434  */
1435 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1436 {
1437         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1438         wlc_hw->maccontrol = 0;
1439         wlc_hw->suspended_fifos = 0;
1440         wlc_hw->wake_override = 0;
1441         wlc_hw->mute_override = 0;
1442         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1443 }
1444
1445 /* set or clear maccontrol bits */
1446 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1447 {
1448         u32 maccontrol;
1449         u32 new_maccontrol;
1450
1451         if (val & ~mask)
1452                 return; /* error condition */
1453         maccontrol = wlc_hw->maccontrol;
1454         new_maccontrol = (maccontrol & ~mask) | val;
1455
1456         /* if the new maccontrol value is the same as the old, nothing to do */
1457         if (new_maccontrol == maccontrol)
1458                 return;
1459
1460         /* something changed, cache the new value */
1461         wlc_hw->maccontrol = new_maccontrol;
1462
1463         /* write the new values with overrides applied */
1464         wlc_mctrl_write(wlc_hw);
1465 }
1466
1467 /* write the software state of maccontrol and overrides to the maccontrol register */
1468 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1469 {
1470         u32 maccontrol = wlc_hw->maccontrol;
1471
1472         /* OR in the wake bit if overridden */
1473         if (wlc_hw->wake_override)
1474                 maccontrol |= MCTL_WAKE;
1475
1476         /* set AP and INFRA bits for mute if needed */
1477         if (wlc_hw->mute_override) {
1478                 maccontrol &= ~(MCTL_AP);
1479                 maccontrol |= MCTL_INFRA;
1480         }
1481
1482         W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1483 }
1484
1485 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1486 {
1487         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1488                 mboolset(wlc_hw->wake_override, override_bit);
1489                 return;
1490         }
1491
1492         mboolset(wlc_hw->wake_override, override_bit);
1493
1494         wlc_mctrl_write(wlc_hw);
1495         wlc_bmac_wait_for_wake(wlc_hw);
1496
1497         return;
1498 }
1499
1500 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1501 {
1502         mboolclr(wlc_hw->wake_override, override_bit);
1503
1504         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1505                 return;
1506
1507         wlc_mctrl_write(wlc_hw);
1508
1509         return;
1510 }
1511
1512 /* When driver needs ucode to stop beaconing, it has to make sure that
1513  * MCTL_AP is clear and MCTL_INFRA is set
1514  * Mode           MCTL_AP        MCTL_INFRA
1515  * AP                1              1
1516  * STA               0              1 <--- This will ensure no beacons
1517  * IBSS              0              0
1518  */
1519 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1520 {
1521         wlc_hw->mute_override = 1;
1522
1523         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1524          * override, then there is no change to write
1525          */
1526         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1527                 return;
1528
1529         wlc_mctrl_write(wlc_hw);
1530
1531         return;
1532 }
1533
1534 /* Clear the override on AP and INFRA bits */
1535 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1536 {
1537         if (wlc_hw->mute_override == 0)
1538                 return;
1539
1540         wlc_hw->mute_override = 0;
1541
1542         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1543          * override, then there is no change to write
1544          */
1545         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1546                 return;
1547
1548         wlc_mctrl_write(wlc_hw);
1549 }
1550
1551 /*
1552  * Write a MAC address to the given match reg offset in the RXE match engine.
1553  */
1554 void
1555 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1556                        const u8 *addr)
1557 {
1558         d11regs_t *regs;
1559         u16 mac_l;
1560         u16 mac_m;
1561         u16 mac_h;
1562
1563         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
1564                  wlc_hw->unit);
1565
1566         regs = wlc_hw->regs;
1567         mac_l = addr[0] | (addr[1] << 8);
1568         mac_m = addr[2] | (addr[3] << 8);
1569         mac_h = addr[4] | (addr[5] << 8);
1570
1571         /* enter the MAC addr into the RXE match registers */
1572         W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1573         W_REG(&regs->rcm_mat_data, mac_l);
1574         W_REG(&regs->rcm_mat_data, mac_m);
1575         W_REG(&regs->rcm_mat_data, mac_h);
1576
1577 }
1578
1579 void
1580 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1581                             void *buf)
1582 {
1583         d11regs_t *regs;
1584         u32 word;
1585         bool be_bit;
1586         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1587
1588         regs = wlc_hw->regs;
1589         W_REG(&regs->tplatewrptr, offset);
1590
1591         /* if MCTL_BIGEND bit set in mac control register,
1592          * the chip swaps data in fifo, as well as data in
1593          * template ram
1594          */
1595         be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1596
1597         while (len > 0) {
1598                 memcpy(&word, buf, sizeof(u32));
1599
1600                 if (be_bit)
1601                         word = cpu_to_be32(word);
1602                 else
1603                         word = cpu_to_le32(word);
1604
1605                 W_REG(&regs->tplatewrdata, word);
1606
1607                 buf = (u8 *) buf + sizeof(u32);
1608                 len -= sizeof(u32);
1609         }
1610 }
1611
1612 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1613 {
1614         wlc_hw->band->CWmin = newmin;
1615
1616         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1617         (void)R_REG(&wlc_hw->regs->objaddr);
1618         W_REG(&wlc_hw->regs->objdata, newmin);
1619 }
1620
1621 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1622 {
1623         wlc_hw->band->CWmax = newmax;
1624
1625         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1626         (void)R_REG(&wlc_hw->regs->objaddr);
1627         W_REG(&wlc_hw->regs->objdata, newmax);
1628 }
1629
1630 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1631 {
1632         bool fastclk;
1633
1634         /* request FAST clock if not on */
1635         fastclk = wlc_hw->forcefastclk;
1636         if (!fastclk)
1637                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1638
1639         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1640
1641         wlc_bmac_phy_reset(wlc_hw);
1642         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1643
1644         /* restore the clk */
1645         if (!fastclk)
1646                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1647 }
1648
1649 static void
1650 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1651 {
1652         d11regs_t *regs = wlc_hw->regs;
1653
1654         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1655                                     bcn);
1656         /* write beacon length to SCR */
1657         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1658         /* mark beacon0 valid */
1659         OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1660 }
1661
1662 static void
1663 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1664 {
1665         d11regs_t *regs = wlc_hw->regs;
1666
1667         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1668                                     bcn);
1669         /* write beacon length to SCR */
1670         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1671         /* mark beacon1 valid */
1672         OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1673 }
1674
1675 /* mac is assumed to be suspended at this point */
1676 void
1677 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1678                                bool both)
1679 {
1680         d11regs_t *regs = wlc_hw->regs;
1681
1682         if (both) {
1683                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1684                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1685         } else {
1686                 /* bcn 0 */
1687                 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1688                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1689                 /* bcn 1 */
1690                 else if (!
1691                          (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1692                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1693         }
1694 }
1695
1696 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1697 {
1698         u16 v;
1699         struct wlc_info *wlc = wlc_hw->wlc;
1700         /* update SYNTHPU_DLY */
1701
1702         if (WLCISLCNPHY(wlc->band)) {
1703                 v = SYNTHPU_DLY_LPPHY_US;
1704         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1705                 v = SYNTHPU_DLY_NPHY_US;
1706         } else {
1707                 v = SYNTHPU_DLY_BPHY_US;
1708         }
1709
1710         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1711 }
1712
1713 /* band-specific init */
1714 static void
1715 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1716 {
1717         struct wlc_hw_info *wlc_hw = wlc->hw;
1718
1719         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1720                 wlc_hw->band->bandunit);
1721
1722         wlc_ucode_bsinit(wlc_hw);
1723
1724         wlc_phy_init(wlc_hw->band->pi, chanspec);
1725
1726         wlc_ucode_txant_set(wlc_hw);
1727
1728         /* cwmin is band-specific, update hardware with value for current band */
1729         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1730         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1731
1732         wlc_bmac_update_slot_timing(wlc_hw,
1733                                     BAND_5G(wlc_hw->band->
1734                                             bandtype) ? true : wlc_hw->
1735                                     shortslot);
1736
1737         /* write phytype and phyvers */
1738         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1739         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1740
1741         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1742         wlc_upd_ofdm_pctl1_table(wlc_hw);
1743
1744         wlc_bmac_upd_synthpu(wlc_hw);
1745 }
1746
1747 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1748 {
1749         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1750
1751         wlc_hw->phyclk = clk;
1752
1753         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1754
1755                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1756                                (SICF_PRST | SICF_FGC));
1757                 udelay(1);
1758                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1759                 udelay(1);
1760
1761         } else {                /* take phy out of reset */
1762
1763                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1764                 udelay(1);
1765                 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1766                 udelay(1);
1767
1768         }
1769 }
1770
1771 /* Perform a soft reset of the PHY PLL */
1772 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1773 {
1774         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1775
1776         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1777                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1778         udelay(1);
1779         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1780                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1781         udelay(1);
1782         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1783                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1784         udelay(1);
1785         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1786                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1787         udelay(1);
1788 }
1789
1790 /* light way to turn on phy clock without reset for NPHY only
1791  *  refer to wlc_bmac_core_phy_clk for full version
1792  */
1793 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1794 {
1795         /* support(necessary for NPHY and HYPHY) only */
1796         if (!WLCISNPHY(wlc_hw->band))
1797                 return;
1798
1799         if (ON == clk)
1800                 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1801         else
1802                 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1803
1804 }
1805
1806 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1807 {
1808         if (ON == clk)
1809                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1810         else
1811                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1812 }
1813
1814 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1815 {
1816         wlc_phy_t *pih = wlc_hw->band->pi;
1817         u32 phy_bw_clkbits;
1818         bool phy_in_reset = false;
1819
1820         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1821
1822         if (pih == NULL)
1823                 return;
1824
1825         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1826
1827         /* Specific reset sequence required for NPHY rev 3 and 4 */
1828         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1829             NREV_LE(wlc_hw->band->phyrev, 4)) {
1830                 /* Set the PHY bandwidth */
1831                 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1832
1833                 udelay(1);
1834
1835                 /* Perform a soft reset of the PHY PLL */
1836                 wlc_bmac_core_phypll_reset(wlc_hw);
1837
1838                 /* reset the PHY */
1839                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1840                                (SICF_PRST | SICF_PCLKE));
1841                 phy_in_reset = true;
1842         } else {
1843
1844                 ai_core_cflags(wlc_hw->sih,
1845                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1846                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1847         }
1848
1849         udelay(2);
1850         wlc_bmac_core_phy_clk(wlc_hw, ON);
1851
1852         if (pih)
1853                 wlc_phy_anacore(pih, ON);
1854 }
1855
1856 /* switch to and initialize new band */
1857 static void
1858 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1859                                 chanspec_t chanspec) {
1860         struct wlc_info *wlc = wlc_hw->wlc;
1861         u32 macintmask;
1862
1863         /* Enable the d11 core before accessing it */
1864         if (!ai_iscoreup(wlc_hw->sih)) {
1865                 ai_core_reset(wlc_hw->sih, 0, 0);
1866                 wlc_mctrl_reset(wlc_hw);
1867         }
1868
1869         macintmask = wlc_setband_inact(wlc, bandunit);
1870
1871         if (!wlc_hw->up)
1872                 return;
1873
1874         wlc_bmac_core_phy_clk(wlc_hw, ON);
1875
1876         /* band-specific initializations */
1877         wlc_bmac_bsinit(wlc, chanspec);
1878
1879         /*
1880          * If there are any pending software interrupt bits,
1881          * then replace these with a harmless nonzero value
1882          * so wlc_dpc() will re-enable interrupts when done.
1883          */
1884         if (wlc->macintstatus)
1885                 wlc->macintstatus = MI_DMAINT;
1886
1887         /* restore macintmask */
1888         wl_intrsrestore(wlc->wl, macintmask);
1889
1890         /* ucode should still be suspended.. */
1891         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1892 }
1893
1894 /* low-level band switch utility routine */
1895 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1896 {
1897         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1898                 bandunit);
1899
1900         wlc_hw->band = wlc_hw->bandstate[bandunit];
1901
1902         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1903         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1904
1905         /* set gmode core flag */
1906         if (wlc_hw->sbclk && !wlc_hw->noreset) {
1907                 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1908                                ((bandunit == 0) ? SICF_GMODE : 0));
1909         }
1910 }
1911
1912 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1913 {
1914
1915         /* reject unsupported corerev */
1916         if (!VALID_COREREV(wlc_hw->corerev)) {
1917                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1918                           wlc_hw->corerev);
1919                 return false;
1920         }
1921
1922         return true;
1923 }
1924
1925 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1926 {
1927         bool goodboard = true;
1928         uint boardrev = wlc_hw->boardrev;
1929
1930         if (boardrev == 0)
1931                 goodboard = false;
1932         else if (boardrev > 0xff) {
1933                 uint brt = (boardrev & 0xf000) >> 12;
1934                 uint b0 = (boardrev & 0xf00) >> 8;
1935                 uint b1 = (boardrev & 0xf0) >> 4;
1936                 uint b2 = boardrev & 0xf;
1937
1938                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1939                     || (b2 > 9))
1940                         goodboard = false;
1941         }
1942
1943         if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1944                 return goodboard;
1945
1946         return goodboard;
1947 }
1948
1949 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1950 {
1951         const char *varname = "macaddr";
1952         char *macaddr;
1953
1954         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1955         macaddr = getvar(wlc_hw->vars, varname);
1956         if (macaddr != NULL)
1957                 return macaddr;
1958
1959         if (NBANDS_HW(wlc_hw) > 1)
1960                 varname = "et1macaddr";
1961         else
1962                 varname = "il0macaddr";
1963
1964         macaddr = getvar(wlc_hw->vars, varname);
1965         if (macaddr == NULL) {
1966                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1967                           "getvar(%s) not found\n", wlc_hw->unit, varname);
1968         }
1969
1970         return macaddr;
1971 }
1972
1973 /*
1974  * Return true if radio is disabled, otherwise false.
1975  * hw radio disable signal is an external pin, users activate it asynchronously
1976  * this function could be called when driver is down and w/o clock
1977  * it operates on different registers depending on corerev and boardflag.
1978  */
1979 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
1980 {
1981         bool v, clk, xtal;
1982         u32 resetbits = 0, flags = 0;
1983
1984         xtal = wlc_hw->sbclk;
1985         if (!xtal)
1986                 wlc_bmac_xtal(wlc_hw, ON);
1987
1988         /* may need to take core out of reset first */
1989         clk = wlc_hw->clk;
1990         if (!clk) {
1991                 /*
1992                  * mac no longer enables phyclk automatically when driver
1993                  * accesses phyreg throughput mac. This can be skipped since
1994                  * only mac reg is accessed below
1995                  */
1996                 flags |= SICF_PCLKE;
1997
1998                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1999                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2000                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2001                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2002                         wlc_hw->regs =
2003                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2004                                                      0);
2005                 ai_core_reset(wlc_hw->sih, flags, resetbits);
2006                 wlc_mctrl_reset(wlc_hw);
2007         }
2008
2009         v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2010
2011         /* put core back into reset */
2012         if (!clk)
2013                 ai_core_disable(wlc_hw->sih, 0);
2014
2015         if (!xtal)
2016                 wlc_bmac_xtal(wlc_hw, OFF);
2017
2018         return v;
2019 }
2020
2021 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2022 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2023 {
2024         if (wlc_hw->wlc->pub->hw_up)
2025                 return;
2026
2027         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2028
2029         /*
2030          * Enable pll and xtal, initialize the power control registers,
2031          * and force fastclock for the remainder of wlc_up().
2032          */
2033         wlc_bmac_xtal(wlc_hw, ON);
2034         ai_clkctl_init(wlc_hw->sih);
2035         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2036
2037         if (wlc_hw->sih->bustype == PCI_BUS) {
2038                 ai_pci_fixcfg(wlc_hw->sih);
2039
2040                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2041                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2042                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2043                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2044                         wlc_hw->regs =
2045                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2046                                                      0);
2047         }
2048
2049         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2050         wlc_phy_por_inform(wlc_hw->band->pi);
2051
2052         wlc_hw->ucode_loaded = false;
2053         wlc_hw->wlc->pub->hw_up = true;
2054
2055         if ((wlc_hw->boardflags & BFL_FEM)
2056             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2057                 if (!
2058                     (wlc_hw->boardrev >= 0x1250
2059                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2060                         ai_epa_4313war(wlc_hw->sih);
2061         }
2062 }
2063
2064 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2065 {
2066         struct hnddma_pub *di = wlc_hw->di[fifo];
2067         return dma_rxreset(di);
2068 }
2069
2070 /* d11 core reset
2071  *   ensure fask clock during reset
2072  *   reset dma
2073  *   reset d11(out of reset)
2074  *   reset phy(out of reset)
2075  *   clear software macintstatus for fresh new start
2076  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2077  */
2078 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2079 {
2080         d11regs_t *regs;
2081         uint i;
2082         bool fastclk;
2083         u32 resetbits = 0;
2084
2085         if (flags == WLC_USE_COREFLAGS)
2086                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2087
2088         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2089
2090         regs = wlc_hw->regs;
2091
2092         /* request FAST clock if not on  */
2093         fastclk = wlc_hw->forcefastclk;
2094         if (!fastclk)
2095                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2096
2097         /* reset the dma engines except first time thru */
2098         if (ai_iscoreup(wlc_hw->sih)) {
2099                 for (i = 0; i < NFIFO; i++)
2100                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2101                                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2102                                           "dma_txreset[%d]: cannot stop dma\n",
2103                                            wlc_hw->unit, __func__, i);
2104                         }
2105
2106                 if ((wlc_hw->di[RX_FIFO])
2107                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2108                         wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2109                                   "[%d]: cannot stop dma\n",
2110                                   wlc_hw->unit, __func__, RX_FIFO);
2111                 }
2112         }
2113         /* if noreset, just stop the psm and return */
2114         if (wlc_hw->noreset) {
2115                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2116                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2117                 return;
2118         }
2119
2120         /*
2121          * mac no longer enables phyclk automatically when driver accesses
2122          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2123          * band->pi is invalid. need to enable PHY CLK
2124          */
2125         flags |= SICF_PCLKE;
2126
2127         /* reset the core
2128          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2129          *  is cleared by the core_reset. have to re-request it.
2130          *  This adds some delay and we can optimize it by also requesting fastclk through
2131          *  chipcommon during this period if necessary. But that has to work coordinate
2132          *  with other driver like mips/arm since they may touch chipcommon as well.
2133          */
2134         wlc_hw->clk = false;
2135         ai_core_reset(wlc_hw->sih, flags, resetbits);
2136         wlc_hw->clk = true;
2137         if (wlc_hw->band && wlc_hw->band->pi)
2138                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2139
2140         wlc_mctrl_reset(wlc_hw);
2141
2142         if (PMUCTL_ENAB(wlc_hw->sih))
2143                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2144
2145         wlc_bmac_phy_reset(wlc_hw);
2146
2147         /* turn on PHY_PLL */
2148         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2149
2150         /* clear sw intstatus */
2151         wlc_hw->wlc->macintstatus = 0;
2152
2153         /* restore the clk setting */
2154         if (!fastclk)
2155                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2156 }
2157
2158 /* txfifo sizes needs to be modified(increased) since the newer cores
2159  * have more memory.
2160  */
2161 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2162 {
2163         d11regs_t *regs = wlc_hw->regs;
2164         u16 fifo_nu;
2165         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2166         u16 txfifo_def, txfifo_def1;
2167         u16 txfifo_cmd;
2168
2169         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2170         txfifo_startblk = TXFIFO_START_BLK;
2171
2172         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2173         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2174
2175                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2176                 txfifo_def = (txfifo_startblk & 0xff) |
2177                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2178                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2179                     ((((txfifo_endblk -
2180                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2181                 txfifo_cmd =
2182                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2183
2184                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2185                 W_REG(&regs->xmtfifodef, txfifo_def);
2186                 W_REG(&regs->xmtfifodef1, txfifo_def1);
2187
2188                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2189
2190                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2191         }
2192         /*
2193          * need to propagate to shm location to be in sync since ucode/hw won't
2194          * do this
2195          */
2196         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2197                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2198         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2199                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2200         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2201                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2202                             xmtfifo_sz[TX_AC_BK_FIFO]));
2203         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2204                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2205                             xmtfifo_sz[TX_BCMC_FIFO]));
2206 }
2207
2208 /* d11 core init
2209  *   reset PSM
2210  *   download ucode/PCM
2211  *   let ucode run to suspended
2212  *   download ucode inits
2213  *   config other core registers
2214  *   init dma
2215  */
2216 static void wlc_coreinit(struct wlc_info *wlc)
2217 {
2218         struct wlc_hw_info *wlc_hw = wlc->hw;
2219         d11regs_t *regs;
2220         u32 sflags;
2221         uint bcnint_us;
2222         uint i = 0;
2223         bool fifosz_fixup = false;
2224         int err = 0;
2225         u16 buf[NFIFO];
2226         struct wiphy *wiphy = wlc->wiphy;
2227
2228         regs = wlc_hw->regs;
2229
2230         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2231
2232         /* reset PSM */
2233         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2234
2235         wlc_ucode_download(wlc_hw);
2236         /*
2237          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2238          */
2239         fifosz_fixup = true;
2240
2241         /* let the PSM run to the suspended state, set mode to BSS STA */
2242         W_REG(&regs->macintstatus, -1);
2243         wlc_bmac_mctrl(wlc_hw, ~0,
2244                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2245
2246         /* wait for ucode to self-suspend after auto-init */
2247         SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2248                  1000 * 1000);
2249         if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2250                 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2251                           "suspend!\n", wlc_hw->unit);
2252
2253         wlc_gpio_init(wlc);
2254
2255         sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2256
2257         if (D11REV_IS(wlc_hw->corerev, 23)) {
2258                 if (WLCISNPHY(wlc_hw->band))
2259                         wlc_write_inits(wlc_hw, d11n0initvals16);
2260                 else
2261                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2262                                   " %d\n", __func__, wlc_hw->unit,
2263                                   wlc_hw->corerev);
2264         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2265                 if (WLCISLCNPHY(wlc_hw->band)) {
2266                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2267                 } else {
2268                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2269                                   " %d\n", __func__, wlc_hw->unit,
2270                                   wlc_hw->corerev);
2271                 }
2272         } else {
2273                 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2274                           __func__, wlc_hw->unit, wlc_hw->corerev);
2275         }
2276
2277         /* For old ucode, txfifo sizes needs to be modified(increased) */
2278         if (fifosz_fixup == true) {
2279                 wlc_corerev_fifofixup(wlc_hw);
2280         }
2281
2282         /* check txfifo allocations match between ucode and driver */
2283         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2284         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2285                 i = TX_AC_BE_FIFO;
2286                 err = -1;
2287         }
2288         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2289         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2290                 i = TX_AC_VI_FIFO;
2291                 err = -1;
2292         }
2293         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2294         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2295         buf[TX_AC_BK_FIFO] &= 0xff;
2296         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2297                 i = TX_AC_BK_FIFO;
2298                 err = -1;
2299         }
2300         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2301                 i = TX_AC_VO_FIFO;
2302                 err = -1;
2303         }
2304         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2305         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2306         buf[TX_BCMC_FIFO] &= 0xff;
2307         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2308                 i = TX_BCMC_FIFO;
2309                 err = -1;
2310         }
2311         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2312                 i = TX_ATIM_FIFO;
2313                 err = -1;
2314         }
2315         if (err != 0) {
2316                 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2317                           " driver size %d index %d\n", buf[i],
2318                           wlc_hw->xmtfifo_sz[i], i);
2319         }
2320
2321         /* make sure we can still talk to the mac */
2322         WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
2323
2324         /* band-specific inits done by wlc_bsinit() */
2325
2326         /* Set up frame burst size and antenna swap threshold init values */
2327         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2328         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2329
2330         /* enable one rx interrupt per received frame */
2331         W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2332
2333         /* set the station mode (BSS STA) */
2334         wlc_bmac_mctrl(wlc_hw,
2335                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2336                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2337
2338         /* set up Beacon interval */
2339         bcnint_us = 0x8000 << 10;
2340         W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2341         W_REG(&regs->tsf_cfpstart, bcnint_us);
2342         W_REG(&regs->macintstatus, MI_GP1);
2343
2344         /* write interrupt mask */
2345         W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2346
2347         /* allow the MAC to control the PHY clock (dynamic on/off) */
2348         wlc_bmac_macphyclk_set(wlc_hw, ON);
2349
2350         /* program dynamic clock control fast powerup delay register */
2351         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2352         W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2353
2354         /* tell the ucode the corerev */
2355         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2356
2357         /* tell the ucode MAC capabilities */
2358         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2359                            (u16) (wlc_hw->machwcap & 0xffff));
2360         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2361                            (u16) ((wlc_hw->
2362                                       machwcap >> 16) & 0xffff));
2363
2364         /* write retry limits to SCR, this done after PSM init */
2365         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2366         (void)R_REG(&regs->objaddr);
2367         W_REG(&regs->objdata, wlc_hw->SRL);
2368         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2369         (void)R_REG(&regs->objaddr);
2370         W_REG(&regs->objdata, wlc_hw->LRL);
2371
2372         /* write rate fallback retry limits */
2373         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2374         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2375
2376         AND_REG(&regs->ifs_ctl, 0x0FFF);
2377         W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2378
2379         /* dma initializations */
2380         wlc->txpend16165war = 0;
2381
2382         /* init the tx dma engines */
2383         for (i = 0; i < NFIFO; i++) {
2384                 if (wlc_hw->di[i])
2385                         dma_txinit(wlc_hw->di[i]);
2386         }
2387
2388         /* init the rx dma engine(s) and post receive buffers */
2389         dma_rxinit(wlc_hw->di[RX_FIFO]);
2390         dma_rxfill(wlc_hw->di[RX_FIFO]);
2391 }
2392
2393 /* This function is used for changing the tsf frac register
2394  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2395  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2396  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2397  * HTPHY Formula is 2^26/freq(MHz) e.g.
2398  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2399  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2400  * For spuron: 123MHz -> 2^26/123    = 545600.5
2401  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2402  * For spur off: 120MHz -> 2^26/120    = 559240.5
2403  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2404  */
2405
2406 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2407 {
2408         d11regs_t *regs;
2409         regs = wlc_hw->regs;
2410
2411         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2412             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2413                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2414                         W_REG(&regs->tsf_clk_frac_l, 0x2082);
2415                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2416                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2417                         W_REG(&regs->tsf_clk_frac_l, 0x5341);
2418                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2419                 } else {        /* 120Mhz */
2420                         W_REG(&regs->tsf_clk_frac_l, 0x8889);
2421                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2422                 }
2423         } else if (WLCISLCNPHY(wlc_hw->band)) {
2424                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2425                         W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2426                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2427                 } else {        /* 80Mhz */
2428                         W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2429                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2430                 }
2431         }
2432 }
2433
2434 /* Initialize GPIOs that are controlled by D11 core */
2435 static void wlc_gpio_init(struct wlc_info *wlc)
2436 {
2437         struct wlc_hw_info *wlc_hw = wlc->hw;
2438         d11regs_t *regs;
2439         u32 gc, gm;
2440
2441         regs = wlc_hw->regs;
2442
2443         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2444         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2445
2446         /*
2447          * Common GPIO setup:
2448          *      G0 = LED 0 = WLAN Activity
2449          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2450          *      G2 = LED 2 = WLAN 5 GHz Radio State
2451          *      G4 = radio disable input (HI enabled, LO disabled)
2452          */
2453
2454         gc = gm = 0;
2455
2456         /* Allocate GPIOs for mimo antenna diversity feature */
2457         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2458                 /* Enable antenna diversity, use 2x3 mode */
2459                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2460                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2461                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2462                              MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2463
2464                 /* init superswitch control */
2465                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2466
2467         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2468                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2469                 /*
2470                  * The board itself is powered by these GPIOs
2471                  * (when not sending pattern) so set them high
2472                  */
2473                 OR_REG(&regs->psm_gpio_oe,
2474                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2475                 OR_REG(&regs->psm_gpio_out,
2476                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2477
2478                 /* Enable antenna diversity, use 2x4 mode */
2479                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2480                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2481                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2482                              WLC_BAND_ALL);
2483
2484                 /* Configure the desired clock to be 4Mhz */
2485                 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2486                                    ANTSEL_CLKDIV_4MHZ);
2487         }
2488
2489         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2490         if (wlc_hw->boardflags & BFL_PACTRL)
2491                 gm |= gc |= BOARD_GPIO_PACTRL;
2492
2493         /* apply to gpiocontrol register */
2494         ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2495 }
2496
2497 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2498 {
2499         struct wlc_info *wlc;
2500         wlc = wlc_hw->wlc;
2501
2502         if (wlc_hw->ucode_loaded)
2503                 return;
2504
2505         if (D11REV_IS(wlc_hw->corerev, 23)) {
2506                 if (WLCISNPHY(wlc_hw->band)) {
2507                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2508                                         bcm43xx_16_mimosz);
2509                         wlc_hw->ucode_loaded = true;
2510                 } else
2511                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2512                                   "corerev %d\n",
2513                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2514         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2515                 if (WLCISLCNPHY(wlc_hw->band)) {
2516                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2517                                         bcm43xx_24_lcnsz);
2518                         wlc_hw->ucode_loaded = true;
2519                 } else {
2520                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2521                                   "corerev %d\n",
2522                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2523                 }
2524         }
2525 }
2526
2527 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2528                               const uint nbytes) {
2529         d11regs_t *regs = wlc_hw->regs;
2530         uint i;
2531         uint count;
2532
2533         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2534
2535         count = (nbytes / sizeof(u32));
2536
2537         W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2538         (void)R_REG(&regs->objaddr);
2539         for (i = 0; i < count; i++)
2540                 W_REG(&regs->objdata, ucode[i]);
2541 }
2542
2543 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2544                             const struct d11init *inits)
2545 {
2546         int i;
2547         volatile u8 *base;
2548
2549         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2550
2551         base = (volatile u8 *)wlc_hw->regs;
2552
2553         for (i = 0; inits[i].addr != 0xffff; i++) {
2554                 if (inits[i].size == 2)
2555                         W_REG((u16 *)(base + inits[i].addr),
2556                               inits[i].value);
2557                 else if (inits[i].size == 4)
2558                         W_REG((u32 *)(base + inits[i].addr),
2559                               inits[i].value);
2560         }
2561 }
2562
2563 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2564 {
2565         u16 phyctl;
2566         u16 phytxant = wlc_hw->bmac_phytxant;
2567         u16 mask = PHY_TXC_ANT_MASK;
2568
2569         /* set the Probe Response frame phy control word */
2570         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2571         phyctl = (phyctl & ~mask) | phytxant;
2572         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2573
2574         /* set the Response (ACK/CTS) frame phy control word */
2575         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2576         phyctl = (phyctl & ~mask) | phytxant;
2577         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2578 }
2579
2580 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2581 {
2582         /* update sw state */
2583         wlc_hw->bmac_phytxant = phytxant;
2584
2585         /* push to ucode if up */
2586         if (!wlc_hw->up)
2587                 return;
2588         wlc_ucode_txant_set(wlc_hw);
2589
2590 }
2591
2592 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2593 {
2594         return (u16) wlc_hw->wlc->stf->txant;
2595 }
2596
2597 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2598 {
2599         wlc_hw->antsel_type = antsel_type;
2600
2601         /* Update the antsel type for phy module to use */
2602         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2603 }
2604
2605 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2606 {
2607         bool fatal = false;
2608         uint unit;
2609         uint intstatus, idx;
2610         d11regs_t *regs = wlc_hw->regs;
2611         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2612
2613         unit = wlc_hw->unit;
2614
2615         for (idx = 0; idx < NFIFO; idx++) {
2616                 /* read intstatus register and ignore any non-error bits */
2617                 intstatus =
2618                     R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2619                 if (!intstatus)
2620                         continue;
2621
2622                 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2623                         unit, idx, intstatus);
2624
2625                 if (intstatus & I_RO) {
2626                         wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2627                                   "overflow\n", unit, idx);
2628                         fatal = true;
2629                 }
2630
2631                 if (intstatus & I_PC) {
2632                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2633                                  unit, idx);
2634                         fatal = true;
2635                 }
2636
2637                 if (intstatus & I_PD) {
2638                         wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2639                                   idx);
2640                         fatal = true;
2641                 }
2642
2643                 if (intstatus & I_DE) {
2644                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2645                                   "error\n", unit, idx);
2646                         fatal = true;
2647                 }
2648
2649                 if (intstatus & I_RU) {
2650                         wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2651                                   "underflow\n", idx, unit);
2652                 }
2653
2654                 if (intstatus & I_XU) {
2655                         wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2656                                   "underflow\n", idx, unit);
2657                         fatal = true;
2658                 }
2659
2660                 if (fatal) {
2661                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2662                         break;
2663                 } else
2664                         W_REG(&regs->intctrlregs[idx].intstatus,
2665                               intstatus);
2666         }
2667 }
2668
2669 void wlc_intrson(struct wlc_info *wlc)
2670 {
2671         struct wlc_hw_info *wlc_hw = wlc->hw;
2672         wlc->macintmask = wlc->defmacintmask;
2673         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2674 }
2675
2676 /* callback for siutils.c, which has only wlc handler, no wl
2677  * they both check up, not only because there is no need to off/restore d11 interrupt
2678  *  but also because per-port code may require sync with valid interrupt.
2679  */
2680
2681 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2682 {
2683         if (!wlc->hw->up)
2684                 return 0;
2685
2686         return wl_intrsoff(wlc->wl);
2687 }
2688
2689 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2690 {
2691         if (!wlc->hw->up)
2692                 return;
2693
2694         wl_intrsrestore(wlc->wl, macintmask);
2695 }
2696
2697 u32 wlc_intrsoff(struct wlc_info *wlc)
2698 {
2699         struct wlc_hw_info *wlc_hw = wlc->hw;
2700         u32 macintmask;
2701
2702         if (!wlc_hw->clk)
2703                 return 0;
2704
2705         macintmask = wlc->macintmask;   /* isr can still happen */
2706
2707         W_REG(&wlc_hw->regs->macintmask, 0);
2708         (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2709         udelay(1);              /* ensure int line is no longer driven */
2710         wlc->macintmask = 0;
2711
2712         /* return previous macintmask; resolve race between us and our isr */
2713         return wlc->macintstatus ? 0 : macintmask;
2714 }
2715
2716 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2717 {
2718         struct wlc_hw_info *wlc_hw = wlc->hw;
2719         if (!wlc_hw->clk)
2720                 return;
2721
2722         wlc->macintmask = macintmask;
2723         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2724 }
2725
2726 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2727 {
2728         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2729
2730         if (on) {
2731                 /* suspend tx fifos */
2732                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2733                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2734                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2735                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2736
2737                 /* zero the address match register so we do not send ACKs */
2738                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2739                                        null_ether_addr);
2740         } else {
2741                 /* resume tx fifos */
2742                 if (!wlc_hw->wlc->tx_suspended) {
2743                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2744                 }
2745                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2746                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2747                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2748
2749                 /* Restore address */
2750                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2751                                        wlc_hw->etheraddr);
2752         }
2753
2754         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2755
2756         if (on)
2757                 wlc_ucode_mute_override_set(wlc_hw);
2758         else
2759                 wlc_ucode_mute_override_clear(wlc_hw);
2760 }
2761
2762 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2763 {
2764         if (fifo >= NFIFO)
2765                 return -EINVAL;
2766
2767         *blocks = wlc_hw->xmtfifo_sz[fifo];
2768
2769         return 0;
2770 }
2771
2772 /* wlc_bmac_tx_fifo_suspended:
2773  * Check the MAC's tx suspend status for a tx fifo.
2774  *
2775  * When the MAC acknowledges a tx suspend, it indicates that no more
2776  * packets will be transmitted out the radio. This is independent of
2777  * DMA channel suspension---the DMA may have finished suspending, or may still
2778  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2779  * request.
2780  */
2781 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2782 {
2783         /* check that a suspend has been requested and is no longer pending */
2784
2785         /*
2786          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2787          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2788          * chnstatus register.
2789          * The tx fifo suspend completion is independent of the DMA suspend completion and
2790          *   may be acked before or after the DMA is suspended.
2791          */
2792         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2793             (R_REG(&wlc_hw->regs->chnstatus) &
2794              (1 << tx_fifo)) == 0)
2795                 return true;
2796
2797         return false;
2798 }
2799
2800 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2801 {
2802         u8 fifo = 1 << tx_fifo;
2803
2804         /* Two clients of this code, 11h Quiet period and scanning. */
2805
2806         /* only suspend if not already suspended */
2807         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2808                 return;
2809
2810         /* force the core awake only if not already */
2811         if (wlc_hw->suspended_fifos == 0)
2812                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2813
2814         wlc_hw->suspended_fifos |= fifo;
2815
2816         if (wlc_hw->di[tx_fifo]) {
2817                 /* Suspending AMPDU transmissions in the middle can cause underflow
2818                  * which may result in mismatch between ucode and driver
2819                  * so suspend the mac before suspending the FIFO
2820                  */
2821                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2822                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
2823
2824                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2825
2826                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2827                         wlc_enable_mac(wlc_hw->wlc);
2828         }
2829 }
2830
2831 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2832 {
2833         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2834          * here for PIO otherwise the watchdog will catch the inconsistency and fire
2835          */
2836         /* Two clients of this code, 11h Quiet period and scanning. */
2837         if (wlc_hw->di[tx_fifo])
2838                 dma_txresume(wlc_hw->di[tx_fifo]);
2839
2840         /* allow core to sleep again */
2841         if (wlc_hw->suspended_fifos == 0)
2842                 return;
2843         else {
2844                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2845                 if (wlc_hw->suspended_fifos == 0)
2846                         wlc_ucode_wake_override_clear(wlc_hw,
2847                                                       WLC_WAKE_OVERRIDE_TXFIFO);
2848         }
2849 }
2850
2851 /*
2852  * Read and clear macintmask and macintstatus and intstatus registers.
2853  * This routine should be called with interrupts off
2854  * Return:
2855  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
2856  *   0 if the interrupt is not for us, or we are in some special cases;
2857  *   device interrupt status bits otherwise.
2858  */
2859 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2860 {
2861         struct wlc_hw_info *wlc_hw = wlc->hw;
2862         d11regs_t *regs = wlc_hw->regs;
2863         u32 macintstatus;
2864
2865         /* macintstatus includes a DMA interrupt summary bit */
2866         macintstatus = R_REG(&regs->macintstatus);
2867
2868         BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2869                  macintstatus);
2870
2871         /* detect cardbus removed, in power down(suspend) and in reset */
2872         if (DEVICEREMOVED(wlc))
2873                 return -1;
2874
2875         /* DEVICEREMOVED succeeds even when the core is still resetting,
2876          * handle that case here.
2877          */
2878         if (macintstatus == 0xffffffff)
2879                 return 0;
2880
2881         /* defer unsolicited interrupts */
2882         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2883
2884         /* if not for us */
2885         if (macintstatus == 0)
2886                 return 0;
2887
2888         /* interrupts are already turned off for CFE build
2889          * Caution: For CFE Turning off the interrupts again has some undesired
2890          * consequences
2891          */
2892         /* turn off the interrupts */
2893         W_REG(&regs->macintmask, 0);
2894         (void)R_REG(&regs->macintmask); /* sync readback */
2895         wlc->macintmask = 0;
2896
2897         /* clear device interrupts */
2898         W_REG(&regs->macintstatus, macintstatus);
2899
2900         /* MI_DMAINT is indication of non-zero intstatus */
2901         if (macintstatus & MI_DMAINT) {
2902                 /*
2903                  * only fifo interrupt enabled is I_RI in
2904                  * RX_FIFO. If MI_DMAINT is set, assume it
2905                  * is set and clear the interrupt.
2906                  */
2907                 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
2908                       DEF_RXINTMASK);
2909         }
2910
2911         return macintstatus;
2912 }
2913
2914 /* Update wlc->macintstatus and wlc->intstatus[]. */
2915 /* Return true if they are updated successfully. false otherwise */
2916 bool wlc_intrsupd(struct wlc_info *wlc)
2917 {
2918         u32 macintstatus;
2919
2920         /* read and clear macintstatus and intstatus registers */
2921         macintstatus = wlc_intstatus(wlc, false);
2922
2923         /* device is removed */
2924         if (macintstatus == 0xffffffff)
2925                 return false;
2926
2927         /* update interrupt status in software */
2928         wlc->macintstatus |= macintstatus;
2929
2930         return true;
2931 }
2932
2933 /*
2934  * First-level interrupt processing.
2935  * Return true if this was our interrupt, false otherwise.
2936  * *wantdpc will be set to true if further wlc_dpc() processing is required,
2937  * false otherwise.
2938  */
2939 bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2940 {
2941         struct wlc_hw_info *wlc_hw = wlc->hw;
2942         u32 macintstatus;
2943
2944         *wantdpc = false;
2945
2946         if (!wlc_hw->up || !wlc->macintmask)
2947                 return false;
2948
2949         /* read and clear macintstatus and intstatus registers */
2950         macintstatus = wlc_intstatus(wlc, true);
2951
2952         if (macintstatus == 0xffffffff)
2953                 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2954                           " path\n");
2955
2956         /* it is not for us */
2957         if (macintstatus == 0)
2958                 return false;
2959
2960         *wantdpc = true;
2961
2962         /* save interrupt status bits */
2963         wlc->macintstatus = macintstatus;
2964
2965         return true;
2966
2967 }
2968
2969 static bool
2970 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2971 {
2972         /* discard intermediate indications for ucode with one legitimate case:
2973          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2974          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2975          *   transmission count)
2976          */
2977         if (!(txs->status & TX_STATUS_AMPDU)
2978             && (txs->status & TX_STATUS_INTERMEDIATE)) {
2979                 return false;
2980         }
2981
2982         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
2983 }
2984
2985 /* process tx completion events in BMAC
2986  * Return true if more tx status need to be processed. false otherwise.
2987  */
2988 static bool
2989 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
2990 {
2991         bool morepending = false;
2992         struct wlc_info *wlc = wlc_hw->wlc;
2993         d11regs_t *regs;
2994         tx_status_t txstatus, *txs;
2995         u32 s1, s2;
2996         uint n = 0;
2997         /*
2998          * Param 'max_tx_num' indicates max. # tx status to process before
2999          * break out.
3000          */
3001         uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3002
3003         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3004
3005         txs = &txstatus;
3006         regs = wlc_hw->regs;
3007         while (!(*fatal)
3008                && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
3009
3010                 if (s1 == 0xffffffff) {
3011                         wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
3012                                 wlc_hw->unit, __func__);
3013                         return morepending;
3014                 }
3015
3016                         s2 = R_REG(&regs->frmtxstatus2);
3017
3018                 txs->status = s1 & TXS_STATUS_MASK;
3019                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3020                 txs->sequence = s2 & TXS_SEQ_MASK;
3021                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3022                 txs->lasttxtime = 0;
3023
3024                 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3025
3026                 /* !give others some time to run! */
3027                 if (++n >= max_tx_num)
3028                         break;
3029         }
3030
3031         if (*fatal)
3032                 return 0;
3033
3034         if (n >= max_tx_num)
3035                 morepending = true;
3036
3037         if (!pktq_empty(&wlc->pkt_queue->q))
3038                 wlc_send_q(wlc);
3039
3040         return morepending;
3041 }
3042
3043 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3044 {
3045         struct wlc_hw_info *wlc_hw = wlc->hw;
3046         d11regs_t *regs = wlc_hw->regs;
3047         u32 mc, mi;
3048         struct wiphy *wiphy = wlc->wiphy;
3049
3050         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3051                 wlc_hw->band->bandunit);
3052
3053         /*
3054          * Track overlapping suspend requests
3055          */
3056         wlc_hw->mac_suspend_depth++;
3057         if (wlc_hw->mac_suspend_depth > 1)
3058                 return;
3059
3060         /* force the core awake */
3061         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3062
3063         mc = R_REG(&regs->maccontrol);
3064
3065         if (mc == 0xffffffff) {
3066                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3067                           __func__);
3068                 wl_down(wlc->wl);
3069                 return;
3070         }
3071         WARN_ON(mc & MCTL_PSM_JMP_0);
3072         WARN_ON(!(mc & MCTL_PSM_RUN));
3073         WARN_ON(!(mc & MCTL_EN_MAC));
3074
3075         mi = R_REG(&regs->macintstatus);
3076         if (mi == 0xffffffff) {
3077                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3078                           __func__);
3079                 wl_down(wlc->wl);
3080                 return;
3081         }
3082         WARN_ON(mi & MI_MACSSPNDD);
3083
3084         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3085
3086         SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3087                  WLC_MAX_MAC_SUSPEND);
3088
3089         if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3090                 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3091                           " and MI_MACSSPNDD is still not on.\n",
3092                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3093                 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3094                           "psm_brc 0x%04x\n", wlc_hw->unit,
3095                           R_REG(&regs->psmdebug),
3096                           R_REG(&regs->phydebug),
3097                           R_REG(&regs->psm_brc));
3098         }
3099
3100         mc = R_REG(&regs->maccontrol);
3101         if (mc == 0xffffffff) {
3102                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3103                           __func__);
3104                 wl_down(wlc->wl);
3105                 return;
3106         }
3107         WARN_ON(mc & MCTL_PSM_JMP_0);
3108         WARN_ON(!(mc & MCTL_PSM_RUN));
3109         WARN_ON(mc & MCTL_EN_MAC);
3110 }
3111
3112 void wlc_enable_mac(struct wlc_info *wlc)
3113 {
3114         struct wlc_hw_info *wlc_hw = wlc->hw;
3115         d11regs_t *regs = wlc_hw->regs;
3116         u32 mc, mi;
3117
3118         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3119                 wlc->band->bandunit);
3120
3121         /*
3122          * Track overlapping suspend requests
3123          */
3124         wlc_hw->mac_suspend_depth--;
3125         if (wlc_hw->mac_suspend_depth > 0)
3126                 return;
3127
3128         mc = R_REG(&regs->maccontrol);
3129         WARN_ON(mc & MCTL_PSM_JMP_0);
3130         WARN_ON(mc & MCTL_EN_MAC);
3131         WARN_ON(!(mc & MCTL_PSM_RUN));
3132
3133         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3134         W_REG(&regs->macintstatus, MI_MACSSPNDD);
3135
3136         mc = R_REG(&regs->maccontrol);
3137         WARN_ON(mc & MCTL_PSM_JMP_0);
3138         WARN_ON(!(mc & MCTL_EN_MAC));
3139         WARN_ON(!(mc & MCTL_PSM_RUN));
3140
3141         mi = R_REG(&regs->macintstatus);
3142         WARN_ON(mi & MI_MACSSPNDD);
3143
3144         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3145 }
3146
3147 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3148 {
3149         u8 rate;
3150         u8 rates[8] = {
3151                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3152                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3153         };
3154         u16 entry_ptr;
3155         u16 pctl1;
3156         uint i;
3157
3158         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3159                 return;
3160
3161         /* walk the phy rate table and update the entries */
3162         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3163                 rate = rates[i];
3164
3165                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3166
3167                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3168                 pctl1 =
3169                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3170
3171                 /* modify the value */
3172                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3173                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3174
3175                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3176                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3177                                    pctl1);
3178         }
3179 }
3180
3181 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3182 {
3183         uint i;
3184         u8 plcp_rate = 0;
3185         struct plcp_signal_rate_lookup {
3186                 u8 rate;
3187                 u8 signal_rate;
3188         };
3189         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3190         const struct plcp_signal_rate_lookup rate_lookup[] = {
3191                 {WLC_RATE_6M, 0xB},
3192                 {WLC_RATE_9M, 0xF},
3193                 {WLC_RATE_12M, 0xA},
3194                 {WLC_RATE_18M, 0xE},
3195                 {WLC_RATE_24M, 0x9},
3196                 {WLC_RATE_36M, 0xD},
3197                 {WLC_RATE_48M, 0x8},
3198                 {WLC_RATE_54M, 0xC}
3199         };
3200
3201         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3202                 if (rate == rate_lookup[i].rate) {
3203                         plcp_rate = rate_lookup[i].signal_rate;
3204                         break;
3205                 }
3206         }
3207
3208         /* Find the SHM pointer to the rate table entry by looking in the
3209          * Direct-map Table
3210          */
3211         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3212 }
3213
3214 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3215 {
3216         wlc_hw->hw_stf_ss_opmode = stf_mode;
3217
3218         if (wlc_hw->clk)
3219                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3220 }
3221
3222 void
3223 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3224                   u32 *tsf_h_ptr)
3225 {
3226         d11regs_t *regs = wlc_hw->regs;
3227
3228         /* read the tsf timer low, then high to get an atomic read */
3229         *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3230         *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3231
3232         return;
3233 }
3234
3235 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3236 {
3237         d11regs_t *regs;
3238         u32 w, val;
3239         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3240
3241         BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3242
3243         regs = wlc_hw->regs;
3244
3245         /* Validate dchip register access */
3246
3247         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3248         (void)R_REG(&regs->objaddr);
3249         w = R_REG(&regs->objdata);
3250
3251         /* Can we write and read back a 32bit register? */
3252         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3253         (void)R_REG(&regs->objaddr);
3254         W_REG(&regs->objdata, (u32) 0xaa5555aa);
3255
3256         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3257         (void)R_REG(&regs->objaddr);
3258         val = R_REG(&regs->objdata);
3259         if (val != (u32) 0xaa5555aa) {
3260                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3261                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
3262                 return false;
3263         }
3264
3265         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3266         (void)R_REG(&regs->objaddr);
3267         W_REG(&regs->objdata, (u32) 0x55aaaa55);
3268
3269         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3270         (void)R_REG(&regs->objaddr);
3271         val = R_REG(&regs->objdata);
3272         if (val != (u32) 0x55aaaa55) {
3273                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3274                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
3275                 return false;
3276         }
3277
3278         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3279         (void)R_REG(&regs->objaddr);
3280         W_REG(&regs->objdata, w);
3281
3282         /* clear CFPStart */
3283         W_REG(&regs->tsf_cfpstart, 0);
3284
3285         w = R_REG(&regs->maccontrol);
3286         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3287             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3288                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3289                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3290                           (MCTL_IHR_EN | MCTL_WAKE),
3291                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3292                 return false;
3293         }
3294
3295         return true;
3296 }
3297
3298 #define PHYPLL_WAIT_US  100000
3299
3300 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3301 {
3302         d11regs_t *regs;
3303         u32 tmp;
3304
3305         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3306
3307         tmp = 0;
3308         regs = wlc_hw->regs;
3309
3310         if (on) {
3311                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3312                         OR_REG(&regs->clk_ctl_st,
3313                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3314                                 CCS_ERSRC_REQ_PHYPLL));
3315                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3316                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3317                                  PHYPLL_WAIT_US);
3318
3319                         tmp = R_REG(&regs->clk_ctl_st);
3320                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3321                             (CCS_ERSRC_AVAIL_HT)) {
3322                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3323                                           " PLL failed\n", __func__);
3324                         }
3325                 } else {
3326                         OR_REG(&regs->clk_ctl_st,
3327                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3328                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3329                                   (CCS_ERSRC_AVAIL_D11PLL |
3330                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3331                                  (CCS_ERSRC_AVAIL_D11PLL |
3332                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3333
3334                         tmp = R_REG(&regs->clk_ctl_st);
3335                         if ((tmp &
3336                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3337                             !=
3338                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3339                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3340                                           "PHY PLL failed\n", __func__);
3341                         }
3342                 }
3343         } else {
3344                 /* Since the PLL may be shared, other cores can still be requesting it;
3345                  * so we'll deassert the request but not wait for status to comply.
3346                  */
3347                 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3348                 tmp = R_REG(&regs->clk_ctl_st);
3349         }
3350 }
3351
3352 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3353 {
3354         bool dev_gone;
3355
3356         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3357
3358         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3359
3360         if (dev_gone)
3361                 return;
3362
3363         if (wlc_hw->noreset)
3364                 return;
3365
3366         /* radio off */
3367         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3368
3369         /* turn off analog core */
3370         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3371
3372         /* turn off PHYPLL to save power */
3373         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3374
3375         /* No need to set wlc->pub->radio_active = OFF
3376          * because this function needs down capability and
3377          * radio_active is designed for BCMNODOWN.
3378          */
3379
3380         /* remove gpio controls */
3381         if (wlc_hw->ucode_dbgsel)
3382                 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3383
3384         wlc_hw->clk = false;
3385         ai_core_disable(wlc_hw->sih, 0);
3386         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3387 }
3388
3389 /* power both the pll and external oscillator on/off */
3390 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3391 {
3392         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3393
3394         /* dont power down if plldown is false or we must poll hw radio disable */
3395         if (!want && wlc_hw->pllreq)
3396                 return;
3397
3398         if (wlc_hw->sih)
3399                 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3400
3401         wlc_hw->sbclk = want;
3402         if (!wlc_hw->sbclk) {
3403                 wlc_hw->clk = false;
3404                 if (wlc_hw->band && wlc_hw->band->pi)
3405                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3406         }
3407 }
3408
3409 static void wlc_flushqueues(struct wlc_info *wlc)
3410 {
3411         struct wlc_hw_info *wlc_hw = wlc->hw;
3412         uint i;
3413
3414         wlc->txpend16165war = 0;
3415
3416         /* free any posted tx packets */
3417         for (i = 0; i < NFIFO; i++)
3418                 if (wlc_hw->di[i]) {
3419                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3420                         TXPKTPENDCLR(wlc, i);
3421                         BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3422                 }
3423
3424         /* free any posted rx packets */
3425         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3426 }
3427
3428 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3429 {
3430         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3431 }
3432
3433 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3434 {
3435         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3436 }
3437
3438 static u16
3439 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3440 {
3441         d11regs_t *regs = wlc_hw->regs;
3442         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3443         volatile u16 *objdata_hi = objdata_lo + 1;
3444         u16 v;
3445
3446         W_REG(&regs->objaddr, sel | (offset >> 2));
3447         (void)R_REG(&regs->objaddr);
3448         if (offset & 2) {
3449                 v = R_REG(objdata_hi);
3450         } else {
3451                 v = R_REG(objdata_lo);
3452         }
3453
3454         return v;
3455 }
3456
3457 static void
3458 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3459 {
3460         d11regs_t *regs = wlc_hw->regs;
3461         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3462         volatile u16 *objdata_hi = objdata_lo + 1;
3463
3464         W_REG(&regs->objaddr, sel | (offset >> 2));
3465         (void)R_REG(&regs->objaddr);
3466         if (offset & 2) {
3467                 W_REG(objdata_hi, v);
3468         } else {
3469                 W_REG(objdata_lo, v);
3470         }
3471 }
3472
3473 /* Copy a buffer to shared memory of specified type .
3474  * SHM 'offset' needs to be an even address and
3475  * Buffer length 'len' must be an even number of bytes
3476  * 'sel' selects the type of memory
3477  */
3478 void
3479 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3480                        int len, u32 sel)
3481 {
3482         u16 v;
3483         const u8 *p = (const u8 *)buf;
3484         int i;
3485
3486         if (len <= 0 || (offset & 1) || (len & 1))
3487                 return;
3488
3489         for (i = 0; i < len; i += 2) {
3490                 v = p[i] | (p[i + 1] << 8);
3491                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3492         }
3493 }
3494
3495 /* Copy a piece of shared memory of specified type to a buffer .
3496  * SHM 'offset' needs to be an even address and
3497  * Buffer length 'len' must be an even number of bytes
3498  * 'sel' selects the type of memory
3499  */
3500 void
3501 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3502                          int len, u32 sel)
3503 {
3504         u16 v;
3505         u8 *p = (u8 *) buf;
3506         int i;
3507
3508         if (len <= 0 || (offset & 1) || (len & 1))
3509                 return;
3510
3511         for (i = 0; i < len; i += 2) {
3512                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3513                 p[i] = v & 0xFF;
3514                 p[i + 1] = (v >> 8) & 0xFF;
3515         }
3516 }
3517
3518 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3519 {
3520         BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3521                 wlc_hw->vars_size);
3522
3523         *buf = wlc_hw->vars;
3524         *len = wlc_hw->vars_size;
3525 }
3526
3527 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3528 {
3529         wlc_hw->SRL = SRL;
3530         wlc_hw->LRL = LRL;
3531
3532         /* write retry limit to SCR, shouldn't need to suspend */
3533         if (wlc_hw->up) {
3534                 W_REG(&wlc_hw->regs->objaddr,
3535                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3536                 (void)R_REG(&wlc_hw->regs->objaddr);
3537                 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3538                 W_REG(&wlc_hw->regs->objaddr,
3539                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3540                 (void)R_REG(&wlc_hw->regs->objaddr);
3541                 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3542         }
3543 }
3544
3545 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3546 {
3547         if (set) {
3548                 if (mboolisset(wlc_hw->pllreq, req_bit))
3549                         return;
3550
3551                 mboolset(wlc_hw->pllreq, req_bit);
3552
3553                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3554                         if (!wlc_hw->sbclk) {
3555                                 wlc_bmac_xtal(wlc_hw, ON);
3556                         }
3557                 }
3558         } else {
3559                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3560                         return;
3561
3562                 mboolclr(wlc_hw->pllreq, req_bit);
3563
3564                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3565                         if (wlc_hw->sbclk) {
3566                                 wlc_bmac_xtal(wlc_hw, OFF);
3567                         }
3568                 }
3569         }
3570
3571         return;
3572 }
3573
3574 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3575 {
3576         u16 table_ptr;
3577         u8 phy_rate, index;
3578
3579         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3580         /* XXX4321 fixup needed ? */
3581         if (IS_OFDM(rate))
3582                 table_ptr = M_RT_DIRMAP_A;
3583         else
3584                 table_ptr = M_RT_DIRMAP_B;
3585
3586         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3587          * the index into the rate table.
3588          */
3589         phy_rate = rate_info[rate] & WLC_RATE_MASK;
3590         index = phy_rate & 0xf;
3591
3592         /* Find the SHM pointer to the rate table entry by looking in the
3593          * Direct-map Table
3594          */
3595         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3596 }
3597
3598 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3599 {
3600         wlc_hw->antsel_avail = antsel_avail;
3601 }