2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
24 #include <proto/802.11.h>
39 #include "wlc_types.h"
47 #include "phy/wlc_phy_hal.h"
48 #include "wlc_channel.h"
50 #include "wl_export.h"
52 #include "wlc_antsel.h"
53 #include "pcie_core.h"
54 #include "wlc_alloc.h"
58 #define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
60 #define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
61 #define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
62 #define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
63 #define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
65 #define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
67 #ifndef BMAC_DUP_TO_REMOVE
68 #define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
70 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
72 #endif /* BMAC_DUP_TO_REMOVE */
74 #define DMAREG(wlc_hw, direction, fifonum) \
75 ((direction == DMA_TX) ? \
76 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
77 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
80 * The following table lists the buffer memory allocated to xmt fifos in HW.
81 * the size is in units of 256bytes(one block), total size is HW dependent
82 * ucode has default fifo partition, sw can overwrite if necessary
84 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
85 * the twiki is updated before making changes.
88 #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
90 static u16 xmtfifo_sz[][NFIFO] = {
91 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
92 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
93 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
94 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
95 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
98 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
99 static void wlc_coreinit(struct wlc_info *wlc);
101 /* used by wlc_wakeucode_init() */
102 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
103 const struct d11init *inits);
104 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
106 static void wlc_ucode_download(struct wlc_hw_info *wlc);
107 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
109 /* used by wlc_dpc() */
110 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
112 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
113 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
115 /* used by wlc_down() */
116 static void wlc_flushqueues(struct wlc_info *wlc);
118 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
119 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
120 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
121 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
123 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
124 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
126 /* Low Level Prototypes */
127 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
128 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
129 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
130 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
132 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
134 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
135 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
136 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
137 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
138 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
139 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
140 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
141 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
142 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
143 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
144 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
145 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
146 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
147 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
148 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
149 static void wlc_gpio_init(struct wlc_info *wlc);
150 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
152 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
154 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
155 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
156 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
157 chanspec_t chanspec);
158 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
160 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
161 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
164 /* === Low Level functions === */
166 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
168 wlc_hw->shortslot = shortslot;
170 if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
171 wlc_suspend_mac_and_wait(wlc_hw->wlc);
172 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
173 wlc_enable_mac(wlc_hw->wlc);
178 * Update the slot timing for standard 11b/g (20us slots)
179 * or shortslot 11g (9us slots)
180 * The PSM needs to be suspended for this call.
182 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
190 /* 11g short slot: 11a timing */
191 W_REG(®s->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
192 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
194 /* 11g long slot: 11b timing */
195 W_REG(®s->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
196 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
200 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
202 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
204 /* init microcode host flags */
205 wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
207 /* do band-specific ucode IHR, SHM, and SCR inits */
208 if (D11REV_IS(wlc_hw->corerev, 23)) {
209 if (WLCISNPHY(wlc_hw->band)) {
210 wlc_write_inits(wlc_hw, d11n0bsinitvals16);
212 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
213 " %d\n", __func__, wlc_hw->unit,
217 if (D11REV_IS(wlc_hw->corerev, 24)) {
218 if (WLCISLCNPHY(wlc_hw->band)) {
219 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
221 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
222 " core rev %d\n", __func__,
223 wlc_hw->unit, wlc_hw->corerev);
225 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
226 __func__, wlc_hw->unit, wlc_hw->corerev);
231 /* switch to new band but leave it inactive */
232 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
234 struct wlc_hw_info *wlc_hw = wlc->hw;
237 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
239 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
241 /* disable interrupts */
242 macintmask = wl_intrsoff(wlc->wl);
245 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
247 wlc_bmac_core_phy_clk(wlc_hw, OFF);
249 wlc_setxband(wlc_hw, bandunit);
254 /* Process received frames */
256 * Return true if more frames need to be processed. false otherwise.
257 * Param 'bound' indicates max. # frames to process before break out.
260 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
263 struct sk_buff *head = NULL;
264 struct sk_buff *tail = NULL;
266 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
267 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
269 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
270 /* gather received frames */
271 while ((p = dma_rx(wlc_hw->di[fifo]))) {
280 /* !give others some time to run! */
281 if (++n >= bound_limit)
285 /* post more rbufs */
286 dma_rxfill(wlc_hw->di[fifo]);
288 /* process each frame */
289 while ((p = head) != NULL) {
293 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
295 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
296 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
298 wlc_recv(wlc_hw->wlc, p);
301 return n >= bound_limit;
304 /* second-level interrupt processing
305 * Return true if another dpc needs to be re-scheduled. false otherwise.
306 * Param 'bounded' indicates if applicable loops should be bounded.
308 bool wlc_dpc(struct wlc_info *wlc, bool bounded)
311 struct wlc_hw_info *wlc_hw = wlc->hw;
312 d11regs_t *regs = wlc_hw->regs;
314 struct wiphy *wiphy = wlc->wiphy;
316 if (DEVICEREMOVED(wlc)) {
317 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
323 /* grab and clear the saved software intstatus bits */
324 macintstatus = wlc->macintstatus;
325 wlc->macintstatus = 0;
327 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
328 wlc_hw->unit, macintstatus);
330 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
332 /* BCN template is available */
333 /* ZZZ: Use AP_ACTIVE ? */
334 if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
335 && (macintstatus & MI_BCNTPL)) {
336 wlc_update_beacon(wlc);
339 /* PMQ entry addition */
340 if (macintstatus & MI_PMQ) {
344 if (macintstatus & MI_TFS) {
345 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
346 wlc->macintstatus |= MI_TFS;
348 wiphy_err(wiphy, "MI_TFS: fatal\n");
353 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
356 /* ATIM window end */
357 if (macintstatus & MI_ATIMWINEND) {
358 BCMMSG(wlc->wiphy, "end of ATIM window\n");
359 OR_REG(®s->maccommand, wlc->qvalid);
363 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
364 if (macintstatus & MI_DMAINT) {
365 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
366 wlc->macintstatus |= MI_DMAINT;
370 /* TX FIFO suspend/flush completion */
371 if (macintstatus & MI_TXSTOP) {
372 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
373 /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
377 /* noise sample collected */
378 if (macintstatus & MI_BG_NOISE) {
379 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
382 if (macintstatus & MI_GP0) {
383 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
384 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
386 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
387 __func__, wlc_hw->sih->chip,
388 wlc_hw->sih->chiprev);
393 /* gptimer timeout */
394 if (macintstatus & MI_TO) {
395 W_REG(®s->gptimer, 0);
398 if (macintstatus & MI_RFDISABLE) {
399 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
400 " RF Disable Input\n", wlc_hw->unit);
401 wl_rfkill_set_hw_state(wlc->wl);
404 /* send any enq'd tx packets. Just makes sure to jump start tx */
405 if (!pktq_empty(&wlc->pkt_queue->q))
408 /* it isn't done and needs to be resched if macintstatus is non-zero */
409 return wlc->macintstatus != 0;
413 return wlc->macintstatus != 0;
416 /* common low-level watchdog code */
417 void wlc_bmac_watchdog(void *arg)
419 struct wlc_info *wlc = (struct wlc_info *) arg;
420 struct wlc_hw_info *wlc_hw = wlc->hw;
422 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
427 /* increment second count */
430 /* Check for FIFO error interrupts */
431 wlc_bmac_fifoerrors(wlc_hw);
433 /* make sure RX dma has buffers */
434 dma_rxfill(wlc->hw->di[RX_FIFO]);
436 wlc_phy_watchdog(wlc_hw->band->pi);
440 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
441 bool mute, struct txpwr_limits *txpwr)
445 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
447 wlc_hw->chanspec = chanspec;
449 /* Switch bands if necessary */
450 if (NBANDS_HW(wlc_hw) > 1) {
451 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
452 if (wlc_hw->band->bandunit != bandunit) {
453 /* wlc_bmac_setband disables other bandunit,
454 * use light band switch if not up yet
457 wlc_phy_chanspec_radio_set(wlc_hw->
458 bandstate[bandunit]->
460 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
462 wlc_setxband(wlc_hw, bandunit);
467 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
471 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
473 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
475 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
476 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
478 /* Update muting of the channel */
479 wlc_bmac_mute(wlc_hw, mute, 0);
483 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
485 state->machwcap = wlc_hw->machwcap;
490 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
494 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
496 struct wlc_hw_info *wlc_hw = wlc->hw;
497 uint unit = wlc_hw->unit;
498 wlc_tunables_t *tune = wlc->pub->tunables;
499 struct wiphy *wiphy = wlc->wiphy;
501 /* name and offsets for dma_attach */
502 snprintf(name, sizeof(name), "wl%d", unit);
504 if (wlc_hw->di[0] == 0) { /* Init FIFOs */
506 int dma_attach_err = 0;
507 /* Find out the DMA addressing capability and let OS know
508 * All the channels within one DMA core have 'common-minimum' same
512 dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
514 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
515 wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
516 "resources failed\n", unit);
522 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
523 * RX: RX_FIFO (RX data packets)
525 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
526 (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
527 NULL), DMAREG(wlc_hw, DMA_RX, 0),
528 (wme ? tune->ntxd : 0), tune->nrxd,
529 tune->rxbufsz, -1, tune->nrxbufpost,
530 WL_HWRXOFF, &wl_msg_level);
531 dma_attach_err |= (NULL == wlc_hw->di[0]);
535 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
536 * (legacy) TX_DATA_FIFO (TX data packets)
539 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
540 DMAREG(wlc_hw, DMA_TX, 1), NULL,
541 tune->ntxd, 0, 0, -1, 0, 0,
543 dma_attach_err |= (NULL == wlc_hw->di[1]);
547 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
550 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
551 DMAREG(wlc_hw, DMA_TX, 2), NULL,
552 tune->ntxd, 0, 0, -1, 0, 0,
554 dma_attach_err |= (NULL == wlc_hw->di[2]);
557 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
558 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
560 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
561 DMAREG(wlc_hw, DMA_TX, 3),
562 NULL, tune->ntxd, 0, 0, -1,
563 0, 0, &wl_msg_level);
564 dma_attach_err |= (NULL == wlc_hw->di[3]);
565 /* Cleaner to leave this as if with AP defined */
567 if (dma_attach_err) {
568 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
573 /* get pointer to dma engine tx flow control variable */
574 for (i = 0; i < NFIFO; i++)
577 (uint *) dma_getvar(wlc_hw->di[i],
581 /* initial ucode host flags */
582 wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
587 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
591 for (j = 0; j < NFIFO; j++) {
593 dma_detach(wlc_hw->di[j]);
594 wlc_hw->di[j] = NULL;
600 * run backplane attach, init nvram
602 * initialize software state for each core and band
603 * put the whole chip in reset(driver down state), no clock
605 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
606 bool piomode, void *regsva, uint bustype, void *btparam)
608 struct wlc_hw_info *wlc_hw;
610 char *macaddr = NULL;
615 shared_phy_params_t sha_params;
616 struct wiphy *wiphy = wlc->wiphy;
618 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
626 wlc_hw->band = wlc_hw->bandstate[0];
627 wlc_hw->_piomode = piomode;
629 /* populate struct wlc_hw_info with default values */
630 wlc_bmac_info_init(wlc_hw);
633 * Do the hardware portion of the attach.
634 * Also initialize software state that depends on the particular hardware
637 wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
638 &wlc_hw->vars, &wlc_hw->vars_size);
639 if (wlc_hw->sih == NULL) {
640 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
648 * Get vendid/devid nvram overwrites, which could be different
649 * than those the BIOS recognizes for devices on PCMCIA_BUS,
650 * SDIO_BUS, and SROMless devices on PCI_BUS.
653 bustype = BCMBUSTYPE;
655 if (bustype != SI_BUS) {
658 var = getvar(vars, "vendid");
660 vendor = (u16) simple_strtoul(var, NULL, 0);
661 wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
664 var = getvar(vars, "devid");
666 u16 devid = (u16) simple_strtoul(var, NULL, 0);
667 if (devid != 0xffff) {
669 wiphy_err(wiphy, "Overriding device id = 0x%x"
674 /* verify again the device is supported */
675 if (!wlc_chipmatch(vendor, device)) {
676 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
677 "vendor/device (0x%x/0x%x)\n",
678 unit, vendor, device);
684 wlc_hw->vendorid = vendor;
685 wlc_hw->deviceid = device;
687 /* set bar0 window to point at D11 core */
688 wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
689 wlc_hw->corerev = ai_corerev(wlc_hw->sih);
693 wlc->regs = wlc_hw->regs;
695 /* validate chip, chiprev and corerev */
696 if (!wlc_isgoodchip(wlc_hw)) {
701 /* initialize power control registers */
702 ai_clkctl_init(wlc_hw->sih);
704 /* request fastclock and force fastclock for the rest of attach
705 * bring the d11 core out of reset.
706 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
707 * But it will be called again inside wlc_corereset, after d11 is out of reset.
709 wlc_clkctl_clk(wlc_hw, CLK_FAST);
710 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
712 if (!wlc_bmac_validate_chip_access(wlc_hw)) {
713 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
719 /* get the board rev, used just below */
720 j = getintvar(vars, "boardrev");
721 /* promote srom boardrev of 0xFF to 1 */
722 if (j == BOARDREV_PROMOTABLE)
723 j = BOARDREV_PROMOTED;
724 wlc_hw->boardrev = (u16) j;
725 if (!wlc_validboardtype(wlc_hw)) {
726 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
727 "board type (0x%x)" " or revision level (0x%x)\n",
728 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
732 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
733 wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
734 wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
736 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
737 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
739 if ((wlc_hw->sih->bustype == PCI_BUS)
740 && (ai_pci_war16165(wlc_hw->sih)))
741 wlc->war16165 = true;
743 /* check device id(srom, nvram etc.) to set bands */
744 if (wlc_hw->deviceid == BCM43224_D11N_ID) {
745 /* Dualband boards */
750 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
753 /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
754 * init of these values
756 wlc->vendorid = wlc_hw->vendorid;
757 wlc->deviceid = wlc_hw->deviceid;
758 wlc->pub->sih = wlc_hw->sih;
759 wlc->pub->corerev = wlc_hw->corerev;
760 wlc->pub->sromrev = wlc_hw->sromrev;
761 wlc->pub->boardrev = wlc_hw->boardrev;
762 wlc->pub->boardflags = wlc_hw->boardflags;
763 wlc->pub->boardflags2 = wlc_hw->boardflags2;
764 wlc->pub->_nbands = wlc_hw->_nbands;
766 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
768 if (wlc_hw->physhim == NULL) {
769 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
775 /* pass all the parameters to wlc_phy_shared_attach in one struct */
776 sha_params.sih = wlc_hw->sih;
777 sha_params.physhim = wlc_hw->physhim;
778 sha_params.unit = unit;
779 sha_params.corerev = wlc_hw->corerev;
780 sha_params.vars = vars;
781 sha_params.vid = wlc_hw->vendorid;
782 sha_params.did = wlc_hw->deviceid;
783 sha_params.chip = wlc_hw->sih->chip;
784 sha_params.chiprev = wlc_hw->sih->chiprev;
785 sha_params.chippkg = wlc_hw->sih->chippkg;
786 sha_params.sromrev = wlc_hw->sromrev;
787 sha_params.boardtype = wlc_hw->sih->boardtype;
788 sha_params.boardrev = wlc_hw->boardrev;
789 sha_params.boardvendor = wlc_hw->sih->boardvendor;
790 sha_params.boardflags = wlc_hw->boardflags;
791 sha_params.boardflags2 = wlc_hw->boardflags2;
792 sha_params.bustype = wlc_hw->sih->bustype;
793 sha_params.buscorerev = wlc_hw->sih->buscorerev;
795 /* alloc and save pointer to shared phy state area */
796 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
797 if (!wlc_hw->phy_sh) {
802 /* initialize software state for each core and band */
803 for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
805 * band0 is always 2.4Ghz
806 * band1, if present, is 5Ghz
809 /* So if this is a single band 11a card, use band 1 */
810 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
813 wlc_setxband(wlc_hw, j);
815 wlc_hw->band->bandunit = j;
816 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
817 wlc->band->bandunit = j;
818 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
819 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
821 wlc_hw->machwcap = R_REG(®s->machwcap);
822 wlc_hw->machwcap_backup = wlc_hw->machwcap;
824 /* init tx fifo size */
826 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
828 /* Get a phy for this band */
829 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
830 (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
832 if (wlc_hw->band->pi == NULL) {
833 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
834 "attach failed\n", unit);
839 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
841 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
842 &wlc_hw->band->phyrev,
843 &wlc_hw->band->radioid,
844 &wlc_hw->band->radiorev);
845 wlc_hw->band->abgphy_encore =
846 wlc_phy_get_encore(wlc_hw->band->pi);
847 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
848 wlc_hw->band->core_flags =
849 wlc_phy_get_coreflags(wlc_hw->band->pi);
851 /* verify good phy_type & supported phy revision */
852 if (WLCISNPHY(wlc_hw->band)) {
853 if (NCONF_HAS(wlc_hw->band->phyrev))
857 } else if (WLCISLCNPHY(wlc_hw->band)) {
858 if (LCNCONF_HAS(wlc_hw->band->phyrev))
864 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
865 "phy type/rev (%d/%d)\n", unit,
866 wlc_hw->band->phytype, wlc_hw->band->phyrev);
872 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
873 * high level attach. However we can not make that change until all low level access
874 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
875 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
876 * low only init when all fns updated.
878 wlc->band->pi = wlc_hw->band->pi;
879 wlc->band->phytype = wlc_hw->band->phytype;
880 wlc->band->phyrev = wlc_hw->band->phyrev;
881 wlc->band->radioid = wlc_hw->band->radioid;
882 wlc->band->radiorev = wlc_hw->band->radiorev;
884 /* default contention windows size limits */
885 wlc_hw->band->CWmin = APHY_CWMIN;
886 wlc_hw->band->CWmax = PHY_CWMAX;
888 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
894 /* disable core to match driver "down" state */
895 wlc_coredisable(wlc_hw);
897 /* Match driver "down" state */
898 if (wlc_hw->sih->bustype == PCI_BUS)
899 ai_pci_down(wlc_hw->sih);
901 /* register sb interrupt callback functions */
902 ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
903 (void *)wlc_wlintrsrestore, NULL, wlc);
905 /* turn off pll and xtal to match driver "down" state */
906 wlc_bmac_xtal(wlc_hw, OFF);
908 /* *********************************************************************
909 * The hardware is in the DOWN state at this point. D11 core
910 * or cores are in reset with clocks off, and the board PLLs
911 * are off if possible.
913 * Beyond this point, wlc->sbclk == false and chip registers
914 * should not be touched.
915 *********************************************************************
918 /* init etheraddr state variables */
919 macaddr = wlc_get_macaddr(wlc_hw);
920 if (macaddr == NULL) {
921 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
926 bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
927 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
928 is_zero_ether_addr(wlc_hw->etheraddr)) {
929 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
936 "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
937 wlc_hw->deviceid, wlc_hw->_nbands,
938 wlc_hw->sih->boardtype, macaddr);
943 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
949 * Initialize wlc_info default values ...
950 * may get overrides later in this function
951 * BMAC_NOTES, move low out and resolve the dangling ones
953 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
955 struct wlc_info *wlc = wlc_hw->wlc;
957 /* set default sw macintmask value */
958 wlc->defmacintmask = DEF_MACINTMASK;
960 /* various 802.11g modes */
961 wlc_hw->shortslot = false;
963 wlc_hw->SFBL = RETRY_SHORT_FB;
964 wlc_hw->LFBL = RETRY_LONG_FB;
966 /* default mac retry limits */
967 wlc_hw->SRL = RETRY_SHORT_DEF;
968 wlc_hw->LRL = RETRY_LONG_DEF;
969 wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
975 int wlc_bmac_detach(struct wlc_info *wlc)
978 struct wlc_hwband *band;
979 struct wlc_hw_info *wlc_hw = wlc->hw;
985 /* detach interrupt sync mechanism since interrupt is disabled and per-port
986 * interrupt object may has been freed. this must be done before sb core switch
988 ai_deregister_intr_callback(wlc_hw->sih);
990 if (wlc_hw->sih->bustype == PCI_BUS)
991 ai_pci_sleep(wlc_hw->sih);
994 wlc_bmac_detach_dmapio(wlc_hw);
997 for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
999 /* Detach this band's phy */
1000 wlc_phy_detach(band->pi);
1003 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1006 /* Free shared phy state */
1007 wlc_phy_shared_detach(wlc_hw->phy_sh);
1009 wlc_phy_shim_detach(wlc_hw->physhim);
1012 kfree(wlc_hw->vars);
1013 wlc_hw->vars = NULL;
1016 ai_detach(wlc_hw->sih);
1024 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1026 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1028 /* reset the core */
1029 if (!DEVICEREMOVED(wlc_hw->wlc))
1030 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1032 /* purge the dma rings */
1033 wlc_flushqueues(wlc_hw->wlc);
1035 wlc_reset_bmac_done(wlc_hw->wlc);
1039 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1043 struct wlc_info *wlc = wlc_hw->wlc;
1045 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1047 /* request FAST clock if not on */
1048 fastclk = wlc_hw->forcefastclk;
1050 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1052 /* disable interrupts */
1053 macintmask = wl_intrsoff(wlc->wl);
1055 /* set up the specified band and chanspec */
1056 wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1057 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1059 /* do one-time phy inits and calibration */
1060 wlc_phy_cal_init(wlc_hw->band->pi);
1062 /* core-specific initialization */
1065 /* suspend the tx fifos and mute the phy for preism cac time */
1067 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1069 /* band-specific inits */
1070 wlc_bmac_bsinit(wlc, chanspec);
1072 /* restore macintmask */
1073 wl_intrsrestore(wlc->wl, macintmask);
1075 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1076 * and wlc_enable_mac() will clear this override bit.
1078 mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1081 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1083 wlc_hw->mac_suspend_depth = 1;
1085 /* restore the clk */
1087 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1090 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1094 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1097 * Enable pll and xtal, initialize the power control registers,
1098 * and force fastclock for the remainder of wlc_up().
1100 wlc_bmac_xtal(wlc_hw, ON);
1101 ai_clkctl_init(wlc_hw->sih);
1102 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1105 * Configure pci/pcmcia here instead of in wlc_attach()
1106 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1108 coremask = (1 << wlc_hw->wlc->core->coreidx);
1110 if (wlc_hw->sih->bustype == PCI_BUS)
1111 ai_pci_setup(wlc_hw->sih, coremask);
1114 * Need to read the hwradio status here to cover the case where the system
1115 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1117 if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1118 /* put SB PCI in down state again */
1119 if (wlc_hw->sih->bustype == PCI_BUS)
1120 ai_pci_down(wlc_hw->sih);
1121 wlc_bmac_xtal(wlc_hw, OFF);
1125 if (wlc_hw->sih->bustype == PCI_BUS)
1126 ai_pci_up(wlc_hw->sih);
1128 /* reset the d11 core */
1129 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1134 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1136 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1139 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1141 /* FULLY enable dynamic power control and d11 core interrupt */
1142 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1143 wl_intrson(wlc_hw->wlc->wl);
1147 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1152 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1157 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1159 /* disable interrupts */
1161 wlc_hw->wlc->macintmask = 0;
1163 /* now disable interrupts */
1164 wl_intrsoff(wlc_hw->wlc->wl);
1166 /* ensure we're running on the pll clock again */
1167 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1169 /* down phy at the last of this stage */
1170 callbacks += wlc_phy_down(wlc_hw->band->pi);
1175 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1180 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1186 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1188 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1191 wlc_hw->sbclk = false;
1192 wlc_hw->clk = false;
1193 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1195 /* reclaim any posted packets */
1196 wlc_flushqueues(wlc_hw->wlc);
1199 /* Reset and disable the core */
1200 if (ai_iscoreup(wlc_hw->sih)) {
1201 if (R_REG(&wlc_hw->regs->maccontrol) &
1203 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1204 callbacks += wl_reset(wlc_hw->wlc->wl);
1205 wlc_coredisable(wlc_hw);
1208 /* turn off primary xtal and pll */
1209 if (!wlc_hw->noreset) {
1210 if (wlc_hw->sih->bustype == PCI_BUS)
1211 ai_pci_down(wlc_hw->sih);
1212 wlc_bmac_xtal(wlc_hw, OFF);
1219 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1221 /* delay before first read of ucode state */
1224 /* wait until ucode is no longer asleep */
1225 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1226 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1229 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1231 memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1234 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1236 return wlc_hw->band->bandtype;
1239 /* control chip clock to save power, enable dynamic clock or force fast clock */
1240 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1242 if (PMUCTL_ENAB(wlc_hw->sih)) {
1243 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1244 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1245 * which means the FCA bit may not be set.
1246 * should wakeup mac if driver wants it to run on HT.
1250 if (mode == CLK_FAST) {
1251 OR_REG(&wlc_hw->regs->clk_ctl_st,
1258 clk_ctl_st) & CCS_HTAVAIL) == 0),
1259 PMU_MAX_TRANSITION_DLY);
1262 clk_ctl_st) & CCS_HTAVAIL));
1264 if ((wlc_hw->sih->pmurev == 0) &&
1267 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1270 clk_ctl_st) & CCS_HTAVAIL)
1272 PMU_MAX_TRANSITION_DLY);
1273 AND_REG(&wlc_hw->regs->clk_ctl_st,
1277 wlc_hw->forcefastclk = (mode == CLK_FAST);
1280 /* old chips w/o PMU, force HT through cc,
1281 * then use FCA to verify mac is running fast clock
1284 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1286 /* check fast clock is available (if core is not in reset) */
1287 if (wlc_hw->forcefastclk && wlc_hw->clk)
1288 WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1291 /* keep the ucode wake bit on if forcefastclk is on
1292 * since we do not want ucode to put us back to slow clock
1293 * when it dozes for PM mode.
1294 * Code below matches the wake override bit with current forcefastclk state
1295 * Only setting bit in wake_override instead of waking ucode immediately
1296 * since old code (wlc.c 1.4499) had this behavior. Older code set
1297 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1298 * (protected by an up check) was executed just below.
1300 if (wlc_hw->forcefastclk)
1301 mboolset(wlc_hw->wake_override,
1302 WLC_WAKE_OVERRIDE_FORCEFAST);
1304 mboolclr(wlc_hw->wake_override,
1305 WLC_WAKE_OVERRIDE_FORCEFAST);
1309 /* set initial host flags value */
1311 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1313 struct wlc_hw_info *wlc_hw = wlc->hw;
1315 memset(mhfs, 0, MHFMAX * sizeof(u16));
1317 mhfs[MHF2] |= mhf2_init;
1319 /* prohibit use of slowclock on multifunction boards */
1320 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1321 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1323 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1324 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1325 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1329 /* set or clear ucode host flag bits
1330 * it has an optimization for no-change write
1331 * it only writes through shared memory when the core has clock;
1332 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1335 * bands values are: WLC_BAND_AUTO <--- Current band only
1336 * WLC_BAND_5G <--- 5G band only
1337 * WLC_BAND_2G <--- 2G band only
1338 * WLC_BAND_ALL <--- All bands
1341 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1345 u16 addr[MHFMAX] = {
1346 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1349 struct wlc_hwband *band;
1351 if ((val & ~mask) || idx >= MHFMAX)
1352 return; /* error condition */
1355 /* Current band only or all bands,
1356 * then set the band to current band
1360 band = wlc_hw->band;
1363 band = wlc_hw->bandstate[BAND_5G_INDEX];
1366 band = wlc_hw->bandstate[BAND_2G_INDEX];
1369 band = NULL; /* error condition */
1373 save = band->mhfs[idx];
1374 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1376 /* optimization: only write through if changed, and
1377 * changed band is the current band
1379 if (wlc_hw->clk && (band->mhfs[idx] != save)
1380 && (band == wlc_hw->band))
1381 wlc_bmac_write_shm(wlc_hw, addr[idx],
1382 (u16) band->mhfs[idx]);
1385 if (bands == WLC_BAND_ALL) {
1386 wlc_hw->bandstate[0]->mhfs[idx] =
1387 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1388 wlc_hw->bandstate[1]->mhfs[idx] =
1389 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1393 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1395 struct wlc_hwband *band;
1398 return 0; /* error condition */
1401 band = wlc_hw->band;
1404 band = wlc_hw->bandstate[BAND_5G_INDEX];
1407 band = wlc_hw->bandstate[BAND_2G_INDEX];
1410 band = NULL; /* error condition */
1416 return band->mhfs[idx];
1419 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1423 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1427 for (idx = 0; idx < MHFMAX; idx++) {
1428 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1432 /* set the maccontrol register to desired reset state and
1433 * initialize the sw cache of the register
1435 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1437 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1438 wlc_hw->maccontrol = 0;
1439 wlc_hw->suspended_fifos = 0;
1440 wlc_hw->wake_override = 0;
1441 wlc_hw->mute_override = 0;
1442 wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1445 /* set or clear maccontrol bits */
1446 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1452 return; /* error condition */
1453 maccontrol = wlc_hw->maccontrol;
1454 new_maccontrol = (maccontrol & ~mask) | val;
1456 /* if the new maccontrol value is the same as the old, nothing to do */
1457 if (new_maccontrol == maccontrol)
1460 /* something changed, cache the new value */
1461 wlc_hw->maccontrol = new_maccontrol;
1463 /* write the new values with overrides applied */
1464 wlc_mctrl_write(wlc_hw);
1467 /* write the software state of maccontrol and overrides to the maccontrol register */
1468 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1470 u32 maccontrol = wlc_hw->maccontrol;
1472 /* OR in the wake bit if overridden */
1473 if (wlc_hw->wake_override)
1474 maccontrol |= MCTL_WAKE;
1476 /* set AP and INFRA bits for mute if needed */
1477 if (wlc_hw->mute_override) {
1478 maccontrol &= ~(MCTL_AP);
1479 maccontrol |= MCTL_INFRA;
1482 W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1485 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1487 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1488 mboolset(wlc_hw->wake_override, override_bit);
1492 mboolset(wlc_hw->wake_override, override_bit);
1494 wlc_mctrl_write(wlc_hw);
1495 wlc_bmac_wait_for_wake(wlc_hw);
1500 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1502 mboolclr(wlc_hw->wake_override, override_bit);
1504 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1507 wlc_mctrl_write(wlc_hw);
1512 /* When driver needs ucode to stop beaconing, it has to make sure that
1513 * MCTL_AP is clear and MCTL_INFRA is set
1514 * Mode MCTL_AP MCTL_INFRA
1516 * STA 0 1 <--- This will ensure no beacons
1519 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1521 wlc_hw->mute_override = 1;
1523 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1524 * override, then there is no change to write
1526 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1529 wlc_mctrl_write(wlc_hw);
1534 /* Clear the override on AP and INFRA bits */
1535 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1537 if (wlc_hw->mute_override == 0)
1540 wlc_hw->mute_override = 0;
1542 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1543 * override, then there is no change to write
1545 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1548 wlc_mctrl_write(wlc_hw);
1552 * Write a MAC address to the given match reg offset in the RXE match engine.
1555 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1563 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
1566 regs = wlc_hw->regs;
1567 mac_l = addr[0] | (addr[1] << 8);
1568 mac_m = addr[2] | (addr[3] << 8);
1569 mac_h = addr[4] | (addr[5] << 8);
1571 /* enter the MAC addr into the RXE match registers */
1572 W_REG(®s->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1573 W_REG(®s->rcm_mat_data, mac_l);
1574 W_REG(®s->rcm_mat_data, mac_m);
1575 W_REG(®s->rcm_mat_data, mac_h);
1580 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1586 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1588 regs = wlc_hw->regs;
1589 W_REG(®s->tplatewrptr, offset);
1591 /* if MCTL_BIGEND bit set in mac control register,
1592 * the chip swaps data in fifo, as well as data in
1595 be_bit = (R_REG(®s->maccontrol) & MCTL_BIGEND) != 0;
1598 memcpy(&word, buf, sizeof(u32));
1601 word = cpu_to_be32(word);
1603 word = cpu_to_le32(word);
1605 W_REG(®s->tplatewrdata, word);
1607 buf = (u8 *) buf + sizeof(u32);
1612 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1614 wlc_hw->band->CWmin = newmin;
1616 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1617 (void)R_REG(&wlc_hw->regs->objaddr);
1618 W_REG(&wlc_hw->regs->objdata, newmin);
1621 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1623 wlc_hw->band->CWmax = newmax;
1625 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1626 (void)R_REG(&wlc_hw->regs->objaddr);
1627 W_REG(&wlc_hw->regs->objdata, newmax);
1630 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1634 /* request FAST clock if not on */
1635 fastclk = wlc_hw->forcefastclk;
1637 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1639 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1641 wlc_bmac_phy_reset(wlc_hw);
1642 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1644 /* restore the clk */
1646 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1650 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1652 d11regs_t *regs = wlc_hw->regs;
1654 wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1656 /* write beacon length to SCR */
1657 wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1658 /* mark beacon0 valid */
1659 OR_REG(®s->maccommand, MCMD_BCN0VLD);
1663 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1665 d11regs_t *regs = wlc_hw->regs;
1667 wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1669 /* write beacon length to SCR */
1670 wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1671 /* mark beacon1 valid */
1672 OR_REG(®s->maccommand, MCMD_BCN1VLD);
1675 /* mac is assumed to be suspended at this point */
1677 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1680 d11regs_t *regs = wlc_hw->regs;
1683 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1684 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1687 if (!(R_REG(®s->maccommand) & MCMD_BCN0VLD))
1688 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1691 (R_REG(®s->maccommand) & MCMD_BCN1VLD))
1692 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1696 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1699 struct wlc_info *wlc = wlc_hw->wlc;
1700 /* update SYNTHPU_DLY */
1702 if (WLCISLCNPHY(wlc->band)) {
1703 v = SYNTHPU_DLY_LPPHY_US;
1704 } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1705 v = SYNTHPU_DLY_NPHY_US;
1707 v = SYNTHPU_DLY_BPHY_US;
1710 wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1713 /* band-specific init */
1715 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1717 struct wlc_hw_info *wlc_hw = wlc->hw;
1719 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1720 wlc_hw->band->bandunit);
1722 wlc_ucode_bsinit(wlc_hw);
1724 wlc_phy_init(wlc_hw->band->pi, chanspec);
1726 wlc_ucode_txant_set(wlc_hw);
1728 /* cwmin is band-specific, update hardware with value for current band */
1729 wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1730 wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1732 wlc_bmac_update_slot_timing(wlc_hw,
1733 BAND_5G(wlc_hw->band->
1734 bandtype) ? true : wlc_hw->
1737 /* write phytype and phyvers */
1738 wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1739 wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1741 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1742 wlc_upd_ofdm_pctl1_table(wlc_hw);
1744 wlc_bmac_upd_synthpu(wlc_hw);
1747 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1749 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1751 wlc_hw->phyclk = clk;
1753 if (OFF == clk) { /* clear gmode bit, put phy into reset */
1755 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1756 (SICF_PRST | SICF_FGC));
1758 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1761 } else { /* take phy out of reset */
1763 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1765 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1771 /* Perform a soft reset of the PHY PLL */
1772 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1774 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1776 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1777 offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1779 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1780 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1782 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1783 offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1785 ai_corereg(wlc_hw->sih, SI_CC_IDX,
1786 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1790 /* light way to turn on phy clock without reset for NPHY only
1791 * refer to wlc_bmac_core_phy_clk for full version
1793 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1795 /* support(necessary for NPHY and HYPHY) only */
1796 if (!WLCISNPHY(wlc_hw->band))
1800 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1802 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1806 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1809 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1811 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1814 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1816 wlc_phy_t *pih = wlc_hw->band->pi;
1818 bool phy_in_reset = false;
1820 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1825 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1827 /* Specific reset sequence required for NPHY rev 3 and 4 */
1828 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1829 NREV_LE(wlc_hw->band->phyrev, 4)) {
1830 /* Set the PHY bandwidth */
1831 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1835 /* Perform a soft reset of the PHY PLL */
1836 wlc_bmac_core_phypll_reset(wlc_hw);
1839 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1840 (SICF_PRST | SICF_PCLKE));
1841 phy_in_reset = true;
1844 ai_core_cflags(wlc_hw->sih,
1845 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1846 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1850 wlc_bmac_core_phy_clk(wlc_hw, ON);
1853 wlc_phy_anacore(pih, ON);
1856 /* switch to and initialize new band */
1858 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1859 chanspec_t chanspec) {
1860 struct wlc_info *wlc = wlc_hw->wlc;
1863 /* Enable the d11 core before accessing it */
1864 if (!ai_iscoreup(wlc_hw->sih)) {
1865 ai_core_reset(wlc_hw->sih, 0, 0);
1866 wlc_mctrl_reset(wlc_hw);
1869 macintmask = wlc_setband_inact(wlc, bandunit);
1874 wlc_bmac_core_phy_clk(wlc_hw, ON);
1876 /* band-specific initializations */
1877 wlc_bmac_bsinit(wlc, chanspec);
1880 * If there are any pending software interrupt bits,
1881 * then replace these with a harmless nonzero value
1882 * so wlc_dpc() will re-enable interrupts when done.
1884 if (wlc->macintstatus)
1885 wlc->macintstatus = MI_DMAINT;
1887 /* restore macintmask */
1888 wl_intrsrestore(wlc->wl, macintmask);
1890 /* ucode should still be suspended.. */
1891 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1894 /* low-level band switch utility routine */
1895 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1897 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1900 wlc_hw->band = wlc_hw->bandstate[bandunit];
1902 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1903 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1905 /* set gmode core flag */
1906 if (wlc_hw->sbclk && !wlc_hw->noreset) {
1907 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1908 ((bandunit == 0) ? SICF_GMODE : 0));
1912 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1915 /* reject unsupported corerev */
1916 if (!VALID_COREREV(wlc_hw->corerev)) {
1917 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1925 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1927 bool goodboard = true;
1928 uint boardrev = wlc_hw->boardrev;
1932 else if (boardrev > 0xff) {
1933 uint brt = (boardrev & 0xf000) >> 12;
1934 uint b0 = (boardrev & 0xf00) >> 8;
1935 uint b1 = (boardrev & 0xf0) >> 4;
1936 uint b2 = boardrev & 0xf;
1938 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1943 if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1949 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1951 const char *varname = "macaddr";
1954 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1955 macaddr = getvar(wlc_hw->vars, varname);
1956 if (macaddr != NULL)
1959 if (NBANDS_HW(wlc_hw) > 1)
1960 varname = "et1macaddr";
1962 varname = "il0macaddr";
1964 macaddr = getvar(wlc_hw->vars, varname);
1965 if (macaddr == NULL) {
1966 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1967 "getvar(%s) not found\n", wlc_hw->unit, varname);
1974 * Return true if radio is disabled, otherwise false.
1975 * hw radio disable signal is an external pin, users activate it asynchronously
1976 * this function could be called when driver is down and w/o clock
1977 * it operates on different registers depending on corerev and boardflag.
1979 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
1982 u32 resetbits = 0, flags = 0;
1984 xtal = wlc_hw->sbclk;
1986 wlc_bmac_xtal(wlc_hw, ON);
1988 /* may need to take core out of reset first */
1992 * mac no longer enables phyclk automatically when driver
1993 * accesses phyreg throughput mac. This can be skipped since
1994 * only mac reg is accessed below
1996 flags |= SICF_PCLKE;
1998 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1999 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2000 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2001 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2003 (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2005 ai_core_reset(wlc_hw->sih, flags, resetbits);
2006 wlc_mctrl_reset(wlc_hw);
2009 v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2011 /* put core back into reset */
2013 ai_core_disable(wlc_hw->sih, 0);
2016 wlc_bmac_xtal(wlc_hw, OFF);
2021 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2022 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2024 if (wlc_hw->wlc->pub->hw_up)
2027 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2030 * Enable pll and xtal, initialize the power control registers,
2031 * and force fastclock for the remainder of wlc_up().
2033 wlc_bmac_xtal(wlc_hw, ON);
2034 ai_clkctl_init(wlc_hw->sih);
2035 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2037 if (wlc_hw->sih->bustype == PCI_BUS) {
2038 ai_pci_fixcfg(wlc_hw->sih);
2040 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2041 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2042 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2043 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2045 (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2049 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2050 wlc_phy_por_inform(wlc_hw->band->pi);
2052 wlc_hw->ucode_loaded = false;
2053 wlc_hw->wlc->pub->hw_up = true;
2055 if ((wlc_hw->boardflags & BFL_FEM)
2056 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2058 (wlc_hw->boardrev >= 0x1250
2059 && (wlc_hw->boardflags & BFL_FEM_BT)))
2060 ai_epa_4313war(wlc_hw->sih);
2064 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2066 struct hnddma_pub *di = wlc_hw->di[fifo];
2067 return dma_rxreset(di);
2071 * ensure fask clock during reset
2073 * reset d11(out of reset)
2074 * reset phy(out of reset)
2075 * clear software macintstatus for fresh new start
2076 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2078 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2085 if (flags == WLC_USE_COREFLAGS)
2086 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2088 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2090 regs = wlc_hw->regs;
2092 /* request FAST clock if not on */
2093 fastclk = wlc_hw->forcefastclk;
2095 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2097 /* reset the dma engines except first time thru */
2098 if (ai_iscoreup(wlc_hw->sih)) {
2099 for (i = 0; i < NFIFO; i++)
2100 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2101 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2102 "dma_txreset[%d]: cannot stop dma\n",
2103 wlc_hw->unit, __func__, i);
2106 if ((wlc_hw->di[RX_FIFO])
2107 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2108 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2109 "[%d]: cannot stop dma\n",
2110 wlc_hw->unit, __func__, RX_FIFO);
2113 /* if noreset, just stop the psm and return */
2114 if (wlc_hw->noreset) {
2115 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2116 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2121 * mac no longer enables phyclk automatically when driver accesses
2122 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2123 * band->pi is invalid. need to enable PHY CLK
2125 flags |= SICF_PCLKE;
2128 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2129 * is cleared by the core_reset. have to re-request it.
2130 * This adds some delay and we can optimize it by also requesting fastclk through
2131 * chipcommon during this period if necessary. But that has to work coordinate
2132 * with other driver like mips/arm since they may touch chipcommon as well.
2134 wlc_hw->clk = false;
2135 ai_core_reset(wlc_hw->sih, flags, resetbits);
2137 if (wlc_hw->band && wlc_hw->band->pi)
2138 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2140 wlc_mctrl_reset(wlc_hw);
2142 if (PMUCTL_ENAB(wlc_hw->sih))
2143 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2145 wlc_bmac_phy_reset(wlc_hw);
2147 /* turn on PHY_PLL */
2148 wlc_bmac_core_phypll_ctl(wlc_hw, true);
2150 /* clear sw intstatus */
2151 wlc_hw->wlc->macintstatus = 0;
2153 /* restore the clk setting */
2155 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2158 /* txfifo sizes needs to be modified(increased) since the newer cores
2161 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2163 d11regs_t *regs = wlc_hw->regs;
2165 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2166 u16 txfifo_def, txfifo_def1;
2169 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2170 txfifo_startblk = TXFIFO_START_BLK;
2172 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2173 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2175 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2176 txfifo_def = (txfifo_startblk & 0xff) |
2177 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2178 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2180 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2182 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2184 W_REG(®s->xmtfifocmd, txfifo_cmd);
2185 W_REG(®s->xmtfifodef, txfifo_def);
2186 W_REG(®s->xmtfifodef1, txfifo_def1);
2188 W_REG(®s->xmtfifocmd, txfifo_cmd);
2190 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2193 * need to propagate to shm location to be in sync since ucode/hw won't
2196 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2197 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2198 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2199 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2200 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2201 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2202 xmtfifo_sz[TX_AC_BK_FIFO]));
2203 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2204 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2205 xmtfifo_sz[TX_BCMC_FIFO]));
2210 * download ucode/PCM
2211 * let ucode run to suspended
2212 * download ucode inits
2213 * config other core registers
2216 static void wlc_coreinit(struct wlc_info *wlc)
2218 struct wlc_hw_info *wlc_hw = wlc->hw;
2223 bool fifosz_fixup = false;
2226 struct wiphy *wiphy = wlc->wiphy;
2228 regs = wlc_hw->regs;
2230 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2233 wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2235 wlc_ucode_download(wlc_hw);
2237 * FIFOSZ fixup. driver wants to controls the fifo allocation.
2239 fifosz_fixup = true;
2241 /* let the PSM run to the suspended state, set mode to BSS STA */
2242 W_REG(®s->macintstatus, -1);
2243 wlc_bmac_mctrl(wlc_hw, ~0,
2244 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2246 /* wait for ucode to self-suspend after auto-init */
2247 SPINWAIT(((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0),
2249 if ((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0)
2250 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2251 "suspend!\n", wlc_hw->unit);
2255 sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2257 if (D11REV_IS(wlc_hw->corerev, 23)) {
2258 if (WLCISNPHY(wlc_hw->band))
2259 wlc_write_inits(wlc_hw, d11n0initvals16);
2261 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2262 " %d\n", __func__, wlc_hw->unit,
2264 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2265 if (WLCISLCNPHY(wlc_hw->band)) {
2266 wlc_write_inits(wlc_hw, d11lcn0initvals24);
2268 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2269 " %d\n", __func__, wlc_hw->unit,
2273 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2274 __func__, wlc_hw->unit, wlc_hw->corerev);
2277 /* For old ucode, txfifo sizes needs to be modified(increased) */
2278 if (fifosz_fixup == true) {
2279 wlc_corerev_fifofixup(wlc_hw);
2282 /* check txfifo allocations match between ucode and driver */
2283 buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2284 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2288 buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2289 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2293 buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2294 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2295 buf[TX_AC_BK_FIFO] &= 0xff;
2296 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2300 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2304 buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2305 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2306 buf[TX_BCMC_FIFO] &= 0xff;
2307 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2311 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2316 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2317 " driver size %d index %d\n", buf[i],
2318 wlc_hw->xmtfifo_sz[i], i);
2321 /* make sure we can still talk to the mac */
2322 WARN_ON(R_REG(®s->maccontrol) == 0xffffffff);
2324 /* band-specific inits done by wlc_bsinit() */
2326 /* Set up frame burst size and antenna swap threshold init values */
2327 wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2328 wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2330 /* enable one rx interrupt per received frame */
2331 W_REG(®s->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2333 /* set the station mode (BSS STA) */
2334 wlc_bmac_mctrl(wlc_hw,
2335 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2336 (MCTL_INFRA | MCTL_DISCARD_PMQ));
2338 /* set up Beacon interval */
2339 bcnint_us = 0x8000 << 10;
2340 W_REG(®s->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2341 W_REG(®s->tsf_cfpstart, bcnint_us);
2342 W_REG(®s->macintstatus, MI_GP1);
2344 /* write interrupt mask */
2345 W_REG(®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2347 /* allow the MAC to control the PHY clock (dynamic on/off) */
2348 wlc_bmac_macphyclk_set(wlc_hw, ON);
2350 /* program dynamic clock control fast powerup delay register */
2351 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2352 W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2354 /* tell the ucode the corerev */
2355 wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2357 /* tell the ucode MAC capabilities */
2358 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2359 (u16) (wlc_hw->machwcap & 0xffff));
2360 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2362 machwcap >> 16) & 0xffff));
2364 /* write retry limits to SCR, this done after PSM init */
2365 W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2366 (void)R_REG(®s->objaddr);
2367 W_REG(®s->objdata, wlc_hw->SRL);
2368 W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2369 (void)R_REG(®s->objaddr);
2370 W_REG(®s->objdata, wlc_hw->LRL);
2372 /* write rate fallback retry limits */
2373 wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2374 wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2376 AND_REG(®s->ifs_ctl, 0x0FFF);
2377 W_REG(®s->ifs_aifsn, EDCF_AIFSN_MIN);
2379 /* dma initializations */
2380 wlc->txpend16165war = 0;
2382 /* init the tx dma engines */
2383 for (i = 0; i < NFIFO; i++) {
2385 dma_txinit(wlc_hw->di[i]);
2388 /* init the rx dma engine(s) and post receive buffers */
2389 dma_rxinit(wlc_hw->di[RX_FIFO]);
2390 dma_rxfill(wlc_hw->di[RX_FIFO]);
2393 /* This function is used for changing the tsf frac register
2394 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2395 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2396 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2397 * HTPHY Formula is 2^26/freq(MHz) e.g.
2398 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2399 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2400 * For spuron: 123MHz -> 2^26/123 = 545600.5
2401 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2402 * For spur off: 120MHz -> 2^26/120 = 559240.5
2403 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2406 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2409 regs = wlc_hw->regs;
2411 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2412 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2413 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2414 W_REG(®s->tsf_clk_frac_l, 0x2082);
2415 W_REG(®s->tsf_clk_frac_h, 0x8);
2416 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2417 W_REG(®s->tsf_clk_frac_l, 0x5341);
2418 W_REG(®s->tsf_clk_frac_h, 0x8);
2419 } else { /* 120Mhz */
2420 W_REG(®s->tsf_clk_frac_l, 0x8889);
2421 W_REG(®s->tsf_clk_frac_h, 0x8);
2423 } else if (WLCISLCNPHY(wlc_hw->band)) {
2424 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2425 W_REG(®s->tsf_clk_frac_l, 0x7CE0);
2426 W_REG(®s->tsf_clk_frac_h, 0xC);
2427 } else { /* 80Mhz */
2428 W_REG(®s->tsf_clk_frac_l, 0xCCCD);
2429 W_REG(®s->tsf_clk_frac_h, 0xC);
2434 /* Initialize GPIOs that are controlled by D11 core */
2435 static void wlc_gpio_init(struct wlc_info *wlc)
2437 struct wlc_hw_info *wlc_hw = wlc->hw;
2441 regs = wlc_hw->regs;
2443 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2444 wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2447 * Common GPIO setup:
2448 * G0 = LED 0 = WLAN Activity
2449 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2450 * G2 = LED 2 = WLAN 5 GHz Radio State
2451 * G4 = radio disable input (HI enabled, LO disabled)
2456 /* Allocate GPIOs for mimo antenna diversity feature */
2457 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2458 /* Enable antenna diversity, use 2x3 mode */
2459 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2460 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2461 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2462 MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2464 /* init superswitch control */
2465 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2467 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2468 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2470 * The board itself is powered by these GPIOs
2471 * (when not sending pattern) so set them high
2473 OR_REG(®s->psm_gpio_oe,
2474 (BOARD_GPIO_12 | BOARD_GPIO_13));
2475 OR_REG(®s->psm_gpio_out,
2476 (BOARD_GPIO_12 | BOARD_GPIO_13));
2478 /* Enable antenna diversity, use 2x4 mode */
2479 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2480 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2481 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2484 /* Configure the desired clock to be 4Mhz */
2485 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2486 ANTSEL_CLKDIV_4MHZ);
2489 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2490 if (wlc_hw->boardflags & BFL_PACTRL)
2491 gm |= gc |= BOARD_GPIO_PACTRL;
2493 /* apply to gpiocontrol register */
2494 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2497 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2499 struct wlc_info *wlc;
2502 if (wlc_hw->ucode_loaded)
2505 if (D11REV_IS(wlc_hw->corerev, 23)) {
2506 if (WLCISNPHY(wlc_hw->band)) {
2507 wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2509 wlc_hw->ucode_loaded = true;
2511 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2513 __func__, wlc_hw->unit, wlc_hw->corerev);
2514 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2515 if (WLCISLCNPHY(wlc_hw->band)) {
2516 wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2518 wlc_hw->ucode_loaded = true;
2520 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2522 __func__, wlc_hw->unit, wlc_hw->corerev);
2527 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2528 const uint nbytes) {
2529 d11regs_t *regs = wlc_hw->regs;
2533 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2535 count = (nbytes / sizeof(u32));
2537 W_REG(®s->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2538 (void)R_REG(®s->objaddr);
2539 for (i = 0; i < count; i++)
2540 W_REG(®s->objdata, ucode[i]);
2543 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2544 const struct d11init *inits)
2549 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2551 base = (volatile u8 *)wlc_hw->regs;
2553 for (i = 0; inits[i].addr != 0xffff; i++) {
2554 if (inits[i].size == 2)
2555 W_REG((u16 *)(base + inits[i].addr),
2557 else if (inits[i].size == 4)
2558 W_REG((u32 *)(base + inits[i].addr),
2563 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2566 u16 phytxant = wlc_hw->bmac_phytxant;
2567 u16 mask = PHY_TXC_ANT_MASK;
2569 /* set the Probe Response frame phy control word */
2570 phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2571 phyctl = (phyctl & ~mask) | phytxant;
2572 wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2574 /* set the Response (ACK/CTS) frame phy control word */
2575 phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2576 phyctl = (phyctl & ~mask) | phytxant;
2577 wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2580 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2582 /* update sw state */
2583 wlc_hw->bmac_phytxant = phytxant;
2585 /* push to ucode if up */
2588 wlc_ucode_txant_set(wlc_hw);
2592 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2594 return (u16) wlc_hw->wlc->stf->txant;
2597 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2599 wlc_hw->antsel_type = antsel_type;
2601 /* Update the antsel type for phy module to use */
2602 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2605 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2609 uint intstatus, idx;
2610 d11regs_t *regs = wlc_hw->regs;
2611 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2613 unit = wlc_hw->unit;
2615 for (idx = 0; idx < NFIFO; idx++) {
2616 /* read intstatus register and ignore any non-error bits */
2618 R_REG(®s->intctrlregs[idx].intstatus) & I_ERRORS;
2622 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2623 unit, idx, intstatus);
2625 if (intstatus & I_RO) {
2626 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2627 "overflow\n", unit, idx);
2631 if (intstatus & I_PC) {
2632 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2637 if (intstatus & I_PD) {
2638 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2643 if (intstatus & I_DE) {
2644 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2645 "error\n", unit, idx);
2649 if (intstatus & I_RU) {
2650 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2651 "underflow\n", idx, unit);
2654 if (intstatus & I_XU) {
2655 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2656 "underflow\n", idx, unit);
2661 wlc_fatal_error(wlc_hw->wlc); /* big hammer */
2664 W_REG(®s->intctrlregs[idx].intstatus,
2669 void wlc_intrson(struct wlc_info *wlc)
2671 struct wlc_hw_info *wlc_hw = wlc->hw;
2672 wlc->macintmask = wlc->defmacintmask;
2673 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2676 /* callback for siutils.c, which has only wlc handler, no wl
2677 * they both check up, not only because there is no need to off/restore d11 interrupt
2678 * but also because per-port code may require sync with valid interrupt.
2681 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2686 return wl_intrsoff(wlc->wl);
2689 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2694 wl_intrsrestore(wlc->wl, macintmask);
2697 u32 wlc_intrsoff(struct wlc_info *wlc)
2699 struct wlc_hw_info *wlc_hw = wlc->hw;
2705 macintmask = wlc->macintmask; /* isr can still happen */
2707 W_REG(&wlc_hw->regs->macintmask, 0);
2708 (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2709 udelay(1); /* ensure int line is no longer driven */
2710 wlc->macintmask = 0;
2712 /* return previous macintmask; resolve race between us and our isr */
2713 return wlc->macintstatus ? 0 : macintmask;
2716 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2718 struct wlc_hw_info *wlc_hw = wlc->hw;
2722 wlc->macintmask = macintmask;
2723 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2726 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2728 u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2731 /* suspend tx fifos */
2732 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2733 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2734 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2735 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2737 /* zero the address match register so we do not send ACKs */
2738 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2741 /* resume tx fifos */
2742 if (!wlc_hw->wlc->tx_suspended) {
2743 wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2745 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2746 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2747 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2749 /* Restore address */
2750 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2754 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2757 wlc_ucode_mute_override_set(wlc_hw);
2759 wlc_ucode_mute_override_clear(wlc_hw);
2762 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2767 *blocks = wlc_hw->xmtfifo_sz[fifo];
2772 /* wlc_bmac_tx_fifo_suspended:
2773 * Check the MAC's tx suspend status for a tx fifo.
2775 * When the MAC acknowledges a tx suspend, it indicates that no more
2776 * packets will be transmitted out the radio. This is independent of
2777 * DMA channel suspension---the DMA may have finished suspending, or may still
2778 * be pulling data into a tx fifo, by the time the MAC acks the suspend
2781 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2783 /* check that a suspend has been requested and is no longer pending */
2786 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2787 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2788 * chnstatus register.
2789 * The tx fifo suspend completion is independent of the DMA suspend completion and
2790 * may be acked before or after the DMA is suspended.
2792 if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2793 (R_REG(&wlc_hw->regs->chnstatus) &
2794 (1 << tx_fifo)) == 0)
2800 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2802 u8 fifo = 1 << tx_fifo;
2804 /* Two clients of this code, 11h Quiet period and scanning. */
2806 /* only suspend if not already suspended */
2807 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2810 /* force the core awake only if not already */
2811 if (wlc_hw->suspended_fifos == 0)
2812 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2814 wlc_hw->suspended_fifos |= fifo;
2816 if (wlc_hw->di[tx_fifo]) {
2817 /* Suspending AMPDU transmissions in the middle can cause underflow
2818 * which may result in mismatch between ucode and driver
2819 * so suspend the mac before suspending the FIFO
2821 if (WLC_PHY_11N_CAP(wlc_hw->band))
2822 wlc_suspend_mac_and_wait(wlc_hw->wlc);
2824 dma_txsuspend(wlc_hw->di[tx_fifo]);
2826 if (WLC_PHY_11N_CAP(wlc_hw->band))
2827 wlc_enable_mac(wlc_hw->wlc);
2831 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2833 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2834 * here for PIO otherwise the watchdog will catch the inconsistency and fire
2836 /* Two clients of this code, 11h Quiet period and scanning. */
2837 if (wlc_hw->di[tx_fifo])
2838 dma_txresume(wlc_hw->di[tx_fifo]);
2840 /* allow core to sleep again */
2841 if (wlc_hw->suspended_fifos == 0)
2844 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2845 if (wlc_hw->suspended_fifos == 0)
2846 wlc_ucode_wake_override_clear(wlc_hw,
2847 WLC_WAKE_OVERRIDE_TXFIFO);
2852 * Read and clear macintmask and macintstatus and intstatus registers.
2853 * This routine should be called with interrupts off
2855 * -1 if DEVICEREMOVED(wlc) evaluates to true;
2856 * 0 if the interrupt is not for us, or we are in some special cases;
2857 * device interrupt status bits otherwise.
2859 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2861 struct wlc_hw_info *wlc_hw = wlc->hw;
2862 d11regs_t *regs = wlc_hw->regs;
2865 /* macintstatus includes a DMA interrupt summary bit */
2866 macintstatus = R_REG(®s->macintstatus);
2868 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2871 /* detect cardbus removed, in power down(suspend) and in reset */
2872 if (DEVICEREMOVED(wlc))
2875 /* DEVICEREMOVED succeeds even when the core is still resetting,
2876 * handle that case here.
2878 if (macintstatus == 0xffffffff)
2881 /* defer unsolicited interrupts */
2882 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2885 if (macintstatus == 0)
2888 /* interrupts are already turned off for CFE build
2889 * Caution: For CFE Turning off the interrupts again has some undesired
2892 /* turn off the interrupts */
2893 W_REG(®s->macintmask, 0);
2894 (void)R_REG(®s->macintmask); /* sync readback */
2895 wlc->macintmask = 0;
2897 /* clear device interrupts */
2898 W_REG(®s->macintstatus, macintstatus);
2900 /* MI_DMAINT is indication of non-zero intstatus */
2901 if (macintstatus & MI_DMAINT) {
2903 * only fifo interrupt enabled is I_RI in
2904 * RX_FIFO. If MI_DMAINT is set, assume it
2905 * is set and clear the interrupt.
2907 W_REG(®s->intctrlregs[RX_FIFO].intstatus,
2911 return macintstatus;
2914 /* Update wlc->macintstatus and wlc->intstatus[]. */
2915 /* Return true if they are updated successfully. false otherwise */
2916 bool wlc_intrsupd(struct wlc_info *wlc)
2920 /* read and clear macintstatus and intstatus registers */
2921 macintstatus = wlc_intstatus(wlc, false);
2923 /* device is removed */
2924 if (macintstatus == 0xffffffff)
2927 /* update interrupt status in software */
2928 wlc->macintstatus |= macintstatus;
2934 * First-level interrupt processing.
2935 * Return true if this was our interrupt, false otherwise.
2936 * *wantdpc will be set to true if further wlc_dpc() processing is required,
2939 bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2941 struct wlc_hw_info *wlc_hw = wlc->hw;
2946 if (!wlc_hw->up || !wlc->macintmask)
2949 /* read and clear macintstatus and intstatus registers */
2950 macintstatus = wlc_intstatus(wlc, true);
2952 if (macintstatus == 0xffffffff)
2953 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2956 /* it is not for us */
2957 if (macintstatus == 0)
2962 /* save interrupt status bits */
2963 wlc->macintstatus = macintstatus;
2970 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2972 /* discard intermediate indications for ucode with one legitimate case:
2973 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2974 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2975 * transmission count)
2977 if (!(txs->status & TX_STATUS_AMPDU)
2978 && (txs->status & TX_STATUS_INTERMEDIATE)) {
2982 return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
2985 /* process tx completion events in BMAC
2986 * Return true if more tx status need to be processed. false otherwise.
2989 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
2991 bool morepending = false;
2992 struct wlc_info *wlc = wlc_hw->wlc;
2994 tx_status_t txstatus, *txs;
2998 * Param 'max_tx_num' indicates max. # tx status to process before
3001 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3003 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3006 regs = wlc_hw->regs;
3008 && (s1 = R_REG(®s->frmtxstatus)) & TXS_V) {
3010 if (s1 == 0xffffffff) {
3011 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
3012 wlc_hw->unit, __func__);
3016 s2 = R_REG(®s->frmtxstatus2);
3018 txs->status = s1 & TXS_STATUS_MASK;
3019 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3020 txs->sequence = s2 & TXS_SEQ_MASK;
3021 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3022 txs->lasttxtime = 0;
3024 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3026 /* !give others some time to run! */
3027 if (++n >= max_tx_num)
3034 if (n >= max_tx_num)
3037 if (!pktq_empty(&wlc->pkt_queue->q))
3043 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3045 struct wlc_hw_info *wlc_hw = wlc->hw;
3046 d11regs_t *regs = wlc_hw->regs;
3048 struct wiphy *wiphy = wlc->wiphy;
3050 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3051 wlc_hw->band->bandunit);
3054 * Track overlapping suspend requests
3056 wlc_hw->mac_suspend_depth++;
3057 if (wlc_hw->mac_suspend_depth > 1)
3060 /* force the core awake */
3061 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3063 mc = R_REG(®s->maccontrol);
3065 if (mc == 0xffffffff) {
3066 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3071 WARN_ON(mc & MCTL_PSM_JMP_0);
3072 WARN_ON(!(mc & MCTL_PSM_RUN));
3073 WARN_ON(!(mc & MCTL_EN_MAC));
3075 mi = R_REG(®s->macintstatus);
3076 if (mi == 0xffffffff) {
3077 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3082 WARN_ON(mi & MI_MACSSPNDD);
3084 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3086 SPINWAIT(!(R_REG(®s->macintstatus) & MI_MACSSPNDD),
3087 WLC_MAX_MAC_SUSPEND);
3089 if (!(R_REG(®s->macintstatus) & MI_MACSSPNDD)) {
3090 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3091 " and MI_MACSSPNDD is still not on.\n",
3092 wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3093 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3094 "psm_brc 0x%04x\n", wlc_hw->unit,
3095 R_REG(®s->psmdebug),
3096 R_REG(®s->phydebug),
3097 R_REG(®s->psm_brc));
3100 mc = R_REG(®s->maccontrol);
3101 if (mc == 0xffffffff) {
3102 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3107 WARN_ON(mc & MCTL_PSM_JMP_0);
3108 WARN_ON(!(mc & MCTL_PSM_RUN));
3109 WARN_ON(mc & MCTL_EN_MAC);
3112 void wlc_enable_mac(struct wlc_info *wlc)
3114 struct wlc_hw_info *wlc_hw = wlc->hw;
3115 d11regs_t *regs = wlc_hw->regs;
3118 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3119 wlc->band->bandunit);
3122 * Track overlapping suspend requests
3124 wlc_hw->mac_suspend_depth--;
3125 if (wlc_hw->mac_suspend_depth > 0)
3128 mc = R_REG(®s->maccontrol);
3129 WARN_ON(mc & MCTL_PSM_JMP_0);
3130 WARN_ON(mc & MCTL_EN_MAC);
3131 WARN_ON(!(mc & MCTL_PSM_RUN));
3133 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3134 W_REG(®s->macintstatus, MI_MACSSPNDD);
3136 mc = R_REG(®s->maccontrol);
3137 WARN_ON(mc & MCTL_PSM_JMP_0);
3138 WARN_ON(!(mc & MCTL_EN_MAC));
3139 WARN_ON(!(mc & MCTL_PSM_RUN));
3141 mi = R_REG(®s->macintstatus);
3142 WARN_ON(mi & MI_MACSSPNDD);
3144 wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3147 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3151 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3152 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3158 if (!WLC_PHY_11N_CAP(wlc_hw->band))
3161 /* walk the phy rate table and update the entries */
3162 for (i = 0; i < ARRAY_SIZE(rates); i++) {
3165 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3167 /* read the SHM Rate Table entry OFDM PCTL1 values */
3169 wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3171 /* modify the value */
3172 pctl1 &= ~PHY_TXC1_MODE_MASK;
3173 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3175 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3176 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3181 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3185 struct plcp_signal_rate_lookup {
3189 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3190 const struct plcp_signal_rate_lookup rate_lookup[] = {
3193 {WLC_RATE_12M, 0xA},
3194 {WLC_RATE_18M, 0xE},
3195 {WLC_RATE_24M, 0x9},
3196 {WLC_RATE_36M, 0xD},
3197 {WLC_RATE_48M, 0x8},
3201 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3202 if (rate == rate_lookup[i].rate) {
3203 plcp_rate = rate_lookup[i].signal_rate;
3208 /* Find the SHM pointer to the rate table entry by looking in the
3211 return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3214 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3216 wlc_hw->hw_stf_ss_opmode = stf_mode;
3219 wlc_upd_ofdm_pctl1_table(wlc_hw);
3223 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3226 d11regs_t *regs = wlc_hw->regs;
3228 /* read the tsf timer low, then high to get an atomic read */
3229 *tsf_l_ptr = R_REG(®s->tsf_timerlow);
3230 *tsf_h_ptr = R_REG(®s->tsf_timerhigh);
3235 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3239 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3241 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3243 regs = wlc_hw->regs;
3245 /* Validate dchip register access */
3247 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3248 (void)R_REG(®s->objaddr);
3249 w = R_REG(®s->objdata);
3251 /* Can we write and read back a 32bit register? */
3252 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3253 (void)R_REG(®s->objaddr);
3254 W_REG(®s->objdata, (u32) 0xaa5555aa);
3256 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3257 (void)R_REG(®s->objaddr);
3258 val = R_REG(®s->objdata);
3259 if (val != (u32) 0xaa5555aa) {
3260 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3261 "expected 0xaa5555aa\n", wlc_hw->unit, val);
3265 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3266 (void)R_REG(®s->objaddr);
3267 W_REG(®s->objdata, (u32) 0x55aaaa55);
3269 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3270 (void)R_REG(®s->objaddr);
3271 val = R_REG(®s->objdata);
3272 if (val != (u32) 0x55aaaa55) {
3273 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3274 "expected 0x55aaaa55\n", wlc_hw->unit, val);
3278 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3279 (void)R_REG(®s->objaddr);
3280 W_REG(®s->objdata, w);
3282 /* clear CFPStart */
3283 W_REG(®s->tsf_cfpstart, 0);
3285 w = R_REG(®s->maccontrol);
3286 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3287 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3288 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3289 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3290 (MCTL_IHR_EN | MCTL_WAKE),
3291 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3298 #define PHYPLL_WAIT_US 100000
3300 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3305 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3308 regs = wlc_hw->regs;
3311 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3312 OR_REG(®s->clk_ctl_st,
3313 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3314 CCS_ERSRC_REQ_PHYPLL));
3315 SPINWAIT((R_REG(®s->clk_ctl_st) &
3316 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3319 tmp = R_REG(®s->clk_ctl_st);
3320 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3321 (CCS_ERSRC_AVAIL_HT)) {
3322 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3323 " PLL failed\n", __func__);
3326 OR_REG(®s->clk_ctl_st,
3327 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3328 SPINWAIT((R_REG(®s->clk_ctl_st) &
3329 (CCS_ERSRC_AVAIL_D11PLL |
3330 CCS_ERSRC_AVAIL_PHYPLL)) !=
3331 (CCS_ERSRC_AVAIL_D11PLL |
3332 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3334 tmp = R_REG(®s->clk_ctl_st);
3336 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3338 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3339 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3340 "PHY PLL failed\n", __func__);
3344 /* Since the PLL may be shared, other cores can still be requesting it;
3345 * so we'll deassert the request but not wait for status to comply.
3347 AND_REG(®s->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3348 tmp = R_REG(®s->clk_ctl_st);
3352 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3356 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3358 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3363 if (wlc_hw->noreset)
3367 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3369 /* turn off analog core */
3370 wlc_phy_anacore(wlc_hw->band->pi, OFF);
3372 /* turn off PHYPLL to save power */
3373 wlc_bmac_core_phypll_ctl(wlc_hw, false);
3375 /* No need to set wlc->pub->radio_active = OFF
3376 * because this function needs down capability and
3377 * radio_active is designed for BCMNODOWN.
3380 /* remove gpio controls */
3381 if (wlc_hw->ucode_dbgsel)
3382 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3384 wlc_hw->clk = false;
3385 ai_core_disable(wlc_hw->sih, 0);
3386 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3389 /* power both the pll and external oscillator on/off */
3390 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3392 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3394 /* dont power down if plldown is false or we must poll hw radio disable */
3395 if (!want && wlc_hw->pllreq)
3399 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3401 wlc_hw->sbclk = want;
3402 if (!wlc_hw->sbclk) {
3403 wlc_hw->clk = false;
3404 if (wlc_hw->band && wlc_hw->band->pi)
3405 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3409 static void wlc_flushqueues(struct wlc_info *wlc)
3411 struct wlc_hw_info *wlc_hw = wlc->hw;
3414 wlc->txpend16165war = 0;
3416 /* free any posted tx packets */
3417 for (i = 0; i < NFIFO; i++)
3418 if (wlc_hw->di[i]) {
3419 dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3420 TXPKTPENDCLR(wlc, i);
3421 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3424 /* free any posted rx packets */
3425 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3428 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3430 return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3433 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3435 wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3439 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3441 d11regs_t *regs = wlc_hw->regs;
3442 volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
3443 volatile u16 *objdata_hi = objdata_lo + 1;
3446 W_REG(®s->objaddr, sel | (offset >> 2));
3447 (void)R_REG(®s->objaddr);
3449 v = R_REG(objdata_hi);
3451 v = R_REG(objdata_lo);
3458 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3460 d11regs_t *regs = wlc_hw->regs;
3461 volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
3462 volatile u16 *objdata_hi = objdata_lo + 1;
3464 W_REG(®s->objaddr, sel | (offset >> 2));
3465 (void)R_REG(®s->objaddr);
3467 W_REG(objdata_hi, v);
3469 W_REG(objdata_lo, v);
3473 /* Copy a buffer to shared memory of specified type .
3474 * SHM 'offset' needs to be an even address and
3475 * Buffer length 'len' must be an even number of bytes
3476 * 'sel' selects the type of memory
3479 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3483 const u8 *p = (const u8 *)buf;
3486 if (len <= 0 || (offset & 1) || (len & 1))
3489 for (i = 0; i < len; i += 2) {
3490 v = p[i] | (p[i + 1] << 8);
3491 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3495 /* Copy a piece of shared memory of specified type to a buffer .
3496 * SHM 'offset' needs to be an even address and
3497 * Buffer length 'len' must be an even number of bytes
3498 * 'sel' selects the type of memory
3501 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3508 if (len <= 0 || (offset & 1) || (len & 1))
3511 for (i = 0; i < len; i += 2) {
3512 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3514 p[i + 1] = (v >> 8) & 0xFF;
3518 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3520 BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3523 *buf = wlc_hw->vars;
3524 *len = wlc_hw->vars_size;
3527 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3532 /* write retry limit to SCR, shouldn't need to suspend */
3534 W_REG(&wlc_hw->regs->objaddr,
3535 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3536 (void)R_REG(&wlc_hw->regs->objaddr);
3537 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3538 W_REG(&wlc_hw->regs->objaddr,
3539 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3540 (void)R_REG(&wlc_hw->regs->objaddr);
3541 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3545 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3548 if (mboolisset(wlc_hw->pllreq, req_bit))
3551 mboolset(wlc_hw->pllreq, req_bit);
3553 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3554 if (!wlc_hw->sbclk) {
3555 wlc_bmac_xtal(wlc_hw, ON);
3559 if (!mboolisset(wlc_hw->pllreq, req_bit))
3562 mboolclr(wlc_hw->pllreq, req_bit);
3564 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3565 if (wlc_hw->sbclk) {
3566 wlc_bmac_xtal(wlc_hw, OFF);
3574 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3579 /* get the phy specific rate encoding for the PLCP SIGNAL field */
3580 /* XXX4321 fixup needed ? */
3582 table_ptr = M_RT_DIRMAP_A;
3584 table_ptr = M_RT_DIRMAP_B;
3586 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3587 * the index into the rate table.
3589 phy_rate = rate_info[rate] & WLC_RATE_MASK;
3590 index = phy_rate & 0xf;
3592 /* Find the SHM pointer to the rate table entry by looking in the
3595 return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3598 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3600 wlc_hw->antsel_avail = antsel_avail;