drivers/staging/brcm80211/sys/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef WLC_LOW
  18 #error "This file needs WLC_LOW"
  19 #endif
  20
  21 #include <wlc_cfg.h>
  22 #include <typedefs.h>
  23 #include <linuxver.h>
  24 #include <bcmdefs.h>
  25 #include <osl.h>
  26 #include <linux/kernel.h>
  27 #include <proto/802.11.h>
  28 #include <bcmwifi.h>
  29 #include <bcmutils.h>
  30 #include <siutils.h>
  31 #include <bcmendian.h>
  32 #include <wlioctl.h>
  33 #include <sbconfig.h>
  34 #include <sbchipc.h>
  35 #include <pcicfg.h>
  36 #include <sbhndpio.h>
  37 #include <sbhnddma.h>
  38 #include <hnddma.h>
  39 #include <hndpmu.h>
  40 #include <d11.h>
  41 #include <wlc_rate.h>
  42 #include <wlc_pub.h>
  43 #include <wlc_channel.h>
  44 #include <bcmsrom.h>
  45 #include <wlc_key.h>
  46 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
  47  * dependencies. Need to include these to files to allow a clean include of wlc.h
  48  * with WLC_HIGH defined.
  49  * At some point we may be able to skip the include of wlc.h and instead just
  50  * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
  51  */
  52 #include <wlc_mac80211.h>
  53 #include <wlc_bmac.h>
  54 #include <wlc_phy_shim.h>
  55 #include <wlc_phy_hal.h>
  56 #include <wl_export.h>
  57 #include "wl_ucode.h"
  58 #include "d11ucode_ext.h"
  59 #ifdef BCMSDIO
  60 #include <bcmsdh.h>
  61 #endif
  62 #include <bcmotp.h>
  63
  64 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
  65  * functions defined in the headers below. We should be eliminating those calls and
  66  * will be able to delete these include lines.
  67  */
  68 #include <wlc_antsel.h>
  69
  70 #include <pcie_core.h>
  71
  72 #include <wlc_alloc.h>
  73
  74 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  75
  76 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  77 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  78 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  79 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  80
  81 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  82
  83 #ifndef BMAC_DUP_TO_REMOVE
  84 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  85
  86 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  87
  88 #endif                          /* BMAC_DUP_TO_REMOVE */
  89
  90 #define DMAREG(wlc_hw, direction, fifonum)      (D11REV_LT(wlc_hw->corerev, 11) ? \
  91         ((direction == DMA_TX) ? \
  92                 (void *)(uintptr)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
  93                 (void *)(uintptr)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
  94         ((direction == DMA_TX) ? \
  95                 (void *)(uintptr)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
  96                 (void *)(uintptr)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
  97
  98 /*
  99  * The following table lists the buffer memory allocated to xmt fifos in HW.
 100  * the size is in units of 256bytes(one block), total size is HW dependent
 101  * ucode has default fifo partition, sw can overwrite if necessary
 102  *
 103  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 104  * the twiki is updated before making changes.
 105  */
 106
 107 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
 108
 109 static u16 xmtfifo_sz[][NFIFO] = {
 110         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 111         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 112         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 113         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 114         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 115 };
 116
 117 static void wlc_clkctl_clk(wlc_hw_info_t *wlc, uint mode);
 118 static void wlc_coreinit(wlc_info_t *wlc);
 119
 120 /* used by wlc_wakeucode_init() */
 121 static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits);
 122 static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
 123                             const uint nbytes);
 124 static void wlc_ucode_download(wlc_hw_info_t *wlc);
 125 static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw);
 126
 127 /* used by wlc_dpc() */
 128 static bool wlc_bmac_dotxstatus(wlc_hw_info_t *wlc, tx_status_t *txs,
 129                                 u32 s2);
 130 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc);
 131 static bool wlc_bmac_txstatus(wlc_hw_info_t *wlc, bool bound, bool *fatal);
 132 static bool wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound);
 133
 134 /* used by wlc_down() */
 135 static void wlc_flushqueues(wlc_info_t *wlc);
 136
 137 static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs);
 138 static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw);
 139 static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw);
 140
 141 /* Low Level Prototypes */
 142 static u16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset,
 143                                    u32 sel);
 144 static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v,
 145                                   u32 sel);
 146 static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme);
 147 static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw);
 148 static void wlc_ucode_bsinit(wlc_hw_info_t *wlc_hw);
 149 static bool wlc_validboardtype(wlc_hw_info_t *wlc);
 150 static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw);
 151 static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw);
 152 static void wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init);
 153 static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw);
 154 static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw);
 155 static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw);
 156 static u32 wlc_wlintrsoff(wlc_info_t *wlc);
 157 static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask);
 158 static void wlc_gpio_init(wlc_info_t *wlc);
 159 static void wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn,
 160                                       int len);
 161 static void wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn,
 162                                       int len);
 163 static void wlc_bmac_bsinit(wlc_info_t *wlc, chanspec_t chanspec);
 164 static u32 wlc_setband_inact(wlc_info_t *wlc, uint bandunit);
 165 static void wlc_bmac_setband(wlc_hw_info_t *wlc_hw, uint bandunit,
 166                              chanspec_t chanspec);
 167 static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot);
 168 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw);
 169 static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw,
 170                                              u8 rate);
 171
 172 /* === Low Level functions === */
 173
 174 void wlc_bmac_set_shortslot(wlc_hw_info_t *wlc_hw, bool shortslot)
 175 {
 176         wlc_hw->shortslot = shortslot;
 177
 178         if (BAND_2G(wlc_hw->band->bandtype) && wlc_hw->up) {
 179                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 180                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 181                 wlc_enable_mac(wlc_hw->wlc);
 182         }
 183 }
 184
 185 /*
 186  * Update the slot timing for standard 11b/g (20us slots)
 187  * or shortslot 11g (9us slots)
 188  * The PSM needs to be suspended for this call.
 189  */
 190 static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot)
 191 {
 192         osl_t *osh;
 193         d11regs_t *regs;
 194
 195         osh = wlc_hw->osh;
 196         regs = wlc_hw->regs;
 197
 198         if (shortslot) {
 199                 /* 11g short slot: 11a timing */
 200                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 201                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 202         } else {
 203                 /* 11g long slot: 11b timing */
 204                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 205                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 206         }
 207 }
 208
 209 static void WLBANDINITFN(wlc_ucode_bsinit) (wlc_hw_info_t *wlc_hw)
 210 {
 211         /* init microcode host flags */
 212         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 213
 214         /* do band-specific ucode IHR, SHM, and SCR inits */
 215         if (D11REV_IS(wlc_hw->corerev, 23)) {
 216                 if (WLCISNPHY(wlc_hw->band)) {
 217                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 218                 } else {
 219                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
 220                                   __func__, wlc_hw->unit, wlc_hw->corerev));
 221                 }
 222         } else {
 223                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 224                         if (WLCISLCNPHY(wlc_hw->band)) {
 225                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 226                         } else
 227                                 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n", __func__, wlc_hw->unit, wlc_hw->corerev));
 228                 } else {
 229                         WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
 230                                   __func__, wlc_hw->unit, wlc_hw->corerev));
 231                 }
 232         }
 233 }
 234
 235 /* switch to new band but leave it inactive */
 236 static u32 WLBANDINITFN(wlc_setband_inact) (wlc_info_t *wlc, uint bandunit)
 237 {
 238         wlc_hw_info_t *wlc_hw = wlc->hw;
 239         u32 macintmask;
 240         u32 tmp;
 241
 242         WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw->unit));
 243
 244         ASSERT(bandunit != wlc_hw->band->bandunit);
 245         ASSERT(si_iscoreup(wlc_hw->sih));
 246         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 247                0);
 248
 249         /* disable interrupts */
 250         macintmask = wl_intrsoff(wlc->wl);
 251
 252         /* radio off */
 253         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 254
 255         ASSERT(wlc_hw->clk);
 256
 257         if (D11REV_LT(wlc_hw->corerev, 17))
 258                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
 259
 260         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 261
 262         wlc_setxband(wlc_hw, bandunit);
 263
 264         return macintmask;
 265 }
 266
 267 /* Process received frames */
 268 /*
 269  * Return TRUE if more frames need to be processed. FALSE otherwise.
 270  * Param 'bound' indicates max. # frames to process before break out.
 271  */
 272 static bool BCMFASTPATH
 273 wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound)
 274 {
 275         void *p;
 276         void *head = NULL;
 277         void *tail = NULL;
 278         uint n = 0;
 279         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 280         u32 tsf_h, tsf_l;
 281         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 282
 283         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
 284         /* gather received frames */
 285         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 286
 287                 if (!tail)
 288                         head = tail = p;
 289                 else {
 290                         PKTSETLINK(tail, p);
 291                         tail = p;
 292                 }
 293
 294                 /* !give others some time to run! */
 295                 if (++n >= bound_limit)
 296                         break;
 297         }
 298
 299         /* get the TSF REG reading */
 300         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 301
 302         /* post more rbufs */
 303         dma_rxfill(wlc_hw->di[fifo]);
 304
 305         /* process each frame */
 306         while ((p = head) != NULL) {
 307                 head = PKTLINK(head);
 308                 PKTSETLINK(p, NULL);
 309
 310                 /* record the tsf_l in wlc_rxd11hdr */
 311                 wlc_rxhdr = (wlc_d11rxhdr_t *) PKTDATA(p);
 312                 wlc_rxhdr->tsf_l = htol32(tsf_l);
 313
 314                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 315                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 316
 317                 wlc_recv(wlc_hw->wlc, p);
 318         }
 319
 320         return n >= bound_limit;
 321 }
 322
 323 /* second-level interrupt processing
 324  *   Return TRUE if another dpc needs to be re-scheduled. FALSE otherwise.
 325  *   Param 'bounded' indicates if applicable loops should be bounded.
 326  */
 327 bool BCMFASTPATH wlc_dpc(wlc_info_t *wlc, bool bounded)
 328 {
 329         u32 macintstatus;
 330         wlc_hw_info_t *wlc_hw = wlc->hw;
 331         d11regs_t *regs = wlc_hw->regs;
 332         bool fatal = FALSE;
 333
 334         if (DEVICEREMOVED(wlc)) {
 335                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
 336                 wl_down(wlc->wl);
 337                 return FALSE;
 338         }
 339
 340         /* grab and clear the saved software intstatus bits */
 341         macintstatus = wlc->macintstatus;
 342         wlc->macintstatus = 0;
 343
 344         WL_TRACE(("wl%d: wlc_dpc: macintstatus 0x%x\n", wlc_hw->unit,
 345                   macintstatus));
 346
 347         if (macintstatus & MI_PRQ) {
 348                 /* Process probe request FIFO */
 349                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 350         }
 351
 352         /* BCN template is available */
 353         /* ZZZ: Use AP_ACTIVE ? */
 354         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 355             && (macintstatus & MI_BCNTPL)) {
 356                 wlc_update_beacon(wlc);
 357         }
 358
 359         /* PMQ entry addition */
 360         if (macintstatus & MI_PMQ) {
 361         }
 362
 363         /* tx status */
 364         if (macintstatus & MI_TFS) {
 365                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 366                         wlc->macintstatus |= MI_TFS;
 367                 if (fatal) {
 368                         WL_ERROR(("MI_TFS: fatal\n"));
 369                         goto fatal;
 370                 }
 371         }
 372
 373         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 374                 wlc_tbtt(wlc, regs);
 375
 376         /* ATIM window end */
 377         if (macintstatus & MI_ATIMWINEND) {
 378                 WL_TRACE(("wlc_isr: end of ATIM window\n"));
 379
 380                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 381                 wlc->qvalid = 0;
 382         }
 383
 384         /* phy tx error */
 385         if (macintstatus & MI_PHYTXERR) {
 386                 WLCNTINCR(wlc->pub->_cnt->txphyerr);
 387         }
 388
 389         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 390         if (macintstatus & MI_DMAINT) {
 391                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 392                         wlc->macintstatus |= MI_DMAINT;
 393                 }
 394         }
 395
 396         /* TX FIFO suspend/flush completion */
 397         if (macintstatus & MI_TXSTOP) {
 398                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 399                         /*      WL_ERROR(("dpc: fifo_suspend_comlete\n")); */
 400                 }
 401         }
 402
 403         /* noise sample collected */
 404         if (macintstatus & MI_BG_NOISE) {
 405                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 406         }
 407
 408         if (macintstatus & MI_GP0) {
 409                 WL_ERROR(("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now));
 410
 411                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 412                             __func__, CHIPID(wlc_hw->sih->chip),
 413                             CHIPREV(wlc_hw->sih->chiprev));
 414
 415                 WLCNTINCR(wlc->pub->_cnt->psmwds);
 416
 417                 /* big hammer */
 418                 wl_init(wlc->wl);
 419         }
 420
 421         /* gptimer timeout */
 422         if (macintstatus & MI_TO) {
 423                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 424         }
 425
 426         if (macintstatus & MI_RFDISABLE) {
 427 #if defined(BCMDBG)
 428                 u32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD;
 429 #endif
 430
 431                 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw->unit, rfd));
 432
 433                 WLCNTINCR(wlc->pub->_cnt->rfdisable);
 434         }
 435
 436         /* send any enq'd tx packets. Just makes sure to jump start tx */
 437         if (!pktq_empty(&wlc->active_queue->q))
 438                 wlc_send_q(wlc, wlc->active_queue);
 439
 440         ASSERT(wlc_ps_check(wlc));
 441
 442         /* make sure the bound indication and the implementation are in sync */
 443         ASSERT(bounded == TRUE || wlc->macintstatus == 0);
 444
 445         /* it isn't done and needs to be resched if macintstatus is non-zero */
 446         return wlc->macintstatus != 0;
 447
 448  fatal:
 449         wl_init(wlc->wl);
 450         return wlc->macintstatus != 0;
 451 }
 452
 453 /* common low-level watchdog code */
 454 void wlc_bmac_watchdog(void *arg)
 455 {
 456         wlc_info_t *wlc = (wlc_info_t *) arg;
 457         wlc_hw_info_t *wlc_hw = wlc->hw;
 458
 459         WL_TRACE(("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit));
 460
 461         if (!wlc_hw->up)
 462                 return;
 463
 464         /* increment second count */
 465         wlc_hw->now++;
 466
 467         /* Check for FIFO error interrupts */
 468         wlc_bmac_fifoerrors(wlc_hw);
 469
 470         /* make sure RX dma has buffers */
 471         dma_rxfill(wlc->hw->di[RX_FIFO]);
 472         if (D11REV_IS(wlc_hw->corerev, 4)) {
 473                 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
 474         }
 475
 476         wlc_phy_watchdog(wlc_hw->band->pi);
 477 }
 478
 479 void
 480 wlc_bmac_set_chanspec(wlc_hw_info_t *wlc_hw, chanspec_t chanspec, bool mute,
 481                       struct txpwr_limits *txpwr)
 482 {
 483         uint bandunit;
 484
 485         WL_TRACE(("wl%d: wlc_bmac_set_chanspec 0x%x\n", wlc_hw->unit,
 486                   chanspec));
 487
 488         wlc_hw->chanspec = chanspec;
 489
 490         /* Switch bands if necessary */
 491         if (NBANDS_HW(wlc_hw) > 1) {
 492                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 493                 if (wlc_hw->band->bandunit != bandunit) {
 494                         /* wlc_bmac_setband disables other bandunit,
 495                          *  use light band switch if not up yet
 496                          */
 497                         if (wlc_hw->up) {
 498                                 wlc_phy_chanspec_radio_set(wlc_hw->
 499                                                            bandstate[bandunit]->
 500                                                            pi, chanspec);
 501                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 502                         } else {
 503                                 wlc_setxband(wlc_hw, bandunit);
 504                         }
 505                 }
 506         }
 507
 508         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 509
 510         if (!wlc_hw->up) {
 511                 if (wlc_hw->clk)
 512                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 513                                                   chanspec);
 514                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 515         } else {
 516                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 517                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 518
 519                 /* Update muting of the channel */
 520                 wlc_bmac_mute(wlc_hw, mute, 0);
 521         }
 522 }
 523
 524 int wlc_bmac_revinfo_get(wlc_hw_info_t *wlc_hw, wlc_bmac_revinfo_t *revinfo)
 525 {
 526         si_t *sih = wlc_hw->sih;
 527         uint idx;
 528
 529         revinfo->vendorid = wlc_hw->vendorid;
 530         revinfo->deviceid = wlc_hw->deviceid;
 531
 532         revinfo->boardrev = wlc_hw->boardrev;
 533         revinfo->corerev = wlc_hw->corerev;
 534         revinfo->sromrev = wlc_hw->sromrev;
 535         revinfo->chiprev = sih->chiprev;
 536         revinfo->chip = sih->chip;
 537         revinfo->chippkg = sih->chippkg;
 538         revinfo->boardtype = sih->boardtype;
 539         revinfo->boardvendor = sih->boardvendor;
 540         revinfo->bustype = sih->bustype;
 541         revinfo->buscoretype = sih->buscoretype;
 542         revinfo->buscorerev = sih->buscorerev;
 543         revinfo->issim = sih->issim;
 544
 545         revinfo->nbands = NBANDS_HW(wlc_hw);
 546
 547         for (idx = 0; idx < NBANDS_HW(wlc_hw); idx++) {
 548                 wlc_hwband_t *band = wlc_hw->bandstate[idx];
 549                 revinfo->band[idx].bandunit = band->bandunit;
 550                 revinfo->band[idx].bandtype = band->bandtype;
 551                 revinfo->band[idx].phytype = band->phytype;
 552                 revinfo->band[idx].phyrev = band->phyrev;
 553                 revinfo->band[idx].radioid = band->radioid;
 554                 revinfo->band[idx].radiorev = band->radiorev;
 555                 revinfo->band[idx].abgphy_encore = band->abgphy_encore;
 556                 revinfo->band[idx].anarev = 0;
 557
 558         }
 559         return 0;
 560 }
 561
 562 int wlc_bmac_state_get(wlc_hw_info_t *wlc_hw, wlc_bmac_state_t *state)
 563 {
 564         state->machwcap = wlc_hw->machwcap;
 565
 566         return 0;
 567 }
 568
 569 static bool
 570 BCMATTACHFN(wlc_bmac_attach_dmapio) (wlc_info_t *wlc, uint j, bool wme)
 571 {
 572         uint i;
 573         char name[8];
 574         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 575         u16 pio_mhf2 = 0;
 576         wlc_hw_info_t *wlc_hw = wlc->hw;
 577         uint unit = wlc_hw->unit;
 578         wlc_tunables_t *tune = wlc->pub->tunables;
 579
 580         /* name and offsets for dma_attach */
 581         snprintf(name, sizeof(name), "wl%d", unit);
 582
 583         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 584                 uint addrwidth;
 585                 int dma_attach_err = 0;
 586                 osl_t *osh = wlc_hw->osh;
 587
 588                 /* Find out the DMA addressing capability and let OS know
 589                  * All the channels within one DMA core have 'common-minimum' same
 590                  * capability
 591                  */
 592                 addrwidth =
 593                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 594                 OSL_DMADDRWIDTH(osh, addrwidth);
 595
 596                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 597                         WL_ERROR(("wl%d: wlc_attach: alloc_dma_resources failed\n", unit));
 598                         return FALSE;
 599                 }
 600
 601                 /*
 602                  * FIFO 0
 603                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 604                  * RX: RX_FIFO (RX data packets)
 605                  */
 606                 ASSERT(TX_AC_BK_FIFO == 0);
 607                 ASSERT(RX_FIFO == 0);
 608                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 609                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 610                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 611                                            (wme ? tune->ntxd : 0), tune->nrxd,
 612                                            tune->rxbufsz, -1, tune->nrxbufpost,
 613                                            WL_HWRXOFF, &wl_msg_level);
 614                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 615
 616                 /*
 617                  * FIFO 1
 618                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 619                  *   (legacy) TX_DATA_FIFO (TX data packets)
 620                  * RX: UNUSED
 621                  */
 622                 ASSERT(TX_AC_BE_FIFO == 1);
 623                 ASSERT(TX_DATA_FIFO == 1);
 624                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 625                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 626                                            tune->ntxd, 0, 0, -1, 0, 0,
 627                                            &wl_msg_level);
 628                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 629
 630                 /*
 631                  * FIFO 2
 632                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 633                  * RX: UNUSED
 634                  */
 635                 ASSERT(TX_AC_VI_FIFO == 2);
 636                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 637                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 638                                            tune->ntxd, 0, 0, -1, 0, 0,
 639                                            &wl_msg_level);
 640                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 641                 /*
 642                  * FIFO 3
 643                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 644                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 645                  * RX: RX_TXSTATUS_FIFO (transmit-status packets)
 646                  *      for corerev < 5 only
 647                  */
 648                 ASSERT(TX_AC_VO_FIFO == 3);
 649                 ASSERT(TX_CTL_FIFO == 3);
 650                 if (D11REV_IS(wlc_hw->corerev, 4)) {
 651                         ASSERT(RX_TXSTATUS_FIFO == 3);
 652                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 653                                                    DMAREG(wlc_hw, DMA_TX, 3),
 654                                                    DMAREG(wlc_hw, DMA_RX, 3),
 655                                                    tune->ntxd, tune->nrxd,
 656                                                    sizeof(tx_status_t), -1,
 657                                                    tune->nrxbufpost, 0,
 658                                                    &wl_msg_level);
 659                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 660                 } else {
 661                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 662                                                    DMAREG(wlc_hw, DMA_TX, 3),
 663                                                    NULL, tune->ntxd, 0, 0, -1,
 664                                                    0, 0, &wl_msg_level);
 665                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 666                 }
 667 /* Cleaner to leave this as if with AP defined */
 668
 669                 if (dma_attach_err) {
 670                         WL_ERROR(("wl%d: wlc_attach: dma_attach failed\n",
 671                                   unit));
 672                         return FALSE;
 673                 }
 674
 675                 /* get pointer to dma engine tx flow control variable */
 676                 for (i = 0; i < NFIFO; i++)
 677                         if (wlc_hw->di[i])
 678                                 wlc_hw->txavail[i] =
 679                                     (uint *) dma_getvar(wlc_hw->di[i],
 680                                                         "&txavail");
 681         }
 682
 683         /* initial ucode host flags */
 684         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 685
 686         return TRUE;
 687 }
 688
 689 static void BCMATTACHFN(wlc_bmac_detach_dmapio) (wlc_hw_info_t *wlc_hw)
 690 {
 691         uint j;
 692
 693         for (j = 0; j < NFIFO; j++) {
 694                 if (wlc_hw->di[j]) {
 695                         dma_detach(wlc_hw->di[j]);
 696                         wlc_hw->di[j] = NULL;
 697                 }
 698         }
 699 }
 700
 701 /* low level attach
 702  *    run backplane attach, init nvram
 703  *    run phy attach
 704  *    initialize software state for each core and band
 705  *    put the whole chip in reset(driver down state), no clock
 706  */
 707
 708 int
 709 BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, u16 vendor, u16 device,
 710                               uint unit, bool piomode, osl_t *osh,
 711                               void *regsva, uint bustype, void *btparam) {
 712         wlc_hw_info_t *wlc_hw;
 713         d11regs_t *regs;
 714         char *macaddr = NULL;
 715         char *vars;
 716         uint err = 0;
 717         uint j;
 718         bool wme = FALSE;
 719         shared_phy_params_t sha_params;
 720
 721         WL_TRACE(("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n", unit,
 722                   vendor, device));
 723
 724         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 725
 726         wme = TRUE;
 727
 728         wlc_hw = wlc->hw;
 729         wlc_hw->wlc = wlc;
 730         wlc_hw->unit = unit;
 731         wlc_hw->osh = osh;
 732         wlc_hw->band = wlc_hw->bandstate[0];
 733         wlc_hw->_piomode = piomode;
 734
 735         /* populate wlc_hw_info_t with default values  */
 736         wlc_bmac_info_init(wlc_hw);
 737
 738         /*
 739          * Do the hardware portion of the attach.
 740          * Also initialize software state that depends on the particular hardware
 741          * we are running.
 742          */
 743         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 744                                 &wlc_hw->vars, &wlc_hw->vars_size);
 745         if (wlc_hw->sih == NULL) {
 746                 WL_ERROR(("wl%d: wlc_bmac_attach: si_attach failed\n", unit));
 747                 err = 11;
 748                 goto fail;
 749         }
 750         vars = wlc_hw->vars;
 751
 752         /*
 753          * Get vendid/devid nvram overwrites, which could be different
 754          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 755          * SDIO_BUS, and SROMless devices on PCI_BUS.
 756          */
 757 #ifdef BCMBUSTYPE
 758         bustype = BCMBUSTYPE;
 759 #endif
 760         if (bustype != SI_BUS) {
 761                 char *var;
 762
 763                 var = getvar(vars, "vendid");
 764                 if (var) {
 765                         vendor = (u16) simple_strtoul(var, NULL, 0);
 766                         WL_ERROR(("Overriding vendor id = 0x%x\n", vendor));
 767                 }
 768                 var = getvar(vars, "devid");
 769                 if (var) {
 770                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 771                         if (devid != 0xffff) {
 772                                 device = devid;
 773                                 WL_ERROR(("Overriding device id = 0x%x\n",
 774                                           device));
 775                         }
 776                 }
 777
 778                 /* verify again the device is supported */
 779                 if (!wlc_chipmatch(vendor, device)) {
 780                         WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n", unit, vendor, device));
 781                         err = 12;
 782                         goto fail;
 783                 }
 784         }
 785
 786         wlc_hw->vendorid = vendor;
 787         wlc_hw->deviceid = device;
 788
 789         /* set bar0 window to point at D11 core */
 790         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 791         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 792
 793         regs = wlc_hw->regs;
 794
 795         wlc->regs = wlc_hw->regs;
 796
 797         /* validate chip, chiprev and corerev */
 798         if (!wlc_isgoodchip(wlc_hw)) {
 799                 err = 13;
 800                 goto fail;
 801         }
 802
 803         /* initialize power control registers */
 804         si_clkctl_init(wlc_hw->sih);
 805
 806         /* request fastclock and force fastclock for the rest of attach
 807          * bring the d11 core out of reset.
 808          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still FALSE;
 809          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 810          */
 811         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 812         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 813
 814         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 815                 WL_ERROR(("wl%d: wlc_bmac_attach: validate_chip_access failed\n", unit));
 816                 err = 14;
 817                 goto fail;
 818         }
 819
 820         /* get the board rev, used just below */
 821         j = getintvar(vars, "boardrev");
 822         /* promote srom boardrev of 0xFF to 1 */
 823         if (j == BOARDREV_PROMOTABLE)
 824                 j = BOARDREV_PROMOTED;
 825         wlc_hw->boardrev = (u16) j;
 826         if (!wlc_validboardtype(wlc_hw)) {
 827                 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit, wlc_hw->sih->boardtype, wlc_hw->boardrev));
 828                 err = 15;
 829                 goto fail;
 830         }
 831         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 832         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 833         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 834
 835         if (D11REV_LE(wlc_hw->corerev, 4)
 836             || (wlc_hw->boardflags & BFL_NOPLLDOWN))
 837                 wlc_bmac_pllreq(wlc_hw, TRUE, WLC_PLLREQ_SHARED);
 838
 839         if ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
 840             && (si_pci_war16165(wlc_hw->sih)))
 841                 wlc->war16165 = TRUE;
 842
 843         /* check device id(srom, nvram etc.) to set bands */
 844         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 845                 /* Dualband boards */
 846                 wlc_hw->_nbands = 2;
 847         } else
 848                 wlc_hw->_nbands = 1;
 849
 850         if ((CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID))
 851                 wlc_hw->_nbands = 1;
 852
 853         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 854          * init of these values
 855          */
 856         wlc->vendorid = wlc_hw->vendorid;
 857         wlc->deviceid = wlc_hw->deviceid;
 858         wlc->pub->sih = wlc_hw->sih;
 859         wlc->pub->corerev = wlc_hw->corerev;
 860         wlc->pub->sromrev = wlc_hw->sromrev;
 861         wlc->pub->boardrev = wlc_hw->boardrev;
 862         wlc->pub->boardflags = wlc_hw->boardflags;
 863         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 864         wlc->pub->_nbands = wlc_hw->_nbands;
 865
 866         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 867
 868         if (wlc_hw->physhim == NULL) {
 869                 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 870                           unit));
 871                 err = 25;
 872                 goto fail;
 873         }
 874
 875         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 876         sha_params.osh = osh;
 877         sha_params.sih = wlc_hw->sih;
 878         sha_params.physhim = wlc_hw->physhim;
 879         sha_params.unit = unit;
 880         sha_params.corerev = wlc_hw->corerev;
 881         sha_params.vars = vars;
 882         sha_params.vid = wlc_hw->vendorid;
 883         sha_params.did = wlc_hw->deviceid;
 884         sha_params.chip = wlc_hw->sih->chip;
 885         sha_params.chiprev = wlc_hw->sih->chiprev;
 886         sha_params.chippkg = wlc_hw->sih->chippkg;
 887         sha_params.sromrev = wlc_hw->sromrev;
 888         sha_params.boardtype = wlc_hw->sih->boardtype;
 889         sha_params.boardrev = wlc_hw->boardrev;
 890         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 891         sha_params.boardflags = wlc_hw->boardflags;
 892         sha_params.boardflags2 = wlc_hw->boardflags2;
 893         sha_params.bustype = wlc_hw->sih->bustype;
 894         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 895
 896         /* alloc and save pointer to shared phy state area */
 897         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 898         if (!wlc_hw->phy_sh) {
 899                 err = 16;
 900                 goto fail;
 901         }
 902
 903         /* initialize software state for each core and band */
 904         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 905                 /*
 906                  * band0 is always 2.4Ghz
 907                  * band1, if present, is 5Ghz
 908                  */
 909
 910                 /* So if this is a single band 11a card, use band 1 */
 911                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 912                         j = BAND_5G_INDEX;
 913
 914                 wlc_setxband(wlc_hw, j);
 915
 916                 wlc_hw->band->bandunit = j;
 917                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 918                 wlc->band->bandunit = j;
 919                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 920                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 921
 922                 if (D11REV_GE(wlc_hw->corerev, 13)) {
 923                         wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 924                         wlc_hw->machwcap_backup = wlc_hw->machwcap;
 925                 }
 926
 927                 /* init tx fifo size */
 928                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 929                        ARRAY_SIZE(xmtfifo_sz));
 930                 wlc_hw->xmtfifo_sz =
 931                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 932
 933                 /* Get a phy for this band */
 934                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 935                         (void *)(uintptr) regs, wlc_hw->band->bandtype, vars);
 936                 if (wlc_hw->band->pi == NULL) {
 937                         WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n", unit));
 938                         err = 17;
 939                         goto fail;
 940                 }
 941
 942                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 943
 944                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 945                                        &wlc_hw->band->phyrev,
 946                                        &wlc_hw->band->radioid,
 947                                        &wlc_hw->band->radiorev);
 948                 wlc_hw->band->abgphy_encore =
 949                     wlc_phy_get_encore(wlc_hw->band->pi);
 950                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 951                 wlc_hw->band->core_flags =
 952                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 953
 954                 /* verify good phy_type & supported phy revision */
 955                 if (WLCISNPHY(wlc_hw->band)) {
 956                         if (NCONF_HAS(wlc_hw->band->phyrev))
 957                                 goto good_phy;
 958                         else
 959                                 goto bad_phy;
 960                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 961                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 962                                 goto good_phy;
 963                         else
 964                                 goto bad_phy;
 965                 } else {
 966  bad_phy:
 967                         WL_ERROR(("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n", unit, wlc_hw->band->phytype, wlc_hw->band->phyrev));
 968                         err = 18;
 969                         goto fail;
 970                 }
 971
 972  good_phy:
 973                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 974                  * high level attach. However we can not make that change until all low level access
 975                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 976                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 977                  * low only init when all fns updated.
 978                  */
 979                 wlc->band->pi = wlc_hw->band->pi;
 980                 wlc->band->phytype = wlc_hw->band->phytype;
 981                 wlc->band->phyrev = wlc_hw->band->phyrev;
 982                 wlc->band->radioid = wlc_hw->band->radioid;
 983                 wlc->band->radiorev = wlc_hw->band->radiorev;
 984
 985                 /* default contention windows size limits */
 986                 wlc_hw->band->CWmin = APHY_CWMIN;
 987                 wlc_hw->band->CWmax = PHY_CWMAX;
 988
 989                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 990                         err = 19;
 991                         goto fail;
 992                 }
 993         }
 994
 995         /* disable core to match driver "down" state */
 996         wlc_coredisable(wlc_hw);
 997
 998         /* Match driver "down" state */
 999         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1000                 si_pci_down(wlc_hw->sih);
1001
1002         /* register sb interrupt callback functions */
1003         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
1004                                   (void *)wlc_wlintrsrestore, NULL, wlc);
1005
1006         /* turn off pll and xtal to match driver "down" state */
1007         wlc_bmac_xtal(wlc_hw, OFF);
1008
1009         /* *********************************************************************
1010          * The hardware is in the DOWN state at this point. D11 core
1011          * or cores are in reset with clocks off, and the board PLLs
1012          * are off if possible.
1013          *
1014          * Beyond this point, wlc->sbclk == FALSE and chip registers
1015          * should not be touched.
1016          *********************************************************************
1017          */
1018
1019         /* init etheraddr state variables */
1020         macaddr = wlc_get_macaddr(wlc_hw);
1021         if (macaddr == NULL) {
1022                 WL_ERROR(("wl%d: wlc_bmac_attach: macaddr not found\n", unit));
1023                 err = 21;
1024                 goto fail;
1025         }
1026         bcm_ether_atoe(macaddr, &wlc_hw->etheraddr);
1027         if (ETHER_ISBCAST((char *)&wlc_hw->etheraddr) ||
1028             ETHER_ISNULLADDR((char *)&wlc_hw->etheraddr)) {
1029                 WL_ERROR(("wl%d: wlc_bmac_attach: bad macaddr %s\n", unit,
1030                           macaddr));
1031                 err = 22;
1032                 goto fail;
1033         }
1034
1035         WL_ERROR(("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1036                   __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1037                   wlc_hw->sih->boardtype, macaddr));
1038
1039         return err;
1040
1041  fail:
1042         WL_ERROR(("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err));
1043         return err;
1044 }
1045
1046 /*
1047  * Initialize wlc_info default values ...
1048  * may get overrides later in this function
1049  *  BMAC_NOTES, move low out and resolve the dangling ones
1050  */
1051 void BCMATTACHFN(wlc_bmac_info_init) (wlc_hw_info_t *wlc_hw)
1052 {
1053         wlc_info_t *wlc = wlc_hw->wlc;
1054
1055         /* set default sw macintmask value */
1056         wlc->defmacintmask = DEF_MACINTMASK;
1057
1058         /* various 802.11g modes */
1059         wlc_hw->shortslot = FALSE;
1060
1061         wlc_hw->SFBL = RETRY_SHORT_FB;
1062         wlc_hw->LFBL = RETRY_LONG_FB;
1063
1064         /* default mac retry limits */
1065         wlc_hw->SRL = RETRY_SHORT_DEF;
1066         wlc_hw->LRL = RETRY_LONG_DEF;
1067         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1068 }
1069
1070 /*
1071  * low level detach
1072  */
1073 int BCMATTACHFN(wlc_bmac_detach) (wlc_info_t *wlc)
1074 {
1075         uint i;
1076         wlc_hwband_t *band;
1077         wlc_hw_info_t *wlc_hw = wlc->hw;
1078         int callbacks;
1079
1080         callbacks = 0;
1081
1082         if (wlc_hw->sih) {
1083                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1084                  * interrupt object may has been freed. this must be done before sb core switch
1085                  */
1086                 si_deregister_intr_callback(wlc_hw->sih);
1087
1088                 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1089                         si_pci_sleep(wlc_hw->sih);
1090         }
1091
1092         wlc_bmac_detach_dmapio(wlc_hw);
1093
1094         band = wlc_hw->band;
1095         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1096                 if (band->pi) {
1097                         /* Detach this band's phy */
1098                         wlc_phy_detach(band->pi);
1099                         band->pi = NULL;
1100                 }
1101                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1102         }
1103
1104         /* Free shared phy state */
1105         wlc_phy_shared_detach(wlc_hw->phy_sh);
1106
1107         wlc_phy_shim_detach(wlc_hw->physhim);
1108
1109         /* free vars */
1110         if (wlc_hw->vars) {
1111                 MFREE(wlc_hw->osh, wlc_hw->vars, wlc_hw->vars_size);
1112                 wlc_hw->vars = NULL;
1113         }
1114
1115         if (wlc_hw->sih) {
1116                 si_detach(wlc_hw->sih);
1117                 wlc_hw->sih = NULL;
1118         }
1119
1120         return callbacks;
1121
1122 }
1123
1124 void BCMINITFN(wlc_bmac_reset) (wlc_hw_info_t *wlc_hw)
1125 {
1126         WL_TRACE(("wl%d: wlc_bmac_reset\n", wlc_hw->unit));
1127
1128         WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1129
1130         /* reset the core */
1131         if (!DEVICEREMOVED(wlc_hw->wlc))
1132                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1133
1134         /* purge the dma rings */
1135         wlc_flushqueues(wlc_hw->wlc);
1136
1137         wlc_reset_bmac_done(wlc_hw->wlc);
1138 }
1139
1140 void
1141 BCMINITFN(wlc_bmac_init) (wlc_hw_info_t *wlc_hw, chanspec_t chanspec,
1142                           bool mute) {
1143         u32 macintmask;
1144         bool fastclk;
1145         wlc_info_t *wlc = wlc_hw->wlc;
1146
1147         WL_TRACE(("wl%d: wlc_bmac_init\n", wlc_hw->unit));
1148
1149         /* request FAST clock if not on */
1150         fastclk = wlc_hw->forcefastclk;
1151         if (!fastclk)
1152                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1153
1154         /* disable interrupts */
1155         macintmask = wl_intrsoff(wlc->wl);
1156
1157         /* set up the specified band and chanspec */
1158         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1159         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1160
1161         /* do one-time phy inits and calibration */
1162         wlc_phy_cal_init(wlc_hw->band->pi);
1163
1164         /* core-specific initialization */
1165         wlc_coreinit(wlc);
1166
1167         /* suspend the tx fifos and mute the phy for preism cac time */
1168         if (mute)
1169                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1170
1171         /* band-specific inits */
1172         wlc_bmac_bsinit(wlc, chanspec);
1173
1174         /* restore macintmask */
1175         wl_intrsrestore(wlc->wl, macintmask);
1176
1177         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1178          * and wlc_enable_mac() will clear this override bit.
1179          */
1180         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1181
1182         /*
1183          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1184          */
1185         wlc_hw->mac_suspend_depth = 1;
1186
1187         /* restore the clk */
1188         if (!fastclk)
1189                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1190 }
1191
1192 int BCMINITFN(wlc_bmac_up_prep) (wlc_hw_info_t *wlc_hw)
1193 {
1194         uint coremask;
1195
1196         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1197
1198         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1199
1200         /*
1201          * Enable pll and xtal, initialize the power control registers,
1202          * and force fastclock for the remainder of wlc_up().
1203          */
1204         wlc_bmac_xtal(wlc_hw, ON);
1205         si_clkctl_init(wlc_hw->sih);
1206         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1207
1208         /*
1209          * Configure pci/pcmcia here instead of in wlc_attach()
1210          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1211          */
1212         coremask = (1 << wlc_hw->wlc->core->coreidx);
1213
1214         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1215                 si_pci_setup(wlc_hw->sih, coremask);
1216
1217         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1218
1219         /*
1220          * Need to read the hwradio status here to cover the case where the system
1221          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1222          */
1223         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1224                 /* put SB PCI in down state again */
1225                 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1226                         si_pci_down(wlc_hw->sih);
1227                 wlc_bmac_xtal(wlc_hw, OFF);
1228                 return BCME_RADIOOFF;
1229         }
1230
1231         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1232                 si_pci_up(wlc_hw->sih);
1233
1234         /* reset the d11 core */
1235         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1236
1237         return 0;
1238 }
1239
1240 int BCMINITFN(wlc_bmac_up_finish) (wlc_hw_info_t *wlc_hw)
1241 {
1242         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1243
1244         wlc_hw->up = TRUE;
1245         wlc_phy_hw_state_upd(wlc_hw->band->pi, TRUE);
1246
1247         /* FULLY enable dynamic power control and d11 core interrupt */
1248         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1249         ASSERT(wlc_hw->wlc->macintmask == 0);
1250         wl_intrson(wlc_hw->wlc->wl);
1251         return 0;
1252 }
1253
1254 int BCMUNINITFN(wlc_bmac_down_prep) (wlc_hw_info_t *wlc_hw)
1255 {
1256         bool dev_gone;
1257         uint callbacks = 0;
1258
1259         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1260
1261         if (!wlc_hw->up)
1262                 return callbacks;
1263
1264         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1265
1266         /* disable interrupts */
1267         if (dev_gone)
1268                 wlc_hw->wlc->macintmask = 0;
1269         else {
1270                 /* now disable interrupts */
1271                 wl_intrsoff(wlc_hw->wlc->wl);
1272
1273                 /* ensure we're running on the pll clock again */
1274                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1275         }
1276         /* down phy at the last of this stage */
1277         callbacks += wlc_phy_down(wlc_hw->band->pi);
1278
1279         return callbacks;
1280 }
1281
1282 int BCMUNINITFN(wlc_bmac_down_finish) (wlc_hw_info_t *wlc_hw)
1283 {
1284         uint callbacks = 0;
1285         bool dev_gone;
1286
1287         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1288
1289         if (!wlc_hw->up)
1290                 return callbacks;
1291
1292         wlc_hw->up = FALSE;
1293         wlc_phy_hw_state_upd(wlc_hw->band->pi, FALSE);
1294
1295         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1296
1297         if (dev_gone) {
1298                 wlc_hw->sbclk = FALSE;
1299                 wlc_hw->clk = FALSE;
1300                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, FALSE);
1301
1302                 /* reclaim any posted packets */
1303                 wlc_flushqueues(wlc_hw->wlc);
1304         } else {
1305
1306                 /* Reset and disable the core */
1307                 if (si_iscoreup(wlc_hw->sih)) {
1308                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1309                             MCTL_EN_MAC)
1310                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1311                         callbacks += wl_reset(wlc_hw->wlc->wl);
1312                         wlc_coredisable(wlc_hw);
1313                 }
1314
1315                 /* turn off primary xtal and pll */
1316                 if (!wlc_hw->noreset) {
1317                         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1318                                 si_pci_down(wlc_hw->sih);
1319                         wlc_bmac_xtal(wlc_hw, OFF);
1320                 }
1321         }
1322
1323         return callbacks;
1324 }
1325
1326 void wlc_bmac_wait_for_wake(wlc_hw_info_t *wlc_hw)
1327 {
1328         if (D11REV_IS(wlc_hw->corerev, 4))      /* no slowclock */
1329                 OSL_DELAY(5);
1330         else {
1331                 /* delay before first read of ucode state */
1332                 OSL_DELAY(40);
1333
1334                 /* wait until ucode is no longer asleep */
1335                 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1336                           DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1337         }
1338
1339         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1340 }
1341
1342 void wlc_bmac_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
1343 {
1344         bcopy(&wlc_hw->etheraddr, ea, ETHER_ADDR_LEN);
1345 }
1346
1347 void wlc_bmac_set_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
1348 {
1349         bcopy(ea, &wlc_hw->etheraddr, ETHER_ADDR_LEN);
1350 }
1351
1352 int wlc_bmac_bandtype(wlc_hw_info_t *wlc_hw)
1353 {
1354         return wlc_hw->band->bandtype;
1355 }
1356
1357 void *wlc_cur_phy(wlc_info_t *wlc)
1358 {
1359         wlc_hw_info_t *wlc_hw = wlc->hw;
1360         return (void *)wlc_hw->band->pi;
1361 }
1362
1363 /* control chip clock to save power, enable dynamic clock or force fast clock */
1364 static void wlc_clkctl_clk(wlc_hw_info_t *wlc_hw, uint mode)
1365 {
1366         if (PMUCTL_ENAB(wlc_hw->sih)) {
1367                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1368                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1369                  *      which means the FCA bit may not be set.
1370                  *      should wakeup mac if driver wants it to run on HT.
1371                  */
1372
1373                 if (wlc_hw->clk) {
1374                         if (mode == CLK_FAST) {
1375                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1376                                        CCS_FORCEHT);
1377
1378                                 OSL_DELAY(64);
1379
1380                                 SPINWAIT(((R_REG
1381                                            (wlc_hw->osh,
1382                                             &wlc_hw->regs->
1383                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1384                                          PMU_MAX_TRANSITION_DLY);
1385                                 ASSERT(R_REG
1386                                        (wlc_hw->osh,
1387                                         &wlc_hw->regs->
1388                                         clk_ctl_st) & CCS_HTAVAIL);
1389                         } else {
1390                                 if ((wlc_hw->sih->pmurev == 0) &&
1391                                     (R_REG
1392                                      (wlc_hw->osh,
1393                                       &wlc_hw->regs->
1394                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1395                                         SPINWAIT(((R_REG
1396                                                    (wlc_hw->osh,
1397                                                     &wlc_hw->regs->
1398                                                     clk_ctl_st) & CCS_HTAVAIL)
1399                                                   == 0),
1400                                                  PMU_MAX_TRANSITION_DLY);
1401                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1402                                         ~CCS_FORCEHT);
1403                         }
1404                 }
1405                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1406         } else {
1407                 bool wakeup_ucode;
1408
1409                 /* old chips w/o PMU, force HT through cc,
1410                  * then use FCA to verify mac is running fast clock
1411                  */
1412
1413                 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1414
1415                 if (wlc_hw->up && wakeup_ucode)
1416                         wlc_ucode_wake_override_set(wlc_hw,
1417                                                     WLC_WAKE_OVERRIDE_CLKCTL);
1418
1419                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1420
1421                 if (D11REV_LT(wlc_hw->corerev, 11)) {
1422                         /* ucode WAR for old chips */
1423                         if (wlc_hw->forcefastclk)
1424                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1425                                              MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1426                         else
1427                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1428                                              WLC_BAND_ALL);
1429                 }
1430
1431                 /* check fast clock is available (if core is not in reset) */
1432                 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1433                     && wlc_hw->clk)
1434                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1435
1436                 /* keep the ucode wake bit on if forcefastclk is on
1437                  * since we do not want ucode to put us back to slow clock
1438                  * when it dozes for PM mode.
1439                  * Code below matches the wake override bit with current forcefastclk state
1440                  * Only setting bit in wake_override instead of waking ucode immediately
1441                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1442                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1443                  * (protected by an up check) was executed just below.
1444                  */
1445                 if (wlc_hw->forcefastclk)
1446                         mboolset(wlc_hw->wake_override,
1447                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1448                 else
1449                         mboolclr(wlc_hw->wake_override,
1450                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1451
1452                 /* ok to clear the wakeup now */
1453                 if (wlc_hw->up && wakeup_ucode)
1454                         wlc_ucode_wake_override_clear(wlc_hw,
1455                                                       WLC_WAKE_OVERRIDE_CLKCTL);
1456         }
1457 }
1458
1459 /* set initial host flags value */
1460 static void
1461 BCMINITFN(wlc_mhfdef) (wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init)
1462 {
1463         wlc_hw_info_t *wlc_hw = wlc->hw;
1464
1465         bzero(mhfs, sizeof(u16) * MHFMAX);
1466
1467         mhfs[MHF2] |= mhf2_init;
1468
1469         /* prohibit use of slowclock on multifunction boards */
1470         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1471                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1472
1473         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1474                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1475                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1476         }
1477 }
1478
1479 /* set or clear ucode host flag bits
1480  * it has an optimization for no-change write
1481  * it only writes through shared memory when the core has clock;
1482  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1483  *
1484  *
1485  * bands values are: WLC_BAND_AUTO <--- Current band only
1486  *                   WLC_BAND_5G   <--- 5G band only
1487  *                   WLC_BAND_2G   <--- 2G band only
1488  *                   WLC_BAND_ALL  <--- All bands
1489  */
1490 void
1491 wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask, u16 val,
1492              int bands)
1493 {
1494         u16 save;
1495         u16 addr[MHFMAX] = {
1496                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1497                 M_HOST_FLAGS5
1498         };
1499         wlc_hwband_t *band;
1500
1501         ASSERT((val & ~mask) == 0);
1502         ASSERT(idx < MHFMAX);
1503         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1504
1505         switch (bands) {
1506                 /* Current band only or all bands,
1507                  * then set the band to current band
1508                  */
1509         case WLC_BAND_AUTO:
1510         case WLC_BAND_ALL:
1511                 band = wlc_hw->band;
1512                 break;
1513         case WLC_BAND_5G:
1514                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1515                 break;
1516         case WLC_BAND_2G:
1517                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1518                 break;
1519         default:
1520                 ASSERT(0);
1521                 band = NULL;
1522         }
1523
1524         if (band) {
1525                 save = band->mhfs[idx];
1526                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1527
1528                 /* optimization: only write through if changed, and
1529                  * changed band is the current band
1530                  */
1531                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1532                     && (band == wlc_hw->band))
1533                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1534                                            (u16) band->mhfs[idx]);
1535         }
1536
1537         if (bands == WLC_BAND_ALL) {
1538                 wlc_hw->bandstate[0]->mhfs[idx] =
1539                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1540                 wlc_hw->bandstate[1]->mhfs[idx] =
1541                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1542         }
1543 }
1544
1545 u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands)
1546 {
1547         wlc_hwband_t *band;
1548         ASSERT(idx < MHFMAX);
1549
1550         switch (bands) {
1551         case WLC_BAND_AUTO:
1552                 band = wlc_hw->band;
1553                 break;
1554         case WLC_BAND_5G:
1555                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1556                 break;
1557         case WLC_BAND_2G:
1558                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1559                 break;
1560         default:
1561                 ASSERT(0);
1562                 band = NULL;
1563         }
1564
1565         if (!band)
1566                 return 0;
1567
1568         return band->mhfs[idx];
1569 }
1570
1571 static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs)
1572 {
1573         u8 idx;
1574         u16 addr[] = {
1575                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1576                 M_HOST_FLAGS5
1577         };
1578
1579         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1580
1581         for (idx = 0; idx < MHFMAX; idx++) {
1582                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1583         }
1584 }
1585
1586 /* set the maccontrol register to desired reset state and
1587  * initialize the sw cache of the register
1588  */
1589 static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw)
1590 {
1591         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1592         wlc_hw->maccontrol = 0;
1593         wlc_hw->suspended_fifos = 0;
1594         wlc_hw->wake_override = 0;
1595         wlc_hw->mute_override = 0;
1596         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1597 }
1598
1599 /* set or clear maccontrol bits */
1600 void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, u32 mask, u32 val)
1601 {
1602         u32 maccontrol;
1603         u32 new_maccontrol;
1604
1605         ASSERT((val & ~mask) == 0);
1606
1607         maccontrol = wlc_hw->maccontrol;
1608         new_maccontrol = (maccontrol & ~mask) | val;
1609
1610         /* if the new maccontrol value is the same as the old, nothing to do */
1611         if (new_maccontrol == maccontrol)
1612                 return;
1613
1614         /* something changed, cache the new value */
1615         wlc_hw->maccontrol = new_maccontrol;
1616
1617         /* write the new values with overrides applied */
1618         wlc_mctrl_write(wlc_hw);
1619 }
1620
1621 /* write the software state of maccontrol and overrides to the maccontrol register */
1622 static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw)
1623 {
1624         u32 maccontrol = wlc_hw->maccontrol;
1625
1626         /* OR in the wake bit if overridden */
1627         if (wlc_hw->wake_override)
1628                 maccontrol |= MCTL_WAKE;
1629
1630         /* set AP and INFRA bits for mute if needed */
1631         if (wlc_hw->mute_override) {
1632                 maccontrol &= ~(MCTL_AP);
1633                 maccontrol |= MCTL_INFRA;
1634         }
1635
1636         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1637 }
1638
1639 void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, u32 override_bit)
1640 {
1641         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1642
1643         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1644                 mboolset(wlc_hw->wake_override, override_bit);
1645                 return;
1646         }
1647
1648         mboolset(wlc_hw->wake_override, override_bit);
1649
1650         wlc_mctrl_write(wlc_hw);
1651         wlc_bmac_wait_for_wake(wlc_hw);
1652
1653         return;
1654 }
1655
1656 void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw, u32 override_bit)
1657 {
1658         ASSERT(wlc_hw->wake_override & override_bit);
1659
1660         mboolclr(wlc_hw->wake_override, override_bit);
1661
1662         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1663                 return;
1664
1665         wlc_mctrl_write(wlc_hw);
1666
1667         return;
1668 }
1669
1670 /* When driver needs ucode to stop beaconing, it has to make sure that
1671  * MCTL_AP is clear and MCTL_INFRA is set
1672  * Mode           MCTL_AP        MCTL_INFRA
1673  * AP                1              1
1674  * STA               0              1 <--- This will ensure no beacons
1675  * IBSS              0              0
1676  */
1677 static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw)
1678 {
1679         wlc_hw->mute_override = 1;
1680
1681         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1682          * override, then there is no change to write
1683          */
1684         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1685                 return;
1686
1687         wlc_mctrl_write(wlc_hw);
1688
1689         return;
1690 }
1691
1692 /* Clear the override on AP and INFRA bits */
1693 static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw)
1694 {
1695         if (wlc_hw->mute_override == 0)
1696                 return;
1697
1698         wlc_hw->mute_override = 0;
1699
1700         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1701          * override, then there is no change to write
1702          */
1703         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1704                 return;
1705
1706         wlc_mctrl_write(wlc_hw);
1707 }
1708
1709 /*
1710  * Write a MAC address to the rcmta structure
1711  */
1712 void
1713 wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx,
1714                    const struct ether_addr *addr)
1715 {
1716         d11regs_t *regs = wlc_hw->regs;
1717         volatile u16 *objdata16 =
1718             (volatile u16 *)(uintptr) & regs->objdata;
1719         u32 mac_hm;
1720         u16 mac_l;
1721         osl_t *osh;
1722
1723         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
1724
1725         ASSERT(wlc_hw->corerev > 4);
1726
1727         mac_hm =
1728             (addr->octet[3] << 24) | (addr->octet[2] << 16) | (addr->
1729                                                                octet[1] << 8) |
1730             addr->octet[0];
1731         mac_l = (addr->octet[5] << 8) | addr->octet[4];
1732
1733         osh = wlc_hw->osh;
1734
1735         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1736         (void)R_REG(osh, &regs->objaddr);
1737         W_REG(osh, &regs->objdata, mac_hm);
1738         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1739         (void)R_REG(osh, &regs->objaddr);
1740         W_REG(osh, objdata16, mac_l);
1741 }
1742
1743 /*
1744  * Write a MAC address to the given match reg offset in the RXE match engine.
1745  */
1746 void
1747 wlc_bmac_set_addrmatch(wlc_hw_info_t *wlc_hw, int match_reg_offset,
1748                        const struct ether_addr *addr)
1749 {
1750         d11regs_t *regs;
1751         u16 mac_l;
1752         u16 mac_m;
1753         u16 mac_h;
1754         osl_t *osh;
1755
1756         WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit));
1757
1758         ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1759
1760         regs = wlc_hw->regs;
1761         mac_l = addr->octet[0] | (addr->octet[1] << 8);
1762         mac_m = addr->octet[2] | (addr->octet[3] << 8);
1763         mac_h = addr->octet[4] | (addr->octet[5] << 8);
1764
1765         osh = wlc_hw->osh;
1766
1767         /* enter the MAC addr into the RXE match registers */
1768         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1769         W_REG(osh, &regs->rcm_mat_data, mac_l);
1770         W_REG(osh, &regs->rcm_mat_data, mac_m);
1771         W_REG(osh, &regs->rcm_mat_data, mac_h);
1772
1773 }
1774
1775 void
1776 wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
1777                             void *buf)
1778 {
1779         d11regs_t *regs;
1780         u32 word;
1781         bool be_bit;
1782 #ifdef IL_BIGENDIAN
1783         volatile u16 *dptr = NULL;
1784 #endif                          /* IL_BIGENDIAN */
1785         osl_t *osh;
1786
1787         WL_TRACE(("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit));
1788
1789         regs = wlc_hw->regs;
1790         osh = wlc_hw->osh;
1791
1792         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1793         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1794         ASSERT((offset & ~0xffff) == 0);
1795
1796         W_REG(osh, &regs->tplatewrptr, offset);
1797
1798         /* if MCTL_BIGEND bit set in mac control register,
1799          * the chip swaps data in fifo, as well as data in
1800          * template ram
1801          */
1802         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1803
1804         while (len > 0) {
1805                 bcopy((u8 *) buf, &word, sizeof(u32));
1806
1807                 if (be_bit)
1808                         word = hton32(word);
1809                 else
1810                         word = htol32(word);
1811
1812                 W_REG(osh, &regs->tplatewrdata, word);
1813
1814                 buf = (u8 *) buf + sizeof(u32);
1815                 len -= sizeof(u32);
1816         }
1817 }
1818
1819 void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin)
1820 {
1821         osl_t *osh;
1822
1823         osh = wlc_hw->osh;
1824         wlc_hw->band->CWmin = newmin;
1825
1826         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1827         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1828         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1829 }
1830
1831 void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax)
1832 {
1833         osl_t *osh;
1834
1835         osh = wlc_hw->osh;
1836         wlc_hw->band->CWmax = newmax;
1837
1838         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1839         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1840         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1841 }
1842
1843 void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw)
1844 {
1845         bool fastclk;
1846         u32 tmp;
1847
1848         /* request FAST clock if not on */
1849         fastclk = wlc_hw->forcefastclk;
1850         if (!fastclk)
1851                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1852
1853         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1854
1855         ASSERT(wlc_hw->clk);
1856         if (D11REV_LT(wlc_hw->corerev, 17))
1857                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1858
1859         wlc_bmac_phy_reset(wlc_hw);
1860         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1861
1862         /* restore the clk */
1863         if (!fastclk)
1864                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1865 }
1866
1867 static void
1868 wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn, int len)
1869 {
1870         d11regs_t *regs = wlc_hw->regs;
1871
1872         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1873                                     bcn);
1874         /* write beacon length to SCR */
1875         ASSERT(len < 65536);
1876         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1877         /* mark beacon0 valid */
1878         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1879 }
1880
1881 static void
1882 wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn, int len)
1883 {
1884         d11regs_t *regs = wlc_hw->regs;
1885
1886         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1887                                     bcn);
1888         /* write beacon length to SCR */
1889         ASSERT(len < 65536);
1890         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1891         /* mark beacon1 valid */
1892         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1893 }
1894
1895 /* mac is assumed to be suspended at this point */
1896 void
1897 wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn, int len,
1898                                bool both)
1899 {
1900         d11regs_t *regs = wlc_hw->regs;
1901
1902         if (both) {
1903                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1904                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1905         } else {
1906                 /* bcn 0 */
1907                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1908                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1909                 /* bcn 1 */
1910                 else if (!
1911                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1912                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1913                 else            /* one template should always have been available */
1914                         ASSERT(0);
1915         }
1916 }
1917
1918 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (wlc_hw_info_t *wlc_hw)
1919 {
1920         u16 v;
1921         wlc_info_t *wlc = wlc_hw->wlc;
1922         /* update SYNTHPU_DLY */
1923
1924         if (WLCISLCNPHY(wlc->band)) {
1925                 v = SYNTHPU_DLY_LPPHY_US;
1926         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1927                 v = SYNTHPU_DLY_NPHY_US;
1928         } else {
1929                 v = SYNTHPU_DLY_BPHY_US;
1930         }
1931
1932         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1933 }
1934
1935 /* band-specific init */
1936 static void
1937 WLBANDINITFN(wlc_bmac_bsinit) (wlc_info_t *wlc, chanspec_t chanspec)
1938 {
1939         wlc_hw_info_t *wlc_hw = wlc->hw;
1940
1941         WL_TRACE(("wl%d: wlc_bmac_bsinit: bandunit %d\n", wlc_hw->unit,
1942                   wlc_hw->band->bandunit));
1943
1944         /* sanity check */
1945         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1946             PHY_TYPE_LCNXN)
1947                 ASSERT((uint)
1948                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1949                        == wlc_hw->band->phytype);
1950
1951         wlc_ucode_bsinit(wlc_hw);
1952
1953         wlc_phy_init(wlc_hw->band->pi, chanspec);
1954
1955         wlc_ucode_txant_set(wlc_hw);
1956
1957         /* cwmin is band-specific, update hardware with value for current band */
1958         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1959         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1960
1961         wlc_bmac_update_slot_timing(wlc_hw,
1962                                     BAND_5G(wlc_hw->band->
1963                                             bandtype) ? TRUE : wlc_hw->
1964                                     shortslot);
1965
1966         /* write phytype and phyvers */
1967         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1968         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1969
1970         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1971         wlc_upd_ofdm_pctl1_table(wlc_hw);
1972
1973         wlc_bmac_upd_synthpu(wlc_hw);
1974 }
1975
1976 void wlc_bmac_core_phy_clk(wlc_hw_info_t *wlc_hw, bool clk)
1977 {
1978         WL_TRACE(("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk));
1979
1980         wlc_hw->phyclk = clk;
1981
1982         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1983
1984                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1985                                (SICF_PRST | SICF_FGC));
1986                 OSL_DELAY(1);
1987                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1988                 OSL_DELAY(1);
1989
1990         } else {                /* take phy out of reset */
1991
1992                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1993                 OSL_DELAY(1);
1994                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1995                 OSL_DELAY(1);
1996
1997         }
1998 }
1999
2000 /* Perform a soft reset of the PHY PLL */
2001 void wlc_bmac_core_phypll_reset(wlc_hw_info_t *wlc_hw)
2002 {
2003         WL_TRACE(("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit));
2004
2005         si_corereg(wlc_hw->sih, SI_CC_IDX,
2006                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
2007         OSL_DELAY(1);
2008         si_corereg(wlc_hw->sih, SI_CC_IDX,
2009                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
2010         OSL_DELAY(1);
2011         si_corereg(wlc_hw->sih, SI_CC_IDX,
2012                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
2013         OSL_DELAY(1);
2014         si_corereg(wlc_hw->sih, SI_CC_IDX,
2015                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
2016         OSL_DELAY(1);
2017 }
2018
2019 /* light way to turn on phy clock without reset for NPHY only
2020  *  refer to wlc_bmac_core_phy_clk for full version
2021  */
2022 void wlc_bmac_phyclk_fgc(wlc_hw_info_t *wlc_hw, bool clk)
2023 {
2024         /* support(necessary for NPHY and HYPHY) only */
2025         if (!WLCISNPHY(wlc_hw->band))
2026                 return;
2027
2028         if (ON == clk)
2029                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
2030         else
2031                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
2032
2033 }
2034
2035 void wlc_bmac_macphyclk_set(wlc_hw_info_t *wlc_hw, bool clk)
2036 {
2037         if (ON == clk)
2038                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
2039         else
2040                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
2041 }
2042
2043 void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw)
2044 {
2045         wlc_phy_t *pih = wlc_hw->band->pi;
2046         u32 phy_bw_clkbits;
2047         bool phy_in_reset = FALSE;
2048
2049         WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit));
2050
2051         if (pih == NULL)
2052                 return;
2053
2054         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2055
2056         /* Specfic reset sequence required for NPHY rev 3 and 4 */
2057         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2058             NREV_LE(wlc_hw->band->phyrev, 4)) {
2059                 /* Set the PHY bandwidth */
2060                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2061
2062                 OSL_DELAY(1);
2063
2064                 /* Perform a soft reset of the PHY PLL */
2065                 wlc_bmac_core_phypll_reset(wlc_hw);
2066
2067                 /* reset the PHY */
2068                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2069                                (SICF_PRST | SICF_PCLKE));
2070                 phy_in_reset = TRUE;
2071         } else {
2072
2073                 si_core_cflags(wlc_hw->sih,
2074                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2075                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2076         }
2077
2078         OSL_DELAY(2);
2079         wlc_bmac_core_phy_clk(wlc_hw, ON);
2080
2081         if (pih)
2082                 wlc_phy_anacore(pih, ON);
2083 }
2084
2085 /* switch to and initialize new band */
2086 static void
2087 WLBANDINITFN(wlc_bmac_setband) (wlc_hw_info_t *wlc_hw, uint bandunit,
2088                                 chanspec_t chanspec) {
2089         wlc_info_t *wlc = wlc_hw->wlc;
2090         u32 macintmask;
2091
2092         ASSERT(NBANDS_HW(wlc_hw) > 1);
2093         ASSERT(bandunit != wlc_hw->band->bandunit);
2094
2095         /* Enable the d11 core before accessing it */
2096         if (!si_iscoreup(wlc_hw->sih)) {
2097                 si_core_reset(wlc_hw->sih, 0, 0);
2098                 ASSERT(si_iscoreup(wlc_hw->sih));
2099                 wlc_mctrl_reset(wlc_hw);
2100         }
2101
2102         macintmask = wlc_setband_inact(wlc, bandunit);
2103
2104         if (!wlc_hw->up)
2105                 return;
2106
2107         wlc_bmac_core_phy_clk(wlc_hw, ON);
2108
2109         /* band-specific initializations */
2110         wlc_bmac_bsinit(wlc, chanspec);
2111
2112         /*
2113          * If there are any pending software interrupt bits,
2114          * then replace these with a harmless nonzero value
2115          * so wlc_dpc() will re-enable interrupts when done.
2116          */
2117         if (wlc->macintstatus)
2118                 wlc->macintstatus = MI_DMAINT;
2119
2120         /* restore macintmask */
2121         wl_intrsrestore(wlc->wl, macintmask);
2122
2123         /* ucode should still be suspended.. */
2124         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2125                0);
2126 }
2127
2128 /* low-level band switch utility routine */
2129 void WLBANDINITFN(wlc_setxband) (wlc_hw_info_t *wlc_hw, uint bandunit)
2130 {
2131         WL_TRACE(("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit));
2132
2133         wlc_hw->band = wlc_hw->bandstate[bandunit];
2134
2135         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2136         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2137
2138         /* set gmode core flag */
2139         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2140                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2141                                ((bandunit == 0) ? SICF_GMODE : 0));
2142         }
2143 }
2144
2145 static bool BCMATTACHFN(wlc_isgoodchip) (wlc_hw_info_t *wlc_hw)
2146 {
2147
2148         /* reject unsupported corerev */
2149         if (!VALID_COREREV(wlc_hw->corerev)) {
2150                 WL_ERROR(("unsupported core rev %d\n", wlc_hw->corerev));
2151                 return FALSE;
2152         }
2153
2154         return TRUE;
2155 }
2156
2157 static bool BCMATTACHFN(wlc_validboardtype) (wlc_hw_info_t *wlc_hw)
2158 {
2159         bool goodboard = TRUE;
2160         uint boardrev = wlc_hw->boardrev;
2161
2162         if (boardrev == 0)
2163                 goodboard = FALSE;
2164         else if (boardrev > 0xff) {
2165                 uint brt = (boardrev & 0xf000) >> 12;
2166                 uint b0 = (boardrev & 0xf00) >> 8;
2167                 uint b1 = (boardrev & 0xf0) >> 4;
2168                 uint b2 = boardrev & 0xf;
2169
2170                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2171                     || (b2 > 9))
2172                         goodboard = FALSE;
2173         }
2174
2175         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2176                 return goodboard;
2177
2178         return goodboard;
2179 }
2180
2181 static char *BCMINITFN(wlc_get_macaddr) (wlc_hw_info_t *wlc_hw)
2182 {
2183         const char *varname = "macaddr";
2184         char *macaddr;
2185
2186         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2187         macaddr = getvar(wlc_hw->vars, varname);
2188         if (macaddr != NULL)
2189                 return macaddr;
2190
2191         if (NBANDS_HW(wlc_hw) > 1)
2192                 varname = "et1macaddr";
2193         else
2194                 varname = "il0macaddr";
2195
2196         macaddr = getvar(wlc_hw->vars, varname);
2197         if (macaddr == NULL) {
2198                 WL_ERROR(("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n", wlc_hw->unit, varname));
2199         }
2200
2201         return macaddr;
2202 }
2203
2204 /*
2205  * Return TRUE if radio is disabled, otherwise FALSE.
2206  * hw radio disable signal is an external pin, users activate it asynchronously
2207  * this function could be called when driver is down and w/o clock
2208  * it operates on different registers depending on corerev and boardflag.
2209  */
2210 bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t *wlc_hw)
2211 {
2212         bool v, clk, xtal;
2213         u32 resetbits = 0, flags = 0;
2214
2215         xtal = wlc_hw->sbclk;
2216         if (!xtal)
2217                 wlc_bmac_xtal(wlc_hw, ON);
2218
2219         /* may need to take core out of reset first */
2220         clk = wlc_hw->clk;
2221         if (!clk) {
2222                 if (D11REV_LE(wlc_hw->corerev, 11))
2223                         resetbits |= SICF_PCLKE;
2224
2225                 /*
2226                  * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2227                  * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2228                  */
2229                 if (D11REV_GE(wlc_hw->corerev, 18))
2230                         flags |= SICF_PCLKE;
2231
2232                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2233                 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2234                     (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2235                     (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2236                         wlc_hw->regs =
2237                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2238                                                      0);
2239                 si_core_reset(wlc_hw->sih, flags, resetbits);
2240                 wlc_mctrl_reset(wlc_hw);
2241         }
2242
2243         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2244
2245         /* put core back into reset */
2246         if (!clk)
2247                 si_core_disable(wlc_hw->sih, 0);
2248
2249         if (!xtal)
2250                 wlc_bmac_xtal(wlc_hw, OFF);
2251
2252         return v;
2253 }
2254
2255 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2256 void BCMINITFN(wlc_bmac_hw_up) (wlc_hw_info_t *wlc_hw)
2257 {
2258         if (wlc_hw->wlc->pub->hw_up)
2259                 return;
2260
2261         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
2262
2263         /*
2264          * Enable pll and xtal, initialize the power control registers,
2265          * and force fastclock for the remainder of wlc_up().
2266          */
2267         wlc_bmac_xtal(wlc_hw, ON);
2268         si_clkctl_init(wlc_hw->sih);
2269         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2270
2271         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) {
2272                 si_pci_fixcfg(wlc_hw->sih);
2273
2274                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2275                 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2276                     (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2277                     (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2278                         wlc_hw->regs =
2279                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2280                                                      0);
2281         }
2282
2283         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2284         wlc_phy_por_inform(wlc_hw->band->pi);
2285
2286         wlc_hw->ucode_loaded = FALSE;
2287         wlc_hw->wlc->pub->hw_up = TRUE;
2288
2289         if ((wlc_hw->boardflags & BFL_FEM)
2290             && (CHIPID(wlc_hw->sih->chip) == BCM4313_CHIP_ID)) {
2291                 if (!
2292                     (wlc_hw->boardrev >= 0x1250
2293                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2294                         si_epa_4313war(wlc_hw->sih);
2295         }
2296 }
2297
2298 static bool wlc_dma_rxreset(wlc_hw_info_t *wlc_hw, uint fifo)
2299 {
2300         hnddma_t *di = wlc_hw->di[fifo];
2301         osl_t *osh;
2302
2303         if (D11REV_LT(wlc_hw->corerev, 12)) {
2304                 bool rxidle = TRUE;
2305                 u16 rcv_frm_cnt = 0;
2306
2307                 osh = wlc_hw->osh;
2308
2309                 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2310                 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2311                          ((rcv_frm_cnt =
2312                            R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2313                          50000);
2314
2315                 if (!rxidle && (rcv_frm_cnt != 0))
2316                         WL_ERROR(("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n", wlc_hw->unit, __func__, fifo, rcv_frm_cnt));
2317                 OSL_DELAY(2000);
2318         }
2319
2320         return dma_rxreset(di);
2321 }
2322
2323 /* d11 core reset
2324  *   ensure fask clock during reset
2325  *   reset dma
2326  *   reset d11(out of reset)
2327  *   reset phy(out of reset)
2328  *   clear software macintstatus for fresh new start
2329  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2330  */
2331 void BCMINITFN(wlc_bmac_corereset) (wlc_hw_info_t *wlc_hw, u32 flags)
2332 {
2333         d11regs_t *regs;
2334         uint i;
2335         bool fastclk;
2336         u32 resetbits = 0;
2337
2338         if (flags == WLC_USE_COREFLAGS)
2339                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2340
2341         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
2342
2343         regs = wlc_hw->regs;
2344
2345         /* request FAST clock if not on  */
2346         fastclk = wlc_hw->forcefastclk;
2347         if (!fastclk)
2348                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2349
2350         /* reset the dma engines except first time thru */
2351         if (si_iscoreup(wlc_hw->sih)) {
2352                 for (i = 0; i < NFIFO; i++)
2353                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2354                                 WL_ERROR(("wl%d: %s: dma_txreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, i));
2355                         }
2356
2357                 if ((wlc_hw->di[RX_FIFO])
2358                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2359                         WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_FIFO));
2360                 }
2361                 if (D11REV_IS(wlc_hw->corerev, 4)
2362                     && wlc_hw->di[RX_TXSTATUS_FIFO]
2363                     && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2364                         WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_TXSTATUS_FIFO));
2365                 }
2366         }
2367         /* if noreset, just stop the psm and return */
2368         if (wlc_hw->noreset) {
2369                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2370                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2371                 return;
2372         }
2373
2374         if (D11REV_LE(wlc_hw->corerev, 11))
2375                 resetbits |= SICF_PCLKE;
2376
2377         /*
2378          * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2379          * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2380          * need to enable PHY CLK
2381          */
2382         if (D11REV_GE(wlc_hw->corerev, 18))
2383                 flags |= SICF_PCLKE;
2384
2385         /* reset the core
2386          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2387          *  is cleared by the core_reset. have to re-request it.
2388          *  This adds some delay and we can optimize it by also requesting fastclk through
2389          *  chipcommon during this period if necessary. But that has to work coordinate
2390          *  with other driver like mips/arm since they may touch chipcommon as well.
2391          */
2392         wlc_hw->clk = FALSE;
2393         si_core_reset(wlc_hw->sih, flags, resetbits);
2394         wlc_hw->clk = TRUE;
2395         if (wlc_hw->band && wlc_hw->band->pi)
2396                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, TRUE);
2397
2398         wlc_mctrl_reset(wlc_hw);
2399
2400         if (PMUCTL_ENAB(wlc_hw->sih))
2401                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2402
2403         wlc_bmac_phy_reset(wlc_hw);
2404
2405         /* turn on PHY_PLL */
2406         wlc_bmac_core_phypll_ctl(wlc_hw, TRUE);
2407
2408         /* clear sw intstatus */
2409         wlc_hw->wlc->macintstatus = 0;
2410
2411         /* restore the clk setting */
2412         if (!fastclk)
2413                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2414 }
2415
2416 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2417  * txfifo sizes needs to be modified(increased) since the newer cores
2418  * have more memory.
2419  */
2420 static void BCMINITFN(wlc_corerev_fifofixup) (wlc_hw_info_t *wlc_hw)
2421 {
2422         d11regs_t *regs = wlc_hw->regs;
2423         u16 fifo_nu;
2424         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2425         u16 txfifo_def, txfifo_def1;
2426         u16 txfifo_cmd;
2427         osl_t *osh;
2428
2429         if (D11REV_LT(wlc_hw->corerev, 9))
2430                 goto exit;
2431
2432         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2433         txfifo_startblk = TXFIFO_START_BLK;
2434
2435         osh = wlc_hw->osh;
2436
2437         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2438         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2439
2440                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2441                 txfifo_def = (txfifo_startblk & 0xff) |
2442                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2443                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2444                     ((((txfifo_endblk -
2445                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2446                 txfifo_cmd =
2447                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2448
2449                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2450                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2451                 if (D11REV_GE(wlc_hw->corerev, 16))
2452                         W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2453
2454                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2455
2456                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2457         }
2458  exit:
2459         /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2460         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2461                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2462         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2463                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2464         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2465                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2466                             xmtfifo_sz[TX_AC_BK_FIFO]));
2467         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2468                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2469                             xmtfifo_sz[TX_BCMC_FIFO]));
2470 }
2471
2472 /* d11 core init
2473  *   reset PSM
2474  *   download ucode/PCM
2475  *   let ucode run to suspended
2476  *   download ucode inits
2477  *   config other core registers
2478  *   init dma
2479  */
2480 static void BCMINITFN(wlc_coreinit) (wlc_info_t *wlc)
2481 {
2482         wlc_hw_info_t *wlc_hw = wlc->hw;
2483         d11regs_t *regs;
2484         u32 sflags;
2485         uint bcnint_us;
2486         uint i = 0;
2487         bool fifosz_fixup = FALSE;
2488         osl_t *osh;
2489         int err = 0;
2490         u16 buf[NFIFO];
2491
2492         regs = wlc_hw->regs;
2493         osh = wlc_hw->osh;
2494
2495         WL_TRACE(("wl%d: wlc_coreinit\n", wlc_hw->unit));
2496
2497         /* reset PSM */
2498         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2499
2500         wlc_ucode_download(wlc_hw);
2501         /*
2502          * FIFOSZ fixup
2503          * 1) core5-9 use ucode 5 to save space since the PSM is the same
2504          * 2) newer chips, driver wants to controls the fifo allocation
2505          */
2506         if (D11REV_GE(wlc_hw->corerev, 4))
2507                 fifosz_fixup = TRUE;
2508
2509         /* let the PSM run to the suspended state, set mode to BSS STA */
2510         W_REG(osh, &regs->macintstatus, -1);
2511         wlc_bmac_mctrl(wlc_hw, ~0,
2512                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2513
2514         /* wait for ucode to self-suspend after auto-init */
2515         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2516                  1000 * 1000);
2517         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2518                 WL_ERROR(("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2519                           wlc_hw->unit));
2520
2521         wlc_gpio_init(wlc);
2522
2523         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2524
2525         if (D11REV_IS(wlc_hw->corerev, 23)) {
2526                 if (WLCISNPHY(wlc_hw->band))
2527                         wlc_write_inits(wlc_hw, d11n0initvals16);
2528                 else
2529                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2530                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2531         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2532                 if (WLCISLCNPHY(wlc_hw->band)) {
2533                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2534                 } else {
2535                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2536                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2537                 }
2538         } else {
2539                 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
2540                           __func__, wlc_hw->unit, wlc_hw->corerev));
2541         }
2542
2543         /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2544         if (fifosz_fixup == TRUE) {
2545                 wlc_corerev_fifofixup(wlc_hw);
2546         }
2547
2548         /* check txfifo allocations match between ucode and driver */
2549         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2550         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2551                 i = TX_AC_BE_FIFO;
2552                 err = -1;
2553         }
2554         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2555         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2556                 i = TX_AC_VI_FIFO;
2557                 err = -1;
2558         }
2559         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2560         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2561         buf[TX_AC_BK_FIFO] &= 0xff;
2562         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2563                 i = TX_AC_BK_FIFO;
2564                 err = -1;
2565         }
2566         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2567                 i = TX_AC_VO_FIFO;
2568                 err = -1;
2569         }
2570         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2571         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2572         buf[TX_BCMC_FIFO] &= 0xff;
2573         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2574                 i = TX_BCMC_FIFO;
2575                 err = -1;
2576         }
2577         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2578                 i = TX_ATIM_FIFO;
2579                 err = -1;
2580         }
2581         if (err != 0) {
2582                 WL_ERROR(("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n", buf[i], wlc_hw->xmtfifo_sz[i], i));
2583                 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2584                  * shmem, since driver don't overwrite those chip and
2585                  * ucode initialize data will be used.
2586                  */
2587                 if (D11REV_GE(wlc_hw->corerev, 4))
2588                         ASSERT(0);
2589         }
2590
2591         /* make sure we can still talk to the mac */
2592         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2593
2594         /* band-specific inits done by wlc_bsinit() */
2595
2596         /* Set up frame burst size and antenna swap threshold init values */
2597         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2598         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2599
2600         /* enable one rx interrupt per received frame */
2601         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2602         if (D11REV_IS(wlc_hw->corerev, 4))
2603                 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2604
2605         /* set the station mode (BSS STA) */
2606         wlc_bmac_mctrl(wlc_hw,
2607                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2608                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2609
2610         /* set up Beacon interval */
2611         bcnint_us = 0x8000 << 10;
2612         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2613         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2614         W_REG(osh, &regs->macintstatus, MI_GP1);
2615
2616         /* write interrupt mask */
2617         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2618         if (D11REV_IS(wlc_hw->corerev, 4))
2619                 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2620                       DEF_RXINTMASK);
2621
2622         /* allow the MAC to control the PHY clock (dynamic on/off) */
2623         wlc_bmac_macphyclk_set(wlc_hw, ON);
2624
2625         /* program dynamic clock control fast powerup delay register */
2626         if (D11REV_GT(wlc_hw->corerev, 4)) {
2627                 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2628                 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2629         }
2630
2631         /* tell the ucode the corerev */
2632         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2633
2634         /* tell the ucode MAC capabilities */
2635         if (D11REV_GE(wlc_hw->corerev, 13)) {
2636                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2637                                    (u16) (wlc_hw->machwcap & 0xffff));
2638                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2639                                    (u16) ((wlc_hw->
2640                                               machwcap >> 16) & 0xffff));
2641         }
2642
2643         /* write retry limits to SCR, this done after PSM init */
2644         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2645         (void)R_REG(osh, &regs->objaddr);
2646         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2647         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2648         (void)R_REG(osh, &regs->objaddr);
2649         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2650
2651         /* write rate fallback retry limits */
2652         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2653         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2654
2655         if (D11REV_GE(wlc_hw->corerev, 16)) {
2656                 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2657                 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2658         }
2659
2660         /* dma initializations */
2661         wlc->txpend16165war = 0;
2662
2663         /* init the tx dma engines */
2664         for (i = 0; i < NFIFO; i++) {
2665                 if (wlc_hw->di[i])
2666                         dma_txinit(wlc_hw->di[i]);
2667         }
2668
2669         /* init the rx dma engine(s) and post receive buffers */
2670         dma_rxinit(wlc_hw->di[RX_FIFO]);
2671         dma_rxfill(wlc_hw->di[RX_FIFO]);
2672         if (D11REV_IS(wlc_hw->corerev, 4)) {
2673                 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2674                 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2675         }
2676 }
2677
2678 /* This function is used for changing the tsf frac register
2679  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2680  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2681  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2682  * HTPHY Formula is 2^26/freq(MHz) e.g.
2683  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2684  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2685  * For spuron: 123MHz -> 2^26/123    = 545600.5
2686  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2687  * For spur off: 120MHz -> 2^26/120    = 559240.5
2688  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2689  */
2690
2691 void wlc_bmac_switch_macfreq(wlc_hw_info_t *wlc_hw, u8 spurmode)
2692 {
2693         d11regs_t *regs;
2694         osl_t *osh;
2695         regs = wlc_hw->regs;
2696         osh = wlc_hw->osh;
2697
2698         if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2699             (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID)) {
2700                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2701                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2702                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2703                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2704                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2705                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2706                 } else {        /* 120Mhz */
2707                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2708                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2709                 }
2710         } else if (WLCISLCNPHY(wlc_hw->band)) {
2711                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2712                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2713                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2714                 } else {        /* 80Mhz */
2715                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2716                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2717                 }
2718         }
2719 }
2720
2721 /* Initialize GPIOs that are controlled by D11 core */
2722 static void BCMINITFN(wlc_gpio_init) (wlc_info_t *wlc)
2723 {
2724         wlc_hw_info_t *wlc_hw = wlc->hw;
2725         d11regs_t *regs;
2726         u32 gc, gm;
2727         osl_t *osh;
2728
2729         regs = wlc_hw->regs;
2730         osh = wlc_hw->osh;
2731
2732         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2733         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2734
2735         /*
2736          * Common GPIO setup:
2737          *      G0 = LED 0 = WLAN Activity
2738          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2739          *      G2 = LED 2 = WLAN 5 GHz Radio State
2740          *      G4 = radio disable input (HI enabled, LO disabled)
2741          */
2742
2743         gc = gm = 0;
2744
2745         /* Allocate GPIOs for mimo antenna diversity feature */
2746         if (WLANTSEL_ENAB(wlc)) {
2747                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2748                         /* Enable antenna diversity, use 2x3 mode */
2749                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2750                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2751                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2752                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2753
2754                         /* init superswitch control */
2755                         wlc_phy_antsel_init(wlc_hw->band->pi, FALSE);
2756
2757                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2758                         ASSERT((gm & BOARD_GPIO_12) == 0);
2759                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2760                         /* The board itself is powered by these GPIOs (when not sending pattern)
2761                          * So set them high
2762                          */
2763                         OR_REG(osh, &regs->psm_gpio_oe,
2764                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2765                         OR_REG(osh, &regs->psm_gpio_out,
2766                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2767
2768                         /* Enable antenna diversity, use 2x4 mode */
2769                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2770                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2771                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2772                                      WLC_BAND_ALL);
2773
2774                         /* Configure the desired clock to be 4Mhz */
2775                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2776                                            ANTSEL_CLKDIV_4MHZ);
2777                 }
2778         }
2779         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2780         if (wlc_hw->boardflags & BFL_PACTRL)
2781                 gm |= gc |= BOARD_GPIO_PACTRL;
2782
2783         /* apply to gpiocontrol register */
2784         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2785 }
2786
2787 static void BCMATTACHFN(wlc_ucode_download) (wlc_hw_info_t *wlc_hw)
2788 {
2789         wlc_info_t *wlc;
2790         wlc = wlc_hw->wlc;
2791
2792         if (wlc_hw->ucode_loaded)
2793                 return;
2794
2795         if (D11REV_IS(wlc_hw->corerev, 23)) {
2796                 if (WLCISNPHY(wlc_hw->band)) {
2797                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2798                                         bcm43xx_16_mimosz);
2799                         wlc_hw->ucode_loaded = TRUE;
2800                 } else
2801                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2802                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2803         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2804                 if (WLCISLCNPHY(wlc_hw->band)) {
2805                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2806                                         bcm43xx_24_lcnsz);
2807                         wlc_hw->ucode_loaded = TRUE;
2808                 } else {
2809                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2810                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2811                 }
2812         }
2813 }
2814
2815 static void
2816 BCMATTACHFN(wlc_ucode_write) (wlc_hw_info_t *wlc_hw, const u32 ucode[],
2817                               const uint nbytes) {
2818         osl_t *osh;
2819         d11regs_t *regs = wlc_hw->regs;
2820         uint i;
2821         uint count;
2822
2823         osh = wlc_hw->osh;
2824
2825         WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw->unit));
2826
2827         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2828
2829         count = (nbytes / sizeof(u32));
2830
2831         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2832         (void)R_REG(osh, &regs->objaddr);
2833         for (i = 0; i < count; i++)
2834                 W_REG(osh, &regs->objdata, ucode[i]);
2835 }
2836
2837 static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits)
2838 {
2839         int i;
2840         osl_t *osh;
2841         volatile u8 *base;
2842
2843         WL_TRACE(("wl%d: wlc_write_inits\n", wlc_hw->unit));
2844
2845         osh = wlc_hw->osh;
2846         base = (volatile u8 *)wlc_hw->regs;
2847
2848         for (i = 0; inits[i].addr != 0xffff; i++) {
2849                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2850
2851                 if (inits[i].size == 2)
2852                         W_REG(osh, (u16 *) (uintptr) (base + inits[i].addr),
2853                               inits[i].value);
2854                 else if (inits[i].size == 4)
2855                         W_REG(osh, (u32 *) (uintptr) (base + inits[i].addr),
2856                               inits[i].value);
2857         }
2858 }
2859
2860 static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw)
2861 {
2862         u16 phyctl;
2863         u16 phytxant = wlc_hw->bmac_phytxant;
2864         u16 mask = PHY_TXC_ANT_MASK;
2865
2866         /* set the Probe Response frame phy control word */
2867         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2868         phyctl = (phyctl & ~mask) | phytxant;
2869         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2870
2871         /* set the Response (ACK/CTS) frame phy control word */
2872         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2873         phyctl = (phyctl & ~mask) | phytxant;
2874         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2875 }
2876
2877 void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, u16 phytxant)
2878 {
2879         /* update sw state */
2880         wlc_hw->bmac_phytxant = phytxant;
2881
2882         /* push to ucode if up */
2883         if (!wlc_hw->up)
2884                 return;
2885         wlc_ucode_txant_set(wlc_hw);
2886
2887 }
2888
2889 u16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw)
2890 {
2891         return (u16) wlc_hw->wlc->stf->txant;
2892 }
2893
2894 void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type)
2895 {
2896         wlc_hw->antsel_type = antsel_type;
2897
2898         /* Update the antsel type for phy module to use */
2899         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2900 }
2901
2902 void wlc_bmac_fifoerrors(wlc_hw_info_t *wlc_hw)
2903 {
2904         bool fatal = FALSE;
2905         uint unit;
2906         uint intstatus, idx;
2907         d11regs_t *regs = wlc_hw->regs;
2908
2909         unit = wlc_hw->unit;
2910
2911         for (idx = 0; idx < NFIFO; idx++) {
2912                 /* read intstatus register and ignore any non-error bits */
2913                 intstatus =
2914                     R_REG(wlc_hw->osh,
2915                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2916                 if (!intstatus)
2917                         continue;
2918
2919                 WL_TRACE(("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n", unit,
2920                           idx, intstatus));
2921
2922                 if (intstatus & I_RO) {
2923                         WL_ERROR(("wl%d: fifo %d: receive fifo overflow\n",
2924                                   unit, idx));
2925                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
2926                         fatal = TRUE;
2927                 }
2928
2929                 if (intstatus & I_PC) {
2930                         WL_ERROR(("wl%d: fifo %d: descriptor error\n", unit,
2931                                   idx));
2932                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
2933                         fatal = TRUE;
2934                 }
2935
2936                 if (intstatus & I_PD) {
2937                         WL_ERROR(("wl%d: fifo %d: data error\n", unit, idx));
2938                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
2939                         fatal = TRUE;
2940                 }
2941
2942                 if (intstatus & I_DE) {
2943                         WL_ERROR(("wl%d: fifo %d: descriptor protocol error\n",
2944                                   unit, idx));
2945                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
2946                         fatal = TRUE;
2947                 }
2948
2949                 if (intstatus & I_RU) {
2950                         WL_ERROR(("wl%d: fifo %d: receive descriptor underflow\n", unit, idx));
2951                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2952                 }
2953
2954                 if (intstatus & I_XU) {
2955                         WL_ERROR(("wl%d: fifo %d: transmit fifo underflow\n",
2956                                   idx, unit));
2957                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
2958                         fatal = TRUE;
2959                 }
2960
2961                 if (fatal) {
2962                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2963                         break;
2964                 } else
2965                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2966                               intstatus);
2967         }
2968 }
2969
2970 void wlc_intrson(wlc_info_t *wlc)
2971 {
2972         wlc_hw_info_t *wlc_hw = wlc->hw;
2973         ASSERT(wlc->defmacintmask);
2974         wlc->macintmask = wlc->defmacintmask;
2975         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2976 }
2977
2978 /* callback for siutils.c, which has only wlc handler, no wl
2979  * they both check up, not only because there is no need to off/restore d11 interrupt
2980  *  but also because per-port code may require sync with valid interrupt.
2981  */
2982
2983 static u32 wlc_wlintrsoff(wlc_info_t *wlc)
2984 {
2985         if (!wlc->hw->up)
2986                 return 0;
2987
2988         return wl_intrsoff(wlc->wl);
2989 }
2990
2991 static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask)
2992 {
2993         if (!wlc->hw->up)
2994                 return;
2995
2996         wl_intrsrestore(wlc->wl, macintmask);
2997 }
2998
2999 u32 wlc_intrsoff(wlc_info_t *wlc)
3000 {
3001         wlc_hw_info_t *wlc_hw = wlc->hw;
3002         u32 macintmask;
3003
3004         if (!wlc_hw->clk)
3005                 return 0;
3006
3007         macintmask = wlc->macintmask;   /* isr can still happen */
3008
3009         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
3010         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
3011         OSL_DELAY(1);           /* ensure int line is no longer driven */
3012         wlc->macintmask = 0;
3013
3014         /* return previous macintmask; resolve race between us and our isr */
3015         return wlc->macintstatus ? 0 : macintmask;
3016 }
3017
3018 void wlc_intrsrestore(wlc_info_t *wlc, u32 macintmask)
3019 {
3020         wlc_hw_info_t *wlc_hw = wlc->hw;
3021         if (!wlc_hw->clk)
3022                 return;
3023
3024         wlc->macintmask = macintmask;
3025         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
3026 }
3027
3028 void wlc_bmac_mute(wlc_hw_info_t *wlc_hw, bool on, mbool flags)
3029 {
3030         struct ether_addr null_ether_addr = { {0, 0, 0, 0, 0, 0} };
3031
3032         if (on) {
3033                 /* suspend tx fifos */
3034                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
3035                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
3036                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
3037                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
3038
3039                 /* zero the address match register so we do not send ACKs */
3040                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3041                                        &null_ether_addr);
3042         } else {
3043                 /* resume tx fifos */
3044                 if (!wlc_hw->wlc->tx_suspended) {
3045                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3046                 }
3047                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3048                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3049                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3050
3051                 /* Restore address */
3052                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3053                                        &wlc_hw->etheraddr);
3054         }
3055
3056         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3057
3058         if (on)
3059                 wlc_ucode_mute_override_set(wlc_hw);
3060         else
3061                 wlc_ucode_mute_override_clear(wlc_hw);
3062 }
3063
3064 void wlc_bmac_set_deaf(wlc_hw_info_t *wlc_hw, bool user_flag)
3065 {
3066         wlc_phy_set_deaf(wlc_hw->band->pi, user_flag);
3067 }
3068
3069 int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t *wlc_hw, uint fifo, uint *blocks)
3070 {
3071         if (fifo >= NFIFO)
3072                 return BCME_RANGE;
3073
3074         *blocks = wlc_hw->xmtfifo_sz[fifo];
3075
3076         return 0;
3077 }
3078
3079 int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, uint blocks)
3080 {
3081         if (fifo >= NFIFO || blocks > 299)
3082                 return BCME_RANGE;
3083
3084         /* BMAC_NOTE, change blocks to u16 */
3085         wlc_hw->xmtfifo_sz[fifo] = (u16) blocks;
3086
3087         return 0;
3088 }
3089
3090 /* wlc_bmac_tx_fifo_suspended:
3091  * Check the MAC's tx suspend status for a tx fifo.
3092  *
3093  * When the MAC acknowledges a tx suspend, it indicates that no more
3094  * packets will be transmitted out the radio. This is independent of
3095  * DMA channel suspension---the DMA may have finished suspending, or may still
3096  * be pulling data into a tx fifo, by the time the MAC acks the suspend
3097  * request.
3098  */
3099 bool wlc_bmac_tx_fifo_suspended(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3100 {
3101         /* check that a suspend has been requested and is no longer pending */
3102
3103         /*
3104          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3105          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3106          * chnstatus register.
3107          * The tx fifo suspend completion is independent of the DMA suspend completion and
3108          *   may be acked before or after the DMA is suspended.
3109          */
3110         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3111             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3112              (1 << tx_fifo)) == 0)
3113                 return TRUE;
3114
3115         return FALSE;
3116 }
3117
3118 void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3119 {
3120         u8 fifo = 1 << tx_fifo;
3121
3122         /* Two clients of this code, 11h Quiet period and scanning. */
3123
3124         /* only suspend if not already suspended */
3125         if ((wlc_hw->suspended_fifos & fifo) == fifo)
3126                 return;
3127
3128         /* force the core awake only if not already */
3129         if (wlc_hw->suspended_fifos == 0)
3130                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3131
3132         wlc_hw->suspended_fifos |= fifo;
3133
3134         if (wlc_hw->di[tx_fifo]) {
3135                 /* Suspending AMPDU transmissions in the middle can cause underflow
3136                  * which may result in mismatch between ucode and driver
3137                  * so suspend the mac before suspending the FIFO
3138                  */
3139                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3140                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
3141
3142                 dma_txsuspend(wlc_hw->di[tx_fifo]);
3143
3144                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3145                         wlc_enable_mac(wlc_hw->wlc);
3146         }
3147 }
3148
3149 void wlc_bmac_tx_fifo_resume(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3150 {
3151         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3152          * here for PIO otherwise the watchdog will catch the inconsistency and fire
3153          */
3154         /* Two clients of this code, 11h Quiet period and scanning. */
3155         if (wlc_hw->di[tx_fifo])
3156                 dma_txresume(wlc_hw->di[tx_fifo]);
3157
3158         /* allow core to sleep again */
3159         if (wlc_hw->suspended_fifos == 0)
3160                 return;
3161         else {
3162                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3163                 if (wlc_hw->suspended_fifos == 0)
3164                         wlc_ucode_wake_override_clear(wlc_hw,
3165                                                       WLC_WAKE_OVERRIDE_TXFIFO);
3166         }
3167 }
3168
3169 /*
3170  * Read and clear macintmask and macintstatus and intstatus registers.
3171  * This routine should be called with interrupts off
3172  * Return:
3173  *   -1 if DEVICEREMOVED(wlc) evaluates to TRUE;
3174  *   0 if the interrupt is not for us, or we are in some special cases;
3175  *   device interrupt status bits otherwise.
3176  */
3177 static inline u32 wlc_intstatus(wlc_info_t *wlc, bool in_isr)
3178 {
3179         wlc_hw_info_t *wlc_hw = wlc->hw;
3180         d11regs_t *regs = wlc_hw->regs;
3181         u32 macintstatus;
3182         u32 intstatus_rxfifo, intstatus_txsfifo;
3183         osl_t *osh;
3184
3185         osh = wlc_hw->osh;
3186
3187         /* macintstatus includes a DMA interrupt summary bit */
3188         macintstatus = R_REG(osh, &regs->macintstatus);
3189
3190         WL_TRACE(("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus));
3191
3192         /* detect cardbus removed, in power down(suspend) and in reset */
3193         if (DEVICEREMOVED(wlc))
3194                 return -1;
3195
3196         /* DEVICEREMOVED succeeds even when the core is still resetting,
3197          * handle that case here.
3198          */
3199         if (macintstatus == 0xffffffff)
3200                 return 0;
3201
3202         /* defer unsolicited interrupts */
3203         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3204
3205         /* if not for us */
3206         if (macintstatus == 0)
3207                 return 0;
3208
3209         /* interrupts are already turned off for CFE build
3210          * Caution: For CFE Turning off the interrupts again has some undesired
3211          * consequences
3212          */
3213         /* turn off the interrupts */
3214         W_REG(osh, &regs->macintmask, 0);
3215 #ifndef BCMSDIO
3216         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3217 #endif
3218         wlc->macintmask = 0;
3219
3220         /* clear device interrupts */
3221         W_REG(osh, &regs->macintstatus, macintstatus);
3222
3223         /* MI_DMAINT is indication of non-zero intstatus */
3224         if (macintstatus & MI_DMAINT) {
3225                 if (D11REV_IS(wlc_hw->corerev, 4)) {
3226                         intstatus_rxfifo =
3227                             R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3228                         intstatus_txsfifo =
3229                             R_REG(osh,
3230                                   &regs->intctrlregs[RX_TXSTATUS_FIFO].
3231                                   intstatus);
3232                         WL_TRACE(("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n", wlc_hw->unit, intstatus_rxfifo, intstatus_txsfifo));
3233
3234                         /* defer unsolicited interrupt hints */
3235                         intstatus_rxfifo &= DEF_RXINTMASK;
3236                         intstatus_txsfifo &= DEF_RXINTMASK;
3237
3238                         /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3239                         /* clear interrupt hints */
3240                         if (intstatus_rxfifo)
3241                                 W_REG(osh,
3242                                       &regs->intctrlregs[RX_FIFO].intstatus,
3243                                       intstatus_rxfifo);
3244                         else
3245                                 macintstatus &= ~MI_DMAINT;
3246
3247                         /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3248                         if (intstatus_txsfifo) {
3249                                 W_REG(osh,
3250                                       &regs->intctrlregs[RX_TXSTATUS_FIFO].
3251                                       intstatus, intstatus_txsfifo);
3252                                 macintstatus |= MI_TFS;
3253                         }
3254                 } else {
3255                         /*
3256                          * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3257                          * If MI_DMAINT is set, assume it is set and clear the interrupt.
3258                          */
3259                         W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3260                               DEF_RXINTMASK);
3261                 }
3262         }
3263
3264         return macintstatus;
3265 }
3266
3267 /* Update wlc->macintstatus and wlc->intstatus[]. */
3268 /* Return TRUE if they are updated successfully. FALSE otherwise */
3269 bool wlc_intrsupd(wlc_info_t *wlc)
3270 {
3271         u32 macintstatus;
3272
3273         ASSERT(wlc->macintstatus != 0);
3274
3275         /* read and clear macintstatus and intstatus registers */
3276         macintstatus = wlc_intstatus(wlc, FALSE);
3277
3278         /* device is removed */
3279         if (macintstatus == 0xffffffff)
3280                 return FALSE;
3281
3282         /* update interrupt status in software */
3283         wlc->macintstatus |= macintstatus;
3284
3285         return TRUE;
3286 }
3287
3288 /*
3289  * First-level interrupt processing.
3290  * Return TRUE if this was our interrupt, FALSE otherwise.
3291  * *wantdpc will be set to TRUE if further wlc_dpc() processing is required,
3292  * FALSE otherwise.
3293  */
3294 bool BCMFASTPATH wlc_isr(wlc_info_t *wlc, bool *wantdpc)
3295 {
3296         wlc_hw_info_t *wlc_hw = wlc->hw;
3297         u32 macintstatus;
3298
3299         *wantdpc = FALSE;
3300
3301         if (!wlc_hw->up || !wlc->macintmask)
3302                 return FALSE;
3303
3304         /* read and clear macintstatus and intstatus registers */
3305         macintstatus = wlc_intstatus(wlc, TRUE);
3306
3307         if (macintstatus == 0xffffffff)
3308                 WL_ERROR(("DEVICEREMOVED detected in the ISR code path.\n"));
3309
3310         /* it is not for us */
3311         if (macintstatus == 0)
3312                 return FALSE;
3313
3314         *wantdpc = TRUE;
3315
3316         /* save interrupt status bits */
3317         ASSERT(wlc->macintstatus == 0);
3318         wlc->macintstatus = macintstatus;
3319
3320         return TRUE;
3321
3322 }
3323
3324 /* process tx completion events for corerev < 5 */
3325 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc_hw)
3326 {
3327         void *status_p;
3328         tx_status_t *txs;
3329         osl_t *osh;
3330         bool fatal = FALSE;
3331
3332         WL_TRACE(("wl%d: wlc_txstatusrecv\n", wlc_hw->unit));
3333
3334         osh = wlc_hw->osh;
3335
3336         while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3337
3338                 txs = (tx_status_t *) PKTDATA(status_p);
3339                 /* MAC uses little endian only */
3340                 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3341
3342                 /* shift low bits for tx_status_t status compatibility */
3343                 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3344                     | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3345
3346                 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3347
3348                 PKTFREE(osh, status_p, FALSE);
3349         }
3350
3351         if (fatal)
3352                 return TRUE;
3353
3354         /* post more rbufs */
3355         dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3356
3357         return FALSE;
3358 }
3359
3360 static bool BCMFASTPATH
3361 wlc_bmac_dotxstatus(wlc_hw_info_t *wlc_hw, tx_status_t *txs, u32 s2)
3362 {
3363         /* discard intermediate indications for ucode with one legitimate case:
3364          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3365          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3366          *   transmission count)
3367          */
3368         if (!(txs->status & TX_STATUS_AMPDU)
3369             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3370                 return FALSE;
3371         }
3372
3373         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3374 }
3375
3376 /* process tx completion events in BMAC
3377  * Return TRUE if more tx status need to be processed. FALSE otherwise.
3378  */
3379 static bool BCMFASTPATH
3380 wlc_bmac_txstatus(wlc_hw_info_t *wlc_hw, bool bound, bool *fatal)
3381 {
3382         bool morepending = FALSE;
3383         wlc_info_t *wlc = wlc_hw->wlc;
3384
3385         WL_TRACE(("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit));
3386
3387         if (D11REV_IS(wlc_hw->corerev, 4)) {
3388                 /* to retire soon */
3389                 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3390
3391                 if (*fatal)
3392                         return 0;
3393         } else {
3394                 /* corerev >= 5 */
3395                 d11regs_t *regs;
3396                 osl_t *osh;
3397                 tx_status_t txstatus, *txs;
3398                 u32 s1, s2;
3399                 uint n = 0;
3400                 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3401                 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3402
3403                 txs = &txstatus;
3404                 regs = wlc_hw->regs;
3405                 osh = wlc_hw->osh;
3406                 while (!(*fatal)
3407                        && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3408
3409                         if (s1 == 0xffffffff) {
3410                                 WL_ERROR(("wl%d: %s: dead chip\n",
3411                                           wlc_hw->unit, __func__));
3412                                 ASSERT(s1 != 0xffffffff);
3413                                 return morepending;
3414                         }
3415
3416                         s2 = R_REG(osh, &regs->frmtxstatus2);
3417
3418                         txs->status = s1 & TXS_STATUS_MASK;
3419                         txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3420                         txs->sequence = s2 & TXS_SEQ_MASK;
3421                         txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3422                         txs->lasttxtime = 0;
3423
3424                         *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3425
3426                         /* !give others some time to run! */
3427                         if (++n >= max_tx_num)
3428                                 break;
3429                 }
3430
3431                 if (*fatal)
3432                         return 0;
3433
3434                 if (n >= max_tx_num)
3435                         morepending = TRUE;
3436         }
3437
3438         if (!pktq_empty(&wlc->active_queue->q))
3439                 wlc_send_q(wlc, wlc->active_queue);
3440
3441         return morepending;
3442 }
3443
3444 void wlc_suspend_mac_and_wait(wlc_info_t *wlc)
3445 {
3446         wlc_hw_info_t *wlc_hw = wlc->hw;
3447         d11regs_t *regs = wlc_hw->regs;
3448         u32 mc, mi;
3449         osl_t *osh;
3450
3451         WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw->unit,
3452                   wlc_hw->band->bandunit));
3453
3454         /*
3455          * Track overlapping suspend requests
3456          */
3457         wlc_hw->mac_suspend_depth++;
3458         if (wlc_hw->mac_suspend_depth > 1)
3459                 return;
3460
3461         osh = wlc_hw->osh;
3462
3463         /* force the core awake */
3464         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3465
3466         mc = R_REG(osh, &regs->maccontrol);
3467
3468         if (mc == 0xffffffff) {
3469                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3470                 wl_down(wlc->wl);
3471                 return;
3472         }
3473         ASSERT(!(mc & MCTL_PSM_JMP_0));
3474         ASSERT(mc & MCTL_PSM_RUN);
3475         ASSERT(mc & MCTL_EN_MAC);
3476
3477         mi = R_REG(osh, &regs->macintstatus);
3478         if (mi == 0xffffffff) {
3479                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3480                 wl_down(wlc->wl);
3481                 return;
3482         }
3483         ASSERT(!(mi & MI_MACSSPNDD));
3484
3485         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3486
3487         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3488                  WLC_MAX_MAC_SUSPEND);
3489
3490         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3491                 WL_ERROR(("wl%d: wlc_suspend_mac_and_wait: waited %d uS and "
3492                           "MI_MACSSPNDD is still not on.\n",
3493                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND));
3494                 WL_ERROR(("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n", wlc_hw->unit, R_REG(osh, &regs->psmdebug), R_REG(osh, &regs->phydebug), R_REG(osh, &regs->psm_brc)));
3495         }
3496
3497         mc = R_REG(osh, &regs->maccontrol);
3498         if (mc == 0xffffffff) {
3499                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3500                 wl_down(wlc->wl);
3501                 return;
3502         }
3503         ASSERT(!(mc & MCTL_PSM_JMP_0));
3504         ASSERT(mc & MCTL_PSM_RUN);
3505         ASSERT(!(mc & MCTL_EN_MAC));
3506 }
3507
3508 void wlc_enable_mac(wlc_info_t *wlc)
3509 {
3510         wlc_hw_info_t *wlc_hw = wlc->hw;
3511         d11regs_t *regs = wlc_hw->regs;
3512         u32 mc, mi;
3513         osl_t *osh;
3514
3515         WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw->unit,
3516                   wlc->band->bandunit));
3517
3518         /*
3519          * Track overlapping suspend requests
3520          */
3521         ASSERT(wlc_hw->mac_suspend_depth > 0);
3522         wlc_hw->mac_suspend_depth--;
3523         if (wlc_hw->mac_suspend_depth > 0)
3524                 return;
3525
3526         osh = wlc_hw->osh;
3527
3528         mc = R_REG(osh, &regs->maccontrol);
3529         ASSERT(!(mc & MCTL_PSM_JMP_0));
3530         ASSERT(!(mc & MCTL_EN_MAC));
3531         ASSERT(mc & MCTL_PSM_RUN);
3532
3533         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3534         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3535
3536         mc = R_REG(osh, &regs->maccontrol);
3537         ASSERT(!(mc & MCTL_PSM_JMP_0));
3538         ASSERT(mc & MCTL_EN_MAC);
3539         ASSERT(mc & MCTL_PSM_RUN);
3540
3541         mi = R_REG(osh, &regs->macintstatus);
3542         ASSERT(!(mi & MI_MACSSPNDD));
3543
3544         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3545 }
3546
3547 void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t *wlc_hw, bool abie, bool isht)
3548 {
3549         if (!(WLCISNPHY(wlc_hw->band) && (D11REV_GE(wlc_hw->corerev, 16))))
3550                 return;
3551
3552         if (isht) {
3553                 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 3)) {
3554                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3555                                 ~IFS_CTL1_EDCRS);
3556                 }
3557         } else {
3558                 /* enable EDCRS for non-11n association */
3559                 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1, IFS_CTL1_EDCRS);
3560         }
3561
3562         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3)) {
3563                 if (CHSPEC_IS20(wlc_hw->chanspec)) {
3564                         /* 20 mhz, use 20U ED only */
3565                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3566                                IFS_CTL1_EDCRS);
3567                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3568                                 ~IFS_CTL1_EDCRS_20L);
3569                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3570                                 ~IFS_CTL1_EDCRS_40);
3571                 } else {
3572                         /* 40 mhz, use 20U 20L and 40 ED */
3573                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3574                                IFS_CTL1_EDCRS);
3575                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3576                                IFS_CTL1_EDCRS_20L);
3577                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3578                                IFS_CTL1_EDCRS_40);
3579                 }
3580         }
3581 }
3582
3583 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw)
3584 {
3585         u8 rate;
3586         u8 rates[8] = {
3587                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3588                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3589         };
3590         u16 entry_ptr;
3591         u16 pctl1;
3592         uint i;
3593
3594         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3595                 return;
3596
3597         /* walk the phy rate table and update the entries */
3598         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3599                 rate = rates[i];
3600
3601                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3602
3603                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3604                 pctl1 =
3605                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3606
3607                 /* modify the value */
3608                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3609                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3610
3611                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3612                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3613                                    pctl1);
3614         }
3615 }
3616
3617 static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, u8 rate)
3618 {
3619         uint i;
3620         u8 plcp_rate = 0;
3621         struct plcp_signal_rate_lookup {
3622                 u8 rate;
3623                 u8 signal_rate;
3624         };
3625         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3626         const struct plcp_signal_rate_lookup rate_lookup[] = {
3627                 {WLC_RATE_6M, 0xB},
3628                 {WLC_RATE_9M, 0xF},
3629                 {WLC_RATE_12M, 0xA},
3630                 {WLC_RATE_18M, 0xE},
3631                 {WLC_RATE_24M, 0x9},
3632                 {WLC_RATE_36M, 0xD},
3633                 {WLC_RATE_48M, 0x8},
3634                 {WLC_RATE_54M, 0xC}
3635         };
3636
3637         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3638                 if (rate == rate_lookup[i].rate) {
3639                         plcp_rate = rate_lookup[i].signal_rate;
3640                         break;
3641                 }
3642         }
3643
3644         /* Find the SHM pointer to the rate table entry by looking in the
3645          * Direct-map Table
3646          */
3647         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3648 }
3649
3650 void wlc_bmac_band_stf_ss_set(wlc_hw_info_t *wlc_hw, u8 stf_mode)
3651 {
3652         wlc_hw->hw_stf_ss_opmode = stf_mode;
3653
3654         if (wlc_hw->clk)
3655                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3656 }
3657
3658 void BCMFASTPATH
3659 wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, u32 *tsf_l_ptr,
3660                   u32 *tsf_h_ptr)
3661 {
3662         d11regs_t *regs = wlc_hw->regs;
3663
3664         /* read the tsf timer low, then high to get an atomic read */
3665         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3666         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3667
3668         return;
3669 }
3670
3671 bool BCMATTACHFN(wlc_bmac_validate_chip_access) (wlc_hw_info_t *wlc_hw)
3672 {
3673         d11regs_t *regs;
3674         u32 w, val;
3675         volatile u16 *reg16;
3676         osl_t *osh;
3677
3678         WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw->unit));
3679
3680         regs = wlc_hw->regs;
3681         osh = wlc_hw->osh;
3682
3683         /* Validate dchip register access */
3684
3685         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3686         (void)R_REG(osh, &regs->objaddr);
3687         w = R_REG(osh, &regs->objdata);
3688
3689         /* Can we write and read back a 32bit register? */
3690         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3691         (void)R_REG(osh, &regs->objaddr);
3692         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3693
3694         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3695         (void)R_REG(osh, &regs->objaddr);
3696         val = R_REG(osh, &regs->objdata);
3697         if (val != (u32) 0xaa5555aa) {
3698                 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val));
3699                 return FALSE;
3700         }
3701
3702         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3703         (void)R_REG(osh, &regs->objaddr);
3704         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3705
3706         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3707         (void)R_REG(osh, &regs->objaddr);
3708         val = R_REG(osh, &regs->objdata);
3709         if (val != (u32) 0x55aaaa55) {
3710                 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val));
3711                 return FALSE;
3712         }
3713
3714         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3715         (void)R_REG(osh, &regs->objaddr);
3716         W_REG(osh, &regs->objdata, w);
3717
3718         if (D11REV_LT(wlc_hw->corerev, 11)) {
3719                 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3720                  * for our interface, low to high
3721                  */
3722                 reg16 = (volatile u16 *)(uintptr) & regs->tsf_cfpstart;
3723
3724                 /* write the CFPStart register low half explicitly, starting a buffered write */
3725                 W_REG(osh, reg16, 0xAAAA);
3726
3727                 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3728                  * If the low 16 bits are written first, followed by the high 16 bits then the
3729                  * 32 bit value 0xCCCCBBBB should end up in the register.
3730                  * If the order is reversed, then the write to the high half will trigger a buffered
3731                  * write of 0xCCCCAAAA.
3732                  * If the bus is 32 bits, then this is not much of a test, and the reg should
3733                  * have the correct value 0xCCCCBBBB.
3734                  */
3735                 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3736
3737                 /* verify with the 16 bit registers that have no side effects */
3738                 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3739                 if (val != (uint) 0xBBBB) {
3740                         WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xBBBB));
3741                         return FALSE;
3742                 }
3743                 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3744                 if (val != (uint) 0xCCCC) {
3745                         WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xCCCC));
3746                         return FALSE;
3747                 }
3748
3749         }
3750
3751         /* clear CFPStart */
3752         W_REG(osh, &regs->tsf_cfpstart, 0);
3753
3754         w = R_REG(osh, &regs->maccontrol);
3755         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3756             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3757                 WL_ERROR(("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, (MCTL_IHR_EN | MCTL_WAKE), (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)));
3758                 return FALSE;
3759         }
3760
3761         return TRUE;
3762 }
3763
3764 #define PHYPLL_WAIT_US  100000
3765
3766 void wlc_bmac_core_phypll_ctl(wlc_hw_info_t *wlc_hw, bool on)
3767 {
3768         d11regs_t *regs;
3769         osl_t *osh;
3770         u32 tmp;
3771
3772         WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit));
3773
3774         tmp = 0;
3775         regs = wlc_hw->regs;
3776         osh = wlc_hw->osh;
3777
3778         if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3779                 return;
3780
3781         if (on) {
3782                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3783                         OR_REG(osh, &regs->clk_ctl_st,
3784                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3785                                 CCS_ERSRC_REQ_PHYPLL));
3786                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3787                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3788                                  PHYPLL_WAIT_US);
3789
3790                         tmp = R_REG(osh, &regs->clk_ctl_st);
3791                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3792                             (CCS_ERSRC_AVAIL_HT)) {
3793                                 WL_ERROR(("%s: turn on PHY PLL failed\n",
3794                                           __func__));
3795                                 ASSERT(0);
3796                         }
3797                 } else {
3798                         OR_REG(osh, &regs->clk_ctl_st,
3799                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3800                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3801                                   (CCS_ERSRC_AVAIL_D11PLL |
3802                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3803                                  (CCS_ERSRC_AVAIL_D11PLL |
3804                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3805
3806                         tmp = R_REG(osh, &regs->clk_ctl_st);
3807                         if ((tmp &
3808                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3809                             !=
3810                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3811                                 WL_ERROR(("%s: turn on PHY PLL failed\n",
3812                                           __func__));
3813                                 ASSERT(0);
3814                         }
3815                 }
3816         } else {
3817                 /* Since the PLL may be shared, other cores can still be requesting it;
3818                  * so we'll deassert the request but not wait for status to comply.
3819                  */
3820                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3821                 tmp = R_REG(osh, &regs->clk_ctl_st);
3822         }
3823 }
3824
3825 void wlc_coredisable(wlc_hw_info_t *wlc_hw)
3826 {
3827         bool dev_gone;
3828
3829         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
3830
3831         ASSERT(!wlc_hw->up);
3832
3833         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3834
3835         if (dev_gone)
3836                 return;
3837
3838         if (wlc_hw->noreset)
3839                 return;
3840
3841         /* radio off */
3842         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3843
3844         /* turn off analog core */
3845         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3846
3847         /* turn off PHYPLL to save power */
3848         wlc_bmac_core_phypll_ctl(wlc_hw, FALSE);
3849
3850         /* No need to set wlc->pub->radio_active = OFF
3851          * because this function needs down capability and
3852          * radio_active is designed for BCMNODOWN.
3853          */
3854
3855         /* remove gpio controls */
3856         if (wlc_hw->ucode_dbgsel)
3857                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3858
3859         wlc_hw->clk = FALSE;
3860         si_core_disable(wlc_hw->sih, 0);
3861         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, FALSE);
3862 }
3863
3864 /* power both the pll and external oscillator on/off */
3865 void wlc_bmac_xtal(wlc_hw_info_t *wlc_hw, bool want)
3866 {
3867         WL_TRACE(("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want));
3868
3869         /* dont power down if plldown is false or we must poll hw radio disable */
3870         if (!want && wlc_hw->pllreq)
3871                 return;
3872
3873         if (wlc_hw->sih)
3874                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3875
3876         wlc_hw->sbclk = want;
3877         if (!wlc_hw->sbclk) {
3878                 wlc_hw->clk = FALSE;
3879                 if (wlc_hw->band && wlc_hw->band->pi)
3880                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, FALSE);
3881         }
3882 }
3883
3884 static void wlc_flushqueues(wlc_info_t *wlc)
3885 {
3886         wlc_hw_info_t *wlc_hw = wlc->hw;
3887         uint i;
3888
3889         wlc->txpend16165war = 0;
3890
3891         /* free any posted tx packets */
3892         for (i = 0; i < NFIFO; i++)
3893                 if (wlc_hw->di[i]) {
3894                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3895                         TXPKTPENDCLR(wlc, i);
3896                         WL_TRACE(("wlc_flushqueues: pktpend fifo %d cleared\n",
3897                                   i));
3898                 }
3899
3900         /* free any posted rx packets */
3901         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3902         if (D11REV_IS(wlc_hw->corerev, 4))
3903                 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3904 }
3905
3906 u16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset)
3907 {
3908         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3909 }
3910
3911 void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v)
3912 {
3913         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3914 }
3915
3916 /* Set a range of shared memory to a value.
3917  * SHM 'offset' needs to be an even address and
3918  * Buffer length 'len' must be an even number of bytes
3919  */
3920 void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v, int len)
3921 {
3922         int i;
3923
3924         /* offset and len need to be even */
3925         ASSERT((offset & 1) == 0);
3926         ASSERT((len & 1) == 0);
3927
3928         if (len <= 0)
3929                 return;
3930
3931         for (i = 0; i < len; i += 2) {
3932                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3933         }
3934 }
3935
3936 static u16
3937 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, u32 sel)
3938 {
3939         d11regs_t *regs = wlc_hw->regs;
3940         volatile u16 *objdata_lo =
3941             (volatile u16 *)(uintptr) & regs->objdata;
3942         volatile u16 *objdata_hi = objdata_lo + 1;
3943         u16 v;
3944
3945         ASSERT((offset & 1) == 0);
3946
3947         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3948         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3949         if (offset & 2) {
3950                 v = R_REG(wlc_hw->osh, objdata_hi);
3951         } else {
3952                 v = R_REG(wlc_hw->osh, objdata_lo);
3953         }
3954
3955         return v;
3956 }
3957
3958 static void
3959 wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, u32 sel)
3960 {
3961         d11regs_t *regs = wlc_hw->regs;
3962         volatile u16 *objdata_lo =
3963             (volatile u16 *)(uintptr) & regs->objdata;
3964         volatile u16 *objdata_hi = objdata_lo + 1;
3965
3966         ASSERT((offset & 1) == 0);
3967
3968         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3969         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3970         if (offset & 2) {
3971                 W_REG(wlc_hw->osh, objdata_hi, v);
3972         } else {
3973                 W_REG(wlc_hw->osh, objdata_lo, v);
3974         }
3975 }
3976
3977 /* Copy a buffer to shared memory of specified type .
3978  * SHM 'offset' needs to be an even address and
3979  * Buffer length 'len' must be an even number of bytes
3980  * 'sel' selects the type of memory
3981  */
3982 void
3983 wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf,
3984                        int len, u32 sel)
3985 {
3986         u16 v;
3987         const u8 *p = (const u8 *)buf;
3988         int i;
3989
3990         /* offset and len need to be even */
3991         ASSERT((offset & 1) == 0);
3992         ASSERT((len & 1) == 0);
3993
3994         if (len <= 0)
3995                 return;
3996
3997         for (i = 0; i < len; i += 2) {
3998                 v = p[i] | (p[i + 1] << 8);
3999                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
4000         }
4001 }
4002
4003 /* Copy a piece of shared memory of specified type to a buffer .
4004  * SHM 'offset' needs to be an even address and
4005  * Buffer length 'len' must be an even number of bytes
4006  * 'sel' selects the type of memory
4007  */
4008 void
4009 wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf,
4010                          int len, u32 sel)
4011 {
4012         u16 v;
4013         u8 *p = (u8 *) buf;
4014         int i;
4015
4016         /* offset and len need to be even */
4017         ASSERT((offset & 1) == 0);
4018         ASSERT((len & 1) == 0);
4019
4020         if (len <= 0)
4021                 return;
4022
4023         for (i = 0; i < len; i += 2) {
4024                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
4025                 p[i] = v & 0xFF;
4026                 p[i + 1] = (v >> 8) & 0xFF;
4027         }
4028 }
4029
4030 void wlc_bmac_copyfrom_vars(wlc_hw_info_t *wlc_hw, char **buf, uint *len)
4031 {
4032         WL_TRACE(("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
4033                   wlc_hw->vars_size));
4034
4035         *buf = wlc_hw->vars;
4036         *len = wlc_hw->vars_size;
4037 }
4038
4039 void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, u16 SRL, u16 LRL)
4040 {
4041         wlc_hw->SRL = SRL;
4042         wlc_hw->LRL = LRL;
4043
4044         /* write retry limit to SCR, shouldn't need to suspend */
4045         if (wlc_hw->up) {
4046                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4047                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
4048                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4049                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
4050                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4051                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
4052                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4053                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
4054         }
4055 }
4056
4057 void wlc_bmac_set_noreset(wlc_hw_info_t *wlc_hw, bool noreset_flag)
4058 {
4059         wlc_hw->noreset = noreset_flag;
4060 }
4061
4062 void wlc_bmac_set_ucode_loaded(wlc_hw_info_t *wlc_hw, bool ucode_loaded)
4063 {
4064         wlc_hw->ucode_loaded = ucode_loaded;
4065 }
4066
4067 void wlc_bmac_pllreq(wlc_hw_info_t *wlc_hw, bool set, mbool req_bit)
4068 {
4069         ASSERT(req_bit);
4070
4071         if (set) {
4072                 if (mboolisset(wlc_hw->pllreq, req_bit))
4073                         return;
4074
4075                 mboolset(wlc_hw->pllreq, req_bit);
4076
4077                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4078                         if (!wlc_hw->sbclk) {
4079                                 wlc_bmac_xtal(wlc_hw, ON);
4080                         }
4081                 }
4082         } else {
4083                 if (!mboolisset(wlc_hw->pllreq, req_bit))
4084                         return;
4085
4086                 mboolclr(wlc_hw->pllreq, req_bit);
4087
4088                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4089                         if (wlc_hw->sbclk) {
4090                                 wlc_bmac_xtal(wlc_hw, OFF);
4091                         }
4092                 }
4093         }
4094
4095         return;
4096 }
4097
4098 void wlc_bmac_set_clk(wlc_hw_info_t *wlc_hw, bool on)
4099 {
4100         if (on) {
4101                 /* power up pll and oscillator */
4102                 wlc_bmac_xtal(wlc_hw, ON);
4103
4104                 /* enable core(s), ignore bandlocked
4105                  * Leave with the same band selected as we entered
4106                  */
4107                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
4108         } else {
4109                 /* if already down, must skip the core disable */
4110                 if (wlc_hw->clk) {
4111                         /* disable core(s), ignore bandlocked */
4112                         wlc_coredisable(wlc_hw);
4113                 }
4114                 /* power down pll and oscillator */
4115                 wlc_bmac_xtal(wlc_hw, OFF);
4116         }
4117 }
4118
4119 /* this will be true for all ai chips */
4120 bool wlc_bmac_taclear(wlc_hw_info_t *wlc_hw, bool ta_ok)
4121 {
4122         return TRUE;
4123 }
4124
4125 /* Lower down relevant GPIOs like LED when going down w/o
4126  * doing PCI config cycles or touching interrupts
4127  */
4128 void wlc_gpio_fast_deinit(wlc_hw_info_t *wlc_hw)
4129 {
4130         if ((wlc_hw == NULL) || (wlc_hw->sih == NULL))
4131                 return;
4132
4133         /* Only chips with internal bus or PCIE cores or certain PCI cores
4134          * are able to switch cores w/o disabling interrupts
4135          */
4136         if (!((BUSTYPE(wlc_hw->sih->bustype) == SI_BUS) ||
4137               ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) &&
4138                ((wlc_hw->sih->buscoretype == PCIE_CORE_ID) ||
4139                 (wlc_hw->sih->buscorerev >= 13)))))
4140                 return;
4141
4142         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
4143         return;
4144 }
4145
4146 bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable)
4147 {
4148         /* Do not access Phy registers if core is not up */
4149         if (si_iscoreup(wlc_hw->sih) == FALSE)
4150                 return FALSE;
4151
4152         if (enable) {
4153                 if (PMUCTL_ENAB(wlc_hw->sih)) {
4154                         AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4155                                 ~CCS_FORCEHWREQOFF);
4156                         si_pmu_radio_enable(wlc_hw->sih, TRUE);
4157                 }
4158
4159                 wlc_phy_anacore(wlc_hw->band->pi, ON);
4160                 wlc_phy_switch_radio(wlc_hw->band->pi, ON);
4161
4162                 /* resume d11 core */
4163                 wlc_enable_mac(wlc_hw->wlc);
4164         } else {
4165                 /* suspend d11 core */
4166                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
4167
4168                 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
4169                 wlc_phy_anacore(wlc_hw->band->pi, OFF);
4170
4171                 if (PMUCTL_ENAB(wlc_hw->sih)) {
4172                         si_pmu_radio_enable(wlc_hw->sih, FALSE);
4173                         OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4174                                CCS_FORCEHWREQOFF);
4175                 }
4176         }
4177
4178         return TRUE;
4179 }
4180
4181 u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate)
4182 {
4183         u16 table_ptr;
4184         u8 phy_rate, index;
4185
4186         /* get the phy specific rate encoding for the PLCP SIGNAL field */
4187         /* XXX4321 fixup needed ? */
4188         if (IS_OFDM(rate))
4189                 table_ptr = M_RT_DIRMAP_A;
4190         else
4191                 table_ptr = M_RT_DIRMAP_B;
4192
4193         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4194          * the index into the rate table.
4195          */
4196         phy_rate = rate_info[rate] & RATE_MASK;
4197         index = phy_rate & 0xf;
4198
4199         /* Find the SHM pointer to the rate table entry by looking in the
4200          * Direct-map Table
4201          */
4202         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
4203 }
4204
4205 void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val)
4206 {
4207         wlc_phy_txpwr_percent_set(wlc_hw->band->pi, val);
4208 }
4209
4210 void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, u32 antsel_avail)
4211 {
4212         wlc_hw->antsel_avail = antsel_avail;
4213 }