drivers/staging/brcm80211/sys/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef WLC_LOW
  18 #error "This file needs WLC_LOW"
  19 #endif
  20
  21 #include <wlc_cfg.h>
  22 #include <typedefs.h>
  23 #include <linuxver.h>
  24 #include <bcmdefs.h>
  25 #include <osl.h>
  26 #include <linux/kernel.h>
  27 #include <proto/802.11.h>
  28 #include <bcmwifi.h>
  29 #include <bcmutils.h>
  30 #include <siutils.h>
  31 #include <bcmendian.h>
  32 #include <wlioctl.h>
  33 #include <sbconfig.h>
  34 #include <sbchipc.h>
  35 #include <pcicfg.h>
  36 #include <sbhndpio.h>
  37 #include <sbhnddma.h>
  38 #include <hnddma.h>
  39 #include <hndpmu.h>
  40 #include <d11.h>
  41 #include <wlc_rate.h>
  42 #include <wlc_pub.h>
  43 #include <wlc_channel.h>
  44 #include <bcmsrom.h>
  45 #include <wlc_key.h>
  46 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
  47  * dependencies. Need to include these to files to allow a clean include of wlc.h
  48  * with WLC_HIGH defined.
  49  * At some point we may be able to skip the include of wlc.h and instead just
  50  * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
  51  */
  52 #include <wlc_mac80211.h>
  53 #include <wlc_bmac.h>
  54 #include <wlc_phy_shim.h>
  55 #include <wlc_phy_hal.h>
  56 #include <wl_export.h>
  57 #include "wl_ucode.h"
  58 #include "d11ucode_ext.h"
  59 #ifdef BCMSDIO
  60 #include <bcmsdh.h>
  61 #endif
  62 #include <bcmotp.h>
  63
  64 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
  65  * functions defined in the headers below. We should be eliminating those calls and
  66  * will be able to delete these include lines.
  67  */
  68 #include <wlc_antsel.h>
  69
  70 #include <pcie_core.h>
  71
  72 #include <wlc_alloc.h>
  73
  74 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  75
  76 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  77 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  78 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  79 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  80
  81 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  82
  83 #ifndef BMAC_DUP_TO_REMOVE
  84 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  85
  86 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  87
  88 #endif                          /* BMAC_DUP_TO_REMOVE */
  89
  90 #define DMAREG(wlc_hw, direction, fifonum)      (D11REV_LT(wlc_hw->corerev, 11) ? \
  91         ((direction == DMA_TX) ? \
  92                 (void *)(uintptr)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
  93                 (void *)(uintptr)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
  94         ((direction == DMA_TX) ? \
  95                 (void *)(uintptr)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
  96                 (void *)(uintptr)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
  97
  98 /*
  99  * The following table lists the buffer memory allocated to xmt fifos in HW.
 100  * the size is in units of 256bytes(one block), total size is HW dependent
 101  * ucode has default fifo partition, sw can overwrite if necessary
 102  *
 103  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 104  * the twiki is updated before making changes.
 105  */
 106
 107 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
 108
 109 static u16 xmtfifo_sz[][NFIFO] = {
 110         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 111         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 112         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 113         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 114         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 115 };
 116
 117 static void wlc_clkctl_clk(wlc_hw_info_t *wlc, uint mode);
 118 static void wlc_coreinit(wlc_info_t *wlc);
 119
 120 /* used by wlc_wakeucode_init() */
 121 static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits);
 122 static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
 123                             const uint nbytes);
 124 static void wlc_ucode_download(wlc_hw_info_t *wlc);
 125 static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw);
 126
 127 /* used by wlc_dpc() */
 128 static bool wlc_bmac_dotxstatus(wlc_hw_info_t *wlc, tx_status_t *txs,
 129                                 u32 s2);
 130 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc);
 131 static bool wlc_bmac_txstatus(wlc_hw_info_t *wlc, bool bound, bool *fatal);
 132 static bool wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound);
 133
 134 /* used by wlc_down() */
 135 static void wlc_flushqueues(wlc_info_t *wlc);
 136
 137 static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs);
 138 static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw);
 139 static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw);
 140
 141 /* Low Level Prototypes */
 142 static u16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset,
 143                                    u32 sel);
 144 static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v,
 145                                   u32 sel);
 146 static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme);
 147 static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw);
 148 static void wlc_ucode_bsinit(wlc_hw_info_t *wlc_hw);
 149 static bool wlc_validboardtype(wlc_hw_info_t *wlc);
 150 static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw);
 151 static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw);
 152 static void wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init);
 153 static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw);
 154 static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw);
 155 static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw);
 156 static u32 wlc_wlintrsoff(wlc_info_t *wlc);
 157 static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask);
 158 static void wlc_gpio_init(wlc_info_t *wlc);
 159 static void wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn,
 160                                       int len);
 161 static void wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn,
 162                                       int len);
 163 static void wlc_bmac_bsinit(wlc_info_t *wlc, chanspec_t chanspec);
 164 static u32 wlc_setband_inact(wlc_info_t *wlc, uint bandunit);
 165 static void wlc_bmac_setband(wlc_hw_info_t *wlc_hw, uint bandunit,
 166                              chanspec_t chanspec);
 167 static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot);
 168 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw);
 169 static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw,
 170                                              u8 rate);
 171
 172 /* === Low Level functions === */
 173
 174 void wlc_bmac_set_shortslot(wlc_hw_info_t *wlc_hw, bool shortslot)
 175 {
 176         wlc_hw->shortslot = shortslot;
 177
 178         if (BAND_2G(wlc_hw->band->bandtype) && wlc_hw->up) {
 179                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 180                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 181                 wlc_enable_mac(wlc_hw->wlc);
 182         }
 183 }
 184
 185 /*
 186  * Update the slot timing for standard 11b/g (20us slots)
 187  * or shortslot 11g (9us slots)
 188  * The PSM needs to be suspended for this call.
 189  */
 190 static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot)
 191 {
 192         osl_t *osh;
 193         d11regs_t *regs;
 194
 195         osh = wlc_hw->osh;
 196         regs = wlc_hw->regs;
 197
 198         if (shortslot) {
 199                 /* 11g short slot: 11a timing */
 200                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 201                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 202         } else {
 203                 /* 11g long slot: 11b timing */
 204                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 205                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 206         }
 207 }
 208
 209 static void WLBANDINITFN(wlc_ucode_bsinit) (wlc_hw_info_t *wlc_hw)
 210 {
 211         /* init microcode host flags */
 212         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 213
 214         /* do band-specific ucode IHR, SHM, and SCR inits */
 215         if (D11REV_IS(wlc_hw->corerev, 23)) {
 216                 if (WLCISNPHY(wlc_hw->band)) {
 217                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 218                 } else {
 219                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
 220                                   __func__, wlc_hw->unit, wlc_hw->corerev));
 221                 }
 222         } else {
 223                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 224                         if (WLCISLCNPHY(wlc_hw->band)) {
 225                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 226                         } else
 227                                 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n", __func__, wlc_hw->unit, wlc_hw->corerev));
 228                 } else {
 229                         WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
 230                                   __func__, wlc_hw->unit, wlc_hw->corerev));
 231                 }
 232         }
 233 }
 234
 235 /* switch to new band but leave it inactive */
 236 static u32 WLBANDINITFN(wlc_setband_inact) (wlc_info_t *wlc, uint bandunit)
 237 {
 238         wlc_hw_info_t *wlc_hw = wlc->hw;
 239         u32 macintmask;
 240         u32 tmp;
 241
 242         WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw->unit));
 243
 244         ASSERT(bandunit != wlc_hw->band->bandunit);
 245         ASSERT(si_iscoreup(wlc_hw->sih));
 246         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 247                0);
 248
 249         /* disable interrupts */
 250         macintmask = wl_intrsoff(wlc->wl);
 251
 252         /* radio off */
 253         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 254
 255         ASSERT(wlc_hw->clk);
 256
 257         if (D11REV_LT(wlc_hw->corerev, 17))
 258                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
 259
 260         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 261
 262         wlc_setxband(wlc_hw, bandunit);
 263
 264         return macintmask;
 265 }
 266
 267 /* Process received frames */
 268 /*
 269  * Return true if more frames need to be processed. false otherwise.
 270  * Param 'bound' indicates max. # frames to process before break out.
 271  */
 272 static bool BCMFASTPATH
 273 wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound)
 274 {
 275         void *p;
 276         void *head = NULL;
 277         void *tail = NULL;
 278         uint n = 0;
 279         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 280         u32 tsf_h, tsf_l;
 281         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 282
 283         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
 284         /* gather received frames */
 285         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 286
 287                 if (!tail)
 288                         head = tail = p;
 289                 else {
 290                         PKTSETLINK(tail, p);
 291                         tail = p;
 292                 }
 293
 294                 /* !give others some time to run! */
 295                 if (++n >= bound_limit)
 296                         break;
 297         }
 298
 299         /* get the TSF REG reading */
 300         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 301
 302         /* post more rbufs */
 303         dma_rxfill(wlc_hw->di[fifo]);
 304
 305         /* process each frame */
 306         while ((p = head) != NULL) {
 307                 head = PKTLINK(head);
 308                 PKTSETLINK(p, NULL);
 309
 310                 /* record the tsf_l in wlc_rxd11hdr */
 311                 wlc_rxhdr = (wlc_d11rxhdr_t *) PKTDATA(p);
 312                 wlc_rxhdr->tsf_l = htol32(tsf_l);
 313
 314                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 315                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 316
 317                 wlc_recv(wlc_hw->wlc, p);
 318         }
 319
 320         return n >= bound_limit;
 321 }
 322
 323 /* second-level interrupt processing
 324  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 325  *   Param 'bounded' indicates if applicable loops should be bounded.
 326  */
 327 bool BCMFASTPATH wlc_dpc(wlc_info_t *wlc, bool bounded)
 328 {
 329         u32 macintstatus;
 330         wlc_hw_info_t *wlc_hw = wlc->hw;
 331         d11regs_t *regs = wlc_hw->regs;
 332         bool fatal = false;
 333
 334         if (DEVICEREMOVED(wlc)) {
 335                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
 336                 wl_down(wlc->wl);
 337                 return false;
 338         }
 339
 340         /* grab and clear the saved software intstatus bits */
 341         macintstatus = wlc->macintstatus;
 342         wlc->macintstatus = 0;
 343
 344         WL_TRACE(("wl%d: wlc_dpc: macintstatus 0x%x\n", wlc_hw->unit,
 345                   macintstatus));
 346
 347         if (macintstatus & MI_PRQ) {
 348                 /* Process probe request FIFO */
 349                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 350         }
 351
 352         /* BCN template is available */
 353         /* ZZZ: Use AP_ACTIVE ? */
 354         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 355             && (macintstatus & MI_BCNTPL)) {
 356                 wlc_update_beacon(wlc);
 357         }
 358
 359         /* PMQ entry addition */
 360         if (macintstatus & MI_PMQ) {
 361         }
 362
 363         /* tx status */
 364         if (macintstatus & MI_TFS) {
 365                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 366                         wlc->macintstatus |= MI_TFS;
 367                 if (fatal) {
 368                         WL_ERROR(("MI_TFS: fatal\n"));
 369                         goto fatal;
 370                 }
 371         }
 372
 373         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 374                 wlc_tbtt(wlc, regs);
 375
 376         /* ATIM window end */
 377         if (macintstatus & MI_ATIMWINEND) {
 378                 WL_TRACE(("wlc_isr: end of ATIM window\n"));
 379
 380                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 381                 wlc->qvalid = 0;
 382         }
 383
 384         /* phy tx error */
 385         if (macintstatus & MI_PHYTXERR) {
 386                 WLCNTINCR(wlc->pub->_cnt->txphyerr);
 387         }
 388
 389         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 390         if (macintstatus & MI_DMAINT) {
 391                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 392                         wlc->macintstatus |= MI_DMAINT;
 393                 }
 394         }
 395
 396         /* TX FIFO suspend/flush completion */
 397         if (macintstatus & MI_TXSTOP) {
 398                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 399                         /*      WL_ERROR(("dpc: fifo_suspend_comlete\n")); */
 400                 }
 401         }
 402
 403         /* noise sample collected */
 404         if (macintstatus & MI_BG_NOISE) {
 405                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 406         }
 407
 408         if (macintstatus & MI_GP0) {
 409                 WL_ERROR(("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now));
 410
 411                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 412                             __func__, CHIPID(wlc_hw->sih->chip),
 413                             CHIPREV(wlc_hw->sih->chiprev));
 414
 415                 WLCNTINCR(wlc->pub->_cnt->psmwds);
 416
 417                 /* big hammer */
 418                 wl_init(wlc->wl);
 419         }
 420
 421         /* gptimer timeout */
 422         if (macintstatus & MI_TO) {
 423                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 424         }
 425
 426         if (macintstatus & MI_RFDISABLE) {
 427 #if defined(BCMDBG)
 428                 u32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD;
 429 #endif
 430
 431                 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw->unit, rfd));
 432
 433                 WLCNTINCR(wlc->pub->_cnt->rfdisable);
 434         }
 435
 436         /* send any enq'd tx packets. Just makes sure to jump start tx */
 437         if (!pktq_empty(&wlc->active_queue->q))
 438                 wlc_send_q(wlc, wlc->active_queue);
 439
 440         ASSERT(wlc_ps_check(wlc));
 441
 442         /* make sure the bound indication and the implementation are in sync */
 443         ASSERT(bounded == true || wlc->macintstatus == 0);
 444
 445         /* it isn't done and needs to be resched if macintstatus is non-zero */
 446         return wlc->macintstatus != 0;
 447
 448  fatal:
 449         wl_init(wlc->wl);
 450         return wlc->macintstatus != 0;
 451 }
 452
 453 /* common low-level watchdog code */
 454 void wlc_bmac_watchdog(void *arg)
 455 {
 456         wlc_info_t *wlc = (wlc_info_t *) arg;
 457         wlc_hw_info_t *wlc_hw = wlc->hw;
 458
 459         WL_TRACE(("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit));
 460
 461         if (!wlc_hw->up)
 462                 return;
 463
 464         /* increment second count */
 465         wlc_hw->now++;
 466
 467         /* Check for FIFO error interrupts */
 468         wlc_bmac_fifoerrors(wlc_hw);
 469
 470         /* make sure RX dma has buffers */
 471         dma_rxfill(wlc->hw->di[RX_FIFO]);
 472         if (D11REV_IS(wlc_hw->corerev, 4)) {
 473                 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
 474         }
 475
 476         wlc_phy_watchdog(wlc_hw->band->pi);
 477 }
 478
 479 void
 480 wlc_bmac_set_chanspec(wlc_hw_info_t *wlc_hw, chanspec_t chanspec, bool mute,
 481                       struct txpwr_limits *txpwr)
 482 {
 483         uint bandunit;
 484
 485         WL_TRACE(("wl%d: wlc_bmac_set_chanspec 0x%x\n", wlc_hw->unit,
 486                   chanspec));
 487
 488         wlc_hw->chanspec = chanspec;
 489
 490         /* Switch bands if necessary */
 491         if (NBANDS_HW(wlc_hw) > 1) {
 492                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 493                 if (wlc_hw->band->bandunit != bandunit) {
 494                         /* wlc_bmac_setband disables other bandunit,
 495                          *  use light band switch if not up yet
 496                          */
 497                         if (wlc_hw->up) {
 498                                 wlc_phy_chanspec_radio_set(wlc_hw->
 499                                                            bandstate[bandunit]->
 500                                                            pi, chanspec);
 501                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 502                         } else {
 503                                 wlc_setxband(wlc_hw, bandunit);
 504                         }
 505                 }
 506         }
 507
 508         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 509
 510         if (!wlc_hw->up) {
 511                 if (wlc_hw->clk)
 512                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 513                                                   chanspec);
 514                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 515         } else {
 516                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 517                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 518
 519                 /* Update muting of the channel */
 520                 wlc_bmac_mute(wlc_hw, mute, 0);
 521         }
 522 }
 523
 524 int wlc_bmac_revinfo_get(wlc_hw_info_t *wlc_hw, wlc_bmac_revinfo_t *revinfo)
 525 {
 526         si_t *sih = wlc_hw->sih;
 527         uint idx;
 528
 529         revinfo->vendorid = wlc_hw->vendorid;
 530         revinfo->deviceid = wlc_hw->deviceid;
 531
 532         revinfo->boardrev = wlc_hw->boardrev;
 533         revinfo->corerev = wlc_hw->corerev;
 534         revinfo->sromrev = wlc_hw->sromrev;
 535         revinfo->chiprev = sih->chiprev;
 536         revinfo->chip = sih->chip;
 537         revinfo->chippkg = sih->chippkg;
 538         revinfo->boardtype = sih->boardtype;
 539         revinfo->boardvendor = sih->boardvendor;
 540         revinfo->bustype = sih->bustype;
 541         revinfo->buscoretype = sih->buscoretype;
 542         revinfo->buscorerev = sih->buscorerev;
 543         revinfo->issim = sih->issim;
 544
 545         revinfo->nbands = NBANDS_HW(wlc_hw);
 546
 547         for (idx = 0; idx < NBANDS_HW(wlc_hw); idx++) {
 548                 wlc_hwband_t *band = wlc_hw->bandstate[idx];
 549                 revinfo->band[idx].bandunit = band->bandunit;
 550                 revinfo->band[idx].bandtype = band->bandtype;
 551                 revinfo->band[idx].phytype = band->phytype;
 552                 revinfo->band[idx].phyrev = band->phyrev;
 553                 revinfo->band[idx].radioid = band->radioid;
 554                 revinfo->band[idx].radiorev = band->radiorev;
 555                 revinfo->band[idx].abgphy_encore = band->abgphy_encore;
 556                 revinfo->band[idx].anarev = 0;
 557
 558         }
 559         return 0;
 560 }
 561
 562 int wlc_bmac_state_get(wlc_hw_info_t *wlc_hw, wlc_bmac_state_t *state)
 563 {
 564         state->machwcap = wlc_hw->machwcap;
 565
 566         return 0;
 567 }
 568
 569 static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme)
 570 {
 571         uint i;
 572         char name[8];
 573         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 574         u16 pio_mhf2 = 0;
 575         wlc_hw_info_t *wlc_hw = wlc->hw;
 576         uint unit = wlc_hw->unit;
 577         wlc_tunables_t *tune = wlc->pub->tunables;
 578
 579         /* name and offsets for dma_attach */
 580         snprintf(name, sizeof(name), "wl%d", unit);
 581
 582         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 583                 uint addrwidth;
 584                 int dma_attach_err = 0;
 585                 osl_t *osh = wlc_hw->osh;
 586
 587                 /* Find out the DMA addressing capability and let OS know
 588                  * All the channels within one DMA core have 'common-minimum' same
 589                  * capability
 590                  */
 591                 addrwidth =
 592                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 593                 OSL_DMADDRWIDTH(osh, addrwidth);
 594
 595                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 596                         WL_ERROR(("wl%d: wlc_attach: alloc_dma_resources failed\n", unit));
 597                         return false;
 598                 }
 599
 600                 /*
 601                  * FIFO 0
 602                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 603                  * RX: RX_FIFO (RX data packets)
 604                  */
 605                 ASSERT(TX_AC_BK_FIFO == 0);
 606                 ASSERT(RX_FIFO == 0);
 607                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 608                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 609                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 610                                            (wme ? tune->ntxd : 0), tune->nrxd,
 611                                            tune->rxbufsz, -1, tune->nrxbufpost,
 612                                            WL_HWRXOFF, &wl_msg_level);
 613                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 614
 615                 /*
 616                  * FIFO 1
 617                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 618                  *   (legacy) TX_DATA_FIFO (TX data packets)
 619                  * RX: UNUSED
 620                  */
 621                 ASSERT(TX_AC_BE_FIFO == 1);
 622                 ASSERT(TX_DATA_FIFO == 1);
 623                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 624                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 625                                            tune->ntxd, 0, 0, -1, 0, 0,
 626                                            &wl_msg_level);
 627                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 628
 629                 /*
 630                  * FIFO 2
 631                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 632                  * RX: UNUSED
 633                  */
 634                 ASSERT(TX_AC_VI_FIFO == 2);
 635                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 636                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 637                                            tune->ntxd, 0, 0, -1, 0, 0,
 638                                            &wl_msg_level);
 639                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 640                 /*
 641                  * FIFO 3
 642                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 643                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 644                  * RX: RX_TXSTATUS_FIFO (transmit-status packets)
 645                  *      for corerev < 5 only
 646                  */
 647                 ASSERT(TX_AC_VO_FIFO == 3);
 648                 ASSERT(TX_CTL_FIFO == 3);
 649                 if (D11REV_IS(wlc_hw->corerev, 4)) {
 650                         ASSERT(RX_TXSTATUS_FIFO == 3);
 651                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 652                                                    DMAREG(wlc_hw, DMA_TX, 3),
 653                                                    DMAREG(wlc_hw, DMA_RX, 3),
 654                                                    tune->ntxd, tune->nrxd,
 655                                                    sizeof(tx_status_t), -1,
 656                                                    tune->nrxbufpost, 0,
 657                                                    &wl_msg_level);
 658                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 659                 } else {
 660                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 661                                                    DMAREG(wlc_hw, DMA_TX, 3),
 662                                                    NULL, tune->ntxd, 0, 0, -1,
 663                                                    0, 0, &wl_msg_level);
 664                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 665                 }
 666 /* Cleaner to leave this as if with AP defined */
 667
 668                 if (dma_attach_err) {
 669                         WL_ERROR(("wl%d: wlc_attach: dma_attach failed\n",
 670                                   unit));
 671                         return false;
 672                 }
 673
 674                 /* get pointer to dma engine tx flow control variable */
 675                 for (i = 0; i < NFIFO; i++)
 676                         if (wlc_hw->di[i])
 677                                 wlc_hw->txavail[i] =
 678                                     (uint *) dma_getvar(wlc_hw->di[i],
 679                                                         "&txavail");
 680         }
 681
 682         /* initial ucode host flags */
 683         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 684
 685         return true;
 686 }
 687
 688 static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw)
 689 {
 690         uint j;
 691
 692         for (j = 0; j < NFIFO; j++) {
 693                 if (wlc_hw->di[j]) {
 694                         dma_detach(wlc_hw->di[j]);
 695                         wlc_hw->di[j] = NULL;
 696                 }
 697         }
 698 }
 699
 700 /* low level attach
 701  *    run backplane attach, init nvram
 702  *    run phy attach
 703  *    initialize software state for each core and band
 704  *    put the whole chip in reset(driver down state), no clock
 705  */
 706 int wlc_bmac_attach(wlc_info_t *wlc, u16 vendor, u16 device, uint unit,
 707                     bool piomode, osl_t *osh, void *regsva, uint bustype,
 708                     void *btparam)
 709 {
 710         wlc_hw_info_t *wlc_hw;
 711         d11regs_t *regs;
 712         char *macaddr = NULL;
 713         char *vars;
 714         uint err = 0;
 715         uint j;
 716         bool wme = false;
 717         shared_phy_params_t sha_params;
 718
 719         WL_TRACE(("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n", unit,
 720                   vendor, device));
 721
 722         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 723
 724         wme = true;
 725
 726         wlc_hw = wlc->hw;
 727         wlc_hw->wlc = wlc;
 728         wlc_hw->unit = unit;
 729         wlc_hw->osh = osh;
 730         wlc_hw->band = wlc_hw->bandstate[0];
 731         wlc_hw->_piomode = piomode;
 732
 733         /* populate wlc_hw_info_t with default values  */
 734         wlc_bmac_info_init(wlc_hw);
 735
 736         /*
 737          * Do the hardware portion of the attach.
 738          * Also initialize software state that depends on the particular hardware
 739          * we are running.
 740          */
 741         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 742                                 &wlc_hw->vars, &wlc_hw->vars_size);
 743         if (wlc_hw->sih == NULL) {
 744                 WL_ERROR(("wl%d: wlc_bmac_attach: si_attach failed\n", unit));
 745                 err = 11;
 746                 goto fail;
 747         }
 748         vars = wlc_hw->vars;
 749
 750         /*
 751          * Get vendid/devid nvram overwrites, which could be different
 752          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 753          * SDIO_BUS, and SROMless devices on PCI_BUS.
 754          */
 755 #ifdef BCMBUSTYPE
 756         bustype = BCMBUSTYPE;
 757 #endif
 758         if (bustype != SI_BUS) {
 759                 char *var;
 760
 761                 var = getvar(vars, "vendid");
 762                 if (var) {
 763                         vendor = (u16) simple_strtoul(var, NULL, 0);
 764                         WL_ERROR(("Overriding vendor id = 0x%x\n", vendor));
 765                 }
 766                 var = getvar(vars, "devid");
 767                 if (var) {
 768                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 769                         if (devid != 0xffff) {
 770                                 device = devid;
 771                                 WL_ERROR(("Overriding device id = 0x%x\n",
 772                                           device));
 773                         }
 774                 }
 775
 776                 /* verify again the device is supported */
 777                 if (!wlc_chipmatch(vendor, device)) {
 778                         WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n", unit, vendor, device));
 779                         err = 12;
 780                         goto fail;
 781                 }
 782         }
 783
 784         wlc_hw->vendorid = vendor;
 785         wlc_hw->deviceid = device;
 786
 787         /* set bar0 window to point at D11 core */
 788         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 789         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 790
 791         regs = wlc_hw->regs;
 792
 793         wlc->regs = wlc_hw->regs;
 794
 795         /* validate chip, chiprev and corerev */
 796         if (!wlc_isgoodchip(wlc_hw)) {
 797                 err = 13;
 798                 goto fail;
 799         }
 800
 801         /* initialize power control registers */
 802         si_clkctl_init(wlc_hw->sih);
 803
 804         /* request fastclock and force fastclock for the rest of attach
 805          * bring the d11 core out of reset.
 806          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 807          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 808          */
 809         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 810         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 811
 812         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 813                 WL_ERROR(("wl%d: wlc_bmac_attach: validate_chip_access failed\n", unit));
 814                 err = 14;
 815                 goto fail;
 816         }
 817
 818         /* get the board rev, used just below */
 819         j = getintvar(vars, "boardrev");
 820         /* promote srom boardrev of 0xFF to 1 */
 821         if (j == BOARDREV_PROMOTABLE)
 822                 j = BOARDREV_PROMOTED;
 823         wlc_hw->boardrev = (u16) j;
 824         if (!wlc_validboardtype(wlc_hw)) {
 825                 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit, wlc_hw->sih->boardtype, wlc_hw->boardrev));
 826                 err = 15;
 827                 goto fail;
 828         }
 829         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 830         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 831         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 832
 833         if (D11REV_LE(wlc_hw->corerev, 4)
 834             || (wlc_hw->boardflags & BFL_NOPLLDOWN))
 835                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 836
 837         if ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
 838             && (si_pci_war16165(wlc_hw->sih)))
 839                 wlc->war16165 = true;
 840
 841         /* check device id(srom, nvram etc.) to set bands */
 842         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 843                 /* Dualband boards */
 844                 wlc_hw->_nbands = 2;
 845         } else
 846                 wlc_hw->_nbands = 1;
 847
 848         if ((CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID))
 849                 wlc_hw->_nbands = 1;
 850
 851         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 852          * init of these values
 853          */
 854         wlc->vendorid = wlc_hw->vendorid;
 855         wlc->deviceid = wlc_hw->deviceid;
 856         wlc->pub->sih = wlc_hw->sih;
 857         wlc->pub->corerev = wlc_hw->corerev;
 858         wlc->pub->sromrev = wlc_hw->sromrev;
 859         wlc->pub->boardrev = wlc_hw->boardrev;
 860         wlc->pub->boardflags = wlc_hw->boardflags;
 861         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 862         wlc->pub->_nbands = wlc_hw->_nbands;
 863
 864         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 865
 866         if (wlc_hw->physhim == NULL) {
 867                 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 868                           unit));
 869                 err = 25;
 870                 goto fail;
 871         }
 872
 873         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 874         sha_params.osh = osh;
 875         sha_params.sih = wlc_hw->sih;
 876         sha_params.physhim = wlc_hw->physhim;
 877         sha_params.unit = unit;
 878         sha_params.corerev = wlc_hw->corerev;
 879         sha_params.vars = vars;
 880         sha_params.vid = wlc_hw->vendorid;
 881         sha_params.did = wlc_hw->deviceid;
 882         sha_params.chip = wlc_hw->sih->chip;
 883         sha_params.chiprev = wlc_hw->sih->chiprev;
 884         sha_params.chippkg = wlc_hw->sih->chippkg;
 885         sha_params.sromrev = wlc_hw->sromrev;
 886         sha_params.boardtype = wlc_hw->sih->boardtype;
 887         sha_params.boardrev = wlc_hw->boardrev;
 888         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 889         sha_params.boardflags = wlc_hw->boardflags;
 890         sha_params.boardflags2 = wlc_hw->boardflags2;
 891         sha_params.bustype = wlc_hw->sih->bustype;
 892         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 893
 894         /* alloc and save pointer to shared phy state area */
 895         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 896         if (!wlc_hw->phy_sh) {
 897                 err = 16;
 898                 goto fail;
 899         }
 900
 901         /* initialize software state for each core and band */
 902         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 903                 /*
 904                  * band0 is always 2.4Ghz
 905                  * band1, if present, is 5Ghz
 906                  */
 907
 908                 /* So if this is a single band 11a card, use band 1 */
 909                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 910                         j = BAND_5G_INDEX;
 911
 912                 wlc_setxband(wlc_hw, j);
 913
 914                 wlc_hw->band->bandunit = j;
 915                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 916                 wlc->band->bandunit = j;
 917                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 918                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 919
 920                 if (D11REV_GE(wlc_hw->corerev, 13)) {
 921                         wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 922                         wlc_hw->machwcap_backup = wlc_hw->machwcap;
 923                 }
 924
 925                 /* init tx fifo size */
 926                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 927                        ARRAY_SIZE(xmtfifo_sz));
 928                 wlc_hw->xmtfifo_sz =
 929                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 930
 931                 /* Get a phy for this band */
 932                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 933                         (void *)(uintptr) regs, wlc_hw->band->bandtype, vars);
 934                 if (wlc_hw->band->pi == NULL) {
 935                         WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n", unit));
 936                         err = 17;
 937                         goto fail;
 938                 }
 939
 940                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 941
 942                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 943                                        &wlc_hw->band->phyrev,
 944                                        &wlc_hw->band->radioid,
 945                                        &wlc_hw->band->radiorev);
 946                 wlc_hw->band->abgphy_encore =
 947                     wlc_phy_get_encore(wlc_hw->band->pi);
 948                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 949                 wlc_hw->band->core_flags =
 950                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 951
 952                 /* verify good phy_type & supported phy revision */
 953                 if (WLCISNPHY(wlc_hw->band)) {
 954                         if (NCONF_HAS(wlc_hw->band->phyrev))
 955                                 goto good_phy;
 956                         else
 957                                 goto bad_phy;
 958                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 959                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 960                                 goto good_phy;
 961                         else
 962                                 goto bad_phy;
 963                 } else {
 964  bad_phy:
 965                         WL_ERROR(("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n", unit, wlc_hw->band->phytype, wlc_hw->band->phyrev));
 966                         err = 18;
 967                         goto fail;
 968                 }
 969
 970  good_phy:
 971                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 972                  * high level attach. However we can not make that change until all low level access
 973                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 974                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 975                  * low only init when all fns updated.
 976                  */
 977                 wlc->band->pi = wlc_hw->band->pi;
 978                 wlc->band->phytype = wlc_hw->band->phytype;
 979                 wlc->band->phyrev = wlc_hw->band->phyrev;
 980                 wlc->band->radioid = wlc_hw->band->radioid;
 981                 wlc->band->radiorev = wlc_hw->band->radiorev;
 982
 983                 /* default contention windows size limits */
 984                 wlc_hw->band->CWmin = APHY_CWMIN;
 985                 wlc_hw->band->CWmax = PHY_CWMAX;
 986
 987                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 988                         err = 19;
 989                         goto fail;
 990                 }
 991         }
 992
 993         /* disable core to match driver "down" state */
 994         wlc_coredisable(wlc_hw);
 995
 996         /* Match driver "down" state */
 997         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
 998                 si_pci_down(wlc_hw->sih);
 999
1000         /* register sb interrupt callback functions */
1001         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
1002                                   (void *)wlc_wlintrsrestore, NULL, wlc);
1003
1004         /* turn off pll and xtal to match driver "down" state */
1005         wlc_bmac_xtal(wlc_hw, OFF);
1006
1007         /* *********************************************************************
1008          * The hardware is in the DOWN state at this point. D11 core
1009          * or cores are in reset with clocks off, and the board PLLs
1010          * are off if possible.
1011          *
1012          * Beyond this point, wlc->sbclk == false and chip registers
1013          * should not be touched.
1014          *********************************************************************
1015          */
1016
1017         /* init etheraddr state variables */
1018         macaddr = wlc_get_macaddr(wlc_hw);
1019         if (macaddr == NULL) {
1020                 WL_ERROR(("wl%d: wlc_bmac_attach: macaddr not found\n", unit));
1021                 err = 21;
1022                 goto fail;
1023         }
1024         bcm_ether_atoe(macaddr, &wlc_hw->etheraddr);
1025         if (ETHER_ISBCAST((char *)&wlc_hw->etheraddr) ||
1026             ETHER_ISNULLADDR((char *)&wlc_hw->etheraddr)) {
1027                 WL_ERROR(("wl%d: wlc_bmac_attach: bad macaddr %s\n", unit,
1028                           macaddr));
1029                 err = 22;
1030                 goto fail;
1031         }
1032
1033         WL_ERROR(("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1034                   __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1035                   wlc_hw->sih->boardtype, macaddr));
1036
1037         return err;
1038
1039  fail:
1040         WL_ERROR(("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err));
1041         return err;
1042 }
1043
1044 /*
1045  * Initialize wlc_info default values ...
1046  * may get overrides later in this function
1047  *  BMAC_NOTES, move low out and resolve the dangling ones
1048  */
1049 void wlc_bmac_info_init(wlc_hw_info_t *wlc_hw)
1050 {
1051         wlc_info_t *wlc = wlc_hw->wlc;
1052
1053         /* set default sw macintmask value */
1054         wlc->defmacintmask = DEF_MACINTMASK;
1055
1056         /* various 802.11g modes */
1057         wlc_hw->shortslot = false;
1058
1059         wlc_hw->SFBL = RETRY_SHORT_FB;
1060         wlc_hw->LFBL = RETRY_LONG_FB;
1061
1062         /* default mac retry limits */
1063         wlc_hw->SRL = RETRY_SHORT_DEF;
1064         wlc_hw->LRL = RETRY_LONG_DEF;
1065         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1066 }
1067
1068 /*
1069  * low level detach
1070  */
1071 int wlc_bmac_detach(wlc_info_t *wlc)
1072 {
1073         uint i;
1074         wlc_hwband_t *band;
1075         wlc_hw_info_t *wlc_hw = wlc->hw;
1076         int callbacks;
1077
1078         callbacks = 0;
1079
1080         if (wlc_hw->sih) {
1081                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1082                  * interrupt object may has been freed. this must be done before sb core switch
1083                  */
1084                 si_deregister_intr_callback(wlc_hw->sih);
1085
1086                 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1087                         si_pci_sleep(wlc_hw->sih);
1088         }
1089
1090         wlc_bmac_detach_dmapio(wlc_hw);
1091
1092         band = wlc_hw->band;
1093         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1094                 if (band->pi) {
1095                         /* Detach this band's phy */
1096                         wlc_phy_detach(band->pi);
1097                         band->pi = NULL;
1098                 }
1099                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1100         }
1101
1102         /* Free shared phy state */
1103         wlc_phy_shared_detach(wlc_hw->phy_sh);
1104
1105         wlc_phy_shim_detach(wlc_hw->physhim);
1106
1107         /* free vars */
1108         if (wlc_hw->vars) {
1109                 MFREE(wlc_hw->osh, wlc_hw->vars, wlc_hw->vars_size);
1110                 wlc_hw->vars = NULL;
1111         }
1112
1113         if (wlc_hw->sih) {
1114                 si_detach(wlc_hw->sih);
1115                 wlc_hw->sih = NULL;
1116         }
1117
1118         return callbacks;
1119
1120 }
1121
1122 void wlc_bmac_reset(wlc_hw_info_t *wlc_hw)
1123 {
1124         WL_TRACE(("wl%d: wlc_bmac_reset\n", wlc_hw->unit));
1125
1126         WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1127
1128         /* reset the core */
1129         if (!DEVICEREMOVED(wlc_hw->wlc))
1130                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1131
1132         /* purge the dma rings */
1133         wlc_flushqueues(wlc_hw->wlc);
1134
1135         wlc_reset_bmac_done(wlc_hw->wlc);
1136 }
1137
1138 void
1139 wlc_bmac_init(wlc_hw_info_t *wlc_hw, chanspec_t chanspec,
1140                           bool mute) {
1141         u32 macintmask;
1142         bool fastclk;
1143         wlc_info_t *wlc = wlc_hw->wlc;
1144
1145         WL_TRACE(("wl%d: wlc_bmac_init\n", wlc_hw->unit));
1146
1147         /* request FAST clock if not on */
1148         fastclk = wlc_hw->forcefastclk;
1149         if (!fastclk)
1150                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1151
1152         /* disable interrupts */
1153         macintmask = wl_intrsoff(wlc->wl);
1154
1155         /* set up the specified band and chanspec */
1156         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1157         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1158
1159         /* do one-time phy inits and calibration */
1160         wlc_phy_cal_init(wlc_hw->band->pi);
1161
1162         /* core-specific initialization */
1163         wlc_coreinit(wlc);
1164
1165         /* suspend the tx fifos and mute the phy for preism cac time */
1166         if (mute)
1167                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1168
1169         /* band-specific inits */
1170         wlc_bmac_bsinit(wlc, chanspec);
1171
1172         /* restore macintmask */
1173         wl_intrsrestore(wlc->wl, macintmask);
1174
1175         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1176          * and wlc_enable_mac() will clear this override bit.
1177          */
1178         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1179
1180         /*
1181          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1182          */
1183         wlc_hw->mac_suspend_depth = 1;
1184
1185         /* restore the clk */
1186         if (!fastclk)
1187                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1188 }
1189
1190 int wlc_bmac_up_prep(wlc_hw_info_t *wlc_hw)
1191 {
1192         uint coremask;
1193
1194         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1195
1196         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1197
1198         /*
1199          * Enable pll and xtal, initialize the power control registers,
1200          * and force fastclock for the remainder of wlc_up().
1201          */
1202         wlc_bmac_xtal(wlc_hw, ON);
1203         si_clkctl_init(wlc_hw->sih);
1204         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1205
1206         /*
1207          * Configure pci/pcmcia here instead of in wlc_attach()
1208          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1209          */
1210         coremask = (1 << wlc_hw->wlc->core->coreidx);
1211
1212         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1213                 si_pci_setup(wlc_hw->sih, coremask);
1214
1215         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1216
1217         /*
1218          * Need to read the hwradio status here to cover the case where the system
1219          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1220          */
1221         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1222                 /* put SB PCI in down state again */
1223                 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1224                         si_pci_down(wlc_hw->sih);
1225                 wlc_bmac_xtal(wlc_hw, OFF);
1226                 return BCME_RADIOOFF;
1227         }
1228
1229         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1230                 si_pci_up(wlc_hw->sih);
1231
1232         /* reset the d11 core */
1233         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1234
1235         return 0;
1236 }
1237
1238 int wlc_bmac_up_finish(wlc_hw_info_t *wlc_hw)
1239 {
1240         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1241
1242         wlc_hw->up = true;
1243         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1244
1245         /* FULLY enable dynamic power control and d11 core interrupt */
1246         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1247         ASSERT(wlc_hw->wlc->macintmask == 0);
1248         wl_intrson(wlc_hw->wlc->wl);
1249         return 0;
1250 }
1251
1252 int wlc_bmac_down_prep(wlc_hw_info_t *wlc_hw)
1253 {
1254         bool dev_gone;
1255         uint callbacks = 0;
1256
1257         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1258
1259         if (!wlc_hw->up)
1260                 return callbacks;
1261
1262         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1263
1264         /* disable interrupts */
1265         if (dev_gone)
1266                 wlc_hw->wlc->macintmask = 0;
1267         else {
1268                 /* now disable interrupts */
1269                 wl_intrsoff(wlc_hw->wlc->wl);
1270
1271                 /* ensure we're running on the pll clock again */
1272                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1273         }
1274         /* down phy at the last of this stage */
1275         callbacks += wlc_phy_down(wlc_hw->band->pi);
1276
1277         return callbacks;
1278 }
1279
1280 int wlc_bmac_down_finish(wlc_hw_info_t *wlc_hw)
1281 {
1282         uint callbacks = 0;
1283         bool dev_gone;
1284
1285         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1286
1287         if (!wlc_hw->up)
1288                 return callbacks;
1289
1290         wlc_hw->up = false;
1291         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1292
1293         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1294
1295         if (dev_gone) {
1296                 wlc_hw->sbclk = false;
1297                 wlc_hw->clk = false;
1298                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1299
1300                 /* reclaim any posted packets */
1301                 wlc_flushqueues(wlc_hw->wlc);
1302         } else {
1303
1304                 /* Reset and disable the core */
1305                 if (si_iscoreup(wlc_hw->sih)) {
1306                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1307                             MCTL_EN_MAC)
1308                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1309                         callbacks += wl_reset(wlc_hw->wlc->wl);
1310                         wlc_coredisable(wlc_hw);
1311                 }
1312
1313                 /* turn off primary xtal and pll */
1314                 if (!wlc_hw->noreset) {
1315                         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1316                                 si_pci_down(wlc_hw->sih);
1317                         wlc_bmac_xtal(wlc_hw, OFF);
1318                 }
1319         }
1320
1321         return callbacks;
1322 }
1323
1324 void wlc_bmac_wait_for_wake(wlc_hw_info_t *wlc_hw)
1325 {
1326         if (D11REV_IS(wlc_hw->corerev, 4))      /* no slowclock */
1327                 OSL_DELAY(5);
1328         else {
1329                 /* delay before first read of ucode state */
1330                 OSL_DELAY(40);
1331
1332                 /* wait until ucode is no longer asleep */
1333                 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1334                           DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1335         }
1336
1337         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1338 }
1339
1340 void wlc_bmac_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
1341 {
1342         bcopy(&wlc_hw->etheraddr, ea, ETHER_ADDR_LEN);
1343 }
1344
1345 void wlc_bmac_set_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
1346 {
1347         bcopy(ea, &wlc_hw->etheraddr, ETHER_ADDR_LEN);
1348 }
1349
1350 int wlc_bmac_bandtype(wlc_hw_info_t *wlc_hw)
1351 {
1352         return wlc_hw->band->bandtype;
1353 }
1354
1355 void *wlc_cur_phy(wlc_info_t *wlc)
1356 {
1357         wlc_hw_info_t *wlc_hw = wlc->hw;
1358         return (void *)wlc_hw->band->pi;
1359 }
1360
1361 /* control chip clock to save power, enable dynamic clock or force fast clock */
1362 static void wlc_clkctl_clk(wlc_hw_info_t *wlc_hw, uint mode)
1363 {
1364         if (PMUCTL_ENAB(wlc_hw->sih)) {
1365                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1366                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1367                  *      which means the FCA bit may not be set.
1368                  *      should wakeup mac if driver wants it to run on HT.
1369                  */
1370
1371                 if (wlc_hw->clk) {
1372                         if (mode == CLK_FAST) {
1373                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1374                                        CCS_FORCEHT);
1375
1376                                 OSL_DELAY(64);
1377
1378                                 SPINWAIT(((R_REG
1379                                            (wlc_hw->osh,
1380                                             &wlc_hw->regs->
1381                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1382                                          PMU_MAX_TRANSITION_DLY);
1383                                 ASSERT(R_REG
1384                                        (wlc_hw->osh,
1385                                         &wlc_hw->regs->
1386                                         clk_ctl_st) & CCS_HTAVAIL);
1387                         } else {
1388                                 if ((wlc_hw->sih->pmurev == 0) &&
1389                                     (R_REG
1390                                      (wlc_hw->osh,
1391                                       &wlc_hw->regs->
1392                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1393                                         SPINWAIT(((R_REG
1394                                                    (wlc_hw->osh,
1395                                                     &wlc_hw->regs->
1396                                                     clk_ctl_st) & CCS_HTAVAIL)
1397                                                   == 0),
1398                                                  PMU_MAX_TRANSITION_DLY);
1399                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1400                                         ~CCS_FORCEHT);
1401                         }
1402                 }
1403                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1404         } else {
1405                 bool wakeup_ucode;
1406
1407                 /* old chips w/o PMU, force HT through cc,
1408                  * then use FCA to verify mac is running fast clock
1409                  */
1410
1411                 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1412
1413                 if (wlc_hw->up && wakeup_ucode)
1414                         wlc_ucode_wake_override_set(wlc_hw,
1415                                                     WLC_WAKE_OVERRIDE_CLKCTL);
1416
1417                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1418
1419                 if (D11REV_LT(wlc_hw->corerev, 11)) {
1420                         /* ucode WAR for old chips */
1421                         if (wlc_hw->forcefastclk)
1422                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1423                                              MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1424                         else
1425                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1426                                              WLC_BAND_ALL);
1427                 }
1428
1429                 /* check fast clock is available (if core is not in reset) */
1430                 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1431                     && wlc_hw->clk)
1432                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1433
1434                 /* keep the ucode wake bit on if forcefastclk is on
1435                  * since we do not want ucode to put us back to slow clock
1436                  * when it dozes for PM mode.
1437                  * Code below matches the wake override bit with current forcefastclk state
1438                  * Only setting bit in wake_override instead of waking ucode immediately
1439                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1440                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1441                  * (protected by an up check) was executed just below.
1442                  */
1443                 if (wlc_hw->forcefastclk)
1444                         mboolset(wlc_hw->wake_override,
1445                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1446                 else
1447                         mboolclr(wlc_hw->wake_override,
1448                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1449
1450                 /* ok to clear the wakeup now */
1451                 if (wlc_hw->up && wakeup_ucode)
1452                         wlc_ucode_wake_override_clear(wlc_hw,
1453                                                       WLC_WAKE_OVERRIDE_CLKCTL);
1454         }
1455 }
1456
1457 /* set initial host flags value */
1458 static void
1459 wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init)
1460 {
1461         wlc_hw_info_t *wlc_hw = wlc->hw;
1462
1463         bzero(mhfs, sizeof(u16) * MHFMAX);
1464
1465         mhfs[MHF2] |= mhf2_init;
1466
1467         /* prohibit use of slowclock on multifunction boards */
1468         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1469                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1470
1471         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1472                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1473                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1474         }
1475 }
1476
1477 /* set or clear ucode host flag bits
1478  * it has an optimization for no-change write
1479  * it only writes through shared memory when the core has clock;
1480  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1481  *
1482  *
1483  * bands values are: WLC_BAND_AUTO <--- Current band only
1484  *                   WLC_BAND_5G   <--- 5G band only
1485  *                   WLC_BAND_2G   <--- 2G band only
1486  *                   WLC_BAND_ALL  <--- All bands
1487  */
1488 void
1489 wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask, u16 val,
1490              int bands)
1491 {
1492         u16 save;
1493         u16 addr[MHFMAX] = {
1494                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1495                 M_HOST_FLAGS5
1496         };
1497         wlc_hwband_t *band;
1498
1499         ASSERT((val & ~mask) == 0);
1500         ASSERT(idx < MHFMAX);
1501         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1502
1503         switch (bands) {
1504                 /* Current band only or all bands,
1505                  * then set the band to current band
1506                  */
1507         case WLC_BAND_AUTO:
1508         case WLC_BAND_ALL:
1509                 band = wlc_hw->band;
1510                 break;
1511         case WLC_BAND_5G:
1512                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1513                 break;
1514         case WLC_BAND_2G:
1515                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1516                 break;
1517         default:
1518                 ASSERT(0);
1519                 band = NULL;
1520         }
1521
1522         if (band) {
1523                 save = band->mhfs[idx];
1524                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1525
1526                 /* optimization: only write through if changed, and
1527                  * changed band is the current band
1528                  */
1529                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1530                     && (band == wlc_hw->band))
1531                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1532                                            (u16) band->mhfs[idx]);
1533         }
1534
1535         if (bands == WLC_BAND_ALL) {
1536                 wlc_hw->bandstate[0]->mhfs[idx] =
1537                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1538                 wlc_hw->bandstate[1]->mhfs[idx] =
1539                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1540         }
1541 }
1542
1543 u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands)
1544 {
1545         wlc_hwband_t *band;
1546         ASSERT(idx < MHFMAX);
1547
1548         switch (bands) {
1549         case WLC_BAND_AUTO:
1550                 band = wlc_hw->band;
1551                 break;
1552         case WLC_BAND_5G:
1553                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1554                 break;
1555         case WLC_BAND_2G:
1556                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1557                 break;
1558         default:
1559                 ASSERT(0);
1560                 band = NULL;
1561         }
1562
1563         if (!band)
1564                 return 0;
1565
1566         return band->mhfs[idx];
1567 }
1568
1569 static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs)
1570 {
1571         u8 idx;
1572         u16 addr[] = {
1573                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1574                 M_HOST_FLAGS5
1575         };
1576
1577         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1578
1579         for (idx = 0; idx < MHFMAX; idx++) {
1580                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1581         }
1582 }
1583
1584 /* set the maccontrol register to desired reset state and
1585  * initialize the sw cache of the register
1586  */
1587 static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw)
1588 {
1589         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1590         wlc_hw->maccontrol = 0;
1591         wlc_hw->suspended_fifos = 0;
1592         wlc_hw->wake_override = 0;
1593         wlc_hw->mute_override = 0;
1594         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1595 }
1596
1597 /* set or clear maccontrol bits */
1598 void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, u32 mask, u32 val)
1599 {
1600         u32 maccontrol;
1601         u32 new_maccontrol;
1602
1603         ASSERT((val & ~mask) == 0);
1604
1605         maccontrol = wlc_hw->maccontrol;
1606         new_maccontrol = (maccontrol & ~mask) | val;
1607
1608         /* if the new maccontrol value is the same as the old, nothing to do */
1609         if (new_maccontrol == maccontrol)
1610                 return;
1611
1612         /* something changed, cache the new value */
1613         wlc_hw->maccontrol = new_maccontrol;
1614
1615         /* write the new values with overrides applied */
1616         wlc_mctrl_write(wlc_hw);
1617 }
1618
1619 /* write the software state of maccontrol and overrides to the maccontrol register */
1620 static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw)
1621 {
1622         u32 maccontrol = wlc_hw->maccontrol;
1623
1624         /* OR in the wake bit if overridden */
1625         if (wlc_hw->wake_override)
1626                 maccontrol |= MCTL_WAKE;
1627
1628         /* set AP and INFRA bits for mute if needed */
1629         if (wlc_hw->mute_override) {
1630                 maccontrol &= ~(MCTL_AP);
1631                 maccontrol |= MCTL_INFRA;
1632         }
1633
1634         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1635 }
1636
1637 void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, u32 override_bit)
1638 {
1639         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1640
1641         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1642                 mboolset(wlc_hw->wake_override, override_bit);
1643                 return;
1644         }
1645
1646         mboolset(wlc_hw->wake_override, override_bit);
1647
1648         wlc_mctrl_write(wlc_hw);
1649         wlc_bmac_wait_for_wake(wlc_hw);
1650
1651         return;
1652 }
1653
1654 void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw, u32 override_bit)
1655 {
1656         ASSERT(wlc_hw->wake_override & override_bit);
1657
1658         mboolclr(wlc_hw->wake_override, override_bit);
1659
1660         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1661                 return;
1662
1663         wlc_mctrl_write(wlc_hw);
1664
1665         return;
1666 }
1667
1668 /* When driver needs ucode to stop beaconing, it has to make sure that
1669  * MCTL_AP is clear and MCTL_INFRA is set
1670  * Mode           MCTL_AP        MCTL_INFRA
1671  * AP                1              1
1672  * STA               0              1 <--- This will ensure no beacons
1673  * IBSS              0              0
1674  */
1675 static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw)
1676 {
1677         wlc_hw->mute_override = 1;
1678
1679         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1680          * override, then there is no change to write
1681          */
1682         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1683                 return;
1684
1685         wlc_mctrl_write(wlc_hw);
1686
1687         return;
1688 }
1689
1690 /* Clear the override on AP and INFRA bits */
1691 static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw)
1692 {
1693         if (wlc_hw->mute_override == 0)
1694                 return;
1695
1696         wlc_hw->mute_override = 0;
1697
1698         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1699          * override, then there is no change to write
1700          */
1701         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1702                 return;
1703
1704         wlc_mctrl_write(wlc_hw);
1705 }
1706
1707 /*
1708  * Write a MAC address to the rcmta structure
1709  */
1710 void
1711 wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx,
1712                    const struct ether_addr *addr)
1713 {
1714         d11regs_t *regs = wlc_hw->regs;
1715         volatile u16 *objdata16 =
1716             (volatile u16 *)(uintptr) & regs->objdata;
1717         u32 mac_hm;
1718         u16 mac_l;
1719         osl_t *osh;
1720
1721         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
1722
1723         ASSERT(wlc_hw->corerev > 4);
1724
1725         mac_hm =
1726             (addr->octet[3] << 24) | (addr->octet[2] << 16) | (addr->
1727                                                                octet[1] << 8) |
1728             addr->octet[0];
1729         mac_l = (addr->octet[5] << 8) | addr->octet[4];
1730
1731         osh = wlc_hw->osh;
1732
1733         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1734         (void)R_REG(osh, &regs->objaddr);
1735         W_REG(osh, &regs->objdata, mac_hm);
1736         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1737         (void)R_REG(osh, &regs->objaddr);
1738         W_REG(osh, objdata16, mac_l);
1739 }
1740
1741 /*
1742  * Write a MAC address to the given match reg offset in the RXE match engine.
1743  */
1744 void
1745 wlc_bmac_set_addrmatch(wlc_hw_info_t *wlc_hw, int match_reg_offset,
1746                        const struct ether_addr *addr)
1747 {
1748         d11regs_t *regs;
1749         u16 mac_l;
1750         u16 mac_m;
1751         u16 mac_h;
1752         osl_t *osh;
1753
1754         WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit));
1755
1756         ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1757
1758         regs = wlc_hw->regs;
1759         mac_l = addr->octet[0] | (addr->octet[1] << 8);
1760         mac_m = addr->octet[2] | (addr->octet[3] << 8);
1761         mac_h = addr->octet[4] | (addr->octet[5] << 8);
1762
1763         osh = wlc_hw->osh;
1764
1765         /* enter the MAC addr into the RXE match registers */
1766         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1767         W_REG(osh, &regs->rcm_mat_data, mac_l);
1768         W_REG(osh, &regs->rcm_mat_data, mac_m);
1769         W_REG(osh, &regs->rcm_mat_data, mac_h);
1770
1771 }
1772
1773 void
1774 wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
1775                             void *buf)
1776 {
1777         d11regs_t *regs;
1778         u32 word;
1779         bool be_bit;
1780 #ifdef IL_BIGENDIAN
1781         volatile u16 *dptr = NULL;
1782 #endif                          /* IL_BIGENDIAN */
1783         osl_t *osh;
1784
1785         WL_TRACE(("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit));
1786
1787         regs = wlc_hw->regs;
1788         osh = wlc_hw->osh;
1789
1790         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1791         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1792         ASSERT((offset & ~0xffff) == 0);
1793
1794         W_REG(osh, &regs->tplatewrptr, offset);
1795
1796         /* if MCTL_BIGEND bit set in mac control register,
1797          * the chip swaps data in fifo, as well as data in
1798          * template ram
1799          */
1800         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1801
1802         while (len > 0) {
1803                 bcopy((u8 *) buf, &word, sizeof(u32));
1804
1805                 if (be_bit)
1806                         word = hton32(word);
1807                 else
1808                         word = htol32(word);
1809
1810                 W_REG(osh, &regs->tplatewrdata, word);
1811
1812                 buf = (u8 *) buf + sizeof(u32);
1813                 len -= sizeof(u32);
1814         }
1815 }
1816
1817 void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin)
1818 {
1819         osl_t *osh;
1820
1821         osh = wlc_hw->osh;
1822         wlc_hw->band->CWmin = newmin;
1823
1824         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1825         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1826         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1827 }
1828
1829 void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax)
1830 {
1831         osl_t *osh;
1832
1833         osh = wlc_hw->osh;
1834         wlc_hw->band->CWmax = newmax;
1835
1836         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1837         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1838         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1839 }
1840
1841 void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw)
1842 {
1843         bool fastclk;
1844         u32 tmp;
1845
1846         /* request FAST clock if not on */
1847         fastclk = wlc_hw->forcefastclk;
1848         if (!fastclk)
1849                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1850
1851         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1852
1853         ASSERT(wlc_hw->clk);
1854         if (D11REV_LT(wlc_hw->corerev, 17))
1855                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1856
1857         wlc_bmac_phy_reset(wlc_hw);
1858         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1859
1860         /* restore the clk */
1861         if (!fastclk)
1862                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1863 }
1864
1865 static void
1866 wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn, int len)
1867 {
1868         d11regs_t *regs = wlc_hw->regs;
1869
1870         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1871                                     bcn);
1872         /* write beacon length to SCR */
1873         ASSERT(len < 65536);
1874         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1875         /* mark beacon0 valid */
1876         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1877 }
1878
1879 static void
1880 wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn, int len)
1881 {
1882         d11regs_t *regs = wlc_hw->regs;
1883
1884         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1885                                     bcn);
1886         /* write beacon length to SCR */
1887         ASSERT(len < 65536);
1888         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1889         /* mark beacon1 valid */
1890         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1891 }
1892
1893 /* mac is assumed to be suspended at this point */
1894 void
1895 wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn, int len,
1896                                bool both)
1897 {
1898         d11regs_t *regs = wlc_hw->regs;
1899
1900         if (both) {
1901                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1902                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1903         } else {
1904                 /* bcn 0 */
1905                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1906                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1907                 /* bcn 1 */
1908                 else if (!
1909                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1910                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1911                 else            /* one template should always have been available */
1912                         ASSERT(0);
1913         }
1914 }
1915
1916 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (wlc_hw_info_t *wlc_hw)
1917 {
1918         u16 v;
1919         wlc_info_t *wlc = wlc_hw->wlc;
1920         /* update SYNTHPU_DLY */
1921
1922         if (WLCISLCNPHY(wlc->band)) {
1923                 v = SYNTHPU_DLY_LPPHY_US;
1924         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1925                 v = SYNTHPU_DLY_NPHY_US;
1926         } else {
1927                 v = SYNTHPU_DLY_BPHY_US;
1928         }
1929
1930         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1931 }
1932
1933 /* band-specific init */
1934 static void
1935 WLBANDINITFN(wlc_bmac_bsinit) (wlc_info_t *wlc, chanspec_t chanspec)
1936 {
1937         wlc_hw_info_t *wlc_hw = wlc->hw;
1938
1939         WL_TRACE(("wl%d: wlc_bmac_bsinit: bandunit %d\n", wlc_hw->unit,
1940                   wlc_hw->band->bandunit));
1941
1942         /* sanity check */
1943         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1944             PHY_TYPE_LCNXN)
1945                 ASSERT((uint)
1946                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1947                        == wlc_hw->band->phytype);
1948
1949         wlc_ucode_bsinit(wlc_hw);
1950
1951         wlc_phy_init(wlc_hw->band->pi, chanspec);
1952
1953         wlc_ucode_txant_set(wlc_hw);
1954
1955         /* cwmin is band-specific, update hardware with value for current band */
1956         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1957         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1958
1959         wlc_bmac_update_slot_timing(wlc_hw,
1960                                     BAND_5G(wlc_hw->band->
1961                                             bandtype) ? true : wlc_hw->
1962                                     shortslot);
1963
1964         /* write phytype and phyvers */
1965         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1966         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1967
1968         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1969         wlc_upd_ofdm_pctl1_table(wlc_hw);
1970
1971         wlc_bmac_upd_synthpu(wlc_hw);
1972 }
1973
1974 void wlc_bmac_core_phy_clk(wlc_hw_info_t *wlc_hw, bool clk)
1975 {
1976         WL_TRACE(("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk));
1977
1978         wlc_hw->phyclk = clk;
1979
1980         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1981
1982                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1983                                (SICF_PRST | SICF_FGC));
1984                 OSL_DELAY(1);
1985                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1986                 OSL_DELAY(1);
1987
1988         } else {                /* take phy out of reset */
1989
1990                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1991                 OSL_DELAY(1);
1992                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1993                 OSL_DELAY(1);
1994
1995         }
1996 }
1997
1998 /* Perform a soft reset of the PHY PLL */
1999 void wlc_bmac_core_phypll_reset(wlc_hw_info_t *wlc_hw)
2000 {
2001         WL_TRACE(("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit));
2002
2003         si_corereg(wlc_hw->sih, SI_CC_IDX,
2004                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
2005         OSL_DELAY(1);
2006         si_corereg(wlc_hw->sih, SI_CC_IDX,
2007                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
2008         OSL_DELAY(1);
2009         si_corereg(wlc_hw->sih, SI_CC_IDX,
2010                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
2011         OSL_DELAY(1);
2012         si_corereg(wlc_hw->sih, SI_CC_IDX,
2013                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
2014         OSL_DELAY(1);
2015 }
2016
2017 /* light way to turn on phy clock without reset for NPHY only
2018  *  refer to wlc_bmac_core_phy_clk for full version
2019  */
2020 void wlc_bmac_phyclk_fgc(wlc_hw_info_t *wlc_hw, bool clk)
2021 {
2022         /* support(necessary for NPHY and HYPHY) only */
2023         if (!WLCISNPHY(wlc_hw->band))
2024                 return;
2025
2026         if (ON == clk)
2027                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
2028         else
2029                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
2030
2031 }
2032
2033 void wlc_bmac_macphyclk_set(wlc_hw_info_t *wlc_hw, bool clk)
2034 {
2035         if (ON == clk)
2036                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
2037         else
2038                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
2039 }
2040
2041 void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw)
2042 {
2043         wlc_phy_t *pih = wlc_hw->band->pi;
2044         u32 phy_bw_clkbits;
2045         bool phy_in_reset = false;
2046
2047         WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit));
2048
2049         if (pih == NULL)
2050                 return;
2051
2052         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2053
2054         /* Specfic reset sequence required for NPHY rev 3 and 4 */
2055         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2056             NREV_LE(wlc_hw->band->phyrev, 4)) {
2057                 /* Set the PHY bandwidth */
2058                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2059
2060                 OSL_DELAY(1);
2061
2062                 /* Perform a soft reset of the PHY PLL */
2063                 wlc_bmac_core_phypll_reset(wlc_hw);
2064
2065                 /* reset the PHY */
2066                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2067                                (SICF_PRST | SICF_PCLKE));
2068                 phy_in_reset = true;
2069         } else {
2070
2071                 si_core_cflags(wlc_hw->sih,
2072                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2073                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2074         }
2075
2076         OSL_DELAY(2);
2077         wlc_bmac_core_phy_clk(wlc_hw, ON);
2078
2079         if (pih)
2080                 wlc_phy_anacore(pih, ON);
2081 }
2082
2083 /* switch to and initialize new band */
2084 static void
2085 WLBANDINITFN(wlc_bmac_setband) (wlc_hw_info_t *wlc_hw, uint bandunit,
2086                                 chanspec_t chanspec) {
2087         wlc_info_t *wlc = wlc_hw->wlc;
2088         u32 macintmask;
2089
2090         ASSERT(NBANDS_HW(wlc_hw) > 1);
2091         ASSERT(bandunit != wlc_hw->band->bandunit);
2092
2093         /* Enable the d11 core before accessing it */
2094         if (!si_iscoreup(wlc_hw->sih)) {
2095                 si_core_reset(wlc_hw->sih, 0, 0);
2096                 ASSERT(si_iscoreup(wlc_hw->sih));
2097                 wlc_mctrl_reset(wlc_hw);
2098         }
2099
2100         macintmask = wlc_setband_inact(wlc, bandunit);
2101
2102         if (!wlc_hw->up)
2103                 return;
2104
2105         wlc_bmac_core_phy_clk(wlc_hw, ON);
2106
2107         /* band-specific initializations */
2108         wlc_bmac_bsinit(wlc, chanspec);
2109
2110         /*
2111          * If there are any pending software interrupt bits,
2112          * then replace these with a harmless nonzero value
2113          * so wlc_dpc() will re-enable interrupts when done.
2114          */
2115         if (wlc->macintstatus)
2116                 wlc->macintstatus = MI_DMAINT;
2117
2118         /* restore macintmask */
2119         wl_intrsrestore(wlc->wl, macintmask);
2120
2121         /* ucode should still be suspended.. */
2122         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2123                0);
2124 }
2125
2126 /* low-level band switch utility routine */
2127 void WLBANDINITFN(wlc_setxband) (wlc_hw_info_t *wlc_hw, uint bandunit)
2128 {
2129         WL_TRACE(("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit));
2130
2131         wlc_hw->band = wlc_hw->bandstate[bandunit];
2132
2133         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2134         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2135
2136         /* set gmode core flag */
2137         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2138                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2139                                ((bandunit == 0) ? SICF_GMODE : 0));
2140         }
2141 }
2142
2143 static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw)
2144 {
2145
2146         /* reject unsupported corerev */
2147         if (!VALID_COREREV(wlc_hw->corerev)) {
2148                 WL_ERROR(("unsupported core rev %d\n", wlc_hw->corerev));
2149                 return false;
2150         }
2151
2152         return true;
2153 }
2154
2155 static bool wlc_validboardtype(wlc_hw_info_t *wlc_hw)
2156 {
2157         bool goodboard = true;
2158         uint boardrev = wlc_hw->boardrev;
2159
2160         if (boardrev == 0)
2161                 goodboard = false;
2162         else if (boardrev > 0xff) {
2163                 uint brt = (boardrev & 0xf000) >> 12;
2164                 uint b0 = (boardrev & 0xf00) >> 8;
2165                 uint b1 = (boardrev & 0xf0) >> 4;
2166                 uint b2 = boardrev & 0xf;
2167
2168                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2169                     || (b2 > 9))
2170                         goodboard = false;
2171         }
2172
2173         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2174                 return goodboard;
2175
2176         return goodboard;
2177 }
2178
2179 static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw)
2180 {
2181         const char *varname = "macaddr";
2182         char *macaddr;
2183
2184         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2185         macaddr = getvar(wlc_hw->vars, varname);
2186         if (macaddr != NULL)
2187                 return macaddr;
2188
2189         if (NBANDS_HW(wlc_hw) > 1)
2190                 varname = "et1macaddr";
2191         else
2192                 varname = "il0macaddr";
2193
2194         macaddr = getvar(wlc_hw->vars, varname);
2195         if (macaddr == NULL) {
2196                 WL_ERROR(("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n", wlc_hw->unit, varname));
2197         }
2198
2199         return macaddr;
2200 }
2201
2202 /*
2203  * Return true if radio is disabled, otherwise false.
2204  * hw radio disable signal is an external pin, users activate it asynchronously
2205  * this function could be called when driver is down and w/o clock
2206  * it operates on different registers depending on corerev and boardflag.
2207  */
2208 bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t *wlc_hw)
2209 {
2210         bool v, clk, xtal;
2211         u32 resetbits = 0, flags = 0;
2212
2213         xtal = wlc_hw->sbclk;
2214         if (!xtal)
2215                 wlc_bmac_xtal(wlc_hw, ON);
2216
2217         /* may need to take core out of reset first */
2218         clk = wlc_hw->clk;
2219         if (!clk) {
2220                 if (D11REV_LE(wlc_hw->corerev, 11))
2221                         resetbits |= SICF_PCLKE;
2222
2223                 /*
2224                  * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2225                  * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2226                  */
2227                 if (D11REV_GE(wlc_hw->corerev, 18))
2228                         flags |= SICF_PCLKE;
2229
2230                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2231                 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2232                     (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2233                     (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2234                         wlc_hw->regs =
2235                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2236                                                      0);
2237                 si_core_reset(wlc_hw->sih, flags, resetbits);
2238                 wlc_mctrl_reset(wlc_hw);
2239         }
2240
2241         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2242
2243         /* put core back into reset */
2244         if (!clk)
2245                 si_core_disable(wlc_hw->sih, 0);
2246
2247         if (!xtal)
2248                 wlc_bmac_xtal(wlc_hw, OFF);
2249
2250         return v;
2251 }
2252
2253 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2254 void wlc_bmac_hw_up(wlc_hw_info_t *wlc_hw)
2255 {
2256         if (wlc_hw->wlc->pub->hw_up)
2257                 return;
2258
2259         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
2260
2261         /*
2262          * Enable pll and xtal, initialize the power control registers,
2263          * and force fastclock for the remainder of wlc_up().
2264          */
2265         wlc_bmac_xtal(wlc_hw, ON);
2266         si_clkctl_init(wlc_hw->sih);
2267         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2268
2269         if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) {
2270                 si_pci_fixcfg(wlc_hw->sih);
2271
2272                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2273                 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2274                     (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2275                     (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2276                         wlc_hw->regs =
2277                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2278                                                      0);
2279         }
2280
2281         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2282         wlc_phy_por_inform(wlc_hw->band->pi);
2283
2284         wlc_hw->ucode_loaded = false;
2285         wlc_hw->wlc->pub->hw_up = true;
2286
2287         if ((wlc_hw->boardflags & BFL_FEM)
2288             && (CHIPID(wlc_hw->sih->chip) == BCM4313_CHIP_ID)) {
2289                 if (!
2290                     (wlc_hw->boardrev >= 0x1250
2291                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2292                         si_epa_4313war(wlc_hw->sih);
2293         }
2294 }
2295
2296 static bool wlc_dma_rxreset(wlc_hw_info_t *wlc_hw, uint fifo)
2297 {
2298         hnddma_t *di = wlc_hw->di[fifo];
2299         osl_t *osh;
2300
2301         if (D11REV_LT(wlc_hw->corerev, 12)) {
2302                 bool rxidle = true;
2303                 u16 rcv_frm_cnt = 0;
2304
2305                 osh = wlc_hw->osh;
2306
2307                 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2308                 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2309                          ((rcv_frm_cnt =
2310                            R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2311                          50000);
2312
2313                 if (!rxidle && (rcv_frm_cnt != 0))
2314                         WL_ERROR(("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n", wlc_hw->unit, __func__, fifo, rcv_frm_cnt));
2315                 OSL_DELAY(2000);
2316         }
2317
2318         return dma_rxreset(di);
2319 }
2320
2321 /* d11 core reset
2322  *   ensure fask clock during reset
2323  *   reset dma
2324  *   reset d11(out of reset)
2325  *   reset phy(out of reset)
2326  *   clear software macintstatus for fresh new start
2327  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2328  */
2329 void wlc_bmac_corereset(wlc_hw_info_t *wlc_hw, u32 flags)
2330 {
2331         d11regs_t *regs;
2332         uint i;
2333         bool fastclk;
2334         u32 resetbits = 0;
2335
2336         if (flags == WLC_USE_COREFLAGS)
2337                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2338
2339         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
2340
2341         regs = wlc_hw->regs;
2342
2343         /* request FAST clock if not on  */
2344         fastclk = wlc_hw->forcefastclk;
2345         if (!fastclk)
2346                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2347
2348         /* reset the dma engines except first time thru */
2349         if (si_iscoreup(wlc_hw->sih)) {
2350                 for (i = 0; i < NFIFO; i++)
2351                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2352                                 WL_ERROR(("wl%d: %s: dma_txreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, i));
2353                         }
2354
2355                 if ((wlc_hw->di[RX_FIFO])
2356                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2357                         WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_FIFO));
2358                 }
2359                 if (D11REV_IS(wlc_hw->corerev, 4)
2360                     && wlc_hw->di[RX_TXSTATUS_FIFO]
2361                     && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2362                         WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_TXSTATUS_FIFO));
2363                 }
2364         }
2365         /* if noreset, just stop the psm and return */
2366         if (wlc_hw->noreset) {
2367                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2368                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2369                 return;
2370         }
2371
2372         if (D11REV_LE(wlc_hw->corerev, 11))
2373                 resetbits |= SICF_PCLKE;
2374
2375         /*
2376          * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2377          * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2378          * need to enable PHY CLK
2379          */
2380         if (D11REV_GE(wlc_hw->corerev, 18))
2381                 flags |= SICF_PCLKE;
2382
2383         /* reset the core
2384          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2385          *  is cleared by the core_reset. have to re-request it.
2386          *  This adds some delay and we can optimize it by also requesting fastclk through
2387          *  chipcommon during this period if necessary. But that has to work coordinate
2388          *  with other driver like mips/arm since they may touch chipcommon as well.
2389          */
2390         wlc_hw->clk = false;
2391         si_core_reset(wlc_hw->sih, flags, resetbits);
2392         wlc_hw->clk = true;
2393         if (wlc_hw->band && wlc_hw->band->pi)
2394                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2395
2396         wlc_mctrl_reset(wlc_hw);
2397
2398         if (PMUCTL_ENAB(wlc_hw->sih))
2399                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2400
2401         wlc_bmac_phy_reset(wlc_hw);
2402
2403         /* turn on PHY_PLL */
2404         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2405
2406         /* clear sw intstatus */
2407         wlc_hw->wlc->macintstatus = 0;
2408
2409         /* restore the clk setting */
2410         if (!fastclk)
2411                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2412 }
2413
2414 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2415  * txfifo sizes needs to be modified(increased) since the newer cores
2416  * have more memory.
2417  */
2418 static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw)
2419 {
2420         d11regs_t *regs = wlc_hw->regs;
2421         u16 fifo_nu;
2422         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2423         u16 txfifo_def, txfifo_def1;
2424         u16 txfifo_cmd;
2425         osl_t *osh;
2426
2427         if (D11REV_LT(wlc_hw->corerev, 9))
2428                 goto exit;
2429
2430         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2431         txfifo_startblk = TXFIFO_START_BLK;
2432
2433         osh = wlc_hw->osh;
2434
2435         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2436         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2437
2438                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2439                 txfifo_def = (txfifo_startblk & 0xff) |
2440                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2441                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2442                     ((((txfifo_endblk -
2443                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2444                 txfifo_cmd =
2445                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2446
2447                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2448                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2449                 if (D11REV_GE(wlc_hw->corerev, 16))
2450                         W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2451
2452                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2453
2454                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2455         }
2456  exit:
2457         /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2458         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2459                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2460         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2461                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2462         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2463                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2464                             xmtfifo_sz[TX_AC_BK_FIFO]));
2465         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2466                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2467                             xmtfifo_sz[TX_BCMC_FIFO]));
2468 }
2469
2470 /* d11 core init
2471  *   reset PSM
2472  *   download ucode/PCM
2473  *   let ucode run to suspended
2474  *   download ucode inits
2475  *   config other core registers
2476  *   init dma
2477  */
2478 static void wlc_coreinit(wlc_info_t *wlc)
2479 {
2480         wlc_hw_info_t *wlc_hw = wlc->hw;
2481         d11regs_t *regs;
2482         u32 sflags;
2483         uint bcnint_us;
2484         uint i = 0;
2485         bool fifosz_fixup = false;
2486         osl_t *osh;
2487         int err = 0;
2488         u16 buf[NFIFO];
2489
2490         regs = wlc_hw->regs;
2491         osh = wlc_hw->osh;
2492
2493         WL_TRACE(("wl%d: wlc_coreinit\n", wlc_hw->unit));
2494
2495         /* reset PSM */
2496         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2497
2498         wlc_ucode_download(wlc_hw);
2499         /*
2500          * FIFOSZ fixup
2501          * 1) core5-9 use ucode 5 to save space since the PSM is the same
2502          * 2) newer chips, driver wants to controls the fifo allocation
2503          */
2504         if (D11REV_GE(wlc_hw->corerev, 4))
2505                 fifosz_fixup = true;
2506
2507         /* let the PSM run to the suspended state, set mode to BSS STA */
2508         W_REG(osh, &regs->macintstatus, -1);
2509         wlc_bmac_mctrl(wlc_hw, ~0,
2510                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2511
2512         /* wait for ucode to self-suspend after auto-init */
2513         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2514                  1000 * 1000);
2515         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2516                 WL_ERROR(("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2517                           wlc_hw->unit));
2518
2519         wlc_gpio_init(wlc);
2520
2521         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2522
2523         if (D11REV_IS(wlc_hw->corerev, 23)) {
2524                 if (WLCISNPHY(wlc_hw->band))
2525                         wlc_write_inits(wlc_hw, d11n0initvals16);
2526                 else
2527                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2528                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2529         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2530                 if (WLCISLCNPHY(wlc_hw->band)) {
2531                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2532                 } else {
2533                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2534                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2535                 }
2536         } else {
2537                 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
2538                           __func__, wlc_hw->unit, wlc_hw->corerev));
2539         }
2540
2541         /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2542         if (fifosz_fixup == true) {
2543                 wlc_corerev_fifofixup(wlc_hw);
2544         }
2545
2546         /* check txfifo allocations match between ucode and driver */
2547         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2548         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2549                 i = TX_AC_BE_FIFO;
2550                 err = -1;
2551         }
2552         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2553         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2554                 i = TX_AC_VI_FIFO;
2555                 err = -1;
2556         }
2557         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2558         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2559         buf[TX_AC_BK_FIFO] &= 0xff;
2560         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2561                 i = TX_AC_BK_FIFO;
2562                 err = -1;
2563         }
2564         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2565                 i = TX_AC_VO_FIFO;
2566                 err = -1;
2567         }
2568         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2569         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2570         buf[TX_BCMC_FIFO] &= 0xff;
2571         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2572                 i = TX_BCMC_FIFO;
2573                 err = -1;
2574         }
2575         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2576                 i = TX_ATIM_FIFO;
2577                 err = -1;
2578         }
2579         if (err != 0) {
2580                 WL_ERROR(("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n", buf[i], wlc_hw->xmtfifo_sz[i], i));
2581                 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2582                  * shmem, since driver don't overwrite those chip and
2583                  * ucode initialize data will be used.
2584                  */
2585                 if (D11REV_GE(wlc_hw->corerev, 4))
2586                         ASSERT(0);
2587         }
2588
2589         /* make sure we can still talk to the mac */
2590         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2591
2592         /* band-specific inits done by wlc_bsinit() */
2593
2594         /* Set up frame burst size and antenna swap threshold init values */
2595         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2596         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2597
2598         /* enable one rx interrupt per received frame */
2599         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2600         if (D11REV_IS(wlc_hw->corerev, 4))
2601                 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2602
2603         /* set the station mode (BSS STA) */
2604         wlc_bmac_mctrl(wlc_hw,
2605                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2606                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2607
2608         /* set up Beacon interval */
2609         bcnint_us = 0x8000 << 10;
2610         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2611         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2612         W_REG(osh, &regs->macintstatus, MI_GP1);
2613
2614         /* write interrupt mask */
2615         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2616         if (D11REV_IS(wlc_hw->corerev, 4))
2617                 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2618                       DEF_RXINTMASK);
2619
2620         /* allow the MAC to control the PHY clock (dynamic on/off) */
2621         wlc_bmac_macphyclk_set(wlc_hw, ON);
2622
2623         /* program dynamic clock control fast powerup delay register */
2624         if (D11REV_GT(wlc_hw->corerev, 4)) {
2625                 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2626                 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2627         }
2628
2629         /* tell the ucode the corerev */
2630         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2631
2632         /* tell the ucode MAC capabilities */
2633         if (D11REV_GE(wlc_hw->corerev, 13)) {
2634                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2635                                    (u16) (wlc_hw->machwcap & 0xffff));
2636                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2637                                    (u16) ((wlc_hw->
2638                                               machwcap >> 16) & 0xffff));
2639         }
2640
2641         /* write retry limits to SCR, this done after PSM init */
2642         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2643         (void)R_REG(osh, &regs->objaddr);
2644         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2645         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2646         (void)R_REG(osh, &regs->objaddr);
2647         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2648
2649         /* write rate fallback retry limits */
2650         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2651         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2652
2653         if (D11REV_GE(wlc_hw->corerev, 16)) {
2654                 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2655                 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2656         }
2657
2658         /* dma initializations */
2659         wlc->txpend16165war = 0;
2660
2661         /* init the tx dma engines */
2662         for (i = 0; i < NFIFO; i++) {
2663                 if (wlc_hw->di[i])
2664                         dma_txinit(wlc_hw->di[i]);
2665         }
2666
2667         /* init the rx dma engine(s) and post receive buffers */
2668         dma_rxinit(wlc_hw->di[RX_FIFO]);
2669         dma_rxfill(wlc_hw->di[RX_FIFO]);
2670         if (D11REV_IS(wlc_hw->corerev, 4)) {
2671                 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2672                 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2673         }
2674 }
2675
2676 /* This function is used for changing the tsf frac register
2677  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2678  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2679  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2680  * HTPHY Formula is 2^26/freq(MHz) e.g.
2681  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2682  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2683  * For spuron: 123MHz -> 2^26/123    = 545600.5
2684  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2685  * For spur off: 120MHz -> 2^26/120    = 559240.5
2686  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2687  */
2688
2689 void wlc_bmac_switch_macfreq(wlc_hw_info_t *wlc_hw, u8 spurmode)
2690 {
2691         d11regs_t *regs;
2692         osl_t *osh;
2693         regs = wlc_hw->regs;
2694         osh = wlc_hw->osh;
2695
2696         if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2697             (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID)) {
2698                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2699                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2700                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2701                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2702                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2703                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2704                 } else {        /* 120Mhz */
2705                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2706                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2707                 }
2708         } else if (WLCISLCNPHY(wlc_hw->band)) {
2709                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2710                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2711                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2712                 } else {        /* 80Mhz */
2713                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2714                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2715                 }
2716         }
2717 }
2718
2719 /* Initialize GPIOs that are controlled by D11 core */
2720 static void wlc_gpio_init(wlc_info_t *wlc)
2721 {
2722         wlc_hw_info_t *wlc_hw = wlc->hw;
2723         d11regs_t *regs;
2724         u32 gc, gm;
2725         osl_t *osh;
2726
2727         regs = wlc_hw->regs;
2728         osh = wlc_hw->osh;
2729
2730         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2731         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2732
2733         /*
2734          * Common GPIO setup:
2735          *      G0 = LED 0 = WLAN Activity
2736          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2737          *      G2 = LED 2 = WLAN 5 GHz Radio State
2738          *      G4 = radio disable input (HI enabled, LO disabled)
2739          */
2740
2741         gc = gm = 0;
2742
2743         /* Allocate GPIOs for mimo antenna diversity feature */
2744         if (WLANTSEL_ENAB(wlc)) {
2745                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2746                         /* Enable antenna diversity, use 2x3 mode */
2747                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2748                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2749                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2750                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2751
2752                         /* init superswitch control */
2753                         wlc_phy_antsel_init(wlc_hw->band->pi, false);
2754
2755                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2756                         ASSERT((gm & BOARD_GPIO_12) == 0);
2757                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2758                         /* The board itself is powered by these GPIOs (when not sending pattern)
2759                          * So set them high
2760                          */
2761                         OR_REG(osh, &regs->psm_gpio_oe,
2762                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2763                         OR_REG(osh, &regs->psm_gpio_out,
2764                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2765
2766                         /* Enable antenna diversity, use 2x4 mode */
2767                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2768                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2769                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2770                                      WLC_BAND_ALL);
2771
2772                         /* Configure the desired clock to be 4Mhz */
2773                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2774                                            ANTSEL_CLKDIV_4MHZ);
2775                 }
2776         }
2777         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2778         if (wlc_hw->boardflags & BFL_PACTRL)
2779                 gm |= gc |= BOARD_GPIO_PACTRL;
2780
2781         /* apply to gpiocontrol register */
2782         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2783 }
2784
2785 static void wlc_ucode_download(wlc_hw_info_t *wlc_hw)
2786 {
2787         wlc_info_t *wlc;
2788         wlc = wlc_hw->wlc;
2789
2790         if (wlc_hw->ucode_loaded)
2791                 return;
2792
2793         if (D11REV_IS(wlc_hw->corerev, 23)) {
2794                 if (WLCISNPHY(wlc_hw->band)) {
2795                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2796                                         bcm43xx_16_mimosz);
2797                         wlc_hw->ucode_loaded = true;
2798                 } else
2799                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2800                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2801         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2802                 if (WLCISLCNPHY(wlc_hw->band)) {
2803                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2804                                         bcm43xx_24_lcnsz);
2805                         wlc_hw->ucode_loaded = true;
2806                 } else {
2807                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2808                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2809                 }
2810         }
2811 }
2812
2813 static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
2814                               const uint nbytes) {
2815         osl_t *osh;
2816         d11regs_t *regs = wlc_hw->regs;
2817         uint i;
2818         uint count;
2819
2820         osh = wlc_hw->osh;
2821
2822         WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw->unit));
2823
2824         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2825
2826         count = (nbytes / sizeof(u32));
2827
2828         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2829         (void)R_REG(osh, &regs->objaddr);
2830         for (i = 0; i < count; i++)
2831                 W_REG(osh, &regs->objdata, ucode[i]);
2832 }
2833
2834 static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits)
2835 {
2836         int i;
2837         osl_t *osh;
2838         volatile u8 *base;
2839
2840         WL_TRACE(("wl%d: wlc_write_inits\n", wlc_hw->unit));
2841
2842         osh = wlc_hw->osh;
2843         base = (volatile u8 *)wlc_hw->regs;
2844
2845         for (i = 0; inits[i].addr != 0xffff; i++) {
2846                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2847
2848                 if (inits[i].size == 2)
2849                         W_REG(osh, (u16 *) (uintptr) (base + inits[i].addr),
2850                               inits[i].value);
2851                 else if (inits[i].size == 4)
2852                         W_REG(osh, (u32 *) (uintptr) (base + inits[i].addr),
2853                               inits[i].value);
2854         }
2855 }
2856
2857 static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw)
2858 {
2859         u16 phyctl;
2860         u16 phytxant = wlc_hw->bmac_phytxant;
2861         u16 mask = PHY_TXC_ANT_MASK;
2862
2863         /* set the Probe Response frame phy control word */
2864         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2865         phyctl = (phyctl & ~mask) | phytxant;
2866         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2867
2868         /* set the Response (ACK/CTS) frame phy control word */
2869         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2870         phyctl = (phyctl & ~mask) | phytxant;
2871         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2872 }
2873
2874 void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, u16 phytxant)
2875 {
2876         /* update sw state */
2877         wlc_hw->bmac_phytxant = phytxant;
2878
2879         /* push to ucode if up */
2880         if (!wlc_hw->up)
2881                 return;
2882         wlc_ucode_txant_set(wlc_hw);
2883
2884 }
2885
2886 u16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw)
2887 {
2888         return (u16) wlc_hw->wlc->stf->txant;
2889 }
2890
2891 void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type)
2892 {
2893         wlc_hw->antsel_type = antsel_type;
2894
2895         /* Update the antsel type for phy module to use */
2896         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2897 }
2898
2899 void wlc_bmac_fifoerrors(wlc_hw_info_t *wlc_hw)
2900 {
2901         bool fatal = false;
2902         uint unit;
2903         uint intstatus, idx;
2904         d11regs_t *regs = wlc_hw->regs;
2905
2906         unit = wlc_hw->unit;
2907
2908         for (idx = 0; idx < NFIFO; idx++) {
2909                 /* read intstatus register and ignore any non-error bits */
2910                 intstatus =
2911                     R_REG(wlc_hw->osh,
2912                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2913                 if (!intstatus)
2914                         continue;
2915
2916                 WL_TRACE(("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n", unit,
2917                           idx, intstatus));
2918
2919                 if (intstatus & I_RO) {
2920                         WL_ERROR(("wl%d: fifo %d: receive fifo overflow\n",
2921                                   unit, idx));
2922                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
2923                         fatal = true;
2924                 }
2925
2926                 if (intstatus & I_PC) {
2927                         WL_ERROR(("wl%d: fifo %d: descriptor error\n", unit,
2928                                   idx));
2929                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
2930                         fatal = true;
2931                 }
2932
2933                 if (intstatus & I_PD) {
2934                         WL_ERROR(("wl%d: fifo %d: data error\n", unit, idx));
2935                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
2936                         fatal = true;
2937                 }
2938
2939                 if (intstatus & I_DE) {
2940                         WL_ERROR(("wl%d: fifo %d: descriptor protocol error\n",
2941                                   unit, idx));
2942                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
2943                         fatal = true;
2944                 }
2945
2946                 if (intstatus & I_RU) {
2947                         WL_ERROR(("wl%d: fifo %d: receive descriptor underflow\n", unit, idx));
2948                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2949                 }
2950
2951                 if (intstatus & I_XU) {
2952                         WL_ERROR(("wl%d: fifo %d: transmit fifo underflow\n",
2953                                   idx, unit));
2954                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
2955                         fatal = true;
2956                 }
2957
2958                 if (fatal) {
2959                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2960                         break;
2961                 } else
2962                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2963                               intstatus);
2964         }
2965 }
2966
2967 void wlc_intrson(wlc_info_t *wlc)
2968 {
2969         wlc_hw_info_t *wlc_hw = wlc->hw;
2970         ASSERT(wlc->defmacintmask);
2971         wlc->macintmask = wlc->defmacintmask;
2972         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2973 }
2974
2975 /* callback for siutils.c, which has only wlc handler, no wl
2976  * they both check up, not only because there is no need to off/restore d11 interrupt
2977  *  but also because per-port code may require sync with valid interrupt.
2978  */
2979
2980 static u32 wlc_wlintrsoff(wlc_info_t *wlc)
2981 {
2982         if (!wlc->hw->up)
2983                 return 0;
2984
2985         return wl_intrsoff(wlc->wl);
2986 }
2987
2988 static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask)
2989 {
2990         if (!wlc->hw->up)
2991                 return;
2992
2993         wl_intrsrestore(wlc->wl, macintmask);
2994 }
2995
2996 u32 wlc_intrsoff(wlc_info_t *wlc)
2997 {
2998         wlc_hw_info_t *wlc_hw = wlc->hw;
2999         u32 macintmask;
3000
3001         if (!wlc_hw->clk)
3002                 return 0;
3003
3004         macintmask = wlc->macintmask;   /* isr can still happen */
3005
3006         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
3007         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
3008         OSL_DELAY(1);           /* ensure int line is no longer driven */
3009         wlc->macintmask = 0;
3010
3011         /* return previous macintmask; resolve race between us and our isr */
3012         return wlc->macintstatus ? 0 : macintmask;
3013 }
3014
3015 void wlc_intrsrestore(wlc_info_t *wlc, u32 macintmask)
3016 {
3017         wlc_hw_info_t *wlc_hw = wlc->hw;
3018         if (!wlc_hw->clk)
3019                 return;
3020
3021         wlc->macintmask = macintmask;
3022         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
3023 }
3024
3025 void wlc_bmac_mute(wlc_hw_info_t *wlc_hw, bool on, mbool flags)
3026 {
3027         struct ether_addr null_ether_addr = { {0, 0, 0, 0, 0, 0} };
3028
3029         if (on) {
3030                 /* suspend tx fifos */
3031                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
3032                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
3033                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
3034                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
3035
3036                 /* zero the address match register so we do not send ACKs */
3037                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3038                                        &null_ether_addr);
3039         } else {
3040                 /* resume tx fifos */
3041                 if (!wlc_hw->wlc->tx_suspended) {
3042                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3043                 }
3044                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3045                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3046                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3047
3048                 /* Restore address */
3049                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3050                                        &wlc_hw->etheraddr);
3051         }
3052
3053         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3054
3055         if (on)
3056                 wlc_ucode_mute_override_set(wlc_hw);
3057         else
3058                 wlc_ucode_mute_override_clear(wlc_hw);
3059 }
3060
3061 void wlc_bmac_set_deaf(wlc_hw_info_t *wlc_hw, bool user_flag)
3062 {
3063         wlc_phy_set_deaf(wlc_hw->band->pi, user_flag);
3064 }
3065
3066 int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t *wlc_hw, uint fifo, uint *blocks)
3067 {
3068         if (fifo >= NFIFO)
3069                 return BCME_RANGE;
3070
3071         *blocks = wlc_hw->xmtfifo_sz[fifo];
3072
3073         return 0;
3074 }
3075
3076 int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, uint blocks)
3077 {
3078         if (fifo >= NFIFO || blocks > 299)
3079                 return BCME_RANGE;
3080
3081         /* BMAC_NOTE, change blocks to u16 */
3082         wlc_hw->xmtfifo_sz[fifo] = (u16) blocks;
3083
3084         return 0;
3085 }
3086
3087 /* wlc_bmac_tx_fifo_suspended:
3088  * Check the MAC's tx suspend status for a tx fifo.
3089  *
3090  * When the MAC acknowledges a tx suspend, it indicates that no more
3091  * packets will be transmitted out the radio. This is independent of
3092  * DMA channel suspension---the DMA may have finished suspending, or may still
3093  * be pulling data into a tx fifo, by the time the MAC acks the suspend
3094  * request.
3095  */
3096 bool wlc_bmac_tx_fifo_suspended(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3097 {
3098         /* check that a suspend has been requested and is no longer pending */
3099
3100         /*
3101          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3102          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3103          * chnstatus register.
3104          * The tx fifo suspend completion is independent of the DMA suspend completion and
3105          *   may be acked before or after the DMA is suspended.
3106          */
3107         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3108             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3109              (1 << tx_fifo)) == 0)
3110                 return true;
3111
3112         return false;
3113 }
3114
3115 void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3116 {
3117         u8 fifo = 1 << tx_fifo;
3118
3119         /* Two clients of this code, 11h Quiet period and scanning. */
3120
3121         /* only suspend if not already suspended */
3122         if ((wlc_hw->suspended_fifos & fifo) == fifo)
3123                 return;
3124
3125         /* force the core awake only if not already */
3126         if (wlc_hw->suspended_fifos == 0)
3127                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3128
3129         wlc_hw->suspended_fifos |= fifo;
3130
3131         if (wlc_hw->di[tx_fifo]) {
3132                 /* Suspending AMPDU transmissions in the middle can cause underflow
3133                  * which may result in mismatch between ucode and driver
3134                  * so suspend the mac before suspending the FIFO
3135                  */
3136                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3137                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
3138
3139                 dma_txsuspend(wlc_hw->di[tx_fifo]);
3140
3141                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3142                         wlc_enable_mac(wlc_hw->wlc);
3143         }
3144 }
3145
3146 void wlc_bmac_tx_fifo_resume(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3147 {
3148         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3149          * here for PIO otherwise the watchdog will catch the inconsistency and fire
3150          */
3151         /* Two clients of this code, 11h Quiet period and scanning. */
3152         if (wlc_hw->di[tx_fifo])
3153                 dma_txresume(wlc_hw->di[tx_fifo]);
3154
3155         /* allow core to sleep again */
3156         if (wlc_hw->suspended_fifos == 0)
3157                 return;
3158         else {
3159                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3160                 if (wlc_hw->suspended_fifos == 0)
3161                         wlc_ucode_wake_override_clear(wlc_hw,
3162                                                       WLC_WAKE_OVERRIDE_TXFIFO);
3163         }
3164 }
3165
3166 /*
3167  * Read and clear macintmask and macintstatus and intstatus registers.
3168  * This routine should be called with interrupts off
3169  * Return:
3170  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
3171  *   0 if the interrupt is not for us, or we are in some special cases;
3172  *   device interrupt status bits otherwise.
3173  */
3174 static inline u32 wlc_intstatus(wlc_info_t *wlc, bool in_isr)
3175 {
3176         wlc_hw_info_t *wlc_hw = wlc->hw;
3177         d11regs_t *regs = wlc_hw->regs;
3178         u32 macintstatus;
3179         u32 intstatus_rxfifo, intstatus_txsfifo;
3180         osl_t *osh;
3181
3182         osh = wlc_hw->osh;
3183
3184         /* macintstatus includes a DMA interrupt summary bit */
3185         macintstatus = R_REG(osh, &regs->macintstatus);
3186
3187         WL_TRACE(("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus));
3188
3189         /* detect cardbus removed, in power down(suspend) and in reset */
3190         if (DEVICEREMOVED(wlc))
3191                 return -1;
3192
3193         /* DEVICEREMOVED succeeds even when the core is still resetting,
3194          * handle that case here.
3195          */
3196         if (macintstatus == 0xffffffff)
3197                 return 0;
3198
3199         /* defer unsolicited interrupts */
3200         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3201
3202         /* if not for us */
3203         if (macintstatus == 0)
3204                 return 0;
3205
3206         /* interrupts are already turned off for CFE build
3207          * Caution: For CFE Turning off the interrupts again has some undesired
3208          * consequences
3209          */
3210         /* turn off the interrupts */
3211         W_REG(osh, &regs->macintmask, 0);
3212 #ifndef BCMSDIO
3213         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3214 #endif
3215         wlc->macintmask = 0;
3216
3217         /* clear device interrupts */
3218         W_REG(osh, &regs->macintstatus, macintstatus);
3219
3220         /* MI_DMAINT is indication of non-zero intstatus */
3221         if (macintstatus & MI_DMAINT) {
3222                 if (D11REV_IS(wlc_hw->corerev, 4)) {
3223                         intstatus_rxfifo =
3224                             R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3225                         intstatus_txsfifo =
3226                             R_REG(osh,
3227                                   &regs->intctrlregs[RX_TXSTATUS_FIFO].
3228                                   intstatus);
3229                         WL_TRACE(("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n", wlc_hw->unit, intstatus_rxfifo, intstatus_txsfifo));
3230
3231                         /* defer unsolicited interrupt hints */
3232                         intstatus_rxfifo &= DEF_RXINTMASK;
3233                         intstatus_txsfifo &= DEF_RXINTMASK;
3234
3235                         /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3236                         /* clear interrupt hints */
3237                         if (intstatus_rxfifo)
3238                                 W_REG(osh,
3239                                       &regs->intctrlregs[RX_FIFO].intstatus,
3240                                       intstatus_rxfifo);
3241                         else
3242                                 macintstatus &= ~MI_DMAINT;
3243
3244                         /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3245                         if (intstatus_txsfifo) {
3246                                 W_REG(osh,
3247                                       &regs->intctrlregs[RX_TXSTATUS_FIFO].
3248                                       intstatus, intstatus_txsfifo);
3249                                 macintstatus |= MI_TFS;
3250                         }
3251                 } else {
3252                         /*
3253                          * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3254                          * If MI_DMAINT is set, assume it is set and clear the interrupt.
3255                          */
3256                         W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3257                               DEF_RXINTMASK);
3258                 }
3259         }
3260
3261         return macintstatus;
3262 }
3263
3264 /* Update wlc->macintstatus and wlc->intstatus[]. */
3265 /* Return true if they are updated successfully. false otherwise */
3266 bool wlc_intrsupd(wlc_info_t *wlc)
3267 {
3268         u32 macintstatus;
3269
3270         ASSERT(wlc->macintstatus != 0);
3271
3272         /* read and clear macintstatus and intstatus registers */
3273         macintstatus = wlc_intstatus(wlc, false);
3274
3275         /* device is removed */
3276         if (macintstatus == 0xffffffff)
3277                 return false;
3278
3279         /* update interrupt status in software */
3280         wlc->macintstatus |= macintstatus;
3281
3282         return true;
3283 }
3284
3285 /*
3286  * First-level interrupt processing.
3287  * Return true if this was our interrupt, false otherwise.
3288  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3289  * false otherwise.
3290  */
3291 bool BCMFASTPATH wlc_isr(wlc_info_t *wlc, bool *wantdpc)
3292 {
3293         wlc_hw_info_t *wlc_hw = wlc->hw;
3294         u32 macintstatus;
3295
3296         *wantdpc = false;
3297
3298         if (!wlc_hw->up || !wlc->macintmask)
3299                 return false;
3300
3301         /* read and clear macintstatus and intstatus registers */
3302         macintstatus = wlc_intstatus(wlc, true);
3303
3304         if (macintstatus == 0xffffffff)
3305                 WL_ERROR(("DEVICEREMOVED detected in the ISR code path.\n"));
3306
3307         /* it is not for us */
3308         if (macintstatus == 0)
3309                 return false;
3310
3311         *wantdpc = true;
3312
3313         /* save interrupt status bits */
3314         ASSERT(wlc->macintstatus == 0);
3315         wlc->macintstatus = macintstatus;
3316
3317         return true;
3318
3319 }
3320
3321 /* process tx completion events for corerev < 5 */
3322 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc_hw)
3323 {
3324         void *status_p;
3325         tx_status_t *txs;
3326         osl_t *osh;
3327         bool fatal = false;
3328
3329         WL_TRACE(("wl%d: wlc_txstatusrecv\n", wlc_hw->unit));
3330
3331         osh = wlc_hw->osh;
3332
3333         while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3334
3335                 txs = (tx_status_t *) PKTDATA(status_p);
3336                 /* MAC uses little endian only */
3337                 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3338
3339                 /* shift low bits for tx_status_t status compatibility */
3340                 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3341                     | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3342
3343                 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3344
3345                 PKTFREE(osh, status_p, false);
3346         }
3347
3348         if (fatal)
3349                 return true;
3350
3351         /* post more rbufs */
3352         dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3353
3354         return false;
3355 }
3356
3357 static bool BCMFASTPATH
3358 wlc_bmac_dotxstatus(wlc_hw_info_t *wlc_hw, tx_status_t *txs, u32 s2)
3359 {
3360         /* discard intermediate indications for ucode with one legitimate case:
3361          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3362          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3363          *   transmission count)
3364          */
3365         if (!(txs->status & TX_STATUS_AMPDU)
3366             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3367                 return false;
3368         }
3369
3370         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3371 }
3372
3373 /* process tx completion events in BMAC
3374  * Return true if more tx status need to be processed. false otherwise.
3375  */
3376 static bool BCMFASTPATH
3377 wlc_bmac_txstatus(wlc_hw_info_t *wlc_hw, bool bound, bool *fatal)
3378 {
3379         bool morepending = false;
3380         wlc_info_t *wlc = wlc_hw->wlc;
3381
3382         WL_TRACE(("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit));
3383
3384         if (D11REV_IS(wlc_hw->corerev, 4)) {
3385                 /* to retire soon */
3386                 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3387
3388                 if (*fatal)
3389                         return 0;
3390         } else {
3391                 /* corerev >= 5 */
3392                 d11regs_t *regs;
3393                 osl_t *osh;
3394                 tx_status_t txstatus, *txs;
3395                 u32 s1, s2;
3396                 uint n = 0;
3397                 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3398                 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3399
3400                 txs = &txstatus;
3401                 regs = wlc_hw->regs;
3402                 osh = wlc_hw->osh;
3403                 while (!(*fatal)
3404                        && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3405
3406                         if (s1 == 0xffffffff) {
3407                                 WL_ERROR(("wl%d: %s: dead chip\n",
3408                                           wlc_hw->unit, __func__));
3409                                 ASSERT(s1 != 0xffffffff);
3410                                 return morepending;
3411                         }
3412
3413                         s2 = R_REG(osh, &regs->frmtxstatus2);
3414
3415                         txs->status = s1 & TXS_STATUS_MASK;
3416                         txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3417                         txs->sequence = s2 & TXS_SEQ_MASK;
3418                         txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3419                         txs->lasttxtime = 0;
3420
3421                         *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3422
3423                         /* !give others some time to run! */
3424                         if (++n >= max_tx_num)
3425                                 break;
3426                 }
3427
3428                 if (*fatal)
3429                         return 0;
3430
3431                 if (n >= max_tx_num)
3432                         morepending = true;
3433         }
3434
3435         if (!pktq_empty(&wlc->active_queue->q))
3436                 wlc_send_q(wlc, wlc->active_queue);
3437
3438         return morepending;
3439 }
3440
3441 void wlc_suspend_mac_and_wait(wlc_info_t *wlc)
3442 {
3443         wlc_hw_info_t *wlc_hw = wlc->hw;
3444         d11regs_t *regs = wlc_hw->regs;
3445         u32 mc, mi;
3446         osl_t *osh;
3447
3448         WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw->unit,
3449                   wlc_hw->band->bandunit));
3450
3451         /*
3452          * Track overlapping suspend requests
3453          */
3454         wlc_hw->mac_suspend_depth++;
3455         if (wlc_hw->mac_suspend_depth > 1)
3456                 return;
3457
3458         osh = wlc_hw->osh;
3459
3460         /* force the core awake */
3461         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3462
3463         mc = R_REG(osh, &regs->maccontrol);
3464
3465         if (mc == 0xffffffff) {
3466                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3467                 wl_down(wlc->wl);
3468                 return;
3469         }
3470         ASSERT(!(mc & MCTL_PSM_JMP_0));
3471         ASSERT(mc & MCTL_PSM_RUN);
3472         ASSERT(mc & MCTL_EN_MAC);
3473
3474         mi = R_REG(osh, &regs->macintstatus);
3475         if (mi == 0xffffffff) {
3476                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3477                 wl_down(wlc->wl);
3478                 return;
3479         }
3480         ASSERT(!(mi & MI_MACSSPNDD));
3481
3482         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3483
3484         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3485                  WLC_MAX_MAC_SUSPEND);
3486
3487         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3488                 WL_ERROR(("wl%d: wlc_suspend_mac_and_wait: waited %d uS and "
3489                           "MI_MACSSPNDD is still not on.\n",
3490                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND));
3491                 WL_ERROR(("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n", wlc_hw->unit, R_REG(osh, &regs->psmdebug), R_REG(osh, &regs->phydebug), R_REG(osh, &regs->psm_brc)));
3492         }
3493
3494         mc = R_REG(osh, &regs->maccontrol);
3495         if (mc == 0xffffffff) {
3496                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3497                 wl_down(wlc->wl);
3498                 return;
3499         }
3500         ASSERT(!(mc & MCTL_PSM_JMP_0));
3501         ASSERT(mc & MCTL_PSM_RUN);
3502         ASSERT(!(mc & MCTL_EN_MAC));
3503 }
3504
3505 void wlc_enable_mac(wlc_info_t *wlc)
3506 {
3507         wlc_hw_info_t *wlc_hw = wlc->hw;
3508         d11regs_t *regs = wlc_hw->regs;
3509         u32 mc, mi;
3510         osl_t *osh;
3511
3512         WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw->unit,
3513                   wlc->band->bandunit));
3514
3515         /*
3516          * Track overlapping suspend requests
3517          */
3518         ASSERT(wlc_hw->mac_suspend_depth > 0);
3519         wlc_hw->mac_suspend_depth--;
3520         if (wlc_hw->mac_suspend_depth > 0)
3521                 return;
3522
3523         osh = wlc_hw->osh;
3524
3525         mc = R_REG(osh, &regs->maccontrol);
3526         ASSERT(!(mc & MCTL_PSM_JMP_0));
3527         ASSERT(!(mc & MCTL_EN_MAC));
3528         ASSERT(mc & MCTL_PSM_RUN);
3529
3530         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3531         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3532
3533         mc = R_REG(osh, &regs->maccontrol);
3534         ASSERT(!(mc & MCTL_PSM_JMP_0));
3535         ASSERT(mc & MCTL_EN_MAC);
3536         ASSERT(mc & MCTL_PSM_RUN);
3537
3538         mi = R_REG(osh, &regs->macintstatus);
3539         ASSERT(!(mi & MI_MACSSPNDD));
3540
3541         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3542 }
3543
3544 void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t *wlc_hw, bool abie, bool isht)
3545 {
3546         if (!(WLCISNPHY(wlc_hw->band) && (D11REV_GE(wlc_hw->corerev, 16))))
3547                 return;
3548
3549         if (isht) {
3550                 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 3)) {
3551                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3552                                 ~IFS_CTL1_EDCRS);
3553                 }
3554         } else {
3555                 /* enable EDCRS for non-11n association */
3556                 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1, IFS_CTL1_EDCRS);
3557         }
3558
3559         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3)) {
3560                 if (CHSPEC_IS20(wlc_hw->chanspec)) {
3561                         /* 20 mhz, use 20U ED only */
3562                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3563                                IFS_CTL1_EDCRS);
3564                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3565                                 ~IFS_CTL1_EDCRS_20L);
3566                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3567                                 ~IFS_CTL1_EDCRS_40);
3568                 } else {
3569                         /* 40 mhz, use 20U 20L and 40 ED */
3570                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3571                                IFS_CTL1_EDCRS);
3572                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3573                                IFS_CTL1_EDCRS_20L);
3574                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3575                                IFS_CTL1_EDCRS_40);
3576                 }
3577         }
3578 }
3579
3580 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw)
3581 {
3582         u8 rate;
3583         u8 rates[8] = {
3584                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3585                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3586         };
3587         u16 entry_ptr;
3588         u16 pctl1;
3589         uint i;
3590
3591         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3592                 return;
3593
3594         /* walk the phy rate table and update the entries */
3595         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3596                 rate = rates[i];
3597
3598                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3599
3600                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3601                 pctl1 =
3602                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3603
3604                 /* modify the value */
3605                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3606                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3607
3608                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3609                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3610                                    pctl1);
3611         }
3612 }
3613
3614 static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, u8 rate)
3615 {
3616         uint i;
3617         u8 plcp_rate = 0;
3618         struct plcp_signal_rate_lookup {
3619                 u8 rate;
3620                 u8 signal_rate;
3621         };
3622         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3623         const struct plcp_signal_rate_lookup rate_lookup[] = {
3624                 {WLC_RATE_6M, 0xB},
3625                 {WLC_RATE_9M, 0xF},
3626                 {WLC_RATE_12M, 0xA},
3627                 {WLC_RATE_18M, 0xE},
3628                 {WLC_RATE_24M, 0x9},
3629                 {WLC_RATE_36M, 0xD},
3630                 {WLC_RATE_48M, 0x8},
3631                 {WLC_RATE_54M, 0xC}
3632         };
3633
3634         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3635                 if (rate == rate_lookup[i].rate) {
3636                         plcp_rate = rate_lookup[i].signal_rate;
3637                         break;
3638                 }
3639         }
3640
3641         /* Find the SHM pointer to the rate table entry by looking in the
3642          * Direct-map Table
3643          */
3644         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3645 }
3646
3647 void wlc_bmac_band_stf_ss_set(wlc_hw_info_t *wlc_hw, u8 stf_mode)
3648 {
3649         wlc_hw->hw_stf_ss_opmode = stf_mode;
3650
3651         if (wlc_hw->clk)
3652                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3653 }
3654
3655 void BCMFASTPATH
3656 wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, u32 *tsf_l_ptr,
3657                   u32 *tsf_h_ptr)
3658 {
3659         d11regs_t *regs = wlc_hw->regs;
3660
3661         /* read the tsf timer low, then high to get an atomic read */
3662         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3663         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3664
3665         return;
3666 }
3667
3668 bool wlc_bmac_validate_chip_access(wlc_hw_info_t *wlc_hw)
3669 {
3670         d11regs_t *regs;
3671         u32 w, val;
3672         volatile u16 *reg16;
3673         osl_t *osh;
3674
3675         WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw->unit));
3676
3677         regs = wlc_hw->regs;
3678         osh = wlc_hw->osh;
3679
3680         /* Validate dchip register access */
3681
3682         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3683         (void)R_REG(osh, &regs->objaddr);
3684         w = R_REG(osh, &regs->objdata);
3685
3686         /* Can we write and read back a 32bit register? */
3687         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3688         (void)R_REG(osh, &regs->objaddr);
3689         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3690
3691         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3692         (void)R_REG(osh, &regs->objaddr);
3693         val = R_REG(osh, &regs->objdata);
3694         if (val != (u32) 0xaa5555aa) {
3695                 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val));
3696                 return false;
3697         }
3698
3699         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3700         (void)R_REG(osh, &regs->objaddr);
3701         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3702
3703         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3704         (void)R_REG(osh, &regs->objaddr);
3705         val = R_REG(osh, &regs->objdata);
3706         if (val != (u32) 0x55aaaa55) {
3707                 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val));
3708                 return false;
3709         }
3710
3711         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3712         (void)R_REG(osh, &regs->objaddr);
3713         W_REG(osh, &regs->objdata, w);
3714
3715         if (D11REV_LT(wlc_hw->corerev, 11)) {
3716                 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3717                  * for our interface, low to high
3718                  */
3719                 reg16 = (volatile u16 *)(uintptr) & regs->tsf_cfpstart;
3720
3721                 /* write the CFPStart register low half explicitly, starting a buffered write */
3722                 W_REG(osh, reg16, 0xAAAA);
3723
3724                 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3725                  * If the low 16 bits are written first, followed by the high 16 bits then the
3726                  * 32 bit value 0xCCCCBBBB should end up in the register.
3727                  * If the order is reversed, then the write to the high half will trigger a buffered
3728                  * write of 0xCCCCAAAA.
3729                  * If the bus is 32 bits, then this is not much of a test, and the reg should
3730                  * have the correct value 0xCCCCBBBB.
3731                  */
3732                 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3733
3734                 /* verify with the 16 bit registers that have no side effects */
3735                 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3736                 if (val != (uint) 0xBBBB) {
3737                         WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xBBBB));
3738                         return false;
3739                 }
3740                 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3741                 if (val != (uint) 0xCCCC) {
3742                         WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xCCCC));
3743                         return false;
3744                 }
3745
3746         }
3747
3748         /* clear CFPStart */
3749         W_REG(osh, &regs->tsf_cfpstart, 0);
3750
3751         w = R_REG(osh, &regs->maccontrol);
3752         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3753             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3754                 WL_ERROR(("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, (MCTL_IHR_EN | MCTL_WAKE), (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)));
3755                 return false;
3756         }
3757
3758         return true;
3759 }
3760
3761 #define PHYPLL_WAIT_US  100000
3762
3763 void wlc_bmac_core_phypll_ctl(wlc_hw_info_t *wlc_hw, bool on)
3764 {
3765         d11regs_t *regs;
3766         osl_t *osh;
3767         u32 tmp;
3768
3769         WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit));
3770
3771         tmp = 0;
3772         regs = wlc_hw->regs;
3773         osh = wlc_hw->osh;
3774
3775         if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3776                 return;
3777
3778         if (on) {
3779                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3780                         OR_REG(osh, &regs->clk_ctl_st,
3781                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3782                                 CCS_ERSRC_REQ_PHYPLL));
3783                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3784                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3785                                  PHYPLL_WAIT_US);
3786
3787                         tmp = R_REG(osh, &regs->clk_ctl_st);
3788                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3789                             (CCS_ERSRC_AVAIL_HT)) {
3790                                 WL_ERROR(("%s: turn on PHY PLL failed\n",
3791                                           __func__));
3792                                 ASSERT(0);
3793                         }
3794                 } else {
3795                         OR_REG(osh, &regs->clk_ctl_st,
3796                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3797                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3798                                   (CCS_ERSRC_AVAIL_D11PLL |
3799                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3800                                  (CCS_ERSRC_AVAIL_D11PLL |
3801                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3802
3803                         tmp = R_REG(osh, &regs->clk_ctl_st);
3804                         if ((tmp &
3805                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3806                             !=
3807                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3808                                 WL_ERROR(("%s: turn on PHY PLL failed\n",
3809                                           __func__));
3810                                 ASSERT(0);
3811                         }
3812                 }
3813         } else {
3814                 /* Since the PLL may be shared, other cores can still be requesting it;
3815                  * so we'll deassert the request but not wait for status to comply.
3816                  */
3817                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3818                 tmp = R_REG(osh, &regs->clk_ctl_st);
3819         }
3820 }
3821
3822 void wlc_coredisable(wlc_hw_info_t *wlc_hw)
3823 {
3824         bool dev_gone;
3825
3826         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
3827
3828         ASSERT(!wlc_hw->up);
3829
3830         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3831
3832         if (dev_gone)
3833                 return;
3834
3835         if (wlc_hw->noreset)
3836                 return;
3837
3838         /* radio off */
3839         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3840
3841         /* turn off analog core */
3842         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3843
3844         /* turn off PHYPLL to save power */
3845         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3846
3847         /* No need to set wlc->pub->radio_active = OFF
3848          * because this function needs down capability and
3849          * radio_active is designed for BCMNODOWN.
3850          */
3851
3852         /* remove gpio controls */
3853         if (wlc_hw->ucode_dbgsel)
3854                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3855
3856         wlc_hw->clk = false;
3857         si_core_disable(wlc_hw->sih, 0);
3858         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3859 }
3860
3861 /* power both the pll and external oscillator on/off */
3862 void wlc_bmac_xtal(wlc_hw_info_t *wlc_hw, bool want)
3863 {
3864         WL_TRACE(("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want));
3865
3866         /* dont power down if plldown is false or we must poll hw radio disable */
3867         if (!want && wlc_hw->pllreq)
3868                 return;
3869
3870         if (wlc_hw->sih)
3871                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3872
3873         wlc_hw->sbclk = want;
3874         if (!wlc_hw->sbclk) {
3875                 wlc_hw->clk = false;
3876                 if (wlc_hw->band && wlc_hw->band->pi)
3877                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3878         }
3879 }
3880
3881 static void wlc_flushqueues(wlc_info_t *wlc)
3882 {
3883         wlc_hw_info_t *wlc_hw = wlc->hw;
3884         uint i;
3885
3886         wlc->txpend16165war = 0;
3887
3888         /* free any posted tx packets */
3889         for (i = 0; i < NFIFO; i++)
3890                 if (wlc_hw->di[i]) {
3891                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3892                         TXPKTPENDCLR(wlc, i);
3893                         WL_TRACE(("wlc_flushqueues: pktpend fifo %d cleared\n",
3894                                   i));
3895                 }
3896
3897         /* free any posted rx packets */
3898         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3899         if (D11REV_IS(wlc_hw->corerev, 4))
3900                 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3901 }
3902
3903 u16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset)
3904 {
3905         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3906 }
3907
3908 void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v)
3909 {
3910         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3911 }
3912
3913 /* Set a range of shared memory to a value.
3914  * SHM 'offset' needs to be an even address and
3915  * Buffer length 'len' must be an even number of bytes
3916  */
3917 void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v, int len)
3918 {
3919         int i;
3920
3921         /* offset and len need to be even */
3922         ASSERT((offset & 1) == 0);
3923         ASSERT((len & 1) == 0);
3924
3925         if (len <= 0)
3926                 return;
3927
3928         for (i = 0; i < len; i += 2) {
3929                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3930         }
3931 }
3932
3933 static u16
3934 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, u32 sel)
3935 {
3936         d11regs_t *regs = wlc_hw->regs;
3937         volatile u16 *objdata_lo =
3938             (volatile u16 *)(uintptr) & regs->objdata;
3939         volatile u16 *objdata_hi = objdata_lo + 1;
3940         u16 v;
3941
3942         ASSERT((offset & 1) == 0);
3943
3944         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3945         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3946         if (offset & 2) {
3947                 v = R_REG(wlc_hw->osh, objdata_hi);
3948         } else {
3949                 v = R_REG(wlc_hw->osh, objdata_lo);
3950         }
3951
3952         return v;
3953 }
3954
3955 static void
3956 wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, u32 sel)
3957 {
3958         d11regs_t *regs = wlc_hw->regs;
3959         volatile u16 *objdata_lo =
3960             (volatile u16 *)(uintptr) & regs->objdata;
3961         volatile u16 *objdata_hi = objdata_lo + 1;
3962
3963         ASSERT((offset & 1) == 0);
3964
3965         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3966         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3967         if (offset & 2) {
3968                 W_REG(wlc_hw->osh, objdata_hi, v);
3969         } else {
3970                 W_REG(wlc_hw->osh, objdata_lo, v);
3971         }
3972 }
3973
3974 /* Copy a buffer to shared memory of specified type .
3975  * SHM 'offset' needs to be an even address and
3976  * Buffer length 'len' must be an even number of bytes
3977  * 'sel' selects the type of memory
3978  */
3979 void
3980 wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf,
3981                        int len, u32 sel)
3982 {
3983         u16 v;
3984         const u8 *p = (const u8 *)buf;
3985         int i;
3986
3987         /* offset and len need to be even */
3988         ASSERT((offset & 1) == 0);
3989         ASSERT((len & 1) == 0);
3990
3991         if (len <= 0)
3992                 return;
3993
3994         for (i = 0; i < len; i += 2) {
3995                 v = p[i] | (p[i + 1] << 8);
3996                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3997         }
3998 }
3999
4000 /* Copy a piece of shared memory of specified type to a buffer .
4001  * SHM 'offset' needs to be an even address and
4002  * Buffer length 'len' must be an even number of bytes
4003  * 'sel' selects the type of memory
4004  */
4005 void
4006 wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf,
4007                          int len, u32 sel)
4008 {
4009         u16 v;
4010         u8 *p = (u8 *) buf;
4011         int i;
4012
4013         /* offset and len need to be even */
4014         ASSERT((offset & 1) == 0);
4015         ASSERT((len & 1) == 0);
4016
4017         if (len <= 0)
4018                 return;
4019
4020         for (i = 0; i < len; i += 2) {
4021                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
4022                 p[i] = v & 0xFF;
4023                 p[i + 1] = (v >> 8) & 0xFF;
4024         }
4025 }
4026
4027 void wlc_bmac_copyfrom_vars(wlc_hw_info_t *wlc_hw, char **buf, uint *len)
4028 {
4029         WL_TRACE(("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
4030                   wlc_hw->vars_size));
4031
4032         *buf = wlc_hw->vars;
4033         *len = wlc_hw->vars_size;
4034 }
4035
4036 void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, u16 SRL, u16 LRL)
4037 {
4038         wlc_hw->SRL = SRL;
4039         wlc_hw->LRL = LRL;
4040
4041         /* write retry limit to SCR, shouldn't need to suspend */
4042         if (wlc_hw->up) {
4043                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4044                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
4045                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4046                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
4047                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4048                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
4049                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4050                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
4051         }
4052 }
4053
4054 void wlc_bmac_set_noreset(wlc_hw_info_t *wlc_hw, bool noreset_flag)
4055 {
4056         wlc_hw->noreset = noreset_flag;
4057 }
4058
4059 void wlc_bmac_set_ucode_loaded(wlc_hw_info_t *wlc_hw, bool ucode_loaded)
4060 {
4061         wlc_hw->ucode_loaded = ucode_loaded;
4062 }
4063
4064 void wlc_bmac_pllreq(wlc_hw_info_t *wlc_hw, bool set, mbool req_bit)
4065 {
4066         ASSERT(req_bit);
4067
4068         if (set) {
4069                 if (mboolisset(wlc_hw->pllreq, req_bit))
4070                         return;
4071
4072                 mboolset(wlc_hw->pllreq, req_bit);
4073
4074                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4075                         if (!wlc_hw->sbclk) {
4076                                 wlc_bmac_xtal(wlc_hw, ON);
4077                         }
4078                 }
4079         } else {
4080                 if (!mboolisset(wlc_hw->pllreq, req_bit))
4081                         return;
4082
4083                 mboolclr(wlc_hw->pllreq, req_bit);
4084
4085                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4086                         if (wlc_hw->sbclk) {
4087                                 wlc_bmac_xtal(wlc_hw, OFF);
4088                         }
4089                 }
4090         }
4091
4092         return;
4093 }
4094
4095 void wlc_bmac_set_clk(wlc_hw_info_t *wlc_hw, bool on)
4096 {
4097         if (on) {
4098                 /* power up pll and oscillator */
4099                 wlc_bmac_xtal(wlc_hw, ON);
4100
4101                 /* enable core(s), ignore bandlocked
4102                  * Leave with the same band selected as we entered
4103                  */
4104                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
4105         } else {
4106                 /* if already down, must skip the core disable */
4107                 if (wlc_hw->clk) {
4108                         /* disable core(s), ignore bandlocked */
4109                         wlc_coredisable(wlc_hw);
4110                 }
4111                 /* power down pll and oscillator */
4112                 wlc_bmac_xtal(wlc_hw, OFF);
4113         }
4114 }
4115
4116 /* this will be true for all ai chips */
4117 bool wlc_bmac_taclear(wlc_hw_info_t *wlc_hw, bool ta_ok)
4118 {
4119         return true;
4120 }
4121
4122 /* Lower down relevant GPIOs like LED when going down w/o
4123  * doing PCI config cycles or touching interrupts
4124  */
4125 void wlc_gpio_fast_deinit(wlc_hw_info_t *wlc_hw)
4126 {
4127         if ((wlc_hw == NULL) || (wlc_hw->sih == NULL))
4128                 return;
4129
4130         /* Only chips with internal bus or PCIE cores or certain PCI cores
4131          * are able to switch cores w/o disabling interrupts
4132          */
4133         if (!((BUSTYPE(wlc_hw->sih->bustype) == SI_BUS) ||
4134               ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) &&
4135                ((wlc_hw->sih->buscoretype == PCIE_CORE_ID) ||
4136                 (wlc_hw->sih->buscorerev >= 13)))))
4137                 return;
4138
4139         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
4140         return;
4141 }
4142
4143 bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable)
4144 {
4145         /* Do not access Phy registers if core is not up */
4146         if (si_iscoreup(wlc_hw->sih) == false)
4147                 return false;
4148
4149         if (enable) {
4150                 if (PMUCTL_ENAB(wlc_hw->sih)) {
4151                         AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4152                                 ~CCS_FORCEHWREQOFF);
4153                         si_pmu_radio_enable(wlc_hw->sih, true);
4154                 }
4155
4156                 wlc_phy_anacore(wlc_hw->band->pi, ON);
4157                 wlc_phy_switch_radio(wlc_hw->band->pi, ON);
4158
4159                 /* resume d11 core */
4160                 wlc_enable_mac(wlc_hw->wlc);
4161         } else {
4162                 /* suspend d11 core */
4163                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
4164
4165                 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
4166                 wlc_phy_anacore(wlc_hw->band->pi, OFF);
4167
4168                 if (PMUCTL_ENAB(wlc_hw->sih)) {
4169                         si_pmu_radio_enable(wlc_hw->sih, false);
4170                         OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4171                                CCS_FORCEHWREQOFF);
4172                 }
4173         }
4174
4175         return true;
4176 }
4177
4178 u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate)
4179 {
4180         u16 table_ptr;
4181         u8 phy_rate, index;
4182
4183         /* get the phy specific rate encoding for the PLCP SIGNAL field */
4184         /* XXX4321 fixup needed ? */
4185         if (IS_OFDM(rate))
4186                 table_ptr = M_RT_DIRMAP_A;
4187         else
4188                 table_ptr = M_RT_DIRMAP_B;
4189
4190         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4191          * the index into the rate table.
4192          */
4193         phy_rate = rate_info[rate] & RATE_MASK;
4194         index = phy_rate & 0xf;
4195
4196         /* Find the SHM pointer to the rate table entry by looking in the
4197          * Direct-map Table
4198          */
4199         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
4200 }
4201
4202 void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val)
4203 {
4204         wlc_phy_txpwr_percent_set(wlc_hw->band->pi, val);
4205 }
4206
4207 void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, u32 antsel_avail)
4208 {
4209         wlc_hw->antsel_avail = antsel_avail;
4210 }