2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/kernel.h>
19 #include <linux/string.h>
24 #include <bcmendian.h>
34 #define DMA_ERROR(args) \
36 if (!(*di->msg_level & 1)) \
41 #define DMA_TRACE(args) \
43 if (!(*di->msg_level & 2)) \
49 #define DMA_ERROR(args)
50 #define DMA_TRACE(args)
53 #define DMA_NONE(args)
55 #define d32txregs dregs.d32_u.txregs_32
56 #define d32rxregs dregs.d32_u.rxregs_32
57 #define txd32 dregs.d32_u.txd_32
58 #define rxd32 dregs.d32_u.rxd_32
60 #define d64txregs dregs.d64_u.txregs_64
61 #define d64rxregs dregs.d64_u.rxregs_64
62 #define txd64 dregs.d64_u.txd_64
63 #define rxd64 dregs.d64_u.rxd_64
65 /* default dma message level (if input msg_level pointer is null in dma_attach()) */
66 static uint dma_msg_level;
68 #define MAXNAMEL 8 /* 8 char names */
70 #define DI_INFO(dmah) ((dma_info_t *)dmah)
72 /* dma engine software state */
73 typedef struct dma_info {
74 struct hnddma_pub hnddma; /* exported structure, don't use hnddma_t,
75 * which could be const
77 uint *msg_level; /* message level pointer */
78 char name[MAXNAMEL]; /* callers name for diag msgs */
80 void *osh; /* os handle */
81 si_t *sih; /* sb handle */
83 bool dma64; /* this dma engine is operating in 64-bit mode */
84 bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
88 dma32regs_t *txregs_32; /* 32-bit dma tx engine registers */
89 dma32regs_t *rxregs_32; /* 32-bit dma rx engine registers */
90 dma32dd_t *txd_32; /* pointer to dma32 tx descriptor ring */
91 dma32dd_t *rxd_32; /* pointer to dma32 rx descriptor ring */
94 dma64regs_t *txregs_64; /* 64-bit dma tx engine registers */
95 dma64regs_t *rxregs_64; /* 64-bit dma rx engine registers */
96 dma64dd_t *txd_64; /* pointer to dma64 tx descriptor ring */
97 dma64dd_t *rxd_64; /* pointer to dma64 rx descriptor ring */
101 u16 dmadesc_align; /* alignment requirement for dma descriptors */
103 u16 ntxd; /* # tx descriptors tunable */
104 u16 txin; /* index of next descriptor to reclaim */
105 u16 txout; /* index of next descriptor to post */
106 void **txp; /* pointer to parallel array of pointers to packets */
107 osldma_t *tx_dmah; /* DMA TX descriptor ring handle */
108 hnddma_seg_map_t *txp_dmah; /* DMA MAP meta-data handle */
109 dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */
110 dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */
111 u16 txdalign; /* #bytes added to alloc'd mem to align txd */
112 u32 txdalloc; /* #bytes allocated for the ring */
113 u32 xmtptrbase; /* When using unaligned descriptors, the ptr register
114 * is not just an index, it needs all 13 bits to be
115 * an offset from the addr register.
118 u16 nrxd; /* # rx descriptors tunable */
119 u16 rxin; /* index of next descriptor to reclaim */
120 u16 rxout; /* index of next descriptor to post */
121 void **rxp; /* pointer to parallel array of pointers to packets */
122 osldma_t *rx_dmah; /* DMA RX descriptor ring handle */
123 hnddma_seg_map_t *rxp_dmah; /* DMA MAP meta-data handle */
124 dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */
125 dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */
126 u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */
127 u32 rxdalloc; /* #bytes allocated for the ring */
128 u32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */
131 u16 rxbufsize; /* rx buffer size in bytes,
132 * not including the extra headroom
134 uint rxextrahdrroom; /* extra rx headroom, reverseved to assist upper stack
135 * e.g. some rx pkt buffers will be bridged to tx side
136 * without byte copying. The extra headroom needs to be
137 * large enough to fit txheader needs.
138 * Some dongle driver may not need it.
140 uint nrxpost; /* # rx buffers to keep posted */
141 uint rxoffset; /* rxcontrol offset */
142 uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
143 uint ddoffsethigh; /* high 32 bits */
144 uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
145 uint dataoffsethigh; /* high 32 bits */
146 bool aligndesc_4k; /* descriptor base need to be aligned or not */
150 * If BCMDMA32 is defined, hnddma will support both 32-bit and 64-bit DMA engines.
151 * Otherwise it will support only 64-bit.
153 * DMA32_ENAB indicates whether hnddma is compiled with support for 32-bit DMA engines.
154 * DMA64_ENAB indicates whether hnddma is compiled with support for 64-bit DMA engines.
156 * DMA64_MODE indicates whether the current DMA engine is running as 64-bit.
159 #define DMA32_ENAB(di) 1
160 #define DMA64_ENAB(di) 1
161 #define DMA64_MODE(di) ((di)->dma64)
162 #else /* !BCMDMA32 */
163 #define DMA32_ENAB(di) 0
164 #define DMA64_ENAB(di) 1
165 #define DMA64_MODE(di) 1
166 #endif /* !BCMDMA32 */
168 /* DMA Scatter-gather list is supported. Note this is limited to TX direction only */
169 #ifdef BCMDMASGLISTOSL
170 #define DMASGLIST_ENAB TRUE
172 #define DMASGLIST_ENAB FALSE
173 #endif /* BCMDMASGLISTOSL */
175 /* descriptor bumping macros */
176 #define XXD(x, n) ((x) & ((n) - 1)) /* faster than %, but n must be power of 2 */
177 #define TXD(x) XXD((x), di->ntxd)
178 #define RXD(x) XXD((x), di->nrxd)
179 #define NEXTTXD(i) TXD((i) + 1)
180 #define PREVTXD(i) TXD((i) - 1)
181 #define NEXTRXD(i) RXD((i) + 1)
182 #define PREVRXD(i) RXD((i) - 1)
184 #define NTXDACTIVE(h, t) TXD((t) - (h))
185 #define NRXDACTIVE(h, t) RXD((t) - (h))
187 /* macros to convert between byte offsets and indexes */
188 #define B2I(bytes, type) ((bytes) / sizeof(type))
189 #define I2B(index, type) ((index) * sizeof(type))
191 #define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
192 #define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
194 #define PCI64ADDR_HIGH 0x80000000 /* address[63] */
195 #define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
197 /* Common prototypes */
198 static bool _dma_isaddrext(dma_info_t *di);
199 static bool _dma_descriptor_align(dma_info_t *di);
200 static bool _dma_alloc(dma_info_t *di, uint direction);
201 static void _dma_detach(dma_info_t *di);
202 static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa);
203 static void _dma_rxinit(dma_info_t *di);
204 static void *_dma_rx(dma_info_t *di);
205 static bool _dma_rxfill(dma_info_t *di);
206 static void _dma_rxreclaim(dma_info_t *di);
207 static void _dma_rxenable(dma_info_t *di);
208 static void *_dma_getnextrxp(dma_info_t *di, bool forceall);
209 static void _dma_rx_param_get(dma_info_t *di, u16 *rxoffset,
212 static void _dma_txblock(dma_info_t *di);
213 static void _dma_txunblock(dma_info_t *di);
214 static uint _dma_txactive(dma_info_t *di);
215 static uint _dma_rxactive(dma_info_t *di);
216 static uint _dma_txpending(dma_info_t *di);
217 static uint _dma_txcommitted(dma_info_t *di);
219 static void *_dma_peeknexttxp(dma_info_t *di);
220 static void *_dma_peeknextrxp(dma_info_t *di);
221 static uintptr _dma_getvar(dma_info_t *di, const char *name);
222 static void _dma_counterreset(dma_info_t *di);
223 static void _dma_fifoloopbackenable(dma_info_t *di);
224 static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags);
225 static u8 dma_align_sizetobits(uint size);
226 static void *dma_ringalloc(osl_t *osh, u32 boundary, uint size,
227 u16 *alignbits, uint *alloced,
228 dmaaddr_t *descpa, osldma_t **dmah);
230 /* Prototypes for 32-bit routines */
231 static bool dma32_alloc(dma_info_t *di, uint direction);
232 static bool dma32_txreset(dma_info_t *di);
233 static bool dma32_rxreset(dma_info_t *di);
234 static bool dma32_txsuspendedidle(dma_info_t *di);
235 static int dma32_txfast(dma_info_t *di, void *p0, bool commit);
236 static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range);
237 static void *dma32_getnextrxp(dma_info_t *di, bool forceall);
238 static void dma32_txrotate(dma_info_t *di);
239 static bool dma32_rxidle(dma_info_t *di);
240 static void dma32_txinit(dma_info_t *di);
241 static bool dma32_txenabled(dma_info_t *di);
242 static void dma32_txsuspend(dma_info_t *di);
243 static void dma32_txresume(dma_info_t *di);
244 static bool dma32_txsuspended(dma_info_t *di);
245 static void dma32_txreclaim(dma_info_t *di, txd_range_t range);
246 static bool dma32_txstopped(dma_info_t *di);
247 static bool dma32_rxstopped(dma_info_t *di);
248 static bool dma32_rxenabled(dma_info_t *di);
250 static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs);
252 /* Prototypes for 64-bit routines */
253 static bool dma64_alloc(dma_info_t *di, uint direction);
254 static bool dma64_txreset(dma_info_t *di);
255 static bool dma64_rxreset(dma_info_t *di);
256 static bool dma64_txsuspendedidle(dma_info_t *di);
257 static int dma64_txfast(dma_info_t *di, void *p0, bool commit);
258 static int dma64_txunframed(dma_info_t *di, void *p0, uint len, bool commit);
259 static void *dma64_getpos(dma_info_t *di, bool direction);
260 static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range);
261 static void *dma64_getnextrxp(dma_info_t *di, bool forceall);
262 static void dma64_txrotate(dma_info_t *di);
264 static bool dma64_rxidle(dma_info_t *di);
265 static void dma64_txinit(dma_info_t *di);
266 static bool dma64_txenabled(dma_info_t *di);
267 static void dma64_txsuspend(dma_info_t *di);
268 static void dma64_txresume(dma_info_t *di);
269 static bool dma64_txsuspended(dma_info_t *di);
270 static void dma64_txreclaim(dma_info_t *di, txd_range_t range);
271 static bool dma64_txstopped(dma_info_t *di);
272 static bool dma64_rxstopped(dma_info_t *di);
273 static bool dma64_rxenabled(dma_info_t *di);
274 static bool _dma64_addrext(osl_t *osh, dma64regs_t *dma64regs);
276 static inline u32 parity32(u32 data);
278 const di_fcn_t dma64proc = {
279 (di_detach_t) _dma_detach,
280 (di_txinit_t) dma64_txinit,
281 (di_txreset_t) dma64_txreset,
282 (di_txenabled_t) dma64_txenabled,
283 (di_txsuspend_t) dma64_txsuspend,
284 (di_txresume_t) dma64_txresume,
285 (di_txsuspended_t) dma64_txsuspended,
286 (di_txsuspendedidle_t) dma64_txsuspendedidle,
287 (di_txfast_t) dma64_txfast,
288 (di_txunframed_t) dma64_txunframed,
289 (di_getpos_t) dma64_getpos,
290 (di_txstopped_t) dma64_txstopped,
291 (di_txreclaim_t) dma64_txreclaim,
292 (di_getnexttxp_t) dma64_getnexttxp,
293 (di_peeknexttxp_t) _dma_peeknexttxp,
294 (di_txblock_t) _dma_txblock,
295 (di_txunblock_t) _dma_txunblock,
296 (di_txactive_t) _dma_txactive,
297 (di_txrotate_t) dma64_txrotate,
299 (di_rxinit_t) _dma_rxinit,
300 (di_rxreset_t) dma64_rxreset,
301 (di_rxidle_t) dma64_rxidle,
302 (di_rxstopped_t) dma64_rxstopped,
303 (di_rxenable_t) _dma_rxenable,
304 (di_rxenabled_t) dma64_rxenabled,
306 (di_rxfill_t) _dma_rxfill,
307 (di_rxreclaim_t) _dma_rxreclaim,
308 (di_getnextrxp_t) _dma_getnextrxp,
309 (di_peeknextrxp_t) _dma_peeknextrxp,
310 (di_rxparam_get_t) _dma_rx_param_get,
312 (di_fifoloopbackenable_t) _dma_fifoloopbackenable,
313 (di_getvar_t) _dma_getvar,
314 (di_counterreset_t) _dma_counterreset,
315 (di_ctrlflags_t) _dma_ctrlflags,
319 (di_rxactive_t) _dma_rxactive,
320 (di_txpending_t) _dma_txpending,
321 (di_txcommitted_t) _dma_txcommitted,
325 static const di_fcn_t dma32proc = {
326 (di_detach_t) _dma_detach,
327 (di_txinit_t) dma32_txinit,
328 (di_txreset_t) dma32_txreset,
329 (di_txenabled_t) dma32_txenabled,
330 (di_txsuspend_t) dma32_txsuspend,
331 (di_txresume_t) dma32_txresume,
332 (di_txsuspended_t) dma32_txsuspended,
333 (di_txsuspendedidle_t) dma32_txsuspendedidle,
334 (di_txfast_t) dma32_txfast,
337 (di_txstopped_t) dma32_txstopped,
338 (di_txreclaim_t) dma32_txreclaim,
339 (di_getnexttxp_t) dma32_getnexttxp,
340 (di_peeknexttxp_t) _dma_peeknexttxp,
341 (di_txblock_t) _dma_txblock,
342 (di_txunblock_t) _dma_txunblock,
343 (di_txactive_t) _dma_txactive,
344 (di_txrotate_t) dma32_txrotate,
346 (di_rxinit_t) _dma_rxinit,
347 (di_rxreset_t) dma32_rxreset,
348 (di_rxidle_t) dma32_rxidle,
349 (di_rxstopped_t) dma32_rxstopped,
350 (di_rxenable_t) _dma_rxenable,
351 (di_rxenabled_t) dma32_rxenabled,
353 (di_rxfill_t) _dma_rxfill,
354 (di_rxreclaim_t) _dma_rxreclaim,
355 (di_getnextrxp_t) _dma_getnextrxp,
356 (di_peeknextrxp_t) _dma_peeknextrxp,
357 (di_rxparam_get_t) _dma_rx_param_get,
359 (di_fifoloopbackenable_t) _dma_fifoloopbackenable,
360 (di_getvar_t) _dma_getvar,
361 (di_counterreset_t) _dma_counterreset,
362 (di_ctrlflags_t) _dma_ctrlflags,
366 (di_rxactive_t) _dma_rxactive,
367 (di_txpending_t) _dma_txpending,
368 (di_txcommitted_t) _dma_txcommitted,
372 hnddma_t *dma_attach(osl_t *osh, char *name, si_t *sih, void *dmaregstx,
373 void *dmaregsrx, uint ntxd, uint nrxd, uint rxbufsize,
374 int rxextheadroom, uint nrxpost, uint rxoffset,
380 /* allocate private info structure */
381 di = MALLOC(osh, sizeof(dma_info_t));
384 printf("dma_attach: out of memory, malloced %d bytes\n",
390 bzero((char *)di, sizeof(dma_info_t));
392 di->msg_level = msg_level ? msg_level : &dma_msg_level;
394 /* old chips w/o sb is no longer supported */
399 ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
403 /* check arguments */
404 ASSERT(ISPOWEROF2(ntxd));
405 ASSERT(ISPOWEROF2(nrxd));
408 ASSERT(dmaregsrx == NULL);
410 ASSERT(dmaregstx == NULL);
412 /* init dma reg pointer */
413 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
414 ASSERT(ntxd <= D64MAXDD);
415 ASSERT(nrxd <= D64MAXDD);
416 di->d64txregs = (dma64regs_t *) dmaregstx;
417 di->d64rxregs = (dma64regs_t *) dmaregsrx;
418 di->hnddma.di_fn = (const di_fcn_t *)&dma64proc;
419 } else if (DMA32_ENAB(di)) {
420 ASSERT(ntxd <= D32MAXDD);
421 ASSERT(nrxd <= D32MAXDD);
422 di->d32txregs = (dma32regs_t *) dmaregstx;
423 di->d32rxregs = (dma32regs_t *) dmaregsrx;
424 di->hnddma.di_fn = (const di_fcn_t *)&dma32proc;
426 DMA_ERROR(("dma_attach: driver doesn't support 32-bit DMA\n"));
431 /* Default flags (which can be changed by the driver calling dma_ctrlflags
432 * before enable): For backwards compatibility both Rx Overflow Continue
433 * and Parity are DISABLED.
436 di->hnddma.di_fn->ctrlflags(&di->hnddma, DMA_CTRL_ROC | DMA_CTRL_PEN,
439 DMA_TRACE(("%s: dma_attach: %s osh %p flags 0x%x ntxd %d nrxd %d rxbufsize %d " "rxextheadroom %d nrxpost %d rxoffset %d dmaregstx %p dmaregsrx %p\n", name, (DMA64_MODE(di) ? "DMA64" : "DMA32"), osh, di->hnddma.dmactrlflags, ntxd, nrxd, rxbufsize, rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx));
441 /* make a private copy of our callers name */
442 strncpy(di->name, name, MAXNAMEL);
443 di->name[MAXNAMEL - 1] = '\0';
449 di->ntxd = (u16) ntxd;
450 di->nrxd = (u16) nrxd;
452 /* the actual dma size doesn't include the extra headroom */
454 (rxextheadroom == -1) ? BCMEXTRAHDROOM : rxextheadroom;
455 if (rxbufsize > BCMEXTRAHDROOM)
456 di->rxbufsize = (u16) (rxbufsize - di->rxextrahdrroom);
458 di->rxbufsize = (u16) rxbufsize;
460 di->nrxpost = (u16) nrxpost;
461 di->rxoffset = (u8) rxoffset;
464 * figure out the DMA physical address offset for dd and data
465 * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
466 * Other bus: use zero
467 * SI_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
470 di->dataoffsetlow = 0;
471 /* for pci bus, add offset */
472 if (sih->bustype == PCI_BUS) {
473 if ((sih->buscoretype == PCIE_CORE_ID) && DMA64_MODE(di)) {
474 /* pcie with DMA64 */
476 di->ddoffsethigh = SI_PCIE_DMA_H32;
478 /* pci(DMA32/DMA64) or pcie with DMA32 */
479 di->ddoffsetlow = SI_PCI_DMA;
480 di->ddoffsethigh = 0;
482 di->dataoffsetlow = di->ddoffsetlow;
483 di->dataoffsethigh = di->ddoffsethigh;
485 #if defined(__mips__) && defined(IL_BIGENDIAN)
486 di->dataoffsetlow = di->dataoffsetlow + SI_SDRAM_SWAPPED;
487 #endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
488 /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
489 if ((si_coreid(sih) == SDIOD_CORE_ID)
490 && ((si_corerev(sih) > 0) && (si_corerev(sih) <= 2)))
492 else if ((si_coreid(sih) == I2S_CORE_ID) &&
493 ((si_corerev(sih) == 0) || (si_corerev(sih) == 1)))
496 di->addrext = _dma_isaddrext(di);
498 /* does the descriptors need to be aligned and if yes, on 4K/8K or not */
499 di->aligndesc_4k = _dma_descriptor_align(di);
500 if (di->aligndesc_4k) {
501 if (DMA64_MODE(di)) {
502 di->dmadesc_align = D64RINGALIGN_BITS;
503 if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
504 /* for smaller dd table, HW relax the alignment requirement */
505 di->dmadesc_align = D64RINGALIGN_BITS - 1;
508 di->dmadesc_align = D32RINGALIGN_BITS;
510 di->dmadesc_align = 4; /* 16 byte alignment */
512 DMA_NONE(("DMA descriptor align_needed %d, align %d\n",
513 di->aligndesc_4k, di->dmadesc_align));
515 /* allocate tx packet pointer vector */
517 size = ntxd * sizeof(void *);
518 di->txp = MALLOC(osh, size);
519 if (di->txp == NULL) {
520 DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
523 bzero((char *)di->txp, size);
526 /* allocate rx packet pointer vector */
528 size = nrxd * sizeof(void *);
529 di->rxp = MALLOC(osh, size);
530 if (di->rxp == NULL) {
531 DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
534 bzero((char *)di->rxp, size);
537 /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
539 if (!_dma_alloc(di, DMA_TX))
543 /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
545 if (!_dma_alloc(di, DMA_RX))
549 if ((di->ddoffsetlow != 0) && !di->addrext) {
550 if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) {
551 DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->txdpa)));
554 if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) {
555 DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->rxdpa)));
560 DMA_TRACE(("ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x dataoffsethigh " "0x%x addrext %d\n", di->ddoffsetlow, di->ddoffsethigh, di->dataoffsetlow, di->dataoffsethigh, di->addrext));
562 /* allocate DMA mapping vectors */
563 if (DMASGLIST_ENAB) {
565 size = ntxd * sizeof(hnddma_seg_map_t);
566 di->txp_dmah = (hnddma_seg_map_t *) MALLOC(osh, size);
567 if (di->txp_dmah == NULL)
569 bzero((char *)di->txp_dmah, size);
573 size = nrxd * sizeof(hnddma_seg_map_t);
574 di->rxp_dmah = (hnddma_seg_map_t *) MALLOC(osh, size);
575 if (di->rxp_dmah == NULL)
577 bzero((char *)di->rxp_dmah, size);
581 return (hnddma_t *) di;
588 /* init the tx or rx descriptor */
590 dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx,
591 u32 *flags, u32 bufcount)
593 /* dma32 uses 32-bit control to fit both flags and bufcounter */
594 *flags = *flags | (bufcount & CTRL_BC_MASK);
596 if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
597 W_SM(&ddring[outidx].addr,
598 BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
599 W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags));
601 /* address extension */
604 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
605 PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
607 *flags |= (ae << CTRL_AE_SHIFT);
608 W_SM(&ddring[outidx].addr,
609 BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
610 W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags));
614 /* Check for odd number of 1's */
615 static inline u32 parity32(u32 data)
626 #define DMA64_DD_PARITY(dd) parity32((dd)->addrlow ^ (dd)->addrhigh ^ (dd)->ctrl1 ^ (dd)->ctrl2)
629 dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
630 u32 *flags, u32 bufcount)
632 u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
634 /* PCI bus with big(>1G) physical address, use address extension */
635 #if defined(__mips__) && defined(IL_BIGENDIAN)
636 if ((di->dataoffsetlow == SI_SDRAM_SWAPPED)
637 || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
639 if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
640 #endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
641 ASSERT((PHYSADDRHI(pa) & PCI64ADDR_HIGH) == 0);
643 W_SM(&ddring[outidx].addrlow,
644 BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
645 W_SM(&ddring[outidx].addrhigh,
646 BUS_SWAP32(PHYSADDRHI(pa) + di->dataoffsethigh));
647 W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
648 W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
650 /* address extension for 32-bit PCI */
654 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
655 PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
656 ASSERT(PHYSADDRHI(pa) == 0);
658 ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
659 W_SM(&ddring[outidx].addrlow,
660 BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
661 W_SM(&ddring[outidx].addrhigh,
662 BUS_SWAP32(0 + di->dataoffsethigh));
663 W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
664 W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
666 if (di->hnddma.dmactrlflags & DMA_CTRL_PEN) {
667 if (DMA64_DD_PARITY(&ddring[outidx])) {
668 W_SM(&ddring[outidx].ctrl2,
669 BUS_SWAP32(ctrl2 | D64_CTRL2_PARITY));
674 static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs)
678 OR_REG(osh, &dma32regs->control, XC_AE);
679 w = R_REG(osh, &dma32regs->control);
680 AND_REG(osh, &dma32regs->control, ~XC_AE);
681 return (w & XC_AE) == XC_AE;
684 static bool _dma_alloc(dma_info_t *di, uint direction)
686 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
687 return dma64_alloc(di, direction);
688 } else if (DMA32_ENAB(di)) {
689 return dma32_alloc(di, direction);
694 /* !! may be called with core in reset */
695 static void _dma_detach(dma_info_t *di)
698 DMA_TRACE(("%s: dma_detach\n", di->name));
700 /* shouldn't be here if descriptors are unreclaimed */
701 ASSERT(di->txin == di->txout);
702 ASSERT(di->rxin == di->rxout);
704 /* free dma descriptor rings */
705 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
707 DMA_FREE_CONSISTENT(di->osh,
709 di->txdalign), di->txdalloc,
710 (di->txdpaorig), &di->tx_dmah);
712 DMA_FREE_CONSISTENT(di->osh,
714 di->rxdalign), di->rxdalloc,
715 (di->rxdpaorig), &di->rx_dmah);
716 } else if (DMA32_ENAB(di)) {
718 DMA_FREE_CONSISTENT(di->osh,
720 di->txdalign), di->txdalloc,
721 (di->txdpaorig), &di->tx_dmah);
723 DMA_FREE_CONSISTENT(di->osh,
725 di->rxdalign), di->rxdalloc,
726 (di->rxdpaorig), &di->rx_dmah);
730 /* free packet pointer vectors */
732 MFREE(di->osh, (void *)di->txp, (di->ntxd * sizeof(void *)));
734 MFREE(di->osh, (void *)di->rxp, (di->nrxd * sizeof(void *)));
736 /* free tx packet DMA handles */
738 MFREE(di->osh, (void *)di->txp_dmah,
739 di->ntxd * sizeof(hnddma_seg_map_t));
741 /* free rx packet DMA handles */
743 MFREE(di->osh, (void *)di->rxp_dmah,
744 di->nrxd * sizeof(hnddma_seg_map_t));
746 /* free our private info structure */
747 MFREE(di->osh, (void *)di, sizeof(dma_info_t));
751 static bool _dma_descriptor_align(dma_info_t *di)
753 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
756 /* Check to see if the descriptors need to be aligned on 4K/8K or not */
757 if (di->d64txregs != NULL) {
758 W_REG(di->osh, &di->d64txregs->addrlow, 0xff0);
759 addrl = R_REG(di->osh, &di->d64txregs->addrlow);
762 } else if (di->d64rxregs != NULL) {
763 W_REG(di->osh, &di->d64rxregs->addrlow, 0xff0);
764 addrl = R_REG(di->osh, &di->d64rxregs->addrlow);
772 /* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
773 static bool _dma_isaddrext(dma_info_t *di)
775 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
776 /* DMA64 supports full 32- or 64-bit operation. AE is always valid */
778 /* not all tx or rx channel are available */
779 if (di->d64txregs != NULL) {
780 if (!_dma64_addrext(di->osh, di->d64txregs)) {
781 DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have AE set\n", di->name));
785 } else if (di->d64rxregs != NULL) {
786 if (!_dma64_addrext(di->osh, di->d64rxregs)) {
787 DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have AE set\n", di->name));
793 } else if (DMA32_ENAB(di)) {
795 return _dma32_addrext(di->osh, di->d32txregs);
796 else if (di->d32rxregs)
797 return _dma32_addrext(di->osh, di->d32rxregs);
804 /* initialize descriptor table base address */
805 static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
807 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
808 if (!di->aligndesc_4k) {
809 if (direction == DMA_TX)
810 di->xmtptrbase = PHYSADDRLO(pa);
812 di->rcvptrbase = PHYSADDRLO(pa);
815 if ((di->ddoffsetlow == 0)
816 || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
817 if (direction == DMA_TX) {
818 W_REG(di->osh, &di->d64txregs->addrlow,
819 (PHYSADDRLO(pa) + di->ddoffsetlow));
820 W_REG(di->osh, &di->d64txregs->addrhigh,
821 (PHYSADDRHI(pa) + di->ddoffsethigh));
823 W_REG(di->osh, &di->d64rxregs->addrlow,
824 (PHYSADDRLO(pa) + di->ddoffsetlow));
825 W_REG(di->osh, &di->d64rxregs->addrhigh,
826 (PHYSADDRHI(pa) + di->ddoffsethigh));
829 /* DMA64 32bits address extension */
832 ASSERT(PHYSADDRHI(pa) == 0);
834 /* shift the high bit(s) from pa to ae */
835 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
836 PCI32ADDR_HIGH_SHIFT;
837 PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
839 if (direction == DMA_TX) {
840 W_REG(di->osh, &di->d64txregs->addrlow,
841 (PHYSADDRLO(pa) + di->ddoffsetlow));
842 W_REG(di->osh, &di->d64txregs->addrhigh,
844 SET_REG(di->osh, &di->d64txregs->control,
845 D64_XC_AE, (ae << D64_XC_AE_SHIFT));
847 W_REG(di->osh, &di->d64rxregs->addrlow,
848 (PHYSADDRLO(pa) + di->ddoffsetlow));
849 W_REG(di->osh, &di->d64rxregs->addrhigh,
851 SET_REG(di->osh, &di->d64rxregs->control,
852 D64_RC_AE, (ae << D64_RC_AE_SHIFT));
856 } else if (DMA32_ENAB(di)) {
857 ASSERT(PHYSADDRHI(pa) == 0);
858 if ((di->ddoffsetlow == 0)
859 || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
860 if (direction == DMA_TX)
861 W_REG(di->osh, &di->d32txregs->addr,
862 (PHYSADDRLO(pa) + di->ddoffsetlow));
864 W_REG(di->osh, &di->d32rxregs->addr,
865 (PHYSADDRLO(pa) + di->ddoffsetlow));
867 /* dma32 address extension */
871 /* shift the high bit(s) from pa to ae */
872 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
873 PCI32ADDR_HIGH_SHIFT;
874 PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
876 if (direction == DMA_TX) {
877 W_REG(di->osh, &di->d32txregs->addr,
878 (PHYSADDRLO(pa) + di->ddoffsetlow));
879 SET_REG(di->osh, &di->d32txregs->control, XC_AE,
882 W_REG(di->osh, &di->d32rxregs->addr,
883 (PHYSADDRLO(pa) + di->ddoffsetlow));
884 SET_REG(di->osh, &di->d32rxregs->control, RC_AE,
892 static void _dma_fifoloopbackenable(dma_info_t *di)
894 DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
896 if (DMA64_ENAB(di) && DMA64_MODE(di))
897 OR_REG(di->osh, &di->d64txregs->control, D64_XC_LE);
898 else if (DMA32_ENAB(di))
899 OR_REG(di->osh, &di->d32txregs->control, XC_LE);
904 static void _dma_rxinit(dma_info_t *di)
906 DMA_TRACE(("%s: dma_rxinit\n", di->name));
911 di->rxin = di->rxout = 0;
913 /* clear rx descriptor ring */
914 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
915 BZERO_SM((void *)di->rxd64,
916 (di->nrxd * sizeof(dma64dd_t)));
918 /* DMA engine with out alignment requirement requires table to be inited
919 * before enabling the engine
921 if (!di->aligndesc_4k)
922 _dma_ddtable_init(di, DMA_RX, di->rxdpa);
926 if (di->aligndesc_4k)
927 _dma_ddtable_init(di, DMA_RX, di->rxdpa);
928 } else if (DMA32_ENAB(di)) {
929 BZERO_SM((void *)di->rxd32,
930 (di->nrxd * sizeof(dma32dd_t)));
932 _dma_ddtable_init(di, DMA_RX, di->rxdpa);
937 static void _dma_rxenable(dma_info_t *di)
939 uint dmactrlflags = di->hnddma.dmactrlflags;
941 DMA_TRACE(("%s: dma_rxenable\n", di->name));
943 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
945 (R_REG(di->osh, &di->d64rxregs->control) & D64_RC_AE) |
948 if ((dmactrlflags & DMA_CTRL_PEN) == 0)
949 control |= D64_RC_PD;
951 if (dmactrlflags & DMA_CTRL_ROC)
952 control |= D64_RC_OC;
954 W_REG(di->osh, &di->d64rxregs->control,
955 ((di->rxoffset << D64_RC_RO_SHIFT) | control));
956 } else if (DMA32_ENAB(di)) {
958 (R_REG(di->osh, &di->d32rxregs->control) & RC_AE) | RC_RE;
960 if ((dmactrlflags & DMA_CTRL_PEN) == 0)
963 if (dmactrlflags & DMA_CTRL_ROC)
966 W_REG(di->osh, &di->d32rxregs->control,
967 ((di->rxoffset << RC_RO_SHIFT) | control));
973 _dma_rx_param_get(dma_info_t *di, u16 *rxoffset, u16 *rxbufsize)
975 /* the normal values fit into 16 bits */
976 *rxoffset = (u16) di->rxoffset;
977 *rxbufsize = (u16) di->rxbufsize;
980 /* !! rx entry routine
981 * returns a pointer to the next frame received, or NULL if there are no more
982 * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is supported
984 * otherwise, it's treated as giant pkt and will be tossed.
985 * The DMA scattering starts with normal DMA header, followed by first buffer data.
986 * After it reaches the max size of buffer, the data continues in next DMA descriptor
987 * buffer WITHOUT DMA header
989 static void *BCMFASTPATH _dma_rx(dma_info_t *di)
991 void *p, *head, *tail;
997 head = _dma_getnextrxp(di, FALSE);
1001 len = ltoh16(*(u16 *) (PKTDATA(head)));
1002 DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
1004 #if defined(__mips__)
1006 while (!(len = *(u16 *) OSL_UNCACHED(PKTDATA(head))))
1009 *(u16 *) PKTDATA(head) = htol16((u16) len);
1011 #endif /* defined(__mips__) */
1013 /* set actual length */
1014 pkt_len = min((di->rxoffset + len), di->rxbufsize);
1015 PKTSETLEN(head, pkt_len);
1016 resid = len - (di->rxbufsize - di->rxoffset);
1018 /* check for single or multi-buffer rx */
1021 while ((resid > 0) && (p = _dma_getnextrxp(di, FALSE))) {
1022 PKTSETNEXT(tail, p);
1023 pkt_len = min(resid, (int)di->rxbufsize);
1024 PKTSETLEN(p, pkt_len);
1027 resid -= di->rxbufsize;
1034 cur = (DMA64_ENAB(di) && DMA64_MODE(di)) ?
1035 B2I(((R_REG(di->osh, &di->d64rxregs->status0) &
1037 di->rcvptrbase) & D64_RS0_CD_MASK,
1038 dma64dd_t) : B2I(R_REG(di->osh,
1040 status) & RS_CD_MASK,
1042 DMA_ERROR(("_dma_rx, rxin %d rxout %d, hw_curr %d\n",
1043 di->rxin, di->rxout, cur));
1047 if ((di->hnddma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
1048 DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n",
1050 PKTFREE(di->osh, head, FALSE);
1051 di->hnddma.rxgiants++;
1059 /* post receive buffers
1060 * return FALSE is refill failed completely and ring is empty
1061 * this will stall the rx dma and user might want to call rxfill again asap
1062 * This unlikely happens on memory-rich NIC, but often on memory-constrained dongle
1064 static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
1072 uint extra_offset = 0;
1078 * Determine how many receive buffers we're lacking
1079 * from the full complement, allocate, initialize,
1080 * and post them, then update the chip rx lastdscr.
1086 n = di->nrxpost - NRXDACTIVE(rxin, rxout);
1088 DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
1090 if (di->rxbufsize > BCMEXTRAHDROOM)
1091 extra_offset = di->rxextrahdrroom;
1093 for (i = 0; i < n; i++) {
1094 /* the di->rxbufsize doesn't include the extra headroom, we need to add it to the
1095 size to be allocated
1098 p = osl_pktget(di->osh, di->rxbufsize + extra_offset);
1101 DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n",
1104 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1105 if (dma64_rxidle(di)) {
1106 DMA_ERROR(("%s: rxfill64: ring is empty !\n", di->name));
1109 } else if (DMA32_ENAB(di)) {
1110 if (dma32_rxidle(di)) {
1111 DMA_ERROR(("%s: rxfill32: ring is empty !\n", di->name));
1117 di->hnddma.rxnobuf++;
1120 /* reserve an extra headroom, if applicable */
1122 PKTPULL(p, extra_offset);
1124 /* Do a cached write instead of uncached write since DMA_MAP
1125 * will flush the cache.
1127 *(u32 *) (PKTDATA(p)) = 0;
1130 bzero(&di->rxp_dmah[rxout], sizeof(hnddma_seg_map_t));
1132 pa = DMA_MAP(di->osh, PKTDATA(p),
1133 di->rxbufsize, DMA_RX, p, &di->rxp_dmah[rxout]);
1135 ASSERT(IS_ALIGNED(PHYSADDRLO(pa), 4));
1137 /* save the free packet pointer */
1138 ASSERT(di->rxp[rxout] == NULL);
1141 /* reset flags for each descriptor */
1143 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1144 if (rxout == (di->nrxd - 1))
1145 flags = D64_CTRL1_EOT;
1147 dma64_dd_upd(di, di->rxd64, pa, rxout, &flags,
1149 } else if (DMA32_ENAB(di)) {
1150 if (rxout == (di->nrxd - 1))
1153 ASSERT(PHYSADDRHI(pa) == 0);
1154 dma32_dd_upd(di, di->rxd32, pa, rxout, &flags,
1158 rxout = NEXTRXD(rxout);
1163 /* update the chip lastdscr pointer */
1164 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1165 W_REG(di->osh, &di->d64rxregs->ptr,
1166 di->rcvptrbase + I2B(rxout, dma64dd_t));
1167 } else if (DMA32_ENAB(di)) {
1168 W_REG(di->osh, &di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
1175 /* like getnexttxp but no reclaim */
1176 static void *_dma_peeknexttxp(dma_info_t *di)
1183 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1185 B2I(((R_REG(di->osh, &di->d64txregs->status0) &
1186 D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
1188 } else if (DMA32_ENAB(di)) {
1190 B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK,
1195 for (i = di->txin; i != end; i = NEXTTXD(i))
1202 /* like getnextrxp but not take off the ring */
1203 static void *_dma_peeknextrxp(dma_info_t *di)
1210 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1212 B2I(((R_REG(di->osh, &di->d64rxregs->status0) &
1213 D64_RS0_CD_MASK) - di->rcvptrbase) & D64_RS0_CD_MASK,
1215 } else if (DMA32_ENAB(di)) {
1217 B2I(R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK,
1222 for (i = di->rxin; i != end; i = NEXTRXD(i))
1229 static void _dma_rxreclaim(dma_info_t *di)
1233 /* "unused local" warning suppression for OSLs that
1234 * define PKTFREE() without using the di->osh arg
1238 DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
1240 while ((p = _dma_getnextrxp(di, TRUE)))
1241 PKTFREE(di->osh, p, FALSE);
1244 static void *BCMFASTPATH _dma_getnextrxp(dma_info_t *di, bool forceall)
1249 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1250 return dma64_getnextrxp(di, forceall);
1251 } else if (DMA32_ENAB(di)) {
1252 return dma32_getnextrxp(di, forceall);
1257 static void _dma_txblock(dma_info_t *di)
1259 di->hnddma.txavail = 0;
1262 static void _dma_txunblock(dma_info_t *di)
1264 di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1267 static uint _dma_txactive(dma_info_t *di)
1269 return NTXDACTIVE(di->txin, di->txout);
1272 static uint _dma_txpending(dma_info_t *di)
1276 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1278 B2I(((R_REG(di->osh, &di->d64txregs->status0) &
1279 D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
1281 } else if (DMA32_ENAB(di)) {
1283 B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK,
1288 return NTXDACTIVE(curr, di->txout);
1291 static uint _dma_txcommitted(dma_info_t *di)
1294 uint txin = di->txin;
1296 if (txin == di->txout)
1299 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1300 ptr = B2I(R_REG(di->osh, &di->d64txregs->ptr), dma64dd_t);
1301 } else if (DMA32_ENAB(di)) {
1302 ptr = B2I(R_REG(di->osh, &di->d32txregs->ptr), dma32dd_t);
1306 return NTXDACTIVE(di->txin, ptr);
1309 static uint _dma_rxactive(dma_info_t *di)
1311 return NRXDACTIVE(di->rxin, di->rxout);
1314 static void _dma_counterreset(dma_info_t *di)
1316 /* reset all software counter */
1317 di->hnddma.rxgiants = 0;
1318 di->hnddma.rxnobuf = 0;
1319 di->hnddma.txnobuf = 0;
1322 static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
1324 uint dmactrlflags = di->hnddma.dmactrlflags;
1327 DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
1331 ASSERT((flags & ~mask) == 0);
1333 dmactrlflags &= ~mask;
1334 dmactrlflags |= flags;
1336 /* If trying to enable parity, check if parity is actually supported */
1337 if (dmactrlflags & DMA_CTRL_PEN) {
1340 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1341 control = R_REG(di->osh, &di->d64txregs->control);
1342 W_REG(di->osh, &di->d64txregs->control,
1343 control | D64_XC_PD);
1344 if (R_REG(di->osh, &di->d64txregs->control) & D64_XC_PD) {
1345 /* We *can* disable it so it is supported,
1346 * restore control register
1348 W_REG(di->osh, &di->d64txregs->control,
1351 /* Not supported, don't allow it to be enabled */
1352 dmactrlflags &= ~DMA_CTRL_PEN;
1354 } else if (DMA32_ENAB(di)) {
1355 control = R_REG(di->osh, &di->d32txregs->control);
1356 W_REG(di->osh, &di->d32txregs->control,
1358 if (R_REG(di->osh, &di->d32txregs->control) & XC_PD) {
1359 W_REG(di->osh, &di->d32txregs->control,
1362 /* Not supported, don't allow it to be enabled */
1363 dmactrlflags &= ~DMA_CTRL_PEN;
1369 di->hnddma.dmactrlflags = dmactrlflags;
1371 return dmactrlflags;
1374 /* get the address of the var in order to change later */
1375 static uintptr _dma_getvar(dma_info_t *di, const char *name)
1377 if (!strcmp(name, "&txavail"))
1378 return (uintptr) &(di->hnddma.txavail);
1385 void dma_txpioloopback(osl_t *osh, dma32regs_t *regs)
1387 OR_REG(osh, ®s->control, XC_LE);
1391 u8 dma_align_sizetobits(uint size)
1395 ASSERT(!(size & (size - 1)));
1396 while (size >>= 1) {
1402 /* This function ensures that the DMA descriptor ring will not get allocated
1403 * across Page boundary. If the allocation is done across the page boundary
1404 * at the first time, then it is freed and the allocation is done at
1405 * descriptor ring size aligned location. This will ensure that the ring will
1406 * not cross page boundary
1408 static void *dma_ringalloc(osl_t *osh, u32 boundary, uint size,
1409 u16 *alignbits, uint *alloced,
1410 dmaaddr_t *descpa, osldma_t **dmah)
1414 u32 alignbytes = 1 << *alignbits;
1416 va = DMA_ALLOC_CONSISTENT(osh, size, *alignbits, alloced, descpa,
1421 desc_strtaddr = (u32) roundup((uintptr) va, alignbytes);
1422 if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
1424 *alignbits = dma_align_sizetobits(size);
1425 DMA_FREE_CONSISTENT(osh, va, size, *descpa, dmah);
1426 va = DMA_ALLOC_CONSISTENT(osh, size, *alignbits, alloced,
1432 /* 32-bit DMA functions */
1434 static void dma32_txinit(dma_info_t *di)
1436 u32 control = XC_XE;
1438 DMA_TRACE(("%s: dma_txinit\n", di->name));
1443 di->txin = di->txout = 0;
1444 di->hnddma.txavail = di->ntxd - 1;
1446 /* clear tx descriptor ring */
1447 BZERO_SM((void *)di->txd32, (di->ntxd * sizeof(dma32dd_t)));
1449 if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0)
1451 W_REG(di->osh, &di->d32txregs->control, control);
1452 _dma_ddtable_init(di, DMA_TX, di->txdpa);
1455 static bool dma32_txenabled(dma_info_t *di)
1459 /* If the chip is dead, it is not enabled :-) */
1460 xc = R_REG(di->osh, &di->d32txregs->control);
1461 return (xc != 0xffffffff) && (xc & XC_XE);
1464 static void dma32_txsuspend(dma_info_t *di)
1466 DMA_TRACE(("%s: dma_txsuspend\n", di->name));
1471 OR_REG(di->osh, &di->d32txregs->control, XC_SE);
1474 static void dma32_txresume(dma_info_t *di)
1476 DMA_TRACE(("%s: dma_txresume\n", di->name));
1481 AND_REG(di->osh, &di->d32txregs->control, ~XC_SE);
1484 static bool dma32_txsuspended(dma_info_t *di)
1486 return (di->ntxd == 0)
1487 || ((R_REG(di->osh, &di->d32txregs->control) & XC_SE) == XC_SE);
1490 static void dma32_txreclaim(dma_info_t *di, txd_range_t range)
1494 DMA_TRACE(("%s: dma_txreclaim %s\n", di->name,
1495 (range == HNDDMA_RANGE_ALL) ? "all" :
1497 HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
1500 if (di->txin == di->txout)
1503 while ((p = dma32_getnexttxp(di, range)))
1504 PKTFREE(di->osh, p, TRUE);
1507 static bool dma32_txstopped(dma_info_t *di)
1509 return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) ==
1513 static bool dma32_rxstopped(dma_info_t *di)
1515 return ((R_REG(di->osh, &di->d32rxregs->status) & RS_RS_MASK) ==
1519 static bool dma32_alloc(dma_info_t *di, uint direction)
1528 ddlen = sizeof(dma32dd_t);
1530 size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
1533 align_bits = di->dmadesc_align;
1534 align = (1 << align_bits);
1536 if (direction == DMA_TX) {
1537 va = dma_ringalloc(di->osh, D32RINGALIGN, size, &align_bits,
1538 &alloced, &di->txdpaorig, &di->tx_dmah);
1540 DMA_ERROR(("%s: dma_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
1544 PHYSADDRHISET(di->txdpa, 0);
1545 ASSERT(PHYSADDRHI(di->txdpaorig) == 0);
1546 di->txd32 = (dma32dd_t *) roundup((uintptr) va, align);
1548 (uint) ((s8 *)di->txd32 - (s8 *) va);
1550 PHYSADDRLOSET(di->txdpa,
1551 PHYSADDRLO(di->txdpaorig) + di->txdalign);
1552 /* Make sure that alignment didn't overflow */
1553 ASSERT(PHYSADDRLO(di->txdpa) >= PHYSADDRLO(di->txdpaorig));
1555 di->txdalloc = alloced;
1556 ASSERT(IS_ALIGNED((uintptr) di->txd32, align));
1558 va = dma_ringalloc(di->osh, D32RINGALIGN, size, &align_bits,
1559 &alloced, &di->rxdpaorig, &di->rx_dmah);
1561 DMA_ERROR(("%s: dma_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
1565 PHYSADDRHISET(di->rxdpa, 0);
1566 ASSERT(PHYSADDRHI(di->rxdpaorig) == 0);
1567 di->rxd32 = (dma32dd_t *) roundup((uintptr) va, align);
1569 (uint) ((s8 *)di->rxd32 - (s8 *) va);
1571 PHYSADDRLOSET(di->rxdpa,
1572 PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
1573 /* Make sure that alignment didn't overflow */
1574 ASSERT(PHYSADDRLO(di->rxdpa) >= PHYSADDRLO(di->rxdpaorig));
1575 di->rxdalloc = alloced;
1576 ASSERT(IS_ALIGNED((uintptr) di->rxd32, align));
1582 static bool dma32_txreset(dma_info_t *di)
1589 /* suspend tx DMA first */
1590 W_REG(di->osh, &di->d32txregs->control, XC_SE);
1592 (R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK))
1593 != XS_XS_DISABLED) && (status != XS_XS_IDLE)
1594 && (status != XS_XS_STOPPED), (10000));
1596 W_REG(di->osh, &di->d32txregs->control, 0);
1597 SPINWAIT(((status = (R_REG(di->osh,
1598 &di->d32txregs->status) & XS_XS_MASK)) !=
1599 XS_XS_DISABLED), 10000);
1601 /* wait for the last transaction to complete */
1604 return status == XS_XS_DISABLED;
1607 static bool dma32_rxidle(dma_info_t *di)
1609 DMA_TRACE(("%s: dma_rxidle\n", di->name));
1614 return ((R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK) ==
1615 R_REG(di->osh, &di->d32rxregs->ptr));
1618 static bool dma32_rxreset(dma_info_t *di)
1625 W_REG(di->osh, &di->d32rxregs->control, 0);
1626 SPINWAIT(((status = (R_REG(di->osh,
1627 &di->d32rxregs->status) & RS_RS_MASK)) !=
1628 RS_RS_DISABLED), 10000);
1630 return status == RS_RS_DISABLED;
1633 static bool dma32_rxenabled(dma_info_t *di)
1637 rc = R_REG(di->osh, &di->d32rxregs->control);
1638 return (rc != 0xffffffff) && (rc & RC_RE);
1641 static bool dma32_txsuspendedidle(dma_info_t *di)
1646 if (!(R_REG(di->osh, &di->d32txregs->control) & XC_SE))
1649 if ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
1653 return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) ==
1657 /* !! tx entry routine
1658 * supports full 32bit dma engine buffer addressing so
1659 * dma buffers can cross 4 Kbyte page boundaries.
1661 * WARNING: call must check the return value for error.
1662 * the error(toss frames) could be fatal and cause many subsequent hard to debug problems
1664 static int dma32_txfast(dma_info_t *di, void *p0, bool commit)
1667 unsigned char *data;
1673 DMA_TRACE(("%s: dma_txfast\n", di->name));
1678 * Walk the chain of packet buffers
1679 * allocating and initializing transmit descriptor entries.
1681 for (p = p0; p; p = next) {
1683 hnddma_seg_map_t *map;
1688 len += PKTDMAPAD(di->osh, p);
1692 /* return nonzero if out of tx descriptors */
1693 if (NEXTTXD(txout) == di->txin)
1700 bzero(&di->txp_dmah[txout], sizeof(hnddma_seg_map_t));
1702 /* get physical address of buffer start */
1703 pa = DMA_MAP(di->osh, data, len, DMA_TX, p,
1704 &di->txp_dmah[txout]);
1706 if (DMASGLIST_ENAB) {
1707 map = &di->txp_dmah[txout];
1709 /* See if all the segments can be accounted for */
1711 (uint) (di->ntxd - NTXDACTIVE(di->txin, di->txout) -
1719 for (j = 1; j <= nsegs; j++) {
1721 if (p == p0 && j == 1)
1724 /* With a DMA segment list, Descriptor table is filled
1725 * using the segment list instead of looping over
1726 * buffers in multi-chain DMA. Therefore, EOF for SGLIST is when
1727 * end of segment list is reached.
1729 if ((!DMASGLIST_ENAB && next == NULL) ||
1730 (DMASGLIST_ENAB && j == nsegs))
1731 flags |= (CTRL_IOC | CTRL_EOF);
1732 if (txout == (di->ntxd - 1))
1735 if (DMASGLIST_ENAB) {
1736 len = map->segs[j - 1].length;
1737 pa = map->segs[j - 1].addr;
1739 ASSERT(PHYSADDRHI(pa) == 0);
1741 dma32_dd_upd(di, di->txd32, pa, txout, &flags, len);
1742 ASSERT(di->txp[txout] == NULL);
1744 txout = NEXTTXD(txout);
1747 /* See above. No need to loop over individual buffers */
1752 /* if last txd eof not set, fix it */
1753 if (!(flags & CTRL_EOF))
1754 W_SM(&di->txd32[PREVTXD(txout)].ctrl,
1755 BUS_SWAP32(flags | CTRL_IOC | CTRL_EOF));
1757 /* save the packet */
1758 di->txp[PREVTXD(txout)] = p0;
1760 /* bump the tx descriptor index */
1765 W_REG(di->osh, &di->d32txregs->ptr, I2B(txout, dma32dd_t));
1767 /* tx flow control */
1768 di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1773 DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
1774 PKTFREE(di->osh, p0, TRUE);
1775 di->hnddma.txavail = 0;
1776 di->hnddma.txnobuf++;
1781 * Reclaim next completed txd (txds if using chained buffers) in the range
1782 * specified and return associated packet.
1783 * If range is HNDDMA_RANGE_TRANSMITTED, reclaim descriptors that have be
1784 * transmitted as noted by the hardware "CurrDescr" pointer.
1785 * If range is HNDDMA_RANGE_TRANSFERED, reclaim descriptors that have be
1786 * transfered by the DMA as noted by the hardware "ActiveDescr" pointer.
1787 * If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
1788 * return associated packet regardless of the value of hardware pointers.
1790 static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range)
1796 DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name,
1797 (range == HNDDMA_RANGE_ALL) ? "all" :
1799 HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
1808 if (range == HNDDMA_RANGE_ALL)
1811 dma32regs_t *dregs = di->d32txregs;
1814 (u16) B2I(R_REG(di->osh, &dregs->status) & XS_CD_MASK,
1817 if (range == HNDDMA_RANGE_TRANSFERED) {
1819 (u16) ((R_REG(di->osh, &dregs->status) &
1820 XS_AD_MASK) >> XS_AD_SHIFT);
1821 active_desc = (u16) B2I(active_desc, dma32dd_t);
1822 if (end != active_desc)
1823 end = PREVTXD(active_desc);
1827 if ((start == 0) && (end > di->txout))
1830 for (i = start; i != end && !txp; i = NEXTTXD(i)) {
1832 hnddma_seg_map_t *map = NULL;
1833 uint size, j, nsegs;
1836 (BUS_SWAP32(R_SM(&di->txd32[i].addr)) -
1837 di->dataoffsetlow));
1838 PHYSADDRHISET(pa, 0);
1840 if (DMASGLIST_ENAB) {
1841 map = &di->txp_dmah[i];
1842 size = map->origsize;
1846 (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) &
1851 for (j = nsegs; j > 0; j--) {
1852 W_SM(&di->txd32[i].addr, 0xdeadbeef);
1860 DMA_UNMAP(di->osh, pa, size, DMA_TX, txp, map);
1865 /* tx flow control */
1866 di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1871 DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall));
1875 static void *dma32_getnextrxp(dma_info_t *di, bool forceall)
1880 /* if forcing, dma engine must be disabled */
1881 ASSERT(!forceall || !dma32_rxenabled(di));
1885 /* return if no packets posted */
1890 B2I(R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK, dma32dd_t);
1892 /* ignore curr if forceall */
1893 if (!forceall && (i == curr))
1896 /* get the packet pointer that corresponds to the rx descriptor */
1902 (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) -
1903 di->dataoffsetlow));
1904 PHYSADDRHISET(pa, 0);
1906 /* clear this packet from the descriptor ring */
1907 DMA_UNMAP(di->osh, pa, di->rxbufsize, DMA_RX, rxp, &di->rxp_dmah[i]);
1909 W_SM(&di->rxd32[i].addr, 0xdeadbeef);
1911 di->rxin = NEXTRXD(i);
1917 * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
1919 static void dma32_txrotate(dma_info_t *di)
1928 ASSERT(dma32_txsuspendedidle(di));
1930 nactive = _dma_txactive(di);
1932 (((R_REG(di->osh, &di->d32txregs->status) & XS_AD_MASK)
1933 >> XS_AD_SHIFT), dma32dd_t));
1934 rot = TXD(ad - di->txin);
1936 ASSERT(rot < di->ntxd);
1938 /* full-ring case is a lot harder - don't worry about this */
1939 if (rot >= (di->ntxd - nactive)) {
1940 DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
1945 last = PREVTXD(di->txout);
1947 /* move entries starting at last and moving backwards to first */
1948 for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
1949 new = TXD(old + rot);
1952 * Move the tx dma descriptor.
1953 * EOT is set only in the last entry in the ring.
1955 w = BUS_SWAP32(R_SM(&di->txd32[old].ctrl)) & ~CTRL_EOT;
1956 if (new == (di->ntxd - 1))
1958 W_SM(&di->txd32[new].ctrl, BUS_SWAP32(w));
1959 W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
1961 /* zap the old tx dma descriptor address field */
1962 W_SM(&di->txd32[old].addr, BUS_SWAP32(0xdeadbeef));
1964 /* move the corresponding txp[] entry */
1965 ASSERT(di->txp[new] == NULL);
1966 di->txp[new] = di->txp[old];
1968 /* Move the segment map as well */
1969 if (DMASGLIST_ENAB) {
1970 bcopy(&di->txp_dmah[old], &di->txp_dmah[new],
1971 sizeof(hnddma_seg_map_t));
1972 bzero(&di->txp_dmah[old], sizeof(hnddma_seg_map_t));
1975 di->txp[old] = NULL;
1978 /* update txin and txout */
1980 di->txout = TXD(di->txout + rot);
1981 di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1984 W_REG(di->osh, &di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
1987 /* 64-bit DMA functions */
1989 static void dma64_txinit(dma_info_t *di)
1991 u32 control = D64_XC_XE;
1993 DMA_TRACE(("%s: dma_txinit\n", di->name));
1998 di->txin = di->txout = 0;
1999 di->hnddma.txavail = di->ntxd - 1;
2001 /* clear tx descriptor ring */
2002 BZERO_SM((void *)di->txd64, (di->ntxd * sizeof(dma64dd_t)));
2004 /* DMA engine with out alignment requirement requires table to be inited
2005 * before enabling the engine
2007 if (!di->aligndesc_4k)
2008 _dma_ddtable_init(di, DMA_TX, di->txdpa);
2010 if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0)
2011 control |= D64_XC_PD;
2012 OR_REG(di->osh, &di->d64txregs->control, control);
2014 /* DMA engine with alignment requirement requires table to be inited
2015 * before enabling the engine
2017 if (di->aligndesc_4k)
2018 _dma_ddtable_init(di, DMA_TX, di->txdpa);
2021 static bool dma64_txenabled(dma_info_t *di)
2025 /* If the chip is dead, it is not enabled :-) */
2026 xc = R_REG(di->osh, &di->d64txregs->control);
2027 return (xc != 0xffffffff) && (xc & D64_XC_XE);
2030 static void dma64_txsuspend(dma_info_t *di)
2032 DMA_TRACE(("%s: dma_txsuspend\n", di->name));
2037 OR_REG(di->osh, &di->d64txregs->control, D64_XC_SE);
2040 static void dma64_txresume(dma_info_t *di)
2042 DMA_TRACE(("%s: dma_txresume\n", di->name));
2047 AND_REG(di->osh, &di->d64txregs->control, ~D64_XC_SE);
2050 static bool dma64_txsuspended(dma_info_t *di)
2052 return (di->ntxd == 0) ||
2053 ((R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE) ==
2057 static void BCMFASTPATH dma64_txreclaim(dma_info_t *di, txd_range_t range)
2061 DMA_TRACE(("%s: dma_txreclaim %s\n", di->name,
2062 (range == HNDDMA_RANGE_ALL) ? "all" :
2064 HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
2067 if (di->txin == di->txout)
2070 while ((p = dma64_getnexttxp(di, range))) {
2071 /* For unframed data, we don't have any packets to free */
2072 if (!(di->hnddma.dmactrlflags & DMA_CTRL_UNFRAMED))
2073 PKTFREE(di->osh, p, TRUE);
2077 static bool dma64_txstopped(dma_info_t *di)
2079 return ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) ==
2080 D64_XS0_XS_STOPPED);
2083 static bool dma64_rxstopped(dma_info_t *di)
2085 return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK) ==
2086 D64_RS0_RS_STOPPED);
2089 static bool dma64_alloc(dma_info_t *di, uint direction)
2098 ddlen = sizeof(dma64dd_t);
2100 size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
2101 align_bits = di->dmadesc_align;
2102 align = (1 << align_bits);
2104 if (direction == DMA_TX) {
2105 va = dma_ringalloc(di->osh, D64RINGALIGN, size, &align_bits,
2106 &alloced, &di->txdpaorig, &di->tx_dmah);
2108 DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
2111 align = (1 << align_bits);
2112 di->txd64 = (dma64dd_t *) roundup((uintptr) va, align);
2113 di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
2114 PHYSADDRLOSET(di->txdpa,
2115 PHYSADDRLO(di->txdpaorig) + di->txdalign);
2116 /* Make sure that alignment didn't overflow */
2117 ASSERT(PHYSADDRLO(di->txdpa) >= PHYSADDRLO(di->txdpaorig));
2119 PHYSADDRHISET(di->txdpa, PHYSADDRHI(di->txdpaorig));
2120 di->txdalloc = alloced;
2121 ASSERT(IS_ALIGNED((uintptr) di->txd64, align));
2123 va = dma_ringalloc(di->osh, D64RINGALIGN, size, &align_bits,
2124 &alloced, &di->rxdpaorig, &di->rx_dmah);
2126 DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
2129 align = (1 << align_bits);
2130 di->rxd64 = (dma64dd_t *) roundup((uintptr) va, align);
2131 di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
2132 PHYSADDRLOSET(di->rxdpa,
2133 PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
2134 /* Make sure that alignment didn't overflow */
2135 ASSERT(PHYSADDRLO(di->rxdpa) >= PHYSADDRLO(di->rxdpaorig));
2137 PHYSADDRHISET(di->rxdpa, PHYSADDRHI(di->rxdpaorig));
2138 di->rxdalloc = alloced;
2139 ASSERT(IS_ALIGNED((uintptr) di->rxd64, align));
2145 static bool dma64_txreset(dma_info_t *di)
2152 /* suspend tx DMA first */
2153 W_REG(di->osh, &di->d64txregs->control, D64_XC_SE);
2155 (R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK))
2156 != D64_XS0_XS_DISABLED) && (status != D64_XS0_XS_IDLE)
2157 && (status != D64_XS0_XS_STOPPED), 10000);
2159 W_REG(di->osh, &di->d64txregs->control, 0);
2161 (R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK))
2162 != D64_XS0_XS_DISABLED), 10000);
2164 /* wait for the last transaction to complete */
2167 return status == D64_XS0_XS_DISABLED;
2170 static bool dma64_rxidle(dma_info_t *di)
2172 DMA_TRACE(("%s: dma_rxidle\n", di->name));
2177 return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
2178 (R_REG(di->osh, &di->d64rxregs->ptr) & D64_RS0_CD_MASK));
2181 static bool dma64_rxreset(dma_info_t *di)
2188 W_REG(di->osh, &di->d64rxregs->control, 0);
2190 (R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK))
2191 != D64_RS0_RS_DISABLED), 10000);
2193 return status == D64_RS0_RS_DISABLED;
2196 static bool dma64_rxenabled(dma_info_t *di)
2200 rc = R_REG(di->osh, &di->d64rxregs->control);
2201 return (rc != 0xffffffff) && (rc & D64_RC_RE);
2204 static bool dma64_txsuspendedidle(dma_info_t *di)
2210 if (!(R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE))
2213 if ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) ==
2220 /* Useful when sending unframed data. This allows us to get a progress report from the DMA.
2221 * We return a pointer to the beginning of the DATA buffer of the current descriptor.
2222 * If DMA is idle, we return NULL.
2224 static void *dma64_getpos(dma_info_t *di, bool direction)
2230 if (direction == DMA_TX) {
2232 R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_CD_MASK;
2233 idle = !NTXDACTIVE(di->txin, di->txout);
2234 va = di->txp[B2I(cd_offset, dma64dd_t)];
2237 R_REG(di->osh, &di->d64rxregs->status0) & D64_XS0_CD_MASK;
2238 idle = !NRXDACTIVE(di->rxin, di->rxout);
2239 va = di->rxp[B2I(cd_offset, dma64dd_t)];
2242 /* If DMA is IDLE, return NULL */
2244 DMA_TRACE(("%s: DMA idle, return NULL\n", __func__));
2251 /* TX of unframed data
2253 * Adds a DMA ring descriptor for the data pointed to by "buf".
2254 * This is for DMA of a buffer of data and is unlike other hnddma TX functions
2255 * that take a pointer to a "packet"
2256 * Each call to this is results in a single descriptor being added for "len" bytes of
2257 * data starting at "buf", it doesn't handle chained buffers.
2259 static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
2263 dmaaddr_t pa; /* phys addr */
2267 /* return nonzero if out of tx descriptors */
2268 if (NEXTTXD(txout) == di->txin)
2274 pa = DMA_MAP(di->osh, buf, len, DMA_TX, NULL, &di->txp_dmah[txout]);
2276 flags = (D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF);
2278 if (txout == (di->ntxd - 1))
2279 flags |= D64_CTRL1_EOT;
2281 dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
2282 ASSERT(di->txp[txout] == NULL);
2284 /* save the buffer pointer - used by dma_getpos */
2285 di->txp[txout] = buf;
2287 txout = NEXTTXD(txout);
2288 /* bump the tx descriptor index */
2293 W_REG(di->osh, &di->d64txregs->ptr,
2294 di->xmtptrbase + I2B(txout, dma64dd_t));
2297 /* tx flow control */
2298 di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2303 DMA_ERROR(("%s: %s: out of txds !!!\n", di->name, __func__));
2304 di->hnddma.txavail = 0;
2305 di->hnddma.txnobuf++;
2309 /* !! tx entry routine
2310 * WARNING: call must check the return value for error.
2311 * the error(toss frames) could be fatal and cause many subsequent hard to debug problems
2313 static int BCMFASTPATH dma64_txfast(dma_info_t *di, void *p0, bool commit)
2316 unsigned char *data;
2322 DMA_TRACE(("%s: dma_txfast\n", di->name));
2327 * Walk the chain of packet buffers
2328 * allocating and initializing transmit descriptor entries.
2330 for (p = p0; p; p = next) {
2332 hnddma_seg_map_t *map;
2337 len += PKTDMAPAD(di->osh, p);
2338 #endif /* BCM_DMAPAD */
2341 /* return nonzero if out of tx descriptors */
2342 if (NEXTTXD(txout) == di->txin)
2348 /* get physical address of buffer start */
2350 bzero(&di->txp_dmah[txout], sizeof(hnddma_seg_map_t));
2352 pa = DMA_MAP(di->osh, data, len, DMA_TX, p,
2353 &di->txp_dmah[txout]);
2355 if (DMASGLIST_ENAB) {
2356 map = &di->txp_dmah[txout];
2358 /* See if all the segments can be accounted for */
2360 (uint) (di->ntxd - NTXDACTIVE(di->txin, di->txout) -
2368 for (j = 1; j <= nsegs; j++) {
2370 if (p == p0 && j == 1)
2371 flags |= D64_CTRL1_SOF;
2373 /* With a DMA segment list, Descriptor table is filled
2374 * using the segment list instead of looping over
2375 * buffers in multi-chain DMA. Therefore, EOF for SGLIST is when
2376 * end of segment list is reached.
2378 if ((!DMASGLIST_ENAB && next == NULL) ||
2379 (DMASGLIST_ENAB && j == nsegs))
2380 flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
2381 if (txout == (di->ntxd - 1))
2382 flags |= D64_CTRL1_EOT;
2384 if (DMASGLIST_ENAB) {
2385 len = map->segs[j - 1].length;
2386 pa = map->segs[j - 1].addr;
2388 dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
2389 ASSERT(di->txp[txout] == NULL);
2391 txout = NEXTTXD(txout);
2394 /* See above. No need to loop over individual buffers */
2399 /* if last txd eof not set, fix it */
2400 if (!(flags & D64_CTRL1_EOF))
2401 W_SM(&di->txd64[PREVTXD(txout)].ctrl1,
2402 BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
2404 /* save the packet */
2405 di->txp[PREVTXD(txout)] = p0;
2407 /* bump the tx descriptor index */
2412 W_REG(di->osh, &di->d64txregs->ptr,
2413 di->xmtptrbase + I2B(txout, dma64dd_t));
2415 /* tx flow control */
2416 di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2421 DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di->name));
2422 PKTFREE(di->osh, p0, TRUE);
2423 di->hnddma.txavail = 0;
2424 di->hnddma.txnobuf++;
2429 * Reclaim next completed txd (txds if using chained buffers) in the range
2430 * specified and return associated packet.
2431 * If range is HNDDMA_RANGE_TRANSMITTED, reclaim descriptors that have be
2432 * transmitted as noted by the hardware "CurrDescr" pointer.
2433 * If range is HNDDMA_RANGE_TRANSFERED, reclaim descriptors that have be
2434 * transfered by the DMA as noted by the hardware "ActiveDescr" pointer.
2435 * If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
2436 * return associated packet regardless of the value of hardware pointers.
2438 static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range)
2444 DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name,
2445 (range == HNDDMA_RANGE_ALL) ? "all" :
2447 HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
2456 if (range == HNDDMA_RANGE_ALL)
2459 dma64regs_t *dregs = di->d64txregs;
2463 (((R_REG(di->osh, &dregs->status0) &
2465 di->xmtptrbase) & D64_XS0_CD_MASK, dma64dd_t));
2467 if (range == HNDDMA_RANGE_TRANSFERED) {
2469 (u16) (R_REG(di->osh, &dregs->status1) &
2472 (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK;
2473 active_desc = B2I(active_desc, dma64dd_t);
2474 if (end != active_desc)
2475 end = PREVTXD(active_desc);
2479 if ((start == 0) && (end > di->txout))
2482 for (i = start; i != end && !txp; i = NEXTTXD(i)) {
2484 hnddma_seg_map_t *map = NULL;
2485 uint size, j, nsegs;
2488 (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) -
2489 di->dataoffsetlow));
2491 (BUS_SWAP32(R_SM(&di->txd64[i].addrhigh)) -
2492 di->dataoffsethigh));
2494 if (DMASGLIST_ENAB) {
2495 map = &di->txp_dmah[i];
2496 size = map->origsize;
2500 (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) &
2505 for (j = nsegs; j > 0; j--) {
2506 W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
2507 W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
2515 DMA_UNMAP(di->osh, pa, size, DMA_TX, txp, map);
2520 /* tx flow control */
2521 di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2526 DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall));
2530 static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
2536 /* if forcing, dma engine must be disabled */
2537 ASSERT(!forceall || !dma64_rxenabled(di));
2541 /* return if no packets posted */
2546 B2I(((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) -
2547 di->rcvptrbase) & D64_RS0_CD_MASK, dma64dd_t);
2549 /* ignore curr if forceall */
2550 if (!forceall && (i == curr))
2553 /* get the packet pointer that corresponds to the rx descriptor */
2559 (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) -
2560 di->dataoffsetlow));
2562 (BUS_SWAP32(R_SM(&di->rxd64[i].addrhigh)) -
2563 di->dataoffsethigh));
2565 /* clear this packet from the descriptor ring */
2566 DMA_UNMAP(di->osh, pa, di->rxbufsize, DMA_RX, rxp, &di->rxp_dmah[i]);
2568 W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
2569 W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
2571 di->rxin = NEXTRXD(i);
2576 static bool _dma64_addrext(osl_t *osh, dma64regs_t * dma64regs)
2579 OR_REG(osh, &dma64regs->control, D64_XC_AE);
2580 w = R_REG(osh, &dma64regs->control);
2581 AND_REG(osh, &dma64regs->control, ~D64_XC_AE);
2582 return (w & D64_XC_AE) == D64_XC_AE;
2586 * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
2588 static void dma64_txrotate(dma_info_t *di)
2597 ASSERT(dma64_txsuspendedidle(di));
2599 nactive = _dma_txactive(di);
2601 ((((R_REG(di->osh, &di->d64txregs->status1) &
2603 - di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t));
2604 rot = TXD(ad - di->txin);
2606 ASSERT(rot < di->ntxd);
2608 /* full-ring case is a lot harder - don't worry about this */
2609 if (rot >= (di->ntxd - nactive)) {
2610 DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
2615 last = PREVTXD(di->txout);
2617 /* move entries starting at last and moving backwards to first */
2618 for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
2619 new = TXD(old + rot);
2622 * Move the tx dma descriptor.
2623 * EOT is set only in the last entry in the ring.
2625 w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl1)) & ~D64_CTRL1_EOT;
2626 if (new == (di->ntxd - 1))
2628 W_SM(&di->txd64[new].ctrl1, BUS_SWAP32(w));
2630 w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl2));
2631 W_SM(&di->txd64[new].ctrl2, BUS_SWAP32(w));
2633 W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
2634 W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
2636 /* zap the old tx dma descriptor address field */
2637 W_SM(&di->txd64[old].addrlow, BUS_SWAP32(0xdeadbeef));
2638 W_SM(&di->txd64[old].addrhigh, BUS_SWAP32(0xdeadbeef));
2640 /* move the corresponding txp[] entry */
2641 ASSERT(di->txp[new] == NULL);
2642 di->txp[new] = di->txp[old];
2645 if (DMASGLIST_ENAB) {
2646 bcopy(&di->txp_dmah[old], &di->txp_dmah[new],
2647 sizeof(hnddma_seg_map_t));
2648 bzero(&di->txp_dmah[old], sizeof(hnddma_seg_map_t));
2651 di->txp[old] = NULL;
2654 /* update txin and txout */
2656 di->txout = TXD(di->txout + rot);
2657 di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2660 W_REG(di->osh, &di->d64txregs->ptr,
2661 di->xmtptrbase + I2B(di->txout, dma64dd_t));
2664 uint dma_addrwidth(si_t *sih, void *dmaregs)
2666 dma32regs_t *dma32regs;
2671 /* Perform 64-bit checks only if we want to advertise 64-bit (> 32bit) capability) */
2672 /* DMA engine is 64-bit capable */
2673 if ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64) {
2674 /* backplane are 64-bit capable */
2675 if (si_backplane64(sih))
2676 /* If bus is System Backplane or PCIE then we can access 64-bits */
2677 if ((BUSTYPE(sih->bustype) == SI_BUS) ||
2678 ((BUSTYPE(sih->bustype) == PCI_BUS) &&
2679 (sih->buscoretype == PCIE_CORE_ID)))
2680 return DMADDRWIDTH_64;
2682 /* DMA64 is always 32-bit capable, AE is always TRUE */
2683 ASSERT(_dma64_addrext(osh, (dma64regs_t *) dmaregs));
2685 return DMADDRWIDTH_32;
2688 /* Start checking for 32-bit / 30-bit addressing */
2689 dma32regs = (dma32regs_t *) dmaregs;
2691 /* For System Backplane, PCIE bus or addrext feature, 32-bits ok */
2692 if ((BUSTYPE(sih->bustype) == SI_BUS) ||
2693 ((BUSTYPE(sih->bustype) == PCI_BUS)
2694 && sih->buscoretype == PCIE_CORE_ID)
2695 || (_dma32_addrext(osh, dma32regs)))
2696 return DMADDRWIDTH_32;
2699 return DMADDRWIDTH_30;