2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/string.h>
22 #include <linux/kernel.h>
29 #include "siutils_priv.h"
31 #define PMU_ERROR(args)
34 #define PMU_MSG(args) printf args
39 /* To check in verbose debugging messages not intended
40 * to be on except on private builds.
42 #define PMU_NONE(args)
44 /* PLL controls/clocks */
45 static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc,
47 static u32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
48 static u32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
51 static bool si_pmu_res_depfltr_bb(si_t *sih);
52 static bool si_pmu_res_depfltr_ncb(si_t *sih);
53 static bool si_pmu_res_depfltr_paldo(si_t *sih);
54 static bool si_pmu_res_depfltr_npaldo(si_t *sih);
55 static u32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc,
57 static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
59 static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax);
60 static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
61 osl_t *osh, u8 spuravoid);
63 static void si_pmu_set_4330_plldivs(si_t *sih);
66 #define FVCO_880 880000 /* 880MHz */
67 #define FVCO_1760 1760000 /* 1760MHz */
68 #define FVCO_1440 1440000 /* 1440MHz */
69 #define FVCO_960 960000 /* 960MHz */
71 /* Read/write a chipcontrol reg */
72 u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
74 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
76 return si_corereg(sih, SI_CC_IDX,
77 offsetof(chipcregs_t, chipcontrol_data), mask, val);
80 /* Read/write a regcontrol reg */
81 u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
83 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
85 return si_corereg(sih, SI_CC_IDX,
86 offsetof(chipcregs_t, regcontrol_data), mask, val);
89 /* Read/write a pllcontrol reg */
90 u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
92 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
94 return si_corereg(sih, SI_CC_IDX,
95 offsetof(chipcregs_t, pllcontrol_data), mask, val);
99 void si_pmu_pllupd(si_t *sih)
101 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
102 PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
105 /* Setup switcher voltage */
107 BCMATTACHFN(si_pmu_set_switcher_voltage) (si_t *sih, osl_t *osh,
108 u8 bb_voltage, u8 rf_voltage) {
112 ASSERT(sih->cccaps & CC_CAP_PMU);
114 /* Remember original core before switch to chipc */
115 origidx = si_coreidx(sih);
116 cc = si_setcoreidx(sih, SI_CC_IDX);
119 W_REG(osh, &cc->regcontrol_addr, 0x01);
120 W_REG(osh, &cc->regcontrol_data, (u32) (bb_voltage & 0x1f) << 22);
122 W_REG(osh, &cc->regcontrol_addr, 0x00);
123 W_REG(osh, &cc->regcontrol_data, (u32) (rf_voltage & 0x1f) << 14);
125 /* Return to original core */
126 si_setcoreidx(sih, origidx);
130 BCMATTACHFN(si_pmu_set_ldo_voltage) (si_t *sih, osl_t *osh, u8 ldo,
132 u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
135 ASSERT(sih->cccaps & CC_CAP_PMU);
137 switch (CHIPID(sih->chip)) {
138 case BCM4336_CHIP_ID:
140 case SET_LDO_VOLTAGE_CLDO_PWM:
145 case SET_LDO_VOLTAGE_CLDO_BURST:
150 case SET_LDO_VOLTAGE_LNLDO1:
160 case BCM4330_CHIP_ID:
162 case SET_LDO_VOLTAGE_CBUCK_PWM:
177 shift = sr_cntl_shift + rc_shift;
179 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
181 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
182 mask << shift, (voltage & mask) << shift);
185 /* d11 slow to fast clock transition time in slow clock cycles */
186 #define D11SCC_SLOW2FAST_TRANSITION 2
188 u16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh)
190 uint delay = PMU_MAX_TRANSITION_DLY;
195 chn[0] = 0; /* to suppress compile error */
198 ASSERT(sih->cccaps & CC_CAP_PMU);
200 /* Remember original core before switch to chipc */
201 origidx = si_coreidx(sih);
202 cc = si_setcoreidx(sih, SI_CC_IDX);
205 switch (CHIPID(sih->chip)) {
206 case BCM43224_CHIP_ID:
207 case BCM43225_CHIP_ID:
208 case BCM43421_CHIP_ID:
209 case BCM43235_CHIP_ID:
210 case BCM43236_CHIP_ID:
211 case BCM43238_CHIP_ID:
212 case BCM4331_CHIP_ID:
213 case BCM6362_CHIP_ID:
214 case BCM4313_CHIP_ID:
215 delay = ISSIM_ENAB(sih) ? 70 : 3700;
217 case BCM4329_CHIP_ID:
221 u32 ilp = si_ilp_clock(sih);
223 (si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) +
224 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
226 delay = (11 * delay) / 10;
229 case BCM4319_CHIP_ID:
230 delay = ISSIM_ENAB(sih) ? 70 : 3700;
232 case BCM4336_CHIP_ID:
236 u32 ilp = si_ilp_clock(sih);
238 (si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) +
239 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
241 delay = (11 * delay) / 10;
244 case BCM4330_CHIP_ID:
248 u32 ilp = si_ilp_clock(sih);
250 (si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) +
251 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
253 delay = (11 * delay) / 10;
259 /* Return to original core */
260 si_setcoreidx(sih, origidx);
265 u32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force)
271 ASSERT(sih->cccaps & CC_CAP_PMU);
273 /* Remember original core before switch to chipc */
274 origidx = si_coreidx(sih);
275 cc = si_setcoreidx(sih, SI_CC_IDX);
278 oldpmucontrol = R_REG(osh, &cc->pmucontrol);
280 W_REG(osh, &cc->pmucontrol, oldpmucontrol &
281 ~(PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN));
283 W_REG(osh, &cc->pmucontrol, oldpmucontrol |
284 (PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN));
286 /* Return to original core */
287 si_setcoreidx(sih, origidx);
289 return oldpmucontrol;
292 /* Setup resource up/down timers */
298 /* Change resource dependancies masks */
300 u32 res_mask; /* resources (chip specific) */
301 s8 action; /* action */
302 u32 depend_mask; /* changes to the dependancies mask */
303 bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return TRUE */
306 /* Resource dependancies mask change action */
307 #define RES_DEPEND_SET 0 /* Override the dependancies mask */
308 #define RES_DEPEND_ADD 1 /* Add to the dependancies mask */
309 #define RES_DEPEND_REMOVE -1 /* Remove from the dependancies mask */
311 static const pmu_res_updown_t bcm4328a0_res_updown[] = {
313 RES4328_EXT_SWITCHER_PWM, 0x0101}, {
314 RES4328_BB_SWITCHER_PWM, 0x1f01}, {
315 RES4328_BB_SWITCHER_BURST, 0x010f}, {
316 RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, {
317 RES4328_ILP_REQUEST, 0x0202}, {
318 RES4328_RADIO_SWITCHER_PWM, 0x0f01}, {
319 RES4328_RADIO_SWITCHER_BURST, 0x0f01}, {
320 RES4328_ROM_SWITCH, 0x0101}, {
321 RES4328_PA_REF_LDO, 0x0f01}, {
322 RES4328_RADIO_LDO, 0x0f01}, {
323 RES4328_AFE_LDO, 0x0f01}, {
324 RES4328_PLL_LDO, 0x0f01}, {
325 RES4328_BG_FILTBYP, 0x0101}, {
326 RES4328_TX_FILTBYP, 0x0101}, {
327 RES4328_RX_FILTBYP, 0x0101}, {
328 RES4328_XTAL_PU, 0x0101}, {
329 RES4328_XTAL_EN, 0xa001}, {
330 RES4328_BB_PLL_FILTBYP, 0x0101}, {
331 RES4328_RF_PLL_FILTBYP, 0x0101}, {
332 RES4328_BB_PLL_PU, 0x0701}
335 static const pmu_res_depend_t bcm4328a0_res_depend[] = {
336 /* Adjust ILP request resource not to force ext/BB switchers into burst mode */
338 PMURES_BIT(RES4328_ILP_REQUEST),
340 PMURES_BIT(RES4328_EXT_SWITCHER_PWM) |
341 PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL}
344 static const pmu_res_updown_t bcm4325a0_res_updown_qt[] = {
346 RES4325_HT_AVAIL, 0x0300}, {
347 RES4325_BBPLL_PWRSW_PU, 0x0101}, {
348 RES4325_RFPLL_PWRSW_PU, 0x0101}, {
349 RES4325_ALP_AVAIL, 0x0100}, {
350 RES4325_XTAL_PU, 0x1000}, {
351 RES4325_LNLDO1_PU, 0x0800}, {
352 RES4325_CLDO_CBUCK_PWM, 0x0101}, {
353 RES4325_CBUCK_PWM, 0x0803}
356 static const pmu_res_updown_t bcm4325a0_res_updown[] = {
358 RES4325_XTAL_PU, 0x1501}
361 static const pmu_res_depend_t bcm4325a0_res_depend[] = {
362 /* Adjust OTP PU resource dependencies - remove BB BURST */
364 PMURES_BIT(RES4325_OTP_PU),
366 PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL},
367 /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */
369 PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL),
371 PMURES_BIT(RES4325_BUCK_BOOST_BURST) |
372 PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb},
373 /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
375 PMURES_BIT(RES4325_HT_AVAIL),
377 PMURES_BIT(RES4325_RX_PWRSW_PU) |
378 PMURES_BIT(RES4325_TX_PWRSW_PU) |
379 PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
380 PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL},
381 /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
383 PMURES_BIT(RES4325_ILP_REQUEST) |
384 PMURES_BIT(RES4325_ABUCK_BURST) |
385 PMURES_BIT(RES4325_ABUCK_PWM) |
386 PMURES_BIT(RES4325_LNLDO1_PU) |
387 PMURES_BIT(RES4325C1_LNLDO2_PU) |
388 PMURES_BIT(RES4325_XTAL_PU) |
389 PMURES_BIT(RES4325_ALP_AVAIL) |
390 PMURES_BIT(RES4325_RX_PWRSW_PU) |
391 PMURES_BIT(RES4325_TX_PWRSW_PU) |
392 PMURES_BIT(RES4325_RFPLL_PWRSW_PU) |
393 PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
394 PMURES_BIT(RES4325_AFE_PWRSW_PU) |
395 PMURES_BIT(RES4325_BBPLL_PWRSW_PU) |
396 PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE,
397 PMURES_BIT(RES4325B0_CBUCK_LPOM) |
398 PMURES_BIT(RES4325B0_CBUCK_BURST) |
399 PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb}
402 static const pmu_res_updown_t bcm4315a0_res_updown_qt[] = {
404 RES4315_HT_AVAIL, 0x0101}, {
405 RES4315_XTAL_PU, 0x0100}, {
406 RES4315_LNLDO1_PU, 0x0100}, {
407 RES4315_PALDO_PU, 0x0100}, {
408 RES4315_CLDO_PU, 0x0100}, {
409 RES4315_CBUCK_PWM, 0x0100}, {
410 RES4315_CBUCK_BURST, 0x0100}, {
411 RES4315_CBUCK_LPOM, 0x0100}
414 static const pmu_res_updown_t bcm4315a0_res_updown[] = {
416 RES4315_XTAL_PU, 0x2501}
419 static const pmu_res_depend_t bcm4315a0_res_depend[] = {
420 /* Adjust OTP PU resource dependencies - not need PALDO unless write */
422 PMURES_BIT(RES4315_OTP_PU),
424 PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo},
425 /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */
427 PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL),
429 PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo},
430 /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
432 PMURES_BIT(RES4315_HT_AVAIL),
434 PMURES_BIT(RES4315_RX_PWRSW_PU) |
435 PMURES_BIT(RES4315_TX_PWRSW_PU) |
436 PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
437 PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL},
438 /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
440 PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) |
441 PMURES_BIT(RES4315_LNLDO1_PU) |
442 PMURES_BIT(RES4315_OTP_PU) |
443 PMURES_BIT(RES4315_LNLDO2_PU) |
444 PMURES_BIT(RES4315_XTAL_PU) |
445 PMURES_BIT(RES4315_ALP_AVAIL) |
446 PMURES_BIT(RES4315_RX_PWRSW_PU) |
447 PMURES_BIT(RES4315_TX_PWRSW_PU) |
448 PMURES_BIT(RES4315_RFPLL_PWRSW_PU) |
449 PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
450 PMURES_BIT(RES4315_AFE_PWRSW_PU) |
451 PMURES_BIT(RES4315_BBPLL_PWRSW_PU) |
452 PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE,
453 PMURES_BIT(RES4315_CBUCK_LPOM) |
454 PMURES_BIT(RES4315_CBUCK_BURST) |
455 PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb}
458 /* 4329 specific. needs to come back this issue later */
459 static const pmu_res_updown_t BCMINITDATA(bcm4329_res_updown)[] = {
461 RES4329_XTAL_PU, 0x1501}
464 static const pmu_res_depend_t BCMINITDATA(bcm4329_res_depend)[] = {
465 /* Adjust HT Avail resource dependencies */
467 PMURES_BIT(RES4329_HT_AVAIL),
469 PMURES_BIT(RES4329_CBUCK_LPOM) |
470 PMURES_BIT(RES4329_CBUCK_BURST) |
471 PMURES_BIT(RES4329_CBUCK_PWM) |
472 PMURES_BIT(RES4329_CLDO_PU) |
473 PMURES_BIT(RES4329_PALDO_PU) |
474 PMURES_BIT(RES4329_LNLDO1_PU) |
475 PMURES_BIT(RES4329_XTAL_PU) |
476 PMURES_BIT(RES4329_ALP_AVAIL) |
477 PMURES_BIT(RES4329_RX_PWRSW_PU) |
478 PMURES_BIT(RES4329_TX_PWRSW_PU) |
479 PMURES_BIT(RES4329_RFPLL_PWRSW_PU) |
480 PMURES_BIT(RES4329_LOGEN_PWRSW_PU) |
481 PMURES_BIT(RES4329_AFE_PWRSW_PU) |
482 PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL}
485 static const pmu_res_updown_t bcm4319a0_res_updown_qt[] = {
487 RES4319_HT_AVAIL, 0x0101}, {
488 RES4319_XTAL_PU, 0x0100}, {
489 RES4319_LNLDO1_PU, 0x0100}, {
490 RES4319_PALDO_PU, 0x0100}, {
491 RES4319_CLDO_PU, 0x0100}, {
492 RES4319_CBUCK_PWM, 0x0100}, {
493 RES4319_CBUCK_BURST, 0x0100}, {
494 RES4319_CBUCK_LPOM, 0x0100}
497 static const pmu_res_updown_t bcm4319a0_res_updown[] = {
499 RES4319_XTAL_PU, 0x3f01}
502 static const pmu_res_depend_t bcm4319a0_res_depend[] = {
503 /* Adjust OTP PU resource dependencies - not need PALDO unless write */
505 PMURES_BIT(RES4319_OTP_PU),
507 PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo},
508 /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */
510 PMURES_BIT(RES4319_HT_AVAIL),
512 PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo},
513 /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
515 PMURES_BIT(RES4319_HT_AVAIL),
517 PMURES_BIT(RES4319_RX_PWRSW_PU) |
518 PMURES_BIT(RES4319_TX_PWRSW_PU) |
519 PMURES_BIT(RES4319_RFPLL_PWRSW_PU) |
520 PMURES_BIT(RES4319_LOGEN_PWRSW_PU) |
521 PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL}
524 static const pmu_res_updown_t bcm4336a0_res_updown_qt[] = {
526 RES4336_HT_AVAIL, 0x0101}, {
527 RES4336_XTAL_PU, 0x0100}, {
528 RES4336_CLDO_PU, 0x0100}, {
529 RES4336_CBUCK_PWM, 0x0100}, {
530 RES4336_CBUCK_BURST, 0x0100}, {
531 RES4336_CBUCK_LPOM, 0x0100}
534 static const pmu_res_updown_t bcm4336a0_res_updown[] = {
536 RES4336_HT_AVAIL, 0x0D01}
539 static const pmu_res_depend_t bcm4336a0_res_depend[] = {
540 /* Just a dummy entry for now */
542 PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL}
545 static const pmu_res_updown_t bcm4330a0_res_updown_qt[] = {
547 RES4330_HT_AVAIL, 0x0101}, {
548 RES4330_XTAL_PU, 0x0100}, {
549 RES4330_CLDO_PU, 0x0100}, {
550 RES4330_CBUCK_PWM, 0x0100}, {
551 RES4330_CBUCK_BURST, 0x0100}, {
552 RES4330_CBUCK_LPOM, 0x0100}
555 static const pmu_res_updown_t bcm4330a0_res_updown[] = {
557 RES4330_HT_AVAIL, 0x0e02}
560 static const pmu_res_depend_t bcm4330a0_res_depend[] = {
561 /* Just a dummy entry for now */
563 PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL}
566 /* TRUE if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
567 static bool BCMATTACHFN(si_pmu_res_depfltr_bb) (si_t *sih)
569 return (sih->boardflags & BFL_BUCKBOOST) != 0;
572 /* TRUE if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
573 static bool BCMATTACHFN(si_pmu_res_depfltr_ncb) (si_t *sih)
576 return (sih->boardflags & BFL_NOCBUCK) != 0;
579 /* TRUE if the power topology uses the PALDO */
580 static bool BCMATTACHFN(si_pmu_res_depfltr_paldo) (si_t *sih)
582 return (sih->boardflags & BFL_PALDO) != 0;
585 /* TRUE if the power topology doesn't use the PALDO */
586 static bool BCMATTACHFN(si_pmu_res_depfltr_npaldo) (si_t *sih)
588 return (sih->boardflags & BFL_PALDO) == 0;
591 #define BCM94325_BBVDDIOSD_BOARDS(sih) (sih->boardtype == BCM94325DEVBU_BOARD || \
592 sih->boardtype == BCM94325BGABU_BOARD)
594 /* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
595 static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
597 u32 min_mask = 0, max_mask = 0;
602 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
604 /* determine min/max rsrc masks */
605 switch (CHIPID(sih->chip)) {
606 case BCM43224_CHIP_ID:
607 case BCM43225_CHIP_ID:
608 case BCM43421_CHIP_ID:
609 case BCM43235_CHIP_ID:
610 case BCM43236_CHIP_ID:
611 case BCM43238_CHIP_ID:
612 case BCM4331_CHIP_ID:
613 case BCM6362_CHIP_ID:
617 case BCM4329_CHIP_ID:
618 /* 4329 spedific issue. Needs to come back this issue later */
619 /* Down to save the power. */
621 PMURES_BIT(RES4329_CBUCK_LPOM) |
622 PMURES_BIT(RES4329_CLDO_PU);
623 /* Allow (but don't require) PLL to turn on */
626 case BCM4319_CHIP_ID:
627 /* We only need a few resources to be kept on all the time */
628 min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
629 PMURES_BIT(RES4319_CLDO_PU);
631 /* Allow everything else to be turned on upon requests */
632 max_mask = ~(~0 << rsrcs);
634 case BCM4336_CHIP_ID:
635 /* Down to save the power. */
637 PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU)
638 | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU)
639 | PMURES_BIT(RES4336_DIS_INT_RESET_PD);
640 /* Allow (but don't require) PLL to turn on */
641 max_mask = 0x1ffffff;
644 case BCM4330_CHIP_ID:
645 /* Down to save the power. */
647 PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU)
648 | PMURES_BIT(RES4330_DIS_INT_RESET_PD) |
649 PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU);
650 /* Allow (but don't require) PLL to turn on */
651 max_mask = 0xfffffff;
654 case BCM4313_CHIP_ID:
655 min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
656 PMURES_BIT(RES4313_XTAL_PU_RSRC) |
657 PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
658 PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
665 /* Apply nvram override to min mask */
666 val = getvar(NULL, "rmin");
668 PMU_MSG(("Applying rmin=%s to min_mask\n", val));
669 min_mask = (u32) simple_strtoul(val, NULL, 0);
671 /* Apply nvram override to max mask */
672 val = getvar(NULL, "rmax");
674 PMU_MSG(("Applying rmax=%s to max_mask\n", val));
675 max_mask = (u32) simple_strtoul(val, NULL, 0);
682 /* initialize PMU resources */
683 void BCMATTACHFN(si_pmu_res_init) (si_t *sih, osl_t *osh)
687 const pmu_res_updown_t *pmu_res_updown_table = NULL;
688 uint pmu_res_updown_table_sz = 0;
689 const pmu_res_depend_t *pmu_res_depend_table = NULL;
690 uint pmu_res_depend_table_sz = 0;
691 u32 min_mask = 0, max_mask = 0;
695 ASSERT(sih->cccaps & CC_CAP_PMU);
697 /* Remember original core before switch to chipc */
698 origidx = si_coreidx(sih);
699 cc = si_setcoreidx(sih, SI_CC_IDX);
702 switch (CHIPID(sih->chip)) {
703 case BCM4329_CHIP_ID:
704 /* Optimize resources up/down timers */
705 if (ISSIM_ENAB(sih)) {
706 pmu_res_updown_table = NULL;
707 pmu_res_updown_table_sz = 0;
709 pmu_res_updown_table = bcm4329_res_updown;
710 pmu_res_updown_table_sz = ARRAY_SIZE(bcm4329_res_updown);
712 /* Optimize resources dependencies */
713 pmu_res_depend_table = bcm4329_res_depend;
714 pmu_res_depend_table_sz = ARRAY_SIZE(bcm4329_res_depend);
717 case BCM4319_CHIP_ID:
718 /* Optimize resources up/down timers */
719 if (ISSIM_ENAB(sih)) {
720 pmu_res_updown_table = bcm4319a0_res_updown_qt;
721 pmu_res_updown_table_sz =
722 ARRAY_SIZE(bcm4319a0_res_updown_qt);
724 pmu_res_updown_table = bcm4319a0_res_updown;
725 pmu_res_updown_table_sz =
726 ARRAY_SIZE(bcm4319a0_res_updown);
728 /* Optimize resources dependancies masks */
729 pmu_res_depend_table = bcm4319a0_res_depend;
730 pmu_res_depend_table_sz = ARRAY_SIZE(bcm4319a0_res_depend);
733 case BCM4336_CHIP_ID:
734 /* Optimize resources up/down timers */
735 if (ISSIM_ENAB(sih)) {
736 pmu_res_updown_table = bcm4336a0_res_updown_qt;
737 pmu_res_updown_table_sz =
738 ARRAY_SIZE(bcm4336a0_res_updown_qt);
740 pmu_res_updown_table = bcm4336a0_res_updown;
741 pmu_res_updown_table_sz =
742 ARRAY_SIZE(bcm4336a0_res_updown);
744 /* Optimize resources dependancies masks */
745 pmu_res_depend_table = bcm4336a0_res_depend;
746 pmu_res_depend_table_sz = ARRAY_SIZE(bcm4336a0_res_depend);
749 case BCM4330_CHIP_ID:
750 /* Optimize resources up/down timers */
751 if (ISSIM_ENAB(sih)) {
752 pmu_res_updown_table = bcm4330a0_res_updown_qt;
753 pmu_res_updown_table_sz =
754 ARRAY_SIZE(bcm4330a0_res_updown_qt);
756 pmu_res_updown_table = bcm4330a0_res_updown;
757 pmu_res_updown_table_sz =
758 ARRAY_SIZE(bcm4330a0_res_updown);
760 /* Optimize resources dependancies masks */
761 pmu_res_depend_table = bcm4330a0_res_depend;
762 pmu_res_depend_table_sz = ARRAY_SIZE(bcm4330a0_res_depend);
770 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
772 /* Program up/down timers */
773 while (pmu_res_updown_table_sz--) {
774 ASSERT(pmu_res_updown_table != NULL);
775 PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n",
776 pmu_res_updown_table[pmu_res_updown_table_sz].resnum,
777 pmu_res_updown_table[pmu_res_updown_table_sz].updown));
778 W_REG(osh, &cc->res_table_sel,
779 pmu_res_updown_table[pmu_res_updown_table_sz].resnum);
780 W_REG(osh, &cc->res_updn_timer,
781 pmu_res_updown_table[pmu_res_updown_table_sz].updown);
783 /* Apply nvram overrides to up/down timers */
784 for (i = 0; i < rsrcs; i++) {
785 snprintf(name, sizeof(name), "r%dt", i);
786 val = getvar(NULL, name);
789 PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name,
791 W_REG(osh, &cc->res_table_sel, (u32) i);
792 W_REG(osh, &cc->res_updn_timer,
793 (u32) simple_strtoul(val, NULL, 0));
796 /* Program resource dependencies table */
797 while (pmu_res_depend_table_sz--) {
798 ASSERT(pmu_res_depend_table != NULL);
799 if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL
800 && !(pmu_res_depend_table[pmu_res_depend_table_sz].
803 for (i = 0; i < rsrcs; i++) {
804 if ((pmu_res_depend_table[pmu_res_depend_table_sz].
805 res_mask & PMURES_BIT(i)) == 0)
807 W_REG(osh, &cc->res_table_sel, i);
808 switch (pmu_res_depend_table[pmu_res_depend_table_sz].
811 PMU_MSG(("Changing rsrc %d res_dep_mask to 0x%x\n", i, pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask));
812 W_REG(osh, &cc->res_dep_mask,
814 [pmu_res_depend_table_sz].depend_mask);
817 PMU_MSG(("Adding 0x%x to rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i));
818 OR_REG(osh, &cc->res_dep_mask,
820 [pmu_res_depend_table_sz].depend_mask);
822 case RES_DEPEND_REMOVE:
823 PMU_MSG(("Removing 0x%x from rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i));
824 AND_REG(osh, &cc->res_dep_mask,
825 ~pmu_res_depend_table
826 [pmu_res_depend_table_sz].depend_mask);
834 /* Apply nvram overrides to dependancies masks */
835 for (i = 0; i < rsrcs; i++) {
836 snprintf(name, sizeof(name), "r%dd", i);
837 val = getvar(NULL, name);
840 PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val,
842 W_REG(osh, &cc->res_table_sel, (u32) i);
843 W_REG(osh, &cc->res_dep_mask,
844 (u32) simple_strtoul(val, NULL, 0));
847 /* Determine min/max rsrc masks */
848 si_pmu_res_masks(sih, &min_mask, &max_mask);
850 /* It is required to program max_mask first and then min_mask */
852 /* Program max resource mask */
855 PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask));
856 W_REG(osh, &cc->max_res_mask, max_mask);
859 /* Program min resource mask */
862 PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask));
863 W_REG(osh, &cc->min_res_mask, min_mask);
866 /* Add some delay; allow resources to come up and settle. */
869 /* Return to original core */
870 si_setcoreidx(sih, origidx);
873 /* setup pll and query clock speed */
881 /* the following table is based on 880Mhz fvco */
882 static const pmu0_xtaltab0_t BCMINITDATA(pmu0_xtaltab0)[] = {
884 12000, 1, 73, 349525}, {
885 13000, 2, 67, 725937}, {
886 14400, 3, 61, 116508}, {
887 15360, 4, 57, 305834}, {
888 16200, 5, 54, 336579}, {
889 16800, 6, 52, 399457}, {
890 19200, 7, 45, 873813}, {
891 19800, 8, 44, 466033}, {
893 25000, 10, 70, 419430}, {
894 26000, 11, 67, 725937}, {
895 30000, 12, 58, 699050}, {
896 38400, 13, 45, 873813}, {
901 #define PMU0_XTAL0_DEFAULT 8
903 /* setup pll and query clock speed */
913 static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880_4329)[] = {
915 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
916 13000, 2, 1, 6, 0xb, 0x483483}, {
917 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
918 15360, 4, 1, 5, 0xb, 0x755555}, {
919 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
920 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
921 19200, 7, 1, 4, 0xb, 0x755555}, {
922 19800, 8, 1, 11, 0x4, 0xA57EB}, {
923 20000, 9, 1, 11, 0x4, 0x0}, {
924 24000, 10, 3, 11, 0xa, 0x0}, {
925 25000, 11, 5, 16, 0xb, 0x0}, {
926 26000, 12, 1, 1, 0x21, 0xD89D89}, {
927 30000, 13, 3, 8, 0xb, 0x0}, {
928 37400, 14, 3, 1, 0x46, 0x969696}, {
929 38400, 15, 1, 1, 0x16, 0xEAAAAA}, {
930 40000, 16, 1, 2, 0xb, 0}, {
934 /* the following table is based on 880Mhz fvco */
935 static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880)[] = {
937 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
938 13000, 2, 1, 6, 0xb, 0x483483}, {
939 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
940 15360, 4, 1, 5, 0xb, 0x755555}, {
941 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
942 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
943 19200, 7, 1, 4, 0xb, 0x755555}, {
944 19800, 8, 1, 11, 0x4, 0xA57EB}, {
945 20000, 9, 1, 11, 0x4, 0x0}, {
946 24000, 10, 3, 11, 0xa, 0x0}, {
947 25000, 11, 5, 16, 0xb, 0x0}, {
948 26000, 12, 1, 2, 0x10, 0xEC4EC4}, {
949 30000, 13, 3, 8, 0xb, 0x0}, {
950 33600, 14, 1, 2, 0xd, 0x186186}, {
951 38400, 15, 1, 2, 0xb, 0x755555}, {
952 40000, 16, 1, 2, 0xb, 0}, {
956 #define PMU1_XTALTAB0_880_12000K 0
957 #define PMU1_XTALTAB0_880_13000K 1
958 #define PMU1_XTALTAB0_880_14400K 2
959 #define PMU1_XTALTAB0_880_15360K 3
960 #define PMU1_XTALTAB0_880_16200K 4
961 #define PMU1_XTALTAB0_880_16800K 5
962 #define PMU1_XTALTAB0_880_19200K 6
963 #define PMU1_XTALTAB0_880_19800K 7
964 #define PMU1_XTALTAB0_880_20000K 8
965 #define PMU1_XTALTAB0_880_24000K 9
966 #define PMU1_XTALTAB0_880_25000K 10
967 #define PMU1_XTALTAB0_880_26000K 11
968 #define PMU1_XTALTAB0_880_30000K 12
969 #define PMU1_XTALTAB0_880_37400K 13
970 #define PMU1_XTALTAB0_880_38400K 14
971 #define PMU1_XTALTAB0_880_40000K 15
973 /* the following table is based on 1760Mhz fvco */
974 static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1760)[] = {
976 12000, 1, 3, 44, 0x9, 0xFFFFEF}, {
977 13000, 2, 1, 12, 0xb, 0x483483}, {
978 14400, 3, 1, 20, 0xa, 0x1C71C7}, {
979 15360, 4, 1, 10, 0xb, 0x755555}, {
980 16200, 5, 1, 20, 0x5, 0x6E9E06}, {
981 16800, 6, 1, 20, 0x5, 0x3Cf3Cf}, {
982 19200, 7, 1, 18, 0x5, 0x17B425}, {
983 19800, 8, 1, 22, 0x4, 0xA57EB}, {
984 20000, 9, 1, 22, 0x4, 0x0}, {
985 24000, 10, 3, 22, 0xa, 0x0}, {
986 25000, 11, 5, 32, 0xb, 0x0}, {
987 26000, 12, 1, 4, 0x10, 0xEC4EC4}, {
988 30000, 13, 3, 16, 0xb, 0x0}, {
989 38400, 14, 1, 10, 0x4, 0x955555}, {
990 40000, 15, 1, 4, 0xb, 0}, {
995 #define PMU1_XTALTAB0_1760_12000K 0
996 #define PMU1_XTALTAB0_1760_13000K 1
997 #define PMU1_XTALTAB0_1760_14400K 2
998 #define PMU1_XTALTAB0_1760_15360K 3
999 #define PMU1_XTALTAB0_1760_16200K 4
1000 #define PMU1_XTALTAB0_1760_16800K 5
1001 #define PMU1_XTALTAB0_1760_19200K 6
1002 #define PMU1_XTALTAB0_1760_19800K 7
1003 #define PMU1_XTALTAB0_1760_20000K 8
1004 #define PMU1_XTALTAB0_1760_24000K 9
1005 #define PMU1_XTALTAB0_1760_25000K 10
1006 #define PMU1_XTALTAB0_1760_26000K 11
1007 #define PMU1_XTALTAB0_1760_30000K 12
1008 #define PMU1_XTALTAB0_1760_38400K 13
1009 #define PMU1_XTALTAB0_1760_40000K 14
1011 /* the following table is based on 1440Mhz fvco */
1012 static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_1440)[] = {
1014 12000, 1, 1, 1, 0x78, 0x0}, {
1015 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, {
1016 14400, 3, 1, 1, 0x64, 0x0}, {
1017 15360, 4, 1, 1, 0x5D, 0xC00000}, {
1018 16200, 5, 1, 1, 0x58, 0xE38E38}, {
1019 16800, 6, 1, 1, 0x55, 0xB6DB6D}, {
1020 19200, 7, 1, 1, 0x4B, 0}, {
1021 19800, 8, 1, 1, 0x48, 0xBA2E8B}, {
1022 20000, 9, 1, 1, 0x48, 0x0}, {
1023 25000, 10, 1, 1, 0x39, 0x999999}, {
1024 26000, 11, 1, 1, 0x37, 0x627627}, {
1025 30000, 12, 1, 1, 0x30, 0x0}, {
1026 37400, 13, 2, 1, 0x4D, 0x15E76}, {
1027 38400, 13, 2, 1, 0x4B, 0x0}, {
1028 40000, 14, 2, 1, 0x48, 0x0}, {
1029 48000, 15, 2, 1, 0x3c, 0x0}, {
1034 #define PMU1_XTALTAB0_1440_12000K 0
1035 #define PMU1_XTALTAB0_1440_13000K 1
1036 #define PMU1_XTALTAB0_1440_14400K 2
1037 #define PMU1_XTALTAB0_1440_15360K 3
1038 #define PMU1_XTALTAB0_1440_16200K 4
1039 #define PMU1_XTALTAB0_1440_16800K 5
1040 #define PMU1_XTALTAB0_1440_19200K 6
1041 #define PMU1_XTALTAB0_1440_19800K 7
1042 #define PMU1_XTALTAB0_1440_20000K 8
1043 #define PMU1_XTALTAB0_1440_25000K 9
1044 #define PMU1_XTALTAB0_1440_26000K 10
1045 #define PMU1_XTALTAB0_1440_30000K 11
1046 #define PMU1_XTALTAB0_1440_37400K 12
1047 #define PMU1_XTALTAB0_1440_38400K 13
1048 #define PMU1_XTALTAB0_1440_40000K 14
1049 #define PMU1_XTALTAB0_1440_48000K 15
1051 #define XTAL_FREQ_24000MHZ 24000
1052 #define XTAL_FREQ_30000MHZ 30000
1053 #define XTAL_FREQ_37400MHZ 37400
1054 #define XTAL_FREQ_48000MHZ 48000
1056 static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_960)[] = {
1058 12000, 1, 1, 1, 0x50, 0x0}, {
1059 13000, 2, 1, 1, 0x49, 0xD89D89}, {
1060 14400, 3, 1, 1, 0x42, 0xAAAAAA}, {
1061 15360, 4, 1, 1, 0x3E, 0x800000}, {
1062 16200, 5, 1, 1, 0x39, 0x425ED0}, {
1063 16800, 6, 1, 1, 0x39, 0x249249}, {
1064 19200, 7, 1, 1, 0x32, 0x0}, {
1065 19800, 8, 1, 1, 0x30, 0x7C1F07}, {
1066 20000, 9, 1, 1, 0x30, 0x0}, {
1067 25000, 10, 1, 1, 0x26, 0x666666}, {
1068 26000, 11, 1, 1, 0x24, 0xEC4EC4}, {
1069 30000, 12, 1, 1, 0x20, 0x0}, {
1070 37400, 13, 2, 1, 0x33, 0x563EF9}, {
1071 38400, 14, 2, 1, 0x32, 0x0}, {
1072 40000, 15, 2, 1, 0x30, 0x0}, {
1073 48000, 16, 2, 1, 0x28, 0x0}, {
1078 #define PMU1_XTALTAB0_960_12000K 0
1079 #define PMU1_XTALTAB0_960_13000K 1
1080 #define PMU1_XTALTAB0_960_14400K 2
1081 #define PMU1_XTALTAB0_960_15360K 3
1082 #define PMU1_XTALTAB0_960_16200K 4
1083 #define PMU1_XTALTAB0_960_16800K 5
1084 #define PMU1_XTALTAB0_960_19200K 6
1085 #define PMU1_XTALTAB0_960_19800K 7
1086 #define PMU1_XTALTAB0_960_20000K 8
1087 #define PMU1_XTALTAB0_960_25000K 9
1088 #define PMU1_XTALTAB0_960_26000K 10
1089 #define PMU1_XTALTAB0_960_30000K 11
1090 #define PMU1_XTALTAB0_960_37400K 12
1091 #define PMU1_XTALTAB0_960_38400K 13
1092 #define PMU1_XTALTAB0_960_40000K 14
1093 #define PMU1_XTALTAB0_960_48000K 15
1095 /* select xtal table for each chip */
1096 static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaltab0) (si_t *sih)
1101 switch (CHIPID(sih->chip)) {
1102 case BCM4329_CHIP_ID:
1103 return pmu1_xtaltab0_880_4329;
1104 case BCM4319_CHIP_ID:
1105 return pmu1_xtaltab0_1440;
1106 case BCM4336_CHIP_ID:
1107 return pmu1_xtaltab0_960;
1108 case BCM4330_CHIP_ID:
1109 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1110 return pmu1_xtaltab0_960;
1112 return pmu1_xtaltab0_1440;
1114 PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n",
1115 bcm_chipname(sih->chip, chn, 8)));
1122 /* select default xtal frequency for each chip */
1123 static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaldef0) (si_t *sih)
1129 switch (CHIPID(sih->chip)) {
1130 case BCM4329_CHIP_ID:
1131 /* Default to 38400Khz */
1132 return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K];
1133 case BCM4319_CHIP_ID:
1134 /* Default to 30000Khz */
1135 return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K];
1136 case BCM4336_CHIP_ID:
1137 /* Default to 26000Khz */
1138 return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K];
1139 case BCM4330_CHIP_ID:
1140 /* Default to 37400Khz */
1141 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1142 return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K];
1144 return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K];
1146 PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n",
1147 bcm_chipname(sih->chip, chn, 8)));
1154 /* select default pll fvco for each chip */
1155 static u32 BCMINITFN(si_pmu1_pllfvco0) (si_t *sih)
1161 switch (CHIPID(sih->chip)) {
1162 case BCM4329_CHIP_ID:
1164 case BCM4319_CHIP_ID:
1166 case BCM4336_CHIP_ID:
1168 case BCM4330_CHIP_ID:
1169 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1174 PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n",
1175 bcm_chipname(sih->chip, chn, 8)));
1182 /* query alp/xtal clock frequency */
1184 BCMINITFN(si_pmu1_alpclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc)
1186 const pmu1_xtaltab0_t *xt;
1189 /* Find the frequency in the table */
1190 xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
1191 PCTL_XTALFREQ_SHIFT;
1192 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
1195 /* Could not find it so assign a default value */
1196 if (xt == NULL || xt->fref == 0)
1197 xt = si_pmu1_xtaldef0(sih);
1198 ASSERT(xt != NULL && xt->fref != 0);
1200 return xt->fref * 1000;
1203 /* Set up PLL registers in the PMU as per the crystal speed.
1204 * XtalFreq field in pmucontrol register being 0 indicates the PLL
1205 * is not programmed and the h/w default is assumed to work, in which
1206 * case the xtal frequency is unknown to the s/w so we need to call
1207 * si_pmu1_xtaldef0() wherever it is needed to return a default value.
1210 BCMATTACHFN(si_pmu1_pllinit0) (si_t *sih, osl_t *osh, chipcregs_t *cc,
1212 const pmu1_xtaltab0_t *xt;
1214 u32 buf_strength = 0;
1217 /* Use h/w default PLL config */
1219 PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n"));
1223 /* Find the frequency in the table */
1224 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
1225 if (xt->fref == xtal)
1228 /* Check current PLL state, bail out if it has been programmed or
1229 * we don't know how to program it.
1231 if (xt == NULL || xt->fref == 0) {
1232 PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n", xtal / 1000, xtal % 1000));
1235 /* for 4319 bootloader already programs the PLL but bootloader does not program the
1236 PLL4 and PLL5. So Skip this check for 4319
1238 if ((((R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
1239 PCTL_XTALFREQ_SHIFT) == xt->xf) &&
1240 !((CHIPID(sih->chip) == BCM4319_CHIP_ID)
1241 || (CHIPID(sih->chip) == BCM4330_CHIP_ID))) {
1242 PMU_MSG(("PLL already programmed for %d.%d MHz\n",
1243 xt->fref / 1000, xt->fref % 1000));
1247 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
1248 PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000,
1251 switch (CHIPID(sih->chip)) {
1252 case BCM4329_CHIP_ID:
1253 /* Change the BBPLL drive strength to 8 for all channels */
1254 buf_strength = 0x888888;
1255 AND_REG(osh, &cc->min_res_mask,
1256 ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
1257 PMURES_BIT(RES4329_HT_AVAIL)));
1258 AND_REG(osh, &cc->max_res_mask,
1259 ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
1260 PMURES_BIT(RES4329_HT_AVAIL)));
1261 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1262 PMU_MAX_TRANSITION_DLY);
1263 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1264 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
1265 if (xt->fref == 38400)
1267 else if (xt->fref == 37400)
1269 else if (xt->fref == 26000)
1272 tmp = 0x200005C0; /* Chip Dflt Settings */
1273 W_REG(osh, &cc->pllcontrol_data, tmp);
1274 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
1277 &cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK;
1278 if ((xt->fref == 38400) || (xt->fref == 37400)
1279 || (xt->fref == 26000))
1282 tmp |= 0x25; /* Chip Dflt Settings */
1283 W_REG(osh, &cc->pllcontrol_data, tmp);
1286 case BCM4319_CHIP_ID:
1287 /* Change the BBPLL drive strength to 2 for all channels */
1288 buf_strength = 0x222222;
1290 /* Make sure the PLL is off */
1291 /* WAR65104: Disable the HT_AVAIL resource first and then
1292 * after a delay (more than downtime for HT_AVAIL) remove the
1293 * BBPLL resource; backplane clock moves to ALP from HT.
1295 AND_REG(osh, &cc->min_res_mask,
1296 ~(PMURES_BIT(RES4319_HT_AVAIL)));
1297 AND_REG(osh, &cc->max_res_mask,
1298 ~(PMURES_BIT(RES4319_HT_AVAIL)));
1301 AND_REG(osh, &cc->min_res_mask,
1302 ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
1303 AND_REG(osh, &cc->max_res_mask,
1304 ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
1307 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1308 PMU_MAX_TRANSITION_DLY);
1309 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1310 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
1312 W_REG(osh, &cc->pllcontrol_data, tmp);
1315 case BCM4336_CHIP_ID:
1316 AND_REG(osh, &cc->min_res_mask,
1317 ~(PMURES_BIT(RES4336_HT_AVAIL) |
1318 PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
1319 AND_REG(osh, &cc->max_res_mask,
1320 ~(PMURES_BIT(RES4336_HT_AVAIL) |
1321 PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
1323 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1324 PMU_MAX_TRANSITION_DLY);
1325 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1328 case BCM4330_CHIP_ID:
1329 AND_REG(osh, &cc->min_res_mask,
1330 ~(PMURES_BIT(RES4330_HT_AVAIL) |
1331 PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
1332 AND_REG(osh, &cc->max_res_mask,
1333 ~(PMURES_BIT(RES4330_HT_AVAIL) |
1334 PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
1336 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1337 PMU_MAX_TRANSITION_DLY);
1338 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1345 PMU_MSG(("Done masking\n"));
1347 /* Write p1div and p2div to pllcontrol[0] */
1348 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
1349 tmp = R_REG(osh, &cc->pllcontrol_data) &
1350 ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK);
1353 p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
1355 p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK);
1356 W_REG(osh, &cc->pllcontrol_data, tmp);
1358 if ((CHIPID(sih->chip) == BCM4330_CHIP_ID))
1359 si_pmu_set_4330_plldivs(sih);
1361 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID)
1362 && (CHIPREV(sih->chiprev) == 0)) {
1364 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
1365 tmp = R_REG(osh, &cc->pllcontrol_data);
1366 tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK);
1367 tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL;
1368 W_REG(osh, &cc->pllcontrol_data, tmp);
1370 if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
1371 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
1372 (CHIPID(sih->chip) == BCM4330_CHIP_ID))
1373 ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB;
1375 ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH;
1377 /* Write ndiv_int and ndiv_mode to pllcontrol[2] */
1378 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
1379 tmp = R_REG(osh, &cc->pllcontrol_data) &
1380 ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK);
1383 ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) &
1384 PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode <<
1385 PMU1_PLL0_PC2_NDIV_MODE_SHIFT) &
1386 PMU1_PLL0_PC2_NDIV_MODE_MASK);
1387 W_REG(osh, &cc->pllcontrol_data, tmp);
1389 /* Write ndiv_frac to pllcontrol[3] */
1390 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
1391 tmp = R_REG(osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
1392 tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) &
1393 PMU1_PLL0_PC3_NDIV_FRAC_MASK);
1394 W_REG(osh, &cc->pllcontrol_data, tmp);
1396 /* Write clock driving strength to pllcontrol[5] */
1398 PMU_MSG(("Adjusting PLL buffer drive strength: %x\n",
1401 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
1404 &cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
1405 tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT);
1406 W_REG(osh, &cc->pllcontrol_data, tmp);
1409 PMU_MSG(("Done pll\n"));
1411 /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs
1414 if ((CHIPID(sih->chip) == BCM4319_CHIP_ID)
1415 && (xt->fref != XTAL_FREQ_30000MHZ)) {
1416 W_REG(osh, &cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
1419 &cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK;
1420 if (xt->fref == XTAL_FREQ_24000MHZ) {
1422 (CCTL_4319USB_24MHZ_PLL_SEL <<
1423 CCTL_4319USB_XTAL_SEL_SHIFT);
1424 } else if (xt->fref == XTAL_FREQ_48000MHZ) {
1426 (CCTL_4319USB_48MHZ_PLL_SEL <<
1427 CCTL_4319USB_XTAL_SEL_SHIFT);
1429 W_REG(osh, &cc->chipcontrol_data, tmp);
1432 /* Flush deferred pll control registers writes */
1433 if (sih->pmurev >= 2)
1434 OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
1436 /* Write XtalFreq. Set the divisor also. */
1437 tmp = R_REG(osh, &cc->pmucontrol) &
1438 ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK);
1439 tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) &
1440 PCTL_ILP_DIV_MASK) |
1441 ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
1443 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID)
1444 && CHIPREV(sih->chiprev) == 0) {
1445 /* clear the htstretch before clearing HTReqEn */
1446 AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT);
1447 tmp &= ~PCTL_HT_REQ_EN;
1450 W_REG(osh, &cc->pmucontrol, tmp);
1453 /* query the CPU clock frequency */
1455 BCMINITFN(si_pmu1_cpuclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc)
1459 u32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
1462 u32 FVCO = si_pmu1_pllfvco0(sih);
1464 /* Read m1div from pllcontrol[1] */
1465 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
1466 tmp = R_REG(osh, &cc->pllcontrol_data);
1467 m1div = (tmp & PMU1_PLL0_PC1_M1DIV_MASK) >> PMU1_PLL0_PC1_M1DIV_SHIFT;
1470 /* Read p2div/p1div from pllcontrol[0] */
1471 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
1472 tmp = R_REG(osh, &cc->pllcontrol_data);
1473 p2div = (tmp & PMU1_PLL0_PC0_P2DIV_MASK) >> PMU1_PLL0_PC0_P2DIV_SHIFT;
1474 p1div = (tmp & PMU1_PLL0_PC0_P1DIV_MASK) >> PMU1_PLL0_PC0_P1DIV_SHIFT;
1476 /* Calculate fvco based on xtal freq and ndiv and pdiv */
1477 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
1478 tmp = R_REG(osh, &cc->pllcontrol_data);
1480 (tmp & PMU1_PLL0_PC2_NDIV_INT_MASK) >> PMU1_PLL0_PC2_NDIV_INT_SHIFT;
1482 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
1483 tmp = R_REG(osh, &cc->pllcontrol_data);
1485 (tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >>
1486 PMU1_PLL0_PC3_NDIV_FRAC_SHIFT;
1488 fref = si_pmu1_alpclk0(sih, osh, cc) / 1000;
1490 fvco = (fref * ndiv_int) << 8;
1491 fvco += (fref * (ndiv_frac >> 12)) >> 4;
1492 fvco += (fref * (ndiv_frac & 0xfff)) >> 12;
1499 PMU_MSG(("si_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco));
1504 /* Return ARM/SB clock */
1505 return FVCO / m1div * 1000;
1508 /* initialize PLL */
1509 void BCMATTACHFN(si_pmu_pll_init) (si_t *sih, osl_t *osh, uint xtalfreq)
1517 ASSERT(sih->cccaps & CC_CAP_PMU);
1519 /* Remember original core before switch to chipc */
1520 origidx = si_coreidx(sih);
1521 cc = si_setcoreidx(sih, SI_CC_IDX);
1524 switch (CHIPID(sih->chip)) {
1525 case BCM4329_CHIP_ID:
1528 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
1530 case BCM4313_CHIP_ID:
1531 case BCM43224_CHIP_ID:
1532 case BCM43225_CHIP_ID:
1533 case BCM43421_CHIP_ID:
1534 case BCM43235_CHIP_ID:
1535 case BCM43236_CHIP_ID:
1536 case BCM43238_CHIP_ID:
1537 case BCM4331_CHIP_ID:
1538 case BCM6362_CHIP_ID:
1541 case BCM4319_CHIP_ID:
1542 case BCM4336_CHIP_ID:
1543 case BCM4330_CHIP_ID:
1544 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
1547 PMU_MSG(("No PLL init done for chip %s rev %d pmurev %d\n",
1548 bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1553 #ifdef BCMDBG_FORCEHT
1554 OR_REG(osh, &cc->clk_ctl_st, CCS_FORCEHT);
1557 /* Return to original core */
1558 si_setcoreidx(sih, origidx);
1561 /* query alp/xtal clock frequency */
1562 u32 BCMINITFN(si_pmu_alp_clock) (si_t *sih, osl_t *osh)
1566 u32 clock = ALP_CLOCK;
1571 ASSERT(sih->cccaps & CC_CAP_PMU);
1573 /* Remember original core before switch to chipc */
1574 origidx = si_coreidx(sih);
1575 cc = si_setcoreidx(sih, SI_CC_IDX);
1578 switch (CHIPID(sih->chip)) {
1579 case BCM43224_CHIP_ID:
1580 case BCM43225_CHIP_ID:
1581 case BCM43421_CHIP_ID:
1582 case BCM43235_CHIP_ID:
1583 case BCM43236_CHIP_ID:
1584 case BCM43238_CHIP_ID:
1585 case BCM4331_CHIP_ID:
1586 case BCM6362_CHIP_ID:
1587 case BCM4716_CHIP_ID:
1588 case BCM4748_CHIP_ID:
1589 case BCM47162_CHIP_ID:
1590 case BCM4313_CHIP_ID:
1591 case BCM5357_CHIP_ID:
1593 clock = 20000 * 1000;
1595 case BCM4329_CHIP_ID:
1596 case BCM4319_CHIP_ID:
1597 case BCM4336_CHIP_ID:
1598 case BCM4330_CHIP_ID:
1600 clock = si_pmu1_alpclk0(sih, osh, cc);
1602 case BCM5356_CHIP_ID:
1604 clock = 25000 * 1000;
1607 PMU_MSG(("No ALP clock specified "
1608 "for chip %s rev %d pmurev %d, using default %d Hz\n",
1609 bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1610 sih->pmurev, clock));
1614 /* Return to original core */
1615 si_setcoreidx(sih, origidx);
1619 /* Find the output of the "m" pll divider given pll controls that start with
1620 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
1623 BCMINITFN(si_pmu5_clock) (si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0,
1625 u32 tmp, div, ndiv, p1, p2, fc;
1627 if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) {
1628 PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0));
1632 /* Strictly there is an m5 divider, but I'm not sure we use it */
1633 if ((m == 0) || (m > 4)) {
1634 PMU_ERROR(("%s: Bad m divider: %d\n", __func__, m));
1638 if (CHIPID(sih->chip) == BCM5357_CHIP_ID) {
1639 /* Detect failure in clock setting */
1640 if ((R_REG(osh, &cc->chipstatus) & 0x40000) != 0) {
1641 return 133 * 1000000;
1645 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF);
1646 (void)R_REG(osh, &cc->pllcontrol_addr);
1647 tmp = R_REG(osh, &cc->pllcontrol_data);
1648 p1 = (tmp & PMU5_PLL_P1_MASK) >> PMU5_PLL_P1_SHIFT;
1649 p2 = (tmp & PMU5_PLL_P2_MASK) >> PMU5_PLL_P2_SHIFT;
1651 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF);
1652 (void)R_REG(osh, &cc->pllcontrol_addr);
1653 tmp = R_REG(osh, &cc->pllcontrol_data);
1654 div = (tmp >> ((m - 1) * PMU5_PLL_MDIV_WIDTH)) & PMU5_PLL_MDIV_MASK;
1656 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF);
1657 (void)R_REG(osh, &cc->pllcontrol_addr);
1658 tmp = R_REG(osh, &cc->pllcontrol_data);
1659 ndiv = (tmp & PMU5_PLL_NDIV_MASK) >> PMU5_PLL_NDIV_SHIFT;
1661 /* Do calculation in Mhz */
1662 fc = si_pmu_alp_clock(sih, osh) / 1000000;
1663 fc = (p1 * ndiv * fc) / p2;
1665 PMU_NONE(("%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n",
1666 __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div));
1668 /* Return clock in Hertz */
1669 return (fc / div) * 1000000;
1672 /* query backplane clock frequency */
1673 /* For designs that feed the same clock to both backplane
1674 * and CPU just return the CPU clock speed.
1676 u32 BCMINITFN(si_pmu_si_clock) (si_t *sih, osl_t *osh)
1680 u32 clock = HT_CLOCK;
1685 ASSERT(sih->cccaps & CC_CAP_PMU);
1687 /* Remember original core before switch to chipc */
1688 origidx = si_coreidx(sih);
1689 cc = si_setcoreidx(sih, SI_CC_IDX);
1692 switch (CHIPID(sih->chip)) {
1693 case BCM43224_CHIP_ID:
1694 case BCM43225_CHIP_ID:
1695 case BCM43421_CHIP_ID:
1696 case BCM4331_CHIP_ID:
1697 case BCM6362_CHIP_ID:
1698 /* 96MHz backplane clock */
1699 clock = 96000 * 1000;
1701 case BCM4716_CHIP_ID:
1702 case BCM4748_CHIP_ID:
1703 case BCM47162_CHIP_ID:
1705 si_pmu5_clock(sih, osh, cc, PMU4716_MAINPLL_PLL0,
1708 case BCM4329_CHIP_ID:
1709 if (CHIPREV(sih->chiprev) == 0)
1710 clock = 38400 * 1000;
1712 clock = si_pmu1_cpuclk0(sih, osh, cc);
1714 case BCM4319_CHIP_ID:
1715 case BCM4336_CHIP_ID:
1716 case BCM4330_CHIP_ID:
1717 clock = si_pmu1_cpuclk0(sih, osh, cc);
1719 case BCM4313_CHIP_ID:
1720 /* 80MHz backplane clock */
1721 clock = 80000 * 1000;
1723 case BCM43235_CHIP_ID:
1724 case BCM43236_CHIP_ID:
1725 case BCM43238_CHIP_ID:
1727 (cc->chipstatus & CST43236_BP_CLK) ? (120000 *
1731 case BCM5356_CHIP_ID:
1733 si_pmu5_clock(sih, osh, cc, PMU5356_MAINPLL_PLL0,
1736 case BCM5357_CHIP_ID:
1738 si_pmu5_clock(sih, osh, cc, PMU5357_MAINPLL_PLL0,
1742 PMU_MSG(("No backplane clock specified "
1743 "for chip %s rev %d pmurev %d, using default %d Hz\n",
1744 bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1745 sih->pmurev, clock));
1749 /* Return to original core */
1750 si_setcoreidx(sih, origidx);
1754 /* query CPU clock frequency */
1755 u32 BCMINITFN(si_pmu_cpu_clock) (si_t *sih, osl_t *osh)
1761 ASSERT(sih->cccaps & CC_CAP_PMU);
1763 if ((sih->pmurev >= 5) &&
1764 !((CHIPID(sih->chip) == BCM4329_CHIP_ID) ||
1765 (CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
1766 (CHIPID(sih->chip) == BCM43236_CHIP_ID) ||
1767 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
1768 (CHIPID(sih->chip) == BCM4330_CHIP_ID))) {
1771 switch (CHIPID(sih->chip)) {
1772 case BCM5356_CHIP_ID:
1773 pll = PMU5356_MAINPLL_PLL0;
1775 case BCM5357_CHIP_ID:
1776 pll = PMU5357_MAINPLL_PLL0;
1779 pll = PMU4716_MAINPLL_PLL0;
1783 /* Remember original core before switch to chipc */
1784 origidx = si_coreidx(sih);
1785 cc = si_setcoreidx(sih, SI_CC_IDX);
1788 clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_CPU);
1790 /* Return to original core */
1791 si_setcoreidx(sih, origidx);
1793 clock = si_pmu_si_clock(sih, osh);
1798 /* query memory clock frequency */
1799 u32 BCMINITFN(si_pmu_mem_clock) (si_t *sih, osl_t *osh)
1805 ASSERT(sih->cccaps & CC_CAP_PMU);
1807 if ((sih->pmurev >= 5) &&
1808 !((CHIPID(sih->chip) == BCM4329_CHIP_ID) ||
1809 (CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
1810 (CHIPID(sih->chip) == BCM4330_CHIP_ID) ||
1811 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
1812 (CHIPID(sih->chip) == BCM43236_CHIP_ID))) {
1815 switch (CHIPID(sih->chip)) {
1816 case BCM5356_CHIP_ID:
1817 pll = PMU5356_MAINPLL_PLL0;
1819 case BCM5357_CHIP_ID:
1820 pll = PMU5357_MAINPLL_PLL0;
1823 pll = PMU4716_MAINPLL_PLL0;
1827 /* Remember original core before switch to chipc */
1828 origidx = si_coreidx(sih);
1829 cc = si_setcoreidx(sih, SI_CC_IDX);
1832 clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_MEM);
1834 /* Return to original core */
1835 si_setcoreidx(sih, origidx);
1837 clock = si_pmu_si_clock(sih, osh);
1843 /* Measure ILP clock frequency */
1844 #define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */
1846 static u32 ilpcycles_per_sec;
1848 u32 BCMINITFN(si_pmu_ilp_clock) (si_t *sih, osl_t *osh)
1850 if (ISSIM_ENAB(sih))
1853 if (ilpcycles_per_sec == 0) {
1854 u32 start, end, delta;
1855 u32 origidx = si_coreidx(sih);
1856 chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
1858 start = R_REG(osh, &cc->pmutimer);
1859 OSL_DELAY(ILP_CALC_DUR * 1000);
1860 end = R_REG(osh, &cc->pmutimer);
1861 delta = end - start;
1862 ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
1863 si_setcoreidx(sih, origidx);
1866 return ilpcycles_per_sec;
1869 /* SDIO Pad drive strength to select value mappings */
1871 u8 strength; /* Pad Drive Strength in mA */
1872 u8 sel; /* Chip-specific select value */
1873 } sdiod_drive_str_t;
1875 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
1876 static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab1)[] = {
1884 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
1885 static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab2)[] = {
1896 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
1897 static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab3)[] = {
1909 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
1912 BCMINITFN(si_sdiod_drive_strength_init) (si_t *sih, osl_t *osh,
1913 u32 drivestrength) {
1915 uint origidx, intr_val = 0;
1916 sdiod_drive_str_t *str_tab = NULL;
1923 if (!(sih->cccaps & CC_CAP_PMU)) {
1927 /* Remember original core before switch to chipc */
1928 cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
1931 switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) {
1932 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
1933 str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1;
1934 str_mask = 0x30000000;
1937 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
1938 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
1939 str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2;
1940 str_mask = 0x00003800;
1943 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
1944 str_tab = (sdiod_drive_str_t *) &sdiod_drive_strength_tab3;
1945 str_mask = 0x00003800;
1950 PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev));
1955 if (str_tab != NULL) {
1956 u32 drivestrength_sel = 0;
1960 for (i = 0; str_tab[i].strength != 0; i++) {
1961 if (drivestrength >= str_tab[i].strength) {
1962 drivestrength_sel = str_tab[i].sel;
1967 W_REG(osh, &cc->chipcontrol_addr, 1);
1968 cc_data_temp = R_REG(osh, &cc->chipcontrol_data);
1969 cc_data_temp &= ~str_mask;
1970 drivestrength_sel <<= str_shift;
1971 cc_data_temp |= drivestrength_sel;
1972 W_REG(osh, &cc->chipcontrol_data, cc_data_temp);
1974 PMU_MSG(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
1975 drivestrength, cc_data_temp));
1978 /* Return to original core */
1979 si_restore_core(sih, origidx, intr_val);
1982 /* initialize PMU */
1983 void BCMATTACHFN(si_pmu_init) (si_t *sih, osl_t *osh)
1988 ASSERT(sih->cccaps & CC_CAP_PMU);
1990 /* Remember original core before switch to chipc */
1991 origidx = si_coreidx(sih);
1992 cc = si_setcoreidx(sih, SI_CC_IDX);
1995 if (sih->pmurev == 1)
1996 AND_REG(osh, &cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
1997 else if (sih->pmurev >= 2)
1998 OR_REG(osh, &cc->pmucontrol, PCTL_NOILP_ON_WAIT);
2000 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
2001 /* Fix for 4329b0 bad LPOM state. */
2002 W_REG(osh, &cc->regcontrol_addr, 2);
2003 OR_REG(osh, &cc->regcontrol_data, 0x100);
2005 W_REG(osh, &cc->regcontrol_addr, 3);
2006 OR_REG(osh, &cc->regcontrol_data, 0x4);
2009 /* Return to original core */
2010 si_setcoreidx(sih, origidx);
2013 /* Return up time in ILP cycles for the given resource. */
2015 BCMINITFN(si_pmu_res_uptime) (si_t *sih, osl_t *osh, chipcregs_t *cc,
2018 uint up, i, dup, dmax;
2019 u32 min_mask = 0, max_mask = 0;
2021 /* uptime of resource 'rsrc' */
2022 W_REG(osh, &cc->res_table_sel, rsrc);
2023 up = (R_REG(osh, &cc->res_updn_timer) >> 8) & 0xff;
2025 /* direct dependancies of resource 'rsrc' */
2026 deps = si_pmu_res_deps(sih, osh, cc, PMURES_BIT(rsrc), FALSE);
2027 for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2028 if (!(deps & PMURES_BIT(i)))
2030 deps &= ~si_pmu_res_deps(sih, osh, cc, PMURES_BIT(i), TRUE);
2032 si_pmu_res_masks(sih, &min_mask, &max_mask);
2035 /* max uptime of direct dependancies */
2037 for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2038 if (!(deps & PMURES_BIT(i)))
2040 dup = si_pmu_res_uptime(sih, osh, cc, (u8) i);
2045 PMU_MSG(("si_pmu_res_uptime: rsrc %u uptime %u(deps 0x%08x uptime %u)\n", rsrc, up, deps, dmax));
2047 return up + dmax + PMURES_UP_TRANSITION;
2050 /* Return dependancies (direct or all/indirect) for the given resources */
2052 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 rsrcs,
2058 for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2059 if (!(rsrcs & PMURES_BIT(i)))
2061 W_REG(osh, &cc->res_table_sel, i);
2062 deps |= R_REG(osh, &cc->res_dep_mask);
2065 return !all ? deps : (deps
2067 si_pmu_res_deps(sih, osh, cc, deps,
2071 /* power up/down OTP through PMU resources */
2072 void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on)
2076 u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
2078 ASSERT(sih->cccaps & CC_CAP_PMU);
2080 /* Don't do anything if OTP is disabled */
2081 if (si_is_otp_disabled(sih)) {
2082 PMU_MSG(("si_pmu_otp_power: OTP is disabled\n"));
2086 /* Remember original core before switch to chipc */
2087 origidx = si_coreidx(sih);
2088 cc = si_setcoreidx(sih, SI_CC_IDX);
2091 switch (CHIPID(sih->chip)) {
2092 case BCM4329_CHIP_ID:
2093 rsrcs = PMURES_BIT(RES4329_OTP_PU);
2095 case BCM4319_CHIP_ID:
2096 rsrcs = PMURES_BIT(RES4319_OTP_PU);
2098 case BCM4336_CHIP_ID:
2099 rsrcs = PMURES_BIT(RES4336_OTP_PU);
2101 case BCM4330_CHIP_ID:
2102 rsrcs = PMURES_BIT(RES4330_OTP_PU);
2111 /* Figure out the dependancies (exclude min_res_mask) */
2112 u32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, TRUE);
2113 u32 min_mask = 0, max_mask = 0;
2114 si_pmu_res_masks(sih, &min_mask, &max_mask);
2116 /* Turn on/off the power */
2118 PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n",
2120 OR_REG(osh, &cc->min_res_mask, (rsrcs | deps));
2121 SPINWAIT(!(R_REG(osh, &cc->res_state) & rsrcs),
2122 PMU_MAX_TRANSITION_DLY);
2123 ASSERT(R_REG(osh, &cc->res_state) & rsrcs);
2125 PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n",
2127 AND_REG(osh, &cc->min_res_mask, ~(rsrcs | deps));
2130 SPINWAIT((((otps = R_REG(osh, &cc->otpstatus)) & OTPS_READY) !=
2131 (on ? OTPS_READY : 0)), 100);
2132 ASSERT((otps & OTPS_READY) == (on ? OTPS_READY : 0));
2133 if ((otps & OTPS_READY) != (on ? OTPS_READY : 0))
2134 PMU_MSG(("OTP ready bit not %s after wait\n",
2135 (on ? "ON" : "OFF")));
2138 /* Return to original core */
2139 si_setcoreidx(sih, origidx);
2142 void si_pmu_rcal(si_t *sih, osl_t *osh)
2147 ASSERT(sih->cccaps & CC_CAP_PMU);
2149 /* Remember original core before switch to chipc */
2150 origidx = si_coreidx(sih);
2151 cc = si_setcoreidx(sih, SI_CC_IDX);
2154 switch (CHIPID(sih->chip)) {
2155 case BCM4329_CHIP_ID:{
2160 W_REG(osh, &cc->chipcontrol_addr, 1);
2162 /* Power Down RCAL Block */
2163 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
2165 /* Power Up RCAL block */
2166 OR_REG(osh, &cc->chipcontrol_data, 0x04);
2168 /* Wait for completion */
2169 SPINWAIT(0 == (R_REG(osh, &cc->chipstatus) & 0x08),
2171 ASSERT(R_REG(osh, &cc->chipstatus) & 0x08);
2173 /* Drop the LSB to convert from 5 bit code to 4 bit code */
2175 (u8) (R_REG(osh, &cc->chipstatus) >> 5) & 0x0f;
2177 PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n",
2178 R_REG(osh, &cc->chipstatus), rcal_code));
2180 /* Write RCal code into pmu_vreg_ctrl[32:29] */
2181 W_REG(osh, &cc->regcontrol_addr, 0);
2185 regcontrol_data) & ~((u32) 0x07 << 29);
2186 val |= (u32) (rcal_code & 0x07) << 29;
2187 W_REG(osh, &cc->regcontrol_data, val);
2188 W_REG(osh, &cc->regcontrol_addr, 1);
2189 val = R_REG(osh, &cc->regcontrol_data) & ~(u32) 0x01;
2190 val |= (u32) ((rcal_code >> 3) & 0x01);
2191 W_REG(osh, &cc->regcontrol_data, val);
2193 /* Write RCal code into pmu_chip_ctrl[33:30] */
2194 W_REG(osh, &cc->chipcontrol_addr, 0);
2198 chipcontrol_data) & ~((u32) 0x03 << 30);
2199 val |= (u32) (rcal_code & 0x03) << 30;
2200 W_REG(osh, &cc->chipcontrol_data, val);
2201 W_REG(osh, &cc->chipcontrol_addr, 1);
2203 R_REG(osh, &cc->chipcontrol_data) & ~(u32) 0x03;
2204 val |= (u32) ((rcal_code >> 2) & 0x03);
2205 W_REG(osh, &cc->chipcontrol_data, val);
2207 /* Set override in pmu_chip_ctrl[29] */
2208 W_REG(osh, &cc->chipcontrol_addr, 0);
2209 OR_REG(osh, &cc->chipcontrol_data, (0x01 << 29));
2211 /* Power off RCal block */
2212 W_REG(osh, &cc->chipcontrol_addr, 1);
2213 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
2221 /* Return to original core */
2222 si_setcoreidx(sih, origidx);
2225 void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid)
2228 uint origidx, intr_val;
2231 /* Remember original core before switch to chipc */
2232 cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
2236 /* force the HT off */
2237 if (CHIPID(sih->chip) == BCM4336_CHIP_ID) {
2238 tmp = R_REG(osh, &cc->max_res_mask);
2239 tmp &= ~RES4336_HT_AVAIL;
2240 W_REG(osh, &cc->max_res_mask, tmp);
2241 /* wait for the ht to really go away */
2242 SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0),
2244 ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0);
2247 /* update the pll changes */
2248 si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
2250 /* enable HT back on */
2251 if (CHIPID(sih->chip) == BCM4336_CHIP_ID) {
2252 tmp = R_REG(osh, &cc->max_res_mask);
2253 tmp |= RES4336_HT_AVAIL;
2254 W_REG(osh, &cc->max_res_mask, tmp);
2257 /* Return to original core */
2258 si_restore_core(sih, origidx, intr_val);
2262 si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh,
2266 u8 phypll_offset = 0;
2267 u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
2268 u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
2270 switch (CHIPID(sih->chip)) {
2271 case BCM5357_CHIP_ID:
2272 case BCM43235_CHIP_ID:
2273 case BCM43236_CHIP_ID:
2274 case BCM43238_CHIP_ID:
2276 /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */
2277 phypll_offset = (CHIPID(sih->chip) == BCM5357_CHIP_ID) ? 6 : 0;
2279 /* RMW only the P1 divider */
2280 W_REG(osh, &cc->pllcontrol_addr,
2281 PMU1_PLL0_PLLCTL0 + phypll_offset);
2282 tmp = R_REG(osh, &cc->pllcontrol_data);
2283 tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK));
2285 (bcm5357_bcm43236_p1div[spuravoid] <<
2286 PMU1_PLL0_PC0_P1DIV_SHIFT);
2287 W_REG(osh, &cc->pllcontrol_data, tmp);
2289 /* RMW only the int feedback divider */
2290 W_REG(osh, &cc->pllcontrol_addr,
2291 PMU1_PLL0_PLLCTL2 + phypll_offset);
2292 tmp = R_REG(osh, &cc->pllcontrol_data);
2293 tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK);
2295 (bcm5357_bcm43236_ndiv[spuravoid]) <<
2296 PMU1_PLL0_PC2_NDIV_INT_SHIFT;
2297 W_REG(osh, &cc->pllcontrol_data, tmp);
2302 case BCM4331_CHIP_ID:
2303 if (spuravoid == 2) {
2304 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2305 W_REG(osh, &cc->pllcontrol_data, 0x11500014);
2306 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2307 W_REG(osh, &cc->pllcontrol_data, 0x0FC00a08);
2308 } else if (spuravoid == 1) {
2309 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2310 W_REG(osh, &cc->pllcontrol_data, 0x11500014);
2311 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2312 W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
2314 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2315 W_REG(osh, &cc->pllcontrol_data, 0x11100014);
2316 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2317 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2322 case BCM43224_CHIP_ID:
2323 case BCM43225_CHIP_ID:
2324 case BCM43421_CHIP_ID:
2325 case BCM6362_CHIP_ID:
2326 if (spuravoid == 1) {
2327 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2328 W_REG(osh, &cc->pllcontrol_data, 0x11500010);
2329 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2330 W_REG(osh, &cc->pllcontrol_data, 0x000C0C06);
2331 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2332 W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
2333 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2334 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2335 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2336 W_REG(osh, &cc->pllcontrol_data, 0x2001E920);
2337 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2338 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2340 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2341 W_REG(osh, &cc->pllcontrol_data, 0x11100010);
2342 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2343 W_REG(osh, &cc->pllcontrol_data, 0x000c0c06);
2344 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2345 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2346 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2347 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2348 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2349 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2350 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2351 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2356 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2357 W_REG(osh, &cc->pllcontrol_data, 0x11100008);
2358 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2359 W_REG(osh, &cc->pllcontrol_data, 0x0c000c06);
2360 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2361 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2362 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2363 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2364 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2365 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2366 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2367 W_REG(osh, &cc->pllcontrol_data, 0x88888855);
2372 case BCM4716_CHIP_ID:
2373 case BCM4748_CHIP_ID:
2374 case BCM47162_CHIP_ID:
2375 if (spuravoid == 1) {
2376 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2377 W_REG(osh, &cc->pllcontrol_data, 0x11500060);
2378 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2379 W_REG(osh, &cc->pllcontrol_data, 0x080C0C06);
2380 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2381 W_REG(osh, &cc->pllcontrol_data, 0x0F600000);
2382 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2383 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2384 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2385 W_REG(osh, &cc->pllcontrol_data, 0x2001E924);
2386 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2387 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2389 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2390 W_REG(osh, &cc->pllcontrol_data, 0x11100060);
2391 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2392 W_REG(osh, &cc->pllcontrol_data, 0x080c0c06);
2393 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2394 W_REG(osh, &cc->pllcontrol_data, 0x03000000);
2395 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2396 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2397 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2398 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2399 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2400 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2406 case BCM4319_CHIP_ID:
2407 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2408 W_REG(osh, &cc->pllcontrol_data, 0x11100070);
2409 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2410 W_REG(osh, &cc->pllcontrol_data, 0x1014140a);
2411 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2412 W_REG(osh, &cc->pllcontrol_data, 0x88888854);
2414 if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */
2415 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2416 W_REG(osh, &cc->pllcontrol_data, 0x05201828);
2417 } else { /* enable 40/80/160Mhz clock mode */
2418 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2419 W_REG(osh, &cc->pllcontrol_data, 0x05001828);
2422 case BCM4336_CHIP_ID:
2423 /* Looks like these are only for default xtal freq 26MHz */
2424 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2425 W_REG(osh, &cc->pllcontrol_data, 0x02100020);
2427 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2428 W_REG(osh, &cc->pllcontrol_data, 0x0C0C0C0C);
2430 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2431 W_REG(osh, &cc->pllcontrol_data, 0x01240C0C);
2433 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2434 W_REG(osh, &cc->pllcontrol_data, 0x202C2820);
2436 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2437 W_REG(osh, &cc->pllcontrol_data, 0x88888825);
2439 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2440 if (spuravoid == 1) {
2441 W_REG(osh, &cc->pllcontrol_data, 0x00EC4EC4);
2443 W_REG(osh, &cc->pllcontrol_data, 0x00762762);
2446 tmp = PCTL_PLL_PLLCTL_UPD;
2450 PMU_ERROR(("%s: unknown spuravoidance settings for chip %s, not changing PLL\n", __func__, bcm_chipname(sih->chip, chn, 8)));
2454 tmp |= R_REG(osh, &cc->pmucontrol);
2455 W_REG(osh, &cc->pmucontrol, tmp);
2458 bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh)
2464 /* Remember original core before switch to chipc */
2465 idx = si_coreidx(sih);
2466 cc = si_setcoreidx(sih, SI_CC_IDX);
2469 switch (CHIPID(sih->chip)) {
2470 case BCM4329_CHIP_ID:
2471 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4329_OTP_PU))
2474 case BCM4319_CHIP_ID:
2475 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4319_OTP_PU))
2478 case BCM4336_CHIP_ID:
2479 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4336_OTP_PU))
2482 case BCM4330_CHIP_ID:
2483 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4330_OTP_PU))
2487 /* These chip doesn't use PMU bit to power up/down OTP. OTP always on.
2488 * Use OTP_INIT command to reset/refresh state.
2490 case BCM43224_CHIP_ID:
2491 case BCM43225_CHIP_ID:
2492 case BCM43421_CHIP_ID:
2493 case BCM43236_CHIP_ID:
2494 case BCM43235_CHIP_ID:
2495 case BCM43238_CHIP_ID:
2503 /* Return to original core */
2504 si_setcoreidx(sih, idx);
2510 si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
2512 BCMATTACHFN(si_pmu_sprom_enable) (si_t *sih, osl_t *osh, bool enable)
2518 /* Remember original core before switch to chipc */
2519 origidx = si_coreidx(sih);
2520 cc = si_setcoreidx(sih, SI_CC_IDX);
2523 /* Return to original core */
2524 si_setcoreidx(sih, origidx);
2527 /* initialize PMU chip controls and other chip level stuff */
2528 void BCMATTACHFN(si_pmu_chip_init) (si_t *sih, osl_t *osh)
2532 ASSERT(sih->cccaps & CC_CAP_PMU);
2534 #ifdef CHIPC_UART_ALWAYS_ON
2535 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, clk_ctl_st),
2536 CCS_FORCEALP, CCS_FORCEALP);
2537 #endif /* CHIPC_UART_ALWAYS_ON */
2539 /* Gate off SPROM clock and chip select signals */
2540 si_pmu_sprom_enable(sih, osh, FALSE);
2542 /* Remember original core */
2543 origidx = si_coreidx(sih);
2545 /* Return to original core */
2546 si_setcoreidx(sih, origidx);
2549 /* initialize PMU switch/regulators */
2550 void BCMATTACHFN(si_pmu_swreg_init) (si_t *sih, osl_t *osh)
2552 ASSERT(sih->cccaps & CC_CAP_PMU);
2554 switch (CHIPID(sih->chip)) {
2555 case BCM4336_CHIP_ID:
2556 /* Reduce CLDO PWM output voltage to 1.2V */
2557 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
2558 /* Reduce CLDO BURST output voltage to 1.2V */
2559 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST,
2561 /* Reduce LNLDO1 output voltage to 1.2V */
2562 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe);
2563 if (CHIPREV(sih->chiprev) == 0)
2564 si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
2567 case BCM4330_CHIP_ID:
2568 /* CBUCK Voltage is 1.8 by default and set that to 1.5 */
2569 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
2576 void si_pmu_radio_enable(si_t *sih, bool enable)
2578 ASSERT(sih->cccaps & CC_CAP_PMU);
2580 switch (CHIPID(sih->chip)) {
2581 case BCM4319_CHIP_ID:
2583 si_write_wrapperreg(sih, AI_OOBSELOUTB74,
2586 si_write_wrapperreg(sih, AI_OOBSELOUTB74,
2592 /* Wait for a particular clock level to be on the backplane */
2594 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, u32 clk,
2600 ASSERT(sih->cccaps & CC_CAP_PMU);
2602 /* Remember original core before switch to chipc */
2603 origidx = si_coreidx(sih);
2604 cc = si_setcoreidx(sih, SI_CC_IDX);
2608 SPINWAIT(((R_REG(osh, &cc->pmustatus) & clk) != clk), delay);
2610 /* Return to original core */
2611 si_setcoreidx(sih, origidx);
2613 return R_REG(osh, &cc->pmustatus) & clk;
2617 * Measures the ALP clock frequency in KHz. Returns 0 if not possible.
2618 * Possible only if PMU rev >= 10 and there is an external LPO 32768Hz crystal.
2621 #define EXT_ILP_HZ 32768
2623 u32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh)
2629 if (sih->pmurev < 10)
2632 ASSERT(sih->cccaps & CC_CAP_PMU);
2634 /* Remember original core before switch to chipc */
2635 origidx = si_coreidx(sih);
2636 cc = si_setcoreidx(sih, SI_CC_IDX);
2639 if (R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL) {
2640 u32 ilp_ctr, alp_hz;
2642 /* Enable the reg to measure the freq, in case disabled before */
2643 W_REG(osh, &cc->pmu_xtalfreq,
2644 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
2646 /* Delay for well over 4 ILP clocks */
2649 /* Read the latched number of ALP ticks per 4 ILP ticks */
2652 &cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
2654 /* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT bit to save power */
2655 W_REG(osh, &cc->pmu_xtalfreq, 0);
2657 /* Calculate ALP frequency */
2658 alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
2660 /* Round to nearest 100KHz, and at the same time convert to KHz */
2661 alp_khz = (alp_hz + 50000) / 100000 * 100;
2665 /* Return to original core */
2666 si_setcoreidx(sih, origidx);
2671 static void BCMATTACHFN(si_pmu_set_4330_plldivs) (si_t *sih)
2673 u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
2674 u32 m1div, m2div, m3div, m4div, m5div, m6div;
2677 m2div = m3div = m4div = m6div = FVCO / 80;
2680 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
2685 (m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div <<
2686 PMU1_PLL0_PC1_M2DIV_SHIFT) |
2687 (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div <<
2688 PMU1_PLL0_PC1_M4DIV_SHIFT);
2689 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1);
2691 pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
2692 pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK);
2694 ((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) |
2695 (m6div << PMU1_PLL0_PC2_M6DIV_SHIFT));
2696 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2);