drivers/staging/ccree/cc_hw_queue_defs.h

   1 /*
   2  * Copyright (C) 2012-2017 ARM Limited or its affiliates.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __CC_HW_QUEUE_DEFS_H__
  18 #define __CC_HW_QUEUE_DEFS_H__
  19
  20 #include "cc_pal_log.h"
  21 #include "cc_regs.h"
  22 #include "dx_crys_kernel.h"
  23
  24 #ifdef __KERNEL__
  25 #include <linux/types.h>
  26 #define UINT32_MAX 0xFFFFFFFFL
  27 #define INT32_MAX  0x7FFFFFFFL
  28 #define UINT16_MAX 0xFFFFL
  29 #else
  30 #include <stdint.h>
  31 #endif
  32
  33 /******************************************************************************
  34 *                               DEFINITIONS
  35 ******************************************************************************/
  36
  37
  38 /* Dma AXI Secure bit */
  39 #define AXI_SECURE      0
  40 #define AXI_NOT_SECURE  1
  41
  42 #define HW_DESC_SIZE_WORDS              6
  43 #define HW_QUEUE_SLOTS_MAX              15 /* Max. available slots in HW queue */
  44
  45 #define _HW_DESC_MONITOR_KICK 0x7FFFC00
  46
  47 /******************************************************************************
  48 *                               TYPE DEFINITIONS
  49 ******************************************************************************/
  50
  51 typedef struct HwDesc {
  52         uint32_t word[HW_DESC_SIZE_WORDS];
  53 } HwDesc_s;
  54
  55 typedef enum DescDirection {
  56         DESC_DIRECTION_ILLEGAL = -1,
  57         DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,
  58         DESC_DIRECTION_DECRYPT_DECRYPT = 1,
  59         DESC_DIRECTION_DECRYPT_ENCRYPT = 3,
  60         DESC_DIRECTION_END = INT32_MAX,
  61 }DescDirection_t;
  62
  63 typedef enum DmaMode {
  64         DMA_MODE_NULL           = -1,
  65         NO_DMA                  = 0,
  66         DMA_SRAM                = 1,
  67         DMA_DLLI                = 2,
  68         DMA_MLLI                = 3,
  69         DmaMode_OPTIONTS,
  70         DmaMode_END             = INT32_MAX,
  71 }DmaMode_t;
  72
  73 typedef enum FlowMode {
  74         FLOW_MODE_NULL          = -1,
  75         /* data flows */
  76         BYPASS                  = 0,
  77         DIN_AES_DOUT            = 1,
  78         AES_to_HASH             = 2,
  79         AES_and_HASH            = 3,
  80         DIN_DES_DOUT            = 4,
  81         DES_to_HASH             = 5,
  82         DES_and_HASH            = 6,
  83         DIN_HASH                = 7,
  84         DIN_HASH_and_BYPASS     = 8,
  85         AESMAC_and_BYPASS       = 9,
  86         AES_to_HASH_and_DOUT    = 10,
  87         DIN_RC4_DOUT            = 11,
  88         DES_to_HASH_and_DOUT    = 12,
  89         AES_to_AES_to_HASH_and_DOUT     = 13,
  90         AES_to_AES_to_HASH      = 14,
  91         AES_to_HASH_and_AES     = 15,
  92         DIN_MULTI2_DOUT         = 16,
  93         DIN_AES_AESMAC          = 17,
  94         HASH_to_DOUT            = 18,
  95         /* setup flows */
  96         S_DIN_to_AES            = 32,
  97         S_DIN_to_AES2           = 33,
  98         S_DIN_to_DES            = 34,
  99         S_DIN_to_RC4            = 35,
 100         S_DIN_to_MULTI2         = 36,
 101         S_DIN_to_HASH           = 37,
 102         S_AES_to_DOUT           = 38,
 103         S_AES2_to_DOUT          = 39,
 104         S_RC4_to_DOUT           = 41,
 105         S_DES_to_DOUT           = 42,
 106         S_HASH_to_DOUT          = 43,
 107         SET_FLOW_ID             = 44,
 108         FlowMode_OPTIONTS,
 109         FlowMode_END = INT32_MAX,
 110 }FlowMode_t;
 111
 112 typedef enum TunnelOp {
 113         TUNNEL_OP_INVALID = -1,
 114         TUNNEL_OFF = 0,
 115         TUNNEL_ON = 1,
 116         TunnelOp_OPTIONS,
 117         TunnelOp_END = INT32_MAX,
 118 } TunnelOp_t;
 119
 120 typedef enum SetupOp {
 121         SETUP_LOAD_NOP          = 0,
 122         SETUP_LOAD_STATE0       = 1,
 123         SETUP_LOAD_STATE1       = 2,
 124         SETUP_LOAD_STATE2       = 3,
 125         SETUP_LOAD_KEY0         = 4,
 126         SETUP_LOAD_XEX_KEY      = 5,
 127         SETUP_WRITE_STATE0      = 8,
 128         SETUP_WRITE_STATE1      = 9,
 129         SETUP_WRITE_STATE2      = 10,
 130         SETUP_WRITE_STATE3      = 11,
 131         setupOp_OPTIONTS,
 132         setupOp_END = INT32_MAX,
 133 }SetupOp_t;
 134
 135 enum AesMacSelector {
 136         AES_SK = 1,
 137         AES_CMAC_INIT = 2,
 138         AES_CMAC_SIZE0 = 3,
 139         AesMacEnd = INT32_MAX,
 140 };
 141
 142 #define HW_KEY_MASK_CIPHER_DO     0x3
 143 #define HW_KEY_SHIFT_CIPHER_CFG2  2
 144
 145
 146 /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
 147 /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
 148 typedef enum HwCryptoKey {
 149         USER_KEY = 0,                   /* 0x0000 */
 150         ROOT_KEY = 1,                   /* 0x0001 */
 151         PROVISIONING_KEY = 2,           /* 0x0010 */ /* ==KCP */
 152         SESSION_KEY = 3,                /* 0x0011 */
 153         RESERVED_KEY = 4,               /* NA */
 154         PLATFORM_KEY = 5,               /* 0x0101 */
 155         CUSTOMER_KEY = 6,               /* 0x0110 */
 156         KFDE0_KEY = 7,                  /* 0x0111 */
 157         KFDE1_KEY = 9,                  /* 0x1001 */
 158         KFDE2_KEY = 10,                 /* 0x1010 */
 159         KFDE3_KEY = 11,                 /* 0x1011 */
 160         END_OF_KEYS = INT32_MAX,
 161 }HwCryptoKey_t;
 162
 163 typedef enum HwAesKeySize {
 164         AES_128_KEY = 0,
 165         AES_192_KEY = 1,
 166         AES_256_KEY = 2,
 167         END_OF_AES_KEYS = INT32_MAX,
 168 }HwAesKeySize_t;
 169
 170 typedef enum HwDesKeySize {
 171         DES_ONE_KEY = 0,
 172         DES_TWO_KEYS = 1,
 173         DES_THREE_KEYS = 2,
 174         END_OF_DES_KEYS = INT32_MAX,
 175 }HwDesKeySize_t;
 176
 177 /*****************************/
 178 /* Descriptor packing macros */
 179 /*****************************/
 180
 181 #define GET_HW_Q_DESC_WORD_IDX(descWordIdx) (CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD ## descWordIdx) )
 182
 183 #define HW_DESC_INIT(pDesc)  do { \
 184         (pDesc)->word[0] = 0;     \
 185         (pDesc)->word[1] = 0;     \
 186         (pDesc)->word[2] = 0;     \
 187         (pDesc)->word[3] = 0;     \
 188         (pDesc)->word[4] = 0;     \
 189         (pDesc)->word[5] = 0;     \
 190 } while (0)
 191
 192 /* HW descriptor debug functions */
 193 int createDetailedDump(HwDesc_s *pDesc);
 194 void descriptor_log(HwDesc_s *desc);
 195
 196 #if defined(HW_DESCRIPTOR_LOG) || defined(HW_DESC_DUMP_HOST_BUF)
 197 #define LOG_HW_DESC(pDesc) descriptor_log(pDesc)
 198 #else
 199 #define LOG_HW_DESC(pDesc)
 200 #endif
 201
 202 #if (CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_TRACE) || defined(OEMFW_LOG)
 203
 204 #ifdef UART_PRINTF
 205 #define CREATE_DETAILED_DUMP(pDesc) createDetailedDump(pDesc)
 206 #else
 207 #define CREATE_DETAILED_DUMP(pDesc)
 208 #endif
 209
 210 #define HW_DESC_DUMP(pDesc) do {                                \
 211         CC_PAL_LOG_TRACE("\n---------------------------------------------------\n");    \
 212         CREATE_DETAILED_DUMP(pDesc);                            \
 213         CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[0]);   \
 214         CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[1]);   \
 215         CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[2]);   \
 216         CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[3]);   \
 217         CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[4]);   \
 218         CC_PAL_LOG_TRACE("0x%08X\n", (unsigned int)(pDesc)->word[5]);   \
 219         CC_PAL_LOG_TRACE("---------------------------------------------------\n\n");    \
 220 } while (0)
 221
 222 #else
 223 #define HW_DESC_DUMP(pDesc) do {} while (0)
 224 #endif
 225
 226
 227 /*!
 228  * This macro indicates the end of current HW descriptors flow and release the HW engines.
 229  *
 230  * \param pDesc pointer HW descriptor struct
 231  */
 232 #define HW_DESC_SET_QUEUE_LAST_IND(pDesc)                                                               \
 233         do {                                                                                            \
 234                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1);   \
 235         } while (0)
 236
 237 /*!
 238  * This macro signs the end of HW descriptors flow by asking for completion ack, and release the HW engines
 239  *
 240  * \param pDesc pointer HW descriptor struct
 241  */
 242 #define HW_DESC_SET_ACK_LAST(pDesc)                                                                     \
 243         do {                                                                                            \
 244                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1);   \
 245                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, ACK_NEEDED, (pDesc)->word[4], 1);       \
 246         } while (0)
 247
 248
 249 #define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&UINT16_MAX)
 250
 251 /*!
 252  * This macro sets the DIN field of a HW descriptors
 253  *
 254  * \param pDesc pointer HW descriptor struct
 255  * \param dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
 256  * \param dinAdr DIN address
 257  * \param dinSize Data size in bytes
 258  * \param axiNs AXI secure bit
 259  */
 260 #define HW_DESC_SET_DIN_TYPE(pDesc, dmaMode, dinAdr, dinSize, axiNs)                                                            \
 261         do {                                                                                                                    \
 262                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (dinAdr)&UINT32_MAX );                 \
 263                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DIN_ADDR_HIGH, (pDesc)->word[5], MSB64(dinAdr) );               \
 264                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], (dmaMode));                     \
 265                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));                         \
 266                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NS_BIT, (pDesc)->word[1], (axiNs));                             \
 267         } while (0)
 268
 269
 270 /*!
 271  * This macro sets the DIN field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and
 272  * other special modes
 273  *
 274  * \param pDesc pointer HW descriptor struct
 275  * \param dinAdr DIN address
 276  * \param dinSize Data size in bytes
 277  */
 278 #define HW_DESC_SET_DIN_NO_DMA(pDesc, dinAdr, dinSize)                                                                  \
 279         do {                                                                                                            \
 280                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr));           \
 281                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));                 \
 282         } while (0)
 283
 284 /*!
 285  * This macro sets the DIN field of a HW descriptors to SRAM mode.
 286  * Note: No need to check SRAM alignment since host requests do not use SRAM and
 287  * adaptor will enforce alignment check.
 288  *
 289  * \param pDesc pointer HW descriptor struct
 290  * \param dinAdr DIN address
 291  * \param dinSize Data size in bytes
 292  */
 293 #define HW_DESC_SET_DIN_SRAM(pDesc, dinAdr, dinSize)                                                                    \
 294         do {                                                                                                            \
 295                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr));           \
 296                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM);              \
 297                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));                 \
 298         } while (0)
 299
 300 /*! This macro sets the DIN field of a HW descriptors to CONST mode
 301  *
 302  * \param pDesc pointer HW descriptor struct
 303  * \param val DIN const value
 304  * \param dinSize Data size in bytes
 305  */
 306 #define HW_DESC_SET_DIN_CONST(pDesc, val, dinSize)                                                                      \
 307         do {                                                                                                            \
 308                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(val));              \
 309                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_CONST_VALUE, (pDesc)->word[1], 1);                  \
 310                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM);              \
 311                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));                 \
 312         } while (0)
 313
 314 /*!
 315  * This macro sets the DIN not last input data indicator
 316  *
 317  * \param pDesc pointer HW descriptor struct
 318  */
 319 #define HW_DESC_SET_DIN_NOT_LAST_INDICATION(pDesc)                                                                      \
 320         do {                                                                                                            \
 321                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NOT_LAST, (pDesc)->word[1], 1);                         \
 322         } while (0)
 323
 324 /*!
 325  * This macro sets the DOUT field of a HW descriptors
 326  *
 327  * \param pDesc pointer HW descriptor struct
 328  * \param dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
 329  * \param doutAdr DOUT address
 330  * \param doutSize Data size in bytes
 331  * \param axiNs AXI secure bit
 332  */
 333 #define HW_DESC_SET_DOUT_TYPE(pDesc, dmaMode, doutAdr, doutSize, axiNs)                                                 \
 334         do {                                                                                                            \
 335                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );                \
 336                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );     \
 337                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], (dmaMode));            \
 338                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));               \
 339                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs));                     \
 340         } while (0)
 341
 342 /*!
 343  * This macro sets the DOUT field of a HW descriptors to DLLI type
 344  * The LAST INDICATION is provided by the user
 345  *
 346  * \param pDesc pointer HW descriptor struct
 347  * \param doutAdr DOUT address
 348  * \param doutSize Data size in bytes
 349  * \param lastInd The last indication bit
 350  * \param axiNs AXI secure bit
 351  */
 352 #define HW_DESC_SET_DOUT_DLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd)                                                         \
 353         do {                                                                                                                    \
 354                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );                \
 355                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );     \
 356                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_DLLI);                     \
 357                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));                       \
 358                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd);                      \
 359                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs));                             \
 360         } while (0)
 361
 362 /*!
 363  * This macro sets the DOUT field of a HW descriptors to DLLI type
 364  * The LAST INDICATION is provided by the user
 365  *
 366  * \param pDesc pointer HW descriptor struct
 367  * \param doutAdr DOUT address
 368  * \param doutSize Data size in bytes
 369  * \param lastInd The last indication bit
 370  * \param axiNs AXI secure bit
 371  */
 372 #define HW_DESC_SET_DOUT_MLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd)                                                         \
 373         do {                                                                                                                    \
 374                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );                \
 375                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );     \
 376                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_MLLI);                     \
 377                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));                       \
 378                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd);                      \
 379                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs));                             \
 380         } while (0)
 381
 382 /*!
 383  * This macro sets the DOUT field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and
 384  * other special modes
 385  *
 386  * \param pDesc pointer HW descriptor struct
 387  * \param doutAdr DOUT address
 388  * \param doutSize Data size in bytes
 389  * \param registerWriteEnable Enables a write operation to a register
 390  */
 391 #define HW_DESC_SET_DOUT_NO_DMA(pDesc, doutAdr, doutSize, registerWriteEnable)                                                  \
 392         do {                                                                                                                    \
 393                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr));                  \
 394                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));                       \
 395                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], (registerWriteEnable));        \
 396         } while (0)
 397
 398 /*!
 399  * This macro sets the word for the XOR operation.
 400  *
 401  * \param pDesc pointer HW descriptor struct
 402  * \param xorVal xor data value
 403  */
 404 #define HW_DESC_SET_XOR_VAL(pDesc, xorVal)                                                                              \
 405         do {                                                                                                            \
 406                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(xorVal));           \
 407         } while (0)
 408
 409 /*!
 410  * This macro sets the XOR indicator bit in the descriptor
 411  *
 412  * \param pDesc pointer HW descriptor struct
 413  */
 414 #define HW_DESC_SET_XOR_ACTIVE(pDesc)                                                                                   \
 415         do {                                                                                                            \
 416                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, HASH_XOR_BIT, (pDesc)->word[3], 1);                     \
 417         } while (0)
 418
 419 /*!
 420  * This macro selects the AES engine instead of HASH engine when setting up combined mode with AES XCBC MAC
 421  *
 422  * \param pDesc pointer HW descriptor struct
 423  */
 424 #define HW_DESC_SET_AES_NOT_HASH_MODE(pDesc)                                                                            \
 425         do {                                                                                                            \
 426                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, AES_SEL_N_HASH, (pDesc)->word[4], 1);                   \
 427         } while (0)
 428
 429 /*!
 430  * This macro sets the DOUT field of a HW descriptors to SRAM mode
 431  * Note: No need to check SRAM alignment since host requests do not use SRAM and
 432  * adaptor will enforce alignment check.
 433  *
 434  * \param pDesc pointer HW descriptor struct
 435  * \param doutAdr DOUT address
 436  * \param doutSize Data size in bytes
 437  */
 438 #define HW_DESC_SET_DOUT_SRAM(pDesc, doutAdr, doutSize)                                                                 \
 439         do {                                                                                                            \
 440                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr));          \
 441                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_SRAM);             \
 442                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));               \
 443         } while (0)
 444
 445
 446 /*!
 447  * This macro sets the data unit size for XEX mode in data_out_addr[15:0]
 448  *
 449  * \param pDesc pointer HW descriptor struct
 450  * \param dataUnitSize data unit size for XEX mode
 451  */
 452 #define HW_DESC_SET_XEX_DATA_UNIT_SIZE(pDesc, dataUnitSize)                                                             \
 453         do {                                                                                                            \
 454                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(dataUnitSize));     \
 455         } while (0)
 456
 457 /*!
 458  * This macro sets the number of rounds for Multi2 in data_out_addr[15:0]
 459  *
 460  * \param pDesc pointer HW descriptor struct
 461  * \param numRounds number of rounds for Multi2
 462 */
 463 #define HW_DESC_SET_MULTI2_NUM_ROUNDS(pDesc, numRounds)                                                                 \
 464         do {                                                                                                            \
 465                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(numRounds));        \
 466         } while (0)
 467
 468 /*!
 469  * This macro sets the flow mode.
 470  *
 471  * \param pDesc pointer HW descriptor struct
 472  * \param flowMode Any one of the modes defined in [CC7x-DESC]
 473 */
 474
 475 #define HW_DESC_SET_FLOW_MODE(pDesc, flowMode)                                                                          \
 476         do {                                                                                                            \
 477                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, DATA_FLOW_MODE, (pDesc)->word[4], (flowMode));          \
 478         } while (0)
 479
 480 /*!
 481  * This macro sets the cipher mode.
 482  *
 483  * \param pDesc pointer HW descriptor struct
 484  * \param cipherMode Any one of the modes defined in [CC7x-DESC]
 485 */
 486 #define HW_DESC_SET_CIPHER_MODE(pDesc, cipherMode)                                                                      \
 487         do {                                                                                                            \
 488                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_MODE, (pDesc)->word[4], (cipherMode));           \
 489         } while (0)
 490
 491 /*!
 492  * This macro sets the cipher configuration fields.
 493  *
 494  * \param pDesc pointer HW descriptor struct
 495  * \param cipherConfig Any one of the modes defined in [CC7x-DESC]
 496 */
 497 #define HW_DESC_SET_CIPHER_CONFIG0(pDesc, cipherConfig)                                                                 \
 498         do {                                                                                                            \
 499                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF0, (pDesc)->word[4], (cipherConfig));        \
 500         } while (0)
 501
 502 /*!
 503  * This macro sets the cipher configuration fields.
 504  *
 505  * \param pDesc pointer HW descriptor struct
 506  * \param cipherConfig Any one of the modes defined in [CC7x-DESC]
 507 */
 508 #define HW_DESC_SET_CIPHER_CONFIG1(pDesc, cipherConfig)                                                                 \
 509         do {                                                                                                            \
 510                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF1, (pDesc)->word[4], (cipherConfig));        \
 511         } while (0)
 512
 513 /*!
 514  * This macro sets HW key configuration fields.
 515  *
 516  * \param pDesc pointer HW descriptor struct
 517  * \param hwKey The hw key number as in enun HwCryptoKey
 518 */
 519 #define HW_DESC_SET_HW_CRYPTO_KEY(pDesc, hwKey)                                                                         \
 520         do {                                                                                                            \
 521                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (hwKey)&HW_KEY_MASK_CIPHER_DO);            \
 522                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF2, (pDesc)->word[4], (hwKey>>HW_KEY_SHIFT_CIPHER_CFG2));     \
 523         } while (0)
 524
 525 /*!
 526  * This macro changes the bytes order of all setup-finalize descriptosets.
 527  *
 528  * \param pDesc pointer HW descriptor struct
 529  * \param swapConfig Any one of the modes defined in [CC7x-DESC]
 530 */
 531 #define HW_DESC_SET_BYTES_SWAP(pDesc, swapConfig)                                                                       \
 532         do {                                                                                                            \
 533                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, BYTES_SWAP, (pDesc)->word[4], (swapConfig));            \
 534         } while (0)
 535
 536 /*!
 537  * This macro sets the CMAC_SIZE0 mode.
 538  *
 539  * \param pDesc pointer HW descriptor struct
 540 */
 541 #define HW_DESC_SET_CMAC_SIZE0_MODE(pDesc)                                                                              \
 542         do {                                                                                                            \
 543                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CMAC_SIZE0, (pDesc)->word[4], 0x1);                     \
 544         } while (0)
 545
 546 /*!
 547  * This macro sets the key size for AES engine.
 548  *
 549  * \param pDesc pointer HW descriptor struct
 550  * \param keySize key size in bytes (NOT size code)
 551 */
 552 #define HW_DESC_SET_KEY_SIZE_AES(pDesc, keySize)                                                                        \
 553         do {                                                                                                            \
 554                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, KEY_SIZE, (pDesc)->word[4], ((keySize) >> 3) - 2);      \
 555         } while (0)
 556
 557 /*!
 558  * This macro sets the key size for DES engine.
 559  *
 560  * \param pDesc pointer HW descriptor struct
 561  * \param keySize key size in bytes (NOT size code)
 562 */
 563 #define HW_DESC_SET_KEY_SIZE_DES(pDesc, keySize)                                                                        \
 564         do {                                                                                                            \
 565                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, KEY_SIZE, (pDesc)->word[4], ((keySize) >> 3) - 1);      \
 566         } while (0)
 567
 568 /*!
 569  * This macro sets the descriptor's setup mode
 570  *
 571  * \param pDesc pointer HW descriptor struct
 572  * \param setupMode Any one of the setup modes defined in [CC7x-DESC]
 573 */
 574 #define HW_DESC_SET_SETUP_MODE(pDesc, setupMode)                                                                        \
 575         do {                                                                                                            \
 576                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, SETUP_OPERATION, (pDesc)->word[4], (setupMode));        \
 577         } while (0)
 578
 579 /*!
 580  * This macro sets the descriptor's cipher do
 581  *
 582  * \param pDesc pointer HW descriptor struct
 583  * \param cipherDo Any one of the cipher do defined in [CC7x-DESC]
 584 */
 585 #define HW_DESC_SET_CIPHER_DO(pDesc, cipherDo)                                                                                  \
 586         do {                                                                                                                    \
 587                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (cipherDo)&HW_KEY_MASK_CIPHER_DO); \
 588         } while (0)
 589
 590 /*!
 591  * This macro sets the DIN field of a HW descriptors to star/stop monitor descriptor.
 592  * Used for performance measurements and debug purposes.
 593  *
 594  * \param pDesc pointer HW descriptor struct
 595  */
 596 #define HW_DESC_SET_DIN_MONITOR_CNTR(pDesc)                                                                             \
 597         do {                                                                                                            \
 598                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR, VALUE, (pDesc)->word[1], _HW_DESC_MONITOR_KICK);       \
 599         } while (0)
 600
 601
 602
 603 #endif /*__CC_HW_QUEUE_DEFS_H__*/