3 comedi/drivers/adl_pci9111.c
5 Hardware driver for PCI9111 ADLink cards:
9 Copyright (C) 2002-2005 Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
24 Description: Adlink PCI-9111HR
25 Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>
26 Devices: [ADLink] PCI-9111HR (adl_pci9111)
35 - ai_do_cmd mode with the following sources:
38 - scan_begin_src TRIG_FOLLOW TRIG_TIMER TRIG_EXT
39 - convert_src TRIG_TIMER TRIG_EXT
40 - scan_end_src TRIG_COUNT
41 - stop_src TRIG_COUNT TRIG_NONE
43 The scanned channels must be consecutive and start from 0. They must
44 all have the same range and aref.
46 Configuration options: not applicable, uses PCI auto config
52 2005/02/17 Extend AI streaming capabilities. Now, scan_begin_arg can be
53 a multiple of chanlist_len*convert_arg.
54 2002/02/19 Fixed the two's complement conversion in pci9111_(hr_)ai_get_data.
55 2002/02/18 Added external trigger support for analog input.
59 - Really test implemented functionality.
60 - Add support for the PCI-9111DG with a probe routine to identify
61 the card type (perhaps with the help of the channel number readback
62 of the A/D Data register).
63 - Add external multiplexer support.
67 #include <linux/module.h>
68 #include <linux/pci.h>
69 #include <linux/delay.h>
70 #include <linux/interrupt.h>
72 #include "../comedidev.h"
76 #include "comedi_fc.h"
78 #define PCI9111_FIFO_HALF_SIZE 512
80 #define PCI9111_AI_ACQUISITION_PERIOD_MIN_NS 10000
82 #define PCI9111_RANGE_SETTING_DELAY 10
83 #define PCI9111_AI_INSTANT_READ_UDELAY_US 2
86 * IO address map and bit defines
88 #define PCI9111_AI_FIFO_REG 0x00
89 #define PCI9111_AO_REG 0x00
90 #define PCI9111_DIO_REG 0x02
91 #define PCI9111_EDIO_REG 0x04
92 #define PCI9111_AI_CHANNEL_REG 0x06
93 #define PCI9111_AI_RANGE_STAT_REG 0x08
94 #define PCI9111_AI_STAT_AD_BUSY (1 << 7)
95 #define PCI9111_AI_STAT_FF_FF (1 << 6)
96 #define PCI9111_AI_STAT_FF_HF (1 << 5)
97 #define PCI9111_AI_STAT_FF_EF (1 << 4)
98 #define PCI9111_AI_RANGE_MASK (7 << 0)
99 #define PCI9111_AI_TRIG_CTRL_REG 0x0a
100 #define PCI9111_AI_TRIG_CTRL_TRGEVENT (1 << 5)
101 #define PCI9111_AI_TRIG_CTRL_POTRG (1 << 4)
102 #define PCI9111_AI_TRIG_CTRL_PTRG (1 << 3)
103 #define PCI9111_AI_TRIG_CTRL_ETIS (1 << 2)
104 #define PCI9111_AI_TRIG_CTRL_TPST (1 << 1)
105 #define PCI9111_AI_TRIG_CTRL_ASCAN (1 << 0)
106 #define PCI9111_INT_CTRL_REG 0x0c
107 #define PCI9111_INT_CTRL_ISC2 (1 << 3)
108 #define PCI9111_INT_CTRL_FFEN (1 << 2)
109 #define PCI9111_INT_CTRL_ISC1 (1 << 1)
110 #define PCI9111_INT_CTRL_ISC0 (1 << 0)
111 #define PCI9111_SOFT_TRIG_REG 0x0e
112 #define PCI9111_8254_BASE_REG 0x40
113 #define PCI9111_INT_CLR_REG 0x48
115 /* PLX 9052 Local Interrupt 1 enabled and active */
116 #define PCI9111_LI1_ACTIVE (PLX9052_INTCSR_LI1ENAB | \
117 PLX9052_INTCSR_LI1STAT)
119 /* PLX 9052 Local Interrupt 2 enabled and active */
120 #define PCI9111_LI2_ACTIVE (PLX9052_INTCSR_LI2ENAB | \
121 PLX9052_INTCSR_LI2STAT)
123 static const struct comedi_lrange pci9111_ai_range = {
133 struct pci9111_private_data {
134 unsigned long lcr_io_base;
138 unsigned int scan_delay;
139 unsigned int chunk_counter;
140 unsigned int chunk_num_samples;
145 unsigned short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE];
148 static void plx9050_interrupt_control(unsigned long io_base,
150 bool LINTi1_active_high,
152 bool LINTi2_active_high,
153 bool interrupt_enable)
158 flags |= PLX9052_INTCSR_LI1ENAB;
159 if (LINTi1_active_high)
160 flags |= PLX9052_INTCSR_LI1POL;
162 flags |= PLX9052_INTCSR_LI2ENAB;
163 if (LINTi2_active_high)
164 flags |= PLX9052_INTCSR_LI2POL;
166 if (interrupt_enable)
167 flags |= PLX9052_INTCSR_PCIENAB;
169 outb(flags, io_base + PLX9052_INTCSR);
172 static void pci9111_timer_set(struct comedi_device *dev)
174 struct pci9111_private_data *dev_private = dev->private;
175 unsigned long timer_base = dev->iobase + PCI9111_8254_BASE_REG;
177 i8254_set_mode(timer_base, 1, 0, I8254_MODE0 | I8254_BINARY);
178 i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY);
179 i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY);
183 i8254_write(timer_base, 1, 2, dev_private->div2);
184 i8254_write(timer_base, 1, 1, dev_private->div1);
187 enum pci9111_ISC0_sources {
189 irq_on_fifo_half_full
192 enum pci9111_ISC1_sources {
194 irq_on_external_trigger
197 static void pci9111_interrupt_source_set(struct comedi_device *dev,
198 enum pci9111_ISC0_sources irq_0_source,
199 enum pci9111_ISC1_sources irq_1_source)
203 /* Read the current interrupt control bits */
204 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
205 /* Shift the bits so they are compatible with the write register */
207 /* Mask off the ISCx bits */
210 /* Now set the new ISCx bits */
211 if (irq_0_source == irq_on_fifo_half_full)
212 flags |= PCI9111_INT_CTRL_ISC0;
214 if (irq_1_source == irq_on_external_trigger)
215 flags |= PCI9111_INT_CTRL_ISC1;
217 outb(flags, dev->iobase + PCI9111_INT_CTRL_REG);
220 static void pci9111_fifo_reset(struct comedi_device *dev)
222 unsigned long int_ctrl_reg = dev->iobase + PCI9111_INT_CTRL_REG;
224 /* To reset the FIFO, set FFEN sequence as 0 -> 1 -> 0 */
225 outb(0, int_ctrl_reg);
226 outb(PCI9111_INT_CTRL_FFEN, int_ctrl_reg);
227 outb(0, int_ctrl_reg);
230 static int pci9111_ai_cancel(struct comedi_device *dev,
231 struct comedi_subdevice *s)
233 struct pci9111_private_data *dev_private = dev->private;
235 /* Disable interrupts */
236 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true,
239 /* disable A/D triggers (software trigger mode) and auto scan off */
240 outb(0, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
242 pci9111_fifo_reset(dev);
247 static int pci9111_ai_check_chanlist(struct comedi_device *dev,
248 struct comedi_subdevice *s,
249 struct comedi_cmd *cmd)
251 unsigned int range0 = CR_RANGE(cmd->chanlist[0]);
252 unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
255 for (i = 1; i < cmd->chanlist_len; i++) {
256 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
257 unsigned int range = CR_RANGE(cmd->chanlist[i]);
258 unsigned int aref = CR_AREF(cmd->chanlist[i]);
261 dev_dbg(dev->class_dev,
262 "entries in chanlist must be consecutive channels,counting upwards from 0\n");
266 if (range != range0) {
267 dev_dbg(dev->class_dev,
268 "entries in chanlist must all have the same gain\n");
273 dev_dbg(dev->class_dev,
274 "entries in chanlist must all have the same reference\n");
282 static int pci9111_ai_do_cmd_test(struct comedi_device *dev,
283 struct comedi_subdevice *s,
284 struct comedi_cmd *cmd)
286 struct pci9111_private_data *dev_private = dev->private;
290 /* Step 1 : check if triggers are trivially valid */
292 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
293 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
294 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
295 err |= cfc_check_trigger_src(&cmd->convert_src,
296 TRIG_TIMER | TRIG_EXT);
297 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
298 err |= cfc_check_trigger_src(&cmd->stop_src,
299 TRIG_COUNT | TRIG_NONE);
304 /* Step 2a : make sure trigger sources are unique */
306 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
307 err |= cfc_check_trigger_is_unique(cmd->convert_src);
308 err |= cfc_check_trigger_is_unique(cmd->stop_src);
310 /* Step 2b : and mutually compatible */
312 if (cmd->scan_begin_src != TRIG_FOLLOW) {
313 if (cmd->scan_begin_src != cmd->convert_src)
320 /* Step 3: check if arguments are trivially valid */
322 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
324 if (cmd->convert_src == TRIG_TIMER)
325 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
326 PCI9111_AI_ACQUISITION_PERIOD_MIN_NS);
328 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
330 if (cmd->scan_begin_src == TRIG_TIMER)
331 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
332 PCI9111_AI_ACQUISITION_PERIOD_MIN_NS);
333 else /* TRIG_FOLLOW || TRIG_EXT */
334 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
336 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
338 if (cmd->stop_src == TRIG_COUNT)
339 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
341 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
346 /* Step 4: fix up any arguments */
348 if (cmd->convert_src == TRIG_TIMER) {
349 arg = cmd->convert_arg;
350 i8253_cascade_ns_to_timer(I8254_OSC_BASE_2MHZ,
354 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
358 * There's only one timer on this card, so the scan_begin timer
359 * must be a multiple of chanlist_len*convert_arg
361 if (cmd->scan_begin_src == TRIG_TIMER) {
362 arg = cmd->chanlist_len * cmd->convert_arg;
364 if (arg < cmd->scan_begin_arg)
365 arg *= (cmd->scan_begin_arg / arg);
367 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
373 /* Step 5: check channel list if it exists */
374 if (cmd->chanlist && cmd->chanlist_len > 0)
375 err |= pci9111_ai_check_chanlist(dev, s, cmd);
384 static int pci9111_ai_do_cmd(struct comedi_device *dev,
385 struct comedi_subdevice *s)
387 struct pci9111_private_data *dev_private = dev->private;
388 struct comedi_cmd *cmd = &s->async->cmd;
389 unsigned int last_chan = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
390 unsigned int trig = 0;
392 /* Set channel scan limit */
393 /* PCI9111 allows only scanning from channel 0 to channel n */
394 /* TODO: handle the case of an external multiplexer */
396 if (cmd->chanlist_len > 1)
397 trig |= PCI9111_AI_TRIG_CTRL_ASCAN;
399 outb(last_chan, dev->iobase + PCI9111_AI_CHANNEL_REG);
402 /* This is the same gain on every channel */
404 outb(CR_RANGE(cmd->chanlist[0]) & PCI9111_AI_RANGE_MASK,
405 dev->iobase + PCI9111_AI_RANGE_STAT_REG);
408 if (cmd->stop_src == TRIG_COUNT)
409 dev_private->stop_counter = cmd->stop_arg * cmd->chanlist_len;
411 dev_private->stop_counter = 0;
413 /* Set timer pacer */
414 dev_private->scan_delay = 0;
415 if (cmd->convert_src == TRIG_TIMER) {
416 trig |= PCI9111_AI_TRIG_CTRL_TPST;
417 pci9111_timer_set(dev);
418 pci9111_fifo_reset(dev);
419 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full,
421 plx9050_interrupt_control(dev_private->lcr_io_base, true, true,
424 if (cmd->scan_begin_src == TRIG_TIMER) {
425 dev_private->scan_delay = (cmd->scan_begin_arg /
426 (cmd->convert_arg * cmd->chanlist_len)) - 1;
428 } else { /* TRIG_EXT */
429 trig |= PCI9111_AI_TRIG_CTRL_ETIS;
430 pci9111_fifo_reset(dev);
431 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full,
433 plx9050_interrupt_control(dev_private->lcr_io_base, true, true,
436 outb(trig, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
438 dev_private->stop_counter *= (1 + dev_private->scan_delay);
439 dev_private->chunk_counter = 0;
440 dev_private->chunk_num_samples = cmd->chanlist_len *
441 (1 + dev_private->scan_delay);
446 static void pci9111_ai_munge(struct comedi_device *dev,
447 struct comedi_subdevice *s, void *data,
448 unsigned int num_bytes,
449 unsigned int start_chan_index)
451 unsigned short *array = data;
452 unsigned int maxdata = s->maxdata;
453 unsigned int invert = (maxdata + 1) >> 1;
454 unsigned int shift = (maxdata == 0xffff) ? 0 : 4;
455 unsigned int num_samples = num_bytes / sizeof(short);
458 for (i = 0; i < num_samples; i++)
459 array[i] = ((array[i] >> shift) & maxdata) ^ invert;
462 static void pci9111_handle_fifo_half_full(struct comedi_device *dev,
463 struct comedi_subdevice *s)
465 struct pci9111_private_data *devpriv = dev->private;
466 struct comedi_cmd *cmd = &s->async->cmd;
467 unsigned int total = 0;
468 unsigned int samples;
470 if (cmd->stop_src == TRIG_COUNT &&
471 PCI9111_FIFO_HALF_SIZE > devpriv->stop_counter)
472 samples = devpriv->stop_counter;
474 samples = PCI9111_FIFO_HALF_SIZE;
476 insw(dev->iobase + PCI9111_AI_FIFO_REG,
477 devpriv->ai_bounce_buffer, samples);
479 if (devpriv->scan_delay < 1) {
480 total = comedi_buf_write_samples(s, devpriv->ai_bounce_buffer,
483 unsigned int pos = 0;
484 unsigned int to_read;
486 while (pos < samples) {
487 if (devpriv->chunk_counter < cmd->chanlist_len) {
488 to_read = cmd->chanlist_len -
489 devpriv->chunk_counter;
491 if (to_read > samples - pos)
492 to_read = samples - pos;
494 total += comedi_buf_write_samples(s,
495 devpriv->ai_bounce_buffer + pos,
498 to_read = devpriv->chunk_num_samples -
499 devpriv->chunk_counter;
501 if (to_read > samples - pos)
502 to_read = samples - pos;
504 total += to_read * sizeof(short);
508 devpriv->chunk_counter += to_read;
510 if (devpriv->chunk_counter >=
511 devpriv->chunk_num_samples)
512 devpriv->chunk_counter = 0;
516 devpriv->stop_counter -= total / sizeof(short);
519 static irqreturn_t pci9111_interrupt(int irq, void *p_device)
521 struct comedi_device *dev = p_device;
522 struct pci9111_private_data *dev_private = dev->private;
523 struct comedi_subdevice *s = dev->read_subdev;
524 struct comedi_async *async;
525 struct comedi_cmd *cmd;
527 unsigned long irq_flags;
528 unsigned char intcsr;
530 if (!dev->attached) {
531 /* Ignore interrupt before device fully attached. */
532 /* Might not even have allocated subdevices yet! */
539 spin_lock_irqsave(&dev->spinlock, irq_flags);
541 /* Check if we are source of interrupt */
542 intcsr = inb(dev_private->lcr_io_base + PLX9052_INTCSR);
543 if (!(((intcsr & PLX9052_INTCSR_PCIENAB) != 0) &&
544 (((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) ||
545 ((intcsr & PCI9111_LI2_ACTIVE) == PCI9111_LI2_ACTIVE)))) {
546 /* Not the source of the interrupt. */
547 /* (N.B. not using PLX9052_INTCSR_SOFTINT) */
548 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
552 if ((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) {
553 /* Interrupt comes from fifo_half-full signal */
555 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
557 /* '0' means FIFO is full, data may have been lost */
558 if (!(status & PCI9111_AI_STAT_FF_FF)) {
559 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
560 dev_dbg(dev->class_dev, "fifo overflow\n");
561 outb(0, dev->iobase + PCI9111_INT_CLR_REG);
562 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
563 comedi_handle_events(dev, s);
568 /* '0' means FIFO is half-full */
569 if (!(status & PCI9111_AI_STAT_FF_HF))
570 pci9111_handle_fifo_half_full(dev, s);
573 if (cmd->stop_src == TRIG_COUNT && dev_private->stop_counter == 0)
574 async->events |= COMEDI_CB_EOA;
576 outb(0, dev->iobase + PCI9111_INT_CLR_REG);
578 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
580 comedi_handle_events(dev, s);
585 static int pci9111_ai_eoc(struct comedi_device *dev,
586 struct comedi_subdevice *s,
587 struct comedi_insn *insn,
588 unsigned long context)
592 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
593 if (status & PCI9111_AI_STAT_FF_EF)
598 static int pci9111_ai_insn_read(struct comedi_device *dev,
599 struct comedi_subdevice *s,
600 struct comedi_insn *insn, unsigned int *data)
602 unsigned int chan = CR_CHAN(insn->chanspec);
603 unsigned int range = CR_RANGE(insn->chanspec);
604 unsigned int maxdata = s->maxdata;
605 unsigned int invert = (maxdata + 1) >> 1;
606 unsigned int shift = (maxdata == 0xffff) ? 0 : 4;
611 outb(chan, dev->iobase + PCI9111_AI_CHANNEL_REG);
613 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
614 if ((status & PCI9111_AI_RANGE_MASK) != range) {
615 outb(range & PCI9111_AI_RANGE_MASK,
616 dev->iobase + PCI9111_AI_RANGE_STAT_REG);
619 pci9111_fifo_reset(dev);
621 for (i = 0; i < insn->n; i++) {
622 /* Generate a software trigger */
623 outb(0, dev->iobase + PCI9111_SOFT_TRIG_REG);
625 ret = comedi_timeout(dev, s, insn, pci9111_ai_eoc, 0);
627 pci9111_fifo_reset(dev);
631 data[i] = inw(dev->iobase + PCI9111_AI_FIFO_REG);
632 data[i] = ((data[i] >> shift) & maxdata) ^ invert;
638 static int pci9111_ao_insn_write(struct comedi_device *dev,
639 struct comedi_subdevice *s,
640 struct comedi_insn *insn,
643 unsigned int chan = CR_CHAN(insn->chanspec);
644 unsigned int val = s->readback[chan];
647 for (i = 0; i < insn->n; i++) {
649 outw(val, dev->iobase + PCI9111_AO_REG);
651 s->readback[chan] = val;
656 static int pci9111_di_insn_bits(struct comedi_device *dev,
657 struct comedi_subdevice *s,
658 struct comedi_insn *insn,
661 data[1] = inw(dev->iobase + PCI9111_DIO_REG);
666 static int pci9111_do_insn_bits(struct comedi_device *dev,
667 struct comedi_subdevice *s,
668 struct comedi_insn *insn,
671 if (comedi_dio_update_state(s, data))
672 outw(s->state, dev->iobase + PCI9111_DIO_REG);
679 static int pci9111_reset(struct comedi_device *dev)
681 struct pci9111_private_data *dev_private = dev->private;
683 /* Set trigger source to software */
684 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true,
687 /* disable A/D triggers (software trigger mode) and auto scan off */
688 outb(0, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
690 /* Reset 8254 chip */
691 dev_private->div1 = 0;
692 dev_private->div2 = 0;
693 pci9111_timer_set(dev);
698 static int pci9111_auto_attach(struct comedi_device *dev,
699 unsigned long context_unused)
701 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
702 struct pci9111_private_data *dev_private;
703 struct comedi_subdevice *s;
706 dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private));
710 ret = comedi_pci_enable(dev);
713 dev_private->lcr_io_base = pci_resource_start(pcidev, 1);
714 dev->iobase = pci_resource_start(pcidev, 2);
719 ret = request_irq(pcidev->irq, pci9111_interrupt,
720 IRQF_SHARED, dev->board_name, dev);
722 dev->irq = pcidev->irq;
725 ret = comedi_alloc_subdevices(dev, 4);
729 s = &dev->subdevices[0];
730 s->type = COMEDI_SUBD_AI;
731 s->subdev_flags = SDF_READABLE | SDF_COMMON;
734 s->range_table = &pci9111_ai_range;
735 s->insn_read = pci9111_ai_insn_read;
737 dev->read_subdev = s;
738 s->subdev_flags |= SDF_CMD_READ;
739 s->len_chanlist = s->n_chan;
740 s->do_cmdtest = pci9111_ai_do_cmd_test;
741 s->do_cmd = pci9111_ai_do_cmd;
742 s->cancel = pci9111_ai_cancel;
743 s->munge = pci9111_ai_munge;
746 s = &dev->subdevices[1];
747 s->type = COMEDI_SUBD_AO;
748 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
752 s->range_table = &range_bipolar10;
753 s->insn_write = pci9111_ao_insn_write;
754 s->insn_read = comedi_readback_insn_read;
756 ret = comedi_alloc_subdev_readback(s);
760 s = &dev->subdevices[2];
761 s->type = COMEDI_SUBD_DI;
762 s->subdev_flags = SDF_READABLE;
765 s->range_table = &range_digital;
766 s->insn_bits = pci9111_di_insn_bits;
768 s = &dev->subdevices[3];
769 s->type = COMEDI_SUBD_DO;
770 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
773 s->range_table = &range_digital;
774 s->insn_bits = pci9111_do_insn_bits;
779 static void pci9111_detach(struct comedi_device *dev)
783 comedi_pci_detach(dev);
786 static struct comedi_driver adl_pci9111_driver = {
787 .driver_name = "adl_pci9111",
788 .module = THIS_MODULE,
789 .auto_attach = pci9111_auto_attach,
790 .detach = pci9111_detach,
793 static int pci9111_pci_probe(struct pci_dev *dev,
794 const struct pci_device_id *id)
796 return comedi_pci_auto_config(dev, &adl_pci9111_driver,
800 static const struct pci_device_id pci9111_pci_table[] = {
801 { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, 0x9111) },
802 /* { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HG_DEVICE_ID) }, */
805 MODULE_DEVICE_TABLE(pci, pci9111_pci_table);
807 static struct pci_driver adl_pci9111_pci_driver = {
808 .name = "adl_pci9111",
809 .id_table = pci9111_pci_table,
810 .probe = pci9111_pci_probe,
811 .remove = comedi_pci_auto_unconfig,
813 module_comedi_pci_driver(adl_pci9111_driver, adl_pci9111_pci_driver);
815 MODULE_AUTHOR("Comedi http://www.comedi.org");
816 MODULE_DESCRIPTION("Comedi low-level driver");
817 MODULE_LICENSE("GPL");