2 * comedi/drivers/adv_pci_dio.c
4 * Author: Michal Dobes <dobes@tesnet.cz>
6 * Hardware driver for Advantech PCI DIO cards.
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
22 This driver supports now only insn interface for DI/DO/DIO.
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
36 #include "../comedidev.h"
41 /* hardware types of the cards */
43 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
48 TYPE_PCI1753, TYPE_PCI1753E,
49 TYPE_PCI1754, TYPE_PCI1756,
54 /* which I/O instructions to use */
59 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
60 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
61 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
63 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
65 /* (could be more than one 8254 per
68 #define SIZE_8254 4 /* 8254 IO space length */
69 #define SIZE_8255 4 /* 8255 IO space length */
71 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
73 /* Register offset definitions */
74 /* Advantech PCI-1730/3/4 */
75 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
76 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
77 #define PCI1730_DI 2 /* R: Digital input 0-15 */
78 #define PCI1730_DO 2 /* W: Digital output 0-15 */
79 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
80 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
81 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
83 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
84 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
85 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
87 /* Advantech PCI-1735U */
88 #define PCI1735_DI 0 /* R: Digital input 0-31 */
89 #define PCI1735_DO 0 /* W: Digital output 0-31 */
90 #define PCI1735_C8254 4 /* R/W: 8254 counter */
91 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
93 /* Advantech PCI-1736UP */
94 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
95 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
96 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
97 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
99 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
100 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
101 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
103 /* Advantech PCI-1739U */
104 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
105 #define PCI1739_ICR 32 /* W: Interrupt control register */
106 #define PCI1739_ISR 32 /* R: Interrupt status register */
107 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
109 /* Advantech PCI-1750 */
110 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
111 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
112 #define PCI1750_ICR 32 /* W: Interrupt control register */
113 #define PCI1750_ISR 32 /* R: Interrupt status register */
115 /* Advantech PCI-1751/3/3E */
116 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
117 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
118 #define PCI1751_ICR 32 /* W: Interrupt control register */
119 #define PCI1751_ISR 32 /* R: Interrupt status register */
120 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
121 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
122 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
123 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
124 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
125 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
126 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
127 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
128 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
129 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
131 /* Advantech PCI-1752/4/6 */
132 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
133 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
134 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
135 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
136 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
137 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
138 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
139 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
140 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
141 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
142 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
143 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
145 /* Advantech PCI-1762 registers */
146 #define PCI1762_RO 0 /* R/W: Relays status/output */
147 #define PCI1762_IDI 2 /* R: Isolated input status */
148 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
149 #define PCI1762_ICR 6 /* W: Interrupt control register */
150 #define PCI1762_ISR 6 /* R: Interrupt status register */
152 /* Advantech PCI-1760 registers */
153 #define OMB0 0x0c /* W: Mailbox outgoing registers */
157 #define IMB0 0x1c /* R: Mailbox incoming registers */
161 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
166 /* PCI-1760 mailbox commands */
167 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
168 * DI status in IMB3 */
169 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
170 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
171 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
172 * register in OMB0, result in IMB0 */
173 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
175 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
177 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
179 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
181 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
183 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
185 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
186 * OMB0 to its reset values */
187 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
188 * interrupts based on bits in OMB0 */
189 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
190 * interrupts based on bits in OMB0 */
191 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
192 * - rising, =1 - falling) */
193 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
195 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
197 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
199 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
201 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
203 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
205 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
207 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
209 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
211 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
213 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
215 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
217 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
219 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
221 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
223 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
225 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
228 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
230 struct diosubd_data {
231 int chans; /* num of chans */
232 int addr; /* PCI address ofset */
233 int regs; /* number of registers to read or 8255
234 subdevices or 8254 chips */
235 unsigned int specflags; /* addon subdevice flags */
238 struct dio_boardtype {
239 const char *name; /* board name */
240 int main_pci_region; /* main I/O PCI region */
241 enum hw_cards_id cardtype;
243 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
244 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
245 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
246 struct diosubd_data boardid; /* card supports board ID switch */
247 struct diosubd_data s8254[MAX_8254_SUBDEVS]; /* 8254 subdevices */
248 enum hw_io_access io_access;
251 static const struct dio_boardtype boardtypes[] = {
254 .main_pci_region = PCIDIO_MAINREG,
255 .cardtype = TYPE_PCI1730,
257 .sdi[0] = { 16, PCI1730_DI, 2, 0, },
258 .sdi[1] = { 16, PCI1730_IDI, 2, 0, },
259 .sdo[0] = { 16, PCI1730_DO, 2, 0, },
260 .sdo[1] = { 16, PCI1730_IDO, 2, 0, },
261 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
266 .main_pci_region = PCIDIO_MAINREG,
267 .cardtype = TYPE_PCI1733,
269 .sdi[1] = { 32, PCI1733_IDI, 4, 0, },
270 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
275 .main_pci_region = PCIDIO_MAINREG,
276 .cardtype = TYPE_PCI1734,
278 .sdo[1] = { 32, PCI1734_IDO, 4, 0, },
279 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
284 .main_pci_region = PCIDIO_MAINREG,
285 .cardtype = TYPE_PCI1735,
287 .sdi[0] = { 32, PCI1735_DI, 4, 0, },
288 .sdo[0] = { 32, PCI1735_DO, 4, 0, },
289 .boardid = { 4, PCI1735_BOARDID, 1, SDF_INTERNAL, },
290 .s8254[0] = { 3, PCI1735_C8254, 1, 0, },
295 .main_pci_region = PCI1736_MAINREG,
296 .cardtype = TYPE_PCI1736,
298 .sdi[1] = { 16, PCI1736_IDI, 2, 0, },
299 .sdo[1] = { 16, PCI1736_IDO, 2, 0, },
300 .boardid = { 4, PCI1736_BOARDID, 1, SDF_INTERNAL, },
305 .main_pci_region = PCIDIO_MAINREG,
306 .cardtype = TYPE_PCI1739,
308 .sdio[0] = { 48, PCI1739_DIO, 2, 0, },
313 .main_pci_region = PCIDIO_MAINREG,
314 .cardtype = TYPE_PCI1750,
316 .sdi[1] = { 16, PCI1750_IDI, 2, 0, },
317 .sdo[1] = { 16, PCI1750_IDO, 2, 0, },
322 .main_pci_region = PCIDIO_MAINREG,
323 .cardtype = TYPE_PCI1751,
325 .sdio[0] = { 48, PCI1751_DIO, 2, 0, },
326 .s8254[0] = { 3, PCI1751_CNT, 1, 0, },
331 .main_pci_region = PCIDIO_MAINREG,
332 .cardtype = TYPE_PCI1752,
334 .sdo[0] = { 32, PCI1752_IDO, 2, 0, },
335 .sdo[1] = { 32, PCI1752_IDO2, 2, 0, },
336 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
341 .main_pci_region = PCIDIO_MAINREG,
342 .cardtype = TYPE_PCI1753,
344 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
349 .main_pci_region = PCIDIO_MAINREG,
350 .cardtype = TYPE_PCI1753E,
352 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
353 .sdio[1] = { 96, PCI1753E_DIO, 4, 0, },
358 .main_pci_region = PCIDIO_MAINREG,
359 .cardtype = TYPE_PCI1754,
361 .sdi[0] = { 32, PCI1754_IDI, 2, 0, },
362 .sdi[1] = { 32, PCI1754_IDI2, 2, 0, },
363 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
368 .main_pci_region = PCIDIO_MAINREG,
369 .cardtype = TYPE_PCI1756,
371 .sdi[1] = { 32, PCI1756_IDI, 2, 0, },
372 .sdo[1] = { 32, PCI1756_IDO, 2, 0, },
373 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
377 /* This card has its own 'attach' */
379 .main_pci_region = 0,
380 .cardtype = TYPE_PCI1760,
386 .main_pci_region = PCIDIO_MAINREG,
387 .cardtype = TYPE_PCI1762,
389 .sdi[1] = { 16, PCI1762_IDI, 1, 0, },
390 .sdo[1] = { 16, PCI1762_RO, 1, 0, },
391 .boardid = { 4, PCI1762_BOARDID, 1, SDF_INTERNAL, },
396 struct pci_dio_private {
397 char valid; /* card is usable */
398 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
399 /* PCI-1760 specific data */
400 unsigned char IDICntEnable; /* counter's counting enable status */
401 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
403 unsigned char IDICntMatchEnable; /* counter's match interrupts
405 unsigned char IDICntEdge; /* counter's count edge value
406 * (bit=0 - rising, =1 - falling) */
407 unsigned short CntResValue[8]; /* counters' reset value */
408 unsigned short CntMatchValue[8]; /* counters' match interrupt value */
409 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
410 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
411 unsigned char IDIPatMatchValue; /* IDI's pattern match value */
412 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
413 unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */
417 ==============================================================================
419 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
420 struct comedi_subdevice *s,
421 struct comedi_insn *insn, unsigned int *data)
423 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
427 for (i = 0; i < d->regs; i++)
428 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
435 ==============================================================================
437 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
438 struct comedi_subdevice *s,
439 struct comedi_insn *insn, unsigned int *data)
441 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
445 for (i = 0; i < d->regs; i++)
446 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
452 ==============================================================================
454 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
455 struct comedi_subdevice *s,
456 struct comedi_insn *insn, unsigned int *data)
458 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
462 s->state &= ~data[0];
463 s->state |= (data[0] & data[1]);
464 for (i = 0; i < d->regs; i++)
465 outb((s->state >> (8 * i)) & 0xff,
466 dev->iobase + d->addr + i);
474 ==============================================================================
476 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
477 struct comedi_subdevice *s,
478 struct comedi_insn *insn, unsigned int *data)
480 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
484 s->state &= ~data[0];
485 s->state |= (data[0] & data[1]);
486 for (i = 0; i < d->regs; i++)
487 outw((s->state >> (16 * i)) & 0xffff,
488 dev->iobase + d->addr + 2 * i);
496 ==============================================================================
498 static int pci_8254_insn_read(struct comedi_device *dev,
499 struct comedi_subdevice *s,
500 struct comedi_insn *insn, unsigned int *data)
502 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
503 unsigned int chan, chip, chipchan;
506 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
507 chip = chan / 3; /* chip on subdevice */
508 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
509 spin_lock_irqsave(&s->spin_lock, flags);
510 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip),
512 spin_unlock_irqrestore(&s->spin_lock, flags);
517 ==============================================================================
519 static int pci_8254_insn_write(struct comedi_device *dev,
520 struct comedi_subdevice *s,
521 struct comedi_insn *insn, unsigned int *data)
523 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
524 unsigned int chan, chip, chipchan;
527 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
528 chip = chan / 3; /* chip on subdevice */
529 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
530 spin_lock_irqsave(&s->spin_lock, flags);
531 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip),
532 0, chipchan, data[0]);
533 spin_unlock_irqrestore(&s->spin_lock, flags);
538 ==============================================================================
540 static int pci_8254_insn_config(struct comedi_device *dev,
541 struct comedi_subdevice *s,
542 struct comedi_insn *insn, unsigned int *data)
544 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
545 unsigned int chan, chip, chipchan;
546 unsigned long iobase;
550 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
551 chip = chan / 3; /* chip on subdevice */
552 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
553 iobase = dev->iobase + d->addr + (SIZE_8254 * chip);
554 spin_lock_irqsave(&s->spin_lock, flags);
556 case INSN_CONFIG_SET_COUNTER_MODE:
557 ret = i8254_set_mode(iobase, 0, chipchan, data[1]);
561 case INSN_CONFIG_8254_READ_STATUS:
562 data[1] = i8254_status(iobase, 0, chipchan);
568 spin_unlock_irqrestore(&s->spin_lock, flags);
569 return ret < 0 ? ret : insn->n;
573 ==============================================================================
575 static int pci1760_unchecked_mbxrequest(struct comedi_device *dev,
576 unsigned char *omb, unsigned char *imb,
579 int cnt, tout, ok = 0;
581 for (cnt = 0; cnt < repeats; cnt++) {
582 outb(omb[0], dev->iobase + OMB0);
583 outb(omb[1], dev->iobase + OMB1);
584 outb(omb[2], dev->iobase + OMB2);
585 outb(omb[3], dev->iobase + OMB3);
586 for (tout = 0; tout < 251; tout++) {
587 imb[2] = inb(dev->iobase + IMB2);
588 if (imb[2] == omb[2]) {
589 imb[0] = inb(dev->iobase + IMB0);
590 imb[1] = inb(dev->iobase + IMB1);
591 imb[3] = inb(dev->iobase + IMB3);
601 comedi_error(dev, "PCI-1760 mailbox request timeout!");
605 static int pci1760_clear_imb2(struct comedi_device *dev)
607 unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 };
608 unsigned char imb[4];
609 /* check if imb2 is already clear */
610 if (inb(dev->iobase + IMB2) == CMD_ClearIMB2)
612 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
615 static int pci1760_mbxrequest(struct comedi_device *dev,
616 unsigned char *omb, unsigned char *imb)
618 if (omb[2] == CMD_ClearIMB2) {
620 "bug! this function should not be used for CMD_ClearIMB2 command");
623 if (inb(dev->iobase + IMB2) == omb[2]) {
625 retval = pci1760_clear_imb2(dev);
629 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
633 ==============================================================================
635 static int pci1760_insn_bits_di(struct comedi_device *dev,
636 struct comedi_subdevice *s,
637 struct comedi_insn *insn, unsigned int *data)
639 data[1] = inb(dev->iobase + IMB3);
645 ==============================================================================
647 static int pci1760_insn_bits_do(struct comedi_device *dev,
648 struct comedi_subdevice *s,
649 struct comedi_insn *insn, unsigned int *data)
652 unsigned char omb[4] = {
658 unsigned char imb[4];
661 s->state &= ~data[0];
662 s->state |= (data[0] & data[1]);
664 ret = pci1760_mbxrequest(dev, omb, imb);
674 ==============================================================================
676 static int pci1760_insn_cnt_read(struct comedi_device *dev,
677 struct comedi_subdevice *s,
678 struct comedi_insn *insn, unsigned int *data)
681 unsigned char omb[4] = {
682 CR_CHAN(insn->chanspec) & 0x07,
684 CMD_GetIDICntCurValue,
687 unsigned char imb[4];
689 for (n = 0; n < insn->n; n++) {
690 ret = pci1760_mbxrequest(dev, omb, imb);
693 data[n] = (imb[1] << 8) + imb[0];
700 ==============================================================================
702 static int pci1760_insn_cnt_write(struct comedi_device *dev,
703 struct comedi_subdevice *s,
704 struct comedi_insn *insn, unsigned int *data)
706 struct pci_dio_private *devpriv = dev->private;
708 unsigned char chan = CR_CHAN(insn->chanspec) & 0x07;
709 unsigned char bitmask = 1 << chan;
710 unsigned char omb[4] = {
712 (data[0] >> 8) & 0xff,
713 CMD_SetIDI0CntResetValue + chan,
716 unsigned char imb[4];
718 /* Set reset value if different */
719 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
720 ret = pci1760_mbxrequest(dev, omb, imb);
723 devpriv->CntResValue[chan] = data[0] & 0xffff;
726 omb[0] = bitmask; /* reset counter to it reset value */
727 omb[2] = CMD_ResetIDICounters;
728 ret = pci1760_mbxrequest(dev, omb, imb);
732 /* start counter if it don't run */
733 if (!(bitmask & devpriv->IDICntEnable)) {
735 omb[2] = CMD_EnableIDICounters;
736 ret = pci1760_mbxrequest(dev, omb, imb);
739 devpriv->IDICntEnable |= bitmask;
745 ==============================================================================
747 static int pci1760_reset(struct comedi_device *dev)
749 struct pci_dio_private *devpriv = dev->private;
751 unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 };
752 unsigned char imb[4];
754 outb(0, dev->iobase + INTCSR0); /* disable IRQ */
755 outb(0, dev->iobase + INTCSR1);
756 outb(0, dev->iobase + INTCSR2);
757 outb(0, dev->iobase + INTCSR3);
758 devpriv->GlobalIrqEnabled = 0;
761 omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */
762 pci1760_mbxrequest(dev, omb, imb);
765 omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */
766 pci1760_mbxrequest(dev, omb, imb);
767 devpriv->IDICntEnable = 0;
770 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
772 pci1760_mbxrequest(dev, omb, imb);
773 devpriv->IDICntOverEnable = 0;
776 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
778 pci1760_mbxrequest(dev, omb, imb);
779 devpriv->IDICntMatchEnable = 0;
783 for (i = 0; i < 8; i++) { /* set IDI up counters match value */
784 omb[2] = CMD_SetIDI0CntMatchValue + i;
785 pci1760_mbxrequest(dev, omb, imb);
786 devpriv->CntMatchValue[i] = 0x8000;
791 for (i = 0; i < 8; i++) { /* set IDI up counters reset value */
792 omb[2] = CMD_SetIDI0CntResetValue + i;
793 pci1760_mbxrequest(dev, omb, imb);
794 devpriv->CntResValue[i] = 0x0000;
798 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
800 pci1760_mbxrequest(dev, omb, imb);
803 omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */
804 pci1760_mbxrequest(dev, omb, imb);
805 devpriv->IDICntEdge = 0x00;
808 omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */
809 pci1760_mbxrequest(dev, omb, imb);
810 devpriv->IDIFiltersEn = 0x00;
813 omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */
814 pci1760_mbxrequest(dev, omb, imb);
815 devpriv->IDIPatMatchEn = 0x00;
818 omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */
819 pci1760_mbxrequest(dev, omb, imb);
820 devpriv->IDIPatMatchValue = 0x00;
826 ==============================================================================
828 static int pci_dio_reset(struct comedi_device *dev)
830 const struct dio_boardtype *this_board = comedi_board(dev);
832 switch (this_board->cardtype) {
834 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
835 outb(0, dev->iobase + PCI1730_DO + 1);
836 outb(0, dev->iobase + PCI1730_IDO);
837 outb(0, dev->iobase + PCI1730_IDO + 1);
838 /* NO break there! */
840 /* disable interrupts */
841 outb(0, dev->iobase + PCI1730_3_INT_EN);
842 /* clear interrupts */
843 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
844 /* set rising edge trigger */
845 outb(0, dev->iobase + PCI1730_3_INT_RF);
848 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
849 outb(0, dev->iobase + PCI1734_IDO + 1);
850 outb(0, dev->iobase + PCI1734_IDO + 2);
851 outb(0, dev->iobase + PCI1734_IDO + 3);
854 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
855 outb(0, dev->iobase + PCI1735_DO + 1);
856 outb(0, dev->iobase + PCI1735_DO + 2);
857 outb(0, dev->iobase + PCI1735_DO + 3);
858 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 0, I8254_MODE0);
859 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 1, I8254_MODE0);
860 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 2, I8254_MODE0);
864 outb(0, dev->iobase + PCI1736_IDO);
865 outb(0, dev->iobase + PCI1736_IDO + 1);
866 /* disable interrupts */
867 outb(0, dev->iobase + PCI1736_3_INT_EN);
868 /* clear interrupts */
869 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
870 /* set rising edge trigger */
871 outb(0, dev->iobase + PCI1736_3_INT_RF);
875 /* disable & clear interrupts */
876 outb(0x88, dev->iobase + PCI1739_ICR);
881 /* disable & clear interrupts */
882 outb(0x88, dev->iobase + PCI1750_ICR);
885 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
887 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
888 outw(0, dev->iobase + PCI1752_IDO + 2);
889 outw(0, dev->iobase + PCI1752_IDO2);
890 outw(0, dev->iobase + PCI1752_IDO2 + 2);
893 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
895 outb(0x80, dev->iobase + PCI1753E_ICR1);
896 outb(0x80, dev->iobase + PCI1753E_ICR2);
897 outb(0x80, dev->iobase + PCI1753E_ICR3);
898 /* NO break there! */
900 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
902 outb(0x80, dev->iobase + PCI1753_ICR1);
903 outb(0x80, dev->iobase + PCI1753_ICR2);
904 outb(0x80, dev->iobase + PCI1753_ICR3);
907 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
909 outw(0x08, dev->iobase + PCI1754_6_ICR1);
910 outw(0x08, dev->iobase + PCI1754_ICR2);
911 outw(0x08, dev->iobase + PCI1754_ICR3);
914 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
916 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
918 outw(0x08, dev->iobase + PCI1754_6_ICR1);
919 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
920 outw(0, dev->iobase + PCI1756_IDO + 2);
926 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
935 ==============================================================================
937 static int pci1760_attach(struct comedi_device *dev)
939 struct comedi_subdevice *s;
941 s = &dev->subdevices[0];
942 s->type = COMEDI_SUBD_DI;
943 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
947 s->range_table = &range_digital;
948 s->insn_bits = pci1760_insn_bits_di;
950 s = &dev->subdevices[1];
951 s->type = COMEDI_SUBD_DO;
952 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
956 s->range_table = &range_digital;
958 s->insn_bits = pci1760_insn_bits_do;
960 s = &dev->subdevices[2];
961 s->type = COMEDI_SUBD_TIMER;
962 s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL;
964 s->maxdata = 0xffffffff;
966 /* s->insn_config=pci1760_insn_pwm_cfg; */
968 s = &dev->subdevices[3];
969 s->type = COMEDI_SUBD_COUNTER;
970 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
974 s->insn_read = pci1760_insn_cnt_read;
975 s->insn_write = pci1760_insn_cnt_write;
976 /* s->insn_config=pci1760_insn_cnt_cfg; */
982 ==============================================================================
984 static int pci_dio_add_di(struct comedi_device *dev,
985 struct comedi_subdevice *s,
986 const struct diosubd_data *d)
988 const struct dio_boardtype *this_board = comedi_board(dev);
990 s->type = COMEDI_SUBD_DI;
991 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | d->specflags;
993 s->subdev_flags |= SDF_LSAMPL;
994 s->n_chan = d->chans;
996 s->len_chanlist = d->chans;
997 s->range_table = &range_digital;
998 switch (this_board->io_access) {
1000 s->insn_bits = pci_dio_insn_bits_di_b;
1003 s->insn_bits = pci_dio_insn_bits_di_w;
1006 s->private = (void *)d;
1012 ==============================================================================
1014 static int pci_dio_add_do(struct comedi_device *dev,
1015 struct comedi_subdevice *s,
1016 const struct diosubd_data *d)
1018 const struct dio_boardtype *this_board = comedi_board(dev);
1020 s->type = COMEDI_SUBD_DO;
1021 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1023 s->subdev_flags |= SDF_LSAMPL;
1024 s->n_chan = d->chans;
1026 s->len_chanlist = d->chans;
1027 s->range_table = &range_digital;
1029 switch (this_board->io_access) {
1031 s->insn_bits = pci_dio_insn_bits_do_b;
1034 s->insn_bits = pci_dio_insn_bits_do_w;
1037 s->private = (void *)d;
1043 ==============================================================================
1045 static int pci_dio_add_8254(struct comedi_device *dev,
1046 struct comedi_subdevice *s,
1047 const struct diosubd_data *d)
1049 s->type = COMEDI_SUBD_COUNTER;
1050 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1051 s->n_chan = d->chans;
1053 s->len_chanlist = d->chans;
1054 s->insn_read = pci_8254_insn_read;
1055 s->insn_write = pci_8254_insn_write;
1056 s->insn_config = pci_8254_insn_config;
1057 s->private = (void *)d;
1062 static unsigned long pci_dio_override_cardtype(struct pci_dev *pcidev,
1063 unsigned long cardtype)
1066 * Change cardtype from TYPE_PCI1753 to TYPE_PCI1753E if expansion
1067 * board available. Need to enable PCI device and request the main
1068 * registers PCI BAR temporarily to perform the test.
1070 if (cardtype != TYPE_PCI1753)
1072 if (pci_enable_device(pcidev) < 0)
1074 if (pci_request_region(pcidev, PCIDIO_MAINREG, "adv_pci_dio") == 0) {
1076 * This test is based on Advantech's "advdaq" driver source
1077 * (which declares its module licence as "GPL" although the
1078 * driver source does not include a "COPYING" file).
1081 pci_resource_start(pcidev, PCIDIO_MAINREG) + 53;
1084 if ((inb(reg) & 0x07) == 0x02) {
1086 if ((inb(reg) & 0x07) == 0x05)
1087 cardtype = TYPE_PCI1753E;
1089 pci_release_region(pcidev, PCIDIO_MAINREG);
1091 pci_disable_device(pcidev);
1095 static int pci_dio_auto_attach(struct comedi_device *dev,
1096 unsigned long context)
1098 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1099 const struct dio_boardtype *this_board = NULL;
1100 struct pci_dio_private *devpriv;
1101 struct comedi_subdevice *s;
1102 int ret, subdev, i, j;
1104 if (context < ARRAY_SIZE(boardtypes))
1105 this_board = &boardtypes[context];
1108 dev->board_ptr = this_board;
1109 dev->board_name = this_board->name;
1111 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1115 ret = comedi_pci_enable(dev);
1118 dev->iobase = pci_resource_start(pcidev, this_board->main_pci_region);
1120 ret = comedi_alloc_subdevices(dev, this_board->nsubdevs);
1125 for (i = 0; i < MAX_DI_SUBDEVS; i++)
1126 if (this_board->sdi[i].chans) {
1127 s = &dev->subdevices[subdev];
1128 pci_dio_add_di(dev, s, &this_board->sdi[i]);
1132 for (i = 0; i < MAX_DO_SUBDEVS; i++)
1133 if (this_board->sdo[i].chans) {
1134 s = &dev->subdevices[subdev];
1135 pci_dio_add_do(dev, s, &this_board->sdo[i]);
1139 for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1140 for (j = 0; j < this_board->sdio[i].regs; j++) {
1141 s = &dev->subdevices[subdev];
1142 subdev_8255_init(dev, s, NULL,
1144 this_board->sdio[i].addr +
1149 if (this_board->boardid.chans) {
1150 s = &dev->subdevices[subdev];
1151 s->type = COMEDI_SUBD_DI;
1152 pci_dio_add_di(dev, s, &this_board->boardid);
1156 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1157 if (this_board->s8254[i].chans) {
1158 s = &dev->subdevices[subdev];
1159 pci_dio_add_8254(dev, s, &this_board->s8254[i]);
1163 if (this_board->cardtype == TYPE_PCI1760)
1164 pci1760_attach(dev);
1173 static void pci_dio_detach(struct comedi_device *dev)
1175 struct pci_dio_private *devpriv = dev->private;
1181 comedi_pci_disable(dev);
1184 static struct comedi_driver adv_pci_dio_driver = {
1185 .driver_name = "adv_pci_dio",
1186 .module = THIS_MODULE,
1187 .auto_attach = pci_dio_auto_attach,
1188 .detach = pci_dio_detach,
1191 static int adv_pci_dio_pci_probe(struct pci_dev *dev,
1192 const struct pci_device_id *id)
1194 unsigned long cardtype;
1196 cardtype = pci_dio_override_cardtype(dev, id->driver_data);
1197 return comedi_pci_auto_config(dev, &adv_pci_dio_driver, cardtype);
1200 static DEFINE_PCI_DEVICE_TABLE(adv_pci_dio_pci_table) = {
1201 { PCI_VDEVICE(ADVANTECH, 0x1730), TYPE_PCI1730 },
1202 { PCI_VDEVICE(ADVANTECH, 0x1733), TYPE_PCI1733 },
1203 { PCI_VDEVICE(ADVANTECH, 0x1734), TYPE_PCI1734 },
1204 { PCI_VDEVICE(ADVANTECH, 0x1735), TYPE_PCI1735 },
1205 { PCI_VDEVICE(ADVANTECH, 0x1736), TYPE_PCI1736 },
1206 { PCI_VDEVICE(ADVANTECH, 0x1739), TYPE_PCI1739 },
1207 { PCI_VDEVICE(ADVANTECH, 0x1750), TYPE_PCI1750 },
1208 { PCI_VDEVICE(ADVANTECH, 0x1751), TYPE_PCI1751 },
1209 { PCI_VDEVICE(ADVANTECH, 0x1752), TYPE_PCI1752 },
1210 { PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 },
1211 { PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 },
1212 { PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 },
1213 { PCI_VDEVICE(ADVANTECH, 0x1760), TYPE_PCI1760 },
1214 { PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 },
1217 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
1219 static struct pci_driver adv_pci_dio_pci_driver = {
1220 .name = "adv_pci_dio",
1221 .id_table = adv_pci_dio_pci_table,
1222 .probe = adv_pci_dio_pci_probe,
1223 .remove = comedi_pci_auto_unconfig,
1225 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
1227 MODULE_AUTHOR("Comedi http://www.comedi.org");
1228 MODULE_DESCRIPTION("Comedi low-level driver");
1229 MODULE_LICENSE("GPL");