3 * Driver for Access I/O Products PC-104 AIO12-8 Analog I/O Board
4 * Copyright (C) 2006 C&C Technologies, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
19 * Description: Access I/O Products PC-104 AIO12-8 Analog I/O Board
20 * Author: Pablo Mejia <pablo.mejia@cctechnol.com>
21 * Devices: [Access I/O] PC-104 AIO12-8 (aio_aio12_8),
22 * [Access I/O] PC-104 AI12-8 (aio_ai12_8),
23 * [Access I/O] PC-104 AO12-8 (aio_ao12_8)
24 * Status: experimental
26 * Configuration Options:
27 * [0] - I/O port base address
30 * Only synchronous operations are supported.
33 #include <linux/module.h>
34 #include "../comedidev.h"
40 #define AIO12_8_STATUS_REG 0x00
41 #define AIO12_8_STATUS_ADC_EOC BIT(7)
42 #define AIO12_8_STATUS_PORT_C_COS BIT(6)
43 #define AIO12_8_STATUS_IRQ_ENA BIT(2)
44 #define AIO12_8_INTERRUPT_REG 0x01
45 #define AIO12_8_INTERRUPT_ADC BIT(7)
46 #define AIO12_8_INTERRUPT_COS BIT(6)
47 #define AIO12_8_INTERRUPT_COUNTER1 BIT(5)
48 #define AIO12_8_INTERRUPT_PORT_C3 BIT(4)
49 #define AIO12_8_INTERRUPT_PORT_C0 BIT(3)
50 #define AIO12_8_INTERRUPT_ENA BIT(2)
51 #define AIO12_8_ADC_REG 0x02
52 #define AIO12_8_ADC_MODE(x) (((x) & 0x3) << 6)
53 #define AIO12_8_ADC_MODE_NORMAL AIO12_8_ADC_MODE(0)
54 #define AIO12_8_ADC_MODE_INT_CLK AIO12_8_ADC_MODE(1)
55 #define AIO12_8_ADC_MODE_STANDBY AIO12_8_ADC_MODE(2)
56 #define AIO12_8_ADC_MODE_POWERDOWN AIO12_8_ADC_MODE(3)
57 #define AIO12_8_ADC_ACQ(x) (((x) & 0x1) << 5)
58 #define AIO12_8_ADC_ACQ_3USEC AIO12_8_ADC_ACQ(0)
59 #define AIO12_8_ADC_ACQ_PROGRAM AIO12_8_ADC_ACQ(1)
60 #define AIO12_8_ADC_RANGE(x) ((x) << 3)
61 #define AIO12_8_ADC_CHAN(x) ((x) << 0)
62 #define AIO12_8_DAC_REG(x) (0x04 + (x) * 2)
63 #define AIO12_8_8254_BASE_REG 0x0c
64 #define AIO12_8_8255_BASE_REG 0x10
65 #define AIO12_8_DIO_CONTROL_REG 0x14
66 #define AIO12_8_DIO_CONTROL_TST BIT(0)
67 #define AIO12_8_ADC_TRIGGER_REG 0x15
68 #define AIO12_8_ADC_TRIGGER_RANGE(x) ((x) << 3)
69 #define AIO12_8_ADC_TRIGGER_CHAN(x) ((x) << 0)
70 #define AIO12_8_TRIGGER_REG 0x16
71 #define AIO12_8_TRIGGER_ADTRIG BIT(1)
72 #define AIO12_8_TRIGGER_DACTRIG BIT(0)
73 #define AIO12_8_COS_REG 0x17
74 #define AIO12_8_DAC_ENABLE_REG 0x18
75 #define AIO12_8_DAC_ENABLE_REF_ENA BIT(0)
77 struct aio12_8_boardtype {
83 static const struct aio12_8_boardtype board_types[] = {
85 .name = "aio_aio12_8",
97 static int aio_aio12_8_ai_eoc(struct comedi_device *dev,
98 struct comedi_subdevice *s,
99 struct comedi_insn *insn,
100 unsigned long context)
104 status = inb(dev->iobase + AIO12_8_STATUS_REG);
105 if (status & AIO12_8_STATUS_ADC_EOC)
110 static int aio_aio12_8_ai_read(struct comedi_device *dev,
111 struct comedi_subdevice *s,
112 struct comedi_insn *insn, unsigned int *data)
114 unsigned int chan = CR_CHAN(insn->chanspec);
115 unsigned int range = CR_RANGE(insn->chanspec);
116 unsigned char control;
121 * Setup the control byte for internal 2MHz clock, 3uS conversion,
122 * at the desired range of the requested channel.
124 control = AIO12_8_ADC_MODE_NORMAL | AIO12_8_ADC_ACQ_3USEC |
125 AIO12_8_ADC_RANGE(range) | AIO12_8_ADC_CHAN(chan);
127 /* Read status to clear EOC latch */
128 inb(dev->iobase + AIO12_8_STATUS_REG);
130 for (n = 0; n < insn->n; n++) {
131 /* Setup and start conversion */
132 outb(control, dev->iobase + AIO12_8_ADC_REG);
134 /* Wait for conversion to complete */
135 ret = comedi_timeout(dev, s, insn, aio_aio12_8_ai_eoc, 0);
139 data[n] = inw(dev->iobase + AIO12_8_ADC_REG) & s->maxdata;
145 static int aio_aio12_8_ao_insn_write(struct comedi_device *dev,
146 struct comedi_subdevice *s,
147 struct comedi_insn *insn,
150 unsigned int chan = CR_CHAN(insn->chanspec);
151 unsigned int val = s->readback[chan];
155 outb(AIO12_8_DAC_ENABLE_REF_ENA, dev->iobase + AIO12_8_DAC_ENABLE_REG);
157 for (i = 0; i < insn->n; i++) {
159 outw(val, dev->iobase + AIO12_8_DAC_REG(chan));
161 s->readback[chan] = val;
166 static const struct comedi_lrange range_aio_aio12_8 = {
175 static int aio_aio12_8_attach(struct comedi_device *dev,
176 struct comedi_devconfig *it)
178 const struct aio12_8_boardtype *board = dev->board_ptr;
179 struct comedi_subdevice *s;
182 ret = comedi_request_region(dev, it->options[0], 32);
186 ret = comedi_alloc_subdevices(dev, 4);
190 s = &dev->subdevices[0];
191 if (board->ai_nchan) {
192 /* Analog input subdevice */
193 s->type = COMEDI_SUBD_AI;
194 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF;
195 s->n_chan = board->ai_nchan;
197 s->range_table = &range_aio_aio12_8;
198 s->insn_read = aio_aio12_8_ai_read;
200 s->type = COMEDI_SUBD_UNUSED;
203 s = &dev->subdevices[1];
204 if (board->ao_nchan) {
205 /* Analog output subdevice */
206 s->type = COMEDI_SUBD_AO;
207 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_DIFF;
210 s->range_table = &range_aio_aio12_8;
211 s->insn_write = aio_aio12_8_ao_insn_write;
213 ret = comedi_alloc_subdev_readback(s);
217 s->type = COMEDI_SUBD_UNUSED;
220 s = &dev->subdevices[2];
221 /* 8255 Digital i/o subdevice */
222 ret = subdev_8255_init(dev, s, NULL, AIO12_8_8255_BASE_REG);
226 s = &dev->subdevices[3];
227 /* 8254 counter/timer subdevice */
228 s->type = COMEDI_SUBD_UNUSED;
233 static struct comedi_driver aio_aio12_8_driver = {
234 .driver_name = "aio_aio12_8",
235 .module = THIS_MODULE,
236 .attach = aio_aio12_8_attach,
237 .detach = comedi_legacy_detach,
238 .board_name = &board_types[0].name,
239 .num_names = ARRAY_SIZE(board_types),
240 .offset = sizeof(struct aio12_8_boardtype),
242 module_comedi_driver(aio_aio12_8_driver);
244 MODULE_AUTHOR("Comedi http://www.comedi.org");
245 MODULE_DESCRIPTION("Comedi low-level driver");
246 MODULE_LICENSE("GPL");