2 comedi/drivers/cb_pcidas64.c
3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 64xx, 60xx, and 4020 cards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2001, 2002 Frank Mori Hess
9 Thanks also go to the following people:
11 Steve Rosenbluth, for providing the source code for
12 his pci-das6402 driver, and source code for working QNX pci-6402
13 drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 used directly here, but it was useful as an additional source of
15 documentation on how to program the boards.
17 John Sims, for much testing and feedback on pcidas-4020 support.
19 COMEDI - Linux Control and Measurement Device Interface
20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
22 This program is free software; you can redistribute it and/or modify
23 it under the terms of the GNU General Public License as published by
24 the Free Software Foundation; either version 2 of the License, or
25 (at your option) any later version.
27 This program is distributed in the hope that it will be useful,
28 but WITHOUT ANY WARRANTY; without even the implied warranty of
29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 GNU General Public License for more details.
35 * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
36 * with the PLX 9080 PCI controller
37 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
39 * Updated: Fri, 02 Nov 2012 18:58:55 +0000
40 * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
41 * PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
42 * PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
43 * PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
44 * PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
45 * PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
46 * PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
47 * PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
48 * PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
50 * Configuration options:
53 * Manual attachment of PCI cards with the comedi_config utility is not
54 * supported by this driver; they are attached automatically.
56 * These boards may be autocalibrated with the comedi_calibrate utility.
58 * To select the bnc trigger input on the 4020 (instead of the dio input),
59 * specify a nonzero channel in the chanspec. If you wish to use an external
60 * master clock on the 4020, you may do so by setting the scan_begin_src
61 * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
62 * to configure the divisor to use for the external clock.
64 * Some devices are not identified because the PCI device IDs are not yet
65 * known. If you have such a board, please let the maintainers know.
71 make it return error if user attempts an ai command that uses the
72 external queue, and an ao command simultaneously user counter subdevice
73 there are a number of boards this driver will support when they are
74 fully released, but does not yet since the pci device id numbers
75 are not yet available.
77 support prescaled 100khz clock for slow pacing (not available on 6000
80 make ao fifo size adjustable like ai fifo
83 #include <linux/module.h>
84 #include <linux/pci.h>
85 #include <linux/delay.h>
86 #include <linux/interrupt.h>
88 #include "../comedidev.h"
93 #include "comedi_fc.h"
95 #define TIMER_BASE 25 /* 40MHz master clock */
96 /* 100kHz 'prescaled' clock for slow acquisition,
97 * maybe I'll support this someday */
98 #define PRESCALED_TIMER_BASE 10000
99 #define DMA_BUFFER_SIZE 0x1000
101 /* maximum value that can be loaded into board's 24-bit counters*/
102 static const int max_counter_value = 0xffffff;
104 /* PCI-DAS64xxx base addresses */
106 /* devpriv->main_iobase registers */
107 enum write_only_registers {
108 INTR_ENABLE_REG = 0x0, /* interrupt enable register */
109 HW_CONFIG_REG = 0x2, /* hardware config register */
111 DAQ_ATRIG_LOW_4020_REG = 0xc,
112 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
113 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */
114 CALIBRATION_REG = 0x14,
115 /* lower 16 bits of adc sample interval counter */
116 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
117 /* upper 8 bits of adc sample interval counter */
118 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
119 /* lower 16 bits of delay interval counter */
120 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
121 /* upper 8 bits of delay interval counter */
122 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
123 /* lower 16 bits of hardware conversion/scan counter */
124 ADC_COUNT_LOWER_REG = 0x1e,
125 /* upper 8 bits of hardware conversion/scan counter */
126 ADC_COUNT_UPPER_REG = 0x20,
127 ADC_START_REG = 0x22, /* software trigger to start acquisition */
128 ADC_CONVERT_REG = 0x24, /* initiates single conversion */
129 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
130 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
131 ADC_BUFFER_CLEAR_REG = 0x2a,
132 /* high channel for internal queue, use adc_chan_bits() inline above */
133 ADC_QUEUE_HIGH_REG = 0x2c,
134 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */
135 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */
136 /* lower 16 bits of dac sample interval counter */
137 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
138 /* upper 8 bits of dac sample interval counter */
139 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
140 DAC_SELECT_REG = 0x60,
141 DAC_START_REG = 0x64,
142 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */
145 static inline unsigned int dac_convert_reg(unsigned int channel)
147 return 0x70 + (2 * (channel & 0x1));
150 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
152 return 0x70 + (4 * (channel & 0x1));
155 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
157 return 0x72 + (4 * (channel & 0x1));
160 enum read_only_registers {
161 /* hardware status register,
162 * reading this apparently clears pending interrupts as well */
164 PIPE1_READ_REG = 0x4,
165 ADC_READ_PNTR_REG = 0x8,
166 LOWER_XFER_REG = 0x10,
167 ADC_WRITE_PNTR_REG = 0xc,
171 enum read_write_registers {
172 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */
173 /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
174 ADC_QUEUE_FIFO_REG = 0x100,
175 ADC_FIFO_REG = 0x200, /* adc data fifo */
176 /* dac data fifo, has weird interactions with external channel queue */
177 DAC_FIFO_REG = 0x300,
180 /* dev->mmio registers */
181 enum dio_counter_registers {
182 DIO_8255_OFFSET = 0x0,
185 DIO_DIRECTION_60XX_REG = 0x40,
186 DIO_DATA_60XX_REG = 0x48,
189 /* bit definitions for write-only registers */
191 enum intr_enable_contents {
192 ADC_INTR_SRC_MASK = 0x3, /* adc interrupt source mask */
193 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quarter full */
194 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */
195 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
196 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence mask */
197 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
198 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done intr */
199 DAC_INTR_SRC_MASK = 0x30,
200 DAC_INTR_QEMPTY_BITS = 0x0,
201 DAC_INTR_HIGH_CHAN_BITS = 0x10,
202 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */
203 EN_DAC_DONE_INTR_BIT = 0x80,
204 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
205 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */
206 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
207 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */
208 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */
211 enum hw_config_contents {
212 MASTER_CLOCK_4020_MASK = 0x3, /* master clock source mask for 4020 */
213 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */
214 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */
215 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */
216 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue */
217 /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
218 SLOW_DAC_BIT = 0x400,
219 /* bit with unknown function yet given as default value in pci-das64
221 HW_CONFIG_DUMMY_BITS = 0x2000,
222 /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
223 DMA_CH_SELECT_BIT = 0x8000,
224 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */
225 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */
226 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
228 #define DAC_FIFO_SIZE 0x2000
230 enum daq_atrig_low_4020_contents {
231 /* use trig/ext clk bnc input for analog gate signal */
232 EXT_AGATE_BNC_BIT = 0x8000,
233 /* use trig/ext clk bnc input for external stop trigger signal */
234 EXT_STOP_TRIG_BNC_BIT = 0x4000,
235 /* use trig/ext clk bnc input for external start trigger signal */
236 EXT_START_TRIG_BNC_BIT = 0x2000,
239 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
241 return threshold & 0xfff;
244 enum adc_control0_contents {
245 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */
246 ADC_SOFT_GATE_BITS = 0x1, /* software gate */
247 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */
248 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */
249 ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */
250 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */
251 ADC_START_TRIG_SOFT_BITS = 0x10,
252 ADC_START_TRIG_EXT_BITS = 0x20,
253 ADC_START_TRIG_ANALOG_BITS = 0x30,
254 ADC_START_TRIG_MASK = 0x30,
255 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */
256 /* external pacing uses falling edge */
257 ADC_EXT_CONV_FALLING_BIT = 0x800,
258 /* enable hardware scan counter */
259 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
260 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */
261 ADC_ENABLE_BIT = 0x8000, /* master adc enable */
264 enum adc_control1_contents {
265 /* should be set for boards with > 16 channels */
266 ADC_QUEUE_CONFIG_BIT = 0x1,
267 CONVERT_POLARITY_BIT = 0x10,
268 EOC_POLARITY_BIT = 0x20,
269 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */
270 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */
271 RETRIGGER_BIT = 0x800,
272 ADC_LO_CHANNEL_4020_MASK = 0x300,
273 ADC_HI_CHANNEL_4020_MASK = 0xc00,
274 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */
275 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */
276 CHANNEL_MODE_4020_MASK = 0x3000,
277 ADC_MODE_MASK = 0xf000,
280 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
282 return (channel & 0x3) << 8;
285 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
287 return (channel & 0x3) << 10;
290 static inline uint16_t adc_mode_bits(unsigned int mode)
292 return (mode & 0xf) << 12;
295 enum calibration_contents {
296 SELECT_8800_BIT = 0x1,
297 SELECT_8402_64XX_BIT = 0x2,
298 SELECT_1590_60XX_BIT = 0x2,
299 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */
300 SERIAL_DATA_IN_BIT = 0x80,
301 SERIAL_CLOCK_BIT = 0x100,
302 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */
303 CAL_GAIN_BIT = 0x800,
306 /* calibration sources for 6025 are:
317 static inline uint16_t adc_src_bits(unsigned int source)
319 return (source & 0xf) << 3;
322 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
324 return (channel & 0x3) << 8;
327 enum adc_queue_load_contents {
328 UNIP_BIT = 0x800, /* unipolar/bipolar bit */
329 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */
330 /* non-referenced single-ended (common-mode input) */
331 ADC_COMMON_BIT = 0x2000,
332 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */
333 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */
336 static inline uint16_t adc_chan_bits(unsigned int channel)
338 return channel & 0x3f;
341 enum dac_control0_contents {
342 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */
343 DAC_CYCLIC_STOP_BIT = 0x4000,
344 DAC_WAVEFORM_MODE_BIT = 0x100,
345 DAC_EXT_UPDATE_FALLING_BIT = 0x80,
346 DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
347 WAVEFORM_TRIG_MASK = 0x30,
348 WAVEFORM_TRIG_DISABLED_BITS = 0x0,
349 WAVEFORM_TRIG_SOFT_BITS = 0x10,
350 WAVEFORM_TRIG_EXT_BITS = 0x20,
351 WAVEFORM_TRIG_ADC1_BITS = 0x30,
352 WAVEFORM_TRIG_FALLING_BIT = 0x8,
353 WAVEFORM_GATE_LEVEL_BIT = 0x4,
354 WAVEFORM_GATE_ENABLE_BIT = 0x2,
355 WAVEFORM_GATE_SELECT_BIT = 0x1,
358 enum dac_control1_contents {
359 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
360 DAC1_EXT_REF_BIT = 0x200,
361 DAC0_EXT_REF_BIT = 0x100,
362 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */
363 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
364 DAC_SW_GATE_BIT = 0x20,
365 DAC1_UNIPOLAR_BIT = 0x8,
366 DAC0_UNIPOLAR_BIT = 0x2,
369 /* bit definitions for read-only registers */
370 enum hw_status_contents {
371 DAC_UNDERRUN_BIT = 0x1,
372 ADC_OVERRUN_BIT = 0x2,
373 DAC_ACTIVE_BIT = 0x4,
374 ADC_ACTIVE_BIT = 0x8,
375 DAC_INTR_PENDING_BIT = 0x10,
376 ADC_INTR_PENDING_BIT = 0x20,
379 EXT_INTR_PENDING_BIT = 0x100,
380 ADC_STOP_BIT = 0x200,
383 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
385 return (hw_status_bits >> 10) & 0x3;
388 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
390 return (prepost_bits >> 6) & 0x3;
393 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
395 return (prepost_bits >> 12) & 0x3;
398 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
400 return (prepost_bits >> 14) & 0x3;
403 /* I2C addresses for 4020 */
405 RANGE_CAL_I2C_ADDR = 0x20,
406 CALDAC0_I2C_ADDR = 0xc,
407 CALDAC1_I2C_ADDR = 0xd,
410 enum range_cal_i2c_contents {
411 /* bits that set what source the adc converter measures */
412 ADC_SRC_4020_MASK = 0x70,
413 /* make bnc trig/ext clock threshold 0V instead of 2.5V */
414 BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
417 static inline uint8_t adc_src_4020_bits(unsigned int source)
419 return (source << 4) & ADC_SRC_4020_MASK;
422 static inline uint8_t attenuate_bit(unsigned int channel)
424 /* attenuate channel (+-5V input range) */
425 return 1 << (channel & 0x3);
428 /* analog input ranges for 64xx boards */
429 static const struct comedi_lrange ai_ranges_64xx = {
442 /* analog input ranges for 60xx boards */
443 static const struct comedi_lrange ai_ranges_60xx = {
452 /* analog input ranges for 6030, etc boards */
453 static const struct comedi_lrange ai_ranges_6030 = {
472 /* analog input ranges for 6052, etc boards */
473 static const struct comedi_lrange ai_ranges_6052 = {
493 /* analog input ranges for 4020 board */
494 static const struct comedi_lrange ai_ranges_4020 = {
501 /* analog output ranges */
502 static const struct comedi_lrange ao_ranges_64xx = {
511 static const int ao_range_code_64xx[] = {
518 static const int ao_range_code_60xx[] = {
522 static const struct comedi_lrange ao_ranges_6030 = {
529 static const int ao_range_code_6030[] = {
534 static const struct comedi_lrange ao_ranges_4020 = {
541 static const int ao_range_code_4020[] = {
546 enum register_layout {
552 struct hw_fifo_info {
553 unsigned int num_segments;
554 unsigned int max_segment_length;
555 unsigned int sample_packing_ratio;
556 uint16_t fifo_size_reg_mask;
559 enum pcidas64_boardid {
562 BOARD_PCIDAS64_M1_16,
563 BOARD_PCIDAS64_M2_16,
564 BOARD_PCIDAS64_M3_16,
581 BOARD_PCIDAS6402_16_JR,
582 BOARD_PCIDAS64_M1_16_JR,
583 BOARD_PCIDAS64_M2_16_JR,
584 BOARD_PCIDAS64_M3_16_JR,
585 BOARD_PCIDAS64_M1_14,
586 BOARD_PCIDAS64_M2_14,
587 BOARD_PCIDAS64_M3_14,
590 struct pcidas64_board {
592 int ai_se_chans; /* number of ai inputs in single-ended mode */
593 int ai_bits; /* analog input resolution */
594 int ai_speed; /* fastest conversion period in ns */
595 const struct comedi_lrange *ai_range_table;
596 int ao_nchan; /* number of analog out channels */
597 int ao_bits; /* analog output resolution */
598 int ao_scan_speed; /* analog output scan speed */
599 const struct comedi_lrange *ao_range_table;
600 const int *ao_range_code;
601 const struct hw_fifo_info *const ai_fifo;
602 /* different board families have slightly different registers */
603 enum register_layout layout;
607 static const struct hw_fifo_info ai_fifo_4020 = {
609 .max_segment_length = 0x8000,
610 .sample_packing_ratio = 2,
611 .fifo_size_reg_mask = 0x7f,
614 static const struct hw_fifo_info ai_fifo_64xx = {
616 .max_segment_length = 0x800,
617 .sample_packing_ratio = 1,
618 .fifo_size_reg_mask = 0x3f,
621 static const struct hw_fifo_info ai_fifo_60xx = {
623 .max_segment_length = 0x800,
624 .sample_packing_ratio = 1,
625 .fifo_size_reg_mask = 0x7f,
628 /* maximum number of dma transfers we will chain together into a ring
629 * (and the maximum number of dma buffers we maintain) */
630 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
631 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
632 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
633 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
635 if (board->layout == LAYOUT_4020)
636 return MAX_AI_DMA_RING_COUNT;
638 return MIN_AI_DMA_RING_COUNT;
641 static const int bytes_in_sample = 2;
643 static const struct pcidas64_board pcidas64_boards[] = {
644 [BOARD_PCIDAS6402_16] = {
645 .name = "pci-das6402/16",
651 .ao_scan_speed = 10000,
652 .layout = LAYOUT_64XX,
653 .ai_range_table = &ai_ranges_64xx,
654 .ao_range_table = &ao_ranges_64xx,
655 .ao_range_code = ao_range_code_64xx,
656 .ai_fifo = &ai_fifo_64xx,
659 [BOARD_PCIDAS6402_12] = {
660 .name = "pci-das6402/12", /* XXX check */
666 .ao_scan_speed = 10000,
667 .layout = LAYOUT_64XX,
668 .ai_range_table = &ai_ranges_64xx,
669 .ao_range_table = &ao_ranges_64xx,
670 .ao_range_code = ao_range_code_64xx,
671 .ai_fifo = &ai_fifo_64xx,
674 [BOARD_PCIDAS64_M1_16] = {
675 .name = "pci-das64/m1/16",
681 .ao_scan_speed = 10000,
682 .layout = LAYOUT_64XX,
683 .ai_range_table = &ai_ranges_64xx,
684 .ao_range_table = &ao_ranges_64xx,
685 .ao_range_code = ao_range_code_64xx,
686 .ai_fifo = &ai_fifo_64xx,
689 [BOARD_PCIDAS64_M2_16] = {
690 .name = "pci-das64/m2/16",
696 .ao_scan_speed = 10000,
697 .layout = LAYOUT_64XX,
698 .ai_range_table = &ai_ranges_64xx,
699 .ao_range_table = &ao_ranges_64xx,
700 .ao_range_code = ao_range_code_64xx,
701 .ai_fifo = &ai_fifo_64xx,
704 [BOARD_PCIDAS64_M3_16] = {
705 .name = "pci-das64/m3/16",
711 .ao_scan_speed = 10000,
712 .layout = LAYOUT_64XX,
713 .ai_range_table = &ai_ranges_64xx,
714 .ao_range_table = &ao_ranges_64xx,
715 .ao_range_code = ao_range_code_64xx,
716 .ai_fifo = &ai_fifo_64xx,
719 [BOARD_PCIDAS6013] = {
720 .name = "pci-das6013",
726 .layout = LAYOUT_60XX,
727 .ai_range_table = &ai_ranges_60xx,
728 .ao_range_table = &range_bipolar10,
729 .ao_range_code = ao_range_code_60xx,
730 .ai_fifo = &ai_fifo_60xx,
733 [BOARD_PCIDAS6014] = {
734 .name = "pci-das6014",
740 .ao_scan_speed = 100000,
741 .layout = LAYOUT_60XX,
742 .ai_range_table = &ai_ranges_60xx,
743 .ao_range_table = &range_bipolar10,
744 .ao_range_code = ao_range_code_60xx,
745 .ai_fifo = &ai_fifo_60xx,
748 [BOARD_PCIDAS6023] = {
749 .name = "pci-das6023",
754 .ao_scan_speed = 100000,
755 .layout = LAYOUT_60XX,
756 .ai_range_table = &ai_ranges_60xx,
757 .ao_range_table = &range_bipolar10,
758 .ao_range_code = ao_range_code_60xx,
759 .ai_fifo = &ai_fifo_60xx,
762 [BOARD_PCIDAS6025] = {
763 .name = "pci-das6025",
769 .ao_scan_speed = 100000,
770 .layout = LAYOUT_60XX,
771 .ai_range_table = &ai_ranges_60xx,
772 .ao_range_table = &range_bipolar10,
773 .ao_range_code = ao_range_code_60xx,
774 .ai_fifo = &ai_fifo_60xx,
777 [BOARD_PCIDAS6030] = {
778 .name = "pci-das6030",
784 .ao_scan_speed = 10000,
785 .layout = LAYOUT_60XX,
786 .ai_range_table = &ai_ranges_6030,
787 .ao_range_table = &ao_ranges_6030,
788 .ao_range_code = ao_range_code_6030,
789 .ai_fifo = &ai_fifo_60xx,
792 [BOARD_PCIDAS6031] = {
793 .name = "pci-das6031",
799 .ao_scan_speed = 10000,
800 .layout = LAYOUT_60XX,
801 .ai_range_table = &ai_ranges_6030,
802 .ao_range_table = &ao_ranges_6030,
803 .ao_range_code = ao_range_code_6030,
804 .ai_fifo = &ai_fifo_60xx,
807 [BOARD_PCIDAS6032] = {
808 .name = "pci-das6032",
813 .layout = LAYOUT_60XX,
814 .ai_range_table = &ai_ranges_6030,
815 .ai_fifo = &ai_fifo_60xx,
818 [BOARD_PCIDAS6033] = {
819 .name = "pci-das6033",
824 .layout = LAYOUT_60XX,
825 .ai_range_table = &ai_ranges_6030,
826 .ai_fifo = &ai_fifo_60xx,
829 [BOARD_PCIDAS6034] = {
830 .name = "pci-das6034",
836 .layout = LAYOUT_60XX,
837 .ai_range_table = &ai_ranges_60xx,
838 .ai_fifo = &ai_fifo_60xx,
841 [BOARD_PCIDAS6035] = {
842 .name = "pci-das6035",
848 .ao_scan_speed = 100000,
849 .layout = LAYOUT_60XX,
850 .ai_range_table = &ai_ranges_60xx,
851 .ao_range_table = &range_bipolar10,
852 .ao_range_code = ao_range_code_60xx,
853 .ai_fifo = &ai_fifo_60xx,
856 [BOARD_PCIDAS6036] = {
857 .name = "pci-das6036",
863 .ao_scan_speed = 100000,
864 .layout = LAYOUT_60XX,
865 .ai_range_table = &ai_ranges_60xx,
866 .ao_range_table = &range_bipolar10,
867 .ao_range_code = ao_range_code_60xx,
868 .ai_fifo = &ai_fifo_60xx,
871 [BOARD_PCIDAS6040] = {
872 .name = "pci-das6040",
878 .ao_scan_speed = 1000,
879 .layout = LAYOUT_60XX,
880 .ai_range_table = &ai_ranges_6052,
881 .ao_range_table = &ao_ranges_6030,
882 .ao_range_code = ao_range_code_6030,
883 .ai_fifo = &ai_fifo_60xx,
886 [BOARD_PCIDAS6052] = {
887 .name = "pci-das6052",
893 .ao_scan_speed = 3333,
894 .layout = LAYOUT_60XX,
895 .ai_range_table = &ai_ranges_6052,
896 .ao_range_table = &ao_ranges_6030,
897 .ao_range_code = ao_range_code_6030,
898 .ai_fifo = &ai_fifo_60xx,
901 [BOARD_PCIDAS6070] = {
902 .name = "pci-das6070",
908 .ao_scan_speed = 1000,
909 .layout = LAYOUT_60XX,
910 .ai_range_table = &ai_ranges_6052,
911 .ao_range_table = &ao_ranges_6030,
912 .ao_range_code = ao_range_code_6030,
913 .ai_fifo = &ai_fifo_60xx,
916 [BOARD_PCIDAS6071] = {
917 .name = "pci-das6071",
923 .ao_scan_speed = 1000,
924 .layout = LAYOUT_60XX,
925 .ai_range_table = &ai_ranges_6052,
926 .ao_range_table = &ao_ranges_6030,
927 .ao_range_code = ao_range_code_6030,
928 .ai_fifo = &ai_fifo_60xx,
931 [BOARD_PCIDAS4020_12] = {
932 .name = "pci-das4020/12",
938 .ao_scan_speed = 0, /* no hardware pacing on ao */
939 .layout = LAYOUT_4020,
940 .ai_range_table = &ai_ranges_4020,
941 .ao_range_table = &ao_ranges_4020,
942 .ao_range_code = ao_range_code_4020,
943 .ai_fifo = &ai_fifo_4020,
948 * The device id for these boards is unknown
951 [BOARD_PCIDAS6402_16_JR] = {
952 .name = "pci-das6402/16/jr",
957 .ao_scan_speed = 10000,
958 .layout = LAYOUT_64XX,
959 .ai_range_table = &ai_ranges_64xx,
960 .ai_fifo = ai_fifo_64xx,
963 [BOARD_PCIDAS64_M1_16_JR] = {
964 .name = "pci-das64/m1/16/jr",
969 .ao_scan_speed = 10000,
970 .layout = LAYOUT_64XX,
971 .ai_range_table = &ai_ranges_64xx,
972 .ai_fifo = ai_fifo_64xx,
975 [BOARD_PCIDAS64_M2_16_JR] = {
976 .name = "pci-das64/m2/16/jr",
981 .ao_scan_speed = 10000,
982 .layout = LAYOUT_64XX,
983 .ai_range_table = &ai_ranges_64xx,
984 .ai_fifo = ai_fifo_64xx,
987 [BOARD_PCIDAS64_M3_16_JR] = {
988 .name = "pci-das64/m3/16/jr",
993 .ao_scan_speed = 10000,
994 .layout = LAYOUT_64XX,
995 .ai_range_table = &ai_ranges_64xx,
996 .ai_fifo = ai_fifo_64xx,
999 [BOARD_PCIDAS64_M1_14] = {
1000 .name = "pci-das64/m1/14",
1005 .ao_scan_speed = 10000,
1006 .layout = LAYOUT_64XX,
1007 .ai_range_table = &ai_ranges_64xx,
1008 .ai_fifo = ai_fifo_64xx,
1011 [BOARD_PCIDAS64_M2_14] = {
1012 .name = "pci-das64/m2/14",
1017 .ao_scan_speed = 10000,
1018 .layout = LAYOUT_64XX,
1019 .ai_range_table = &ai_ranges_64xx,
1020 .ai_fifo = ai_fifo_64xx,
1023 [BOARD_PCIDAS64_M3_14] = {
1024 .name = "pci-das64/m3/14",
1029 .ao_scan_speed = 10000,
1030 .layout = LAYOUT_64XX,
1031 .ai_range_table = &ai_ranges_64xx,
1032 .ai_fifo = ai_fifo_64xx,
1038 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1039 int use_differential)
1041 const struct pcidas64_board *thisboard = dev->board_ptr;
1043 if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1044 (thisboard->layout == LAYOUT_60XX && use_differential))
1045 return ADC_SE_DIFF_BIT;
1050 struct ext_clock_info {
1051 /* master clock divisor to use for scans with external master clock */
1052 unsigned int divisor;
1053 /* chanspec for master clock input when used as scan begin src */
1054 unsigned int chanspec;
1057 /* this structure is for data unique to this hardware driver. */
1058 struct pcidas64_private {
1059 /* base addresses (physical) */
1060 resource_size_t main_phys_iobase;
1061 resource_size_t dio_counter_phys_iobase;
1062 /* base addresses (ioremapped) */
1063 void __iomem *plx9080_iobase;
1064 void __iomem *main_iobase;
1065 /* local address (used by dma controller) */
1066 uint32_t local0_iobase;
1067 uint32_t local1_iobase;
1068 /* number of analog input samples remaining */
1069 unsigned int ai_count;
1070 /* dma buffers for analog input */
1071 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1072 /* physical addresses of ai dma buffers */
1073 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1074 /* array of ai dma descriptors read by plx9080,
1075 * allocated to get proper alignment */
1076 struct plx_dma_desc *ai_dma_desc;
1077 /* physical address of ai dma descriptor array */
1078 dma_addr_t ai_dma_desc_bus_addr;
1079 /* index of the ai dma descriptor/buffer
1080 * that is currently being used */
1081 unsigned int ai_dma_index;
1082 /* dma buffers for analog output */
1083 uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1084 /* physical addresses of ao dma buffers */
1085 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1086 struct plx_dma_desc *ao_dma_desc;
1087 dma_addr_t ao_dma_desc_bus_addr;
1088 /* keeps track of buffer where the next ao sample should go */
1089 unsigned int ao_dma_index;
1090 /* number of analog output samples remaining */
1091 unsigned long ao_count;
1092 unsigned int hw_revision; /* stc chip hardware revision number */
1093 /* last bits sent to INTR_ENABLE_REG register */
1094 unsigned int intr_enable_bits;
1095 /* last bits sent to ADC_CONTROL1_REG register */
1096 uint16_t adc_control1_bits;
1097 /* last bits sent to FIFO_SIZE_REG register */
1098 uint16_t fifo_size_bits;
1099 /* last bits sent to HW_CONFIG_REG register */
1100 uint16_t hw_config_bits;
1101 uint16_t dac_control1_bits;
1102 /* last bits written to plx9080 control register */
1103 uint32_t plx_control_bits;
1104 /* last bits written to plx interrupt control and status register */
1105 uint32_t plx_intcsr_bits;
1106 /* index of calibration source readable through ai ch0 */
1107 int calibration_source;
1108 /* bits written to i2c calibration/range register */
1109 uint8_t i2c_cal_range_bits;
1110 /* configure digital triggers to trigger on falling edge */
1111 unsigned int ext_trig_falling;
1112 /* states of various devices stored to enable read-back */
1113 unsigned int ad8402_state[2];
1114 unsigned int caldac_state[8];
1115 short ai_cmd_running;
1116 unsigned int ai_fifo_segment_length;
1117 struct ext_clock_info ext_clock;
1118 unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1121 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1122 unsigned int range_index)
1124 const struct pcidas64_board *thisboard = dev->board_ptr;
1125 const struct comedi_krange *range =
1126 &thisboard->ai_range_table->range[range_index];
1127 unsigned int bits = 0;
1129 switch (range->max) {
1158 dev_err(dev->class_dev, "bug! in %s\n", __func__);
1161 if (range->min == 0)
1166 static unsigned int hw_revision(const struct comedi_device *dev,
1167 uint16_t hw_status_bits)
1169 const struct pcidas64_board *thisboard = dev->board_ptr;
1171 if (thisboard->layout == LAYOUT_4020)
1172 return (hw_status_bits >> 13) & 0x7;
1174 return (hw_status_bits >> 12) & 0xf;
1177 static void set_dac_range_bits(struct comedi_device *dev,
1178 uint16_t *bits, unsigned int channel,
1181 const struct pcidas64_board *thisboard = dev->board_ptr;
1182 unsigned int code = thisboard->ao_range_code[range];
1185 dev_err(dev->class_dev, "bug! bad channel?\n");
1187 dev_err(dev->class_dev, "bug! bad range code?\n");
1189 *bits &= ~(0x3 << (2 * channel));
1190 *bits |= code << (2 * channel);
1193 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1195 return board->ao_nchan && board->layout != LAYOUT_4020;
1198 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1200 struct pcidas64_private *devpriv = dev->private;
1201 unsigned long flags;
1203 /* spinlock for plx dma control/status reg */
1204 spin_lock_irqsave(&dev->spinlock, flags);
1206 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1208 spin_unlock_irqrestore(&dev->spinlock, flags);
1211 static void disable_plx_interrupts(struct comedi_device *dev)
1213 struct pcidas64_private *devpriv = dev->private;
1215 devpriv->plx_intcsr_bits = 0;
1216 writel(devpriv->plx_intcsr_bits,
1217 devpriv->plx9080_iobase + PLX_INTRCS_REG);
1220 static void disable_ai_interrupts(struct comedi_device *dev)
1222 struct pcidas64_private *devpriv = dev->private;
1223 unsigned long flags;
1225 spin_lock_irqsave(&dev->spinlock, flags);
1226 devpriv->intr_enable_bits &=
1227 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1228 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1229 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1230 writew(devpriv->intr_enable_bits,
1231 devpriv->main_iobase + INTR_ENABLE_REG);
1232 spin_unlock_irqrestore(&dev->spinlock, flags);
1235 static void enable_ai_interrupts(struct comedi_device *dev,
1236 const struct comedi_cmd *cmd)
1238 const struct pcidas64_board *thisboard = dev->board_ptr;
1239 struct pcidas64_private *devpriv = dev->private;
1241 unsigned long flags;
1243 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1244 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1245 /* Use pio transfer and interrupt on end of conversion
1246 * if CMDF_WAKE_EOS flag is set. */
1247 if (cmd->flags & CMDF_WAKE_EOS) {
1248 /* 4020 doesn't support pio transfers except for fifo dregs */
1249 if (thisboard->layout != LAYOUT_4020)
1250 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1252 spin_lock_irqsave(&dev->spinlock, flags);
1253 devpriv->intr_enable_bits |= bits;
1254 writew(devpriv->intr_enable_bits,
1255 devpriv->main_iobase + INTR_ENABLE_REG);
1256 spin_unlock_irqrestore(&dev->spinlock, flags);
1259 /* initialize plx9080 chip */
1260 static void init_plx9080(struct comedi_device *dev)
1262 const struct pcidas64_board *thisboard = dev->board_ptr;
1263 struct pcidas64_private *devpriv = dev->private;
1265 void __iomem *plx_iobase = devpriv->plx9080_iobase;
1267 devpriv->plx_control_bits =
1268 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1271 bits = BIGEND_DMA0 | BIGEND_DMA1;
1275 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1277 disable_plx_interrupts(dev);
1282 /* configure dma0 mode */
1284 /* enable ready input, not sure if this is necessary */
1285 bits |= PLX_DMA_EN_READYIN_BIT;
1286 /* enable bterm, not sure if this is necessary */
1287 bits |= PLX_EN_BTERM_BIT;
1288 /* enable dma chaining */
1289 bits |= PLX_EN_CHAIN_BIT;
1290 /* enable interrupt on dma done
1291 * (probably don't need this, since chain never finishes) */
1292 bits |= PLX_EN_DMA_DONE_INTR_BIT;
1293 /* don't increment local address during transfers
1294 * (we are transferring from a fixed fifo register) */
1295 bits |= PLX_LOCAL_ADDR_CONST_BIT;
1296 /* route dma interrupt to pci bus */
1297 bits |= PLX_DMA_INTR_PCI_BIT;
1298 /* enable demand mode */
1299 bits |= PLX_DEMAND_MODE_BIT;
1300 /* enable local burst mode */
1301 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1302 /* 4020 uses 32 bit dma */
1303 if (thisboard->layout == LAYOUT_4020)
1304 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1305 else /* localspace0 bus is 16 bits wide */
1306 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1307 writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1308 if (ao_cmd_is_supported(thisboard))
1309 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1311 /* enable interrupts on plx 9080 */
1312 devpriv->plx_intcsr_bits |=
1313 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1314 ICS_DMA0_E | ICS_DMA1_E;
1315 writel(devpriv->plx_intcsr_bits,
1316 devpriv->plx9080_iobase + PLX_INTRCS_REG);
1319 static void disable_ai_pacing(struct comedi_device *dev)
1321 struct pcidas64_private *devpriv = dev->private;
1322 unsigned long flags;
1324 disable_ai_interrupts(dev);
1326 spin_lock_irqsave(&dev->spinlock, flags);
1327 devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1328 writew(devpriv->adc_control1_bits,
1329 devpriv->main_iobase + ADC_CONTROL1_REG);
1330 spin_unlock_irqrestore(&dev->spinlock, flags);
1332 /* disable pacing, triggering, etc */
1333 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1334 devpriv->main_iobase + ADC_CONTROL0_REG);
1337 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1338 unsigned int num_entries)
1340 const struct pcidas64_board *thisboard = dev->board_ptr;
1341 struct pcidas64_private *devpriv = dev->private;
1342 static const int increment_size = 0x100;
1343 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1344 unsigned int num_increments;
1347 if (num_entries < increment_size)
1348 num_entries = increment_size;
1349 if (num_entries > fifo->max_segment_length)
1350 num_entries = fifo->max_segment_length;
1352 /* 1 == 256 entries, 2 == 512 entries, etc */
1353 num_increments = (num_entries + increment_size / 2) / increment_size;
1355 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1356 devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1357 devpriv->fifo_size_bits |= bits;
1358 writew(devpriv->fifo_size_bits,
1359 devpriv->main_iobase + FIFO_SIZE_REG);
1361 devpriv->ai_fifo_segment_length = num_increments * increment_size;
1363 return devpriv->ai_fifo_segment_length;
1366 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1367 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1369 const struct pcidas64_board *thisboard = dev->board_ptr;
1370 unsigned int num_fifo_entries;
1372 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1374 num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1376 retval = set_ai_fifo_segment_length(dev,
1378 fifo->num_segments);
1382 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1387 /* query length of fifo */
1388 static unsigned int ai_fifo_size(struct comedi_device *dev)
1390 const struct pcidas64_board *thisboard = dev->board_ptr;
1391 struct pcidas64_private *devpriv = dev->private;
1393 return devpriv->ai_fifo_segment_length *
1394 thisboard->ai_fifo->num_segments *
1395 thisboard->ai_fifo->sample_packing_ratio;
1398 static void init_stc_registers(struct comedi_device *dev)
1400 const struct pcidas64_board *thisboard = dev->board_ptr;
1401 struct pcidas64_private *devpriv = dev->private;
1403 unsigned long flags;
1405 spin_lock_irqsave(&dev->spinlock, flags);
1407 /* bit should be set for 6025,
1408 * although docs say boards with <= 16 chans should be cleared XXX */
1410 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1411 writew(devpriv->adc_control1_bits,
1412 devpriv->main_iobase + ADC_CONTROL1_REG);
1414 /* 6402/16 manual says this register must be initialized to 0xff? */
1415 writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1417 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1418 if (thisboard->layout == LAYOUT_4020)
1419 bits |= INTERNAL_CLOCK_4020_BITS;
1420 devpriv->hw_config_bits |= bits;
1421 writew(devpriv->hw_config_bits,
1422 devpriv->main_iobase + HW_CONFIG_REG);
1424 writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1425 writew(0, devpriv->main_iobase + CALIBRATION_REG);
1427 spin_unlock_irqrestore(&dev->spinlock, flags);
1429 /* set fifos to maximum size */
1430 devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1431 set_ai_fifo_segment_length(dev,
1432 thisboard->ai_fifo->max_segment_length);
1434 devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1435 devpriv->intr_enable_bits =
1436 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1437 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1438 writew(devpriv->intr_enable_bits,
1439 devpriv->main_iobase + INTR_ENABLE_REG);
1441 disable_ai_pacing(dev);
1444 static int alloc_and_init_dma_members(struct comedi_device *dev)
1446 const struct pcidas64_board *thisboard = dev->board_ptr;
1447 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1448 struct pcidas64_private *devpriv = dev->private;
1451 /* allocate pci dma buffers */
1452 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1453 devpriv->ai_buffer[i] =
1454 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1455 &devpriv->ai_buffer_bus_addr[i]);
1456 if (devpriv->ai_buffer[i] == NULL)
1460 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1461 if (ao_cmd_is_supported(thisboard)) {
1462 devpriv->ao_buffer[i] =
1463 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1465 ao_buffer_bus_addr[i]);
1466 if (devpriv->ao_buffer[i] == NULL)
1471 /* allocate dma descriptors */
1472 devpriv->ai_dma_desc =
1473 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1474 ai_dma_ring_count(thisboard),
1475 &devpriv->ai_dma_desc_bus_addr);
1476 if (devpriv->ai_dma_desc == NULL)
1479 if (ao_cmd_is_supported(thisboard)) {
1480 devpriv->ao_dma_desc =
1481 pci_alloc_consistent(pcidev,
1482 sizeof(struct plx_dma_desc) *
1484 &devpriv->ao_dma_desc_bus_addr);
1485 if (devpriv->ao_dma_desc == NULL)
1488 /* initialize dma descriptors */
1489 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1490 devpriv->ai_dma_desc[i].pci_start_addr =
1491 cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1492 if (thisboard->layout == LAYOUT_4020)
1493 devpriv->ai_dma_desc[i].local_start_addr =
1494 cpu_to_le32(devpriv->local1_iobase +
1497 devpriv->ai_dma_desc[i].local_start_addr =
1498 cpu_to_le32(devpriv->local0_iobase +
1500 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1501 devpriv->ai_dma_desc[i].next =
1502 cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1503 ((i + 1) % ai_dma_ring_count(thisboard)) *
1504 sizeof(devpriv->ai_dma_desc[0])) |
1505 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1506 PLX_XFER_LOCAL_TO_PCI);
1508 if (ao_cmd_is_supported(thisboard)) {
1509 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1510 devpriv->ao_dma_desc[i].pci_start_addr =
1511 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1512 devpriv->ao_dma_desc[i].local_start_addr =
1513 cpu_to_le32(devpriv->local0_iobase +
1515 devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1516 devpriv->ao_dma_desc[i].next =
1517 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1518 ((i + 1) % (AO_DMA_RING_COUNT)) *
1519 sizeof(devpriv->ao_dma_desc[0])) |
1520 PLX_DESC_IN_PCI_BIT |
1521 PLX_INTR_TERM_COUNT);
1527 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1529 const struct pcidas64_board *thisboard = dev->board_ptr;
1530 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1531 struct pcidas64_private *devpriv = dev->private;
1537 /* free pci dma buffers */
1538 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1539 if (devpriv->ai_buffer[i])
1540 pci_free_consistent(pcidev,
1542 devpriv->ai_buffer[i],
1543 devpriv->ai_buffer_bus_addr[i]);
1545 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1546 if (devpriv->ao_buffer[i])
1547 pci_free_consistent(pcidev,
1549 devpriv->ao_buffer[i],
1550 devpriv->ao_buffer_bus_addr[i]);
1552 /* free dma descriptors */
1553 if (devpriv->ai_dma_desc)
1554 pci_free_consistent(pcidev,
1555 sizeof(struct plx_dma_desc) *
1556 ai_dma_ring_count(thisboard),
1557 devpriv->ai_dma_desc,
1558 devpriv->ai_dma_desc_bus_addr);
1559 if (devpriv->ao_dma_desc)
1560 pci_free_consistent(pcidev,
1561 sizeof(struct plx_dma_desc) *
1563 devpriv->ao_dma_desc,
1564 devpriv->ao_dma_desc_bus_addr);
1567 static inline void warn_external_queue(struct comedi_device *dev)
1569 dev_err(dev->class_dev,
1570 "AO command and AI external channel queue cannot be used simultaneously\n");
1571 dev_err(dev->class_dev,
1572 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1575 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1576 static const int i2c_high_udelay = 1000;
1577 static const int i2c_low_udelay = 10;
1579 /* set i2c data line high or low */
1580 static void i2c_set_sda(struct comedi_device *dev, int state)
1582 struct pcidas64_private *devpriv = dev->private;
1583 static const int data_bit = CTL_EE_W;
1584 void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1588 /* set data line high */
1589 devpriv->plx_control_bits &= ~data_bit;
1590 writel(devpriv->plx_control_bits, plx_control_addr);
1591 udelay(i2c_high_udelay);
1592 } else { /* set data line low */
1594 devpriv->plx_control_bits |= data_bit;
1595 writel(devpriv->plx_control_bits, plx_control_addr);
1596 udelay(i2c_low_udelay);
1600 /* set i2c clock line high or low */
1601 static void i2c_set_scl(struct comedi_device *dev, int state)
1603 struct pcidas64_private *devpriv = dev->private;
1604 static const int clock_bit = CTL_USERO;
1605 void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1609 /* set clock line high */
1610 devpriv->plx_control_bits &= ~clock_bit;
1611 writel(devpriv->plx_control_bits, plx_control_addr);
1612 udelay(i2c_high_udelay);
1613 } else { /* set clock line low */
1615 devpriv->plx_control_bits |= clock_bit;
1616 writel(devpriv->plx_control_bits, plx_control_addr);
1617 udelay(i2c_low_udelay);
1621 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1624 unsigned int num_bits = 8;
1626 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1627 i2c_set_scl(dev, 0);
1629 i2c_set_sda(dev, 1);
1631 i2c_set_sda(dev, 0);
1632 i2c_set_scl(dev, 1);
1636 /* we can't really read the lines, so fake it */
1637 static int i2c_read_ack(struct comedi_device *dev)
1639 i2c_set_scl(dev, 0);
1640 i2c_set_sda(dev, 1);
1641 i2c_set_scl(dev, 1);
1643 return 0; /* return fake acknowledge bit */
1646 /* send start bit */
1647 static void i2c_start(struct comedi_device *dev)
1649 i2c_set_scl(dev, 1);
1650 i2c_set_sda(dev, 1);
1651 i2c_set_sda(dev, 0);
1655 static void i2c_stop(struct comedi_device *dev)
1657 i2c_set_scl(dev, 0);
1658 i2c_set_sda(dev, 0);
1659 i2c_set_scl(dev, 1);
1660 i2c_set_sda(dev, 1);
1663 static void i2c_write(struct comedi_device *dev, unsigned int address,
1664 const uint8_t *data, unsigned int length)
1666 struct pcidas64_private *devpriv = dev->private;
1669 static const int read_bit = 0x1;
1671 /* XXX need mutex to prevent simultaneous attempts to access
1672 * eeprom and i2c bus */
1674 /* make sure we dont send anything to eeprom */
1675 devpriv->plx_control_bits &= ~CTL_EE_CS;
1680 /* send address and write bit */
1681 bitstream = (address << 1) & ~read_bit;
1682 i2c_write_byte(dev, bitstream);
1684 /* get acknowledge */
1685 if (i2c_read_ack(dev) != 0) {
1686 dev_err(dev->class_dev, "%s failed: no acknowledge\n",
1691 /* write data bytes */
1692 for (i = 0; i < length; i++) {
1693 i2c_write_byte(dev, data[i]);
1694 if (i2c_read_ack(dev) != 0) {
1695 dev_err(dev->class_dev, "%s failed: no acknowledge\n",
1704 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1705 struct comedi_subdevice *s,
1706 struct comedi_insn *insn,
1707 unsigned long context)
1709 const struct pcidas64_board *thisboard = dev->board_ptr;
1710 struct pcidas64_private *devpriv = dev->private;
1711 unsigned int status;
1713 status = readw(devpriv->main_iobase + HW_STATUS_REG);
1714 if (thisboard->layout == LAYOUT_4020) {
1715 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1719 if (pipe_full_bits(status))
1725 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1726 struct comedi_insn *insn, unsigned int *data)
1728 const struct pcidas64_board *thisboard = dev->board_ptr;
1729 struct pcidas64_private *devpriv = dev->private;
1730 unsigned int bits = 0, n;
1731 unsigned int channel, range, aref;
1732 unsigned long flags;
1735 channel = CR_CHAN(insn->chanspec);
1736 range = CR_RANGE(insn->chanspec);
1737 aref = CR_AREF(insn->chanspec);
1739 /* disable card's analog input interrupt sources and pacing */
1740 /* 4020 generates dac done interrupts even though they are disabled */
1741 disable_ai_pacing(dev);
1743 spin_lock_irqsave(&dev->spinlock, flags);
1744 if (insn->chanspec & CR_ALT_FILTER)
1745 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1747 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1748 writew(devpriv->adc_control1_bits,
1749 devpriv->main_iobase + ADC_CONTROL1_REG);
1750 spin_unlock_irqrestore(&dev->spinlock, flags);
1752 if (thisboard->layout != LAYOUT_4020) {
1753 /* use internal queue */
1754 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1755 writew(devpriv->hw_config_bits,
1756 devpriv->main_iobase + HW_CONFIG_REG);
1758 /* ALT_SOURCE is internal calibration reference */
1759 if (insn->chanspec & CR_ALT_SOURCE) {
1760 unsigned int cal_en_bit;
1762 if (thisboard->layout == LAYOUT_60XX)
1763 cal_en_bit = CAL_EN_60XX_BIT;
1765 cal_en_bit = CAL_EN_64XX_BIT;
1766 /* select internal reference source to connect
1769 adc_src_bits(devpriv->calibration_source),
1770 devpriv->main_iobase + CALIBRATION_REG);
1772 /* make sure internal calibration source
1774 writew(0, devpriv->main_iobase + CALIBRATION_REG);
1776 /* load internal queue */
1779 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1780 /* set single-ended / differential */
1781 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1782 if (aref == AREF_COMMON)
1783 bits |= ADC_COMMON_BIT;
1784 bits |= adc_chan_bits(channel);
1785 /* set stop channel */
1786 writew(adc_chan_bits(channel),
1787 devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1788 /* set start channel, and rest of settings */
1789 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1791 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1793 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1794 if (insn->chanspec & CR_ALT_SOURCE) {
1795 devpriv->i2c_cal_range_bits |=
1796 adc_src_4020_bits(devpriv->calibration_source);
1797 } else { /* select BNC inputs */
1798 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1802 devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1804 devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1805 /* update calibration/range i2c register only if necessary,
1806 * as it is very slow */
1807 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1808 uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1810 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1814 /* 4020 manual asks that sample interval register to be set
1815 * before writing to convert register.
1816 * Using somewhat arbitrary setting of 4 master clock ticks
1818 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1819 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1822 for (n = 0; n < insn->n; n++) {
1824 /* clear adc buffer (inside loop for 4020 sake) */
1825 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1827 /* trigger conversion, bits sent only matter for 4020 */
1828 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1829 devpriv->main_iobase + ADC_CONVERT_REG);
1832 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1836 if (thisboard->layout == LAYOUT_4020)
1837 data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1839 data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1845 static int ai_config_calibration_source(struct comedi_device *dev,
1848 const struct pcidas64_board *thisboard = dev->board_ptr;
1849 struct pcidas64_private *devpriv = dev->private;
1850 unsigned int source = data[1];
1851 int num_calibration_sources;
1853 if (thisboard->layout == LAYOUT_60XX)
1854 num_calibration_sources = 16;
1856 num_calibration_sources = 8;
1857 if (source >= num_calibration_sources) {
1858 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1863 devpriv->calibration_source = source;
1868 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1870 const struct pcidas64_board *thisboard = dev->board_ptr;
1872 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1873 unsigned int block_size, requested_block_size;
1876 requested_block_size = data[1];
1878 if (requested_block_size) {
1879 fifo_size = requested_block_size * fifo->num_segments /
1882 retval = set_ai_fifo_size(dev, fifo_size);
1888 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1890 data[1] = block_size;
1895 static int ai_config_master_clock_4020(struct comedi_device *dev,
1898 struct pcidas64_private *devpriv = dev->private;
1899 unsigned int divisor = data[4];
1908 case COMEDI_EV_SCAN_BEGIN:
1909 devpriv->ext_clock.divisor = divisor;
1910 devpriv->ext_clock.chanspec = data[2];
1918 return retval ? retval : 5;
1921 /* XXX could add support for 60xx series */
1922 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1924 const struct pcidas64_board *thisboard = dev->board_ptr;
1926 switch (thisboard->layout) {
1928 return ai_config_master_clock_4020(dev, data);
1936 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1937 struct comedi_insn *insn, unsigned int *data)
1942 case INSN_CONFIG_ALT_SOURCE:
1943 return ai_config_calibration_source(dev, data);
1944 case INSN_CONFIG_BLOCK_SIZE:
1945 return ai_config_block_size(dev, data);
1946 case INSN_CONFIG_TIMER_1:
1947 return ai_config_master_clock(dev, data);
1954 /* Gets nearest achievable timing given master clock speed, does not
1955 * take into account possible minimum/maximum divisor values. Used
1956 * by other timing checking functions. */
1957 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1959 unsigned int divisor;
1961 switch (flags & CMDF_ROUND_MASK) {
1963 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
1965 case CMDF_ROUND_DOWN:
1966 divisor = ns / TIMER_BASE;
1968 case CMDF_ROUND_NEAREST:
1970 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
1976 /* utility function that rounds desired timing to an achievable time, and
1977 * sets cmd members appropriately.
1978 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
1980 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1982 const struct pcidas64_board *thisboard = dev->board_ptr;
1983 unsigned int convert_divisor = 0, scan_divisor;
1984 static const int min_convert_divisor = 3;
1985 static const int max_convert_divisor =
1986 max_counter_value + min_convert_divisor;
1987 static const int min_scan_divisor_4020 = 2;
1988 unsigned long long max_scan_divisor, min_scan_divisor;
1990 if (cmd->convert_src == TRIG_TIMER) {
1991 if (thisboard->layout == LAYOUT_4020) {
1992 cmd->convert_arg = 0;
1994 convert_divisor = get_divisor(cmd->convert_arg,
1996 if (convert_divisor > max_convert_divisor)
1997 convert_divisor = max_convert_divisor;
1998 if (convert_divisor < min_convert_divisor)
1999 convert_divisor = min_convert_divisor;
2000 cmd->convert_arg = convert_divisor * TIMER_BASE;
2002 } else if (cmd->convert_src == TRIG_NOW) {
2003 cmd->convert_arg = 0;
2006 if (cmd->scan_begin_src == TRIG_TIMER) {
2007 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2008 if (cmd->convert_src == TRIG_TIMER) {
2009 /* XXX check for integer overflows */
2010 min_scan_divisor = convert_divisor * cmd->chanlist_len;
2012 (convert_divisor * cmd->chanlist_len - 1) +
2015 min_scan_divisor = min_scan_divisor_4020;
2016 max_scan_divisor = max_counter_value + min_scan_divisor;
2018 if (scan_divisor > max_scan_divisor)
2019 scan_divisor = max_scan_divisor;
2020 if (scan_divisor < min_scan_divisor)
2021 scan_divisor = min_scan_divisor;
2022 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2026 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2027 struct comedi_subdevice *s,
2028 struct comedi_cmd *cmd)
2030 const struct pcidas64_board *board = dev->board_ptr;
2031 unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2034 for (i = 1; i < cmd->chanlist_len; i++) {
2035 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2037 if (aref != aref0) {
2038 dev_dbg(dev->class_dev,
2039 "all elements in chanlist must use the same analog reference\n");
2044 if (board->layout == LAYOUT_4020) {
2045 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2047 for (i = 1; i < cmd->chanlist_len; i++) {
2048 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2050 if (chan != (chan0 + i)) {
2051 dev_dbg(dev->class_dev,
2052 "chanlist must use consecutive channels\n");
2056 if (cmd->chanlist_len == 3) {
2057 dev_dbg(dev->class_dev,
2058 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2066 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2067 struct comedi_cmd *cmd)
2069 const struct pcidas64_board *thisboard = dev->board_ptr;
2071 unsigned int tmp_arg, tmp_arg2;
2072 unsigned int triggers;
2074 /* Step 1 : check if triggers are trivially valid */
2076 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2078 triggers = TRIG_TIMER;
2079 if (thisboard->layout == LAYOUT_4020)
2080 triggers |= TRIG_OTHER;
2082 triggers |= TRIG_FOLLOW;
2083 err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2085 triggers = TRIG_TIMER;
2086 if (thisboard->layout == LAYOUT_4020)
2087 triggers |= TRIG_NOW;
2089 triggers |= TRIG_EXT;
2090 err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2091 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2092 err |= cfc_check_trigger_src(&cmd->stop_src,
2093 TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2098 /* Step 2a : make sure trigger sources are unique */
2100 err |= cfc_check_trigger_is_unique(cmd->start_src);
2101 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2102 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2103 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2105 /* Step 2b : and mutually compatible */
2107 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2113 /* Step 3: check if arguments are trivially valid */
2115 switch (cmd->start_src) {
2117 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2121 * start_arg is the CR_CHAN | CR_INVERT of the
2127 if (cmd->convert_src == TRIG_TIMER) {
2128 if (thisboard->layout == LAYOUT_4020) {
2129 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2131 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2132 thisboard->ai_speed);
2133 /* if scans are timed faster than conversion rate allows */
2134 if (cmd->scan_begin_src == TRIG_TIMER)
2135 err |= cfc_check_trigger_arg_min(
2136 &cmd->scan_begin_arg,
2142 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2143 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2145 switch (cmd->stop_src) {
2149 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2152 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2161 /* step 4: fix up any arguments */
2163 if (cmd->convert_src == TRIG_TIMER) {
2164 tmp_arg = cmd->convert_arg;
2165 tmp_arg2 = cmd->scan_begin_arg;
2166 check_adc_timing(dev, cmd);
2167 if (tmp_arg != cmd->convert_arg)
2169 if (tmp_arg2 != cmd->scan_begin_arg)
2176 /* Step 5: check channel list if it exists */
2177 if (cmd->chanlist && cmd->chanlist_len > 0)
2178 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2186 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2188 /* disable for now until I work out a race */
2191 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2197 static void setup_sample_counters(struct comedi_device *dev,
2198 struct comedi_cmd *cmd)
2200 struct pcidas64_private *devpriv = dev->private;
2202 if (cmd->stop_src == TRIG_COUNT) {
2203 /* set software count */
2204 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2206 /* load hardware conversion counter */
2207 if (use_hw_sample_counter(cmd)) {
2208 writew(cmd->stop_arg & 0xffff,
2209 devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2210 writew((cmd->stop_arg >> 16) & 0xff,
2211 devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2213 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2217 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2219 const struct pcidas64_board *thisboard = dev->board_ptr;
2220 struct pcidas64_private *devpriv = dev->private;
2221 unsigned int num_samples;
2223 num_samples = devpriv->ai_fifo_segment_length *
2224 thisboard->ai_fifo->sample_packing_ratio;
2225 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2226 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2231 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2232 const struct comedi_cmd *cmd)
2234 /* supposed to load counter with desired divisor minus 3 */
2235 return cmd->convert_arg / TIMER_BASE - 3;
2238 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2239 struct comedi_cmd *cmd)
2243 /* figure out how long we need to delay at end of scan */
2244 switch (cmd->scan_begin_src) {
2246 count = (cmd->scan_begin_arg -
2247 (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2251 count = cmd->convert_arg / TIMER_BASE;
2259 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2260 struct comedi_cmd *cmd)
2262 struct pcidas64_private *devpriv = dev->private;
2263 unsigned int divisor;
2265 switch (cmd->scan_begin_src) {
2267 divisor = cmd->scan_begin_arg / TIMER_BASE;
2270 divisor = devpriv->ext_clock.divisor;
2272 default: /* should never happen */
2273 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2278 /* supposed to load counter with desired divisor minus 2 for 4020 */
2282 static void select_master_clock_4020(struct comedi_device *dev,
2283 const struct comedi_cmd *cmd)
2285 struct pcidas64_private *devpriv = dev->private;
2287 /* select internal/external master clock */
2288 devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2289 if (cmd->scan_begin_src == TRIG_OTHER) {
2290 int chanspec = devpriv->ext_clock.chanspec;
2292 if (CR_CHAN(chanspec))
2293 devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2295 devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2297 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2299 writew(devpriv->hw_config_bits,
2300 devpriv->main_iobase + HW_CONFIG_REG);
2303 static void select_master_clock(struct comedi_device *dev,
2304 const struct comedi_cmd *cmd)
2306 const struct pcidas64_board *thisboard = dev->board_ptr;
2308 switch (thisboard->layout) {
2310 select_master_clock_4020(dev, cmd);
2317 static inline void dma_start_sync(struct comedi_device *dev,
2318 unsigned int channel)
2320 struct pcidas64_private *devpriv = dev->private;
2321 unsigned long flags;
2323 /* spinlock for plx dma control/status reg */
2324 spin_lock_irqsave(&dev->spinlock, flags);
2326 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2327 PLX_CLEAR_DMA_INTR_BIT,
2328 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2330 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2331 PLX_CLEAR_DMA_INTR_BIT,
2332 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2333 spin_unlock_irqrestore(&dev->spinlock, flags);
2336 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2338 const struct pcidas64_board *thisboard = dev->board_ptr;
2339 struct pcidas64_private *devpriv = dev->private;
2340 uint32_t convert_counter = 0, scan_counter = 0;
2342 check_adc_timing(dev, cmd);
2344 select_master_clock(dev, cmd);
2346 if (thisboard->layout == LAYOUT_4020) {
2347 convert_counter = ai_convert_counter_4020(dev, cmd);
2349 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2350 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2353 /* load lower 16 bits of convert interval */
2354 writew(convert_counter & 0xffff,
2355 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2356 /* load upper 8 bits of convert interval */
2357 writew((convert_counter >> 16) & 0xff,
2358 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2359 /* load lower 16 bits of scan delay */
2360 writew(scan_counter & 0xffff,
2361 devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2362 /* load upper 8 bits of scan delay */
2363 writew((scan_counter >> 16) & 0xff,
2364 devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2367 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2371 for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2372 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2373 CR_CHAN(cmd->chanlist[i]) + 1)
2375 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2376 CR_RANGE(cmd->chanlist[i]))
2378 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2384 static int setup_channel_queue(struct comedi_device *dev,
2385 const struct comedi_cmd *cmd)
2387 const struct pcidas64_board *thisboard = dev->board_ptr;
2388 struct pcidas64_private *devpriv = dev->private;
2389 unsigned short bits;
2392 if (thisboard->layout != LAYOUT_4020) {
2393 if (use_internal_queue_6xxx(cmd)) {
2394 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2395 writew(devpriv->hw_config_bits,
2396 devpriv->main_iobase + HW_CONFIG_REG);
2399 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2401 bits |= ai_range_bits_6xxx(dev,
2402 CR_RANGE(cmd->chanlist[0]));
2403 /* set single-ended / differential */
2404 bits |= se_diff_bit_6xxx(dev,
2405 CR_AREF(cmd->chanlist[0]) ==
2407 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2408 bits |= ADC_COMMON_BIT;
2409 /* set stop channel */
2410 writew(adc_chan_bits
2411 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2412 devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2413 /* set start channel, and rest of settings */
2415 devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2417 /* use external queue */
2418 if (dev->write_subdev && dev->write_subdev->busy) {
2419 warn_external_queue(dev);
2422 devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2423 writew(devpriv->hw_config_bits,
2424 devpriv->main_iobase + HW_CONFIG_REG);
2425 /* clear DAC buffer to prevent weird interactions */
2427 devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2428 /* clear queue pointer */
2429 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2430 /* load external queue */
2431 for (i = 0; i < cmd->chanlist_len; i++) {
2434 bits |= adc_chan_bits(CR_CHAN(cmd->
2437 bits |= ai_range_bits_6xxx(dev,
2441 /* set single-ended / differential */
2442 bits |= se_diff_bit_6xxx(dev,
2446 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2447 bits |= ADC_COMMON_BIT;
2448 /* mark end of queue */
2449 if (i == cmd->chanlist_len - 1)
2450 bits |= QUEUE_EOSCAN_BIT |
2453 devpriv->main_iobase +
2454 ADC_QUEUE_FIFO_REG);
2456 /* doing a queue clear is not specified in board docs,
2457 * but required for reliable operation */
2458 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2459 /* prime queue holding register */
2460 writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2463 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2465 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2466 /* select BNC inputs */
2467 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2469 for (i = 0; i < cmd->chanlist_len; i++) {
2470 unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2471 unsigned int range = CR_RANGE(cmd->chanlist[i]);
2474 devpriv->i2c_cal_range_bits |=
2475 attenuate_bit(channel);
2477 devpriv->i2c_cal_range_bits &=
2478 ~attenuate_bit(channel);
2480 /* update calibration/range i2c register only if necessary,
2481 * as it is very slow */
2482 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2483 uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2485 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2492 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2493 unsigned int dma_channel,
2494 unsigned int descriptor_bits)
2496 struct pcidas64_private *devpriv = dev->private;
2498 /* The transfer size, pci address, and local address registers
2499 * are supposedly unused during chained dma,
2500 * but I have found that left over values from last operation
2501 * occasionally cause problems with transfer of first dma
2502 * block. Initializing them to zero seems to fix the problem. */
2505 devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2506 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2508 devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2509 writel(descriptor_bits,
2510 devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2513 devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2514 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2516 devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2517 writel(descriptor_bits,
2518 devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2522 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2524 const struct pcidas64_board *thisboard = dev->board_ptr;
2525 struct pcidas64_private *devpriv = dev->private;
2526 struct comedi_async *async = s->async;
2527 struct comedi_cmd *cmd = &async->cmd;
2530 unsigned long flags;
2533 disable_ai_pacing(dev);
2536 retval = setup_channel_queue(dev, cmd);
2540 /* make sure internal calibration source is turned off */
2541 writew(0, devpriv->main_iobase + CALIBRATION_REG);
2543 set_ai_pacing(dev, cmd);
2545 setup_sample_counters(dev, cmd);
2547 enable_ai_interrupts(dev, cmd);
2549 spin_lock_irqsave(&dev->spinlock, flags);
2550 /* set mode, allow conversions through software gate */
2551 devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2552 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2553 if (thisboard->layout != LAYOUT_4020) {
2554 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2555 if (cmd->convert_src == TRIG_EXT)
2556 /* good old mode 13 */
2557 devpriv->adc_control1_bits |= adc_mode_bits(13);
2559 /* mode 8. What else could you need? */
2560 devpriv->adc_control1_bits |= adc_mode_bits(8);
2562 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2563 if (cmd->chanlist_len == 4)
2564 devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2565 else if (cmd->chanlist_len == 2)
2566 devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2567 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2568 devpriv->adc_control1_bits |=
2569 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2570 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2571 devpriv->adc_control1_bits |=
2572 adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2573 [cmd->chanlist_len - 1]));
2575 writew(devpriv->adc_control1_bits,
2576 devpriv->main_iobase + ADC_CONTROL1_REG);
2577 spin_unlock_irqrestore(&dev->spinlock, flags);
2579 /* clear adc buffer */
2580 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2582 if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2583 thisboard->layout == LAYOUT_4020) {
2584 devpriv->ai_dma_index = 0;
2586 /* set dma transfer size */
2587 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2588 devpriv->ai_dma_desc[i].transfer_size =
2589 cpu_to_le32(dma_transfer_size(dev) *
2592 /* give location of first dma descriptor */
2593 load_first_dma_descriptor(dev, 1,
2594 devpriv->ai_dma_desc_bus_addr |
2595 PLX_DESC_IN_PCI_BIT |
2596 PLX_INTR_TERM_COUNT |
2597 PLX_XFER_LOCAL_TO_PCI);
2599 dma_start_sync(dev, 1);
2602 if (thisboard->layout == LAYOUT_4020) {
2603 /* set source for external triggers */
2605 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2606 bits |= EXT_START_TRIG_BNC_BIT;
2607 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2608 bits |= EXT_STOP_TRIG_BNC_BIT;
2609 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2612 spin_lock_irqsave(&dev->spinlock, flags);
2614 /* enable pacing, triggering, etc */
2615 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2616 if (cmd->flags & CMDF_WAKE_EOS)
2617 bits |= ADC_DMA_DISABLE_BIT;
2618 /* set start trigger */
2619 if (cmd->start_src == TRIG_EXT) {
2620 bits |= ADC_START_TRIG_EXT_BITS;
2621 if (cmd->start_arg & CR_INVERT)
2622 bits |= ADC_START_TRIG_FALLING_BIT;
2623 } else if (cmd->start_src == TRIG_NOW)
2624 bits |= ADC_START_TRIG_SOFT_BITS;
2625 if (use_hw_sample_counter(cmd))
2626 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2627 writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2629 devpriv->ai_cmd_running = 1;
2631 spin_unlock_irqrestore(&dev->spinlock, flags);
2633 /* start acquisition */
2634 if (cmd->start_src == TRIG_NOW)
2635 writew(0, devpriv->main_iobase + ADC_START_REG);
2640 /* read num_samples from 16 bit wide ai fifo */
2641 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2643 struct pcidas64_private *devpriv = dev->private;
2644 struct comedi_subdevice *s = dev->read_subdev;
2645 struct comedi_async *async = s->async;
2646 struct comedi_cmd *cmd = &async->cmd;
2648 uint16_t prepost_bits;
2649 int read_segment, read_index, write_segment, write_index;
2653 /* get least significant 15 bits */
2654 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2656 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2658 /* Get most significant bits (grey code).
2659 * Different boards use different code so use a scheme
2660 * that doesn't depend on encoding. This read must
2661 * occur after reading least significant 15 bits to avoid race
2662 * with fifo switching to next segment. */
2663 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2665 /* if read and write pointers are not on the same fifo segment,
2666 * read to the end of the read segment */
2667 read_segment = adc_upper_read_ptr_code(prepost_bits);
2668 write_segment = adc_upper_write_ptr_code(prepost_bits);
2670 if (read_segment != write_segment)
2672 devpriv->ai_fifo_segment_length - read_index;
2674 num_samples = write_index - read_index;
2676 if (cmd->stop_src == TRIG_COUNT) {
2677 if (devpriv->ai_count == 0)
2679 if (num_samples > devpriv->ai_count)
2680 num_samples = devpriv->ai_count;
2682 devpriv->ai_count -= num_samples;
2685 if (num_samples < 0) {
2686 dev_err(dev->class_dev,
2687 "cb_pcidas64: bug! num_samples < 0\n");
2691 for (i = 0; i < num_samples; i++) {
2692 cfc_write_to_buffer(s,
2693 readw(devpriv->main_iobase +
2697 } while (read_segment != write_segment);
2700 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2701 * pointers. The pci-4020 hardware only supports dma transfers (it only
2702 * supports the use of pio for draining the last remaining points from the
2703 * fifo when a data acquisition operation has completed).
2705 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2707 struct pcidas64_private *devpriv = dev->private;
2708 struct comedi_subdevice *s = dev->read_subdev;
2709 struct comedi_async *async = s->async;
2710 struct comedi_cmd *cmd = &async->cmd;
2712 unsigned int max_transfer = 100000;
2715 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2717 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2719 if (cmd->stop_src == TRIG_COUNT) {
2720 if (max_transfer > devpriv->ai_count)
2721 max_transfer = devpriv->ai_count;
2724 for (i = 0; read_code != write_code && i < max_transfer;) {
2725 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2726 cfc_write_to_buffer(s, fifo_data & 0xffff);
2728 if (i < max_transfer) {
2729 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2732 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2735 devpriv->ai_count -= i;
2739 static void pio_drain_ai_fifo(struct comedi_device *dev)
2741 const struct pcidas64_board *thisboard = dev->board_ptr;
2743 if (thisboard->layout == LAYOUT_4020)
2744 pio_drain_ai_fifo_32(dev);
2746 pio_drain_ai_fifo_16(dev);
2749 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2751 const struct pcidas64_board *thisboard = dev->board_ptr;
2752 struct pcidas64_private *devpriv = dev->private;
2753 struct comedi_async *async = dev->read_subdev->async;
2754 struct comedi_cmd *cmd = &async->cmd;
2755 uint32_t next_transfer_addr;
2757 int num_samples = 0;
2758 void __iomem *pci_addr_reg;
2762 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2765 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2767 /* loop until we have read all the full buffers */
2768 for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2769 (next_transfer_addr <
2770 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2771 next_transfer_addr >=
2772 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2773 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2774 /* transfer data from dma buffer to comedi buffer */
2775 num_samples = dma_transfer_size(dev);
2776 if (cmd->stop_src == TRIG_COUNT) {
2777 if (num_samples > devpriv->ai_count)
2778 num_samples = devpriv->ai_count;
2779 devpriv->ai_count -= num_samples;
2781 cfc_write_array_to_buffer(dev->read_subdev,
2782 devpriv->ai_buffer[devpriv->
2784 num_samples * sizeof(uint16_t));
2785 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2786 ai_dma_ring_count(thisboard);
2788 /* XXX check for dma ring buffer overrun
2789 * (use end-of-chain bit to mark last unused buffer) */
2792 static void handle_ai_interrupt(struct comedi_device *dev,
2793 unsigned short status,
2794 unsigned int plx_status)
2796 const struct pcidas64_board *thisboard = dev->board_ptr;
2797 struct pcidas64_private *devpriv = dev->private;
2798 struct comedi_subdevice *s = dev->read_subdev;
2799 struct comedi_async *async = s->async;
2800 struct comedi_cmd *cmd = &async->cmd;
2801 uint8_t dma1_status;
2802 unsigned long flags;
2804 /* check for fifo overrun */
2805 if (status & ADC_OVERRUN_BIT) {
2806 dev_err(dev->class_dev, "fifo overrun\n");
2807 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2809 /* spin lock makes sure no one else changes plx dma control reg */
2810 spin_lock_irqsave(&dev->spinlock, flags);
2811 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2812 if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
2813 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2814 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2816 if (dma1_status & PLX_DMA_EN_BIT)
2817 drain_dma_buffers(dev, 1);
2819 spin_unlock_irqrestore(&dev->spinlock, flags);
2821 /* drain fifo with pio */
2822 if ((status & ADC_DONE_BIT) ||
2823 ((cmd->flags & CMDF_WAKE_EOS) &&
2824 (status & ADC_INTR_PENDING_BIT) &&
2825 (thisboard->layout != LAYOUT_4020))) {
2826 spin_lock_irqsave(&dev->spinlock, flags);
2827 if (devpriv->ai_cmd_running) {
2828 spin_unlock_irqrestore(&dev->spinlock, flags);
2829 pio_drain_ai_fifo(dev);
2831 spin_unlock_irqrestore(&dev->spinlock, flags);
2833 /* if we are have all the data, then quit */
2834 if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2835 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2836 async->events |= COMEDI_CB_EOA;
2839 comedi_handle_events(dev, s);
2842 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2844 struct pcidas64_private *devpriv = dev->private;
2845 unsigned int buffer_index;
2847 if (devpriv->ao_dma_index == 0)
2848 buffer_index = AO_DMA_RING_COUNT - 1;
2850 buffer_index = devpriv->ao_dma_index - 1;
2851 return buffer_index;
2854 static int last_ao_dma_load_completed(struct comedi_device *dev)
2856 struct pcidas64_private *devpriv = dev->private;
2857 unsigned int buffer_index;
2858 unsigned int transfer_address;
2859 unsigned short dma_status;
2861 buffer_index = prev_ao_dma_index(dev);
2862 dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2863 if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2867 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2868 if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2874 static int ao_stopped_by_error(struct comedi_device *dev,
2875 const struct comedi_cmd *cmd)
2877 struct pcidas64_private *devpriv = dev->private;
2879 if (cmd->stop_src == TRIG_NONE)
2881 if (cmd->stop_src == TRIG_COUNT) {
2882 if (devpriv->ao_count)
2884 if (last_ao_dma_load_completed(dev) == 0)
2890 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2891 unsigned short dma_status)
2893 if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2894 (dma_status & PLX_DMA_EN_BIT) == 0)
2896 if (last_ao_dma_load_completed(dev))
2902 static void restart_ao_dma(struct comedi_device *dev)
2904 struct pcidas64_private *devpriv = dev->private;
2905 unsigned int dma_desc_bits;
2908 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2909 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2910 load_first_dma_descriptor(dev, 0, dma_desc_bits);
2912 dma_start_sync(dev, 0);
2915 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2916 struct comedi_subdevice *s,
2917 unsigned short *dest,
2918 unsigned int max_bytes)
2920 struct pcidas64_private *devpriv = dev->private;
2921 struct comedi_cmd *cmd = &s->async->cmd;
2922 unsigned int nsamples = max_bytes / bytes_per_sample(s);
2923 unsigned int actual_bytes;
2925 if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count < nsamples)
2926 nsamples = devpriv->ao_count;
2928 actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2929 nsamples = actual_bytes / bytes_per_sample(s);
2930 if (cmd->stop_src == TRIG_COUNT)
2931 devpriv->ao_count -= nsamples;
2936 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2937 const struct comedi_cmd *cmd)
2939 struct pcidas64_private *devpriv = dev->private;
2940 struct comedi_subdevice *s = dev->write_subdev;
2941 unsigned int buffer_index = devpriv->ao_dma_index;
2942 unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2943 unsigned int nsamples;
2944 unsigned int nbytes;
2945 unsigned int next_bits;
2947 nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2948 devpriv->ao_buffer[buffer_index],
2953 nbytes = nsamples * bytes_per_sample(s);
2954 devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2955 /* set end of chain bit so we catch underruns */
2956 next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2957 next_bits |= PLX_END_OF_CHAIN_BIT;
2958 devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2959 /* clear end of chain bit on previous buffer now that we have set it
2960 * for the last buffer */
2961 next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2962 next_bits &= ~PLX_END_OF_CHAIN_BIT;
2963 devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2965 devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2970 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2972 struct pcidas64_private *devpriv = dev->private;
2973 unsigned int num_bytes;
2974 unsigned int next_transfer_addr;
2975 void __iomem *pci_addr_reg =
2976 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2977 unsigned int buffer_index;
2980 buffer_index = devpriv->ao_dma_index;
2981 /* don't overwrite data that hasn't been transferred yet */
2982 next_transfer_addr = readl(pci_addr_reg);
2983 if (next_transfer_addr >=
2984 devpriv->ao_buffer_bus_addr[buffer_index] &&
2985 next_transfer_addr <
2986 devpriv->ao_buffer_bus_addr[buffer_index] +
2989 num_bytes = load_ao_dma_buffer(dev, cmd);
2990 } while (num_bytes >= DMA_BUFFER_SIZE);
2993 static void handle_ao_interrupt(struct comedi_device *dev,
2994 unsigned short status, unsigned int plx_status)
2996 struct pcidas64_private *devpriv = dev->private;
2997 struct comedi_subdevice *s = dev->write_subdev;
2998 struct comedi_async *async;
2999 struct comedi_cmd *cmd;
3000 uint8_t dma0_status;
3001 unsigned long flags;
3003 /* board might not support ao, in which case write_subdev is NULL */
3009 /* spin lock makes sure no one else changes plx dma control reg */
3010 spin_lock_irqsave(&dev->spinlock, flags);
3011 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3012 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
3013 if ((dma0_status & PLX_DMA_EN_BIT) &&
3014 !(dma0_status & PLX_DMA_DONE_BIT))
3015 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3016 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3018 writeb(PLX_CLEAR_DMA_INTR_BIT,
3019 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3020 spin_unlock_irqrestore(&dev->spinlock, flags);
3021 if (dma0_status & PLX_DMA_EN_BIT) {
3022 load_ao_dma(dev, cmd);
3023 /* try to recover from dma end-of-chain event */
3024 if (ao_dma_needs_restart(dev, dma0_status))
3025 restart_ao_dma(dev);
3028 spin_unlock_irqrestore(&dev->spinlock, flags);
3031 if ((status & DAC_DONE_BIT)) {
3032 async->events |= COMEDI_CB_EOA;
3033 if (ao_stopped_by_error(dev, cmd))
3034 async->events |= COMEDI_CB_ERROR;
3036 comedi_handle_events(dev, s);
3039 static irqreturn_t handle_interrupt(int irq, void *d)
3041 struct comedi_device *dev = d;
3042 struct pcidas64_private *devpriv = dev->private;
3043 unsigned short status;
3044 uint32_t plx_status;
3047 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3048 status = readw(devpriv->main_iobase + HW_STATUS_REG);
3050 /* an interrupt before all the postconfig stuff gets done could
3051 * cause a NULL dereference if we continue through the
3052 * interrupt handler */
3056 handle_ai_interrupt(dev, status, plx_status);
3057 handle_ao_interrupt(dev, status, plx_status);
3059 /* clear possible plx9080 interrupt sources */
3060 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
3061 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3062 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3068 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3070 struct pcidas64_private *devpriv = dev->private;
3071 unsigned long flags;
3073 spin_lock_irqsave(&dev->spinlock, flags);
3074 if (devpriv->ai_cmd_running == 0) {
3075 spin_unlock_irqrestore(&dev->spinlock, flags);
3078 devpriv->ai_cmd_running = 0;
3079 spin_unlock_irqrestore(&dev->spinlock, flags);
3081 disable_ai_pacing(dev);
3088 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3089 struct comedi_insn *insn, unsigned int *data)
3091 const struct pcidas64_board *thisboard = dev->board_ptr;
3092 struct pcidas64_private *devpriv = dev->private;
3093 int chan = CR_CHAN(insn->chanspec);
3094 int range = CR_RANGE(insn->chanspec);
3096 /* do some initializing */
3097 writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3100 set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3101 writew(devpriv->dac_control1_bits,
3102 devpriv->main_iobase + DAC_CONTROL1_REG);
3104 /* write to channel */
3105 if (thisboard->layout == LAYOUT_4020) {
3106 writew(data[0] & 0xff,
3107 devpriv->main_iobase + dac_lsb_4020_reg(chan));
3108 writew((data[0] >> 8) & 0xf,
3109 devpriv->main_iobase + dac_msb_4020_reg(chan));
3111 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3114 /* remember output value */
3115 s->readback[chan] = data[0];
3120 static void set_dac_control0_reg(struct comedi_device *dev,
3121 const struct comedi_cmd *cmd)
3123 struct pcidas64_private *devpriv = dev->private;
3124 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3125 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3127 if (cmd->start_src == TRIG_EXT) {
3128 bits |= WAVEFORM_TRIG_EXT_BITS;
3129 if (cmd->start_arg & CR_INVERT)
3130 bits |= WAVEFORM_TRIG_FALLING_BIT;
3132 bits |= WAVEFORM_TRIG_SOFT_BITS;
3134 if (cmd->scan_begin_src == TRIG_EXT) {
3135 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3136 if (cmd->scan_begin_arg & CR_INVERT)
3137 bits |= DAC_EXT_UPDATE_FALLING_BIT;
3139 writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3142 static void set_dac_control1_reg(struct comedi_device *dev,
3143 const struct comedi_cmd *cmd)
3145 struct pcidas64_private *devpriv = dev->private;
3148 for (i = 0; i < cmd->chanlist_len; i++) {
3151 channel = CR_CHAN(cmd->chanlist[i]);
3152 range = CR_RANGE(cmd->chanlist[i]);
3153 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3156 devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3157 writew(devpriv->dac_control1_bits,
3158 devpriv->main_iobase + DAC_CONTROL1_REG);
3161 static void set_dac_select_reg(struct comedi_device *dev,
3162 const struct comedi_cmd *cmd)
3164 struct pcidas64_private *devpriv = dev->private;
3166 unsigned int first_channel, last_channel;
3168 first_channel = CR_CHAN(cmd->chanlist[0]);
3169 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3170 if (last_channel < first_channel)
3171 dev_err(dev->class_dev,
3172 "bug! last ao channel < first ao channel\n");
3174 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3176 writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3179 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3181 return get_divisor(ns, flags) - 2;
3184 static void set_dac_interval_regs(struct comedi_device *dev,
3185 const struct comedi_cmd *cmd)
3187 struct pcidas64_private *devpriv = dev->private;
3188 unsigned int divisor;
3190 if (cmd->scan_begin_src != TRIG_TIMER)
3193 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3194 if (divisor > max_counter_value) {
3195 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3196 divisor = max_counter_value;
3198 writew(divisor & 0xffff,
3199 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3200 writew((divisor >> 16) & 0xff,
3201 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3204 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3206 struct pcidas64_private *devpriv = dev->private;
3207 struct comedi_subdevice *s = dev->write_subdev;
3208 unsigned int nsamples;
3209 unsigned int nbytes;
3212 /* clear queue pointer too, since external queue has
3213 * weird interactions with ao fifo */
3214 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3215 writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3217 nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3218 devpriv->ao_bounce_buffer,
3223 for (i = 0; i < nsamples; i++) {
3224 writew(devpriv->ao_bounce_buffer[i],
3225 devpriv->main_iobase + DAC_FIFO_REG);
3228 if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3231 nbytes = load_ao_dma_buffer(dev, cmd);
3234 load_ao_dma(dev, cmd);
3236 dma_start_sync(dev, 0);
3241 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3242 struct comedi_subdevice *s,
3243 struct comedi_cmd *cmd)
3245 const struct pcidas64_board *thisboard = dev->board_ptr;
3249 if (thisboard->layout == LAYOUT_4020)
3251 else if (use_internal_queue_6xxx(cmd))
3256 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3257 unsigned int trig_num)
3259 struct pcidas64_private *devpriv = dev->private;
3260 struct comedi_cmd *cmd = &s->async->cmd;
3263 if (trig_num != cmd->start_arg)
3266 retval = prep_ao_dma(dev, cmd);
3270 set_dac_control0_reg(dev, cmd);
3272 if (cmd->start_src == TRIG_INT)
3273 writew(0, devpriv->main_iobase + DAC_START_REG);
3275 s->async->inttrig = NULL;
3280 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3282 struct pcidas64_private *devpriv = dev->private;
3283 struct comedi_cmd *cmd = &s->async->cmd;
3285 if (external_ai_queue_in_use(dev, s, cmd)) {
3286 warn_external_queue(dev);
3289 /* disable analog output system during setup */
3290 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3292 devpriv->ao_dma_index = 0;
3293 devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3295 set_dac_select_reg(dev, cmd);
3296 set_dac_interval_regs(dev, cmd);
3297 load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3298 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3300 set_dac_control1_reg(dev, cmd);
3301 s->async->inttrig = ao_inttrig;
3306 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3307 struct comedi_subdevice *s,
3308 struct comedi_cmd *cmd)
3310 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3313 for (i = 1; i < cmd->chanlist_len; i++) {
3314 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3316 if (chan != (chan0 + i)) {
3317 dev_dbg(dev->class_dev,
3318 "chanlist must use consecutive channels\n");
3326 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3327 struct comedi_cmd *cmd)
3329 const struct pcidas64_board *thisboard = dev->board_ptr;
3331 unsigned int tmp_arg;
3333 /* Step 1 : check if triggers are trivially valid */
3335 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3336 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3337 TRIG_TIMER | TRIG_EXT);
3338 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3339 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3340 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3345 /* Step 2a : make sure trigger sources are unique */
3347 err |= cfc_check_trigger_is_unique(cmd->start_src);
3348 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3350 /* Step 2b : and mutually compatible */
3352 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3354 if (cmd->stop_src != TRIG_COUNT &&
3355 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3361 /* Step 3: check if arguments are trivially valid */
3363 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3365 if (cmd->scan_begin_src == TRIG_TIMER) {
3366 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3367 thisboard->ao_scan_speed);
3368 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3369 max_counter_value) {
3370 cmd->scan_begin_arg = (max_counter_value + 2) *
3376 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3377 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3382 /* step 4: fix up any arguments */
3384 if (cmd->scan_begin_src == TRIG_TIMER) {
3385 tmp_arg = cmd->scan_begin_arg;
3386 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3387 cmd->flags) * TIMER_BASE;
3388 if (tmp_arg != cmd->scan_begin_arg)
3395 /* Step 5: check channel list if it exists */
3396 if (cmd->chanlist && cmd->chanlist_len > 0)
3397 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3405 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3407 struct pcidas64_private *devpriv = dev->private;
3409 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3414 static int dio_callback_4020(struct comedi_device *dev,
3415 int dir, int port, int data, unsigned long iobase)
3417 struct pcidas64_private *devpriv = dev->private;
3420 writew(data, devpriv->main_iobase + iobase + 2 * port);
3423 return readw(devpriv->main_iobase + iobase + 2 * port);
3426 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3427 struct comedi_insn *insn, unsigned int *data)
3431 bits = readb(dev->mmio + DI_REG);
3439 static int do_wbits(struct comedi_device *dev,
3440 struct comedi_subdevice *s,
3441 struct comedi_insn *insn,
3444 if (comedi_dio_update_state(s, data))
3445 writeb(s->state, dev->mmio + DO_REG);
3452 static int dio_60xx_config_insn(struct comedi_device *dev,
3453 struct comedi_subdevice *s,
3454 struct comedi_insn *insn,
3459 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3463 writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3468 static int dio_60xx_wbits(struct comedi_device *dev,
3469 struct comedi_subdevice *s,
3470 struct comedi_insn *insn,
3473 if (comedi_dio_update_state(s, data))
3474 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3476 data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3481 /* pci-6025 8800 caldac:
3482 * address 0 == dac channel 0 offset
3483 * address 1 == dac channel 0 gain
3484 * address 2 == dac channel 1 offset
3485 * address 3 == dac channel 1 gain
3486 * address 4 == fine adc offset
3487 * address 5 == coarse adc offset
3488 * address 6 == coarse adc gain
3489 * address 7 == fine adc gain
3491 /* pci-6402/16 uses all 8 channels for dac:
3492 * address 0 == dac channel 0 fine gain
3493 * address 1 == dac channel 0 coarse gain
3494 * address 2 == dac channel 0 coarse offset
3495 * address 3 == dac channel 1 coarse offset
3496 * address 4 == dac channel 1 fine gain
3497 * address 5 == dac channel 1 coarse gain
3498 * address 6 == dac channel 0 fine offset
3499 * address 7 == dac channel 1 fine offset
3502 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3505 struct pcidas64_private *devpriv = dev->private;
3506 static const int num_caldac_channels = 8;
3507 static const int bitstream_length = 11;
3508 unsigned int bitstream = ((address & 0x7) << 8) | value;
3509 unsigned int bit, register_bits;
3510 static const int caldac_8800_udelay = 1;
3512 if (address >= num_caldac_channels) {
3513 dev_err(dev->class_dev, "illegal caldac channel\n");
3516 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3518 if (bitstream & bit)
3519 register_bits |= SERIAL_DATA_IN_BIT;
3520 udelay(caldac_8800_udelay);
3521 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3522 register_bits |= SERIAL_CLOCK_BIT;
3523 udelay(caldac_8800_udelay);
3524 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3526 udelay(caldac_8800_udelay);
3527 writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3528 udelay(caldac_8800_udelay);
3529 writew(0, devpriv->main_iobase + CALIBRATION_REG);
3530 udelay(caldac_8800_udelay);
3535 static int caldac_i2c_write(struct comedi_device *dev,
3536 unsigned int caldac_channel, unsigned int value)
3538 uint8_t serial_bytes[3];
3541 /* manual has gain and offset bits switched */
3548 NOT_CLEAR_REGISTERS = 0x20,
3551 switch (caldac_channel) {
3552 case 0: /* chan 0 offset */
3553 i2c_addr = CALDAC0_I2C_ADDR;
3554 serial_bytes[0] = OFFSET_0_2;
3556 case 1: /* chan 1 offset */
3557 i2c_addr = CALDAC0_I2C_ADDR;
3558 serial_bytes[0] = OFFSET_1_3;
3560 case 2: /* chan 2 offset */
3561 i2c_addr = CALDAC1_I2C_ADDR;
3562 serial_bytes[0] = OFFSET_0_2;
3564 case 3: /* chan 3 offset */
3565 i2c_addr = CALDAC1_I2C_ADDR;
3566 serial_bytes[0] = OFFSET_1_3;
3568 case 4: /* chan 0 gain */
3569 i2c_addr = CALDAC0_I2C_ADDR;
3570 serial_bytes[0] = GAIN_0_2;
3572 case 5: /* chan 1 gain */
3573 i2c_addr = CALDAC0_I2C_ADDR;
3574 serial_bytes[0] = GAIN_1_3;
3576 case 6: /* chan 2 gain */
3577 i2c_addr = CALDAC1_I2C_ADDR;
3578 serial_bytes[0] = GAIN_0_2;
3580 case 7: /* chan 3 gain */
3581 i2c_addr = CALDAC1_I2C_ADDR;
3582 serial_bytes[0] = GAIN_1_3;
3585 dev_err(dev->class_dev, "invalid caldac channel\n");
3588 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3589 serial_bytes[2] = value & 0xff;
3590 i2c_write(dev, i2c_addr, serial_bytes, 3);
3594 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3597 const struct pcidas64_board *thisboard = dev->board_ptr;
3598 struct pcidas64_private *devpriv = dev->private;
3600 devpriv->caldac_state[channel] = value;
3602 switch (thisboard->layout) {
3605 caldac_8800_write(dev, channel, value);
3608 caldac_i2c_write(dev, channel, value);
3615 static int calib_write_insn(struct comedi_device *dev,
3616 struct comedi_subdevice *s,
3617 struct comedi_insn *insn, unsigned int *data)
3619 struct pcidas64_private *devpriv = dev->private;
3620 int channel = CR_CHAN(insn->chanspec);
3622 /* return immediately if setting hasn't changed, since
3623 * programming these things is slow */
3624 if (devpriv->caldac_state[channel] == data[0])
3627 caldac_write(dev, channel, data[0]);
3632 static int calib_read_insn(struct comedi_device *dev,
3633 struct comedi_subdevice *s, struct comedi_insn *insn,
3636 struct pcidas64_private *devpriv = dev->private;
3637 unsigned int channel = CR_CHAN(insn->chanspec);
3639 data[0] = devpriv->caldac_state[channel];
3644 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3647 struct pcidas64_private *devpriv = dev->private;
3648 static const int bitstream_length = 10;
3649 unsigned int bit, register_bits;
3650 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3651 static const int ad8402_udelay = 1;
3653 devpriv->ad8402_state[channel] = value;
3655 register_bits = SELECT_8402_64XX_BIT;
3656 udelay(ad8402_udelay);
3657 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3659 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3660 if (bitstream & bit)
3661 register_bits |= SERIAL_DATA_IN_BIT;
3663 register_bits &= ~SERIAL_DATA_IN_BIT;
3664 udelay(ad8402_udelay);
3665 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3666 udelay(ad8402_udelay);
3667 writew(register_bits | SERIAL_CLOCK_BIT,
3668 devpriv->main_iobase + CALIBRATION_REG);
3671 udelay(ad8402_udelay);
3672 writew(0, devpriv->main_iobase + CALIBRATION_REG);
3675 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3676 static int ad8402_write_insn(struct comedi_device *dev,
3677 struct comedi_subdevice *s,
3678 struct comedi_insn *insn, unsigned int *data)
3680 struct pcidas64_private *devpriv = dev->private;
3681 int channel = CR_CHAN(insn->chanspec);
3683 /* return immediately if setting hasn't changed, since
3684 * programming these things is slow */
3685 if (devpriv->ad8402_state[channel] == data[0])
3688 devpriv->ad8402_state[channel] = data[0];
3690 ad8402_write(dev, channel, data[0]);
3695 static int ad8402_read_insn(struct comedi_device *dev,
3696 struct comedi_subdevice *s,
3697 struct comedi_insn *insn, unsigned int *data)
3699 struct pcidas64_private *devpriv = dev->private;
3700 unsigned int channel = CR_CHAN(insn->chanspec);
3702 data[0] = devpriv->ad8402_state[channel];
3707 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3709 struct pcidas64_private *devpriv = dev->private;
3710 static const int bitstream_length = 11;
3711 static const int read_command = 0x6;
3712 unsigned int bitstream = (read_command << 8) | address;
3714 void __iomem * const plx_control_addr =
3715 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3717 static const int value_length = 16;
3718 static const int eeprom_udelay = 1;
3720 udelay(eeprom_udelay);
3721 devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3722 /* make sure we don't send anything to the i2c bus on 4020 */
3723 devpriv->plx_control_bits |= CTL_USERO;
3724 writel(devpriv->plx_control_bits, plx_control_addr);
3725 /* activate serial eeprom */
3726 udelay(eeprom_udelay);
3727 devpriv->plx_control_bits |= CTL_EE_CS;
3728 writel(devpriv->plx_control_bits, plx_control_addr);
3730 /* write read command and desired memory address */
3731 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3732 /* set bit to be written */
3733 udelay(eeprom_udelay);
3734 if (bitstream & bit)
3735 devpriv->plx_control_bits |= CTL_EE_W;
3737 devpriv->plx_control_bits &= ~CTL_EE_W;
3738 writel(devpriv->plx_control_bits, plx_control_addr);
3740 udelay(eeprom_udelay);
3741 devpriv->plx_control_bits |= CTL_EE_CLK;
3742 writel(devpriv->plx_control_bits, plx_control_addr);
3743 udelay(eeprom_udelay);
3744 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3745 writel(devpriv->plx_control_bits, plx_control_addr);
3747 /* read back value from eeprom memory location */
3749 for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3751 udelay(eeprom_udelay);
3752 devpriv->plx_control_bits |= CTL_EE_CLK;
3753 writel(devpriv->plx_control_bits, plx_control_addr);
3754 udelay(eeprom_udelay);
3755 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3756 writel(devpriv->plx_control_bits, plx_control_addr);
3757 udelay(eeprom_udelay);
3758 if (readl(plx_control_addr) & CTL_EE_R)
3762 /* deactivate eeprom serial input */
3763 udelay(eeprom_udelay);
3764 devpriv->plx_control_bits &= ~CTL_EE_CS;
3765 writel(devpriv->plx_control_bits, plx_control_addr);
3770 static int eeprom_read_insn(struct comedi_device *dev,
3771 struct comedi_subdevice *s,
3772 struct comedi_insn *insn, unsigned int *data)
3774 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3779 /* Allocate and initialize the subdevice structures.
3781 static int setup_subdevices(struct comedi_device *dev)
3783 const struct pcidas64_board *thisboard = dev->board_ptr;
3784 struct pcidas64_private *devpriv = dev->private;
3785 struct comedi_subdevice *s;
3789 ret = comedi_alloc_subdevices(dev, 10);
3793 s = &dev->subdevices[0];
3794 /* analog input subdevice */
3795 dev->read_subdev = s;
3796 s->type = COMEDI_SUBD_AI;
3797 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3798 if (thisboard->layout == LAYOUT_60XX)
3799 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3800 else if (thisboard->layout == LAYOUT_64XX)
3801 s->subdev_flags |= SDF_DIFF;
3802 /* XXX Number of inputs in differential mode is ignored */
3803 s->n_chan = thisboard->ai_se_chans;
3804 s->len_chanlist = 0x2000;
3805 s->maxdata = (1 << thisboard->ai_bits) - 1;
3806 s->range_table = thisboard->ai_range_table;
3807 s->insn_read = ai_rinsn;
3808 s->insn_config = ai_config_insn;
3810 s->do_cmdtest = ai_cmdtest;
3811 s->cancel = ai_cancel;
3812 if (thisboard->layout == LAYOUT_4020) {
3814 /* set adc to read from inputs
3815 * (not internal calibration sources) */
3816 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3817 /* set channels to +-5 volt input ranges */
3818 for (i = 0; i < s->n_chan; i++)
3819 devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3820 data = devpriv->i2c_cal_range_bits;
3821 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3824 /* analog output subdevice */
3825 s = &dev->subdevices[1];
3826 if (thisboard->ao_nchan) {
3827 s->type = COMEDI_SUBD_AO;
3828 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3829 SDF_GROUND | SDF_CMD_WRITE;
3830 s->n_chan = thisboard->ao_nchan;
3831 s->maxdata = (1 << thisboard->ao_bits) - 1;
3832 s->range_table = thisboard->ao_range_table;
3833 s->insn_write = ao_winsn;
3834 s->insn_read = comedi_readback_insn_read;
3836 ret = comedi_alloc_subdev_readback(s);
3840 if (ao_cmd_is_supported(thisboard)) {
3841 dev->write_subdev = s;
3842 s->do_cmdtest = ao_cmdtest;
3844 s->len_chanlist = thisboard->ao_nchan;
3845 s->cancel = ao_cancel;
3848 s->type = COMEDI_SUBD_UNUSED;
3852 s = &dev->subdevices[2];
3853 if (thisboard->layout == LAYOUT_64XX) {
3854 s->type = COMEDI_SUBD_DI;
3855 s->subdev_flags = SDF_READABLE;
3858 s->range_table = &range_digital;
3859 s->insn_bits = di_rbits;
3861 s->type = COMEDI_SUBD_UNUSED;
3863 /* digital output */
3864 if (thisboard->layout == LAYOUT_64XX) {
3865 s = &dev->subdevices[3];
3866 s->type = COMEDI_SUBD_DO;
3867 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3870 s->range_table = &range_digital;
3871 s->insn_bits = do_wbits;
3873 s->type = COMEDI_SUBD_UNUSED;
3876 s = &dev->subdevices[4];
3877 if (thisboard->has_8255) {
3878 if (thisboard->layout == LAYOUT_4020) {
3879 ret = subdev_8255_init(dev, s, dio_callback_4020,
3882 ret = subdev_8255_mm_init(dev, s, NULL,
3888 s->type = COMEDI_SUBD_UNUSED;
3891 /* 8 channel dio for 60xx */
3892 s = &dev->subdevices[5];
3893 if (thisboard->layout == LAYOUT_60XX) {
3894 s->type = COMEDI_SUBD_DIO;
3895 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3898 s->range_table = &range_digital;
3899 s->insn_config = dio_60xx_config_insn;
3900 s->insn_bits = dio_60xx_wbits;
3902 s->type = COMEDI_SUBD_UNUSED;
3905 s = &dev->subdevices[6];
3906 s->type = COMEDI_SUBD_CALIB;
3907 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3909 if (thisboard->layout == LAYOUT_4020)
3913 s->insn_read = calib_read_insn;
3914 s->insn_write = calib_write_insn;
3915 for (i = 0; i < s->n_chan; i++)
3916 caldac_write(dev, i, s->maxdata / 2);
3918 /* 2 channel ad8402 potentiometer */
3919 s = &dev->subdevices[7];
3920 if (thisboard->layout == LAYOUT_64XX) {
3921 s->type = COMEDI_SUBD_CALIB;
3922 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3924 s->insn_read = ad8402_read_insn;
3925 s->insn_write = ad8402_write_insn;
3927 for (i = 0; i < s->n_chan; i++)
3928 ad8402_write(dev, i, s->maxdata / 2);
3930 s->type = COMEDI_SUBD_UNUSED;
3932 /* serial EEPROM, if present */
3933 s = &dev->subdevices[8];
3934 if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3935 s->type = COMEDI_SUBD_MEMORY;
3936 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3938 s->maxdata = 0xffff;
3939 s->insn_read = eeprom_read_insn;
3941 s->type = COMEDI_SUBD_UNUSED;
3943 /* user counter subd XXX */
3944 s = &dev->subdevices[9];
3945 s->type = COMEDI_SUBD_UNUSED;
3950 static int auto_attach(struct comedi_device *dev,
3951 unsigned long context)
3953 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3954 const struct pcidas64_board *thisboard = NULL;
3955 struct pcidas64_private *devpriv;
3956 uint32_t local_range, local_decode;
3959 if (context < ARRAY_SIZE(pcidas64_boards))
3960 thisboard = &pcidas64_boards[context];
3963 dev->board_ptr = thisboard;
3965 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3969 retval = comedi_pci_enable(dev);
3972 pci_set_master(pcidev);
3974 /* Initialize dev->board_name */
3975 dev->board_name = thisboard->name;
3977 devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3978 devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
3980 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
3981 devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
3982 dev->mmio = pci_ioremap_bar(pcidev, 3);
3984 if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
3985 dev_warn(dev->class_dev, "failed to remap io memory\n");
3989 /* figure out what local addresses are */
3990 local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
3992 local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
3993 local_range & LMAP_MEM_MASK;
3994 devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
3995 ~local_range) | local_decode;
3996 local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
3998 local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
3999 local_range & LMAP_MEM_MASK;
4000 devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4001 ~local_range) | local_decode;
4003 retval = alloc_and_init_dma_members(dev);
4007 devpriv->hw_revision =
4008 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4009 dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4010 devpriv->hw_revision);
4012 init_stc_registers(dev);
4014 retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4015 dev->board_name, dev);
4017 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4021 dev->irq = pcidev->irq;
4022 dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4024 retval = setup_subdevices(dev);
4031 static void detach(struct comedi_device *dev)
4033 struct pcidas64_private *devpriv = dev->private;
4036 free_irq(dev->irq, dev);
4038 if (devpriv->plx9080_iobase) {
4039 disable_plx_interrupts(dev);
4040 iounmap(devpriv->plx9080_iobase);
4042 if (devpriv->main_iobase)
4043 iounmap(devpriv->main_iobase);
4047 comedi_pci_disable(dev);
4048 cb_pcidas64_free_dma(dev);
4051 static struct comedi_driver cb_pcidas64_driver = {
4052 .driver_name = "cb_pcidas64",
4053 .module = THIS_MODULE,
4054 .auto_attach = auto_attach,
4058 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4059 const struct pci_device_id *id)
4061 return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4065 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4066 { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4067 { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4068 { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4069 { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4070 { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4071 { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4072 { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4073 { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4074 { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4075 { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4076 { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4077 { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4078 { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4079 { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4080 { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4081 { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4082 { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4083 { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4084 { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4085 { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4086 { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4089 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4091 static struct pci_driver cb_pcidas64_pci_driver = {
4092 .name = "cb_pcidas64",
4093 .id_table = cb_pcidas64_pci_table,
4094 .probe = cb_pcidas64_pci_probe,
4095 .remove = comedi_pci_auto_unconfig,
4097 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4099 MODULE_AUTHOR("Comedi http://www.comedi.org");
4100 MODULE_DESCRIPTION("Comedi low-level driver");
4101 MODULE_LICENSE("GPL");