drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31
  32     You should have received a copy of the GNU General Public License
  33     along with this program; if not, write to the Free Software
  34     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  35
  36 ************************************************************************/
  37
  38 /*
  39  * Driver: cb_pcidas64
  40  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  41  *   with the PLX 9080 PCI controller
  42  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  43  * Status: works
  44  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  45  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  46  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  47  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  48  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  49  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  50  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  51  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  52  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  53  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  54  *
  55  * Configuration options:
  56  *   None.
  57  *
  58  * Manual attachment of PCI cards with the comedi_config utility is not
  59  * supported by this driver; they are attached automatically.
  60  *
  61  * These boards may be autocalibrated with the comedi_calibrate utility.
  62  *
  63  * To select the bnc trigger input on the 4020 (instead of the dio input),
  64  * specify a nonzero channel in the chanspec.  If you wish to use an external
  65  * master clock on the 4020, you may do so by setting the scan_begin_src
  66  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  67  * to configure the divisor to use for the external clock.
  68  *
  69  * Some devices are not identified because the PCI device IDs are not yet
  70  * known. If you have such a board, please let the maintainers know.
  71  */
  72
  73 /*
  74
  75 TODO:
  76         make it return error if user attempts an ai command that uses the
  77         external queue, and an ao command simultaneously user counter subdevice
  78         there are a number of boards this driver will support when they are
  79         fully released, but does not yet since the pci device id numbers
  80         are not yet available.
  81
  82         support prescaled 100khz clock for slow pacing (not available on 6000
  83         series?)
  84
  85         make ao fifo size adjustable like ai fifo
  86 */
  87
  88 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  89
  90 #include <linux/pci.h>
  91 #include <linux/delay.h>
  92 #include <linux/interrupt.h>
  93
  94 #include "../comedidev.h"
  95
  96 #include "8253.h"
  97 #include "8255.h"
  98 #include "plx9080.h"
  99 #include "comedi_fc.h"
 100
 101 #undef PCIDAS64_DEBUG           /*  disable debugging code */
 102 /* #define PCIDAS64_DEBUG         enable debugging code */
 103
 104 #ifdef PCIDAS64_DEBUG
 105 #define DEBUG_PRINT(format, args...)  pr_debug(format, ## args)
 106 #else
 107 #define DEBUG_PRINT(format, args...)  no_printk(format, ## args)
 108 #endif
 109
 110 #define TIMER_BASE 25           /*  40MHz master clock */
 111 /* 100kHz 'prescaled' clock for slow acquisition,
 112  * maybe I'll support this someday */
 113 #define PRESCALED_TIMER_BASE    10000
 114 #define DMA_BUFFER_SIZE 0x1000
 115
 116 /* maximum value that can be loaded into board's 24-bit counters*/
 117 static const int max_counter_value = 0xffffff;
 118
 119 /* PCI-DAS64xxx base addresses */
 120
 121 /* indices of base address regions */
 122 enum base_address_regions {
 123         PLX9080_BADDRINDEX = 0,
 124         MAIN_BADDRINDEX = 2,
 125         DIO_COUNTER_BADDRINDEX = 3,
 126 };
 127
 128 /* devpriv->main_iobase registers */
 129 enum write_only_registers {
 130         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 131         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 132         DAQ_SYNC_REG = 0xc,
 133         DAQ_ATRIG_LOW_4020_REG = 0xc,
 134         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 135         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 136         CALIBRATION_REG = 0x14,
 137         /*  lower 16 bits of adc sample interval counter */
 138         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 139         /*  upper 8 bits of adc sample interval counter */
 140         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 141         /*  lower 16 bits of delay interval counter */
 142         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 143         /*  upper 8 bits of delay interval counter */
 144         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 145         /*  lower 16 bits of hardware conversion/scan counter */
 146         ADC_COUNT_LOWER_REG = 0x1e,
 147         /*  upper 8 bits of hardware conversion/scan counter */
 148         ADC_COUNT_UPPER_REG = 0x20,
 149         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 150         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 151         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 152         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 153         ADC_BUFFER_CLEAR_REG = 0x2a,
 154         /*  high channel for internal queue, use adc_chan_bits() inline above */
 155         ADC_QUEUE_HIGH_REG = 0x2c,
 156         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 157         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 158         /*  lower 16 bits of dac sample interval counter */
 159         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 160         /*  upper 8 bits of dac sample interval counter */
 161         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 162         DAC_SELECT_REG = 0x60,
 163         DAC_START_REG = 0x64,
 164         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 165 };
 166
 167 static inline unsigned int dac_convert_reg(unsigned int channel)
 168 {
 169         return 0x70 + (2 * (channel & 0x1));
 170 }
 171
 172 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 173 {
 174         return 0x70 + (4 * (channel & 0x1));
 175 }
 176
 177 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 178 {
 179         return 0x72 + (4 * (channel & 0x1));
 180 }
 181
 182 enum read_only_registers {
 183         /*  hardware status register,
 184          *  reading this apparently clears pending interrupts as well */
 185         HW_STATUS_REG = 0x0,
 186         PIPE1_READ_REG = 0x4,
 187         ADC_READ_PNTR_REG = 0x8,
 188         LOWER_XFER_REG = 0x10,
 189         ADC_WRITE_PNTR_REG = 0xc,
 190         PREPOST_REG = 0x14,
 191 };
 192
 193 enum read_write_registers {
 194         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 195         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 196         ADC_QUEUE_FIFO_REG = 0x100,
 197         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 198         /* dac data fifo, has weird interactions with external channel queue */
 199         DAC_FIFO_REG = 0x300,
 200 };
 201
 202 /* devpriv->dio_counter_iobase registers */
 203 enum dio_counter_registers {
 204         DIO_8255_OFFSET = 0x0,
 205         DO_REG = 0x20,
 206         DI_REG = 0x28,
 207         DIO_DIRECTION_60XX_REG = 0x40,
 208         DIO_DATA_60XX_REG = 0x48,
 209 };
 210
 211 /* bit definitions for write-only registers */
 212
 213 enum intr_enable_contents {
 214         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 215         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 216         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 217         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 218         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 219         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 220         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 221         DAC_INTR_SRC_MASK = 0x30,
 222         DAC_INTR_QEMPTY_BITS = 0x0,
 223         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 224         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 225         EN_DAC_DONE_INTR_BIT = 0x80,
 226         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 227         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 228         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 229         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 230         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 231 };
 232
 233 enum hw_config_contents {
 234         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 235         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 236         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 237         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 238         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 239         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 240         SLOW_DAC_BIT = 0x400,
 241         /*  bit with unknown function yet given as default value in pci-das64
 242          *  manual */
 243         HW_CONFIG_DUMMY_BITS = 0x2000,
 244         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 245         DMA_CH_SELECT_BIT = 0x8000,
 246         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 247         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 248         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 249 };
 250 #define DAC_FIFO_SIZE 0x2000
 251
 252 enum daq_atrig_low_4020_contents {
 253         /*  use trig/ext clk bnc input for analog gate signal */
 254         EXT_AGATE_BNC_BIT = 0x8000,
 255         /*  use trig/ext clk bnc input for external stop trigger signal */
 256         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 257         /*  use trig/ext clk bnc input for external start trigger signal */
 258         EXT_START_TRIG_BNC_BIT = 0x2000,
 259 };
 260
 261 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 262 {
 263         return threshold & 0xfff;
 264 }
 265
 266 enum adc_control0_contents {
 267         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 268         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 269         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 270         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 271         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 272         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 273         ADC_START_TRIG_SOFT_BITS = 0x10,
 274         ADC_START_TRIG_EXT_BITS = 0x20,
 275         ADC_START_TRIG_ANALOG_BITS = 0x30,
 276         ADC_START_TRIG_MASK = 0x30,
 277         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 278         /*  external pacing uses falling edge */
 279         ADC_EXT_CONV_FALLING_BIT = 0x800,
 280         /*  enable hardware scan counter */
 281         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 282         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 283         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 284 };
 285
 286 enum adc_control1_contents {
 287         /*  should be set for boards with > 16 channels */
 288         ADC_QUEUE_CONFIG_BIT = 0x1,
 289         CONVERT_POLARITY_BIT = 0x10,
 290         EOC_POLARITY_BIT = 0x20,
 291         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 292         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 293         RETRIGGER_BIT = 0x800,
 294         ADC_LO_CHANNEL_4020_MASK = 0x300,
 295         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 296         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 297         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 298         CHANNEL_MODE_4020_MASK = 0x3000,
 299         ADC_MODE_MASK = 0xf000,
 300 };
 301
 302 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 303 {
 304         return (channel & 0x3) << 8;
 305 };
 306
 307 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 308 {
 309         return (channel & 0x3) << 10;
 310 };
 311
 312 static inline uint16_t adc_mode_bits(unsigned int mode)
 313 {
 314         return (mode & 0xf) << 12;
 315 };
 316
 317 enum calibration_contents {
 318         SELECT_8800_BIT = 0x1,
 319         SELECT_8402_64XX_BIT = 0x2,
 320         SELECT_1590_60XX_BIT = 0x2,
 321         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 322         SERIAL_DATA_IN_BIT = 0x80,
 323         SERIAL_CLOCK_BIT = 0x100,
 324         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 325         CAL_GAIN_BIT = 0x800,
 326 };
 327
 328 /* calibration sources for 6025 are:
 329  *  0 : ground
 330  *  1 : 10V
 331  *  2 : 5V
 332  *  3 : 0.5V
 333  *  4 : 0.05V
 334  *  5 : ground
 335  *  6 : dac channel 0
 336  *  7 : dac channel 1
 337  */
 338
 339 static inline uint16_t adc_src_bits(unsigned int source)
 340 {
 341         return (source & 0xf) << 3;
 342 };
 343
 344 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 345 {
 346         return (channel & 0x3) << 8;
 347 };
 348
 349 enum adc_queue_load_contents {
 350         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 351         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 352         /*  non-referenced single-ended (common-mode input) */
 353         ADC_COMMON_BIT = 0x2000,
 354         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 355         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 356 };
 357
 358 static inline uint16_t adc_chan_bits(unsigned int channel)
 359 {
 360         return channel & 0x3f;
 361 };
 362
 363 enum dac_control0_contents {
 364         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 365         DAC_CYCLIC_STOP_BIT = 0x4000,
 366         DAC_WAVEFORM_MODE_BIT = 0x100,
 367         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 368         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 369         WAVEFORM_TRIG_MASK = 0x30,
 370         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 371         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 372         WAVEFORM_TRIG_EXT_BITS = 0x20,
 373         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 374         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 375         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 376         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 377         WAVEFORM_GATE_SELECT_BIT = 0x1,
 378 };
 379
 380 enum dac_control1_contents {
 381         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 382         DAC1_EXT_REF_BIT = 0x200,
 383         DAC0_EXT_REF_BIT = 0x100,
 384         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 385         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 386         DAC_SW_GATE_BIT = 0x20,
 387         DAC1_UNIPOLAR_BIT = 0x8,
 388         DAC0_UNIPOLAR_BIT = 0x2,
 389 };
 390
 391 /* bit definitions for read-only registers */
 392 enum hw_status_contents {
 393         DAC_UNDERRUN_BIT = 0x1,
 394         ADC_OVERRUN_BIT = 0x2,
 395         DAC_ACTIVE_BIT = 0x4,
 396         ADC_ACTIVE_BIT = 0x8,
 397         DAC_INTR_PENDING_BIT = 0x10,
 398         ADC_INTR_PENDING_BIT = 0x20,
 399         DAC_DONE_BIT = 0x40,
 400         ADC_DONE_BIT = 0x80,
 401         EXT_INTR_PENDING_BIT = 0x100,
 402         ADC_STOP_BIT = 0x200,
 403 };
 404
 405 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 406 {
 407         return (hw_status_bits >> 10) & 0x3;
 408 };
 409
 410 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 411 {
 412         return (prepost_bits >> 6) & 0x3;
 413 }
 414
 415 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 416 {
 417         return (prepost_bits >> 12) & 0x3;
 418 }
 419
 420 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 421 {
 422         return (prepost_bits >> 14) & 0x3;
 423 }
 424
 425 /* I2C addresses for 4020 */
 426 enum i2c_addresses {
 427         RANGE_CAL_I2C_ADDR = 0x20,
 428         CALDAC0_I2C_ADDR = 0xc,
 429         CALDAC1_I2C_ADDR = 0xd,
 430 };
 431
 432 enum range_cal_i2c_contents {
 433         /*  bits that set what source the adc converter measures */
 434         ADC_SRC_4020_MASK = 0x70,
 435         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 436         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 437 };
 438
 439 static inline uint8_t adc_src_4020_bits(unsigned int source)
 440 {
 441         return (source << 4) & ADC_SRC_4020_MASK;
 442 };
 443
 444 static inline uint8_t attenuate_bit(unsigned int channel)
 445 {
 446         /*  attenuate channel (+-5V input range) */
 447         return 1 << (channel & 0x3);
 448 };
 449
 450 /* analog input ranges for 64xx boards */
 451 static const struct comedi_lrange ai_ranges_64xx = {
 452         8,
 453         {
 454          BIP_RANGE(10),
 455          BIP_RANGE(5),
 456          BIP_RANGE(2.5),
 457          BIP_RANGE(1.25),
 458          UNI_RANGE(10),
 459          UNI_RANGE(5),
 460          UNI_RANGE(2.5),
 461          UNI_RANGE(1.25)
 462          }
 463 };
 464
 465 /* analog input ranges for 60xx boards */
 466 static const struct comedi_lrange ai_ranges_60xx = {
 467         4,
 468         {
 469          BIP_RANGE(10),
 470          BIP_RANGE(5),
 471          BIP_RANGE(0.5),
 472          BIP_RANGE(0.05),
 473          }
 474 };
 475
 476 /* analog input ranges for 6030, etc boards */
 477 static const struct comedi_lrange ai_ranges_6030 = {
 478         14,
 479         {
 480          BIP_RANGE(10),
 481          BIP_RANGE(5),
 482          BIP_RANGE(2),
 483          BIP_RANGE(1),
 484          BIP_RANGE(0.5),
 485          BIP_RANGE(0.2),
 486          BIP_RANGE(0.1),
 487          UNI_RANGE(10),
 488          UNI_RANGE(5),
 489          UNI_RANGE(2),
 490          UNI_RANGE(1),
 491          UNI_RANGE(0.5),
 492          UNI_RANGE(0.2),
 493          UNI_RANGE(0.1),
 494          }
 495 };
 496
 497 /* analog input ranges for 6052, etc boards */
 498 static const struct comedi_lrange ai_ranges_6052 = {
 499         15,
 500         {
 501          BIP_RANGE(10),
 502          BIP_RANGE(5),
 503          BIP_RANGE(2.5),
 504          BIP_RANGE(1),
 505          BIP_RANGE(0.5),
 506          BIP_RANGE(0.25),
 507          BIP_RANGE(0.1),
 508          BIP_RANGE(0.05),
 509          UNI_RANGE(10),
 510          UNI_RANGE(5),
 511          UNI_RANGE(2),
 512          UNI_RANGE(1),
 513          UNI_RANGE(0.5),
 514          UNI_RANGE(0.2),
 515          UNI_RANGE(0.1),
 516          }
 517 };
 518
 519 /* analog input ranges for 4020 board */
 520 static const struct comedi_lrange ai_ranges_4020 = {
 521         2,
 522         {
 523          BIP_RANGE(5),
 524          BIP_RANGE(1),
 525          }
 526 };
 527
 528 /* analog output ranges */
 529 static const struct comedi_lrange ao_ranges_64xx = {
 530         4,
 531         {
 532          BIP_RANGE(5),
 533          BIP_RANGE(10),
 534          UNI_RANGE(5),
 535          UNI_RANGE(10),
 536          }
 537 };
 538
 539 static const int ao_range_code_64xx[] = {
 540         0x0,
 541         0x1,
 542         0x2,
 543         0x3,
 544 };
 545
 546 static const struct comedi_lrange ao_ranges_60xx = {
 547         1,
 548         {
 549          BIP_RANGE(10),
 550          }
 551 };
 552
 553 static const int ao_range_code_60xx[] = {
 554         0x0,
 555 };
 556
 557 static const struct comedi_lrange ao_ranges_6030 = {
 558         2,
 559         {
 560          BIP_RANGE(10),
 561          UNI_RANGE(10),
 562          }
 563 };
 564
 565 static const int ao_range_code_6030[] = {
 566         0x0,
 567         0x2,
 568 };
 569
 570 static const struct comedi_lrange ao_ranges_4020 = {
 571         2,
 572         {
 573          BIP_RANGE(5),
 574          BIP_RANGE(10),
 575          }
 576 };
 577
 578 static const int ao_range_code_4020[] = {
 579         0x1,
 580         0x0,
 581 };
 582
 583 enum register_layout {
 584         LAYOUT_60XX,
 585         LAYOUT_64XX,
 586         LAYOUT_4020,
 587 };
 588
 589 struct hw_fifo_info {
 590         unsigned int num_segments;
 591         unsigned int max_segment_length;
 592         unsigned int sample_packing_ratio;
 593         uint16_t fifo_size_reg_mask;
 594 };
 595
 596 struct pcidas64_board {
 597         const char *name;
 598         int device_id;          /*  pci device id */
 599         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 600         int ai_bits;            /*  analog input resolution */
 601         int ai_speed;           /*  fastest conversion period in ns */
 602         const struct comedi_lrange *ai_range_table;
 603         int ao_nchan;           /*  number of analog out channels */
 604         int ao_bits;            /*  analog output resolution */
 605         int ao_scan_speed;      /*  analog output scan speed */
 606         const struct comedi_lrange *ao_range_table;
 607         const int *ao_range_code;
 608         const struct hw_fifo_info *const ai_fifo;
 609         /*  different board families have slightly different registers */
 610         enum register_layout layout;
 611         unsigned has_8255:1;
 612 };
 613
 614 static const struct hw_fifo_info ai_fifo_4020 = {
 615         .num_segments = 2,
 616         .max_segment_length = 0x8000,
 617         .sample_packing_ratio = 2,
 618         .fifo_size_reg_mask = 0x7f,
 619 };
 620
 621 static const struct hw_fifo_info ai_fifo_64xx = {
 622         .num_segments = 4,
 623         .max_segment_length = 0x800,
 624         .sample_packing_ratio = 1,
 625         .fifo_size_reg_mask = 0x3f,
 626 };
 627
 628 static const struct hw_fifo_info ai_fifo_60xx = {
 629         .num_segments = 4,
 630         .max_segment_length = 0x800,
 631         .sample_packing_ratio = 1,
 632         .fifo_size_reg_mask = 0x7f,
 633 };
 634
 635 /* maximum number of dma transfers we will chain together into a ring
 636  * (and the maximum number of dma buffers we maintain) */
 637 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 638 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 639 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 640 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 641 {
 642         if (board->layout == LAYOUT_4020)
 643                 return MAX_AI_DMA_RING_COUNT;
 644         else
 645                 return MIN_AI_DMA_RING_COUNT;
 646 }
 647
 648 static const int bytes_in_sample = 2;
 649
 650 static const struct pcidas64_board pcidas64_boards[] = {
 651         {
 652          .name = "pci-das6402/16",
 653          .device_id = 0x1d,
 654          .ai_se_chans = 64,
 655          .ai_bits = 16,
 656          .ai_speed = 5000,
 657          .ao_nchan = 2,
 658          .ao_bits = 16,
 659          .ao_scan_speed = 10000,
 660          .layout = LAYOUT_64XX,
 661          .ai_range_table = &ai_ranges_64xx,
 662          .ao_range_table = &ao_ranges_64xx,
 663          .ao_range_code = ao_range_code_64xx,
 664          .ai_fifo = &ai_fifo_64xx,
 665          .has_8255 = 1,
 666          },
 667         {
 668          .name = "pci-das6402/12",      /*  XXX check */
 669          .device_id = 0x1e,
 670          .ai_se_chans = 64,
 671          .ai_bits = 12,
 672          .ai_speed = 5000,
 673          .ao_nchan = 2,
 674          .ao_bits = 12,
 675          .ao_scan_speed = 10000,
 676          .layout = LAYOUT_64XX,
 677          .ai_range_table = &ai_ranges_64xx,
 678          .ao_range_table = &ao_ranges_64xx,
 679          .ao_range_code = ao_range_code_64xx,
 680          .ai_fifo = &ai_fifo_64xx,
 681          .has_8255 = 1,
 682          },
 683         {
 684          .name = "pci-das64/m1/16",
 685          .device_id = 0x35,
 686          .ai_se_chans = 64,
 687          .ai_bits = 16,
 688          .ai_speed = 1000,
 689          .ao_nchan = 2,
 690          .ao_bits = 16,
 691          .ao_scan_speed = 10000,
 692          .layout = LAYOUT_64XX,
 693          .ai_range_table = &ai_ranges_64xx,
 694          .ao_range_table = &ao_ranges_64xx,
 695          .ao_range_code = ao_range_code_64xx,
 696          .ai_fifo = &ai_fifo_64xx,
 697          .has_8255 = 1,
 698          },
 699         {
 700          .name = "pci-das64/m2/16",
 701          .device_id = 0x36,
 702          .ai_se_chans = 64,
 703          .ai_bits = 16,
 704          .ai_speed = 500,
 705          .ao_nchan = 2,
 706          .ao_bits = 16,
 707          .ao_scan_speed = 10000,
 708          .layout = LAYOUT_64XX,
 709          .ai_range_table = &ai_ranges_64xx,
 710          .ao_range_table = &ao_ranges_64xx,
 711          .ao_range_code = ao_range_code_64xx,
 712          .ai_fifo = &ai_fifo_64xx,
 713          .has_8255 = 1,
 714          },
 715         {
 716          .name = "pci-das64/m3/16",
 717          .device_id = 0x37,
 718          .ai_se_chans = 64,
 719          .ai_bits = 16,
 720          .ai_speed = 333,
 721          .ao_nchan = 2,
 722          .ao_bits = 16,
 723          .ao_scan_speed = 10000,
 724          .layout = LAYOUT_64XX,
 725          .ai_range_table = &ai_ranges_64xx,
 726          .ao_range_table = &ao_ranges_64xx,
 727          .ao_range_code = ao_range_code_64xx,
 728          .ai_fifo = &ai_fifo_64xx,
 729          .has_8255 = 1,
 730          },
 731         {
 732          .name = "pci-das6013",
 733          .device_id = 0x78,
 734          .ai_se_chans = 16,
 735          .ai_bits = 16,
 736          .ai_speed = 5000,
 737          .ao_nchan = 0,
 738          .ao_bits = 16,
 739          .layout = LAYOUT_60XX,
 740          .ai_range_table = &ai_ranges_60xx,
 741          .ao_range_table = &ao_ranges_60xx,
 742          .ao_range_code = ao_range_code_60xx,
 743          .ai_fifo = &ai_fifo_60xx,
 744          .has_8255 = 0,
 745          },
 746         {
 747          .name = "pci-das6014",
 748          .device_id = 0x79,
 749          .ai_se_chans = 16,
 750          .ai_bits = 16,
 751          .ai_speed = 5000,
 752          .ao_nchan = 2,
 753          .ao_bits = 16,
 754          .ao_scan_speed = 100000,
 755          .layout = LAYOUT_60XX,
 756          .ai_range_table = &ai_ranges_60xx,
 757          .ao_range_table = &ao_ranges_60xx,
 758          .ao_range_code = ao_range_code_60xx,
 759          .ai_fifo = &ai_fifo_60xx,
 760          .has_8255 = 0,
 761          },
 762         {
 763          .name = "pci-das6023",
 764          .device_id = 0x5d,
 765          .ai_se_chans = 16,
 766          .ai_bits = 12,
 767          .ai_speed = 5000,
 768          .ao_nchan = 0,
 769          .ao_scan_speed = 100000,
 770          .layout = LAYOUT_60XX,
 771          .ai_range_table = &ai_ranges_60xx,
 772          .ao_range_table = &ao_ranges_60xx,
 773          .ao_range_code = ao_range_code_60xx,
 774          .ai_fifo = &ai_fifo_60xx,
 775          .has_8255 = 1,
 776          },
 777         {
 778          .name = "pci-das6025",
 779          .device_id = 0x5e,
 780          .ai_se_chans = 16,
 781          .ai_bits = 12,
 782          .ai_speed = 5000,
 783          .ao_nchan = 2,
 784          .ao_bits = 12,
 785          .ao_scan_speed = 100000,
 786          .layout = LAYOUT_60XX,
 787          .ai_range_table = &ai_ranges_60xx,
 788          .ao_range_table = &ao_ranges_60xx,
 789          .ao_range_code = ao_range_code_60xx,
 790          .ai_fifo = &ai_fifo_60xx,
 791          .has_8255 = 1,
 792          },
 793         {
 794          .name = "pci-das6030",
 795          .device_id = 0x5f,
 796          .ai_se_chans = 16,
 797          .ai_bits = 16,
 798          .ai_speed = 10000,
 799          .ao_nchan = 2,
 800          .ao_bits = 16,
 801          .ao_scan_speed = 10000,
 802          .layout = LAYOUT_60XX,
 803          .ai_range_table = &ai_ranges_6030,
 804          .ao_range_table = &ao_ranges_6030,
 805          .ao_range_code = ao_range_code_6030,
 806          .ai_fifo = &ai_fifo_60xx,
 807          .has_8255 = 0,
 808          },
 809         {
 810          .name = "pci-das6031",
 811          .device_id = 0x60,
 812          .ai_se_chans = 64,
 813          .ai_bits = 16,
 814          .ai_speed = 10000,
 815          .ao_nchan = 2,
 816          .ao_bits = 16,
 817          .ao_scan_speed = 10000,
 818          .layout = LAYOUT_60XX,
 819          .ai_range_table = &ai_ranges_6030,
 820          .ao_range_table = &ao_ranges_6030,
 821          .ao_range_code = ao_range_code_6030,
 822          .ai_fifo = &ai_fifo_60xx,
 823          .has_8255 = 0,
 824          },
 825         {
 826          .name = "pci-das6032",
 827          .device_id = 0x61,
 828          .ai_se_chans = 16,
 829          .ai_bits = 16,
 830          .ai_speed = 10000,
 831          .ao_nchan = 0,
 832          .layout = LAYOUT_60XX,
 833          .ai_range_table = &ai_ranges_6030,
 834          .ai_fifo = &ai_fifo_60xx,
 835          .has_8255 = 0,
 836          },
 837         {
 838          .name = "pci-das6033",
 839          .device_id = 0x62,
 840          .ai_se_chans = 64,
 841          .ai_bits = 16,
 842          .ai_speed = 10000,
 843          .ao_nchan = 0,
 844          .layout = LAYOUT_60XX,
 845          .ai_range_table = &ai_ranges_6030,
 846          .ai_fifo = &ai_fifo_60xx,
 847          .has_8255 = 0,
 848          },
 849         {
 850          .name = "pci-das6034",
 851          .device_id = 0x63,
 852          .ai_se_chans = 16,
 853          .ai_bits = 16,
 854          .ai_speed = 5000,
 855          .ao_nchan = 0,
 856          .ao_scan_speed = 0,
 857          .layout = LAYOUT_60XX,
 858          .ai_range_table = &ai_ranges_60xx,
 859          .ai_fifo = &ai_fifo_60xx,
 860          .has_8255 = 0,
 861          },
 862         {
 863          .name = "pci-das6035",
 864          .device_id = 0x64,
 865          .ai_se_chans = 16,
 866          .ai_bits = 16,
 867          .ai_speed = 5000,
 868          .ao_nchan = 2,
 869          .ao_bits = 12,
 870          .ao_scan_speed = 100000,
 871          .layout = LAYOUT_60XX,
 872          .ai_range_table = &ai_ranges_60xx,
 873          .ao_range_table = &ao_ranges_60xx,
 874          .ao_range_code = ao_range_code_60xx,
 875          .ai_fifo = &ai_fifo_60xx,
 876          .has_8255 = 0,
 877          },
 878         {
 879          .name = "pci-das6036",
 880          .device_id = 0x6f,
 881          .ai_se_chans = 16,
 882          .ai_bits = 16,
 883          .ai_speed = 5000,
 884          .ao_nchan = 2,
 885          .ao_bits = 16,
 886          .ao_scan_speed = 100000,
 887          .layout = LAYOUT_60XX,
 888          .ai_range_table = &ai_ranges_60xx,
 889          .ao_range_table = &ao_ranges_60xx,
 890          .ao_range_code = ao_range_code_60xx,
 891          .ai_fifo = &ai_fifo_60xx,
 892          .has_8255 = 0,
 893          },
 894         {
 895          .name = "pci-das6040",
 896          .device_id = 0x65,
 897          .ai_se_chans = 16,
 898          .ai_bits = 12,
 899          .ai_speed = 2000,
 900          .ao_nchan = 2,
 901          .ao_bits = 12,
 902          .ao_scan_speed = 1000,
 903          .layout = LAYOUT_60XX,
 904          .ai_range_table = &ai_ranges_6052,
 905          .ao_range_table = &ao_ranges_6030,
 906          .ao_range_code = ao_range_code_6030,
 907          .ai_fifo = &ai_fifo_60xx,
 908          .has_8255 = 0,
 909          },
 910         {
 911          .name = "pci-das6052",
 912          .device_id = 0x66,
 913          .ai_se_chans = 16,
 914          .ai_bits = 16,
 915          .ai_speed = 3333,
 916          .ao_nchan = 2,
 917          .ao_bits = 16,
 918          .ao_scan_speed = 3333,
 919          .layout = LAYOUT_60XX,
 920          .ai_range_table = &ai_ranges_6052,
 921          .ao_range_table = &ao_ranges_6030,
 922          .ao_range_code = ao_range_code_6030,
 923          .ai_fifo = &ai_fifo_60xx,
 924          .has_8255 = 0,
 925          },
 926         {
 927          .name = "pci-das6070",
 928          .device_id = 0x67,
 929          .ai_se_chans = 16,
 930          .ai_bits = 12,
 931          .ai_speed = 800,
 932          .ao_nchan = 2,
 933          .ao_bits = 12,
 934          .ao_scan_speed = 1000,
 935          .layout = LAYOUT_60XX,
 936          .ai_range_table = &ai_ranges_6052,
 937          .ao_range_table = &ao_ranges_6030,
 938          .ao_range_code = ao_range_code_6030,
 939          .ai_fifo = &ai_fifo_60xx,
 940          .has_8255 = 0,
 941          },
 942         {
 943          .name = "pci-das6071",
 944          .device_id = 0x68,
 945          .ai_se_chans = 64,
 946          .ai_bits = 12,
 947          .ai_speed = 800,
 948          .ao_nchan = 2,
 949          .ao_bits = 12,
 950          .ao_scan_speed = 1000,
 951          .layout = LAYOUT_60XX,
 952          .ai_range_table = &ai_ranges_6052,
 953          .ao_range_table = &ao_ranges_6030,
 954          .ao_range_code = ao_range_code_6030,
 955          .ai_fifo = &ai_fifo_60xx,
 956          .has_8255 = 0,
 957          },
 958         {
 959          .name = "pci-das4020/12",
 960          .device_id = 0x52,
 961          .ai_se_chans = 4,
 962          .ai_bits = 12,
 963          .ai_speed = 50,
 964          .ao_bits = 12,
 965          .ao_nchan = 2,
 966          .ao_scan_speed = 0,    /*  no hardware pacing on ao */
 967          .layout = LAYOUT_4020,
 968          .ai_range_table = &ai_ranges_4020,
 969          .ao_range_table = &ao_ranges_4020,
 970          .ao_range_code = ao_range_code_4020,
 971          .ai_fifo = &ai_fifo_4020,
 972          .has_8255 = 1,
 973          },
 974 #if 0
 975         {
 976          .name = "pci-das6402/16/jr",
 977          .device_id = 0         /*  XXX, */
 978          .ai_se_chans = 64,
 979          .ai_bits = 16,
 980          .ai_speed = 5000,
 981          .ao_nchan = 0,
 982          .ao_scan_speed = 10000,
 983          .layout = LAYOUT_64XX,
 984          .ai_range_table = &ai_ranges_64xx,
 985          .ai_fifo = ai_fifo_64xx,
 986          .has_8255 = 1,
 987          },
 988         {
 989          .name = "pci-das64/m1/16/jr",
 990          .device_id = 0         /*  XXX, */
 991          .ai_se_chans = 64,
 992          .ai_bits = 16,
 993          .ai_speed = 1000,
 994          .ao_nchan = 0,
 995          .ao_scan_speed = 10000,
 996          .layout = LAYOUT_64XX,
 997          .ai_range_table = &ai_ranges_64xx,
 998          .ai_fifo = ai_fifo_64xx,
 999          .has_8255 = 1,
1000          },
1001         {
1002          .name = "pci-das64/m2/16/jr",
1003          .device_id = 0         /*  XXX, */
1004          .ai_se_chans = 64,
1005          .ai_bits = 16,
1006          .ai_speed = 500,
1007          .ao_nchan = 0,
1008          .ao_scan_speed = 10000,
1009          .layout = LAYOUT_64XX,
1010          .ai_range_table = &ai_ranges_64xx,
1011          .ai_fifo = ai_fifo_64xx,
1012          .has_8255 = 1,
1013          },
1014         {
1015          .name = "pci-das64/m3/16/jr",
1016          .device_id = 0         /*  XXX, */
1017          .ai_se_chans = 64,
1018          .ai_bits = 16,
1019          .ai_speed = 333,
1020          .ao_nchan = 0,
1021          .ao_scan_speed = 10000,
1022          .layout = LAYOUT_64XX,
1023          .ai_range_table = &ai_ranges_64xx,
1024          .ai_fifo = ai_fifo_64xx,
1025          .has_8255 = 1,
1026          },
1027         {
1028          .name = "pci-das64/m1/14",
1029          .device_id = 0,        /*  XXX */
1030          .ai_se_chans = 64,
1031          .ai_bits = 14,
1032          .ai_speed = 1000,
1033          .ao_nchan = 2,
1034          .ao_scan_speed = 10000,
1035          .layout = LAYOUT_64XX,
1036          .ai_range_table = &ai_ranges_64xx,
1037          .ai_fifo = ai_fifo_64xx,
1038          .has_8255 = 1,
1039          },
1040         {
1041          .name = "pci-das64/m2/14",
1042          .device_id = 0,        /*  XXX */
1043          .ai_se_chans = 64,
1044          .ai_bits = 14,
1045          .ai_speed = 500,
1046          .ao_nchan = 2,
1047          .ao_scan_speed = 10000,
1048          .layout = LAYOUT_64XX,
1049          .ai_range_table = &ai_ranges_64xx,
1050          .ai_fifo = ai_fifo_64xx,
1051          .has_8255 = 1,
1052          },
1053         {
1054          .name = "pci-das64/m3/14",
1055          .device_id = 0,        /*  XXX */
1056          .ai_se_chans = 64,
1057          .ai_bits = 14,
1058          .ai_speed = 333,
1059          .ao_nchan = 2,
1060          .ao_scan_speed = 10000,
1061          .layout = LAYOUT_64XX,
1062          .ai_range_table = &ai_ranges_64xx,
1063          .ai_fifo = ai_fifo_64xx,
1064          .has_8255 = 1,
1065          },
1066 #endif
1067 };
1068
1069 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1070                                               int use_differential)
1071 {
1072         const struct pcidas64_board *thisboard = comedi_board(dev);
1073
1074         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1075             (thisboard->layout == LAYOUT_60XX && use_differential))
1076                 return ADC_SE_DIFF_BIT;
1077         else
1078                 return 0;
1079 };
1080
1081 struct ext_clock_info {
1082         /*  master clock divisor to use for scans with external master clock */
1083         unsigned int divisor;
1084         /*  chanspec for master clock input when used as scan begin src */
1085         unsigned int chanspec;
1086 };
1087
1088 /* this structure is for data unique to this hardware driver. */
1089 struct pcidas64_private {
1090         /*  base addresses (physical) */
1091         resource_size_t plx9080_phys_iobase;
1092         resource_size_t main_phys_iobase;
1093         resource_size_t dio_counter_phys_iobase;
1094         /*  base addresses (ioremapped) */
1095         void __iomem *plx9080_iobase;
1096         void __iomem *main_iobase;
1097         void __iomem *dio_counter_iobase;
1098         /*  local address (used by dma controller) */
1099         uint32_t local0_iobase;
1100         uint32_t local1_iobase;
1101         /*  number of analog input samples remaining */
1102         volatile unsigned int ai_count;
1103         /*  dma buffers for analog input */
1104         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1105         /*  physical addresses of ai dma buffers */
1106         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1107         /*  array of ai dma descriptors read by plx9080,
1108          *  allocated to get proper alignment */
1109         struct plx_dma_desc *ai_dma_desc;
1110         /*  physical address of ai dma descriptor array */
1111         dma_addr_t ai_dma_desc_bus_addr;
1112         /*  index of the ai dma descriptor/buffer
1113          *  that is currently being used */
1114         volatile unsigned int ai_dma_index;
1115         /*  dma buffers for analog output */
1116         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1117         /*  physical addresses of ao dma buffers */
1118         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1119         struct plx_dma_desc *ao_dma_desc;
1120         dma_addr_t ao_dma_desc_bus_addr;
1121         /*  keeps track of buffer where the next ao sample should go */
1122         volatile unsigned int ao_dma_index;
1123         /*  number of analog output samples remaining */
1124         volatile unsigned long ao_count;
1125         /*  remember what the analog outputs are set to, to allow readback */
1126         volatile unsigned int ao_value[2];
1127         unsigned int hw_revision;       /*  stc chip hardware revision number */
1128         /*  last bits sent to INTR_ENABLE_REG register */
1129         volatile unsigned int intr_enable_bits;
1130         /*  last bits sent to ADC_CONTROL1_REG register */
1131         volatile uint16_t adc_control1_bits;
1132         /*  last bits sent to FIFO_SIZE_REG register */
1133         volatile uint16_t fifo_size_bits;
1134         /*  last bits sent to HW_CONFIG_REG register */
1135         volatile uint16_t hw_config_bits;
1136         volatile uint16_t dac_control1_bits;
1137         /*  last bits written to plx9080 control register */
1138         volatile uint32_t plx_control_bits;
1139         /*  last bits written to plx interrupt control and status register */
1140         volatile uint32_t plx_intcsr_bits;
1141         /*  index of calibration source readable through ai ch0 */
1142         volatile int calibration_source;
1143         /*  bits written to i2c calibration/range register */
1144         volatile uint8_t i2c_cal_range_bits;
1145         /*  configure digital triggers to trigger on falling edge */
1146         volatile unsigned int ext_trig_falling;
1147         /*  states of various devices stored to enable read-back */
1148         unsigned int ad8402_state[2];
1149         unsigned int caldac_state[8];
1150         volatile short ai_cmd_running;
1151         unsigned int ai_fifo_segment_length;
1152         struct ext_clock_info ext_clock;
1153         short ao_bounce_buffer[DAC_FIFO_SIZE];
1154 };
1155
1156 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1157                                        unsigned int range_index)
1158 {
1159         const struct pcidas64_board *thisboard = comedi_board(dev);
1160         const struct comedi_krange *range =
1161                 &thisboard->ai_range_table->range[range_index];
1162         unsigned int bits = 0;
1163
1164         switch (range->max) {
1165         case 10000000:
1166                 bits = 0x000;
1167                 break;
1168         case 5000000:
1169                 bits = 0x100;
1170                 break;
1171         case 2000000:
1172         case 2500000:
1173                 bits = 0x200;
1174                 break;
1175         case 1000000:
1176         case 1250000:
1177                 bits = 0x300;
1178                 break;
1179         case 500000:
1180                 bits = 0x400;
1181                 break;
1182         case 200000:
1183         case 250000:
1184                 bits = 0x500;
1185                 break;
1186         case 100000:
1187                 bits = 0x600;
1188                 break;
1189         case 50000:
1190                 bits = 0x700;
1191                 break;
1192         default:
1193                 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1194                 break;
1195         }
1196         if (range->min == 0)
1197                 bits += 0x900;
1198         return bits;
1199 }
1200
1201 static unsigned int hw_revision(const struct comedi_device *dev,
1202                                 uint16_t hw_status_bits)
1203 {
1204         const struct pcidas64_board *thisboard = comedi_board(dev);
1205
1206         if (thisboard->layout == LAYOUT_4020)
1207                 return (hw_status_bits >> 13) & 0x7;
1208
1209         return (hw_status_bits >> 12) & 0xf;
1210 }
1211
1212 static void set_dac_range_bits(struct comedi_device *dev,
1213                                volatile uint16_t *bits, unsigned int channel,
1214                                unsigned int range)
1215 {
1216         const struct pcidas64_board *thisboard = comedi_board(dev);
1217         unsigned int code = thisboard->ao_range_code[range];
1218
1219         if (channel > 1)
1220                 comedi_error(dev, "bug! bad channel?");
1221         if (code & ~0x3)
1222                 comedi_error(dev, "bug! bad range code?");
1223
1224         *bits &= ~(0x3 << (2 * channel));
1225         *bits |= code << (2 * channel);
1226 };
1227
1228 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1229 {
1230         return board->ao_nchan && board->layout != LAYOUT_4020;
1231 }
1232
1233 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1234 {
1235         struct pcidas64_private *devpriv = dev->private;
1236         unsigned long flags;
1237
1238         /*  spinlock for plx dma control/status reg */
1239         spin_lock_irqsave(&dev->spinlock, flags);
1240
1241         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1242
1243         spin_unlock_irqrestore(&dev->spinlock, flags);
1244 }
1245
1246 static void disable_plx_interrupts(struct comedi_device *dev)
1247 {
1248         struct pcidas64_private *devpriv = dev->private;
1249
1250         devpriv->plx_intcsr_bits = 0;
1251         writel(devpriv->plx_intcsr_bits,
1252                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1253 }
1254
1255 static void disable_ai_interrupts(struct comedi_device *dev)
1256 {
1257         struct pcidas64_private *devpriv = dev->private;
1258         unsigned long flags;
1259
1260         spin_lock_irqsave(&dev->spinlock, flags);
1261         devpriv->intr_enable_bits &=
1262                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1263                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1264                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1265         writew(devpriv->intr_enable_bits,
1266                devpriv->main_iobase + INTR_ENABLE_REG);
1267         spin_unlock_irqrestore(&dev->spinlock, flags);
1268
1269         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1270 }
1271
1272 static void enable_ai_interrupts(struct comedi_device *dev,
1273                                  const struct comedi_cmd *cmd)
1274 {
1275         const struct pcidas64_board *thisboard = comedi_board(dev);
1276         struct pcidas64_private *devpriv = dev->private;
1277         uint32_t bits;
1278         unsigned long flags;
1279
1280         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1281                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1282         /*  Use pio transfer and interrupt on end of conversion
1283          *  if TRIG_WAKE_EOS flag is set. */
1284         if (cmd->flags & TRIG_WAKE_EOS) {
1285                 /*  4020 doesn't support pio transfers except for fifo dregs */
1286                 if (thisboard->layout != LAYOUT_4020)
1287                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1288         }
1289         spin_lock_irqsave(&dev->spinlock, flags);
1290         devpriv->intr_enable_bits |= bits;
1291         writew(devpriv->intr_enable_bits,
1292                devpriv->main_iobase + INTR_ENABLE_REG);
1293         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1294         spin_unlock_irqrestore(&dev->spinlock, flags);
1295 }
1296
1297 /* initialize plx9080 chip */
1298 static void init_plx9080(struct comedi_device *dev)
1299 {
1300         const struct pcidas64_board *thisboard = comedi_board(dev);
1301         struct pcidas64_private *devpriv = dev->private;
1302         uint32_t bits;
1303         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1304
1305         devpriv->plx_control_bits =
1306                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1307
1308         /*  plx9080 dump */
1309         DEBUG_PRINT(" plx interrupt status 0x%x\n",
1310                     readl(plx_iobase + PLX_INTRCS_REG));
1311         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1312         DEBUG_PRINT(" plx control reg 0x%x\n", devpriv->plx_control_bits);
1313         DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1314                     readl(plx_iobase + PLX_MARB_REG));
1315         DEBUG_PRINT(" plx region0 reg 0x%x\n",
1316                     readl(plx_iobase + PLX_REGION0_REG));
1317         DEBUG_PRINT(" plx region1 reg 0x%x\n",
1318                     readl(plx_iobase + PLX_REGION1_REG));
1319
1320         DEBUG_PRINT(" plx revision 0x%x\n",
1321                     readl(plx_iobase + PLX_REVISION_REG));
1322         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1323                     readl(plx_iobase + PLX_DMA0_MODE_REG));
1324         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1325                     readl(plx_iobase + PLX_DMA1_MODE_REG));
1326         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1327                     readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1328         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1329                     readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1330         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1331                     readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1332         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1333                     readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1334         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1335                     readb(plx_iobase + PLX_DMA0_CS_REG));
1336         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1337                     readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1338         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1339
1340 #ifdef __BIG_ENDIAN
1341         bits = BIGEND_DMA0 | BIGEND_DMA1;
1342 #else
1343         bits = 0;
1344 #endif
1345         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1346
1347         disable_plx_interrupts(dev);
1348
1349         abort_dma(dev, 0);
1350         abort_dma(dev, 1);
1351
1352         /*  configure dma0 mode */
1353         bits = 0;
1354         /*  enable ready input, not sure if this is necessary */
1355         bits |= PLX_DMA_EN_READYIN_BIT;
1356         /*  enable bterm, not sure if this is necessary */
1357         bits |= PLX_EN_BTERM_BIT;
1358         /*  enable dma chaining */
1359         bits |= PLX_EN_CHAIN_BIT;
1360         /*  enable interrupt on dma done
1361          *  (probably don't need this, since chain never finishes) */
1362         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1363         /*  don't increment local address during transfers
1364          *  (we are transferring from a fixed fifo register) */
1365         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1366         /*  route dma interrupt to pci bus */
1367         bits |= PLX_DMA_INTR_PCI_BIT;
1368         /*  enable demand mode */
1369         bits |= PLX_DEMAND_MODE_BIT;
1370         /*  enable local burst mode */
1371         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1372         /*  4020 uses 32 bit dma */
1373         if (thisboard->layout == LAYOUT_4020)
1374                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1375         else            /*  localspace0 bus is 16 bits wide */
1376                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1377         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1378         if (ao_cmd_is_supported(thisboard))
1379                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1380
1381         /*  enable interrupts on plx 9080 */
1382         devpriv->plx_intcsr_bits |=
1383             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1384             ICS_DMA0_E | ICS_DMA1_E;
1385         writel(devpriv->plx_intcsr_bits,
1386                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1387 }
1388
1389 static void disable_ai_pacing(struct comedi_device *dev)
1390 {
1391         struct pcidas64_private *devpriv = dev->private;
1392         unsigned long flags;
1393
1394         disable_ai_interrupts(dev);
1395
1396         spin_lock_irqsave(&dev->spinlock, flags);
1397         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1398         writew(devpriv->adc_control1_bits,
1399                devpriv->main_iobase + ADC_CONTROL1_REG);
1400         spin_unlock_irqrestore(&dev->spinlock, flags);
1401
1402         /* disable pacing, triggering, etc */
1403         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1404                devpriv->main_iobase + ADC_CONTROL0_REG);
1405 }
1406
1407 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1408                                       unsigned int num_entries)
1409 {
1410         const struct pcidas64_board *thisboard = comedi_board(dev);
1411         struct pcidas64_private *devpriv = dev->private;
1412         static const int increment_size = 0x100;
1413         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1414         unsigned int num_increments;
1415         uint16_t bits;
1416
1417         if (num_entries < increment_size)
1418                 num_entries = increment_size;
1419         if (num_entries > fifo->max_segment_length)
1420                 num_entries = fifo->max_segment_length;
1421
1422         /*  1 == 256 entries, 2 == 512 entries, etc */
1423         num_increments = (num_entries + increment_size / 2) / increment_size;
1424
1425         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1426         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1427         devpriv->fifo_size_bits |= bits;
1428         writew(devpriv->fifo_size_bits,
1429                devpriv->main_iobase + FIFO_SIZE_REG);
1430
1431         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1432
1433         DEBUG_PRINT("set hardware fifo segment length to %i\n",
1434                     devpriv->ai_fifo_segment_length);
1435
1436         return devpriv->ai_fifo_segment_length;
1437 }
1438
1439 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1440 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1441 {
1442         const struct pcidas64_board *thisboard = comedi_board(dev);
1443         unsigned int num_fifo_entries;
1444         int retval;
1445         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1446
1447         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1448
1449         retval = set_ai_fifo_segment_length(dev,
1450                                             num_fifo_entries /
1451                                             fifo->num_segments);
1452         if (retval < 0)
1453                 return retval;
1454
1455         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1456
1457         DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
1458
1459         return num_samples;
1460 }
1461
1462 /* query length of fifo */
1463 static unsigned int ai_fifo_size(struct comedi_device *dev)
1464 {
1465         const struct pcidas64_board *thisboard = comedi_board(dev);
1466         struct pcidas64_private *devpriv = dev->private;
1467
1468         return devpriv->ai_fifo_segment_length *
1469                thisboard->ai_fifo->num_segments *
1470                thisboard->ai_fifo->sample_packing_ratio;
1471 }
1472
1473 static void init_stc_registers(struct comedi_device *dev)
1474 {
1475         const struct pcidas64_board *thisboard = comedi_board(dev);
1476         struct pcidas64_private *devpriv = dev->private;
1477         uint16_t bits;
1478         unsigned long flags;
1479
1480         spin_lock_irqsave(&dev->spinlock, flags);
1481
1482         /*  bit should be set for 6025,
1483          *  although docs say boards with <= 16 chans should be cleared XXX */
1484         if (1)
1485                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1486         writew(devpriv->adc_control1_bits,
1487                devpriv->main_iobase + ADC_CONTROL1_REG);
1488
1489         /*  6402/16 manual says this register must be initialized to 0xff? */
1490         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1491
1492         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1493         if (thisboard->layout == LAYOUT_4020)
1494                 bits |= INTERNAL_CLOCK_4020_BITS;
1495         devpriv->hw_config_bits |= bits;
1496         writew(devpriv->hw_config_bits,
1497                devpriv->main_iobase + HW_CONFIG_REG);
1498
1499         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1500         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1501
1502         spin_unlock_irqrestore(&dev->spinlock, flags);
1503
1504         /*  set fifos to maximum size */
1505         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1506         set_ai_fifo_segment_length(dev,
1507                                    thisboard->ai_fifo->max_segment_length);
1508
1509         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1510         devpriv->intr_enable_bits =
1511                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1512                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1513         writew(devpriv->intr_enable_bits,
1514                devpriv->main_iobase + INTR_ENABLE_REG);
1515
1516         disable_ai_pacing(dev);
1517 };
1518
1519 static int alloc_and_init_dma_members(struct comedi_device *dev)
1520 {
1521         const struct pcidas64_board *thisboard = comedi_board(dev);
1522         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1523         struct pcidas64_private *devpriv = dev->private;
1524         int i;
1525
1526         /*  alocate pci dma buffers */
1527         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1528                 devpriv->ai_buffer[i] =
1529                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1530                                              &devpriv->ai_buffer_bus_addr[i]);
1531                 if (devpriv->ai_buffer[i] == NULL)
1532                         return -ENOMEM;
1533
1534         }
1535         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1536                 if (ao_cmd_is_supported(thisboard)) {
1537                         devpriv->ao_buffer[i] =
1538                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1539                                                      &devpriv->
1540                                                       ao_buffer_bus_addr[i]);
1541                         if (devpriv->ao_buffer[i] == NULL)
1542                                 return -ENOMEM;
1543
1544                 }
1545         }
1546         /*  allocate dma descriptors */
1547         devpriv->ai_dma_desc =
1548                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1549                                      ai_dma_ring_count(thisboard),
1550                                      &devpriv->ai_dma_desc_bus_addr);
1551         if (devpriv->ai_dma_desc == NULL)
1552                 return -ENOMEM;
1553
1554         DEBUG_PRINT("ai dma descriptors start at bus addr 0x%llx\n",
1555                     (unsigned long long)devpriv->ai_dma_desc_bus_addr);
1556         if (ao_cmd_is_supported(thisboard)) {
1557                 devpriv->ao_dma_desc =
1558                         pci_alloc_consistent(pcidev,
1559                                              sizeof(struct plx_dma_desc) *
1560                                              AO_DMA_RING_COUNT,
1561                                              &devpriv->ao_dma_desc_bus_addr);
1562                 if (devpriv->ao_dma_desc == NULL)
1563                         return -ENOMEM;
1564
1565                 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%llx\n",
1566                             (unsigned long long)devpriv->ao_dma_desc_bus_addr);
1567         }
1568         /*  initialize dma descriptors */
1569         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1570                 devpriv->ai_dma_desc[i].pci_start_addr =
1571                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1572                 if (thisboard->layout == LAYOUT_4020)
1573                         devpriv->ai_dma_desc[i].local_start_addr =
1574                                 cpu_to_le32(devpriv->local1_iobase +
1575                                             ADC_FIFO_REG);
1576                 else
1577                         devpriv->ai_dma_desc[i].local_start_addr =
1578                                 cpu_to_le32(devpriv->local0_iobase +
1579                                             ADC_FIFO_REG);
1580                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1581                 devpriv->ai_dma_desc[i].next =
1582                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1583                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1584                                      sizeof(devpriv->ai_dma_desc[0])) |
1585                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1586                                     PLX_XFER_LOCAL_TO_PCI);
1587         }
1588         if (ao_cmd_is_supported(thisboard)) {
1589                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1590                         devpriv->ao_dma_desc[i].pci_start_addr =
1591                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1592                         devpriv->ao_dma_desc[i].local_start_addr =
1593                                 cpu_to_le32(devpriv->local0_iobase +
1594                                             DAC_FIFO_REG);
1595                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1596                         devpriv->ao_dma_desc[i].next =
1597                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1598                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1599                                              sizeof(devpriv->ao_dma_desc[0])) |
1600                                             PLX_DESC_IN_PCI_BIT |
1601                                             PLX_INTR_TERM_COUNT);
1602                 }
1603         }
1604         return 0;
1605 }
1606
1607 static inline void warn_external_queue(struct comedi_device *dev)
1608 {
1609         comedi_error(dev,
1610                      "AO command and AI external channel queue cannot be used simultaneously.");
1611         comedi_error(dev,
1612                      "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1613 }
1614
1615 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1616 static const int i2c_high_udelay = 1000;
1617 static const int i2c_low_udelay = 10;
1618
1619 /* set i2c data line high or low */
1620 static void i2c_set_sda(struct comedi_device *dev, int state)
1621 {
1622         struct pcidas64_private *devpriv = dev->private;
1623         static const int data_bit = CTL_EE_W;
1624         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1625                                          PLX_CONTROL_REG;
1626
1627         if (state) {
1628                 /*  set data line high */
1629                 devpriv->plx_control_bits &= ~data_bit;
1630                 writel(devpriv->plx_control_bits, plx_control_addr);
1631                 udelay(i2c_high_udelay);
1632         } else {                /*  set data line low */
1633
1634                 devpriv->plx_control_bits |= data_bit;
1635                 writel(devpriv->plx_control_bits, plx_control_addr);
1636                 udelay(i2c_low_udelay);
1637         }
1638 }
1639
1640 /* set i2c clock line high or low */
1641 static void i2c_set_scl(struct comedi_device *dev, int state)
1642 {
1643         struct pcidas64_private *devpriv = dev->private;
1644         static const int clock_bit = CTL_USERO;
1645         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1646                                          PLX_CONTROL_REG;
1647
1648         if (state) {
1649                 /*  set clock line high */
1650                 devpriv->plx_control_bits &= ~clock_bit;
1651                 writel(devpriv->plx_control_bits, plx_control_addr);
1652                 udelay(i2c_high_udelay);
1653         } else {                /*  set clock line low */
1654
1655                 devpriv->plx_control_bits |= clock_bit;
1656                 writel(devpriv->plx_control_bits, plx_control_addr);
1657                 udelay(i2c_low_udelay);
1658         }
1659 }
1660
1661 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1662 {
1663         uint8_t bit;
1664         unsigned int num_bits = 8;
1665
1666         DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
1667
1668         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1669                 i2c_set_scl(dev, 0);
1670                 if ((byte & bit))
1671                         i2c_set_sda(dev, 1);
1672                 else
1673                         i2c_set_sda(dev, 0);
1674                 i2c_set_scl(dev, 1);
1675         }
1676 }
1677
1678 /* we can't really read the lines, so fake it */
1679 static int i2c_read_ack(struct comedi_device *dev)
1680 {
1681         i2c_set_scl(dev, 0);
1682         i2c_set_sda(dev, 1);
1683         i2c_set_scl(dev, 1);
1684
1685         return 0;               /*  return fake acknowledge bit */
1686 }
1687
1688 /* send start bit */
1689 static void i2c_start(struct comedi_device *dev)
1690 {
1691         i2c_set_scl(dev, 1);
1692         i2c_set_sda(dev, 1);
1693         i2c_set_sda(dev, 0);
1694 }
1695
1696 /* send stop bit */
1697 static void i2c_stop(struct comedi_device *dev)
1698 {
1699         i2c_set_scl(dev, 0);
1700         i2c_set_sda(dev, 0);
1701         i2c_set_scl(dev, 1);
1702         i2c_set_sda(dev, 1);
1703 }
1704
1705 static void i2c_write(struct comedi_device *dev, unsigned int address,
1706                       const uint8_t *data, unsigned int length)
1707 {
1708         struct pcidas64_private *devpriv = dev->private;
1709         unsigned int i;
1710         uint8_t bitstream;
1711         static const int read_bit = 0x1;
1712
1713         /* XXX need mutex to prevent simultaneous attempts to access
1714          * eeprom and i2c bus */
1715
1716         /*  make sure we dont send anything to eeprom */
1717         devpriv->plx_control_bits &= ~CTL_EE_CS;
1718
1719         i2c_stop(dev);
1720         i2c_start(dev);
1721
1722         /*  send address and write bit */
1723         bitstream = (address << 1) & ~read_bit;
1724         i2c_write_byte(dev, bitstream);
1725
1726         /*  get acknowledge */
1727         if (i2c_read_ack(dev) != 0) {
1728                 comedi_error(dev, "i2c write failed: no acknowledge");
1729                 i2c_stop(dev);
1730                 return;
1731         }
1732         /*  write data bytes */
1733         for (i = 0; i < length; i++) {
1734                 i2c_write_byte(dev, data[i]);
1735                 if (i2c_read_ack(dev) != 0) {
1736                         comedi_error(dev, "i2c write failed: no acknowledge");
1737                         i2c_stop(dev);
1738                         return;
1739                 }
1740         }
1741         i2c_stop(dev);
1742 }
1743
1744 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1745                     struct comedi_insn *insn, unsigned int *data)
1746 {
1747         const struct pcidas64_board *thisboard = comedi_board(dev);
1748         struct pcidas64_private *devpriv = dev->private;
1749         unsigned int bits = 0, n, i;
1750         unsigned int channel, range, aref;
1751         unsigned long flags;
1752         static const int timeout = 100;
1753
1754         DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1755         channel = CR_CHAN(insn->chanspec);
1756         range = CR_RANGE(insn->chanspec);
1757         aref = CR_AREF(insn->chanspec);
1758
1759         /*  disable card's analog input interrupt sources and pacing */
1760         /*  4020 generates dac done interrupts even though they are disabled */
1761         disable_ai_pacing(dev);
1762
1763         spin_lock_irqsave(&dev->spinlock, flags);
1764         if (insn->chanspec & CR_ALT_FILTER)
1765                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1766         else
1767                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1768         writew(devpriv->adc_control1_bits,
1769                devpriv->main_iobase + ADC_CONTROL1_REG);
1770         spin_unlock_irqrestore(&dev->spinlock, flags);
1771
1772         if (thisboard->layout != LAYOUT_4020) {
1773                 /*  use internal queue */
1774                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1775                 writew(devpriv->hw_config_bits,
1776                        devpriv->main_iobase + HW_CONFIG_REG);
1777
1778                 /*  ALT_SOURCE is internal calibration reference */
1779                 if (insn->chanspec & CR_ALT_SOURCE) {
1780                         unsigned int cal_en_bit;
1781
1782                         DEBUG_PRINT("reading calibration source\n");
1783                         if (thisboard->layout == LAYOUT_60XX)
1784                                 cal_en_bit = CAL_EN_60XX_BIT;
1785                         else
1786                                 cal_en_bit = CAL_EN_64XX_BIT;
1787                         /*  select internal reference source to connect
1788                          *  to channel 0 */
1789                         writew(cal_en_bit |
1790                                adc_src_bits(devpriv->calibration_source),
1791                                devpriv->main_iobase + CALIBRATION_REG);
1792                 } else {
1793                         /*  make sure internal calibration source
1794                          *  is turned off */
1795                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1796                 }
1797                 /*  load internal queue */
1798                 bits = 0;
1799                 /*  set gain */
1800                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1801                 /*  set single-ended / differential */
1802                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1803                 if (aref == AREF_COMMON)
1804                         bits |= ADC_COMMON_BIT;
1805                 bits |= adc_chan_bits(channel);
1806                 /*  set stop channel */
1807                 writew(adc_chan_bits(channel),
1808                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1809                 /*  set start channel, and rest of settings */
1810                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1811         } else {
1812                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1813
1814                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1815                 if (insn->chanspec & CR_ALT_SOURCE) {
1816                         DEBUG_PRINT("reading calibration source\n");
1817                         devpriv->i2c_cal_range_bits |=
1818                                 adc_src_4020_bits(devpriv->calibration_source);
1819                 } else {        /* select BNC inputs */
1820                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1821                 }
1822                 /*  select range */
1823                 if (range == 0)
1824                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1825                 else
1826                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1827                 /*  update calibration/range i2c register only if necessary,
1828                  *  as it is very slow */
1829                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1830                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1831                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1832                                   sizeof(i2c_data));
1833                 }
1834
1835                 /* 4020 manual asks that sample interval register to be set
1836                  * before writing to convert register.
1837                  * Using somewhat arbitrary setting of 4 master clock ticks
1838                  * = 0.1 usec */
1839                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1840                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1841         }
1842
1843         for (n = 0; n < insn->n; n++) {
1844
1845                 /*  clear adc buffer (inside loop for 4020 sake) */
1846                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1847
1848                 /* trigger conversion, bits sent only matter for 4020 */
1849                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1850                        devpriv->main_iobase + ADC_CONVERT_REG);
1851
1852                 /*  wait for data */
1853                 for (i = 0; i < timeout; i++) {
1854                         bits = readw(devpriv->main_iobase + HW_STATUS_REG);
1855                         DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1856                         if (thisboard->layout == LAYOUT_4020) {
1857                                 if (readw(devpriv->main_iobase +
1858                                           ADC_WRITE_PNTR_REG))
1859                                         break;
1860                         } else {
1861                                 if (pipe_full_bits(bits))
1862                                         break;
1863                         }
1864                         udelay(1);
1865                 }
1866                 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1867                 if (i == timeout) {
1868                         comedi_error(dev, " analog input read insn timed out");
1869                         dev_info(dev->class_dev, "status 0x%x\n", bits);
1870                         return -ETIME;
1871                 }
1872                 if (thisboard->layout == LAYOUT_4020)
1873                         data[n] = readl(devpriv->dio_counter_iobase +
1874                                         ADC_FIFO_REG) & 0xffff;
1875                 else
1876                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1877         }
1878
1879         return n;
1880 }
1881
1882 static int ai_config_calibration_source(struct comedi_device *dev,
1883                                         unsigned int *data)
1884 {
1885         const struct pcidas64_board *thisboard = comedi_board(dev);
1886         struct pcidas64_private *devpriv = dev->private;
1887         unsigned int source = data[1];
1888         int num_calibration_sources;
1889
1890         if (thisboard->layout == LAYOUT_60XX)
1891                 num_calibration_sources = 16;
1892         else
1893                 num_calibration_sources = 8;
1894         if (source >= num_calibration_sources) {
1895                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1896                         source);
1897                 return -EINVAL;
1898         }
1899
1900         DEBUG_PRINT("setting calibration source to %i\n", source);
1901         devpriv->calibration_source = source;
1902
1903         return 2;
1904 }
1905
1906 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1907 {
1908         const struct pcidas64_board *thisboard = comedi_board(dev);
1909         int fifo_size;
1910         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1911         unsigned int block_size, requested_block_size;
1912         int retval;
1913
1914         requested_block_size = data[1];
1915
1916         if (requested_block_size) {
1917                 fifo_size = requested_block_size * fifo->num_segments /
1918                             bytes_in_sample;
1919
1920                 retval = set_ai_fifo_size(dev, fifo_size);
1921                 if (retval < 0)
1922                         return retval;
1923
1924         }
1925
1926         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1927
1928         data[1] = block_size;
1929
1930         return 2;
1931 }
1932
1933 static int ai_config_master_clock_4020(struct comedi_device *dev,
1934                                        unsigned int *data)
1935 {
1936         struct pcidas64_private *devpriv = dev->private;
1937         unsigned int divisor = data[4];
1938         int retval = 0;
1939
1940         if (divisor < 2) {
1941                 divisor = 2;
1942                 retval = -EAGAIN;
1943         }
1944
1945         switch (data[1]) {
1946         case COMEDI_EV_SCAN_BEGIN:
1947                 devpriv->ext_clock.divisor = divisor;
1948                 devpriv->ext_clock.chanspec = data[2];
1949                 break;
1950         default:
1951                 return -EINVAL;
1952                 break;
1953         }
1954
1955         data[4] = divisor;
1956
1957         return retval ? retval : 5;
1958 }
1959
1960 /* XXX could add support for 60xx series */
1961 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1962 {
1963         const struct pcidas64_board *thisboard = comedi_board(dev);
1964
1965         switch (thisboard->layout) {
1966         case LAYOUT_4020:
1967                 return ai_config_master_clock_4020(dev, data);
1968                 break;
1969         default:
1970                 return -EINVAL;
1971                 break;
1972         }
1973
1974         return -EINVAL;
1975 }
1976
1977 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1978                           struct comedi_insn *insn, unsigned int *data)
1979 {
1980         int id = data[0];
1981
1982         switch (id) {
1983         case INSN_CONFIG_ALT_SOURCE:
1984                 return ai_config_calibration_source(dev, data);
1985                 break;
1986         case INSN_CONFIG_BLOCK_SIZE:
1987                 return ai_config_block_size(dev, data);
1988                 break;
1989         case INSN_CONFIG_TIMER_1:
1990                 return ai_config_master_clock(dev, data);
1991                 break;
1992         default:
1993                 return -EINVAL;
1994                 break;
1995         }
1996         return -EINVAL;
1997 }
1998
1999 /* Gets nearest achievable timing given master clock speed, does not
2000  * take into account possible minimum/maximum divisor values.  Used
2001  * by other timing checking functions. */
2002 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
2003 {
2004         unsigned int divisor;
2005
2006         switch (flags & TRIG_ROUND_MASK) {
2007         case TRIG_ROUND_UP:
2008                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
2009                 break;
2010         case TRIG_ROUND_DOWN:
2011                 divisor = ns / TIMER_BASE;
2012                 break;
2013         case TRIG_ROUND_NEAREST:
2014         default:
2015                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
2016                 break;
2017         }
2018         return divisor;
2019 }
2020
2021 /* utility function that rounds desired timing to an achievable time, and
2022  * sets cmd members appropriately.
2023  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
2024  */
2025 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2026 {
2027         const struct pcidas64_board *thisboard = comedi_board(dev);
2028         unsigned int convert_divisor = 0, scan_divisor;
2029         static const int min_convert_divisor = 3;
2030         static const int max_convert_divisor =
2031                 max_counter_value + min_convert_divisor;
2032         static const int min_scan_divisor_4020 = 2;
2033         unsigned long long max_scan_divisor, min_scan_divisor;
2034
2035         if (cmd->convert_src == TRIG_TIMER) {
2036                 if (thisboard->layout == LAYOUT_4020) {
2037                         cmd->convert_arg = 0;
2038                 } else {
2039                         convert_divisor = get_divisor(cmd->convert_arg,
2040                                                       cmd->flags);
2041                         if (convert_divisor > max_convert_divisor)
2042                                 convert_divisor = max_convert_divisor;
2043                         if (convert_divisor < min_convert_divisor)
2044                                 convert_divisor = min_convert_divisor;
2045                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2046                 }
2047         } else if (cmd->convert_src == TRIG_NOW) {
2048                 cmd->convert_arg = 0;
2049         }
2050
2051         if (cmd->scan_begin_src == TRIG_TIMER) {
2052                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2053                 if (cmd->convert_src == TRIG_TIMER) {
2054                         /*  XXX check for integer overflows */
2055                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2056                         max_scan_divisor =
2057                                 (convert_divisor * cmd->chanlist_len - 1) +
2058                                 max_counter_value;
2059                 } else {
2060                         min_scan_divisor = min_scan_divisor_4020;
2061                         max_scan_divisor = max_counter_value + min_scan_divisor;
2062                 }
2063                 if (scan_divisor > max_scan_divisor)
2064                         scan_divisor = max_scan_divisor;
2065                 if (scan_divisor < min_scan_divisor)
2066                         scan_divisor = min_scan_divisor;
2067                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2068         }
2069
2070         return;
2071 }
2072
2073 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2074                       struct comedi_cmd *cmd)
2075 {
2076         const struct pcidas64_board *thisboard = comedi_board(dev);
2077         int err = 0;
2078         unsigned int tmp_arg, tmp_arg2;
2079         int i;
2080         int aref;
2081         unsigned int triggers;
2082
2083         /* Step 1 : check if triggers are trivially valid */
2084
2085         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2086
2087         triggers = TRIG_TIMER;
2088         if (thisboard->layout == LAYOUT_4020)
2089                 triggers |= TRIG_OTHER;
2090         else
2091                 triggers |= TRIG_FOLLOW;
2092         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2093
2094         triggers = TRIG_TIMER;
2095         if (thisboard->layout == LAYOUT_4020)
2096                 triggers |= TRIG_NOW;
2097         else
2098                 triggers |= TRIG_EXT;
2099         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2100         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2101         err |= cfc_check_trigger_src(&cmd->stop_src,
2102                                      TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2103
2104         if (err)
2105                 return 1;
2106
2107         /* Step 2a : make sure trigger sources are unique */
2108
2109         err |= cfc_check_trigger_is_unique(cmd->start_src);
2110         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2111         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2112         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2113
2114         /* Step 2b : and mutually compatible */
2115
2116         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2117                 err |= -EINVAL;
2118         if (cmd->stop_src != TRIG_COUNT &&
2119             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2120                 err |= -EINVAL;
2121
2122         if (err)
2123                 return 2;
2124
2125         /* Step 3: check if arguments are trivially valid */
2126
2127         if (cmd->convert_src == TRIG_TIMER) {
2128                 if (thisboard->layout == LAYOUT_4020) {
2129                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2130                 } else {
2131                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2132                                                          thisboard->ai_speed);
2133                         /* if scans are timed faster than conversion rate allows */
2134                         if (cmd->scan_begin_src == TRIG_TIMER)
2135                                 err |= cfc_check_trigger_arg_min(
2136                                                 &cmd->scan_begin_arg,
2137                                                 cmd->convert_arg *
2138                                                 cmd->chanlist_len);
2139                 }
2140         }
2141
2142         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2143         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2144
2145         switch (cmd->stop_src) {
2146         case TRIG_EXT:
2147                 break;
2148         case TRIG_COUNT:
2149                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2150                 break;
2151         case TRIG_NONE:
2152                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2153                 break;
2154         default:
2155                 break;
2156         }
2157
2158         if (err)
2159                 return 3;
2160
2161         /* step 4: fix up any arguments */
2162
2163         if (cmd->convert_src == TRIG_TIMER) {
2164                 tmp_arg = cmd->convert_arg;
2165                 tmp_arg2 = cmd->scan_begin_arg;
2166                 check_adc_timing(dev, cmd);
2167                 if (tmp_arg != cmd->convert_arg)
2168                         err++;
2169                 if (tmp_arg2 != cmd->scan_begin_arg)
2170                         err++;
2171         }
2172
2173         if (err)
2174                 return 4;
2175
2176         /*  make sure user is doesn't change analog reference mid chanlist */
2177         if (cmd->chanlist) {
2178                 aref = CR_AREF(cmd->chanlist[0]);
2179                 for (i = 1; i < cmd->chanlist_len; i++) {
2180                         if (aref != CR_AREF(cmd->chanlist[i])) {
2181                                 comedi_error(dev,
2182                                              "all elements in chanlist must use the same analog reference");
2183                                 err++;
2184                                 break;
2185                         }
2186                 }
2187                 /*  check 4020 chanlist */
2188                 if (thisboard->layout == LAYOUT_4020) {
2189                         unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2190                         for (i = 1; i < cmd->chanlist_len; i++) {
2191                                 if (CR_CHAN(cmd->chanlist[i]) !=
2192                                     first_channel + i) {
2193                                         comedi_error(dev,
2194                                                      "chanlist must use consecutive channels");
2195                                         err++;
2196                                         break;
2197                                 }
2198                         }
2199                         if (cmd->chanlist_len == 3) {
2200                                 comedi_error(dev,
2201                                              "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2202                                 err++;
2203                         }
2204                 }
2205         }
2206
2207         if (err)
2208                 return 5;
2209
2210         return 0;
2211 }
2212
2213 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2214 {
2215 /* disable for now until I work out a race */
2216         return 0;
2217
2218         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2219                 return 1;
2220         else
2221                 return 0;
2222 }
2223
2224 static void setup_sample_counters(struct comedi_device *dev,
2225                                   struct comedi_cmd *cmd)
2226 {
2227         struct pcidas64_private *devpriv = dev->private;
2228
2229         if (cmd->stop_src == TRIG_COUNT) {
2230                 /*  set software count */
2231                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2232         }
2233         /*  load hardware conversion counter */
2234         if (use_hw_sample_counter(cmd)) {
2235                 writew(cmd->stop_arg & 0xffff,
2236                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2237                 writew((cmd->stop_arg >> 16) & 0xff,
2238                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2239         } else {
2240                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2241         }
2242 }
2243
2244 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2245 {
2246         const struct pcidas64_board *thisboard = comedi_board(dev);
2247         struct pcidas64_private *devpriv = dev->private;
2248         unsigned int num_samples;
2249
2250         num_samples = devpriv->ai_fifo_segment_length *
2251                       thisboard->ai_fifo->sample_packing_ratio;
2252         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2253                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2254
2255         return num_samples;
2256 }
2257
2258 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2259                                         const struct comedi_cmd *cmd)
2260 {
2261         /*  supposed to load counter with desired divisor minus 3 */
2262         return cmd->convert_arg / TIMER_BASE - 3;
2263 }
2264
2265 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2266                                      struct comedi_cmd *cmd)
2267 {
2268         uint32_t count;
2269
2270         /*  figure out how long we need to delay at end of scan */
2271         switch (cmd->scan_begin_src) {
2272         case TRIG_TIMER:
2273                 count = (cmd->scan_begin_arg -
2274                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2275                         TIMER_BASE;
2276                 break;
2277         case TRIG_FOLLOW:
2278                 count = cmd->convert_arg / TIMER_BASE;
2279                 break;
2280         default:
2281                 return 0;
2282                 break;
2283         }
2284         return count - 3;
2285 }
2286
2287 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2288                                         struct comedi_cmd *cmd)
2289 {
2290         struct pcidas64_private *devpriv = dev->private;
2291         unsigned int divisor;
2292
2293         switch (cmd->scan_begin_src) {
2294         case TRIG_TIMER:
2295                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2296                 break;
2297         case TRIG_OTHER:
2298                 divisor = devpriv->ext_clock.divisor;
2299                 break;
2300         default:                /*  should never happen */
2301                 comedi_error(dev, "bug! failed to set ai pacing!");
2302                 divisor = 1000;
2303                 break;
2304         }
2305
2306         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2307         return divisor - 2;
2308 }
2309
2310 static void select_master_clock_4020(struct comedi_device *dev,
2311                                      const struct comedi_cmd *cmd)
2312 {
2313         struct pcidas64_private *devpriv = dev->private;
2314
2315         /*  select internal/external master clock */
2316         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2317         if (cmd->scan_begin_src == TRIG_OTHER) {
2318                 int chanspec = devpriv->ext_clock.chanspec;
2319
2320                 if (CR_CHAN(chanspec))
2321                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2322                 else
2323                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2324         } else {
2325                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2326         }
2327         writew(devpriv->hw_config_bits,
2328                devpriv->main_iobase + HW_CONFIG_REG);
2329 }
2330
2331 static void select_master_clock(struct comedi_device *dev,
2332                                 const struct comedi_cmd *cmd)
2333 {
2334         const struct pcidas64_board *thisboard = comedi_board(dev);
2335
2336         switch (thisboard->layout) {
2337         case LAYOUT_4020:
2338                 select_master_clock_4020(dev, cmd);
2339                 break;
2340         default:
2341                 break;
2342         }
2343 }
2344
2345 static inline void dma_start_sync(struct comedi_device *dev,
2346                                   unsigned int channel)
2347 {
2348         struct pcidas64_private *devpriv = dev->private;
2349         unsigned long flags;
2350
2351         /*  spinlock for plx dma control/status reg */
2352         spin_lock_irqsave(&dev->spinlock, flags);
2353         if (channel)
2354                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2355                        PLX_CLEAR_DMA_INTR_BIT,
2356                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2357         else
2358                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2359                        PLX_CLEAR_DMA_INTR_BIT,
2360                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2361         spin_unlock_irqrestore(&dev->spinlock, flags);
2362 }
2363
2364 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2365 {
2366         const struct pcidas64_board *thisboard = comedi_board(dev);
2367         struct pcidas64_private *devpriv = dev->private;
2368         uint32_t convert_counter = 0, scan_counter = 0;
2369
2370         check_adc_timing(dev, cmd);
2371
2372         select_master_clock(dev, cmd);
2373
2374         if (thisboard->layout == LAYOUT_4020) {
2375                 convert_counter = ai_convert_counter_4020(dev, cmd);
2376         } else {
2377                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2378                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2379         }
2380
2381         /*  load lower 16 bits of convert interval */
2382         writew(convert_counter & 0xffff,
2383                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2384         DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2385         /*  load upper 8 bits of convert interval */
2386         writew((convert_counter >> 16) & 0xff,
2387                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2388         /*  load lower 16 bits of scan delay */
2389         writew(scan_counter & 0xffff,
2390                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2391         /*  load upper 8 bits of scan delay */
2392         writew((scan_counter >> 16) & 0xff,
2393                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2394         DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2395 }
2396
2397 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2398 {
2399         int i;
2400
2401         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2402                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2403                     CR_CHAN(cmd->chanlist[i]) + 1)
2404                         return 0;
2405                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2406                     CR_RANGE(cmd->chanlist[i]))
2407                         return 0;
2408                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2409                         return 0;
2410         }
2411         return 1;
2412 }
2413
2414 static int setup_channel_queue(struct comedi_device *dev,
2415                                const struct comedi_cmd *cmd)
2416 {
2417         const struct pcidas64_board *thisboard = comedi_board(dev);
2418         struct pcidas64_private *devpriv = dev->private;
2419         unsigned short bits;
2420         int i;
2421
2422         if (thisboard->layout != LAYOUT_4020) {
2423                 if (use_internal_queue_6xxx(cmd)) {
2424                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2425                         writew(devpriv->hw_config_bits,
2426                                devpriv->main_iobase + HW_CONFIG_REG);
2427                         bits = 0;
2428                         /*  set channel */
2429                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2430                         /*  set gain */
2431                         bits |= ai_range_bits_6xxx(dev,
2432                                                    CR_RANGE(cmd->chanlist[0]));
2433                         /*  set single-ended / differential */
2434                         bits |= se_diff_bit_6xxx(dev,
2435                                                  CR_AREF(cmd->chanlist[0]) ==
2436                                                  AREF_DIFF);
2437                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2438                                 bits |= ADC_COMMON_BIT;
2439                         /*  set stop channel */
2440                         writew(adc_chan_bits
2441                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2442                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2443                         /*  set start channel, and rest of settings */
2444                         writew(bits,
2445                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2446                 } else {
2447                         /*  use external queue */
2448                         if (dev->write_subdev && dev->write_subdev->busy) {
2449                                 warn_external_queue(dev);
2450                                 return -EBUSY;
2451                         }
2452                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2453                         writew(devpriv->hw_config_bits,
2454                                devpriv->main_iobase + HW_CONFIG_REG);
2455                         /*  clear DAC buffer to prevent weird interactions */
2456                         writew(0,
2457                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2458                         /*  clear queue pointer */
2459                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2460                         /*  load external queue */
2461                         for (i = 0; i < cmd->chanlist_len; i++) {
2462                                 bits = 0;
2463                                 /*  set channel */
2464                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2465                                                               chanlist[i]));
2466                                 /*  set gain */
2467                                 bits |= ai_range_bits_6xxx(dev,
2468                                                            CR_RANGE(cmd->
2469                                                                     chanlist
2470                                                                     [i]));
2471                                 /*  set single-ended / differential */
2472                                 bits |= se_diff_bit_6xxx(dev,
2473                                                          CR_AREF(cmd->
2474                                                                  chanlist[i]) ==
2475                                                          AREF_DIFF);
2476                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2477                                         bits |= ADC_COMMON_BIT;
2478                                 /*  mark end of queue */
2479                                 if (i == cmd->chanlist_len - 1)
2480                                         bits |= QUEUE_EOSCAN_BIT |
2481                                                 QUEUE_EOSEQ_BIT;
2482                                 writew(bits,
2483                                        devpriv->main_iobase +
2484                                        ADC_QUEUE_FIFO_REG);
2485                                 DEBUG_PRINT(
2486                                             "wrote 0x%x to external channel queue\n",
2487                                             bits);
2488                         }
2489                         /* doing a queue clear is not specified in board docs,
2490                          * but required for reliable operation */
2491                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2492                         /*  prime queue holding register */
2493                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2494                 }
2495         } else {
2496                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2497
2498                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2499                 /* select BNC inputs */
2500                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2501                 /*  select ranges */
2502                 for (i = 0; i < cmd->chanlist_len; i++) {
2503                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2504                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2505
2506                         if (range == 0)
2507                                 devpriv->i2c_cal_range_bits |=
2508                                         attenuate_bit(channel);
2509                         else
2510                                 devpriv->i2c_cal_range_bits &=
2511                                         ~attenuate_bit(channel);
2512                 }
2513                 /*  update calibration/range i2c register only if necessary,
2514                  *  as it is very slow */
2515                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2516                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2517                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2518                                   sizeof(i2c_data));
2519                 }
2520         }
2521         return 0;
2522 }
2523
2524 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2525                                              unsigned int dma_channel,
2526                                              unsigned int descriptor_bits)
2527 {
2528         struct pcidas64_private *devpriv = dev->private;
2529
2530         /* The transfer size, pci address, and local address registers
2531          * are supposedly unused during chained dma,
2532          * but I have found that left over values from last operation
2533          * occasionally cause problems with transfer of first dma
2534          * block.  Initializing them to zero seems to fix the problem. */
2535         if (dma_channel) {
2536                 writel(0,
2537                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2538                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2539                 writel(0,
2540                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2541                 writel(descriptor_bits,
2542                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2543         } else {
2544                 writel(0,
2545                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2546                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2547                 writel(0,
2548                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2549                 writel(descriptor_bits,
2550                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2551         }
2552 }
2553
2554 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2555 {
2556         const struct pcidas64_board *thisboard = comedi_board(dev);
2557         struct pcidas64_private *devpriv = dev->private;
2558         struct comedi_async *async = s->async;
2559         struct comedi_cmd *cmd = &async->cmd;
2560         uint32_t bits;
2561         unsigned int i;
2562         unsigned long flags;
2563         int retval;
2564
2565         disable_ai_pacing(dev);
2566         abort_dma(dev, 1);
2567
2568         retval = setup_channel_queue(dev, cmd);
2569         if (retval < 0)
2570                 return retval;
2571
2572         /*  make sure internal calibration source is turned off */
2573         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2574
2575         set_ai_pacing(dev, cmd);
2576
2577         setup_sample_counters(dev, cmd);
2578
2579         enable_ai_interrupts(dev, cmd);
2580
2581         spin_lock_irqsave(&dev->spinlock, flags);
2582         /* set mode, allow conversions through software gate */
2583         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2584         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2585         if (thisboard->layout != LAYOUT_4020) {
2586                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2587                 if (cmd->convert_src == TRIG_EXT)
2588                         /*  good old mode 13 */
2589                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2590                 else
2591                         /*  mode 8.  What else could you need? */
2592                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2593         } else {
2594                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2595                 if (cmd->chanlist_len == 4)
2596                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2597                 else if (cmd->chanlist_len == 2)
2598                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2599                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2600                 devpriv->adc_control1_bits |=
2601                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2602                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2603                 devpriv->adc_control1_bits |=
2604                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2605                                                       [cmd->chanlist_len - 1]));
2606         }
2607         writew(devpriv->adc_control1_bits,
2608                devpriv->main_iobase + ADC_CONTROL1_REG);
2609         DEBUG_PRINT("control1 bits 0x%x\n", devpriv->adc_control1_bits);
2610         spin_unlock_irqrestore(&dev->spinlock, flags);
2611
2612         /*  clear adc buffer */
2613         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2614
2615         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2616             thisboard->layout == LAYOUT_4020) {
2617                 devpriv->ai_dma_index = 0;
2618
2619                 /*  set dma transfer size */
2620                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2621                         devpriv->ai_dma_desc[i].transfer_size =
2622                                 cpu_to_le32(dma_transfer_size(dev) *
2623                                             sizeof(uint16_t));
2624
2625                 /*  give location of first dma descriptor */
2626                 load_first_dma_descriptor(dev, 1,
2627                                           devpriv->ai_dma_desc_bus_addr |
2628                                           PLX_DESC_IN_PCI_BIT |
2629                                           PLX_INTR_TERM_COUNT |
2630                                           PLX_XFER_LOCAL_TO_PCI);
2631
2632                 dma_start_sync(dev, 1);
2633         }
2634
2635         if (thisboard->layout == LAYOUT_4020) {
2636                 /* set source for external triggers */
2637                 bits = 0;
2638                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2639                         bits |= EXT_START_TRIG_BNC_BIT;
2640                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2641                         bits |= EXT_STOP_TRIG_BNC_BIT;
2642                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2643         }
2644
2645         spin_lock_irqsave(&dev->spinlock, flags);
2646
2647         /* enable pacing, triggering, etc */
2648         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2649         if (cmd->flags & TRIG_WAKE_EOS)
2650                 bits |= ADC_DMA_DISABLE_BIT;
2651         /*  set start trigger */
2652         if (cmd->start_src == TRIG_EXT) {
2653                 bits |= ADC_START_TRIG_EXT_BITS;
2654                 if (cmd->start_arg & CR_INVERT)
2655                         bits |= ADC_START_TRIG_FALLING_BIT;
2656         } else if (cmd->start_src == TRIG_NOW)
2657                 bits |= ADC_START_TRIG_SOFT_BITS;
2658         if (use_hw_sample_counter(cmd))
2659                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2660         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2661         DEBUG_PRINT("control0 bits 0x%x\n", bits);
2662
2663         devpriv->ai_cmd_running = 1;
2664
2665         spin_unlock_irqrestore(&dev->spinlock, flags);
2666
2667         /*  start acquisition */
2668         if (cmd->start_src == TRIG_NOW) {
2669                 writew(0, devpriv->main_iobase + ADC_START_REG);
2670                 DEBUG_PRINT("soft trig\n");
2671         }
2672
2673         return 0;
2674 }
2675
2676 /* read num_samples from 16 bit wide ai fifo */
2677 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2678 {
2679         struct pcidas64_private *devpriv = dev->private;
2680         struct comedi_subdevice *s = dev->read_subdev;
2681         struct comedi_async *async = s->async;
2682         struct comedi_cmd *cmd = &async->cmd;
2683         unsigned int i;
2684         uint16_t prepost_bits;
2685         int read_segment, read_index, write_segment, write_index;
2686         int num_samples;
2687
2688         do {
2689                 /*  get least significant 15 bits */
2690                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2691                              0x7fff;
2692                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2693                               0x7fff;
2694                 /* Get most significant bits (grey code).
2695                  * Different boards use different code so use a scheme
2696                  * that doesn't depend on encoding.  This read must
2697                  * occur after reading least significant 15 bits to avoid race
2698                  * with fifo switching to next segment. */
2699                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2700
2701                 /* if read and write pointers are not on the same fifo segment,
2702                  * read to the end of the read segment */
2703                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2704                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2705
2706                 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2707                             read_segment, write_segment, read_index,
2708                             write_index);
2709
2710                 if (read_segment != write_segment)
2711                         num_samples =
2712                                 devpriv->ai_fifo_segment_length - read_index;
2713                 else
2714                         num_samples = write_index - read_index;
2715
2716                 if (cmd->stop_src == TRIG_COUNT) {
2717                         if (devpriv->ai_count == 0)
2718                                 break;
2719                         if (num_samples > devpriv->ai_count)
2720                                 num_samples = devpriv->ai_count;
2721
2722                         devpriv->ai_count -= num_samples;
2723                 }
2724
2725                 if (num_samples < 0) {
2726                         dev_err(dev->class_dev,
2727                                 "cb_pcidas64: bug! num_samples < 0\n");
2728                         break;
2729                 }
2730
2731                 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2732
2733                 for (i = 0; i < num_samples; i++) {
2734                         cfc_write_to_buffer(s,
2735                                             readw(devpriv->main_iobase +
2736                                                   ADC_FIFO_REG));
2737                 }
2738
2739         } while (read_segment != write_segment);
2740 }
2741
2742 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2743  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2744  * supports the use of pio for draining the last remaining points from the
2745  * fifo when a data acquisition operation has completed).
2746  */
2747 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2748 {
2749         struct pcidas64_private *devpriv = dev->private;
2750         struct comedi_subdevice *s = dev->read_subdev;
2751         struct comedi_async *async = s->async;
2752         struct comedi_cmd *cmd = &async->cmd;
2753         unsigned int i;
2754         unsigned int max_transfer = 100000;
2755         uint32_t fifo_data;
2756         int write_code =
2757                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2758         int read_code =
2759                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2760
2761         if (cmd->stop_src == TRIG_COUNT) {
2762                 if (max_transfer > devpriv->ai_count)
2763                         max_transfer = devpriv->ai_count;
2764
2765         }
2766         for (i = 0; read_code != write_code && i < max_transfer;) {
2767                 fifo_data = readl(devpriv->dio_counter_iobase + ADC_FIFO_REG);
2768                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2769                 i++;
2770                 if (i < max_transfer) {
2771                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2772                         i++;
2773                 }
2774                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2775                             0x7fff;
2776         }
2777         devpriv->ai_count -= i;
2778 }
2779
2780 /* empty fifo */
2781 static void pio_drain_ai_fifo(struct comedi_device *dev)
2782 {
2783         const struct pcidas64_board *thisboard = comedi_board(dev);
2784
2785         if (thisboard->layout == LAYOUT_4020)
2786                 pio_drain_ai_fifo_32(dev);
2787         else
2788                 pio_drain_ai_fifo_16(dev);
2789 }
2790
2791 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2792 {
2793         const struct pcidas64_board *thisboard = comedi_board(dev);
2794         struct pcidas64_private *devpriv = dev->private;
2795         struct comedi_async *async = dev->read_subdev->async;
2796         uint32_t next_transfer_addr;
2797         int j;
2798         int num_samples = 0;
2799         void __iomem *pci_addr_reg;
2800
2801         if (channel)
2802                 pci_addr_reg =
2803                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2804         else
2805                 pci_addr_reg =
2806                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2807
2808         /*  loop until we have read all the full buffers */
2809         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2810              (next_transfer_addr <
2811               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2812               next_transfer_addr >=
2813               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2814               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2815                 /*  transfer data from dma buffer to comedi buffer */
2816                 num_samples = dma_transfer_size(dev);
2817                 if (async->cmd.stop_src == TRIG_COUNT) {
2818                         if (num_samples > devpriv->ai_count)
2819                                 num_samples = devpriv->ai_count;
2820                         devpriv->ai_count -= num_samples;
2821                 }
2822                 cfc_write_array_to_buffer(dev->read_subdev,
2823                                           devpriv->ai_buffer[devpriv->
2824                                                              ai_dma_index],
2825                                           num_samples * sizeof(uint16_t));
2826                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2827                                         ai_dma_ring_count(thisboard);
2828
2829                 DEBUG_PRINT("next buffer addr 0x%lx\n",
2830                             (unsigned long)devpriv->
2831                             ai_buffer_bus_addr[devpriv->ai_dma_index]);
2832                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2833         }
2834         /* XXX check for dma ring buffer overrun
2835          * (use end-of-chain bit to mark last unused buffer) */
2836 }
2837
2838 static void handle_ai_interrupt(struct comedi_device *dev,
2839                                 unsigned short status,
2840                                 unsigned int plx_status)
2841 {
2842         const struct pcidas64_board *thisboard = comedi_board(dev);
2843         struct pcidas64_private *devpriv = dev->private;
2844         struct comedi_subdevice *s = dev->read_subdev;
2845         struct comedi_async *async = s->async;
2846         struct comedi_cmd *cmd = &async->cmd;
2847         uint8_t dma1_status;
2848         unsigned long flags;
2849
2850         /*  check for fifo overrun */
2851         if (status & ADC_OVERRUN_BIT) {
2852                 comedi_error(dev, "fifo overrun");
2853                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2854         }
2855         /*  spin lock makes sure no one else changes plx dma control reg */
2856         spin_lock_irqsave(&dev->spinlock, flags);
2857         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2858         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2859                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2860                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2861                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2862
2863                 if (dma1_status & PLX_DMA_EN_BIT)
2864                         drain_dma_buffers(dev, 1);
2865
2866                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2867         }
2868         spin_unlock_irqrestore(&dev->spinlock, flags);
2869
2870         if (status & ADC_DONE_BIT)
2871                 DEBUG_PRINT("adc done interrupt\n");
2872
2873         /*  drain fifo with pio */
2874         if ((status & ADC_DONE_BIT) ||
2875             ((cmd->flags & TRIG_WAKE_EOS) &&
2876              (status & ADC_INTR_PENDING_BIT) &&
2877              (thisboard->layout != LAYOUT_4020))) {
2878                 DEBUG_PRINT("pio fifo drain\n");
2879                 spin_lock_irqsave(&dev->spinlock, flags);
2880                 if (devpriv->ai_cmd_running) {
2881                         spin_unlock_irqrestore(&dev->spinlock, flags);
2882                         pio_drain_ai_fifo(dev);
2883                 } else
2884                         spin_unlock_irqrestore(&dev->spinlock, flags);
2885         }
2886         /*  if we are have all the data, then quit */
2887         if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2888             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2889                 async->events |= COMEDI_CB_EOA;
2890         }
2891
2892         cfc_handle_events(dev, s);
2893 }
2894
2895 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2896 {
2897         struct pcidas64_private *devpriv = dev->private;
2898         unsigned int buffer_index;
2899
2900         if (devpriv->ao_dma_index == 0)
2901                 buffer_index = AO_DMA_RING_COUNT - 1;
2902         else
2903                 buffer_index = devpriv->ao_dma_index - 1;
2904         return buffer_index;
2905 }
2906
2907 static int last_ao_dma_load_completed(struct comedi_device *dev)
2908 {
2909         struct pcidas64_private *devpriv = dev->private;
2910         unsigned int buffer_index;
2911         unsigned int transfer_address;
2912         unsigned short dma_status;
2913
2914         buffer_index = prev_ao_dma_index(dev);
2915         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2916         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2917                 return 0;
2918
2919         transfer_address =
2920                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2921         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2922                 return 0;
2923
2924         return 1;
2925 }
2926
2927 static int ao_stopped_by_error(struct comedi_device *dev,
2928                                const struct comedi_cmd *cmd)
2929 {
2930         struct pcidas64_private *devpriv = dev->private;
2931
2932         if (cmd->stop_src == TRIG_NONE)
2933                 return 1;
2934         if (cmd->stop_src == TRIG_COUNT) {
2935                 if (devpriv->ao_count)
2936                         return 1;
2937                 if (last_ao_dma_load_completed(dev) == 0)
2938                         return 1;
2939         }
2940         return 0;
2941 }
2942
2943 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2944                                        unsigned short dma_status)
2945 {
2946         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2947             (dma_status & PLX_DMA_EN_BIT) == 0)
2948                 return 0;
2949         if (last_ao_dma_load_completed(dev))
2950                 return 0;
2951
2952         return 1;
2953 }
2954
2955 static void restart_ao_dma(struct comedi_device *dev)
2956 {
2957         struct pcidas64_private *devpriv = dev->private;
2958         unsigned int dma_desc_bits;
2959
2960         dma_desc_bits =
2961                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2962         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2963         DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
2964         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2965
2966         dma_start_sync(dev, 0);
2967 }
2968
2969 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2970                                        const struct comedi_cmd *cmd)
2971 {
2972         struct pcidas64_private *devpriv = dev->private;
2973         unsigned int num_bytes, buffer_index, prev_buffer_index;
2974         unsigned int next_bits;
2975
2976         buffer_index = devpriv->ao_dma_index;
2977         prev_buffer_index = prev_ao_dma_index(dev);
2978
2979         DEBUG_PRINT("attempting to load ao buffer %i (0x%llx)\n", buffer_index,
2980                     (unsigned long long)devpriv->ao_buffer_bus_addr[
2981                                                                 buffer_index]);
2982
2983         num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
2984         if (num_bytes > DMA_BUFFER_SIZE)
2985                 num_bytes = DMA_BUFFER_SIZE;
2986         if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
2987                 num_bytes = devpriv->ao_count;
2988         num_bytes -= num_bytes % bytes_in_sample;
2989
2990         if (num_bytes == 0)
2991                 return 0;
2992
2993         DEBUG_PRINT("loading %i bytes\n", num_bytes);
2994
2995         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
2996                                                devpriv->
2997                                                ao_buffer[buffer_index],
2998                                                num_bytes);
2999         devpriv->ao_dma_desc[buffer_index].transfer_size =
3000                 cpu_to_le32(num_bytes);
3001         /* set end of chain bit so we catch underruns */
3002         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
3003         next_bits |= PLX_END_OF_CHAIN_BIT;
3004         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3005         /* clear end of chain bit on previous buffer now that we have set it
3006          * for the last buffer */
3007         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
3008         next_bits &= ~PLX_END_OF_CHAIN_BIT;
3009         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3010
3011         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3012         devpriv->ao_count -= num_bytes;
3013
3014         return num_bytes;
3015 }
3016
3017 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3018 {
3019         struct pcidas64_private *devpriv = dev->private;
3020         unsigned int num_bytes;
3021         unsigned int next_transfer_addr;
3022         void __iomem *pci_addr_reg =
3023                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3024         unsigned int buffer_index;
3025
3026         do {
3027                 buffer_index = devpriv->ao_dma_index;
3028                 /* don't overwrite data that hasn't been transferred yet */
3029                 next_transfer_addr = readl(pci_addr_reg);
3030                 if (next_transfer_addr >=
3031                     devpriv->ao_buffer_bus_addr[buffer_index] &&
3032                     next_transfer_addr <
3033                     devpriv->ao_buffer_bus_addr[buffer_index] +
3034                     DMA_BUFFER_SIZE)
3035                         return;
3036                 num_bytes = load_ao_dma_buffer(dev, cmd);
3037         } while (num_bytes >= DMA_BUFFER_SIZE);
3038 }
3039
3040 static void handle_ao_interrupt(struct comedi_device *dev,
3041                                 unsigned short status, unsigned int plx_status)
3042 {
3043         struct pcidas64_private *devpriv = dev->private;
3044         struct comedi_subdevice *s = dev->write_subdev;
3045         struct comedi_async *async;
3046         struct comedi_cmd *cmd;
3047         uint8_t dma0_status;
3048         unsigned long flags;
3049
3050         /* board might not support ao, in which case write_subdev is NULL */
3051         if (s == NULL)
3052                 return;
3053         async = s->async;
3054         cmd = &async->cmd;
3055
3056         /*  spin lock makes sure no one else changes plx dma control reg */
3057         spin_lock_irqsave(&dev->spinlock, flags);
3058         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3059         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3060                 if ((dma0_status & PLX_DMA_EN_BIT) &&
3061                     !(dma0_status & PLX_DMA_DONE_BIT))
3062                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3063                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3064                 else
3065                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3066                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3067                 spin_unlock_irqrestore(&dev->spinlock, flags);
3068                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3069                 if (dma0_status & PLX_DMA_EN_BIT) {
3070                         load_ao_dma(dev, cmd);
3071                         /* try to recover from dma end-of-chain event */
3072                         if (ao_dma_needs_restart(dev, dma0_status))
3073                                 restart_ao_dma(dev);
3074                 }
3075                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3076         } else {
3077                 spin_unlock_irqrestore(&dev->spinlock, flags);
3078         }
3079
3080         if ((status & DAC_DONE_BIT)) {
3081                 async->events |= COMEDI_CB_EOA;
3082                 if (ao_stopped_by_error(dev, cmd))
3083                         async->events |= COMEDI_CB_ERROR;
3084                 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3085                             readl(devpriv->plx9080_iobase +
3086                                   PLX_DMA0_DESCRIPTOR_REG));
3087                 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3088                             readl(devpriv->plx9080_iobase +
3089                                   PLX_DMA0_PCI_ADDRESS_REG));
3090         }
3091         cfc_handle_events(dev, s);
3092 }
3093
3094 static irqreturn_t handle_interrupt(int irq, void *d)
3095 {
3096         struct comedi_device *dev = d;
3097         struct pcidas64_private *devpriv = dev->private;
3098         unsigned short status;
3099         uint32_t plx_status;
3100         uint32_t plx_bits;
3101
3102         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3103         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3104
3105         DEBUG_PRINT("hw status 0x%x, plx status 0x%x\n", status, plx_status);
3106
3107         /* an interrupt before all the postconfig stuff gets done could
3108          * cause a NULL dereference if we continue through the
3109          * interrupt handler */
3110         if (dev->attached == 0) {
3111                 DEBUG_PRINT("premature interrupt, ignoring\n");
3112                 return IRQ_HANDLED;
3113         }
3114         handle_ai_interrupt(dev, status, plx_status);
3115         handle_ao_interrupt(dev, status, plx_status);
3116
3117         /*  clear possible plx9080 interrupt sources */
3118         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3119                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3120                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3121                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3122         }
3123
3124         DEBUG_PRINT("exiting handler\n");
3125
3126         return IRQ_HANDLED;
3127 }
3128
3129 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3130 {
3131         struct pcidas64_private *devpriv = dev->private;
3132         unsigned long flags;
3133
3134         spin_lock_irqsave(&dev->spinlock, flags);
3135         if (devpriv->ai_cmd_running == 0) {
3136                 spin_unlock_irqrestore(&dev->spinlock, flags);
3137                 return 0;
3138         }
3139         devpriv->ai_cmd_running = 0;
3140         spin_unlock_irqrestore(&dev->spinlock, flags);
3141
3142         disable_ai_pacing(dev);
3143
3144         abort_dma(dev, 1);
3145
3146         DEBUG_PRINT("ai canceled\n");
3147         return 0;
3148 }
3149
3150 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3151                     struct comedi_insn *insn, unsigned int *data)
3152 {
3153         const struct pcidas64_board *thisboard = comedi_board(dev);
3154         struct pcidas64_private *devpriv = dev->private;
3155         int chan = CR_CHAN(insn->chanspec);
3156         int range = CR_RANGE(insn->chanspec);
3157
3158         /*  do some initializing */
3159         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3160
3161         /*  set range */
3162         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3163         writew(devpriv->dac_control1_bits,
3164                devpriv->main_iobase + DAC_CONTROL1_REG);
3165
3166         /*  write to channel */
3167         if (thisboard->layout == LAYOUT_4020) {
3168                 writew(data[0] & 0xff,
3169                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3170                 writew((data[0] >> 8) & 0xf,
3171                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3172         } else {
3173                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3174         }
3175
3176         /*  remember output value */
3177         devpriv->ao_value[chan] = data[0];
3178
3179         return 1;
3180 }
3181
3182 static int ao_readback_insn(struct comedi_device *dev,
3183                             struct comedi_subdevice *s,
3184                             struct comedi_insn *insn, unsigned int *data)
3185 {
3186         struct pcidas64_private *devpriv = dev->private;
3187
3188         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3189
3190         return 1;
3191 }
3192
3193 static void set_dac_control0_reg(struct comedi_device *dev,
3194                                  const struct comedi_cmd *cmd)
3195 {
3196         struct pcidas64_private *devpriv = dev->private;
3197         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3198                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3199
3200         if (cmd->start_src == TRIG_EXT) {
3201                 bits |= WAVEFORM_TRIG_EXT_BITS;
3202                 if (cmd->start_arg & CR_INVERT)
3203                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3204         } else {
3205                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3206         }
3207         if (cmd->scan_begin_src == TRIG_EXT) {
3208                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3209                 if (cmd->scan_begin_arg & CR_INVERT)
3210                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3211         }
3212         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3213 }
3214
3215 static void set_dac_control1_reg(struct comedi_device *dev,
3216                                  const struct comedi_cmd *cmd)
3217 {
3218         struct pcidas64_private *devpriv = dev->private;
3219         int i;
3220
3221         for (i = 0; i < cmd->chanlist_len; i++) {
3222                 int channel, range;
3223
3224                 channel = CR_CHAN(cmd->chanlist[i]);
3225                 range = CR_RANGE(cmd->chanlist[i]);
3226                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3227                                    range);
3228         }
3229         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3230         writew(devpriv->dac_control1_bits,
3231                devpriv->main_iobase + DAC_CONTROL1_REG);
3232 }
3233
3234 static void set_dac_select_reg(struct comedi_device *dev,
3235                                const struct comedi_cmd *cmd)
3236 {
3237         struct pcidas64_private *devpriv = dev->private;
3238         uint16_t bits;
3239         unsigned int first_channel, last_channel;
3240
3241         first_channel = CR_CHAN(cmd->chanlist[0]);
3242         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3243         if (last_channel < first_channel)
3244                 comedi_error(dev, "bug! last ao channel < first ao channel");
3245
3246         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3247
3248         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3249 }
3250
3251 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3252 {
3253         return get_divisor(ns, flags) - 2;
3254 }
3255
3256 static void set_dac_interval_regs(struct comedi_device *dev,
3257                                   const struct comedi_cmd *cmd)
3258 {
3259         struct pcidas64_private *devpriv = dev->private;
3260         unsigned int divisor;
3261
3262         if (cmd->scan_begin_src != TRIG_TIMER)
3263                 return;
3264
3265         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3266         if (divisor > max_counter_value) {
3267                 comedi_error(dev, "bug! ao divisor too big");
3268                 divisor = max_counter_value;
3269         }
3270         writew(divisor & 0xffff,
3271                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3272         writew((divisor >> 16) & 0xff,
3273                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3274 }
3275
3276 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3277 {
3278         struct pcidas64_private *devpriv = dev->private;
3279         unsigned int num_bytes;
3280         int i;
3281
3282         /* clear queue pointer too, since external queue has
3283          * weird interactions with ao fifo */
3284         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3285         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3286
3287         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3288         if (cmd->stop_src == TRIG_COUNT &&
3289             num_bytes / bytes_in_sample > devpriv->ao_count)
3290                 num_bytes = devpriv->ao_count * bytes_in_sample;
3291         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3292                                                devpriv->ao_bounce_buffer,
3293                                                num_bytes);
3294         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3295                 writew(devpriv->ao_bounce_buffer[i],
3296                        devpriv->main_iobase + DAC_FIFO_REG);
3297         }
3298         devpriv->ao_count -= num_bytes / bytes_in_sample;
3299         if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3300                 return 0;
3301         num_bytes = load_ao_dma_buffer(dev, cmd);
3302         if (num_bytes == 0)
3303                 return -1;
3304         load_ao_dma(dev, cmd);
3305
3306         dma_start_sync(dev, 0);
3307
3308         return 0;
3309 }
3310
3311 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3312 {
3313         const struct pcidas64_board *thisboard = comedi_board(dev);
3314
3315         if (dev->read_subdev->busy)
3316                 return 0;
3317         if (thisboard->layout == LAYOUT_4020)
3318                 return 0;
3319         else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3320                 return 0;
3321         return 1;
3322 }
3323
3324 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3325                       unsigned int trig_num)
3326 {
3327         struct pcidas64_private *devpriv = dev->private;
3328         struct comedi_cmd *cmd = &s->async->cmd;
3329         int retval;
3330
3331         if (trig_num != 0)
3332                 return -EINVAL;
3333
3334         retval = prep_ao_dma(dev, cmd);
3335         if (retval < 0)
3336                 return -EPIPE;
3337
3338         set_dac_control0_reg(dev, cmd);
3339
3340         if (cmd->start_src == TRIG_INT)
3341                 writew(0, devpriv->main_iobase + DAC_START_REG);
3342
3343         s->async->inttrig = NULL;
3344
3345         return 0;
3346 }
3347
3348 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3349 {
3350         struct pcidas64_private *devpriv = dev->private;
3351         struct comedi_cmd *cmd = &s->async->cmd;
3352
3353         if (external_ai_queue_in_use(dev)) {
3354                 warn_external_queue(dev);
3355                 return -EBUSY;
3356         }
3357         /* disable analog output system during setup */
3358         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3359
3360         devpriv->ao_dma_index = 0;
3361         devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3362
3363         set_dac_select_reg(dev, cmd);
3364         set_dac_interval_regs(dev, cmd);
3365         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3366                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3367
3368         set_dac_control1_reg(dev, cmd);
3369         s->async->inttrig = ao_inttrig;
3370
3371         return 0;
3372 }
3373
3374 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3375                       struct comedi_cmd *cmd)
3376 {
3377         const struct pcidas64_board *thisboard = comedi_board(dev);
3378         int err = 0;
3379         unsigned int tmp_arg;
3380         int i;
3381
3382         /* Step 1 : check if triggers are trivially valid */
3383
3384         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3385         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3386                                      TRIG_TIMER | TRIG_EXT);
3387         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3388         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3389         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3390
3391         if (err)
3392                 return 1;
3393
3394         /* Step 2a : make sure trigger sources are unique */
3395
3396         err |= cfc_check_trigger_is_unique(cmd->start_src);
3397         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3398
3399         /* Step 2b : and mutually compatible */
3400
3401         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3402                 err |= -EINVAL;
3403         if (cmd->stop_src != TRIG_COUNT &&
3404             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3405                 err |= -EINVAL;
3406
3407         if (err)
3408                 return 2;
3409
3410         /* Step 3: check if arguments are trivially valid */
3411
3412         if (cmd->scan_begin_src == TRIG_TIMER) {
3413                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3414                                                  thisboard->ao_scan_speed);
3415                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3416                     max_counter_value) {
3417                         cmd->scan_begin_arg = (max_counter_value + 2) *
3418                                               TIMER_BASE;
3419                         err |= -EINVAL;
3420                 }
3421         }
3422
3423         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3424         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3425
3426         if (err)
3427                 return 3;
3428
3429         /* step 4: fix up any arguments */
3430
3431         if (cmd->scan_begin_src == TRIG_TIMER) {
3432                 tmp_arg = cmd->scan_begin_arg;
3433                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3434                                                   cmd->flags) * TIMER_BASE;
3435                 if (tmp_arg != cmd->scan_begin_arg)
3436                         err++;
3437         }
3438
3439         if (err)
3440                 return 4;
3441
3442         if (cmd->chanlist) {
3443                 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3444                 for (i = 1; i < cmd->chanlist_len; i++) {
3445                         if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3446                                 comedi_error(dev,
3447                                              "chanlist must use consecutive channels");
3448                                 err++;
3449                                 break;
3450                         }
3451                 }
3452         }
3453
3454         if (err)
3455                 return 5;
3456
3457         return 0;
3458 }
3459
3460 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3461 {
3462         struct pcidas64_private *devpriv = dev->private;
3463
3464         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3465         abort_dma(dev, 0);
3466         return 0;
3467 }
3468
3469 static int dio_callback(int dir, int port, int data, unsigned long arg)
3470 {
3471         void __iomem *iobase = (void __iomem *)arg;
3472         if (dir) {
3473                 writeb(data, iobase + port);
3474                 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3475                 return 0;
3476         } else {
3477                 return readb(iobase + port);
3478         }
3479 }
3480
3481 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3482 {
3483         void __iomem *iobase = (void __iomem *)arg;
3484         if (dir) {
3485                 writew(data, iobase + 2 * port);
3486                 return 0;
3487         } else {
3488                 return readw(iobase + 2 * port);
3489         }
3490 }
3491
3492 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3493                     struct comedi_insn *insn, unsigned int *data)
3494 {
3495         struct pcidas64_private *devpriv = dev->private;
3496         unsigned int bits;
3497
3498         bits = readb(devpriv->dio_counter_iobase + DI_REG);
3499         bits &= 0xf;
3500         data[1] = bits;
3501         data[0] = 0;
3502
3503         return insn->n;
3504 }
3505
3506 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3507                     struct comedi_insn *insn, unsigned int *data)
3508 {
3509         struct pcidas64_private *devpriv = dev->private;
3510
3511         data[0] &= 0xf;
3512         /*  zero bits we are going to change */
3513         s->state &= ~data[0];
3514         /*  set new bits */
3515         s->state |= data[0] & data[1];
3516
3517         writeb(s->state, devpriv->dio_counter_iobase + DO_REG);
3518
3519         data[1] = s->state;
3520
3521         return insn->n;
3522 }
3523
3524 static int dio_60xx_config_insn(struct comedi_device *dev,
3525                                 struct comedi_subdevice *s,
3526                                 struct comedi_insn *insn, unsigned int *data)
3527 {
3528         struct pcidas64_private *devpriv = dev->private;
3529         unsigned int mask;
3530
3531         mask = 1 << CR_CHAN(insn->chanspec);
3532
3533         switch (data[0]) {
3534         case INSN_CONFIG_DIO_INPUT:
3535                 s->io_bits &= ~mask;
3536                 break;
3537         case INSN_CONFIG_DIO_OUTPUT:
3538                 s->io_bits |= mask;
3539                 break;
3540         case INSN_CONFIG_DIO_QUERY:
3541                 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3542                 return 2;
3543         default:
3544                 return -EINVAL;
3545         }
3546
3547         writeb(s->io_bits,
3548                devpriv->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3549
3550         return 1;
3551 }
3552
3553 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3554                           struct comedi_insn *insn, unsigned int *data)
3555 {
3556         struct pcidas64_private *devpriv = dev->private;
3557
3558         if (data[0]) {
3559                 s->state &= ~data[0];
3560                 s->state |= (data[0] & data[1]);
3561                 writeb(s->state,
3562                        devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3563         }
3564
3565         data[1] = readb(devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3566
3567         return insn->n;
3568 }
3569
3570 /* pci-6025 8800 caldac:
3571  * address 0 == dac channel 0 offset
3572  * address 1 == dac channel 0 gain
3573  * address 2 == dac channel 1 offset
3574  * address 3 == dac channel 1 gain
3575  * address 4 == fine adc offset
3576  * address 5 == coarse adc offset
3577  * address 6 == coarse adc gain
3578  * address 7 == fine adc gain
3579  */
3580 /* pci-6402/16 uses all 8 channels for dac:
3581  * address 0 == dac channel 0 fine gain
3582  * address 1 == dac channel 0 coarse gain
3583  * address 2 == dac channel 0 coarse offset
3584  * address 3 == dac channel 1 coarse offset
3585  * address 4 == dac channel 1 fine gain
3586  * address 5 == dac channel 1 coarse gain
3587  * address 6 == dac channel 0 fine offset
3588  * address 7 == dac channel 1 fine offset
3589 */
3590
3591 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3592                              uint8_t value)
3593 {
3594         struct pcidas64_private *devpriv = dev->private;
3595         static const int num_caldac_channels = 8;
3596         static const int bitstream_length = 11;
3597         unsigned int bitstream = ((address & 0x7) << 8) | value;
3598         unsigned int bit, register_bits;
3599         static const int caldac_8800_udelay = 1;
3600
3601         if (address >= num_caldac_channels) {
3602                 comedi_error(dev, "illegal caldac channel");
3603                 return -1;
3604         }
3605         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3606                 register_bits = 0;
3607                 if (bitstream & bit)
3608                         register_bits |= SERIAL_DATA_IN_BIT;
3609                 udelay(caldac_8800_udelay);
3610                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3611                 register_bits |= SERIAL_CLOCK_BIT;
3612                 udelay(caldac_8800_udelay);
3613                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3614         }
3615         udelay(caldac_8800_udelay);
3616         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3617         udelay(caldac_8800_udelay);
3618         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3619         udelay(caldac_8800_udelay);
3620         return 0;
3621 }
3622
3623 /* 4020 caldacs */
3624 static int caldac_i2c_write(struct comedi_device *dev,
3625                             unsigned int caldac_channel, unsigned int value)
3626 {
3627         uint8_t serial_bytes[3];
3628         uint8_t i2c_addr;
3629         enum pointer_bits {
3630                 /*  manual has gain and offset bits switched */
3631                 OFFSET_0_2 = 0x1,
3632                 GAIN_0_2 = 0x2,
3633                 OFFSET_1_3 = 0x4,
3634                 GAIN_1_3 = 0x8,
3635         };
3636         enum data_bits {
3637                 NOT_CLEAR_REGISTERS = 0x20,
3638         };
3639
3640         switch (caldac_channel) {
3641         case 0:         /*  chan 0 offset */
3642                 i2c_addr = CALDAC0_I2C_ADDR;
3643                 serial_bytes[0] = OFFSET_0_2;
3644                 break;
3645         case 1:         /*  chan 1 offset */
3646                 i2c_addr = CALDAC0_I2C_ADDR;
3647                 serial_bytes[0] = OFFSET_1_3;
3648                 break;
3649         case 2:         /*  chan 2 offset */
3650                 i2c_addr = CALDAC1_I2C_ADDR;
3651                 serial_bytes[0] = OFFSET_0_2;
3652                 break;
3653         case 3:         /*  chan 3 offset */
3654                 i2c_addr = CALDAC1_I2C_ADDR;
3655                 serial_bytes[0] = OFFSET_1_3;
3656                 break;
3657         case 4:         /*  chan 0 gain */
3658                 i2c_addr = CALDAC0_I2C_ADDR;
3659                 serial_bytes[0] = GAIN_0_2;
3660                 break;
3661         case 5:         /*  chan 1 gain */
3662                 i2c_addr = CALDAC0_I2C_ADDR;
3663                 serial_bytes[0] = GAIN_1_3;
3664                 break;
3665         case 6:         /*  chan 2 gain */
3666                 i2c_addr = CALDAC1_I2C_ADDR;
3667                 serial_bytes[0] = GAIN_0_2;
3668                 break;
3669         case 7:         /*  chan 3 gain */
3670                 i2c_addr = CALDAC1_I2C_ADDR;
3671                 serial_bytes[0] = GAIN_1_3;
3672                 break;
3673         default:
3674                 comedi_error(dev, "invalid caldac channel\n");
3675                 return -1;
3676                 break;
3677         }
3678         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3679         serial_bytes[2] = value & 0xff;
3680         i2c_write(dev, i2c_addr, serial_bytes, 3);
3681         return 0;
3682 }
3683
3684 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3685                          unsigned int value)
3686 {
3687         const struct pcidas64_board *thisboard = comedi_board(dev);
3688         struct pcidas64_private *devpriv = dev->private;
3689
3690         devpriv->caldac_state[channel] = value;
3691
3692         switch (thisboard->layout) {
3693         case LAYOUT_60XX:
3694         case LAYOUT_64XX:
3695                 caldac_8800_write(dev, channel, value);
3696                 break;
3697         case LAYOUT_4020:
3698                 caldac_i2c_write(dev, channel, value);
3699                 break;
3700         default:
3701                 break;
3702         }
3703 }
3704
3705 static int calib_write_insn(struct comedi_device *dev,
3706                             struct comedi_subdevice *s,
3707                             struct comedi_insn *insn, unsigned int *data)
3708 {
3709         struct pcidas64_private *devpriv = dev->private;
3710         int channel = CR_CHAN(insn->chanspec);
3711
3712         /* return immediately if setting hasn't changed, since
3713          * programming these things is slow */
3714         if (devpriv->caldac_state[channel] == data[0])
3715                 return 1;
3716
3717         caldac_write(dev, channel, data[0]);
3718
3719         return 1;
3720 }
3721
3722 static int calib_read_insn(struct comedi_device *dev,
3723                            struct comedi_subdevice *s, struct comedi_insn *insn,
3724                            unsigned int *data)
3725 {
3726         struct pcidas64_private *devpriv = dev->private;
3727         unsigned int channel = CR_CHAN(insn->chanspec);
3728
3729         data[0] = devpriv->caldac_state[channel];
3730
3731         return 1;
3732 }
3733
3734 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3735                          unsigned int value)
3736 {
3737         struct pcidas64_private *devpriv = dev->private;
3738         static const int bitstream_length = 10;
3739         unsigned int bit, register_bits;
3740         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3741         static const int ad8402_udelay = 1;
3742
3743         devpriv->ad8402_state[channel] = value;
3744
3745         register_bits = SELECT_8402_64XX_BIT;
3746         udelay(ad8402_udelay);
3747         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3748
3749         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3750                 if (bitstream & bit)
3751                         register_bits |= SERIAL_DATA_IN_BIT;
3752                 else
3753                         register_bits &= ~SERIAL_DATA_IN_BIT;
3754                 udelay(ad8402_udelay);
3755                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3756                 udelay(ad8402_udelay);
3757                 writew(register_bits | SERIAL_CLOCK_BIT,
3758                        devpriv->main_iobase + CALIBRATION_REG);
3759         }
3760
3761         udelay(ad8402_udelay);
3762         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3763 }
3764
3765 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3766 static int ad8402_write_insn(struct comedi_device *dev,
3767                              struct comedi_subdevice *s,
3768                              struct comedi_insn *insn, unsigned int *data)
3769 {
3770         struct pcidas64_private *devpriv = dev->private;
3771         int channel = CR_CHAN(insn->chanspec);
3772
3773         /* return immediately if setting hasn't changed, since
3774          * programming these things is slow */
3775         if (devpriv->ad8402_state[channel] == data[0])
3776                 return 1;
3777
3778         devpriv->ad8402_state[channel] = data[0];
3779
3780         ad8402_write(dev, channel, data[0]);
3781
3782         return 1;
3783 }
3784
3785 static int ad8402_read_insn(struct comedi_device *dev,
3786                             struct comedi_subdevice *s,
3787                             struct comedi_insn *insn, unsigned int *data)
3788 {
3789         struct pcidas64_private *devpriv = dev->private;
3790         unsigned int channel = CR_CHAN(insn->chanspec);
3791
3792         data[0] = devpriv->ad8402_state[channel];
3793
3794         return 1;
3795 }
3796
3797 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3798 {
3799         struct pcidas64_private *devpriv = dev->private;
3800         static const int bitstream_length = 11;
3801         static const int read_command = 0x6;
3802         unsigned int bitstream = (read_command << 8) | address;
3803         unsigned int bit;
3804         void __iomem * const plx_control_addr =
3805                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3806         uint16_t value;
3807         static const int value_length = 16;
3808         static const int eeprom_udelay = 1;
3809
3810         udelay(eeprom_udelay);
3811         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3812         /*  make sure we don't send anything to the i2c bus on 4020 */
3813         devpriv->plx_control_bits |= CTL_USERO;
3814         writel(devpriv->plx_control_bits, plx_control_addr);
3815         /*  activate serial eeprom */
3816         udelay(eeprom_udelay);
3817         devpriv->plx_control_bits |= CTL_EE_CS;
3818         writel(devpriv->plx_control_bits, plx_control_addr);
3819
3820         /*  write read command and desired memory address */
3821         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3822                 /*  set bit to be written */
3823                 udelay(eeprom_udelay);
3824                 if (bitstream & bit)
3825                         devpriv->plx_control_bits |= CTL_EE_W;
3826                 else
3827                         devpriv->plx_control_bits &= ~CTL_EE_W;
3828                 writel(devpriv->plx_control_bits, plx_control_addr);
3829                 /*  clock in bit */
3830                 udelay(eeprom_udelay);
3831                 devpriv->plx_control_bits |= CTL_EE_CLK;
3832                 writel(devpriv->plx_control_bits, plx_control_addr);
3833                 udelay(eeprom_udelay);
3834                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3835                 writel(devpriv->plx_control_bits, plx_control_addr);
3836         }
3837         /*  read back value from eeprom memory location */
3838         value = 0;
3839         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3840                 /*  clock out bit */
3841                 udelay(eeprom_udelay);
3842                 devpriv->plx_control_bits |= CTL_EE_CLK;
3843                 writel(devpriv->plx_control_bits, plx_control_addr);
3844                 udelay(eeprom_udelay);
3845                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3846                 writel(devpriv->plx_control_bits, plx_control_addr);
3847                 udelay(eeprom_udelay);
3848                 if (readl(plx_control_addr) & CTL_EE_R)
3849                         value |= bit;
3850         }
3851
3852         /*  deactivate eeprom serial input */
3853         udelay(eeprom_udelay);
3854         devpriv->plx_control_bits &= ~CTL_EE_CS;
3855         writel(devpriv->plx_control_bits, plx_control_addr);
3856
3857         return value;
3858 }
3859
3860 static int eeprom_read_insn(struct comedi_device *dev,
3861                             struct comedi_subdevice *s,
3862                             struct comedi_insn *insn, unsigned int *data)
3863 {
3864         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3865
3866         return 1;
3867 }
3868
3869 /* Allocate and initialize the subdevice structures.
3870  */
3871 static int setup_subdevices(struct comedi_device *dev)
3872 {
3873         const struct pcidas64_board *thisboard = comedi_board(dev);
3874         struct pcidas64_private *devpriv = dev->private;
3875         struct comedi_subdevice *s;
3876         void __iomem *dio_8255_iobase;
3877         int i;
3878         int ret;
3879
3880         ret = comedi_alloc_subdevices(dev, 10);
3881         if (ret)
3882                 return ret;
3883
3884         s = &dev->subdevices[0];
3885         /* analog input subdevice */
3886         dev->read_subdev = s;
3887         s->type = COMEDI_SUBD_AI;
3888         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3889         if (thisboard->layout == LAYOUT_60XX)
3890                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3891         else if (thisboard->layout == LAYOUT_64XX)
3892                 s->subdev_flags |= SDF_DIFF;
3893         /* XXX Number of inputs in differential mode is ignored */
3894         s->n_chan = thisboard->ai_se_chans;
3895         s->len_chanlist = 0x2000;
3896         s->maxdata = (1 << thisboard->ai_bits) - 1;
3897         s->range_table = thisboard->ai_range_table;
3898         s->insn_read = ai_rinsn;
3899         s->insn_config = ai_config_insn;
3900         s->do_cmd = ai_cmd;
3901         s->do_cmdtest = ai_cmdtest;
3902         s->cancel = ai_cancel;
3903         if (thisboard->layout == LAYOUT_4020) {
3904                 uint8_t data;
3905                 /*  set adc to read from inputs
3906                  *  (not internal calibration sources) */
3907                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3908                 /*  set channels to +-5 volt input ranges */
3909                 for (i = 0; i < s->n_chan; i++)
3910                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3911                 data = devpriv->i2c_cal_range_bits;
3912                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3913         }
3914
3915         /* analog output subdevice */
3916         s = &dev->subdevices[1];
3917         if (thisboard->ao_nchan) {
3918                 s->type = COMEDI_SUBD_AO;
3919                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3920                                   SDF_GROUND | SDF_CMD_WRITE;
3921                 s->n_chan = thisboard->ao_nchan;
3922                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3923                 s->range_table = thisboard->ao_range_table;
3924                 s->insn_read = ao_readback_insn;
3925                 s->insn_write = ao_winsn;
3926                 if (ao_cmd_is_supported(thisboard)) {
3927                         dev->write_subdev = s;
3928                         s->do_cmdtest = ao_cmdtest;
3929                         s->do_cmd = ao_cmd;
3930                         s->len_chanlist = thisboard->ao_nchan;
3931                         s->cancel = ao_cancel;
3932                 }
3933         } else {
3934                 s->type = COMEDI_SUBD_UNUSED;
3935         }
3936
3937         /*  digital input */
3938         s = &dev->subdevices[2];
3939         if (thisboard->layout == LAYOUT_64XX) {
3940                 s->type = COMEDI_SUBD_DI;
3941                 s->subdev_flags = SDF_READABLE;
3942                 s->n_chan = 4;
3943                 s->maxdata = 1;
3944                 s->range_table = &range_digital;
3945                 s->insn_bits = di_rbits;
3946         } else
3947                 s->type = COMEDI_SUBD_UNUSED;
3948
3949         /*  digital output */
3950         if (thisboard->layout == LAYOUT_64XX) {
3951                 s = &dev->subdevices[3];
3952                 s->type = COMEDI_SUBD_DO;
3953                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3954                 s->n_chan = 4;
3955                 s->maxdata = 1;
3956                 s->range_table = &range_digital;
3957                 s->insn_bits = do_wbits;
3958         } else
3959                 s->type = COMEDI_SUBD_UNUSED;
3960
3961         /* 8255 */
3962         s = &dev->subdevices[4];
3963         if (thisboard->has_8255) {
3964                 if (thisboard->layout == LAYOUT_4020) {
3965                         dio_8255_iobase = devpriv->main_iobase + I8255_4020_REG;
3966                         subdev_8255_init(dev, s, dio_callback_4020,
3967                                          (unsigned long)dio_8255_iobase);
3968                 } else {
3969                         dio_8255_iobase =
3970                                 devpriv->dio_counter_iobase + DIO_8255_OFFSET;
3971                         subdev_8255_init(dev, s, dio_callback,
3972                                          (unsigned long)dio_8255_iobase);
3973                 }
3974         } else
3975                 s->type = COMEDI_SUBD_UNUSED;
3976
3977         /*  8 channel dio for 60xx */
3978         s = &dev->subdevices[5];
3979         if (thisboard->layout == LAYOUT_60XX) {
3980                 s->type = COMEDI_SUBD_DIO;
3981                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3982                 s->n_chan = 8;
3983                 s->maxdata = 1;
3984                 s->range_table = &range_digital;
3985                 s->insn_config = dio_60xx_config_insn;
3986                 s->insn_bits = dio_60xx_wbits;
3987         } else
3988                 s->type = COMEDI_SUBD_UNUSED;
3989
3990         /*  caldac */
3991         s = &dev->subdevices[6];
3992         s->type = COMEDI_SUBD_CALIB;
3993         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3994         s->n_chan = 8;
3995         if (thisboard->layout == LAYOUT_4020)
3996                 s->maxdata = 0xfff;
3997         else
3998                 s->maxdata = 0xff;
3999         s->insn_read = calib_read_insn;
4000         s->insn_write = calib_write_insn;
4001         for (i = 0; i < s->n_chan; i++)
4002                 caldac_write(dev, i, s->maxdata / 2);
4003
4004         /*  2 channel ad8402 potentiometer */
4005         s = &dev->subdevices[7];
4006         if (thisboard->layout == LAYOUT_64XX) {
4007                 s->type = COMEDI_SUBD_CALIB;
4008                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4009                 s->n_chan = 2;
4010                 s->insn_read = ad8402_read_insn;
4011                 s->insn_write = ad8402_write_insn;
4012                 s->maxdata = 0xff;
4013                 for (i = 0; i < s->n_chan; i++)
4014                         ad8402_write(dev, i, s->maxdata / 2);
4015         } else
4016                 s->type = COMEDI_SUBD_UNUSED;
4017
4018         /* serial EEPROM, if present */
4019         s = &dev->subdevices[8];
4020         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
4021                 s->type = COMEDI_SUBD_MEMORY;
4022                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4023                 s->n_chan = 128;
4024                 s->maxdata = 0xffff;
4025                 s->insn_read = eeprom_read_insn;
4026         } else
4027                 s->type = COMEDI_SUBD_UNUSED;
4028
4029         /*  user counter subd XXX */
4030         s = &dev->subdevices[9];
4031         s->type = COMEDI_SUBD_UNUSED;
4032
4033         return 0;
4034 }
4035
4036 static const struct pcidas64_board
4037 *cb_pcidas64_find_pci_board(struct pci_dev *pcidev)
4038 {
4039         unsigned int i;
4040
4041         for (i = 0; i < ARRAY_SIZE(pcidas64_boards); i++)
4042                 if (pcidev->device == pcidas64_boards[i].device_id)
4043                         return &pcidas64_boards[i];
4044         return NULL;
4045 }
4046
4047 static int auto_attach(struct comedi_device *dev,
4048                                  unsigned long context_unused)
4049 {
4050         const struct pcidas64_board *thisboard;
4051         struct pcidas64_private *devpriv;
4052         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4053         uint32_t local_range, local_decode;
4054         int retval;
4055
4056         dev->board_ptr = cb_pcidas64_find_pci_board(pcidev);
4057         if (!dev->board_ptr) {
4058                 dev_err(dev->class_dev,
4059                         "cb_pcidas64: does not support pci %s\n",
4060                         pci_name(pcidev));
4061                 return -EINVAL;
4062         }
4063         thisboard = comedi_board(dev);
4064
4065         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4066         if (!devpriv)
4067                 return -ENOMEM;
4068         dev->private = devpriv;
4069
4070         if (comedi_pci_enable(pcidev, dev->driver->driver_name)) {
4071                 dev_warn(dev->class_dev,
4072                          "failed to enable PCI device and request regions\n");
4073                 return -EIO;
4074         }
4075         pci_set_master(pcidev);
4076
4077         /* Initialize dev->board_name */
4078         dev->board_name = thisboard->name;
4079
4080         dev->iobase = pci_resource_start(pcidev, MAIN_BADDRINDEX);
4081
4082         devpriv->plx9080_phys_iobase =
4083                 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
4084         devpriv->main_phys_iobase = dev->iobase;
4085         devpriv->dio_counter_phys_iobase =
4086                 pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
4087
4088         /*  remap, won't work with 2.0 kernels but who cares */
4089         devpriv->plx9080_iobase =
4090                 ioremap(devpriv->plx9080_phys_iobase,
4091                         pci_resource_len(pcidev, PLX9080_BADDRINDEX));
4092         devpriv->main_iobase =
4093                 ioremap(devpriv->main_phys_iobase,
4094                         pci_resource_len(pcidev, MAIN_BADDRINDEX));
4095         devpriv->dio_counter_iobase =
4096                 ioremap(devpriv->dio_counter_phys_iobase,
4097                         pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
4098
4099         if (!devpriv->plx9080_iobase || !devpriv->main_iobase
4100             || !devpriv->dio_counter_iobase) {
4101                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4102                 return -ENOMEM;
4103         }
4104
4105         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
4106         DEBUG_PRINT(" main remapped to 0x%p\n", devpriv->main_iobase);
4107         DEBUG_PRINT(" diocounter remapped to 0x%p\n",
4108                     devpriv->dio_counter_iobase);
4109
4110         /*  figure out what local addresses are */
4111         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
4112                       LRNG_MEM_MASK;
4113         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
4114                        local_range & LMAP_MEM_MASK;
4115         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4116                                   ~local_range) | local_decode;
4117         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
4118                       LRNG_MEM_MASK;
4119         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
4120                        local_range & LMAP_MEM_MASK;
4121         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4122                                   ~local_range) | local_decode;
4123
4124         DEBUG_PRINT(" local 0 io addr 0x%x\n", devpriv->local0_iobase);
4125         DEBUG_PRINT(" local 1 io addr 0x%x\n", devpriv->local1_iobase);
4126
4127         retval = alloc_and_init_dma_members(dev);
4128         if (retval < 0)
4129                 return retval;
4130
4131         devpriv->hw_revision =
4132                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4133         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4134                 devpriv->hw_revision);
4135         init_plx9080(dev);
4136         init_stc_registers(dev);
4137         /*  get irq */
4138         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4139                         "cb_pcidas64", dev)) {
4140                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4141                         pcidev->irq);
4142                 return -EINVAL;
4143         }
4144         dev->irq = pcidev->irq;
4145         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4146
4147         retval = setup_subdevices(dev);
4148         if (retval < 0)
4149                 return retval;
4150
4151         return 0;
4152 }
4153
4154 static void detach(struct comedi_device *dev)
4155 {
4156         const struct pcidas64_board *thisboard = comedi_board(dev);
4157         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4158         struct pcidas64_private *devpriv = dev->private;
4159         unsigned int i;
4160
4161         if (dev->irq)
4162                 free_irq(dev->irq, dev);
4163         if (devpriv) {
4164                 if (pcidev) {
4165                         if (devpriv->plx9080_iobase) {
4166                                 disable_plx_interrupts(dev);
4167                                 iounmap(devpriv->plx9080_iobase);
4168                         }
4169                         if (devpriv->main_iobase)
4170                                 iounmap(devpriv->main_iobase);
4171                         if (devpriv->dio_counter_iobase)
4172                                 iounmap(devpriv->dio_counter_iobase);
4173                         /*  free pci dma buffers */
4174                         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
4175                                 if (devpriv->ai_buffer[i])
4176                                         pci_free_consistent(pcidev,
4177                                                 DMA_BUFFER_SIZE,
4178                                                 devpriv->ai_buffer[i],
4179                                                 devpriv->ai_buffer_bus_addr[i]);
4180                         }
4181                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
4182                                 if (devpriv->ao_buffer[i])
4183                                         pci_free_consistent(pcidev,
4184                                                 DMA_BUFFER_SIZE,
4185                                                 devpriv->ao_buffer[i],
4186                                                 devpriv->ao_buffer_bus_addr[i]);
4187                         }
4188                         /*  free dma descriptors */
4189                         if (devpriv->ai_dma_desc)
4190                                 pci_free_consistent(pcidev,
4191                                         sizeof(struct plx_dma_desc) *
4192                                         ai_dma_ring_count(thisboard),
4193                                         devpriv->ai_dma_desc,
4194                                         devpriv->ai_dma_desc_bus_addr);
4195                         if (devpriv->ao_dma_desc)
4196                                 pci_free_consistent(pcidev,
4197                                         sizeof(struct plx_dma_desc) *
4198                                         AO_DMA_RING_COUNT,
4199                                         devpriv->ao_dma_desc,
4200                                         devpriv->ao_dma_desc_bus_addr);
4201                 }
4202         }
4203         if (dev->subdevices)
4204                 subdev_8255_cleanup(dev, &dev->subdevices[4]);
4205         if (pcidev) {
4206                 if (dev->iobase)
4207                         comedi_pci_disable(pcidev);
4208         }
4209 }
4210
4211 static struct comedi_driver cb_pcidas64_driver = {
4212         .driver_name    = "cb_pcidas64",
4213         .module         = THIS_MODULE,
4214         .auto_attach    = auto_attach,
4215         .detach         = detach,
4216 };
4217
4218 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4219                                            const struct pci_device_id *ent)
4220 {
4221         return comedi_pci_auto_config(dev, &cb_pcidas64_driver);
4222 }
4223
4224 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4225         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001d) },
4226         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001e) },
4227         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0035) },
4228         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0036) },
4229         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0037) },
4230         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0052) },
4231         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005d) },
4232         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005e) },
4233         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005f) },
4234         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0061) },
4235         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0062) },
4236         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0063) },
4237         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0064) },
4238         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0066) },
4239         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0067) },
4240         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0068) },
4241         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x006f) },
4242         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0078) },
4243         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0079) },
4244         { 0 }
4245 };
4246 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4247
4248 static struct pci_driver cb_pcidas64_pci_driver = {
4249         .name           = "cb_pcidas64",
4250         .id_table       = cb_pcidas64_pci_table,
4251         .probe          = cb_pcidas64_pci_probe,
4252         .remove         = comedi_pci_auto_unconfig,
4253 };
4254 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4255
4256 MODULE_AUTHOR("Comedi http://www.comedi.org");
4257 MODULE_DESCRIPTION("Comedi low-level driver");
4258 MODULE_LICENSE("GPL");