drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31 */
  32
  33 /*
  34  * Driver: cb_pcidas64
  35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  36  *   with the PLX 9080 PCI controller
  37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  38  * Status: works
  39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  49  *
  50  * Configuration options:
  51  *   None.
  52  *
  53  * Manual attachment of PCI cards with the comedi_config utility is not
  54  * supported by this driver; they are attached automatically.
  55  *
  56  * These boards may be autocalibrated with the comedi_calibrate utility.
  57  *
  58  * To select the bnc trigger input on the 4020 (instead of the dio input),
  59  * specify a nonzero channel in the chanspec.  If you wish to use an external
  60  * master clock on the 4020, you may do so by setting the scan_begin_src
  61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  62  * to configure the divisor to use for the external clock.
  63  *
  64  * Some devices are not identified because the PCI device IDs are not yet
  65  * known. If you have such a board, please let the maintainers know.
  66  */
  67
  68 /*
  69
  70 TODO:
  71         make it return error if user attempts an ai command that uses the
  72         external queue, and an ao command simultaneously user counter subdevice
  73         there are a number of boards this driver will support when they are
  74         fully released, but does not yet since the pci device id numbers
  75         are not yet available.
  76
  77         support prescaled 100khz clock for slow pacing (not available on 6000
  78         series?)
  79
  80         make ao fifo size adjustable like ai fifo
  81 */
  82
  83 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  84
  85 #include <linux/pci.h>
  86 #include <linux/delay.h>
  87 #include <linux/interrupt.h>
  88
  89 #include "../comedidev.h"
  90
  91 #include "8253.h"
  92 #include "8255.h"
  93 #include "plx9080.h"
  94 #include "comedi_fc.h"
  95
  96 #undef PCIDAS64_DEBUG           /*  disable debugging code */
  97 /* #define PCIDAS64_DEBUG         enable debugging code */
  98
  99 #ifdef PCIDAS64_DEBUG
 100 #define DEBUG_PRINT(format, args...)  pr_debug(format, ## args)
 101 #else
 102 #define DEBUG_PRINT(format, args...)  no_printk(format, ## args)
 103 #endif
 104
 105 #define TIMER_BASE 25           /*  40MHz master clock */
 106 /* 100kHz 'prescaled' clock for slow acquisition,
 107  * maybe I'll support this someday */
 108 #define PRESCALED_TIMER_BASE    10000
 109 #define DMA_BUFFER_SIZE 0x1000
 110
 111 /* maximum value that can be loaded into board's 24-bit counters*/
 112 static const int max_counter_value = 0xffffff;
 113
 114 /* PCI-DAS64xxx base addresses */
 115
 116 /* devpriv->main_iobase registers */
 117 enum write_only_registers {
 118         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 119         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 120         DAQ_SYNC_REG = 0xc,
 121         DAQ_ATRIG_LOW_4020_REG = 0xc,
 122         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 123         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 124         CALIBRATION_REG = 0x14,
 125         /*  lower 16 bits of adc sample interval counter */
 126         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 127         /*  upper 8 bits of adc sample interval counter */
 128         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 129         /*  lower 16 bits of delay interval counter */
 130         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 131         /*  upper 8 bits of delay interval counter */
 132         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 133         /*  lower 16 bits of hardware conversion/scan counter */
 134         ADC_COUNT_LOWER_REG = 0x1e,
 135         /*  upper 8 bits of hardware conversion/scan counter */
 136         ADC_COUNT_UPPER_REG = 0x20,
 137         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 138         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 139         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 140         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 141         ADC_BUFFER_CLEAR_REG = 0x2a,
 142         /*  high channel for internal queue, use adc_chan_bits() inline above */
 143         ADC_QUEUE_HIGH_REG = 0x2c,
 144         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 145         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 146         /*  lower 16 bits of dac sample interval counter */
 147         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 148         /*  upper 8 bits of dac sample interval counter */
 149         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 150         DAC_SELECT_REG = 0x60,
 151         DAC_START_REG = 0x64,
 152         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 153 };
 154
 155 static inline unsigned int dac_convert_reg(unsigned int channel)
 156 {
 157         return 0x70 + (2 * (channel & 0x1));
 158 }
 159
 160 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 161 {
 162         return 0x70 + (4 * (channel & 0x1));
 163 }
 164
 165 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 166 {
 167         return 0x72 + (4 * (channel & 0x1));
 168 }
 169
 170 enum read_only_registers {
 171         /*  hardware status register,
 172          *  reading this apparently clears pending interrupts as well */
 173         HW_STATUS_REG = 0x0,
 174         PIPE1_READ_REG = 0x4,
 175         ADC_READ_PNTR_REG = 0x8,
 176         LOWER_XFER_REG = 0x10,
 177         ADC_WRITE_PNTR_REG = 0xc,
 178         PREPOST_REG = 0x14,
 179 };
 180
 181 enum read_write_registers {
 182         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 183         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 184         ADC_QUEUE_FIFO_REG = 0x100,
 185         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 186         /* dac data fifo, has weird interactions with external channel queue */
 187         DAC_FIFO_REG = 0x300,
 188 };
 189
 190 /* devpriv->dio_counter_iobase registers */
 191 enum dio_counter_registers {
 192         DIO_8255_OFFSET = 0x0,
 193         DO_REG = 0x20,
 194         DI_REG = 0x28,
 195         DIO_DIRECTION_60XX_REG = 0x40,
 196         DIO_DATA_60XX_REG = 0x48,
 197 };
 198
 199 /* bit definitions for write-only registers */
 200
 201 enum intr_enable_contents {
 202         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 203         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 204         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 205         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 206         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 207         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 208         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 209         DAC_INTR_SRC_MASK = 0x30,
 210         DAC_INTR_QEMPTY_BITS = 0x0,
 211         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 212         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 213         EN_DAC_DONE_INTR_BIT = 0x80,
 214         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 215         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 216         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 217         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 218         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 219 };
 220
 221 enum hw_config_contents {
 222         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 223         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 224         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 225         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 226         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 227         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 228         SLOW_DAC_BIT = 0x400,
 229         /*  bit with unknown function yet given as default value in pci-das64
 230          *  manual */
 231         HW_CONFIG_DUMMY_BITS = 0x2000,
 232         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 233         DMA_CH_SELECT_BIT = 0x8000,
 234         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 235         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 236         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 237 };
 238 #define DAC_FIFO_SIZE 0x2000
 239
 240 enum daq_atrig_low_4020_contents {
 241         /*  use trig/ext clk bnc input for analog gate signal */
 242         EXT_AGATE_BNC_BIT = 0x8000,
 243         /*  use trig/ext clk bnc input for external stop trigger signal */
 244         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 245         /*  use trig/ext clk bnc input for external start trigger signal */
 246         EXT_START_TRIG_BNC_BIT = 0x2000,
 247 };
 248
 249 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 250 {
 251         return threshold & 0xfff;
 252 }
 253
 254 enum adc_control0_contents {
 255         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 256         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 257         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 258         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 259         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 260         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 261         ADC_START_TRIG_SOFT_BITS = 0x10,
 262         ADC_START_TRIG_EXT_BITS = 0x20,
 263         ADC_START_TRIG_ANALOG_BITS = 0x30,
 264         ADC_START_TRIG_MASK = 0x30,
 265         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 266         /*  external pacing uses falling edge */
 267         ADC_EXT_CONV_FALLING_BIT = 0x800,
 268         /*  enable hardware scan counter */
 269         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 270         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 271         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 272 };
 273
 274 enum adc_control1_contents {
 275         /*  should be set for boards with > 16 channels */
 276         ADC_QUEUE_CONFIG_BIT = 0x1,
 277         CONVERT_POLARITY_BIT = 0x10,
 278         EOC_POLARITY_BIT = 0x20,
 279         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 280         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 281         RETRIGGER_BIT = 0x800,
 282         ADC_LO_CHANNEL_4020_MASK = 0x300,
 283         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 284         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 285         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 286         CHANNEL_MODE_4020_MASK = 0x3000,
 287         ADC_MODE_MASK = 0xf000,
 288 };
 289
 290 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 291 {
 292         return (channel & 0x3) << 8;
 293 };
 294
 295 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 296 {
 297         return (channel & 0x3) << 10;
 298 };
 299
 300 static inline uint16_t adc_mode_bits(unsigned int mode)
 301 {
 302         return (mode & 0xf) << 12;
 303 };
 304
 305 enum calibration_contents {
 306         SELECT_8800_BIT = 0x1,
 307         SELECT_8402_64XX_BIT = 0x2,
 308         SELECT_1590_60XX_BIT = 0x2,
 309         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 310         SERIAL_DATA_IN_BIT = 0x80,
 311         SERIAL_CLOCK_BIT = 0x100,
 312         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 313         CAL_GAIN_BIT = 0x800,
 314 };
 315
 316 /* calibration sources for 6025 are:
 317  *  0 : ground
 318  *  1 : 10V
 319  *  2 : 5V
 320  *  3 : 0.5V
 321  *  4 : 0.05V
 322  *  5 : ground
 323  *  6 : dac channel 0
 324  *  7 : dac channel 1
 325  */
 326
 327 static inline uint16_t adc_src_bits(unsigned int source)
 328 {
 329         return (source & 0xf) << 3;
 330 };
 331
 332 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 333 {
 334         return (channel & 0x3) << 8;
 335 };
 336
 337 enum adc_queue_load_contents {
 338         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 339         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 340         /*  non-referenced single-ended (common-mode input) */
 341         ADC_COMMON_BIT = 0x2000,
 342         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 343         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 344 };
 345
 346 static inline uint16_t adc_chan_bits(unsigned int channel)
 347 {
 348         return channel & 0x3f;
 349 };
 350
 351 enum dac_control0_contents {
 352         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 353         DAC_CYCLIC_STOP_BIT = 0x4000,
 354         DAC_WAVEFORM_MODE_BIT = 0x100,
 355         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 356         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 357         WAVEFORM_TRIG_MASK = 0x30,
 358         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 359         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 360         WAVEFORM_TRIG_EXT_BITS = 0x20,
 361         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 362         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 363         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 364         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 365         WAVEFORM_GATE_SELECT_BIT = 0x1,
 366 };
 367
 368 enum dac_control1_contents {
 369         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 370         DAC1_EXT_REF_BIT = 0x200,
 371         DAC0_EXT_REF_BIT = 0x100,
 372         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 373         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 374         DAC_SW_GATE_BIT = 0x20,
 375         DAC1_UNIPOLAR_BIT = 0x8,
 376         DAC0_UNIPOLAR_BIT = 0x2,
 377 };
 378
 379 /* bit definitions for read-only registers */
 380 enum hw_status_contents {
 381         DAC_UNDERRUN_BIT = 0x1,
 382         ADC_OVERRUN_BIT = 0x2,
 383         DAC_ACTIVE_BIT = 0x4,
 384         ADC_ACTIVE_BIT = 0x8,
 385         DAC_INTR_PENDING_BIT = 0x10,
 386         ADC_INTR_PENDING_BIT = 0x20,
 387         DAC_DONE_BIT = 0x40,
 388         ADC_DONE_BIT = 0x80,
 389         EXT_INTR_PENDING_BIT = 0x100,
 390         ADC_STOP_BIT = 0x200,
 391 };
 392
 393 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 394 {
 395         return (hw_status_bits >> 10) & 0x3;
 396 };
 397
 398 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 399 {
 400         return (prepost_bits >> 6) & 0x3;
 401 }
 402
 403 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 404 {
 405         return (prepost_bits >> 12) & 0x3;
 406 }
 407
 408 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 409 {
 410         return (prepost_bits >> 14) & 0x3;
 411 }
 412
 413 /* I2C addresses for 4020 */
 414 enum i2c_addresses {
 415         RANGE_CAL_I2C_ADDR = 0x20,
 416         CALDAC0_I2C_ADDR = 0xc,
 417         CALDAC1_I2C_ADDR = 0xd,
 418 };
 419
 420 enum range_cal_i2c_contents {
 421         /*  bits that set what source the adc converter measures */
 422         ADC_SRC_4020_MASK = 0x70,
 423         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 424         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 425 };
 426
 427 static inline uint8_t adc_src_4020_bits(unsigned int source)
 428 {
 429         return (source << 4) & ADC_SRC_4020_MASK;
 430 };
 431
 432 static inline uint8_t attenuate_bit(unsigned int channel)
 433 {
 434         /*  attenuate channel (+-5V input range) */
 435         return 1 << (channel & 0x3);
 436 };
 437
 438 /* analog input ranges for 64xx boards */
 439 static const struct comedi_lrange ai_ranges_64xx = {
 440         8,
 441         {
 442          BIP_RANGE(10),
 443          BIP_RANGE(5),
 444          BIP_RANGE(2.5),
 445          BIP_RANGE(1.25),
 446          UNI_RANGE(10),
 447          UNI_RANGE(5),
 448          UNI_RANGE(2.5),
 449          UNI_RANGE(1.25)
 450          }
 451 };
 452
 453 /* analog input ranges for 60xx boards */
 454 static const struct comedi_lrange ai_ranges_60xx = {
 455         4,
 456         {
 457          BIP_RANGE(10),
 458          BIP_RANGE(5),
 459          BIP_RANGE(0.5),
 460          BIP_RANGE(0.05),
 461          }
 462 };
 463
 464 /* analog input ranges for 6030, etc boards */
 465 static const struct comedi_lrange ai_ranges_6030 = {
 466         14,
 467         {
 468          BIP_RANGE(10),
 469          BIP_RANGE(5),
 470          BIP_RANGE(2),
 471          BIP_RANGE(1),
 472          BIP_RANGE(0.5),
 473          BIP_RANGE(0.2),
 474          BIP_RANGE(0.1),
 475          UNI_RANGE(10),
 476          UNI_RANGE(5),
 477          UNI_RANGE(2),
 478          UNI_RANGE(1),
 479          UNI_RANGE(0.5),
 480          UNI_RANGE(0.2),
 481          UNI_RANGE(0.1),
 482          }
 483 };
 484
 485 /* analog input ranges for 6052, etc boards */
 486 static const struct comedi_lrange ai_ranges_6052 = {
 487         15,
 488         {
 489          BIP_RANGE(10),
 490          BIP_RANGE(5),
 491          BIP_RANGE(2.5),
 492          BIP_RANGE(1),
 493          BIP_RANGE(0.5),
 494          BIP_RANGE(0.25),
 495          BIP_RANGE(0.1),
 496          BIP_RANGE(0.05),
 497          UNI_RANGE(10),
 498          UNI_RANGE(5),
 499          UNI_RANGE(2),
 500          UNI_RANGE(1),
 501          UNI_RANGE(0.5),
 502          UNI_RANGE(0.2),
 503          UNI_RANGE(0.1),
 504          }
 505 };
 506
 507 /* analog input ranges for 4020 board */
 508 static const struct comedi_lrange ai_ranges_4020 = {
 509         2,
 510         {
 511          BIP_RANGE(5),
 512          BIP_RANGE(1),
 513          }
 514 };
 515
 516 /* analog output ranges */
 517 static const struct comedi_lrange ao_ranges_64xx = {
 518         4,
 519         {
 520          BIP_RANGE(5),
 521          BIP_RANGE(10),
 522          UNI_RANGE(5),
 523          UNI_RANGE(10),
 524          }
 525 };
 526
 527 static const int ao_range_code_64xx[] = {
 528         0x0,
 529         0x1,
 530         0x2,
 531         0x3,
 532 };
 533
 534 static const int ao_range_code_60xx[] = {
 535         0x0,
 536 };
 537
 538 static const struct comedi_lrange ao_ranges_6030 = {
 539         2,
 540         {
 541          BIP_RANGE(10),
 542          UNI_RANGE(10),
 543          }
 544 };
 545
 546 static const int ao_range_code_6030[] = {
 547         0x0,
 548         0x2,
 549 };
 550
 551 static const struct comedi_lrange ao_ranges_4020 = {
 552         2,
 553         {
 554          BIP_RANGE(5),
 555          BIP_RANGE(10),
 556          }
 557 };
 558
 559 static const int ao_range_code_4020[] = {
 560         0x1,
 561         0x0,
 562 };
 563
 564 enum register_layout {
 565         LAYOUT_60XX,
 566         LAYOUT_64XX,
 567         LAYOUT_4020,
 568 };
 569
 570 struct hw_fifo_info {
 571         unsigned int num_segments;
 572         unsigned int max_segment_length;
 573         unsigned int sample_packing_ratio;
 574         uint16_t fifo_size_reg_mask;
 575 };
 576
 577 enum pcidas64_boardid {
 578         BOARD_PCIDAS6402_16,
 579         BOARD_PCIDAS6402_12,
 580         BOARD_PCIDAS64_M1_16,
 581         BOARD_PCIDAS64_M2_16,
 582         BOARD_PCIDAS64_M3_16,
 583         BOARD_PCIDAS6013,
 584         BOARD_PCIDAS6014,
 585         BOARD_PCIDAS6023,
 586         BOARD_PCIDAS6025,
 587         BOARD_PCIDAS6030,
 588         BOARD_PCIDAS6031,
 589         BOARD_PCIDAS6032,
 590         BOARD_PCIDAS6033,
 591         BOARD_PCIDAS6034,
 592         BOARD_PCIDAS6035,
 593         BOARD_PCIDAS6036,
 594         BOARD_PCIDAS6040,
 595         BOARD_PCIDAS6052,
 596         BOARD_PCIDAS6070,
 597         BOARD_PCIDAS6071,
 598         BOARD_PCIDAS4020_12,
 599         BOARD_PCIDAS6402_16_JR,
 600         BOARD_PCIDAS64_M1_16_JR,
 601         BOARD_PCIDAS64_M2_16_JR,
 602         BOARD_PCIDAS64_M3_16_JR,
 603         BOARD_PCIDAS64_M1_14,
 604         BOARD_PCIDAS64_M2_14,
 605         BOARD_PCIDAS64_M3_14,
 606 };
 607
 608 struct pcidas64_board {
 609         const char *name;
 610         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 611         int ai_bits;            /*  analog input resolution */
 612         int ai_speed;           /*  fastest conversion period in ns */
 613         const struct comedi_lrange *ai_range_table;
 614         int ao_nchan;           /*  number of analog out channels */
 615         int ao_bits;            /*  analog output resolution */
 616         int ao_scan_speed;      /*  analog output scan speed */
 617         const struct comedi_lrange *ao_range_table;
 618         const int *ao_range_code;
 619         const struct hw_fifo_info *const ai_fifo;
 620         /*  different board families have slightly different registers */
 621         enum register_layout layout;
 622         unsigned has_8255:1;
 623 };
 624
 625 static const struct hw_fifo_info ai_fifo_4020 = {
 626         .num_segments = 2,
 627         .max_segment_length = 0x8000,
 628         .sample_packing_ratio = 2,
 629         .fifo_size_reg_mask = 0x7f,
 630 };
 631
 632 static const struct hw_fifo_info ai_fifo_64xx = {
 633         .num_segments = 4,
 634         .max_segment_length = 0x800,
 635         .sample_packing_ratio = 1,
 636         .fifo_size_reg_mask = 0x3f,
 637 };
 638
 639 static const struct hw_fifo_info ai_fifo_60xx = {
 640         .num_segments = 4,
 641         .max_segment_length = 0x800,
 642         .sample_packing_ratio = 1,
 643         .fifo_size_reg_mask = 0x7f,
 644 };
 645
 646 /* maximum number of dma transfers we will chain together into a ring
 647  * (and the maximum number of dma buffers we maintain) */
 648 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 649 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 650 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 651 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 652 {
 653         if (board->layout == LAYOUT_4020)
 654                 return MAX_AI_DMA_RING_COUNT;
 655         else
 656                 return MIN_AI_DMA_RING_COUNT;
 657 }
 658
 659 static const int bytes_in_sample = 2;
 660
 661 static const struct pcidas64_board pcidas64_boards[] = {
 662         [BOARD_PCIDAS6402_16] = {
 663                 .name           = "pci-das6402/16",
 664                 .ai_se_chans    = 64,
 665                 .ai_bits        = 16,
 666                 .ai_speed       = 5000,
 667                 .ao_nchan       = 2,
 668                 .ao_bits        = 16,
 669                 .ao_scan_speed  = 10000,
 670                 .layout         = LAYOUT_64XX,
 671                 .ai_range_table = &ai_ranges_64xx,
 672                 .ao_range_table = &ao_ranges_64xx,
 673                 .ao_range_code  = ao_range_code_64xx,
 674                 .ai_fifo        = &ai_fifo_64xx,
 675                 .has_8255       = 1,
 676         },
 677         [BOARD_PCIDAS6402_12] = {
 678                 .name           = "pci-das6402/12",     /*  XXX check */
 679                 .ai_se_chans    = 64,
 680                 .ai_bits        = 12,
 681                 .ai_speed       = 5000,
 682                 .ao_nchan       = 2,
 683                 .ao_bits        = 12,
 684                 .ao_scan_speed  = 10000,
 685                 .layout         = LAYOUT_64XX,
 686                 .ai_range_table = &ai_ranges_64xx,
 687                 .ao_range_table = &ao_ranges_64xx,
 688                 .ao_range_code  = ao_range_code_64xx,
 689                 .ai_fifo        = &ai_fifo_64xx,
 690                 .has_8255       = 1,
 691         },
 692         [BOARD_PCIDAS64_M1_16] = {
 693                 .name           = "pci-das64/m1/16",
 694                 .ai_se_chans    = 64,
 695                 .ai_bits        = 16,
 696                 .ai_speed       = 1000,
 697                 .ao_nchan       = 2,
 698                 .ao_bits        = 16,
 699                 .ao_scan_speed  = 10000,
 700                 .layout         = LAYOUT_64XX,
 701                 .ai_range_table = &ai_ranges_64xx,
 702                 .ao_range_table = &ao_ranges_64xx,
 703                 .ao_range_code  = ao_range_code_64xx,
 704                 .ai_fifo        = &ai_fifo_64xx,
 705                 .has_8255       = 1,
 706         },
 707         [BOARD_PCIDAS64_M2_16] = {
 708                 .name = "pci-das64/m2/16",
 709                 .ai_se_chans    = 64,
 710                 .ai_bits        = 16,
 711                 .ai_speed       = 500,
 712                 .ao_nchan       = 2,
 713                 .ao_bits        = 16,
 714                 .ao_scan_speed  = 10000,
 715                 .layout         = LAYOUT_64XX,
 716                 .ai_range_table = &ai_ranges_64xx,
 717                 .ao_range_table = &ao_ranges_64xx,
 718                 .ao_range_code  = ao_range_code_64xx,
 719                 .ai_fifo        = &ai_fifo_64xx,
 720                 .has_8255       = 1,
 721         },
 722         [BOARD_PCIDAS64_M3_16] = {
 723                 .name           = "pci-das64/m3/16",
 724                 .ai_se_chans    = 64,
 725                 .ai_bits        = 16,
 726                 .ai_speed       = 333,
 727                 .ao_nchan       = 2,
 728                 .ao_bits        = 16,
 729                 .ao_scan_speed  = 10000,
 730                 .layout         = LAYOUT_64XX,
 731                 .ai_range_table = &ai_ranges_64xx,
 732                 .ao_range_table = &ao_ranges_64xx,
 733                 .ao_range_code  = ao_range_code_64xx,
 734                 .ai_fifo        = &ai_fifo_64xx,
 735                 .has_8255       = 1,
 736         },
 737         [BOARD_PCIDAS6013] = {
 738                 .name           = "pci-das6013",
 739                 .ai_se_chans    = 16,
 740                 .ai_bits        = 16,
 741                 .ai_speed       = 5000,
 742                 .ao_nchan       = 0,
 743                 .ao_bits        = 16,
 744                 .layout         = LAYOUT_60XX,
 745                 .ai_range_table = &ai_ranges_60xx,
 746                 .ao_range_table = &range_bipolar10,
 747                 .ao_range_code  = ao_range_code_60xx,
 748                 .ai_fifo        = &ai_fifo_60xx,
 749                 .has_8255       = 0,
 750         },
 751         [BOARD_PCIDAS6014] = {
 752                 .name           = "pci-das6014",
 753                 .ai_se_chans    = 16,
 754                 .ai_bits        = 16,
 755                 .ai_speed       = 5000,
 756                 .ao_nchan       = 2,
 757                 .ao_bits        = 16,
 758                 .ao_scan_speed  = 100000,
 759                 .layout         = LAYOUT_60XX,
 760                 .ai_range_table = &ai_ranges_60xx,
 761                 .ao_range_table = &range_bipolar10,
 762                 .ao_range_code  = ao_range_code_60xx,
 763                 .ai_fifo        = &ai_fifo_60xx,
 764                 .has_8255       = 0,
 765         },
 766         [BOARD_PCIDAS6023] = {
 767                 .name           = "pci-das6023",
 768                 .ai_se_chans    = 16,
 769                 .ai_bits        = 12,
 770                 .ai_speed       = 5000,
 771                 .ao_nchan       = 0,
 772                 .ao_scan_speed  = 100000,
 773                 .layout         = LAYOUT_60XX,
 774                 .ai_range_table = &ai_ranges_60xx,
 775                 .ao_range_table = &range_bipolar10,
 776                 .ao_range_code  = ao_range_code_60xx,
 777                 .ai_fifo        = &ai_fifo_60xx,
 778                 .has_8255       = 1,
 779         },
 780         [BOARD_PCIDAS6025] = {
 781                 .name           = "pci-das6025",
 782                 .ai_se_chans    = 16,
 783                 .ai_bits        = 12,
 784                 .ai_speed       = 5000,
 785                 .ao_nchan       = 2,
 786                 .ao_bits        = 12,
 787                 .ao_scan_speed  = 100000,
 788                 .layout         = LAYOUT_60XX,
 789                 .ai_range_table = &ai_ranges_60xx,
 790                 .ao_range_table = &range_bipolar10,
 791                 .ao_range_code  = ao_range_code_60xx,
 792                 .ai_fifo        = &ai_fifo_60xx,
 793                 .has_8255       = 1,
 794         },
 795         [BOARD_PCIDAS6030] = {
 796                 .name           = "pci-das6030",
 797                 .ai_se_chans    = 16,
 798                 .ai_bits        = 16,
 799                 .ai_speed       = 10000,
 800                 .ao_nchan       = 2,
 801                 .ao_bits        = 16,
 802                 .ao_scan_speed  = 10000,
 803                 .layout         = LAYOUT_60XX,
 804                 .ai_range_table = &ai_ranges_6030,
 805                 .ao_range_table = &ao_ranges_6030,
 806                 .ao_range_code  = ao_range_code_6030,
 807                 .ai_fifo        = &ai_fifo_60xx,
 808                 .has_8255       = 0,
 809         },
 810         [BOARD_PCIDAS6031] = {
 811                 .name           = "pci-das6031",
 812                 .ai_se_chans    = 64,
 813                 .ai_bits        = 16,
 814                 .ai_speed       = 10000,
 815                 .ao_nchan       = 2,
 816                 .ao_bits        = 16,
 817                 .ao_scan_speed  = 10000,
 818                 .layout         = LAYOUT_60XX,
 819                 .ai_range_table = &ai_ranges_6030,
 820                 .ao_range_table = &ao_ranges_6030,
 821                 .ao_range_code  = ao_range_code_6030,
 822                 .ai_fifo        = &ai_fifo_60xx,
 823                 .has_8255       = 0,
 824         },
 825         [BOARD_PCIDAS6032] = {
 826                 .name           = "pci-das6032",
 827                 .ai_se_chans    = 16,
 828                 .ai_bits        = 16,
 829                 .ai_speed       = 10000,
 830                 .ao_nchan       = 0,
 831                 .layout         = LAYOUT_60XX,
 832                 .ai_range_table = &ai_ranges_6030,
 833                 .ai_fifo        = &ai_fifo_60xx,
 834                 .has_8255       = 0,
 835         },
 836         [BOARD_PCIDAS6033] = {
 837                 .name           = "pci-das6033",
 838                 .ai_se_chans    = 64,
 839                 .ai_bits        = 16,
 840                 .ai_speed       = 10000,
 841                 .ao_nchan       = 0,
 842                 .layout         = LAYOUT_60XX,
 843                 .ai_range_table = &ai_ranges_6030,
 844                 .ai_fifo        = &ai_fifo_60xx,
 845                 .has_8255       = 0,
 846         },
 847         [BOARD_PCIDAS6034] = {
 848                 .name           = "pci-das6034",
 849                 .ai_se_chans    = 16,
 850                 .ai_bits        = 16,
 851                 .ai_speed       = 5000,
 852                 .ao_nchan       = 0,
 853                 .ao_scan_speed  = 0,
 854                 .layout         = LAYOUT_60XX,
 855                 .ai_range_table = &ai_ranges_60xx,
 856                 .ai_fifo        = &ai_fifo_60xx,
 857                 .has_8255       = 0,
 858         },
 859         [BOARD_PCIDAS6035] = {
 860                 .name           = "pci-das6035",
 861                 .ai_se_chans    = 16,
 862                 .ai_bits        = 16,
 863                 .ai_speed       = 5000,
 864                 .ao_nchan       = 2,
 865                 .ao_bits        = 12,
 866                 .ao_scan_speed  = 100000,
 867                 .layout         = LAYOUT_60XX,
 868                 .ai_range_table = &ai_ranges_60xx,
 869                 .ao_range_table = &range_bipolar10,
 870                 .ao_range_code  = ao_range_code_60xx,
 871                 .ai_fifo        = &ai_fifo_60xx,
 872                 .has_8255       = 0,
 873         },
 874         [BOARD_PCIDAS6036] = {
 875                 .name           = "pci-das6036",
 876                 .ai_se_chans    = 16,
 877                 .ai_bits        = 16,
 878                 .ai_speed       = 5000,
 879                 .ao_nchan       = 2,
 880                 .ao_bits        = 16,
 881                 .ao_scan_speed  = 100000,
 882                 .layout         = LAYOUT_60XX,
 883                 .ai_range_table = &ai_ranges_60xx,
 884                 .ao_range_table = &range_bipolar10,
 885                 .ao_range_code  = ao_range_code_60xx,
 886                 .ai_fifo        = &ai_fifo_60xx,
 887                 .has_8255       = 0,
 888         },
 889         [BOARD_PCIDAS6040] = {
 890                 .name           = "pci-das6040",
 891                 .ai_se_chans    = 16,
 892                 .ai_bits        = 12,
 893                 .ai_speed       = 2000,
 894                 .ao_nchan       = 2,
 895                 .ao_bits        = 12,
 896                 .ao_scan_speed  = 1000,
 897                 .layout         = LAYOUT_60XX,
 898                 .ai_range_table = &ai_ranges_6052,
 899                 .ao_range_table = &ao_ranges_6030,
 900                 .ao_range_code  = ao_range_code_6030,
 901                 .ai_fifo        = &ai_fifo_60xx,
 902                 .has_8255       = 0,
 903         },
 904         [BOARD_PCIDAS6052] = {
 905                 .name           = "pci-das6052",
 906                 .ai_se_chans    = 16,
 907                 .ai_bits        = 16,
 908                 .ai_speed       = 3333,
 909                 .ao_nchan       = 2,
 910                 .ao_bits        = 16,
 911                 .ao_scan_speed  = 3333,
 912                 .layout         = LAYOUT_60XX,
 913                 .ai_range_table = &ai_ranges_6052,
 914                 .ao_range_table = &ao_ranges_6030,
 915                 .ao_range_code  = ao_range_code_6030,
 916                 .ai_fifo        = &ai_fifo_60xx,
 917                 .has_8255       = 0,
 918         },
 919         [BOARD_PCIDAS6070] = {
 920                 .name           = "pci-das6070",
 921                 .ai_se_chans    = 16,
 922                 .ai_bits        = 12,
 923                 .ai_speed       = 800,
 924                 .ao_nchan       = 2,
 925                 .ao_bits        = 12,
 926                 .ao_scan_speed  = 1000,
 927                 .layout         = LAYOUT_60XX,
 928                 .ai_range_table = &ai_ranges_6052,
 929                 .ao_range_table = &ao_ranges_6030,
 930                 .ao_range_code  = ao_range_code_6030,
 931                 .ai_fifo        = &ai_fifo_60xx,
 932                 .has_8255       = 0,
 933         },
 934         [BOARD_PCIDAS6071] = {
 935                 .name           = "pci-das6071",
 936                 .ai_se_chans    = 64,
 937                 .ai_bits        = 12,
 938                 .ai_speed       = 800,
 939                 .ao_nchan       = 2,
 940                 .ao_bits        = 12,
 941                 .ao_scan_speed  = 1000,
 942                 .layout         = LAYOUT_60XX,
 943                 .ai_range_table = &ai_ranges_6052,
 944                 .ao_range_table = &ao_ranges_6030,
 945                 .ao_range_code  = ao_range_code_6030,
 946                 .ai_fifo        = &ai_fifo_60xx,
 947                 .has_8255       = 0,
 948         },
 949         [BOARD_PCIDAS4020_12] = {
 950                 .name           = "pci-das4020/12",
 951                 .ai_se_chans    = 4,
 952                 .ai_bits        = 12,
 953                 .ai_speed       = 50,
 954                 .ao_bits        = 12,
 955                 .ao_nchan       = 2,
 956                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
 957                 .layout         = LAYOUT_4020,
 958                 .ai_range_table = &ai_ranges_4020,
 959                 .ao_range_table = &ao_ranges_4020,
 960                 .ao_range_code  = ao_range_code_4020,
 961                 .ai_fifo        = &ai_fifo_4020,
 962                 .has_8255       = 1,
 963         },
 964 #if 0
 965         /*
 966          * The device id for these boards is unknown
 967          */
 968
 969         [BOARD_PCIDAS6402_16_JR] = {
 970                 .name           = "pci-das6402/16/jr",
 971                 .ai_se_chans    = 64,
 972                 .ai_bits        = 16,
 973                 .ai_speed       = 5000,
 974                 .ao_nchan       = 0,
 975                 .ao_scan_speed  = 10000,
 976                 .layout         = LAYOUT_64XX,
 977                 .ai_range_table = &ai_ranges_64xx,
 978                 .ai_fifo        = ai_fifo_64xx,
 979                 .has_8255       = 1,
 980         },
 981         [BOARD_PCIDAS64_M1_16_JR] = {
 982                 .name           = "pci-das64/m1/16/jr",
 983                 .ai_se_chans    = 64,
 984                 .ai_bits        = 16,
 985                 .ai_speed       = 1000,
 986                 .ao_nchan       = 0,
 987                 .ao_scan_speed  = 10000,
 988                 .layout         = LAYOUT_64XX,
 989                 .ai_range_table = &ai_ranges_64xx,
 990                 .ai_fifo        = ai_fifo_64xx,
 991                 .has_8255       = 1,
 992         },
 993         [BOARD_PCIDAS64_M2_16_JR] = {
 994                 .name = "pci-das64/m2/16/jr",
 995                 .ai_se_chans    = 64,
 996                 .ai_bits        = 16,
 997                 .ai_speed       = 500,
 998                 .ao_nchan       = 0,
 999                 .ao_scan_speed  = 10000,
1000                 .layout         = LAYOUT_64XX,
1001                 .ai_range_table = &ai_ranges_64xx,
1002                 .ai_fifo        = ai_fifo_64xx,
1003                 .has_8255       = 1,
1004         },
1005         [BOARD_PCIDAS64_M3_16_JR] = {
1006                 .name           = "pci-das64/m3/16/jr",
1007                 .ai_se_chans    = 64,
1008                 .ai_bits        = 16,
1009                 .ai_speed       = 333,
1010                 .ao_nchan       = 0,
1011                 .ao_scan_speed  = 10000,
1012                 .layout         = LAYOUT_64XX,
1013                 .ai_range_table = &ai_ranges_64xx,
1014                 .ai_fifo        = ai_fifo_64xx,
1015                 .has_8255       = 1,
1016         },
1017         [BOARD_PCIDAS64_M1_14] = {
1018                 .name           = "pci-das64/m1/14",
1019                 .ai_se_chans    = 64,
1020                 .ai_bits        = 14,
1021                 .ai_speed       = 1000,
1022                 .ao_nchan       = 2,
1023                 .ao_scan_speed  = 10000,
1024                 .layout         = LAYOUT_64XX,
1025                 .ai_range_table = &ai_ranges_64xx,
1026                 .ai_fifo        = ai_fifo_64xx,
1027                 .has_8255       = 1,
1028         },
1029         [BOARD_PCIDAS64_M2_14] = {
1030                 .name           = "pci-das64/m2/14",
1031                 .ai_se_chans    = 64,
1032                 .ai_bits        = 14,
1033                 .ai_speed       = 500,
1034                 .ao_nchan       = 2,
1035                 .ao_scan_speed  = 10000,
1036                 .layout         = LAYOUT_64XX,
1037                 .ai_range_table = &ai_ranges_64xx,
1038                 .ai_fifo        = ai_fifo_64xx,
1039                 .has_8255       = 1,
1040         },
1041         [BOARD_PCIDAS64_M3_14] = {
1042                 .name           = "pci-das64/m3/14",
1043                 .ai_se_chans    = 64,
1044                 .ai_bits        = 14,
1045                 .ai_speed       = 333,
1046                 .ao_nchan       = 2,
1047                 .ao_scan_speed  = 10000,
1048                 .layout         = LAYOUT_64XX,
1049                 .ai_range_table = &ai_ranges_64xx,
1050                 .ai_fifo        = ai_fifo_64xx,
1051                 .has_8255       = 1,
1052         },
1053 #endif
1054 };
1055
1056 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1057                                               int use_differential)
1058 {
1059         const struct pcidas64_board *thisboard = comedi_board(dev);
1060
1061         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1062             (thisboard->layout == LAYOUT_60XX && use_differential))
1063                 return ADC_SE_DIFF_BIT;
1064         else
1065                 return 0;
1066 };
1067
1068 struct ext_clock_info {
1069         /*  master clock divisor to use for scans with external master clock */
1070         unsigned int divisor;
1071         /*  chanspec for master clock input when used as scan begin src */
1072         unsigned int chanspec;
1073 };
1074
1075 /* this structure is for data unique to this hardware driver. */
1076 struct pcidas64_private {
1077         /*  base addresses (physical) */
1078         resource_size_t main_phys_iobase;
1079         resource_size_t dio_counter_phys_iobase;
1080         /*  base addresses (ioremapped) */
1081         void __iomem *plx9080_iobase;
1082         void __iomem *main_iobase;
1083         void __iomem *dio_counter_iobase;
1084         /*  local address (used by dma controller) */
1085         uint32_t local0_iobase;
1086         uint32_t local1_iobase;
1087         /*  number of analog input samples remaining */
1088         volatile unsigned int ai_count;
1089         /*  dma buffers for analog input */
1090         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1091         /*  physical addresses of ai dma buffers */
1092         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1093         /*  array of ai dma descriptors read by plx9080,
1094          *  allocated to get proper alignment */
1095         struct plx_dma_desc *ai_dma_desc;
1096         /*  physical address of ai dma descriptor array */
1097         dma_addr_t ai_dma_desc_bus_addr;
1098         /*  index of the ai dma descriptor/buffer
1099          *  that is currently being used */
1100         volatile unsigned int ai_dma_index;
1101         /*  dma buffers for analog output */
1102         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1103         /*  physical addresses of ao dma buffers */
1104         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1105         struct plx_dma_desc *ao_dma_desc;
1106         dma_addr_t ao_dma_desc_bus_addr;
1107         /*  keeps track of buffer where the next ao sample should go */
1108         volatile unsigned int ao_dma_index;
1109         /*  number of analog output samples remaining */
1110         volatile unsigned long ao_count;
1111         /*  remember what the analog outputs are set to, to allow readback */
1112         volatile unsigned int ao_value[2];
1113         unsigned int hw_revision;       /*  stc chip hardware revision number */
1114         /*  last bits sent to INTR_ENABLE_REG register */
1115         volatile unsigned int intr_enable_bits;
1116         /*  last bits sent to ADC_CONTROL1_REG register */
1117         volatile uint16_t adc_control1_bits;
1118         /*  last bits sent to FIFO_SIZE_REG register */
1119         volatile uint16_t fifo_size_bits;
1120         /*  last bits sent to HW_CONFIG_REG register */
1121         volatile uint16_t hw_config_bits;
1122         volatile uint16_t dac_control1_bits;
1123         /*  last bits written to plx9080 control register */
1124         volatile uint32_t plx_control_bits;
1125         /*  last bits written to plx interrupt control and status register */
1126         volatile uint32_t plx_intcsr_bits;
1127         /*  index of calibration source readable through ai ch0 */
1128         volatile int calibration_source;
1129         /*  bits written to i2c calibration/range register */
1130         volatile uint8_t i2c_cal_range_bits;
1131         /*  configure digital triggers to trigger on falling edge */
1132         volatile unsigned int ext_trig_falling;
1133         /*  states of various devices stored to enable read-back */
1134         unsigned int ad8402_state[2];
1135         unsigned int caldac_state[8];
1136         volatile short ai_cmd_running;
1137         unsigned int ai_fifo_segment_length;
1138         struct ext_clock_info ext_clock;
1139         short ao_bounce_buffer[DAC_FIFO_SIZE];
1140 };
1141
1142 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1143                                        unsigned int range_index)
1144 {
1145         const struct pcidas64_board *thisboard = comedi_board(dev);
1146         const struct comedi_krange *range =
1147                 &thisboard->ai_range_table->range[range_index];
1148         unsigned int bits = 0;
1149
1150         switch (range->max) {
1151         case 10000000:
1152                 bits = 0x000;
1153                 break;
1154         case 5000000:
1155                 bits = 0x100;
1156                 break;
1157         case 2000000:
1158         case 2500000:
1159                 bits = 0x200;
1160                 break;
1161         case 1000000:
1162         case 1250000:
1163                 bits = 0x300;
1164                 break;
1165         case 500000:
1166                 bits = 0x400;
1167                 break;
1168         case 200000:
1169         case 250000:
1170                 bits = 0x500;
1171                 break;
1172         case 100000:
1173                 bits = 0x600;
1174                 break;
1175         case 50000:
1176                 bits = 0x700;
1177                 break;
1178         default:
1179                 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1180                 break;
1181         }
1182         if (range->min == 0)
1183                 bits += 0x900;
1184         return bits;
1185 }
1186
1187 static unsigned int hw_revision(const struct comedi_device *dev,
1188                                 uint16_t hw_status_bits)
1189 {
1190         const struct pcidas64_board *thisboard = comedi_board(dev);
1191
1192         if (thisboard->layout == LAYOUT_4020)
1193                 return (hw_status_bits >> 13) & 0x7;
1194
1195         return (hw_status_bits >> 12) & 0xf;
1196 }
1197
1198 static void set_dac_range_bits(struct comedi_device *dev,
1199                                volatile uint16_t *bits, unsigned int channel,
1200                                unsigned int range)
1201 {
1202         const struct pcidas64_board *thisboard = comedi_board(dev);
1203         unsigned int code = thisboard->ao_range_code[range];
1204
1205         if (channel > 1)
1206                 comedi_error(dev, "bug! bad channel?");
1207         if (code & ~0x3)
1208                 comedi_error(dev, "bug! bad range code?");
1209
1210         *bits &= ~(0x3 << (2 * channel));
1211         *bits |= code << (2 * channel);
1212 };
1213
1214 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1215 {
1216         return board->ao_nchan && board->layout != LAYOUT_4020;
1217 }
1218
1219 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1220 {
1221         struct pcidas64_private *devpriv = dev->private;
1222         unsigned long flags;
1223
1224         /*  spinlock for plx dma control/status reg */
1225         spin_lock_irqsave(&dev->spinlock, flags);
1226
1227         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1228
1229         spin_unlock_irqrestore(&dev->spinlock, flags);
1230 }
1231
1232 static void disable_plx_interrupts(struct comedi_device *dev)
1233 {
1234         struct pcidas64_private *devpriv = dev->private;
1235
1236         devpriv->plx_intcsr_bits = 0;
1237         writel(devpriv->plx_intcsr_bits,
1238                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1239 }
1240
1241 static void disable_ai_interrupts(struct comedi_device *dev)
1242 {
1243         struct pcidas64_private *devpriv = dev->private;
1244         unsigned long flags;
1245
1246         spin_lock_irqsave(&dev->spinlock, flags);
1247         devpriv->intr_enable_bits &=
1248                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1249                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1250                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1251         writew(devpriv->intr_enable_bits,
1252                devpriv->main_iobase + INTR_ENABLE_REG);
1253         spin_unlock_irqrestore(&dev->spinlock, flags);
1254
1255         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1256 }
1257
1258 static void enable_ai_interrupts(struct comedi_device *dev,
1259                                  const struct comedi_cmd *cmd)
1260 {
1261         const struct pcidas64_board *thisboard = comedi_board(dev);
1262         struct pcidas64_private *devpriv = dev->private;
1263         uint32_t bits;
1264         unsigned long flags;
1265
1266         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1267                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1268         /*  Use pio transfer and interrupt on end of conversion
1269          *  if TRIG_WAKE_EOS flag is set. */
1270         if (cmd->flags & TRIG_WAKE_EOS) {
1271                 /*  4020 doesn't support pio transfers except for fifo dregs */
1272                 if (thisboard->layout != LAYOUT_4020)
1273                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1274         }
1275         spin_lock_irqsave(&dev->spinlock, flags);
1276         devpriv->intr_enable_bits |= bits;
1277         writew(devpriv->intr_enable_bits,
1278                devpriv->main_iobase + INTR_ENABLE_REG);
1279         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1280         spin_unlock_irqrestore(&dev->spinlock, flags);
1281 }
1282
1283 /* initialize plx9080 chip */
1284 static void init_plx9080(struct comedi_device *dev)
1285 {
1286         const struct pcidas64_board *thisboard = comedi_board(dev);
1287         struct pcidas64_private *devpriv = dev->private;
1288         uint32_t bits;
1289         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1290
1291         devpriv->plx_control_bits =
1292                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1293
1294         /*  plx9080 dump */
1295         DEBUG_PRINT(" plx interrupt status 0x%x\n",
1296                     readl(plx_iobase + PLX_INTRCS_REG));
1297         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1298         DEBUG_PRINT(" plx control reg 0x%x\n", devpriv->plx_control_bits);
1299         DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1300                     readl(plx_iobase + PLX_MARB_REG));
1301         DEBUG_PRINT(" plx region0 reg 0x%x\n",
1302                     readl(plx_iobase + PLX_REGION0_REG));
1303         DEBUG_PRINT(" plx region1 reg 0x%x\n",
1304                     readl(plx_iobase + PLX_REGION1_REG));
1305
1306         DEBUG_PRINT(" plx revision 0x%x\n",
1307                     readl(plx_iobase + PLX_REVISION_REG));
1308         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1309                     readl(plx_iobase + PLX_DMA0_MODE_REG));
1310         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1311                     readl(plx_iobase + PLX_DMA1_MODE_REG));
1312         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1313                     readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1314         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1315                     readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1316         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1317                     readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1318         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1319                     readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1320         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1321                     readb(plx_iobase + PLX_DMA0_CS_REG));
1322         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1323                     readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1324         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1325
1326 #ifdef __BIG_ENDIAN
1327         bits = BIGEND_DMA0 | BIGEND_DMA1;
1328 #else
1329         bits = 0;
1330 #endif
1331         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1332
1333         disable_plx_interrupts(dev);
1334
1335         abort_dma(dev, 0);
1336         abort_dma(dev, 1);
1337
1338         /*  configure dma0 mode */
1339         bits = 0;
1340         /*  enable ready input, not sure if this is necessary */
1341         bits |= PLX_DMA_EN_READYIN_BIT;
1342         /*  enable bterm, not sure if this is necessary */
1343         bits |= PLX_EN_BTERM_BIT;
1344         /*  enable dma chaining */
1345         bits |= PLX_EN_CHAIN_BIT;
1346         /*  enable interrupt on dma done
1347          *  (probably don't need this, since chain never finishes) */
1348         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1349         /*  don't increment local address during transfers
1350          *  (we are transferring from a fixed fifo register) */
1351         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1352         /*  route dma interrupt to pci bus */
1353         bits |= PLX_DMA_INTR_PCI_BIT;
1354         /*  enable demand mode */
1355         bits |= PLX_DEMAND_MODE_BIT;
1356         /*  enable local burst mode */
1357         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1358         /*  4020 uses 32 bit dma */
1359         if (thisboard->layout == LAYOUT_4020)
1360                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1361         else            /*  localspace0 bus is 16 bits wide */
1362                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1363         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1364         if (ao_cmd_is_supported(thisboard))
1365                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1366
1367         /*  enable interrupts on plx 9080 */
1368         devpriv->plx_intcsr_bits |=
1369             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1370             ICS_DMA0_E | ICS_DMA1_E;
1371         writel(devpriv->plx_intcsr_bits,
1372                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1373 }
1374
1375 static void disable_ai_pacing(struct comedi_device *dev)
1376 {
1377         struct pcidas64_private *devpriv = dev->private;
1378         unsigned long flags;
1379
1380         disable_ai_interrupts(dev);
1381
1382         spin_lock_irqsave(&dev->spinlock, flags);
1383         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1384         writew(devpriv->adc_control1_bits,
1385                devpriv->main_iobase + ADC_CONTROL1_REG);
1386         spin_unlock_irqrestore(&dev->spinlock, flags);
1387
1388         /* disable pacing, triggering, etc */
1389         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1390                devpriv->main_iobase + ADC_CONTROL0_REG);
1391 }
1392
1393 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1394                                       unsigned int num_entries)
1395 {
1396         const struct pcidas64_board *thisboard = comedi_board(dev);
1397         struct pcidas64_private *devpriv = dev->private;
1398         static const int increment_size = 0x100;
1399         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1400         unsigned int num_increments;
1401         uint16_t bits;
1402
1403         if (num_entries < increment_size)
1404                 num_entries = increment_size;
1405         if (num_entries > fifo->max_segment_length)
1406                 num_entries = fifo->max_segment_length;
1407
1408         /*  1 == 256 entries, 2 == 512 entries, etc */
1409         num_increments = (num_entries + increment_size / 2) / increment_size;
1410
1411         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1412         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1413         devpriv->fifo_size_bits |= bits;
1414         writew(devpriv->fifo_size_bits,
1415                devpriv->main_iobase + FIFO_SIZE_REG);
1416
1417         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1418
1419         DEBUG_PRINT("set hardware fifo segment length to %i\n",
1420                     devpriv->ai_fifo_segment_length);
1421
1422         return devpriv->ai_fifo_segment_length;
1423 }
1424
1425 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1426 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1427 {
1428         const struct pcidas64_board *thisboard = comedi_board(dev);
1429         unsigned int num_fifo_entries;
1430         int retval;
1431         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1432
1433         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1434
1435         retval = set_ai_fifo_segment_length(dev,
1436                                             num_fifo_entries /
1437                                             fifo->num_segments);
1438         if (retval < 0)
1439                 return retval;
1440
1441         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1442
1443         DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
1444
1445         return num_samples;
1446 }
1447
1448 /* query length of fifo */
1449 static unsigned int ai_fifo_size(struct comedi_device *dev)
1450 {
1451         const struct pcidas64_board *thisboard = comedi_board(dev);
1452         struct pcidas64_private *devpriv = dev->private;
1453
1454         return devpriv->ai_fifo_segment_length *
1455                thisboard->ai_fifo->num_segments *
1456                thisboard->ai_fifo->sample_packing_ratio;
1457 }
1458
1459 static void init_stc_registers(struct comedi_device *dev)
1460 {
1461         const struct pcidas64_board *thisboard = comedi_board(dev);
1462         struct pcidas64_private *devpriv = dev->private;
1463         uint16_t bits;
1464         unsigned long flags;
1465
1466         spin_lock_irqsave(&dev->spinlock, flags);
1467
1468         /*  bit should be set for 6025,
1469          *  although docs say boards with <= 16 chans should be cleared XXX */
1470         if (1)
1471                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1472         writew(devpriv->adc_control1_bits,
1473                devpriv->main_iobase + ADC_CONTROL1_REG);
1474
1475         /*  6402/16 manual says this register must be initialized to 0xff? */
1476         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1477
1478         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1479         if (thisboard->layout == LAYOUT_4020)
1480                 bits |= INTERNAL_CLOCK_4020_BITS;
1481         devpriv->hw_config_bits |= bits;
1482         writew(devpriv->hw_config_bits,
1483                devpriv->main_iobase + HW_CONFIG_REG);
1484
1485         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1486         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1487
1488         spin_unlock_irqrestore(&dev->spinlock, flags);
1489
1490         /*  set fifos to maximum size */
1491         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1492         set_ai_fifo_segment_length(dev,
1493                                    thisboard->ai_fifo->max_segment_length);
1494
1495         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1496         devpriv->intr_enable_bits =
1497                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1498                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1499         writew(devpriv->intr_enable_bits,
1500                devpriv->main_iobase + INTR_ENABLE_REG);
1501
1502         disable_ai_pacing(dev);
1503 };
1504
1505 static int alloc_and_init_dma_members(struct comedi_device *dev)
1506 {
1507         const struct pcidas64_board *thisboard = comedi_board(dev);
1508         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1509         struct pcidas64_private *devpriv = dev->private;
1510         int i;
1511
1512         /*  allocate pci dma buffers */
1513         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1514                 devpriv->ai_buffer[i] =
1515                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1516                                              &devpriv->ai_buffer_bus_addr[i]);
1517                 if (devpriv->ai_buffer[i] == NULL)
1518                         return -ENOMEM;
1519
1520         }
1521         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1522                 if (ao_cmd_is_supported(thisboard)) {
1523                         devpriv->ao_buffer[i] =
1524                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1525                                                      &devpriv->
1526                                                       ao_buffer_bus_addr[i]);
1527                         if (devpriv->ao_buffer[i] == NULL)
1528                                 return -ENOMEM;
1529
1530                 }
1531         }
1532         /*  allocate dma descriptors */
1533         devpriv->ai_dma_desc =
1534                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1535                                      ai_dma_ring_count(thisboard),
1536                                      &devpriv->ai_dma_desc_bus_addr);
1537         if (devpriv->ai_dma_desc == NULL)
1538                 return -ENOMEM;
1539
1540         DEBUG_PRINT("ai dma descriptors start at bus addr 0x%llx\n",
1541                     (unsigned long long)devpriv->ai_dma_desc_bus_addr);
1542         if (ao_cmd_is_supported(thisboard)) {
1543                 devpriv->ao_dma_desc =
1544                         pci_alloc_consistent(pcidev,
1545                                              sizeof(struct plx_dma_desc) *
1546                                              AO_DMA_RING_COUNT,
1547                                              &devpriv->ao_dma_desc_bus_addr);
1548                 if (devpriv->ao_dma_desc == NULL)
1549                         return -ENOMEM;
1550
1551                 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%llx\n",
1552                             (unsigned long long)devpriv->ao_dma_desc_bus_addr);
1553         }
1554         /*  initialize dma descriptors */
1555         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1556                 devpriv->ai_dma_desc[i].pci_start_addr =
1557                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1558                 if (thisboard->layout == LAYOUT_4020)
1559                         devpriv->ai_dma_desc[i].local_start_addr =
1560                                 cpu_to_le32(devpriv->local1_iobase +
1561                                             ADC_FIFO_REG);
1562                 else
1563                         devpriv->ai_dma_desc[i].local_start_addr =
1564                                 cpu_to_le32(devpriv->local0_iobase +
1565                                             ADC_FIFO_REG);
1566                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1567                 devpriv->ai_dma_desc[i].next =
1568                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1569                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1570                                      sizeof(devpriv->ai_dma_desc[0])) |
1571                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1572                                     PLX_XFER_LOCAL_TO_PCI);
1573         }
1574         if (ao_cmd_is_supported(thisboard)) {
1575                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1576                         devpriv->ao_dma_desc[i].pci_start_addr =
1577                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1578                         devpriv->ao_dma_desc[i].local_start_addr =
1579                                 cpu_to_le32(devpriv->local0_iobase +
1580                                             DAC_FIFO_REG);
1581                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1582                         devpriv->ao_dma_desc[i].next =
1583                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1584                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1585                                              sizeof(devpriv->ao_dma_desc[0])) |
1586                                             PLX_DESC_IN_PCI_BIT |
1587                                             PLX_INTR_TERM_COUNT);
1588                 }
1589         }
1590         return 0;
1591 }
1592
1593 static inline void warn_external_queue(struct comedi_device *dev)
1594 {
1595         comedi_error(dev,
1596                      "AO command and AI external channel queue cannot be used simultaneously.");
1597         comedi_error(dev,
1598                      "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1599 }
1600
1601 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1602 static const int i2c_high_udelay = 1000;
1603 static const int i2c_low_udelay = 10;
1604
1605 /* set i2c data line high or low */
1606 static void i2c_set_sda(struct comedi_device *dev, int state)
1607 {
1608         struct pcidas64_private *devpriv = dev->private;
1609         static const int data_bit = CTL_EE_W;
1610         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1611                                          PLX_CONTROL_REG;
1612
1613         if (state) {
1614                 /*  set data line high */
1615                 devpriv->plx_control_bits &= ~data_bit;
1616                 writel(devpriv->plx_control_bits, plx_control_addr);
1617                 udelay(i2c_high_udelay);
1618         } else {                /*  set data line low */
1619
1620                 devpriv->plx_control_bits |= data_bit;
1621                 writel(devpriv->plx_control_bits, plx_control_addr);
1622                 udelay(i2c_low_udelay);
1623         }
1624 }
1625
1626 /* set i2c clock line high or low */
1627 static void i2c_set_scl(struct comedi_device *dev, int state)
1628 {
1629         struct pcidas64_private *devpriv = dev->private;
1630         static const int clock_bit = CTL_USERO;
1631         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1632                                          PLX_CONTROL_REG;
1633
1634         if (state) {
1635                 /*  set clock line high */
1636                 devpriv->plx_control_bits &= ~clock_bit;
1637                 writel(devpriv->plx_control_bits, plx_control_addr);
1638                 udelay(i2c_high_udelay);
1639         } else {                /*  set clock line low */
1640
1641                 devpriv->plx_control_bits |= clock_bit;
1642                 writel(devpriv->plx_control_bits, plx_control_addr);
1643                 udelay(i2c_low_udelay);
1644         }
1645 }
1646
1647 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1648 {
1649         uint8_t bit;
1650         unsigned int num_bits = 8;
1651
1652         DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
1653
1654         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1655                 i2c_set_scl(dev, 0);
1656                 if ((byte & bit))
1657                         i2c_set_sda(dev, 1);
1658                 else
1659                         i2c_set_sda(dev, 0);
1660                 i2c_set_scl(dev, 1);
1661         }
1662 }
1663
1664 /* we can't really read the lines, so fake it */
1665 static int i2c_read_ack(struct comedi_device *dev)
1666 {
1667         i2c_set_scl(dev, 0);
1668         i2c_set_sda(dev, 1);
1669         i2c_set_scl(dev, 1);
1670
1671         return 0;               /*  return fake acknowledge bit */
1672 }
1673
1674 /* send start bit */
1675 static void i2c_start(struct comedi_device *dev)
1676 {
1677         i2c_set_scl(dev, 1);
1678         i2c_set_sda(dev, 1);
1679         i2c_set_sda(dev, 0);
1680 }
1681
1682 /* send stop bit */
1683 static void i2c_stop(struct comedi_device *dev)
1684 {
1685         i2c_set_scl(dev, 0);
1686         i2c_set_sda(dev, 0);
1687         i2c_set_scl(dev, 1);
1688         i2c_set_sda(dev, 1);
1689 }
1690
1691 static void i2c_write(struct comedi_device *dev, unsigned int address,
1692                       const uint8_t *data, unsigned int length)
1693 {
1694         struct pcidas64_private *devpriv = dev->private;
1695         unsigned int i;
1696         uint8_t bitstream;
1697         static const int read_bit = 0x1;
1698
1699         /* XXX need mutex to prevent simultaneous attempts to access
1700          * eeprom and i2c bus */
1701
1702         /*  make sure we dont send anything to eeprom */
1703         devpriv->plx_control_bits &= ~CTL_EE_CS;
1704
1705         i2c_stop(dev);
1706         i2c_start(dev);
1707
1708         /*  send address and write bit */
1709         bitstream = (address << 1) & ~read_bit;
1710         i2c_write_byte(dev, bitstream);
1711
1712         /*  get acknowledge */
1713         if (i2c_read_ack(dev) != 0) {
1714                 comedi_error(dev, "i2c write failed: no acknowledge");
1715                 i2c_stop(dev);
1716                 return;
1717         }
1718         /*  write data bytes */
1719         for (i = 0; i < length; i++) {
1720                 i2c_write_byte(dev, data[i]);
1721                 if (i2c_read_ack(dev) != 0) {
1722                         comedi_error(dev, "i2c write failed: no acknowledge");
1723                         i2c_stop(dev);
1724                         return;
1725                 }
1726         }
1727         i2c_stop(dev);
1728 }
1729
1730 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1731                     struct comedi_insn *insn, unsigned int *data)
1732 {
1733         const struct pcidas64_board *thisboard = comedi_board(dev);
1734         struct pcidas64_private *devpriv = dev->private;
1735         unsigned int bits = 0, n, i;
1736         unsigned int channel, range, aref;
1737         unsigned long flags;
1738         static const int timeout = 100;
1739
1740         DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1741         channel = CR_CHAN(insn->chanspec);
1742         range = CR_RANGE(insn->chanspec);
1743         aref = CR_AREF(insn->chanspec);
1744
1745         /*  disable card's analog input interrupt sources and pacing */
1746         /*  4020 generates dac done interrupts even though they are disabled */
1747         disable_ai_pacing(dev);
1748
1749         spin_lock_irqsave(&dev->spinlock, flags);
1750         if (insn->chanspec & CR_ALT_FILTER)
1751                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1752         else
1753                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1754         writew(devpriv->adc_control1_bits,
1755                devpriv->main_iobase + ADC_CONTROL1_REG);
1756         spin_unlock_irqrestore(&dev->spinlock, flags);
1757
1758         if (thisboard->layout != LAYOUT_4020) {
1759                 /*  use internal queue */
1760                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1761                 writew(devpriv->hw_config_bits,
1762                        devpriv->main_iobase + HW_CONFIG_REG);
1763
1764                 /*  ALT_SOURCE is internal calibration reference */
1765                 if (insn->chanspec & CR_ALT_SOURCE) {
1766                         unsigned int cal_en_bit;
1767
1768                         DEBUG_PRINT("reading calibration source\n");
1769                         if (thisboard->layout == LAYOUT_60XX)
1770                                 cal_en_bit = CAL_EN_60XX_BIT;
1771                         else
1772                                 cal_en_bit = CAL_EN_64XX_BIT;
1773                         /*  select internal reference source to connect
1774                          *  to channel 0 */
1775                         writew(cal_en_bit |
1776                                adc_src_bits(devpriv->calibration_source),
1777                                devpriv->main_iobase + CALIBRATION_REG);
1778                 } else {
1779                         /*  make sure internal calibration source
1780                          *  is turned off */
1781                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1782                 }
1783                 /*  load internal queue */
1784                 bits = 0;
1785                 /*  set gain */
1786                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1787                 /*  set single-ended / differential */
1788                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1789                 if (aref == AREF_COMMON)
1790                         bits |= ADC_COMMON_BIT;
1791                 bits |= adc_chan_bits(channel);
1792                 /*  set stop channel */
1793                 writew(adc_chan_bits(channel),
1794                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1795                 /*  set start channel, and rest of settings */
1796                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1797         } else {
1798                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1799
1800                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1801                 if (insn->chanspec & CR_ALT_SOURCE) {
1802                         DEBUG_PRINT("reading calibration source\n");
1803                         devpriv->i2c_cal_range_bits |=
1804                                 adc_src_4020_bits(devpriv->calibration_source);
1805                 } else {        /* select BNC inputs */
1806                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1807                 }
1808                 /*  select range */
1809                 if (range == 0)
1810                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1811                 else
1812                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1813                 /*  update calibration/range i2c register only if necessary,
1814                  *  as it is very slow */
1815                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1816                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1817                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1818                                   sizeof(i2c_data));
1819                 }
1820
1821                 /* 4020 manual asks that sample interval register to be set
1822                  * before writing to convert register.
1823                  * Using somewhat arbitrary setting of 4 master clock ticks
1824                  * = 0.1 usec */
1825                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1826                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1827         }
1828
1829         for (n = 0; n < insn->n; n++) {
1830
1831                 /*  clear adc buffer (inside loop for 4020 sake) */
1832                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1833
1834                 /* trigger conversion, bits sent only matter for 4020 */
1835                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1836                        devpriv->main_iobase + ADC_CONVERT_REG);
1837
1838                 /*  wait for data */
1839                 for (i = 0; i < timeout; i++) {
1840                         bits = readw(devpriv->main_iobase + HW_STATUS_REG);
1841                         DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1842                         if (thisboard->layout == LAYOUT_4020) {
1843                                 if (readw(devpriv->main_iobase +
1844                                           ADC_WRITE_PNTR_REG))
1845                                         break;
1846                         } else {
1847                                 if (pipe_full_bits(bits))
1848                                         break;
1849                         }
1850                         udelay(1);
1851                 }
1852                 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1853                 if (i == timeout) {
1854                         comedi_error(dev, " analog input read insn timed out");
1855                         dev_info(dev->class_dev, "status 0x%x\n", bits);
1856                         return -ETIME;
1857                 }
1858                 if (thisboard->layout == LAYOUT_4020)
1859                         data[n] = readl(devpriv->dio_counter_iobase +
1860                                         ADC_FIFO_REG) & 0xffff;
1861                 else
1862                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1863         }
1864
1865         return n;
1866 }
1867
1868 static int ai_config_calibration_source(struct comedi_device *dev,
1869                                         unsigned int *data)
1870 {
1871         const struct pcidas64_board *thisboard = comedi_board(dev);
1872         struct pcidas64_private *devpriv = dev->private;
1873         unsigned int source = data[1];
1874         int num_calibration_sources;
1875
1876         if (thisboard->layout == LAYOUT_60XX)
1877                 num_calibration_sources = 16;
1878         else
1879                 num_calibration_sources = 8;
1880         if (source >= num_calibration_sources) {
1881                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1882                         source);
1883                 return -EINVAL;
1884         }
1885
1886         DEBUG_PRINT("setting calibration source to %i\n", source);
1887         devpriv->calibration_source = source;
1888
1889         return 2;
1890 }
1891
1892 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1893 {
1894         const struct pcidas64_board *thisboard = comedi_board(dev);
1895         int fifo_size;
1896         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1897         unsigned int block_size, requested_block_size;
1898         int retval;
1899
1900         requested_block_size = data[1];
1901
1902         if (requested_block_size) {
1903                 fifo_size = requested_block_size * fifo->num_segments /
1904                             bytes_in_sample;
1905
1906                 retval = set_ai_fifo_size(dev, fifo_size);
1907                 if (retval < 0)
1908                         return retval;
1909
1910         }
1911
1912         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1913
1914         data[1] = block_size;
1915
1916         return 2;
1917 }
1918
1919 static int ai_config_master_clock_4020(struct comedi_device *dev,
1920                                        unsigned int *data)
1921 {
1922         struct pcidas64_private *devpriv = dev->private;
1923         unsigned int divisor = data[4];
1924         int retval = 0;
1925
1926         if (divisor < 2) {
1927                 divisor = 2;
1928                 retval = -EAGAIN;
1929         }
1930
1931         switch (data[1]) {
1932         case COMEDI_EV_SCAN_BEGIN:
1933                 devpriv->ext_clock.divisor = divisor;
1934                 devpriv->ext_clock.chanspec = data[2];
1935                 break;
1936         default:
1937                 return -EINVAL;
1938                 break;
1939         }
1940
1941         data[4] = divisor;
1942
1943         return retval ? retval : 5;
1944 }
1945
1946 /* XXX could add support for 60xx series */
1947 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1948 {
1949         const struct pcidas64_board *thisboard = comedi_board(dev);
1950
1951         switch (thisboard->layout) {
1952         case LAYOUT_4020:
1953                 return ai_config_master_clock_4020(dev, data);
1954                 break;
1955         default:
1956                 return -EINVAL;
1957                 break;
1958         }
1959
1960         return -EINVAL;
1961 }
1962
1963 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1964                           struct comedi_insn *insn, unsigned int *data)
1965 {
1966         int id = data[0];
1967
1968         switch (id) {
1969         case INSN_CONFIG_ALT_SOURCE:
1970                 return ai_config_calibration_source(dev, data);
1971                 break;
1972         case INSN_CONFIG_BLOCK_SIZE:
1973                 return ai_config_block_size(dev, data);
1974                 break;
1975         case INSN_CONFIG_TIMER_1:
1976                 return ai_config_master_clock(dev, data);
1977                 break;
1978         default:
1979                 return -EINVAL;
1980                 break;
1981         }
1982         return -EINVAL;
1983 }
1984
1985 /* Gets nearest achievable timing given master clock speed, does not
1986  * take into account possible minimum/maximum divisor values.  Used
1987  * by other timing checking functions. */
1988 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1989 {
1990         unsigned int divisor;
1991
1992         switch (flags & TRIG_ROUND_MASK) {
1993         case TRIG_ROUND_UP:
1994                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
1995                 break;
1996         case TRIG_ROUND_DOWN:
1997                 divisor = ns / TIMER_BASE;
1998                 break;
1999         case TRIG_ROUND_NEAREST:
2000         default:
2001                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
2002                 break;
2003         }
2004         return divisor;
2005 }
2006
2007 /* utility function that rounds desired timing to an achievable time, and
2008  * sets cmd members appropriately.
2009  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
2010  */
2011 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2012 {
2013         const struct pcidas64_board *thisboard = comedi_board(dev);
2014         unsigned int convert_divisor = 0, scan_divisor;
2015         static const int min_convert_divisor = 3;
2016         static const int max_convert_divisor =
2017                 max_counter_value + min_convert_divisor;
2018         static const int min_scan_divisor_4020 = 2;
2019         unsigned long long max_scan_divisor, min_scan_divisor;
2020
2021         if (cmd->convert_src == TRIG_TIMER) {
2022                 if (thisboard->layout == LAYOUT_4020) {
2023                         cmd->convert_arg = 0;
2024                 } else {
2025                         convert_divisor = get_divisor(cmd->convert_arg,
2026                                                       cmd->flags);
2027                         if (convert_divisor > max_convert_divisor)
2028                                 convert_divisor = max_convert_divisor;
2029                         if (convert_divisor < min_convert_divisor)
2030                                 convert_divisor = min_convert_divisor;
2031                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2032                 }
2033         } else if (cmd->convert_src == TRIG_NOW) {
2034                 cmd->convert_arg = 0;
2035         }
2036
2037         if (cmd->scan_begin_src == TRIG_TIMER) {
2038                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2039                 if (cmd->convert_src == TRIG_TIMER) {
2040                         /*  XXX check for integer overflows */
2041                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2042                         max_scan_divisor =
2043                                 (convert_divisor * cmd->chanlist_len - 1) +
2044                                 max_counter_value;
2045                 } else {
2046                         min_scan_divisor = min_scan_divisor_4020;
2047                         max_scan_divisor = max_counter_value + min_scan_divisor;
2048                 }
2049                 if (scan_divisor > max_scan_divisor)
2050                         scan_divisor = max_scan_divisor;
2051                 if (scan_divisor < min_scan_divisor)
2052                         scan_divisor = min_scan_divisor;
2053                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2054         }
2055
2056         return;
2057 }
2058
2059 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2060                       struct comedi_cmd *cmd)
2061 {
2062         const struct pcidas64_board *thisboard = comedi_board(dev);
2063         int err = 0;
2064         unsigned int tmp_arg, tmp_arg2;
2065         int i;
2066         int aref;
2067         unsigned int triggers;
2068
2069         /* Step 1 : check if triggers are trivially valid */
2070
2071         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2072
2073         triggers = TRIG_TIMER;
2074         if (thisboard->layout == LAYOUT_4020)
2075                 triggers |= TRIG_OTHER;
2076         else
2077                 triggers |= TRIG_FOLLOW;
2078         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2079
2080         triggers = TRIG_TIMER;
2081         if (thisboard->layout == LAYOUT_4020)
2082                 triggers |= TRIG_NOW;
2083         else
2084                 triggers |= TRIG_EXT;
2085         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2086         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2087         err |= cfc_check_trigger_src(&cmd->stop_src,
2088                                      TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2089
2090         if (err)
2091                 return 1;
2092
2093         /* Step 2a : make sure trigger sources are unique */
2094
2095         err |= cfc_check_trigger_is_unique(cmd->start_src);
2096         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2097         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2098         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2099
2100         /* Step 2b : and mutually compatible */
2101
2102         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2103                 err |= -EINVAL;
2104         if (cmd->stop_src != TRIG_COUNT &&
2105             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2106                 err |= -EINVAL;
2107
2108         if (err)
2109                 return 2;
2110
2111         /* Step 3: check if arguments are trivially valid */
2112
2113         if (cmd->convert_src == TRIG_TIMER) {
2114                 if (thisboard->layout == LAYOUT_4020) {
2115                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2116                 } else {
2117                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2118                                                          thisboard->ai_speed);
2119                         /* if scans are timed faster than conversion rate allows */
2120                         if (cmd->scan_begin_src == TRIG_TIMER)
2121                                 err |= cfc_check_trigger_arg_min(
2122                                                 &cmd->scan_begin_arg,
2123                                                 cmd->convert_arg *
2124                                                 cmd->chanlist_len);
2125                 }
2126         }
2127
2128         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2129         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2130
2131         switch (cmd->stop_src) {
2132         case TRIG_EXT:
2133                 break;
2134         case TRIG_COUNT:
2135                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2136                 break;
2137         case TRIG_NONE:
2138                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2139                 break;
2140         default:
2141                 break;
2142         }
2143
2144         if (err)
2145                 return 3;
2146
2147         /* step 4: fix up any arguments */
2148
2149         if (cmd->convert_src == TRIG_TIMER) {
2150                 tmp_arg = cmd->convert_arg;
2151                 tmp_arg2 = cmd->scan_begin_arg;
2152                 check_adc_timing(dev, cmd);
2153                 if (tmp_arg != cmd->convert_arg)
2154                         err++;
2155                 if (tmp_arg2 != cmd->scan_begin_arg)
2156                         err++;
2157         }
2158
2159         if (err)
2160                 return 4;
2161
2162         /*  make sure user is doesn't change analog reference mid chanlist */
2163         if (cmd->chanlist) {
2164                 aref = CR_AREF(cmd->chanlist[0]);
2165                 for (i = 1; i < cmd->chanlist_len; i++) {
2166                         if (aref != CR_AREF(cmd->chanlist[i])) {
2167                                 comedi_error(dev,
2168                                              "all elements in chanlist must use the same analog reference");
2169                                 err++;
2170                                 break;
2171                         }
2172                 }
2173                 /*  check 4020 chanlist */
2174                 if (thisboard->layout == LAYOUT_4020) {
2175                         unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2176                         for (i = 1; i < cmd->chanlist_len; i++) {
2177                                 if (CR_CHAN(cmd->chanlist[i]) !=
2178                                     first_channel + i) {
2179                                         comedi_error(dev,
2180                                                      "chanlist must use consecutive channels");
2181                                         err++;
2182                                         break;
2183                                 }
2184                         }
2185                         if (cmd->chanlist_len == 3) {
2186                                 comedi_error(dev,
2187                                              "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2188                                 err++;
2189                         }
2190                 }
2191         }
2192
2193         if (err)
2194                 return 5;
2195
2196         return 0;
2197 }
2198
2199 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2200 {
2201 /* disable for now until I work out a race */
2202         return 0;
2203
2204         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2205                 return 1;
2206         else
2207                 return 0;
2208 }
2209
2210 static void setup_sample_counters(struct comedi_device *dev,
2211                                   struct comedi_cmd *cmd)
2212 {
2213         struct pcidas64_private *devpriv = dev->private;
2214
2215         if (cmd->stop_src == TRIG_COUNT) {
2216                 /*  set software count */
2217                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2218         }
2219         /*  load hardware conversion counter */
2220         if (use_hw_sample_counter(cmd)) {
2221                 writew(cmd->stop_arg & 0xffff,
2222                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2223                 writew((cmd->stop_arg >> 16) & 0xff,
2224                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2225         } else {
2226                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2227         }
2228 }
2229
2230 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2231 {
2232         const struct pcidas64_board *thisboard = comedi_board(dev);
2233         struct pcidas64_private *devpriv = dev->private;
2234         unsigned int num_samples;
2235
2236         num_samples = devpriv->ai_fifo_segment_length *
2237                       thisboard->ai_fifo->sample_packing_ratio;
2238         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2239                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2240
2241         return num_samples;
2242 }
2243
2244 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2245                                         const struct comedi_cmd *cmd)
2246 {
2247         /*  supposed to load counter with desired divisor minus 3 */
2248         return cmd->convert_arg / TIMER_BASE - 3;
2249 }
2250
2251 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2252                                      struct comedi_cmd *cmd)
2253 {
2254         uint32_t count;
2255
2256         /*  figure out how long we need to delay at end of scan */
2257         switch (cmd->scan_begin_src) {
2258         case TRIG_TIMER:
2259                 count = (cmd->scan_begin_arg -
2260                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2261                         TIMER_BASE;
2262                 break;
2263         case TRIG_FOLLOW:
2264                 count = cmd->convert_arg / TIMER_BASE;
2265                 break;
2266         default:
2267                 return 0;
2268                 break;
2269         }
2270         return count - 3;
2271 }
2272
2273 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2274                                         struct comedi_cmd *cmd)
2275 {
2276         struct pcidas64_private *devpriv = dev->private;
2277         unsigned int divisor;
2278
2279         switch (cmd->scan_begin_src) {
2280         case TRIG_TIMER:
2281                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2282                 break;
2283         case TRIG_OTHER:
2284                 divisor = devpriv->ext_clock.divisor;
2285                 break;
2286         default:                /*  should never happen */
2287                 comedi_error(dev, "bug! failed to set ai pacing!");
2288                 divisor = 1000;
2289                 break;
2290         }
2291
2292         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2293         return divisor - 2;
2294 }
2295
2296 static void select_master_clock_4020(struct comedi_device *dev,
2297                                      const struct comedi_cmd *cmd)
2298 {
2299         struct pcidas64_private *devpriv = dev->private;
2300
2301         /*  select internal/external master clock */
2302         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2303         if (cmd->scan_begin_src == TRIG_OTHER) {
2304                 int chanspec = devpriv->ext_clock.chanspec;
2305
2306                 if (CR_CHAN(chanspec))
2307                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2308                 else
2309                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2310         } else {
2311                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2312         }
2313         writew(devpriv->hw_config_bits,
2314                devpriv->main_iobase + HW_CONFIG_REG);
2315 }
2316
2317 static void select_master_clock(struct comedi_device *dev,
2318                                 const struct comedi_cmd *cmd)
2319 {
2320         const struct pcidas64_board *thisboard = comedi_board(dev);
2321
2322         switch (thisboard->layout) {
2323         case LAYOUT_4020:
2324                 select_master_clock_4020(dev, cmd);
2325                 break;
2326         default:
2327                 break;
2328         }
2329 }
2330
2331 static inline void dma_start_sync(struct comedi_device *dev,
2332                                   unsigned int channel)
2333 {
2334         struct pcidas64_private *devpriv = dev->private;
2335         unsigned long flags;
2336
2337         /*  spinlock for plx dma control/status reg */
2338         spin_lock_irqsave(&dev->spinlock, flags);
2339         if (channel)
2340                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2341                        PLX_CLEAR_DMA_INTR_BIT,
2342                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2343         else
2344                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2345                        PLX_CLEAR_DMA_INTR_BIT,
2346                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2347         spin_unlock_irqrestore(&dev->spinlock, flags);
2348 }
2349
2350 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2351 {
2352         const struct pcidas64_board *thisboard = comedi_board(dev);
2353         struct pcidas64_private *devpriv = dev->private;
2354         uint32_t convert_counter = 0, scan_counter = 0;
2355
2356         check_adc_timing(dev, cmd);
2357
2358         select_master_clock(dev, cmd);
2359
2360         if (thisboard->layout == LAYOUT_4020) {
2361                 convert_counter = ai_convert_counter_4020(dev, cmd);
2362         } else {
2363                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2364                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2365         }
2366
2367         /*  load lower 16 bits of convert interval */
2368         writew(convert_counter & 0xffff,
2369                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2370         DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2371         /*  load upper 8 bits of convert interval */
2372         writew((convert_counter >> 16) & 0xff,
2373                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2374         /*  load lower 16 bits of scan delay */
2375         writew(scan_counter & 0xffff,
2376                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2377         /*  load upper 8 bits of scan delay */
2378         writew((scan_counter >> 16) & 0xff,
2379                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2380         DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2381 }
2382
2383 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2384 {
2385         int i;
2386
2387         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2388                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2389                     CR_CHAN(cmd->chanlist[i]) + 1)
2390                         return 0;
2391                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2392                     CR_RANGE(cmd->chanlist[i]))
2393                         return 0;
2394                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2395                         return 0;
2396         }
2397         return 1;
2398 }
2399
2400 static int setup_channel_queue(struct comedi_device *dev,
2401                                const struct comedi_cmd *cmd)
2402 {
2403         const struct pcidas64_board *thisboard = comedi_board(dev);
2404         struct pcidas64_private *devpriv = dev->private;
2405         unsigned short bits;
2406         int i;
2407
2408         if (thisboard->layout != LAYOUT_4020) {
2409                 if (use_internal_queue_6xxx(cmd)) {
2410                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2411                         writew(devpriv->hw_config_bits,
2412                                devpriv->main_iobase + HW_CONFIG_REG);
2413                         bits = 0;
2414                         /*  set channel */
2415                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2416                         /*  set gain */
2417                         bits |= ai_range_bits_6xxx(dev,
2418                                                    CR_RANGE(cmd->chanlist[0]));
2419                         /*  set single-ended / differential */
2420                         bits |= se_diff_bit_6xxx(dev,
2421                                                  CR_AREF(cmd->chanlist[0]) ==
2422                                                  AREF_DIFF);
2423                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2424                                 bits |= ADC_COMMON_BIT;
2425                         /*  set stop channel */
2426                         writew(adc_chan_bits
2427                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2428                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2429                         /*  set start channel, and rest of settings */
2430                         writew(bits,
2431                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2432                 } else {
2433                         /*  use external queue */
2434                         if (dev->write_subdev && dev->write_subdev->busy) {
2435                                 warn_external_queue(dev);
2436                                 return -EBUSY;
2437                         }
2438                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2439                         writew(devpriv->hw_config_bits,
2440                                devpriv->main_iobase + HW_CONFIG_REG);
2441                         /*  clear DAC buffer to prevent weird interactions */
2442                         writew(0,
2443                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2444                         /*  clear queue pointer */
2445                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2446                         /*  load external queue */
2447                         for (i = 0; i < cmd->chanlist_len; i++) {
2448                                 bits = 0;
2449                                 /*  set channel */
2450                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2451                                                               chanlist[i]));
2452                                 /*  set gain */
2453                                 bits |= ai_range_bits_6xxx(dev,
2454                                                            CR_RANGE(cmd->
2455                                                                     chanlist
2456                                                                     [i]));
2457                                 /*  set single-ended / differential */
2458                                 bits |= se_diff_bit_6xxx(dev,
2459                                                          CR_AREF(cmd->
2460                                                                  chanlist[i]) ==
2461                                                          AREF_DIFF);
2462                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2463                                         bits |= ADC_COMMON_BIT;
2464                                 /*  mark end of queue */
2465                                 if (i == cmd->chanlist_len - 1)
2466                                         bits |= QUEUE_EOSCAN_BIT |
2467                                                 QUEUE_EOSEQ_BIT;
2468                                 writew(bits,
2469                                        devpriv->main_iobase +
2470                                        ADC_QUEUE_FIFO_REG);
2471                                 DEBUG_PRINT(
2472                                             "wrote 0x%x to external channel queue\n",
2473                                             bits);
2474                         }
2475                         /* doing a queue clear is not specified in board docs,
2476                          * but required for reliable operation */
2477                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2478                         /*  prime queue holding register */
2479                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2480                 }
2481         } else {
2482                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2483
2484                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2485                 /* select BNC inputs */
2486                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2487                 /*  select ranges */
2488                 for (i = 0; i < cmd->chanlist_len; i++) {
2489                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2490                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2491
2492                         if (range == 0)
2493                                 devpriv->i2c_cal_range_bits |=
2494                                         attenuate_bit(channel);
2495                         else
2496                                 devpriv->i2c_cal_range_bits &=
2497                                         ~attenuate_bit(channel);
2498                 }
2499                 /*  update calibration/range i2c register only if necessary,
2500                  *  as it is very slow */
2501                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2502                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2503                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2504                                   sizeof(i2c_data));
2505                 }
2506         }
2507         return 0;
2508 }
2509
2510 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2511                                              unsigned int dma_channel,
2512                                              unsigned int descriptor_bits)
2513 {
2514         struct pcidas64_private *devpriv = dev->private;
2515
2516         /* The transfer size, pci address, and local address registers
2517          * are supposedly unused during chained dma,
2518          * but I have found that left over values from last operation
2519          * occasionally cause problems with transfer of first dma
2520          * block.  Initializing them to zero seems to fix the problem. */
2521         if (dma_channel) {
2522                 writel(0,
2523                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2524                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2525                 writel(0,
2526                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2527                 writel(descriptor_bits,
2528                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2529         } else {
2530                 writel(0,
2531                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2532                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2533                 writel(0,
2534                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2535                 writel(descriptor_bits,
2536                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2537         }
2538 }
2539
2540 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2541 {
2542         const struct pcidas64_board *thisboard = comedi_board(dev);
2543         struct pcidas64_private *devpriv = dev->private;
2544         struct comedi_async *async = s->async;
2545         struct comedi_cmd *cmd = &async->cmd;
2546         uint32_t bits;
2547         unsigned int i;
2548         unsigned long flags;
2549         int retval;
2550
2551         disable_ai_pacing(dev);
2552         abort_dma(dev, 1);
2553
2554         retval = setup_channel_queue(dev, cmd);
2555         if (retval < 0)
2556                 return retval;
2557
2558         /*  make sure internal calibration source is turned off */
2559         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2560
2561         set_ai_pacing(dev, cmd);
2562
2563         setup_sample_counters(dev, cmd);
2564
2565         enable_ai_interrupts(dev, cmd);
2566
2567         spin_lock_irqsave(&dev->spinlock, flags);
2568         /* set mode, allow conversions through software gate */
2569         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2570         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2571         if (thisboard->layout != LAYOUT_4020) {
2572                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2573                 if (cmd->convert_src == TRIG_EXT)
2574                         /*  good old mode 13 */
2575                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2576                 else
2577                         /*  mode 8.  What else could you need? */
2578                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2579         } else {
2580                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2581                 if (cmd->chanlist_len == 4)
2582                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2583                 else if (cmd->chanlist_len == 2)
2584                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2585                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2586                 devpriv->adc_control1_bits |=
2587                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2588                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2589                 devpriv->adc_control1_bits |=
2590                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2591                                                       [cmd->chanlist_len - 1]));
2592         }
2593         writew(devpriv->adc_control1_bits,
2594                devpriv->main_iobase + ADC_CONTROL1_REG);
2595         DEBUG_PRINT("control1 bits 0x%x\n", devpriv->adc_control1_bits);
2596         spin_unlock_irqrestore(&dev->spinlock, flags);
2597
2598         /*  clear adc buffer */
2599         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2600
2601         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2602             thisboard->layout == LAYOUT_4020) {
2603                 devpriv->ai_dma_index = 0;
2604
2605                 /*  set dma transfer size */
2606                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2607                         devpriv->ai_dma_desc[i].transfer_size =
2608                                 cpu_to_le32(dma_transfer_size(dev) *
2609                                             sizeof(uint16_t));
2610
2611                 /*  give location of first dma descriptor */
2612                 load_first_dma_descriptor(dev, 1,
2613                                           devpriv->ai_dma_desc_bus_addr |
2614                                           PLX_DESC_IN_PCI_BIT |
2615                                           PLX_INTR_TERM_COUNT |
2616                                           PLX_XFER_LOCAL_TO_PCI);
2617
2618                 dma_start_sync(dev, 1);
2619         }
2620
2621         if (thisboard->layout == LAYOUT_4020) {
2622                 /* set source for external triggers */
2623                 bits = 0;
2624                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2625                         bits |= EXT_START_TRIG_BNC_BIT;
2626                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2627                         bits |= EXT_STOP_TRIG_BNC_BIT;
2628                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2629         }
2630
2631         spin_lock_irqsave(&dev->spinlock, flags);
2632
2633         /* enable pacing, triggering, etc */
2634         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2635         if (cmd->flags & TRIG_WAKE_EOS)
2636                 bits |= ADC_DMA_DISABLE_BIT;
2637         /*  set start trigger */
2638         if (cmd->start_src == TRIG_EXT) {
2639                 bits |= ADC_START_TRIG_EXT_BITS;
2640                 if (cmd->start_arg & CR_INVERT)
2641                         bits |= ADC_START_TRIG_FALLING_BIT;
2642         } else if (cmd->start_src == TRIG_NOW)
2643                 bits |= ADC_START_TRIG_SOFT_BITS;
2644         if (use_hw_sample_counter(cmd))
2645                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2646         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2647         DEBUG_PRINT("control0 bits 0x%x\n", bits);
2648
2649         devpriv->ai_cmd_running = 1;
2650
2651         spin_unlock_irqrestore(&dev->spinlock, flags);
2652
2653         /*  start acquisition */
2654         if (cmd->start_src == TRIG_NOW) {
2655                 writew(0, devpriv->main_iobase + ADC_START_REG);
2656                 DEBUG_PRINT("soft trig\n");
2657         }
2658
2659         return 0;
2660 }
2661
2662 /* read num_samples from 16 bit wide ai fifo */
2663 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2664 {
2665         struct pcidas64_private *devpriv = dev->private;
2666         struct comedi_subdevice *s = dev->read_subdev;
2667         struct comedi_async *async = s->async;
2668         struct comedi_cmd *cmd = &async->cmd;
2669         unsigned int i;
2670         uint16_t prepost_bits;
2671         int read_segment, read_index, write_segment, write_index;
2672         int num_samples;
2673
2674         do {
2675                 /*  get least significant 15 bits */
2676                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2677                              0x7fff;
2678                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2679                               0x7fff;
2680                 /* Get most significant bits (grey code).
2681                  * Different boards use different code so use a scheme
2682                  * that doesn't depend on encoding.  This read must
2683                  * occur after reading least significant 15 bits to avoid race
2684                  * with fifo switching to next segment. */
2685                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2686
2687                 /* if read and write pointers are not on the same fifo segment,
2688                  * read to the end of the read segment */
2689                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2690                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2691
2692                 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2693                             read_segment, write_segment, read_index,
2694                             write_index);
2695
2696                 if (read_segment != write_segment)
2697                         num_samples =
2698                                 devpriv->ai_fifo_segment_length - read_index;
2699                 else
2700                         num_samples = write_index - read_index;
2701
2702                 if (cmd->stop_src == TRIG_COUNT) {
2703                         if (devpriv->ai_count == 0)
2704                                 break;
2705                         if (num_samples > devpriv->ai_count)
2706                                 num_samples = devpriv->ai_count;
2707
2708                         devpriv->ai_count -= num_samples;
2709                 }
2710
2711                 if (num_samples < 0) {
2712                         dev_err(dev->class_dev,
2713                                 "cb_pcidas64: bug! num_samples < 0\n");
2714                         break;
2715                 }
2716
2717                 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2718
2719                 for (i = 0; i < num_samples; i++) {
2720                         cfc_write_to_buffer(s,
2721                                             readw(devpriv->main_iobase +
2722                                                   ADC_FIFO_REG));
2723                 }
2724
2725         } while (read_segment != write_segment);
2726 }
2727
2728 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2729  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2730  * supports the use of pio for draining the last remaining points from the
2731  * fifo when a data acquisition operation has completed).
2732  */
2733 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2734 {
2735         struct pcidas64_private *devpriv = dev->private;
2736         struct comedi_subdevice *s = dev->read_subdev;
2737         struct comedi_async *async = s->async;
2738         struct comedi_cmd *cmd = &async->cmd;
2739         unsigned int i;
2740         unsigned int max_transfer = 100000;
2741         uint32_t fifo_data;
2742         int write_code =
2743                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2744         int read_code =
2745                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2746
2747         if (cmd->stop_src == TRIG_COUNT) {
2748                 if (max_transfer > devpriv->ai_count)
2749                         max_transfer = devpriv->ai_count;
2750
2751         }
2752         for (i = 0; read_code != write_code && i < max_transfer;) {
2753                 fifo_data = readl(devpriv->dio_counter_iobase + ADC_FIFO_REG);
2754                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2755                 i++;
2756                 if (i < max_transfer) {
2757                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2758                         i++;
2759                 }
2760                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2761                             0x7fff;
2762         }
2763         devpriv->ai_count -= i;
2764 }
2765
2766 /* empty fifo */
2767 static void pio_drain_ai_fifo(struct comedi_device *dev)
2768 {
2769         const struct pcidas64_board *thisboard = comedi_board(dev);
2770
2771         if (thisboard->layout == LAYOUT_4020)
2772                 pio_drain_ai_fifo_32(dev);
2773         else
2774                 pio_drain_ai_fifo_16(dev);
2775 }
2776
2777 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2778 {
2779         const struct pcidas64_board *thisboard = comedi_board(dev);
2780         struct pcidas64_private *devpriv = dev->private;
2781         struct comedi_async *async = dev->read_subdev->async;
2782         uint32_t next_transfer_addr;
2783         int j;
2784         int num_samples = 0;
2785         void __iomem *pci_addr_reg;
2786
2787         if (channel)
2788                 pci_addr_reg =
2789                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2790         else
2791                 pci_addr_reg =
2792                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2793
2794         /*  loop until we have read all the full buffers */
2795         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2796              (next_transfer_addr <
2797               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2798               next_transfer_addr >=
2799               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2800               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2801                 /*  transfer data from dma buffer to comedi buffer */
2802                 num_samples = dma_transfer_size(dev);
2803                 if (async->cmd.stop_src == TRIG_COUNT) {
2804                         if (num_samples > devpriv->ai_count)
2805                                 num_samples = devpriv->ai_count;
2806                         devpriv->ai_count -= num_samples;
2807                 }
2808                 cfc_write_array_to_buffer(dev->read_subdev,
2809                                           devpriv->ai_buffer[devpriv->
2810                                                              ai_dma_index],
2811                                           num_samples * sizeof(uint16_t));
2812                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2813                                         ai_dma_ring_count(thisboard);
2814
2815                 DEBUG_PRINT("next buffer addr 0x%lx\n",
2816                             (unsigned long)devpriv->
2817                             ai_buffer_bus_addr[devpriv->ai_dma_index]);
2818                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2819         }
2820         /* XXX check for dma ring buffer overrun
2821          * (use end-of-chain bit to mark last unused buffer) */
2822 }
2823
2824 static void handle_ai_interrupt(struct comedi_device *dev,
2825                                 unsigned short status,
2826                                 unsigned int plx_status)
2827 {
2828         const struct pcidas64_board *thisboard = comedi_board(dev);
2829         struct pcidas64_private *devpriv = dev->private;
2830         struct comedi_subdevice *s = dev->read_subdev;
2831         struct comedi_async *async = s->async;
2832         struct comedi_cmd *cmd = &async->cmd;
2833         uint8_t dma1_status;
2834         unsigned long flags;
2835
2836         /*  check for fifo overrun */
2837         if (status & ADC_OVERRUN_BIT) {
2838                 comedi_error(dev, "fifo overrun");
2839                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2840         }
2841         /*  spin lock makes sure no one else changes plx dma control reg */
2842         spin_lock_irqsave(&dev->spinlock, flags);
2843         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2844         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2845                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2846                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2847                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2848
2849                 if (dma1_status & PLX_DMA_EN_BIT)
2850                         drain_dma_buffers(dev, 1);
2851
2852                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2853         }
2854         spin_unlock_irqrestore(&dev->spinlock, flags);
2855
2856         if (status & ADC_DONE_BIT)
2857                 DEBUG_PRINT("adc done interrupt\n");
2858
2859         /*  drain fifo with pio */
2860         if ((status & ADC_DONE_BIT) ||
2861             ((cmd->flags & TRIG_WAKE_EOS) &&
2862              (status & ADC_INTR_PENDING_BIT) &&
2863              (thisboard->layout != LAYOUT_4020))) {
2864                 DEBUG_PRINT("pio fifo drain\n");
2865                 spin_lock_irqsave(&dev->spinlock, flags);
2866                 if (devpriv->ai_cmd_running) {
2867                         spin_unlock_irqrestore(&dev->spinlock, flags);
2868                         pio_drain_ai_fifo(dev);
2869                 } else
2870                         spin_unlock_irqrestore(&dev->spinlock, flags);
2871         }
2872         /*  if we are have all the data, then quit */
2873         if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2874             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2875                 async->events |= COMEDI_CB_EOA;
2876         }
2877
2878         cfc_handle_events(dev, s);
2879 }
2880
2881 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2882 {
2883         struct pcidas64_private *devpriv = dev->private;
2884         unsigned int buffer_index;
2885
2886         if (devpriv->ao_dma_index == 0)
2887                 buffer_index = AO_DMA_RING_COUNT - 1;
2888         else
2889                 buffer_index = devpriv->ao_dma_index - 1;
2890         return buffer_index;
2891 }
2892
2893 static int last_ao_dma_load_completed(struct comedi_device *dev)
2894 {
2895         struct pcidas64_private *devpriv = dev->private;
2896         unsigned int buffer_index;
2897         unsigned int transfer_address;
2898         unsigned short dma_status;
2899
2900         buffer_index = prev_ao_dma_index(dev);
2901         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2902         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2903                 return 0;
2904
2905         transfer_address =
2906                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2907         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2908                 return 0;
2909
2910         return 1;
2911 }
2912
2913 static int ao_stopped_by_error(struct comedi_device *dev,
2914                                const struct comedi_cmd *cmd)
2915 {
2916         struct pcidas64_private *devpriv = dev->private;
2917
2918         if (cmd->stop_src == TRIG_NONE)
2919                 return 1;
2920         if (cmd->stop_src == TRIG_COUNT) {
2921                 if (devpriv->ao_count)
2922                         return 1;
2923                 if (last_ao_dma_load_completed(dev) == 0)
2924                         return 1;
2925         }
2926         return 0;
2927 }
2928
2929 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2930                                        unsigned short dma_status)
2931 {
2932         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2933             (dma_status & PLX_DMA_EN_BIT) == 0)
2934                 return 0;
2935         if (last_ao_dma_load_completed(dev))
2936                 return 0;
2937
2938         return 1;
2939 }
2940
2941 static void restart_ao_dma(struct comedi_device *dev)
2942 {
2943         struct pcidas64_private *devpriv = dev->private;
2944         unsigned int dma_desc_bits;
2945
2946         dma_desc_bits =
2947                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2948         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2949         DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
2950         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2951
2952         dma_start_sync(dev, 0);
2953 }
2954
2955 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2956                                        const struct comedi_cmd *cmd)
2957 {
2958         struct pcidas64_private *devpriv = dev->private;
2959         unsigned int num_bytes, buffer_index, prev_buffer_index;
2960         unsigned int next_bits;
2961
2962         buffer_index = devpriv->ao_dma_index;
2963         prev_buffer_index = prev_ao_dma_index(dev);
2964
2965         DEBUG_PRINT("attempting to load ao buffer %i (0x%llx)\n", buffer_index,
2966                     (unsigned long long)devpriv->ao_buffer_bus_addr[
2967                                                                 buffer_index]);
2968
2969         num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
2970         if (num_bytes > DMA_BUFFER_SIZE)
2971                 num_bytes = DMA_BUFFER_SIZE;
2972         if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
2973                 num_bytes = devpriv->ao_count;
2974         num_bytes -= num_bytes % bytes_in_sample;
2975
2976         if (num_bytes == 0)
2977                 return 0;
2978
2979         DEBUG_PRINT("loading %i bytes\n", num_bytes);
2980
2981         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
2982                                                devpriv->
2983                                                ao_buffer[buffer_index],
2984                                                num_bytes);
2985         devpriv->ao_dma_desc[buffer_index].transfer_size =
2986                 cpu_to_le32(num_bytes);
2987         /* set end of chain bit so we catch underruns */
2988         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2989         next_bits |= PLX_END_OF_CHAIN_BIT;
2990         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2991         /* clear end of chain bit on previous buffer now that we have set it
2992          * for the last buffer */
2993         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2994         next_bits &= ~PLX_END_OF_CHAIN_BIT;
2995         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2996
2997         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2998         devpriv->ao_count -= num_bytes;
2999
3000         return num_bytes;
3001 }
3002
3003 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3004 {
3005         struct pcidas64_private *devpriv = dev->private;
3006         unsigned int num_bytes;
3007         unsigned int next_transfer_addr;
3008         void __iomem *pci_addr_reg =
3009                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3010         unsigned int buffer_index;
3011
3012         do {
3013                 buffer_index = devpriv->ao_dma_index;
3014                 /* don't overwrite data that hasn't been transferred yet */
3015                 next_transfer_addr = readl(pci_addr_reg);
3016                 if (next_transfer_addr >=
3017                     devpriv->ao_buffer_bus_addr[buffer_index] &&
3018                     next_transfer_addr <
3019                     devpriv->ao_buffer_bus_addr[buffer_index] +
3020                     DMA_BUFFER_SIZE)
3021                         return;
3022                 num_bytes = load_ao_dma_buffer(dev, cmd);
3023         } while (num_bytes >= DMA_BUFFER_SIZE);
3024 }
3025
3026 static void handle_ao_interrupt(struct comedi_device *dev,
3027                                 unsigned short status, unsigned int plx_status)
3028 {
3029         struct pcidas64_private *devpriv = dev->private;
3030         struct comedi_subdevice *s = dev->write_subdev;
3031         struct comedi_async *async;
3032         struct comedi_cmd *cmd;
3033         uint8_t dma0_status;
3034         unsigned long flags;
3035
3036         /* board might not support ao, in which case write_subdev is NULL */
3037         if (s == NULL)
3038                 return;
3039         async = s->async;
3040         cmd = &async->cmd;
3041
3042         /*  spin lock makes sure no one else changes plx dma control reg */
3043         spin_lock_irqsave(&dev->spinlock, flags);
3044         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3045         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3046                 if ((dma0_status & PLX_DMA_EN_BIT) &&
3047                     !(dma0_status & PLX_DMA_DONE_BIT))
3048                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3049                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3050                 else
3051                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3052                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3053                 spin_unlock_irqrestore(&dev->spinlock, flags);
3054                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3055                 if (dma0_status & PLX_DMA_EN_BIT) {
3056                         load_ao_dma(dev, cmd);
3057                         /* try to recover from dma end-of-chain event */
3058                         if (ao_dma_needs_restart(dev, dma0_status))
3059                                 restart_ao_dma(dev);
3060                 }
3061                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3062         } else {
3063                 spin_unlock_irqrestore(&dev->spinlock, flags);
3064         }
3065
3066         if ((status & DAC_DONE_BIT)) {
3067                 async->events |= COMEDI_CB_EOA;
3068                 if (ao_stopped_by_error(dev, cmd))
3069                         async->events |= COMEDI_CB_ERROR;
3070                 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3071                             readl(devpriv->plx9080_iobase +
3072                                   PLX_DMA0_DESCRIPTOR_REG));
3073                 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3074                             readl(devpriv->plx9080_iobase +
3075                                   PLX_DMA0_PCI_ADDRESS_REG));
3076         }
3077         cfc_handle_events(dev, s);
3078 }
3079
3080 static irqreturn_t handle_interrupt(int irq, void *d)
3081 {
3082         struct comedi_device *dev = d;
3083         struct pcidas64_private *devpriv = dev->private;
3084         unsigned short status;
3085         uint32_t plx_status;
3086         uint32_t plx_bits;
3087
3088         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3089         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3090
3091         DEBUG_PRINT("hw status 0x%x, plx status 0x%x\n", status, plx_status);
3092
3093         /* an interrupt before all the postconfig stuff gets done could
3094          * cause a NULL dereference if we continue through the
3095          * interrupt handler */
3096         if (!dev->attached) {
3097                 DEBUG_PRINT("premature interrupt, ignoring\n");
3098                 return IRQ_HANDLED;
3099         }
3100         handle_ai_interrupt(dev, status, plx_status);
3101         handle_ao_interrupt(dev, status, plx_status);
3102
3103         /*  clear possible plx9080 interrupt sources */
3104         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3105                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3106                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3107                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3108         }
3109
3110         DEBUG_PRINT("exiting handler\n");
3111
3112         return IRQ_HANDLED;
3113 }
3114
3115 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3116 {
3117         struct pcidas64_private *devpriv = dev->private;
3118         unsigned long flags;
3119
3120         spin_lock_irqsave(&dev->spinlock, flags);
3121         if (devpriv->ai_cmd_running == 0) {
3122                 spin_unlock_irqrestore(&dev->spinlock, flags);
3123                 return 0;
3124         }
3125         devpriv->ai_cmd_running = 0;
3126         spin_unlock_irqrestore(&dev->spinlock, flags);
3127
3128         disable_ai_pacing(dev);
3129
3130         abort_dma(dev, 1);
3131
3132         DEBUG_PRINT("ai canceled\n");
3133         return 0;
3134 }
3135
3136 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3137                     struct comedi_insn *insn, unsigned int *data)
3138 {
3139         const struct pcidas64_board *thisboard = comedi_board(dev);
3140         struct pcidas64_private *devpriv = dev->private;
3141         int chan = CR_CHAN(insn->chanspec);
3142         int range = CR_RANGE(insn->chanspec);
3143
3144         /*  do some initializing */
3145         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3146
3147         /*  set range */
3148         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3149         writew(devpriv->dac_control1_bits,
3150                devpriv->main_iobase + DAC_CONTROL1_REG);
3151
3152         /*  write to channel */
3153         if (thisboard->layout == LAYOUT_4020) {
3154                 writew(data[0] & 0xff,
3155                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3156                 writew((data[0] >> 8) & 0xf,
3157                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3158         } else {
3159                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3160         }
3161
3162         /*  remember output value */
3163         devpriv->ao_value[chan] = data[0];
3164
3165         return 1;
3166 }
3167
3168 static int ao_readback_insn(struct comedi_device *dev,
3169                             struct comedi_subdevice *s,
3170                             struct comedi_insn *insn, unsigned int *data)
3171 {
3172         struct pcidas64_private *devpriv = dev->private;
3173
3174         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3175
3176         return 1;
3177 }
3178
3179 static void set_dac_control0_reg(struct comedi_device *dev,
3180                                  const struct comedi_cmd *cmd)
3181 {
3182         struct pcidas64_private *devpriv = dev->private;
3183         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3184                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3185
3186         if (cmd->start_src == TRIG_EXT) {
3187                 bits |= WAVEFORM_TRIG_EXT_BITS;
3188                 if (cmd->start_arg & CR_INVERT)
3189                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3190         } else {
3191                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3192         }
3193         if (cmd->scan_begin_src == TRIG_EXT) {
3194                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3195                 if (cmd->scan_begin_arg & CR_INVERT)
3196                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3197         }
3198         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3199 }
3200
3201 static void set_dac_control1_reg(struct comedi_device *dev,
3202                                  const struct comedi_cmd *cmd)
3203 {
3204         struct pcidas64_private *devpriv = dev->private;
3205         int i;
3206
3207         for (i = 0; i < cmd->chanlist_len; i++) {
3208                 int channel, range;
3209
3210                 channel = CR_CHAN(cmd->chanlist[i]);
3211                 range = CR_RANGE(cmd->chanlist[i]);
3212                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3213                                    range);
3214         }
3215         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3216         writew(devpriv->dac_control1_bits,
3217                devpriv->main_iobase + DAC_CONTROL1_REG);
3218 }
3219
3220 static void set_dac_select_reg(struct comedi_device *dev,
3221                                const struct comedi_cmd *cmd)
3222 {
3223         struct pcidas64_private *devpriv = dev->private;
3224         uint16_t bits;
3225         unsigned int first_channel, last_channel;
3226
3227         first_channel = CR_CHAN(cmd->chanlist[0]);
3228         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3229         if (last_channel < first_channel)
3230                 comedi_error(dev, "bug! last ao channel < first ao channel");
3231
3232         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3233
3234         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3235 }
3236
3237 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3238 {
3239         return get_divisor(ns, flags) - 2;
3240 }
3241
3242 static void set_dac_interval_regs(struct comedi_device *dev,
3243                                   const struct comedi_cmd *cmd)
3244 {
3245         struct pcidas64_private *devpriv = dev->private;
3246         unsigned int divisor;
3247
3248         if (cmd->scan_begin_src != TRIG_TIMER)
3249                 return;
3250
3251         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3252         if (divisor > max_counter_value) {
3253                 comedi_error(dev, "bug! ao divisor too big");
3254                 divisor = max_counter_value;
3255         }
3256         writew(divisor & 0xffff,
3257                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3258         writew((divisor >> 16) & 0xff,
3259                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3260 }
3261
3262 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3263 {
3264         struct pcidas64_private *devpriv = dev->private;
3265         unsigned int num_bytes;
3266         int i;
3267
3268         /* clear queue pointer too, since external queue has
3269          * weird interactions with ao fifo */
3270         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3271         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3272
3273         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3274         if (cmd->stop_src == TRIG_COUNT &&
3275             num_bytes / bytes_in_sample > devpriv->ao_count)
3276                 num_bytes = devpriv->ao_count * bytes_in_sample;
3277         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3278                                                devpriv->ao_bounce_buffer,
3279                                                num_bytes);
3280         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3281                 writew(devpriv->ao_bounce_buffer[i],
3282                        devpriv->main_iobase + DAC_FIFO_REG);
3283         }
3284         devpriv->ao_count -= num_bytes / bytes_in_sample;
3285         if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3286                 return 0;
3287         num_bytes = load_ao_dma_buffer(dev, cmd);
3288         if (num_bytes == 0)
3289                 return -1;
3290         load_ao_dma(dev, cmd);
3291
3292         dma_start_sync(dev, 0);
3293
3294         return 0;
3295 }
3296
3297 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3298 {
3299         const struct pcidas64_board *thisboard = comedi_board(dev);
3300
3301         if (dev->read_subdev->busy)
3302                 return 0;
3303         if (thisboard->layout == LAYOUT_4020)
3304                 return 0;
3305         else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3306                 return 0;
3307         return 1;
3308 }
3309
3310 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3311                       unsigned int trig_num)
3312 {
3313         struct pcidas64_private *devpriv = dev->private;
3314         struct comedi_cmd *cmd = &s->async->cmd;
3315         int retval;
3316
3317         if (trig_num != 0)
3318                 return -EINVAL;
3319
3320         retval = prep_ao_dma(dev, cmd);
3321         if (retval < 0)
3322                 return -EPIPE;
3323
3324         set_dac_control0_reg(dev, cmd);
3325
3326         if (cmd->start_src == TRIG_INT)
3327                 writew(0, devpriv->main_iobase + DAC_START_REG);
3328
3329         s->async->inttrig = NULL;
3330
3331         return 0;
3332 }
3333
3334 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3335 {
3336         struct pcidas64_private *devpriv = dev->private;
3337         struct comedi_cmd *cmd = &s->async->cmd;
3338
3339         if (external_ai_queue_in_use(dev)) {
3340                 warn_external_queue(dev);
3341                 return -EBUSY;
3342         }
3343         /* disable analog output system during setup */
3344         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3345
3346         devpriv->ao_dma_index = 0;
3347         devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3348
3349         set_dac_select_reg(dev, cmd);
3350         set_dac_interval_regs(dev, cmd);
3351         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3352                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3353
3354         set_dac_control1_reg(dev, cmd);
3355         s->async->inttrig = ao_inttrig;
3356
3357         return 0;
3358 }
3359
3360 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3361                       struct comedi_cmd *cmd)
3362 {
3363         const struct pcidas64_board *thisboard = comedi_board(dev);
3364         int err = 0;
3365         unsigned int tmp_arg;
3366         int i;
3367
3368         /* Step 1 : check if triggers are trivially valid */
3369
3370         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3371         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3372                                      TRIG_TIMER | TRIG_EXT);
3373         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3374         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3375         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3376
3377         if (err)
3378                 return 1;
3379
3380         /* Step 2a : make sure trigger sources are unique */
3381
3382         err |= cfc_check_trigger_is_unique(cmd->start_src);
3383         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3384
3385         /* Step 2b : and mutually compatible */
3386
3387         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3388                 err |= -EINVAL;
3389         if (cmd->stop_src != TRIG_COUNT &&
3390             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3391                 err |= -EINVAL;
3392
3393         if (err)
3394                 return 2;
3395
3396         /* Step 3: check if arguments are trivially valid */
3397
3398         if (cmd->scan_begin_src == TRIG_TIMER) {
3399                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3400                                                  thisboard->ao_scan_speed);
3401                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3402                     max_counter_value) {
3403                         cmd->scan_begin_arg = (max_counter_value + 2) *
3404                                               TIMER_BASE;
3405                         err |= -EINVAL;
3406                 }
3407         }
3408
3409         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3410         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3411
3412         if (err)
3413                 return 3;
3414
3415         /* step 4: fix up any arguments */
3416
3417         if (cmd->scan_begin_src == TRIG_TIMER) {
3418                 tmp_arg = cmd->scan_begin_arg;
3419                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3420                                                   cmd->flags) * TIMER_BASE;
3421                 if (tmp_arg != cmd->scan_begin_arg)
3422                         err++;
3423         }
3424
3425         if (err)
3426                 return 4;
3427
3428         if (cmd->chanlist) {
3429                 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3430                 for (i = 1; i < cmd->chanlist_len; i++) {
3431                         if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3432                                 comedi_error(dev,
3433                                              "chanlist must use consecutive channels");
3434                                 err++;
3435                                 break;
3436                         }
3437                 }
3438         }
3439
3440         if (err)
3441                 return 5;
3442
3443         return 0;
3444 }
3445
3446 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3447 {
3448         struct pcidas64_private *devpriv = dev->private;
3449
3450         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3451         abort_dma(dev, 0);
3452         return 0;
3453 }
3454
3455 static int dio_callback(int dir, int port, int data, unsigned long arg)
3456 {
3457         void __iomem *iobase = (void __iomem *)arg;
3458         if (dir) {
3459                 writeb(data, iobase + port);
3460                 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3461                 return 0;
3462         } else {
3463                 return readb(iobase + port);
3464         }
3465 }
3466
3467 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3468 {
3469         void __iomem *iobase = (void __iomem *)arg;
3470         if (dir) {
3471                 writew(data, iobase + 2 * port);
3472                 return 0;
3473         } else {
3474                 return readw(iobase + 2 * port);
3475         }
3476 }
3477
3478 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3479                     struct comedi_insn *insn, unsigned int *data)
3480 {
3481         struct pcidas64_private *devpriv = dev->private;
3482         unsigned int bits;
3483
3484         bits = readb(devpriv->dio_counter_iobase + DI_REG);
3485         bits &= 0xf;
3486         data[1] = bits;
3487         data[0] = 0;
3488
3489         return insn->n;
3490 }
3491
3492 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3493                     struct comedi_insn *insn, unsigned int *data)
3494 {
3495         struct pcidas64_private *devpriv = dev->private;
3496
3497         data[0] &= 0xf;
3498         /*  zero bits we are going to change */
3499         s->state &= ~data[0];
3500         /*  set new bits */
3501         s->state |= data[0] & data[1];
3502
3503         writeb(s->state, devpriv->dio_counter_iobase + DO_REG);
3504
3505         data[1] = s->state;
3506
3507         return insn->n;
3508 }
3509
3510 static int dio_60xx_config_insn(struct comedi_device *dev,
3511                                 struct comedi_subdevice *s,
3512                                 struct comedi_insn *insn, unsigned int *data)
3513 {
3514         struct pcidas64_private *devpriv = dev->private;
3515         unsigned int mask;
3516
3517         mask = 1 << CR_CHAN(insn->chanspec);
3518
3519         switch (data[0]) {
3520         case INSN_CONFIG_DIO_INPUT:
3521                 s->io_bits &= ~mask;
3522                 break;
3523         case INSN_CONFIG_DIO_OUTPUT:
3524                 s->io_bits |= mask;
3525                 break;
3526         case INSN_CONFIG_DIO_QUERY:
3527                 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3528                 return 2;
3529         default:
3530                 return -EINVAL;
3531         }
3532
3533         writeb(s->io_bits,
3534                devpriv->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3535
3536         return 1;
3537 }
3538
3539 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3540                           struct comedi_insn *insn, unsigned int *data)
3541 {
3542         struct pcidas64_private *devpriv = dev->private;
3543
3544         if (data[0]) {
3545                 s->state &= ~data[0];
3546                 s->state |= (data[0] & data[1]);
3547                 writeb(s->state,
3548                        devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3549         }
3550
3551         data[1] = readb(devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3552
3553         return insn->n;
3554 }
3555
3556 /* pci-6025 8800 caldac:
3557  * address 0 == dac channel 0 offset
3558  * address 1 == dac channel 0 gain
3559  * address 2 == dac channel 1 offset
3560  * address 3 == dac channel 1 gain
3561  * address 4 == fine adc offset
3562  * address 5 == coarse adc offset
3563  * address 6 == coarse adc gain
3564  * address 7 == fine adc gain
3565  */
3566 /* pci-6402/16 uses all 8 channels for dac:
3567  * address 0 == dac channel 0 fine gain
3568  * address 1 == dac channel 0 coarse gain
3569  * address 2 == dac channel 0 coarse offset
3570  * address 3 == dac channel 1 coarse offset
3571  * address 4 == dac channel 1 fine gain
3572  * address 5 == dac channel 1 coarse gain
3573  * address 6 == dac channel 0 fine offset
3574  * address 7 == dac channel 1 fine offset
3575 */
3576
3577 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3578                              uint8_t value)
3579 {
3580         struct pcidas64_private *devpriv = dev->private;
3581         static const int num_caldac_channels = 8;
3582         static const int bitstream_length = 11;
3583         unsigned int bitstream = ((address & 0x7) << 8) | value;
3584         unsigned int bit, register_bits;
3585         static const int caldac_8800_udelay = 1;
3586
3587         if (address >= num_caldac_channels) {
3588                 comedi_error(dev, "illegal caldac channel");
3589                 return -1;
3590         }
3591         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3592                 register_bits = 0;
3593                 if (bitstream & bit)
3594                         register_bits |= SERIAL_DATA_IN_BIT;
3595                 udelay(caldac_8800_udelay);
3596                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3597                 register_bits |= SERIAL_CLOCK_BIT;
3598                 udelay(caldac_8800_udelay);
3599                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3600         }
3601         udelay(caldac_8800_udelay);
3602         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3603         udelay(caldac_8800_udelay);
3604         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3605         udelay(caldac_8800_udelay);
3606         return 0;
3607 }
3608
3609 /* 4020 caldacs */
3610 static int caldac_i2c_write(struct comedi_device *dev,
3611                             unsigned int caldac_channel, unsigned int value)
3612 {
3613         uint8_t serial_bytes[3];
3614         uint8_t i2c_addr;
3615         enum pointer_bits {
3616                 /*  manual has gain and offset bits switched */
3617                 OFFSET_0_2 = 0x1,
3618                 GAIN_0_2 = 0x2,
3619                 OFFSET_1_3 = 0x4,
3620                 GAIN_1_3 = 0x8,
3621         };
3622         enum data_bits {
3623                 NOT_CLEAR_REGISTERS = 0x20,
3624         };
3625
3626         switch (caldac_channel) {
3627         case 0:         /*  chan 0 offset */
3628                 i2c_addr = CALDAC0_I2C_ADDR;
3629                 serial_bytes[0] = OFFSET_0_2;
3630                 break;
3631         case 1:         /*  chan 1 offset */
3632                 i2c_addr = CALDAC0_I2C_ADDR;
3633                 serial_bytes[0] = OFFSET_1_3;
3634                 break;
3635         case 2:         /*  chan 2 offset */
3636                 i2c_addr = CALDAC1_I2C_ADDR;
3637                 serial_bytes[0] = OFFSET_0_2;
3638                 break;
3639         case 3:         /*  chan 3 offset */
3640                 i2c_addr = CALDAC1_I2C_ADDR;
3641                 serial_bytes[0] = OFFSET_1_3;
3642                 break;
3643         case 4:         /*  chan 0 gain */
3644                 i2c_addr = CALDAC0_I2C_ADDR;
3645                 serial_bytes[0] = GAIN_0_2;
3646                 break;
3647         case 5:         /*  chan 1 gain */
3648                 i2c_addr = CALDAC0_I2C_ADDR;
3649                 serial_bytes[0] = GAIN_1_3;
3650                 break;
3651         case 6:         /*  chan 2 gain */
3652                 i2c_addr = CALDAC1_I2C_ADDR;
3653                 serial_bytes[0] = GAIN_0_2;
3654                 break;
3655         case 7:         /*  chan 3 gain */
3656                 i2c_addr = CALDAC1_I2C_ADDR;
3657                 serial_bytes[0] = GAIN_1_3;
3658                 break;
3659         default:
3660                 comedi_error(dev, "invalid caldac channel\n");
3661                 return -1;
3662                 break;
3663         }
3664         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3665         serial_bytes[2] = value & 0xff;
3666         i2c_write(dev, i2c_addr, serial_bytes, 3);
3667         return 0;
3668 }
3669
3670 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3671                          unsigned int value)
3672 {
3673         const struct pcidas64_board *thisboard = comedi_board(dev);
3674         struct pcidas64_private *devpriv = dev->private;
3675
3676         devpriv->caldac_state[channel] = value;
3677
3678         switch (thisboard->layout) {
3679         case LAYOUT_60XX:
3680         case LAYOUT_64XX:
3681                 caldac_8800_write(dev, channel, value);
3682                 break;
3683         case LAYOUT_4020:
3684                 caldac_i2c_write(dev, channel, value);
3685                 break;
3686         default:
3687                 break;
3688         }
3689 }
3690
3691 static int calib_write_insn(struct comedi_device *dev,
3692                             struct comedi_subdevice *s,
3693                             struct comedi_insn *insn, unsigned int *data)
3694 {
3695         struct pcidas64_private *devpriv = dev->private;
3696         int channel = CR_CHAN(insn->chanspec);
3697
3698         /* return immediately if setting hasn't changed, since
3699          * programming these things is slow */
3700         if (devpriv->caldac_state[channel] == data[0])
3701                 return 1;
3702
3703         caldac_write(dev, channel, data[0]);
3704
3705         return 1;
3706 }
3707
3708 static int calib_read_insn(struct comedi_device *dev,
3709                            struct comedi_subdevice *s, struct comedi_insn *insn,
3710                            unsigned int *data)
3711 {
3712         struct pcidas64_private *devpriv = dev->private;
3713         unsigned int channel = CR_CHAN(insn->chanspec);
3714
3715         data[0] = devpriv->caldac_state[channel];
3716
3717         return 1;
3718 }
3719
3720 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3721                          unsigned int value)
3722 {
3723         struct pcidas64_private *devpriv = dev->private;
3724         static const int bitstream_length = 10;
3725         unsigned int bit, register_bits;
3726         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3727         static const int ad8402_udelay = 1;
3728
3729         devpriv->ad8402_state[channel] = value;
3730
3731         register_bits = SELECT_8402_64XX_BIT;
3732         udelay(ad8402_udelay);
3733         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3734
3735         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3736                 if (bitstream & bit)
3737                         register_bits |= SERIAL_DATA_IN_BIT;
3738                 else
3739                         register_bits &= ~SERIAL_DATA_IN_BIT;
3740                 udelay(ad8402_udelay);
3741                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3742                 udelay(ad8402_udelay);
3743                 writew(register_bits | SERIAL_CLOCK_BIT,
3744                        devpriv->main_iobase + CALIBRATION_REG);
3745         }
3746
3747         udelay(ad8402_udelay);
3748         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3749 }
3750
3751 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3752 static int ad8402_write_insn(struct comedi_device *dev,
3753                              struct comedi_subdevice *s,
3754                              struct comedi_insn *insn, unsigned int *data)
3755 {
3756         struct pcidas64_private *devpriv = dev->private;
3757         int channel = CR_CHAN(insn->chanspec);
3758
3759         /* return immediately if setting hasn't changed, since
3760          * programming these things is slow */
3761         if (devpriv->ad8402_state[channel] == data[0])
3762                 return 1;
3763
3764         devpriv->ad8402_state[channel] = data[0];
3765
3766         ad8402_write(dev, channel, data[0]);
3767
3768         return 1;
3769 }
3770
3771 static int ad8402_read_insn(struct comedi_device *dev,
3772                             struct comedi_subdevice *s,
3773                             struct comedi_insn *insn, unsigned int *data)
3774 {
3775         struct pcidas64_private *devpriv = dev->private;
3776         unsigned int channel = CR_CHAN(insn->chanspec);
3777
3778         data[0] = devpriv->ad8402_state[channel];
3779
3780         return 1;
3781 }
3782
3783 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3784 {
3785         struct pcidas64_private *devpriv = dev->private;
3786         static const int bitstream_length = 11;
3787         static const int read_command = 0x6;
3788         unsigned int bitstream = (read_command << 8) | address;
3789         unsigned int bit;
3790         void __iomem * const plx_control_addr =
3791                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3792         uint16_t value;
3793         static const int value_length = 16;
3794         static const int eeprom_udelay = 1;
3795
3796         udelay(eeprom_udelay);
3797         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3798         /*  make sure we don't send anything to the i2c bus on 4020 */
3799         devpriv->plx_control_bits |= CTL_USERO;
3800         writel(devpriv->plx_control_bits, plx_control_addr);
3801         /*  activate serial eeprom */
3802         udelay(eeprom_udelay);
3803         devpriv->plx_control_bits |= CTL_EE_CS;
3804         writel(devpriv->plx_control_bits, plx_control_addr);
3805
3806         /*  write read command and desired memory address */
3807         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3808                 /*  set bit to be written */
3809                 udelay(eeprom_udelay);
3810                 if (bitstream & bit)
3811                         devpriv->plx_control_bits |= CTL_EE_W;
3812                 else
3813                         devpriv->plx_control_bits &= ~CTL_EE_W;
3814                 writel(devpriv->plx_control_bits, plx_control_addr);
3815                 /*  clock in bit */
3816                 udelay(eeprom_udelay);
3817                 devpriv->plx_control_bits |= CTL_EE_CLK;
3818                 writel(devpriv->plx_control_bits, plx_control_addr);
3819                 udelay(eeprom_udelay);
3820                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3821                 writel(devpriv->plx_control_bits, plx_control_addr);
3822         }
3823         /*  read back value from eeprom memory location */
3824         value = 0;
3825         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3826                 /*  clock out bit */
3827                 udelay(eeprom_udelay);
3828                 devpriv->plx_control_bits |= CTL_EE_CLK;
3829                 writel(devpriv->plx_control_bits, plx_control_addr);
3830                 udelay(eeprom_udelay);
3831                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3832                 writel(devpriv->plx_control_bits, plx_control_addr);
3833                 udelay(eeprom_udelay);
3834                 if (readl(plx_control_addr) & CTL_EE_R)
3835                         value |= bit;
3836         }
3837
3838         /*  deactivate eeprom serial input */
3839         udelay(eeprom_udelay);
3840         devpriv->plx_control_bits &= ~CTL_EE_CS;
3841         writel(devpriv->plx_control_bits, plx_control_addr);
3842
3843         return value;
3844 }
3845
3846 static int eeprom_read_insn(struct comedi_device *dev,
3847                             struct comedi_subdevice *s,
3848                             struct comedi_insn *insn, unsigned int *data)
3849 {
3850         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3851
3852         return 1;
3853 }
3854
3855 /* Allocate and initialize the subdevice structures.
3856  */
3857 static int setup_subdevices(struct comedi_device *dev)
3858 {
3859         const struct pcidas64_board *thisboard = comedi_board(dev);
3860         struct pcidas64_private *devpriv = dev->private;
3861         struct comedi_subdevice *s;
3862         void __iomem *dio_8255_iobase;
3863         int i;
3864         int ret;
3865
3866         ret = comedi_alloc_subdevices(dev, 10);
3867         if (ret)
3868                 return ret;
3869
3870         s = &dev->subdevices[0];
3871         /* analog input subdevice */
3872         dev->read_subdev = s;
3873         s->type = COMEDI_SUBD_AI;
3874         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3875         if (thisboard->layout == LAYOUT_60XX)
3876                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3877         else if (thisboard->layout == LAYOUT_64XX)
3878                 s->subdev_flags |= SDF_DIFF;
3879         /* XXX Number of inputs in differential mode is ignored */
3880         s->n_chan = thisboard->ai_se_chans;
3881         s->len_chanlist = 0x2000;
3882         s->maxdata = (1 << thisboard->ai_bits) - 1;
3883         s->range_table = thisboard->ai_range_table;
3884         s->insn_read = ai_rinsn;
3885         s->insn_config = ai_config_insn;
3886         s->do_cmd = ai_cmd;
3887         s->do_cmdtest = ai_cmdtest;
3888         s->cancel = ai_cancel;
3889         if (thisboard->layout == LAYOUT_4020) {
3890                 uint8_t data;
3891                 /*  set adc to read from inputs
3892                  *  (not internal calibration sources) */
3893                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3894                 /*  set channels to +-5 volt input ranges */
3895                 for (i = 0; i < s->n_chan; i++)
3896                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3897                 data = devpriv->i2c_cal_range_bits;
3898                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3899         }
3900
3901         /* analog output subdevice */
3902         s = &dev->subdevices[1];
3903         if (thisboard->ao_nchan) {
3904                 s->type = COMEDI_SUBD_AO;
3905                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3906                                   SDF_GROUND | SDF_CMD_WRITE;
3907                 s->n_chan = thisboard->ao_nchan;
3908                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3909                 s->range_table = thisboard->ao_range_table;
3910                 s->insn_read = ao_readback_insn;
3911                 s->insn_write = ao_winsn;
3912                 if (ao_cmd_is_supported(thisboard)) {
3913                         dev->write_subdev = s;
3914                         s->do_cmdtest = ao_cmdtest;
3915                         s->do_cmd = ao_cmd;
3916                         s->len_chanlist = thisboard->ao_nchan;
3917                         s->cancel = ao_cancel;
3918                 }
3919         } else {
3920                 s->type = COMEDI_SUBD_UNUSED;
3921         }
3922
3923         /*  digital input */
3924         s = &dev->subdevices[2];
3925         if (thisboard->layout == LAYOUT_64XX) {
3926                 s->type = COMEDI_SUBD_DI;
3927                 s->subdev_flags = SDF_READABLE;
3928                 s->n_chan = 4;
3929                 s->maxdata = 1;
3930                 s->range_table = &range_digital;
3931                 s->insn_bits = di_rbits;
3932         } else
3933                 s->type = COMEDI_SUBD_UNUSED;
3934
3935         /*  digital output */
3936         if (thisboard->layout == LAYOUT_64XX) {
3937                 s = &dev->subdevices[3];
3938                 s->type = COMEDI_SUBD_DO;
3939                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3940                 s->n_chan = 4;
3941                 s->maxdata = 1;
3942                 s->range_table = &range_digital;
3943                 s->insn_bits = do_wbits;
3944         } else
3945                 s->type = COMEDI_SUBD_UNUSED;
3946
3947         /* 8255 */
3948         s = &dev->subdevices[4];
3949         if (thisboard->has_8255) {
3950                 if (thisboard->layout == LAYOUT_4020) {
3951                         dio_8255_iobase = devpriv->main_iobase + I8255_4020_REG;
3952                         subdev_8255_init(dev, s, dio_callback_4020,
3953                                          (unsigned long)dio_8255_iobase);
3954                 } else {
3955                         dio_8255_iobase =
3956                                 devpriv->dio_counter_iobase + DIO_8255_OFFSET;
3957                         subdev_8255_init(dev, s, dio_callback,
3958                                          (unsigned long)dio_8255_iobase);
3959                 }
3960         } else
3961                 s->type = COMEDI_SUBD_UNUSED;
3962
3963         /*  8 channel dio for 60xx */
3964         s = &dev->subdevices[5];
3965         if (thisboard->layout == LAYOUT_60XX) {
3966                 s->type = COMEDI_SUBD_DIO;
3967                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3968                 s->n_chan = 8;
3969                 s->maxdata = 1;
3970                 s->range_table = &range_digital;
3971                 s->insn_config = dio_60xx_config_insn;
3972                 s->insn_bits = dio_60xx_wbits;
3973         } else
3974                 s->type = COMEDI_SUBD_UNUSED;
3975
3976         /*  caldac */
3977         s = &dev->subdevices[6];
3978         s->type = COMEDI_SUBD_CALIB;
3979         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3980         s->n_chan = 8;
3981         if (thisboard->layout == LAYOUT_4020)
3982                 s->maxdata = 0xfff;
3983         else
3984                 s->maxdata = 0xff;
3985         s->insn_read = calib_read_insn;
3986         s->insn_write = calib_write_insn;
3987         for (i = 0; i < s->n_chan; i++)
3988                 caldac_write(dev, i, s->maxdata / 2);
3989
3990         /*  2 channel ad8402 potentiometer */
3991         s = &dev->subdevices[7];
3992         if (thisboard->layout == LAYOUT_64XX) {
3993                 s->type = COMEDI_SUBD_CALIB;
3994                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3995                 s->n_chan = 2;
3996                 s->insn_read = ad8402_read_insn;
3997                 s->insn_write = ad8402_write_insn;
3998                 s->maxdata = 0xff;
3999                 for (i = 0; i < s->n_chan; i++)
4000                         ad8402_write(dev, i, s->maxdata / 2);
4001         } else
4002                 s->type = COMEDI_SUBD_UNUSED;
4003
4004         /* serial EEPROM, if present */
4005         s = &dev->subdevices[8];
4006         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
4007                 s->type = COMEDI_SUBD_MEMORY;
4008                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4009                 s->n_chan = 128;
4010                 s->maxdata = 0xffff;
4011                 s->insn_read = eeprom_read_insn;
4012         } else
4013                 s->type = COMEDI_SUBD_UNUSED;
4014
4015         /*  user counter subd XXX */
4016         s = &dev->subdevices[9];
4017         s->type = COMEDI_SUBD_UNUSED;
4018
4019         return 0;
4020 }
4021
4022 static int auto_attach(struct comedi_device *dev,
4023                        unsigned long context)
4024 {
4025         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4026         const struct pcidas64_board *thisboard = NULL;
4027         struct pcidas64_private *devpriv;
4028         uint32_t local_range, local_decode;
4029         int retval;
4030
4031         if (context < ARRAY_SIZE(pcidas64_boards))
4032                 thisboard = &pcidas64_boards[context];
4033         if (!thisboard)
4034                 return -ENODEV;
4035         dev->board_ptr = thisboard;
4036
4037         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4038         if (!devpriv)
4039                 return -ENOMEM;
4040         dev->private = devpriv;
4041
4042         retval = comedi_pci_enable(dev);
4043         if (retval)
4044                 return retval;
4045         pci_set_master(pcidev);
4046
4047         /* Initialize dev->board_name */
4048         dev->board_name = thisboard->name;
4049
4050         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
4051         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
4052
4053         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4054         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4055         devpriv->dio_counter_iobase = pci_ioremap_bar(pcidev, 3);
4056
4057         if (!devpriv->plx9080_iobase || !devpriv->main_iobase
4058             || !devpriv->dio_counter_iobase) {
4059                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4060                 return -ENOMEM;
4061         }
4062
4063         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
4064         DEBUG_PRINT(" main remapped to 0x%p\n", devpriv->main_iobase);
4065         DEBUG_PRINT(" diocounter remapped to 0x%p\n",
4066                     devpriv->dio_counter_iobase);
4067
4068         /*  figure out what local addresses are */
4069         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
4070                       LRNG_MEM_MASK;
4071         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
4072                        local_range & LMAP_MEM_MASK;
4073         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4074                                   ~local_range) | local_decode;
4075         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
4076                       LRNG_MEM_MASK;
4077         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
4078                        local_range & LMAP_MEM_MASK;
4079         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4080                                   ~local_range) | local_decode;
4081
4082         DEBUG_PRINT(" local 0 io addr 0x%x\n", devpriv->local0_iobase);
4083         DEBUG_PRINT(" local 1 io addr 0x%x\n", devpriv->local1_iobase);
4084
4085         retval = alloc_and_init_dma_members(dev);
4086         if (retval < 0)
4087                 return retval;
4088
4089         devpriv->hw_revision =
4090                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4091         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4092                 devpriv->hw_revision);
4093         init_plx9080(dev);
4094         init_stc_registers(dev);
4095         /*  get irq */
4096         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4097                         "cb_pcidas64", dev)) {
4098                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4099                         pcidev->irq);
4100                 return -EINVAL;
4101         }
4102         dev->irq = pcidev->irq;
4103         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4104
4105         retval = setup_subdevices(dev);
4106         if (retval < 0)
4107                 return retval;
4108
4109         return 0;
4110 }
4111
4112 static void detach(struct comedi_device *dev)
4113 {
4114         const struct pcidas64_board *thisboard = comedi_board(dev);
4115         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4116         struct pcidas64_private *devpriv = dev->private;
4117         unsigned int i;
4118
4119         if (dev->irq)
4120                 free_irq(dev->irq, dev);
4121         if (devpriv) {
4122                 if (pcidev) {
4123                         if (devpriv->plx9080_iobase) {
4124                                 disable_plx_interrupts(dev);
4125                                 iounmap(devpriv->plx9080_iobase);
4126                         }
4127                         if (devpriv->main_iobase)
4128                                 iounmap(devpriv->main_iobase);
4129                         if (devpriv->dio_counter_iobase)
4130                                 iounmap(devpriv->dio_counter_iobase);
4131                         /*  free pci dma buffers */
4132                         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
4133                                 if (devpriv->ai_buffer[i])
4134                                         pci_free_consistent(pcidev,
4135                                                 DMA_BUFFER_SIZE,
4136                                                 devpriv->ai_buffer[i],
4137                                                 devpriv->ai_buffer_bus_addr[i]);
4138                         }
4139                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
4140                                 if (devpriv->ao_buffer[i])
4141                                         pci_free_consistent(pcidev,
4142                                                 DMA_BUFFER_SIZE,
4143                                                 devpriv->ao_buffer[i],
4144                                                 devpriv->ao_buffer_bus_addr[i]);
4145                         }
4146                         /*  free dma descriptors */
4147                         if (devpriv->ai_dma_desc)
4148                                 pci_free_consistent(pcidev,
4149                                         sizeof(struct plx_dma_desc) *
4150                                         ai_dma_ring_count(thisboard),
4151                                         devpriv->ai_dma_desc,
4152                                         devpriv->ai_dma_desc_bus_addr);
4153                         if (devpriv->ao_dma_desc)
4154                                 pci_free_consistent(pcidev,
4155                                         sizeof(struct plx_dma_desc) *
4156                                         AO_DMA_RING_COUNT,
4157                                         devpriv->ao_dma_desc,
4158                                         devpriv->ao_dma_desc_bus_addr);
4159                 }
4160         }
4161         comedi_pci_disable(dev);
4162 }
4163
4164 static struct comedi_driver cb_pcidas64_driver = {
4165         .driver_name    = "cb_pcidas64",
4166         .module         = THIS_MODULE,
4167         .auto_attach    = auto_attach,
4168         .detach         = detach,
4169 };
4170
4171 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4172                                  const struct pci_device_id *id)
4173 {
4174         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4175                                       id->driver_data);
4176 }
4177
4178 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4179         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4180         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4181         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4182         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4183         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4184         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4185         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4186         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4187         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4188         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4189         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4190         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4191         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4192         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4193         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4194         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4195         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4196         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4197         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4198         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4199         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4200         { 0 }
4201 };
4202 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4203
4204 static struct pci_driver cb_pcidas64_pci_driver = {
4205         .name           = "cb_pcidas64",
4206         .id_table       = cb_pcidas64_pci_table,
4207         .probe          = cb_pcidas64_pci_probe,
4208         .remove         = comedi_pci_auto_unconfig,
4209 };
4210 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4211
4212 MODULE_AUTHOR("Comedi http://www.comedi.org");
4213 MODULE_DESCRIPTION("Comedi low-level driver");
4214 MODULE_LICENSE("GPL");