3 * Diamond Systems Diamond-MM-32-AT Comedi driver
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Diamond Systems Diamond-MM-32-AT
22 * Devices: [Diamond Systems] Diamond-MM-32-AT (dmm32at)
23 * Author: Perry J. Piplani <perry.j.piplani@nasa.gov>
24 * Updated: Fri Jun 4 09:13:24 CDT 2004
25 * Status: experimental
27 * Configuration Options:
28 * comedi_config /dev/comedi0 dmm32at baseaddr,irq
30 * This driver is for the Diamond Systems MM-32-AT board
31 * http://www.diamondsystems.com/products/diamondmm32at
33 * It is being used on serveral projects inside NASA, without
34 * problems so far. For analog input commands, TRIG_EXT is not
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include "../comedidev.h"
44 #include "comedi_fc.h"
46 /* Board register addresses */
47 #define DMM32AT_AI_START_CONV_REG 0x00
48 #define DMM32AT_AI_LSB_REG 0x00
49 #define DMM32AT_AUX_DOUT_REG 0x01
50 #define DMM32AT_AUX_DOUT2 (1 << 2) /* J3.42 - OUT2 (OUT2EN) */
51 #define DMM32AT_AUX_DOUT1 (1 << 1) /* J3.43 */
52 #define DMM32AT_AUX_DOUT0 (1 << 0) /* J3.44 - OUT0 (OUT0EN) */
53 #define DMM32AT_AI_MSB_REG 0x01
54 #define DMM32AT_AI_LO_CHAN_REG 0x02
55 #define DMM32AT_AI_HI_CHAN_REG 0x03
56 #define DMM32AT_AUX_DI_REG 0x04
57 #define DMM32AT_AUX_DI_DACBUSY (1 << 7)
58 #define DMM32AT_AUX_DI_CALBUSY (1 << 6)
59 #define DMM32AT_AUX_DI3 (1 << 3) /* J3.45 - ADCLK (CLKSEL) */
60 #define DMM32AT_AUX_DI2 (1 << 2) /* J3.46 - GATE12 (GT12EN) */
61 #define DMM32AT_AUX_DI1 (1 << 1) /* J3.47 - GATE0 (GT0EN) */
62 #define DMM32AT_AUX_DI0 (1 << 0) /* J3.48 - CLK0 (SRC0) */
63 #define DMM32AT_AO_LSB_REG 0x04
64 #define DMM32AT_AO_MSB_REG 0x05
65 #define DMM32AT_AO_MSB_DACH(x) ((x) << 6)
66 #define DMM32AT_FIFO_DEPTH_REG 0x06
67 #define DMM32AT_FIFO_CTRL_REG 0x07
68 #define DMM32AT_FIFO_CTRL_FIFOEN (1 << 3)
69 #define DMM32AT_FIFO_CTRL_SCANEN (1 << 2)
70 #define DMM32AT_FIFO_CTRL_FIFORST (1 << 1)
71 #define DMM32AT_FIFO_STATUS_REG 0x07
72 #define DMM32AT_FIFO_STATUS_EF (1 << 7)
73 #define DMM32AT_FIFO_STATUS_HF (1 << 6)
74 #define DMM32AT_FIFO_STATUS_FF (1 << 5)
75 #define DMM32AT_FIFO_STATUS_OVF (1 << 4)
76 #define DMM32AT_FIFO_STATUS_FIFOEN (1 << 3)
77 #define DMM32AT_FIFO_STATUS_SCANEN (1 << 2)
78 #define DMM32AT_FIFO_STATUS_PAGE_MASK (3 << 0)
79 #define DMM32AT_CTRL_REG 0x08
80 #define DMM32AT_CTRL_RESETA (1 << 5)
81 #define DMM32AT_CTRL_RESETD (1 << 4)
82 #define DMM32AT_CTRL_INTRST (1 << 3)
83 #define DMM32AT_CTRL_PAGE_8254 (0 << 0)
84 #define DMM32AT_CTRL_PAGE_8255 (1 << 0)
85 #define DMM32AT_CTRL_PAGE_CALIB (3 << 0)
86 #define DMM32AT_AI_STATUS_REG 0x08
87 #define DMM32AT_AI_STATUS_STS (1 << 7)
88 #define DMM32AT_AI_STATUS_SD1 (1 << 6)
89 #define DMM32AT_AI_STATUS_SD0 (1 << 5)
90 #define DMM32AT_AI_STATUS_ADCH_MASK (0x1f << 0)
91 #define DMM32AT_INTCLK_REG 0x09
92 #define DMM32AT_INTCLK_ADINT (1 << 7)
93 #define DMM32AT_INTCLK_DINT (1 << 6)
94 #define DMM32AT_INTCLK_TINT (1 << 5)
95 #define DMM32AT_INTCLK_CLKEN (1 << 1) /* 1=see below 0=software */
96 #define DMM32AT_INTCLK_CLKSEL (1 << 0) /* 1=OUT2 0=EXTCLK */
97 #define DMM32AT_CTRDIO_CFG_REG 0x0a
98 #define DMM32AT_CTRDIO_CFG_FREQ12 (1 << 7) /* CLK12 1=100KHz 0=10MHz */
99 #define DMM32AT_CTRDIO_CFG_FREQ0 (1 << 6) /* CLK0 1=10KHz 0=10MHz */
100 #define DMM32AT_CTRDIO_CFG_OUT2EN (1 << 5) /* J3.42 1=OUT2 is DOUT2 */
101 #define DMM32AT_CTRDIO_CFG_OUT0EN (1 << 4) /* J3,44 1=OUT0 is DOUT0 */
102 #define DMM32AT_CTRDIO_CFG_GT0EN (1 << 2) /* J3.47 1=DIN1 is GATE0 */
103 #define DMM32AT_CTRDIO_CFG_SRC0 (1 << 1) /* CLK0 is 0=FREQ0 1=J3.48 */
104 #define DMM32AT_CTRDIO_CFG_GT12EN (1 << 0) /* J3.46 1=DIN2 is GATE12 */
105 #define DMM32AT_AI_CFG_REG 0x0b
106 #define DMM32AT_AI_CFG_SCINT_20US (0 << 4)
107 #define DMM32AT_AI_CFG_SCINT_15US (1 << 4)
108 #define DMM32AT_AI_CFG_SCINT_10US (2 << 4)
109 #define DMM32AT_AI_CFG_SCINT_5US (3 << 4)
110 #define DMM32AT_AI_CFG_RANGE (1 << 3) /* 0=5V 1=10V */
111 #define DMM32AT_AI_CFG_ADBU (1 << 2) /* 0=bipolar 1=unipolar */
112 #define DMM32AT_AI_CFG_GAIN(x) ((x) << 0)
113 #define DMM32AT_AI_READBACK_REG 0x0b
114 #define DMM32AT_AI_READBACK_WAIT (1 << 7) /* DMM32AT_AI_STATUS_STS */
115 #define DMM32AT_AI_READBACK_RANGE (1 << 3)
116 #define DMM32AT_AI_READBACK_ADBU (1 << 2)
117 #define DMM32AT_AI_READBACK_GAIN_MASK (3 << 0)
119 #define DMM32AT_CLK1 0x0d
120 #define DMM32AT_CLK2 0x0e
121 #define DMM32AT_CLKCT 0x0f
123 #define DMM32AT_8255_IOBASE 0x0c /* Page 1 registers */
125 /* Board register values. */
127 /* DMM32AT_AI_CFG_REG 0x0b */
128 #define DMM32AT_RANGE_U10 0x0c
129 #define DMM32AT_RANGE_U5 0x0d
130 #define DMM32AT_RANGE_B10 0x08
131 #define DMM32AT_RANGE_B5 0x00
133 /* DMM32AT_CLKCT 0x0f */
134 #define DMM32AT_CLKCT1 0x56 /* mode3 counter 1 - write low byte only */
135 #define DMM32AT_CLKCT2 0xb6 /* mode3 counter 2 - write high and low byte */
137 /* board AI ranges in comedi structure */
138 static const struct comedi_lrange dmm32at_airanges = {
147 /* register values for above ranges */
148 static const unsigned char dmm32at_rangebits[] = {
155 /* only one of these ranges is valid, as set by a jumper on the
156 * board. The application should only use the range set by the jumper
158 static const struct comedi_lrange dmm32at_aoranges = {
167 static void dmm32at_ai_set_chanspec(struct comedi_device *dev,
168 struct comedi_subdevice *s,
169 unsigned int chanspec, int nchan)
171 unsigned int chan = CR_CHAN(chanspec);
172 unsigned int range = CR_RANGE(chanspec);
173 unsigned int last_chan = (chan + nchan - 1) % s->n_chan;
175 outb(DMM32AT_FIFO_CTRL_FIFORST, dev->iobase + DMM32AT_FIFO_CTRL_REG);
178 outb(DMM32AT_FIFO_CTRL_SCANEN,
179 dev->iobase + DMM32AT_FIFO_CTRL_REG);
181 outb(chan, dev->iobase + DMM32AT_AI_LO_CHAN_REG);
182 outb(last_chan, dev->iobase + DMM32AT_AI_HI_CHAN_REG);
183 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AI_CFG_REG);
186 static unsigned int dmm32at_ai_get_sample(struct comedi_device *dev,
187 struct comedi_subdevice *s)
191 val = inb(dev->iobase + DMM32AT_AI_LSB_REG);
192 val |= (inb(dev->iobase + DMM32AT_AI_MSB_REG) << 8);
194 /* munge two's complement value to offset binary */
195 return comedi_offset_munge(s, val);
198 static int dmm32at_ai_status(struct comedi_device *dev,
199 struct comedi_subdevice *s,
200 struct comedi_insn *insn,
201 unsigned long context)
203 unsigned char status;
205 status = inb(dev->iobase + context);
206 if ((status & DMM32AT_AI_STATUS_STS) == 0)
211 static int dmm32at_ai_insn_read(struct comedi_device *dev,
212 struct comedi_subdevice *s,
213 struct comedi_insn *insn,
219 dmm32at_ai_set_chanspec(dev, s, insn->chanspec, 1);
221 /* wait for circuit to settle */
222 ret = comedi_timeout(dev, s, insn, dmm32at_ai_status,
223 DMM32AT_AI_READBACK_REG);
227 for (i = 0; i < insn->n; i++) {
228 outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG);
230 ret = comedi_timeout(dev, s, insn, dmm32at_ai_status,
231 DMM32AT_AI_STATUS_REG);
235 data[i] = dmm32at_ai_get_sample(dev, s);
241 static int dmm32at_ai_check_chanlist(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_cmd *cmd)
245 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
246 unsigned int range0 = CR_RANGE(cmd->chanlist[0]);
249 for (i = 1; i < cmd->chanlist_len; i++) {
250 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
251 unsigned int range = CR_RANGE(cmd->chanlist[i]);
253 if (chan != (chan0 + i) % s->n_chan) {
254 dev_dbg(dev->class_dev,
255 "entries in chanlist must be consecutive channels, counting upwards\n");
258 if (range != range0) {
259 dev_dbg(dev->class_dev,
260 "entries in chanlist must all have the same gain\n");
268 static int dmm32at_ai_cmdtest(struct comedi_device *dev,
269 struct comedi_subdevice *s,
270 struct comedi_cmd *cmd)
275 /* Step 1 : check if triggers are trivially valid */
277 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
278 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER);
279 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
280 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
281 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
286 /* Step 2a : make sure trigger sources are unique */
288 err |= cfc_check_trigger_is_unique(cmd->stop_src);
290 /* Step 2b : and mutually compatible */
295 /* Step 3: check if arguments are trivially valid */
297 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
299 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 1000000);
300 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 1000000000);
302 if (cmd->convert_arg >= 17500)
303 cmd->convert_arg = 20000;
304 else if (cmd->convert_arg >= 12500)
305 cmd->convert_arg = 15000;
306 else if (cmd->convert_arg >= 7500)
307 cmd->convert_arg = 10000;
309 cmd->convert_arg = 5000;
311 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
313 if (cmd->stop_src == TRIG_COUNT)
314 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
316 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
321 /* Step 4: fix up any arguments */
323 arg = cmd->convert_arg * cmd->scan_end_arg;
324 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, arg);
329 /* Step 5: check channel list if it exists */
330 if (cmd->chanlist && cmd->chanlist_len > 0)
331 err |= dmm32at_ai_check_chanlist(dev, s, cmd);
339 static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec)
341 unsigned char lo1, lo2, hi2;
342 unsigned short both2;
344 /* based on 10mhz clock */
346 both2 = nansec / 20000;
347 hi2 = (both2 & 0xff00) >> 8;
348 lo2 = both2 & 0x00ff;
350 /* set counter clocks to 10MHz, disable all aux dio */
351 outb(0, dev->iobase + DMM32AT_CTRDIO_CFG_REG);
353 /* get access to the clock regs */
354 outb(DMM32AT_CTRL_PAGE_8254, dev->iobase + DMM32AT_CTRL_REG);
356 /* write the counter 1 control word and low byte to counter */
357 outb(DMM32AT_CLKCT1, dev->iobase + DMM32AT_CLKCT);
358 outb(lo1, dev->iobase + DMM32AT_CLK1);
360 /* write the counter 2 control word and low byte then to counter */
361 outb(DMM32AT_CLKCT2, dev->iobase + DMM32AT_CLKCT);
362 outb(lo2, dev->iobase + DMM32AT_CLK2);
363 outb(hi2, dev->iobase + DMM32AT_CLK2);
365 /* enable the ai conversion interrupt and the clock to start scans */
366 outb(DMM32AT_INTCLK_ADINT |
367 DMM32AT_INTCLK_CLKEN | DMM32AT_INTCLK_CLKSEL,
368 dev->iobase + DMM32AT_INTCLK_REG);
371 static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
373 struct comedi_cmd *cmd = &s->async->cmd;
376 dmm32at_ai_set_chanspec(dev, s, cmd->chanlist[0], cmd->chanlist_len);
378 /* reset the interrupt just in case */
379 outb(DMM32AT_CTRL_INTRST, dev->iobase + DMM32AT_CTRL_REG);
382 * wait for circuit to settle
383 * we don't have the 'insn' here but it's not needed
385 ret = comedi_timeout(dev, s, NULL, dmm32at_ai_status,
386 DMM32AT_AI_READBACK_REG);
390 if (cmd->stop_src == TRIG_NONE || cmd->stop_arg > 1) {
391 /* start the clock and enable the interrupts */
392 dmm32at_setaitimer(dev, cmd->scan_begin_arg);
394 /* start the interrups and initiate a single scan */
395 outb(DMM32AT_INTCLK_ADINT, dev->iobase + DMM32AT_INTCLK_REG);
396 outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG);
403 static int dmm32at_ai_cancel(struct comedi_device *dev,
404 struct comedi_subdevice *s)
406 /* disable further interrupts and clocks */
407 outb(0x0, dev->iobase + DMM32AT_INTCLK_REG);
411 static irqreturn_t dmm32at_isr(int irq, void *d)
413 struct comedi_device *dev = d;
414 unsigned char intstat;
418 if (!dev->attached) {
419 dev_err(dev->class_dev, "spurious interrupt\n");
423 intstat = inb(dev->iobase + DMM32AT_INTCLK_REG);
425 if (intstat & DMM32AT_INTCLK_ADINT) {
426 struct comedi_subdevice *s = dev->read_subdev;
427 struct comedi_cmd *cmd = &s->async->cmd;
429 for (i = 0; i < cmd->chanlist_len; i++) {
430 val = dmm32at_ai_get_sample(dev, s);
431 comedi_buf_write_samples(s, &val, 1);
434 if (cmd->stop_src == TRIG_COUNT &&
435 s->async->scans_done >= cmd->stop_arg)
436 s->async->events |= COMEDI_CB_EOA;
438 comedi_handle_events(dev, s);
441 /* reset the interrupt */
442 outb(DMM32AT_CTRL_INTRST, dev->iobase + DMM32AT_CTRL_REG);
446 static int dmm32at_ao_eoc(struct comedi_device *dev,
447 struct comedi_subdevice *s,
448 struct comedi_insn *insn,
449 unsigned long context)
451 unsigned char status;
453 status = inb(dev->iobase + DMM32AT_AUX_DI_REG);
454 if ((status & DMM32AT_AUX_DI_DACBUSY) == 0)
459 static int dmm32at_ao_insn_write(struct comedi_device *dev,
460 struct comedi_subdevice *s,
461 struct comedi_insn *insn,
464 unsigned int chan = CR_CHAN(insn->chanspec);
467 for (i = 0; i < insn->n; i++) {
468 unsigned int val = data[i];
471 /* write LSB then MSB + chan to load DAC */
472 outb(val & 0xff, dev->iobase + DMM32AT_AO_LSB_REG);
473 outb((val >> 8) | DMM32AT_AO_MSB_DACH(chan),
474 dev->iobase + DMM32AT_AO_MSB_REG);
476 /* wait for circuit to settle */
477 ret = comedi_timeout(dev, s, insn, dmm32at_ao_eoc, 0);
481 /* dummy read to update DAC */
482 inb(dev->iobase + DMM32AT_AO_MSB_REG);
484 s->readback[chan] = val;
490 static int dmm32at_8255_io(struct comedi_device *dev,
491 int dir, int port, int data, unsigned long regbase)
493 /* get access to the DIO regs */
494 outb(DMM32AT_CTRL_PAGE_8255, dev->iobase + DMM32AT_CTRL_REG);
497 outb(data, dev->iobase + regbase + port);
500 return inb(dev->iobase + regbase + port);
503 /* Make sure the board is there and put it to a known state */
504 static int dmm32at_reset(struct comedi_device *dev)
506 unsigned char aihi, ailo, fifostat, aistat, intstat, airback;
508 /* reset the board */
509 outb(DMM32AT_CTRL_RESETA, dev->iobase + DMM32AT_CTRL_REG);
511 /* allow a millisecond to reset */
514 /* zero scan and fifo control */
515 outb(0x0, dev->iobase + DMM32AT_FIFO_CTRL_REG);
517 /* zero interrupt and clock control */
518 outb(0x0, dev->iobase + DMM32AT_INTCLK_REG);
520 /* write a test channel range, the high 3 bits should drop */
521 outb(0x80, dev->iobase + DMM32AT_AI_LO_CHAN_REG);
522 outb(0xff, dev->iobase + DMM32AT_AI_HI_CHAN_REG);
524 /* set the range at 10v unipolar */
525 outb(DMM32AT_RANGE_U10, dev->iobase + DMM32AT_AI_CFG_REG);
527 /* should take 10 us to settle, here's a hundred */
530 /* read back the values */
531 ailo = inb(dev->iobase + DMM32AT_AI_LO_CHAN_REG);
532 aihi = inb(dev->iobase + DMM32AT_AI_HI_CHAN_REG);
533 fifostat = inb(dev->iobase + DMM32AT_FIFO_STATUS_REG);
534 aistat = inb(dev->iobase + DMM32AT_AI_STATUS_REG);
535 intstat = inb(dev->iobase + DMM32AT_INTCLK_REG);
536 airback = inb(dev->iobase + DMM32AT_AI_READBACK_REG);
539 * NOTE: The (DMM32AT_AI_STATUS_SD1 | DMM32AT_AI_STATUS_SD0)
540 * test makes this driver only work if the board is configured
541 * with all A/D channels set for single-ended operation.
543 if (ailo != 0x00 || aihi != 0x1f ||
544 fifostat != DMM32AT_FIFO_STATUS_EF ||
545 aistat != (DMM32AT_AI_STATUS_SD1 | DMM32AT_AI_STATUS_SD0) ||
546 intstat != 0x00 || airback != 0x0c)
552 static int dmm32at_attach(struct comedi_device *dev,
553 struct comedi_devconfig *it)
555 struct comedi_subdevice *s;
558 ret = comedi_request_region(dev, it->options[0], 0x10);
562 ret = dmm32at_reset(dev);
564 dev_err(dev->class_dev, "board detection failed\n");
568 if (it->options[1]) {
569 ret = request_irq(it->options[1], dmm32at_isr, 0,
570 dev->board_name, dev);
572 dev->irq = it->options[1];
575 ret = comedi_alloc_subdevices(dev, 3);
579 /* Analog Input subdevice */
580 s = &dev->subdevices[0];
581 s->type = COMEDI_SUBD_AI;
582 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF;
585 s->range_table = &dmm32at_airanges;
586 s->insn_read = dmm32at_ai_insn_read;
588 dev->read_subdev = s;
589 s->subdev_flags |= SDF_CMD_READ;
590 s->len_chanlist = s->n_chan;
591 s->do_cmd = dmm32at_ai_cmd;
592 s->do_cmdtest = dmm32at_ai_cmdtest;
593 s->cancel = dmm32at_ai_cancel;
596 /* Analog Output subdevice */
597 s = &dev->subdevices[1];
598 s->type = COMEDI_SUBD_AO;
599 s->subdev_flags = SDF_WRITABLE;
602 s->range_table = &dmm32at_aoranges;
603 s->insn_write = dmm32at_ao_insn_write;
605 ret = comedi_alloc_subdev_readback(s);
609 /* Digital I/O subdevice */
610 s = &dev->subdevices[2];
611 ret = subdev_8255_init(dev, s, dmm32at_8255_io, DMM32AT_8255_IOBASE);
618 static struct comedi_driver dmm32at_driver = {
619 .driver_name = "dmm32at",
620 .module = THIS_MODULE,
621 .attach = dmm32at_attach,
622 .detach = comedi_legacy_detach,
624 module_comedi_driver(dmm32at_driver);
626 MODULE_AUTHOR("Comedi http://www.comedi.org");
627 MODULE_DESCRIPTION("Comedi: Diamond Systems Diamond-MM-32-AT");
628 MODULE_LICENSE("GPL");