2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 ************************************************************************/
30 * Description: General Standards Corporation High
31 * Speed Parallel Digital Interface rs485 boards
32 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
33 * Status: only receive mode works, transmit not supported
34 * Updated: Thu, 01 Nov 2012 16:17:38 +0000
35 * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
38 * Configuration options:
41 * Manual configuration of supported devices is not supported; they are
42 * configured automatically.
44 * There are some additional hpdi models available from GSC for which
45 * support could be added to this driver.
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50 #include <linux/pci.h>
51 #include <linux/delay.h>
52 #include <linux/interrupt.h>
54 #include "../comedidev.h"
57 #include "comedi_fc.h"
59 static void abort_dma(struct comedi_device *dev, unsigned int channel);
60 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
61 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
62 struct comedi_cmd *cmd);
63 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
64 static irqreturn_t handle_interrupt(int irq, void *d);
65 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
67 #undef HPDI_DEBUG /* disable debugging messages */
68 /* #define HPDI_DEBUG enable debugging code */
71 #define DEBUG_PRINT(format, args...) pr_debug(format , ## args)
73 #define DEBUG_PRINT(format, args...) no_printk(pr_fmt(format), ## args)
76 #define TIMER_BASE 50 /* 20MHz master clock */
77 #define DMA_BUFFER_SIZE 0x10000
78 #define NUM_DMA_BUFFERS 4
79 #define NUM_DMA_DESCRIPTORS 256
81 /* indices of base address regions */
82 enum base_address_regions {
83 PLX9080_BADDRINDEX = 0,
88 FIRMWARE_REV_REG = 0x0,
89 BOARD_CONTROL_REG = 0x4,
90 BOARD_STATUS_REG = 0x8,
91 TX_PROG_ALMOST_REG = 0xc,
92 RX_PROG_ALMOST_REG = 0x10,
95 TX_STATUS_COUNT_REG = 0x1c,
96 TX_LINE_VALID_COUNT_REG = 0x20,
97 TX_LINE_INVALID_COUNT_REG = 0x24,
98 RX_STATUS_COUNT_REG = 0x28,
99 RX_LINE_COUNT_REG = 0x2c,
100 INTERRUPT_CONTROL_REG = 0x30,
101 INTERRUPT_STATUS_REG = 0x34,
102 TX_CLOCK_DIVIDER_REG = 0x38,
103 TX_FIFO_SIZE_REG = 0x40,
104 RX_FIFO_SIZE_REG = 0x44,
105 TX_FIFO_WORDS_REG = 0x48,
106 RX_FIFO_WORDS_REG = 0x4c,
107 INTERRUPT_EDGE_LEVEL_REG = 0x50,
108 INTERRUPT_POLARITY_REG = 0x54,
111 /* bit definitions */
113 enum firmware_revision_bits {
114 FEATURES_REG_PRESENT_BIT = 0x8000,
117 enum board_control_bits {
118 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
119 TX_FIFO_RESET_BIT = 0x2,
120 RX_FIFO_RESET_BIT = 0x4,
121 TX_ENABLE_BIT = 0x10,
122 RX_ENABLE_BIT = 0x20,
123 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
124 /* for ch 0, ch 1 can only transmit (when present) */
125 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
127 CABLE_THROTTLE_ENABLE_BIT = 0x20,
128 TEST_MODE_ENABLE_BIT = 0x80000000,
131 enum board_status_bits {
132 COMMAND_LINE_STATUS_MASK = 0x7f,
133 TX_IN_PROGRESS_BIT = 0x80,
134 TX_NOT_EMPTY_BIT = 0x100,
135 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
136 TX_NOT_ALMOST_FULL_BIT = 0x400,
137 TX_NOT_FULL_BIT = 0x800,
138 RX_NOT_EMPTY_BIT = 0x1000,
139 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
140 RX_NOT_ALMOST_FULL_BIT = 0x4000,
141 RX_NOT_FULL_BIT = 0x8000,
142 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
143 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
144 TX_OVERRUN_BIT = 0x200000,
145 RX_UNDERRUN_BIT = 0x400000,
146 RX_OVERRUN_BIT = 0x800000,
149 static uint32_t almost_full_bits(unsigned int num_words)
151 /* XXX need to add or subtract one? */
152 return (num_words << 16) & 0xff0000;
155 static uint32_t almost_empty_bits(unsigned int num_words)
157 return num_words & 0xffff;
161 FIFO_SIZE_PRESENT_BIT = 0x1,
162 FIFO_WORDS_PRESENT_BIT = 0x2,
163 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
164 GPIO_SUPPORTED_BIT = 0x8,
165 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
166 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
169 enum interrupt_sources {
170 FRAME_VALID_START_INTR = 0,
171 FRAME_VALID_END_INTR = 1,
172 TX_FIFO_EMPTY_INTR = 8,
173 TX_FIFO_ALMOST_EMPTY_INTR = 9,
174 TX_FIFO_ALMOST_FULL_INTR = 10,
175 TX_FIFO_FULL_INTR = 11,
177 RX_ALMOST_EMPTY_INTR = 13,
178 RX_ALMOST_FULL_INTR = 14,
182 static uint32_t intr_bit(int interrupt_source)
184 return 0x1 << interrupt_source;
187 static unsigned int fifo_size(uint32_t fifo_size_bits)
189 return fifo_size_bits & 0xfffff;
193 const char *name; /* board name */
194 int device_id; /* pci device id */
195 int subdevice_id; /* pci subdevice id */
198 static const struct hpdi_board hpdi_boards[] = {
200 .name = "pci-hpdi32",
201 .device_id = PCI_DEVICE_ID_PLX_9080,
202 .subdevice_id = 0x2400,
206 .name = "pxi-hpdi32",
208 .subdevice_id = 0x2705,
213 struct hpdi_private {
214 /* base addresses (ioremapped) */
215 void __iomem *plx9080_iobase;
216 void __iomem *hpdi_iobase;
217 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
218 /* physical addresses of dma buffers */
219 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
220 /* array of dma descriptors read by plx9080, allocated to get proper
222 struct plx_dma_desc *dma_desc;
223 /* physical address of dma descriptor array */
224 dma_addr_t dma_desc_phys_addr;
225 unsigned int num_dma_descriptors;
226 /* pointer to start of buffers indexed by descriptor */
227 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
228 /* index of the dma descriptor that is currently being used */
229 volatile unsigned int dma_desc_index;
230 unsigned int tx_fifo_size;
231 unsigned int rx_fifo_size;
232 volatile unsigned long dio_count;
233 /* software copies of values written to hpdi registers */
234 volatile uint32_t bits[24];
235 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
236 volatile unsigned int block_size;
237 unsigned dio_config_output:1;
240 static int dio_config_insn(struct comedi_device *dev,
241 struct comedi_subdevice *s, struct comedi_insn *insn,
244 struct hpdi_private *devpriv = dev->private;
247 case INSN_CONFIG_DIO_OUTPUT:
248 devpriv->dio_config_output = 1;
251 case INSN_CONFIG_DIO_INPUT:
252 devpriv->dio_config_output = 0;
255 case INSN_CONFIG_DIO_QUERY:
257 devpriv->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
260 case INSN_CONFIG_BLOCK_SIZE:
261 return dio_config_block_size(dev, data);
270 static void disable_plx_interrupts(struct comedi_device *dev)
272 struct hpdi_private *devpriv = dev->private;
274 writel(0, devpriv->plx9080_iobase + PLX_INTRCS_REG);
277 /* initialize plx9080 chip */
278 static void init_plx9080(struct comedi_device *dev)
280 struct hpdi_private *devpriv = dev->private;
282 void __iomem *plx_iobase = devpriv->plx9080_iobase;
285 DEBUG_PRINT(" plx interrupt status 0x%x\n",
286 readl(plx_iobase + PLX_INTRCS_REG));
287 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
288 DEBUG_PRINT(" plx control reg 0x%x\n",
289 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG));
291 DEBUG_PRINT(" plx revision 0x%x\n",
292 readl(plx_iobase + PLX_REVISION_REG));
293 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
294 readl(plx_iobase + PLX_DMA0_MODE_REG));
295 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
296 readl(plx_iobase + PLX_DMA1_MODE_REG));
297 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
298 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
299 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
300 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
301 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
302 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
303 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
304 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
305 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
306 readb(plx_iobase + PLX_DMA0_CS_REG));
307 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
308 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
309 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
311 bits = BIGEND_DMA0 | BIGEND_DMA1;
315 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
317 disable_plx_interrupts(dev);
322 /* configure dma0 mode */
324 /* enable ready input */
325 bits |= PLX_DMA_EN_READYIN_BIT;
326 /* enable dma chaining */
327 bits |= PLX_EN_CHAIN_BIT;
328 /* enable interrupt on dma done
329 * (probably don't need this, since chain never finishes) */
330 bits |= PLX_EN_DMA_DONE_INTR_BIT;
331 /* don't increment local address during transfers
332 * (we are transferring from a fixed fifo register) */
333 bits |= PLX_LOCAL_ADDR_CONST_BIT;
334 /* route dma interrupt to pci bus */
335 bits |= PLX_DMA_INTR_PCI_BIT;
336 /* enable demand mode */
337 bits |= PLX_DEMAND_MODE_BIT;
338 /* enable local burst mode */
339 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
340 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
341 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
344 /* Allocate and initialize the subdevice structures.
346 static int setup_subdevices(struct comedi_device *dev)
348 struct comedi_subdevice *s;
351 ret = comedi_alloc_subdevices(dev, 1);
355 s = &dev->subdevices[0];
356 /* analog input subdevice */
357 dev->read_subdev = s;
358 /* dev->write_subdev = s; */
359 s->type = COMEDI_SUBD_DIO;
361 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
363 s->len_chanlist = 32;
365 s->range_table = &range_digital;
366 s->insn_config = dio_config_insn;
367 s->do_cmd = hpdi_cmd;
368 s->do_cmdtest = hpdi_cmd_test;
369 s->cancel = hpdi_cancel;
374 static int init_hpdi(struct comedi_device *dev)
376 struct hpdi_private *devpriv = dev->private;
377 uint32_t plx_intcsr_bits;
379 writel(BOARD_RESET_BIT, devpriv->hpdi_iobase + BOARD_CONTROL_REG);
382 writel(almost_empty_bits(32) | almost_full_bits(32),
383 devpriv->hpdi_iobase + RX_PROG_ALMOST_REG);
384 writel(almost_empty_bits(32) | almost_full_bits(32),
385 devpriv->hpdi_iobase + TX_PROG_ALMOST_REG);
387 devpriv->tx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
389 devpriv->rx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
392 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
394 /* enable interrupts */
396 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
398 writel(plx_intcsr_bits, devpriv->plx9080_iobase + PLX_INTRCS_REG);
403 /* setup dma descriptors so a link completes every 'transfer_size' bytes */
404 static int setup_dma_descriptors(struct comedi_device *dev,
405 unsigned int transfer_size)
407 struct hpdi_private *devpriv = dev->private;
408 unsigned int buffer_index, buffer_offset;
409 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
410 PLX_XFER_LOCAL_TO_PCI;
413 if (transfer_size > DMA_BUFFER_SIZE)
414 transfer_size = DMA_BUFFER_SIZE;
415 transfer_size -= transfer_size % sizeof(uint32_t);
416 if (transfer_size == 0)
419 DEBUG_PRINT(" transfer_size %i\n", transfer_size);
420 DEBUG_PRINT(" descriptors at 0x%lx\n",
421 (unsigned long)devpriv->dma_desc_phys_addr);
425 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
426 buffer_index < NUM_DMA_BUFFERS; i++) {
427 devpriv->dma_desc[i].pci_start_addr =
428 cpu_to_le32(devpriv->dio_buffer_phys_addr[buffer_index] +
430 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
431 devpriv->dma_desc[i].transfer_size =
432 cpu_to_le32(transfer_size);
433 devpriv->dma_desc[i].next =
434 cpu_to_le32((devpriv->dma_desc_phys_addr + (i +
436 sizeof(devpriv->dma_desc[0])) | next_bits);
438 devpriv->desc_dio_buffer[i] =
439 devpriv->dio_buffer[buffer_index] +
440 (buffer_offset / sizeof(uint32_t));
442 buffer_offset += transfer_size;
443 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
448 DEBUG_PRINT(" desc %i\n", i);
449 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
450 devpriv->desc_dio_buffer[i],
451 (unsigned long)devpriv->dma_desc[i].
453 DEBUG_PRINT(" next 0x%lx\n",
454 (unsigned long)devpriv->dma_desc[i].next);
456 devpriv->num_dma_descriptors = i;
457 /* fix last descriptor to point back to first */
458 devpriv->dma_desc[i - 1].next =
459 cpu_to_le32(devpriv->dma_desc_phys_addr | next_bits);
460 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
461 (unsigned long)devpriv->dma_desc[i - 1].next);
463 devpriv->block_size = transfer_size;
465 return transfer_size;
468 static const struct hpdi_board *hpdi_find_board(struct pci_dev *pcidev)
472 for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
473 if (pcidev->device == hpdi_boards[i].device_id &&
474 pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
475 return &hpdi_boards[i];
479 static int hpdi_auto_attach(struct comedi_device *dev,
480 unsigned long context_unused)
482 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
483 const struct hpdi_board *thisboard;
484 struct hpdi_private *devpriv;
488 thisboard = hpdi_find_board(pcidev);
490 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
494 dev->board_ptr = thisboard;
495 dev->board_name = thisboard->name;
497 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
500 dev->private = devpriv;
502 if (comedi_pci_enable(pcidev, dev->board_name)) {
503 dev_warn(dev->class_dev,
504 "failed enable PCI device and request regions\n");
507 dev->iobase = 1; /* the "detach" needs this */
508 pci_set_master(pcidev);
510 devpriv->plx9080_iobase =
511 ioremap(pci_resource_start(pcidev, PLX9080_BADDRINDEX),
512 pci_resource_len(pcidev, PLX9080_BADDRINDEX));
513 devpriv->hpdi_iobase =
514 ioremap(pci_resource_start(pcidev, HPDI_BADDRINDEX),
515 pci_resource_len(pcidev, HPDI_BADDRINDEX));
516 if (!devpriv->plx9080_iobase || !devpriv->hpdi_iobase) {
517 dev_warn(dev->class_dev, "failed to remap io memory\n");
521 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
522 DEBUG_PRINT(" hpdi remapped to 0x%p\n", devpriv->hpdi_iobase);
527 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
528 dev->board_name, dev)) {
529 dev_warn(dev->class_dev,
530 "unable to allocate irq %u\n", pcidev->irq);
533 dev->irq = pcidev->irq;
535 dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
537 /* allocate pci dma buffers */
538 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
539 devpriv->dio_buffer[i] =
540 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
541 &devpriv->dio_buffer_phys_addr[i]);
542 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
543 devpriv->dio_buffer[i],
544 (unsigned long)devpriv->dio_buffer_phys_addr[i]);
546 /* allocate dma descriptors */
547 devpriv->dma_desc = pci_alloc_consistent(pcidev,
548 sizeof(struct plx_dma_desc) *
550 &devpriv->dma_desc_phys_addr);
551 if (devpriv->dma_desc_phys_addr & 0xf) {
552 dev_warn(dev->class_dev,
553 " dma descriptors not quad-word aligned (bug)\n");
557 retval = setup_dma_descriptors(dev, 0x1000);
561 retval = setup_subdevices(dev);
565 return init_hpdi(dev);
568 static void hpdi_detach(struct comedi_device *dev)
570 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
571 struct hpdi_private *devpriv = dev->private;
575 free_irq(dev->irq, dev);
577 if (devpriv->plx9080_iobase) {
578 disable_plx_interrupts(dev);
579 iounmap(devpriv->plx9080_iobase);
581 if (devpriv->hpdi_iobase)
582 iounmap(devpriv->hpdi_iobase);
583 /* free pci dma buffers */
584 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
585 if (devpriv->dio_buffer[i])
586 pci_free_consistent(pcidev,
588 devpriv->dio_buffer[i],
590 dio_buffer_phys_addr[i]);
592 /* free dma descriptors */
593 if (devpriv->dma_desc)
594 pci_free_consistent(pcidev,
595 sizeof(struct plx_dma_desc) *
598 devpriv->dma_desc_phys_addr);
600 comedi_pci_disable(pcidev);
604 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
606 unsigned int requested_block_size;
609 requested_block_size = data[1];
611 retval = setup_dma_descriptors(dev, requested_block_size);
620 static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
621 struct comedi_cmd *cmd)
626 /* Step 1 : check if triggers are trivially valid */
628 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
629 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
630 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
631 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
632 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
637 /* Step 2a : make sure trigger sources are unique */
639 err |= cfc_check_trigger_is_unique(cmd->stop_src);
641 /* Step 2b : and mutually compatible */
646 /* Step 3: check if arguments are trivially valid */
648 if (!cmd->chanlist_len) {
649 cmd->chanlist_len = 32;
652 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
654 switch (cmd->stop_src) {
656 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
659 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
668 /* step 4: fix up any arguments */
676 for (i = 1; i < cmd->chanlist_len; i++) {
677 if (CR_CHAN(cmd->chanlist[i]) != i) {
678 /* XXX could support 8 or 16 channels */
680 "chanlist must be ch 0 to 31 in order");
692 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
693 struct comedi_cmd *cmd)
695 struct hpdi_private *devpriv = dev->private;
697 if (devpriv->dio_config_output)
700 return di_cmd_test(dev, s, cmd);
703 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
706 struct hpdi_private *devpriv = dev->private;
708 writel(bits | devpriv->bits[offset / sizeof(uint32_t)],
709 devpriv->hpdi_iobase + offset);
712 static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
714 struct hpdi_private *devpriv = dev->private;
717 struct comedi_async *async = s->async;
718 struct comedi_cmd *cmd = &async->cmd;
720 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
722 DEBUG_PRINT("hpdi: in di_cmd\n");
726 devpriv->dma_desc_index = 0;
728 /* These register are supposedly unused during chained dma,
729 * but I have found that left over values from last operation
730 * occasionally cause problems with transfer of first dma
731 * block. Initializing them to zero seems to fix the problem. */
732 writel(0, devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
733 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
734 writel(0, devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
735 /* give location of first dma descriptor */
737 devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
738 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
739 writel(bits, devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
741 /* spinlock for plx dma control/status reg */
742 spin_lock_irqsave(&dev->spinlock, flags);
743 /* enable dma transfer */
744 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
745 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
746 spin_unlock_irqrestore(&dev->spinlock, flags);
748 if (cmd->stop_src == TRIG_COUNT)
749 devpriv->dio_count = cmd->stop_arg;
751 devpriv->dio_count = 1;
753 /* clear over/under run status flags */
754 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
755 devpriv->hpdi_iobase + BOARD_STATUS_REG);
756 /* enable interrupts */
757 writel(intr_bit(RX_FULL_INTR),
758 devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
760 DEBUG_PRINT("hpdi: starting rx\n");
761 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
766 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
768 struct hpdi_private *devpriv = dev->private;
770 if (devpriv->dio_config_output)
773 return di_cmd(dev, s);
776 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
778 struct hpdi_private *devpriv = dev->private;
779 struct comedi_async *async = dev->read_subdev->async;
780 uint32_t next_transfer_addr;
783 void __iomem *pci_addr_reg;
787 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
790 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
792 /* loop until we have read all the full buffers */
794 for (next_transfer_addr = readl(pci_addr_reg);
795 (next_transfer_addr <
796 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
798 || next_transfer_addr >=
799 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
800 pci_start_addr) + devpriv->block_size)
801 && j < devpriv->num_dma_descriptors; j++) {
802 /* transfer data from dma buffer to comedi buffer */
803 num_samples = devpriv->block_size / sizeof(uint32_t);
804 if (async->cmd.stop_src == TRIG_COUNT) {
805 if (num_samples > devpriv->dio_count)
806 num_samples = devpriv->dio_count;
807 devpriv->dio_count -= num_samples;
809 cfc_write_array_to_buffer(dev->read_subdev,
810 devpriv->desc_dio_buffer[devpriv->
812 num_samples * sizeof(uint32_t));
813 devpriv->dma_desc_index++;
814 devpriv->dma_desc_index %= devpriv->num_dma_descriptors;
816 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
817 devpriv->dma_desc[devpriv->dma_desc_index].
819 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
821 /* XXX check for buffer overrun somehow */
824 static irqreturn_t handle_interrupt(int irq, void *d)
826 struct comedi_device *dev = d;
827 struct hpdi_private *devpriv = dev->private;
828 struct comedi_subdevice *s = dev->read_subdev;
829 struct comedi_async *async = s->async;
830 uint32_t hpdi_intr_status, hpdi_board_status;
833 uint8_t dma0_status, dma1_status;
839 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
840 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
843 hpdi_intr_status = readl(devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
844 hpdi_board_status = readl(devpriv->hpdi_iobase + BOARD_STATUS_REG);
848 if (hpdi_intr_status) {
849 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
850 writel(hpdi_intr_status,
851 devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
853 /* spin lock makes sure no one else changes plx dma control reg */
854 spin_lock_irqsave(&dev->spinlock, flags);
855 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
856 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
857 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
858 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
860 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
861 if (dma0_status & PLX_DMA_EN_BIT)
862 drain_dma_buffers(dev, 0);
863 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
865 spin_unlock_irqrestore(&dev->spinlock, flags);
867 /* spin lock makes sure no one else changes plx dma control reg */
868 spin_lock_irqsave(&dev->spinlock, flags);
869 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
870 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
871 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
872 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
873 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
875 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
877 spin_unlock_irqrestore(&dev->spinlock, flags);
879 /* clear possible plx9080 interrupt sources */
880 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
881 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
882 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
883 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
886 if (hpdi_board_status & RX_OVERRUN_BIT) {
887 comedi_error(dev, "rx fifo overrun");
888 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
889 DEBUG_PRINT("dma0_status 0x%x\n",
890 (int)readb(devpriv->plx9080_iobase +
894 if (hpdi_board_status & RX_UNDERRUN_BIT) {
895 comedi_error(dev, "rx fifo underrun");
896 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
899 if (devpriv->dio_count == 0)
900 async->events |= COMEDI_CB_EOA;
902 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
903 DEBUG_PRINT("plx status 0x%x\n", plx_status);
905 DEBUG_PRINT(" events 0x%x\n", async->events);
907 cfc_handle_events(dev, s);
912 static void abort_dma(struct comedi_device *dev, unsigned int channel)
914 struct hpdi_private *devpriv = dev->private;
917 /* spinlock for plx dma control/status reg */
918 spin_lock_irqsave(&dev->spinlock, flags);
920 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
922 spin_unlock_irqrestore(&dev->spinlock, flags);
925 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
927 struct hpdi_private *devpriv = dev->private;
929 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
931 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
938 static struct comedi_driver gsc_hpdi_driver = {
939 .driver_name = "gsc_hpdi",
940 .module = THIS_MODULE,
941 .auto_attach = hpdi_auto_attach,
942 .detach = hpdi_detach,
945 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
946 const struct pci_device_id *ent)
948 return comedi_pci_auto_config(dev, &gsc_hpdi_driver);
951 static DEFINE_PCI_DEVICE_TABLE(gsc_hpdi_pci_table) = {
952 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
956 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
958 static struct pci_driver gsc_hpdi_pci_driver = {
960 .id_table = gsc_hpdi_pci_table,
961 .probe = gsc_hpdi_pci_probe,
962 .remove = comedi_pci_auto_unconfig,
964 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
966 MODULE_AUTHOR("Comedi http://www.comedi.org");
967 MODULE_DESCRIPTION("Comedi low-level driver");
968 MODULE_LICENSE("GPL");