3 Register descriptions and defines for the ME-4000 board family
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 /*=============================================================================
28 PCI vendor and device IDs
29 ===========================================================================*/
31 #define PCI_VENDOR_ID_MEILHAUS 0x1402
33 #define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650 /* Low Cost version */
35 #define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660 /* Standard version */
36 #define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661 /* Isolated version */
37 #define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662 /* Standard version with Sample and Hold */
38 #define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663 /* Isolated version with Sample and Hold */
40 #define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670 /* Standard version */
41 #define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671 /* Isolated version */
42 #define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672 /* Standard version with Sample and Hold */
43 #define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673 /* Isolated version with Sample and Hold */
45 #define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680 /* Standard version */
46 #define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681 /* Isolated version */
47 #define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682 /* Standard version with Sample and Hold */
48 #define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683 /* Isolated version with Sample and Hold */
50 /*=============================================================================
51 ME-4000 base register offsets
52 ===========================================================================*/
54 #define ME4000_AO_00_CTRL_REG 0x00 /* R/W */
55 #define ME4000_AO_00_STATUS_REG 0x04 /* R/_ */
56 #define ME4000_AO_00_FIFO_REG 0x08 /* _/W */
57 #define ME4000_AO_00_SINGLE_REG 0x0C /* R/W */
58 #define ME4000_AO_00_TIMER_REG 0x10 /* _/W */
60 #define ME4000_AO_01_CTRL_REG 0x18 /* R/W */
61 #define ME4000_AO_01_STATUS_REG 0x1C /* R/_ */
62 #define ME4000_AO_01_FIFO_REG 0x20 /* _/W */
63 #define ME4000_AO_01_SINGLE_REG 0x24 /* R/W */
64 #define ME4000_AO_01_TIMER_REG 0x28 /* _/W */
66 #define ME4000_AO_02_CTRL_REG 0x30 /* R/W */
67 #define ME4000_AO_02_STATUS_REG 0x34 /* R/_ */
68 #define ME4000_AO_02_FIFO_REG 0x38 /* _/W */
69 #define ME4000_AO_02_SINGLE_REG 0x3C /* R/W */
70 #define ME4000_AO_02_TIMER_REG 0x40 /* _/W */
72 #define ME4000_AO_03_CTRL_REG 0x48 /* R/W */
73 #define ME4000_AO_03_STATUS_REG 0x4C /* R/_ */
74 #define ME4000_AO_03_FIFO_REG 0x50 /* _/W */
75 #define ME4000_AO_03_SINGLE_REG 0x54 /* R/W */
76 #define ME4000_AO_03_TIMER_REG 0x58 /* _/W */
78 #define ME4000_AI_CTRL_REG 0x74 /* _/W */
79 #define ME4000_AI_STATUS_REG 0x74 /* R/_ */
80 #define ME4000_AI_CHANNEL_LIST_REG 0x78 /* _/W */
81 #define ME4000_AI_DATA_REG 0x7C /* R/_ */
82 #define ME4000_AI_CHAN_TIMER_REG 0x80 /* _/W */
83 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84 /* _/W */
84 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88 /* _/W */
85 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8C /* _/W */
86 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90 /* _/W */
87 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94 /* _/W */
88 #define ME4000_AI_START_REG 0x98 /* R/_ */
90 #define ME4000_IRQ_STATUS_REG 0x9C /* R/_ */
92 #define ME4000_DIO_PORT_0_REG 0xA0 /* R/W */
93 #define ME4000_DIO_PORT_1_REG 0xA4 /* R/W */
94 #define ME4000_DIO_PORT_2_REG 0xA8 /* R/W */
95 #define ME4000_DIO_PORT_3_REG 0xAC /* R/W */
96 #define ME4000_DIO_DIR_REG 0xB0 /* R/W */
98 #define ME4000_AO_LOADSETREG_XX 0xB4 /* R/W */
100 #define ME4000_DIO_CTRL_REG 0xB8 /* R/W */
102 #define ME4000_AO_DEMUX_ADJUST_REG 0xBC /* -/W */
104 #define ME4000_AI_SAMPLE_COUNTER_REG 0xC0 /* _/W */
106 /*=============================================================================
107 Value to adjust Demux
108 ===========================================================================*/
110 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4C
112 /*=============================================================================
113 Counter base register offsets
114 ===========================================================================*/
116 #define ME4000_CNT_COUNTER_0_REG 0x00
117 #define ME4000_CNT_COUNTER_1_REG 0x01
118 #define ME4000_CNT_COUNTER_2_REG 0x02
119 #define ME4000_CNT_CTRL_REG 0x03
121 /*=============================================================================
122 PLX base register offsets
123 ===========================================================================*/
125 #define PLX_INTCSR 0x4C /* Interrupt control and status register */
126 #define PLX_ICR 0x50 /* Initialization control register */
128 /*=============================================================================
129 Bits for the PLX_ICSR register
130 ===========================================================================*/
132 #define PLX_INTCSR_LOCAL_INT1_EN 0x01 /* If set, local interrupt 1 is enabled (r/w) */
133 #define PLX_INTCSR_LOCAL_INT1_POL 0x02 /* If set, local interrupt 1 polarity is active high (r/w) */
134 #define PLX_INTCSR_LOCAL_INT1_STATE 0x04 /* If set, local interrupt 1 is active (r/_) */
135 #define PLX_INTCSR_LOCAL_INT2_EN 0x08 /* If set, local interrupt 2 is enabled (r/w) */
136 #define PLX_INTCSR_LOCAL_INT2_POL 0x10 /* If set, local interrupt 2 polarity is active high (r/w) */
137 #define PLX_INTCSR_LOCAL_INT2_STATE 0x20 /* If set, local interrupt 2 is active (r/_) */
138 #define PLX_INTCSR_PCI_INT_EN 0x40 /* If set, PCI interrupt is enabled (r/w) */
139 #define PLX_INTCSR_SOFT_INT 0x80 /* If set, a software interrupt is generated (r/w) */
141 /*=============================================================================
142 Bits for the PLX_ICR register
143 ===========================================================================*/
145 #define PLX_ICR_BIT_EEPROM_CLOCK_SET 0x01000000
146 #define PLX_ICR_BIT_EEPROM_CHIP_SELECT 0x02000000
147 #define PLX_ICR_BIT_EEPROM_WRITE 0x04000000
148 #define PLX_ICR_BIT_EEPROM_READ 0x08000000
149 #define PLX_ICR_BIT_EEPROM_VALID 0x10000000
151 #define PLX_ICR_MASK_EEPROM 0x1F000000
153 #define EEPROM_DELAY 1
155 /*=============================================================================
156 Bits for the ME4000_AO_CTRL_REG register
157 ===========================================================================*/
159 #define ME4000_AO_CTRL_BIT_MODE_0 0x001
160 #define ME4000_AO_CTRL_BIT_MODE_1 0x002
161 #define ME4000_AO_CTRL_MASK_MODE 0x003
162 #define ME4000_AO_CTRL_BIT_STOP 0x004
163 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO 0x008
164 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG 0x010
165 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE 0x020
166 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP 0x080
167 #define ME4000_AO_CTRL_BIT_ENABLE_DO 0x100
168 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ 0x200
169 #define ME4000_AO_CTRL_BIT_RESET_IRQ 0x400
171 /*=============================================================================
172 Bits for the ME4000_AO_STATUS_REG register
173 ===========================================================================*/
175 #define ME4000_AO_STATUS_BIT_FSM 0x01
176 #define ME4000_AO_STATUS_BIT_FF 0x02
177 #define ME4000_AO_STATUS_BIT_HF 0x04
178 #define ME4000_AO_STATUS_BIT_EF 0x08
180 /*=============================================================================
181 Bits for the ME4000_AI_CTRL_REG register
182 ===========================================================================*/
184 #define ME4000_AI_CTRL_BIT_MODE_0 0x00000001
185 #define ME4000_AI_CTRL_BIT_MODE_1 0x00000002
186 #define ME4000_AI_CTRL_BIT_MODE_2 0x00000004
187 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD 0x00000008
188 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP 0x00000010
189 #define ME4000_AI_CTRL_BIT_STOP 0x00000020
190 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO 0x00000040
191 #define ME4000_AI_CTRL_BIT_DATA_FIFO 0x00000080
192 #define ME4000_AI_CTRL_BIT_FULLSCALE 0x00000100
193 #define ME4000_AI_CTRL_BIT_OFFSET 0x00000200
194 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG 0x00000400
195 #define ME4000_AI_CTRL_BIT_EX_TRIG 0x00000800
196 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING 0x00001000
197 #define ME4000_AI_CTRL_BIT_EX_IRQ 0x00002000
198 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET 0x00004000
199 #define ME4000_AI_CTRL_BIT_LE_IRQ 0x00008000
200 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET 0x00010000
201 #define ME4000_AI_CTRL_BIT_HF_IRQ 0x00020000
202 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET 0x00040000
203 #define ME4000_AI_CTRL_BIT_SC_IRQ 0x00080000
204 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET 0x00100000
205 #define ME4000_AI_CTRL_BIT_SC_RELOAD 0x00200000
206 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH 0x80000000
208 /*=============================================================================
209 Bits for the ME4000_AI_STATUS_REG register
210 ===========================================================================*/
212 #define ME4000_AI_STATUS_BIT_EF_CHANNEL 0x00400000
213 #define ME4000_AI_STATUS_BIT_HF_CHANNEL 0x00800000
214 #define ME4000_AI_STATUS_BIT_FF_CHANNEL 0x01000000
215 #define ME4000_AI_STATUS_BIT_EF_DATA 0x02000000
216 #define ME4000_AI_STATUS_BIT_HF_DATA 0x04000000
217 #define ME4000_AI_STATUS_BIT_FF_DATA 0x08000000
218 #define ME4000_AI_STATUS_BIT_LE 0x10000000
219 #define ME4000_AI_STATUS_BIT_FSM 0x20000000
221 /*=============================================================================
222 Bits for the ME4000_IRQ_STATUS_REG register
223 ===========================================================================*/
225 #define ME4000_IRQ_STATUS_BIT_EX 0x01
226 #define ME4000_IRQ_STATUS_BIT_LE 0x02
227 #define ME4000_IRQ_STATUS_BIT_AI_HF 0x04
228 #define ME4000_IRQ_STATUS_BIT_AO_0_HF 0x08
229 #define ME4000_IRQ_STATUS_BIT_AO_1_HF 0x10
230 #define ME4000_IRQ_STATUS_BIT_AO_2_HF 0x20
231 #define ME4000_IRQ_STATUS_BIT_AO_3_HF 0x40
232 #define ME4000_IRQ_STATUS_BIT_SC 0x80
234 /*=============================================================================
235 Bits for the ME4000_DIO_CTRL_REG register
236 ===========================================================================*/
238 #define ME4000_DIO_CTRL_BIT_MODE_0 0x0001
239 #define ME4000_DIO_CTRL_BIT_MODE_1 0x0002
240 #define ME4000_DIO_CTRL_BIT_MODE_2 0x0004
241 #define ME4000_DIO_CTRL_BIT_MODE_3 0x0008
242 #define ME4000_DIO_CTRL_BIT_MODE_4 0x0010
243 #define ME4000_DIO_CTRL_BIT_MODE_5 0x0020
244 #define ME4000_DIO_CTRL_BIT_MODE_6 0x0040
245 #define ME4000_DIO_CTRL_BIT_MODE_7 0x0080
247 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 0x0100
248 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 0x0200
250 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 0x0400
251 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 0x0800
252 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 0x1000
253 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 0x2000
255 /*=============================================================================
256 Information about the hardware capabilities
257 ===========================================================================*/
259 struct me4000_ao_info {
264 struct me4000_ai_info {
271 struct me4000_dio_info {
275 struct me4000_cnt_info {
279 struct me4000_board {
281 unsigned short device_id;
282 struct me4000_ao_info ao;
283 struct me4000_ai_info ai;
284 struct me4000_dio_info dio;
285 struct me4000_cnt_info cnt;
288 #define thisboard ((const struct me4000_board *)dev->board_ptr)
290 /*=============================================================================
291 Global board and subdevice information structures
292 ===========================================================================*/
294 struct me4000_ao_context {
297 unsigned long mirror; /* Store the last written value */
299 unsigned long ctrl_reg;
300 unsigned long status_reg;
301 unsigned long fifo_reg;
302 unsigned long single_reg;
303 unsigned long timer_reg;
304 unsigned long irq_status_reg;
305 unsigned long preload_reg;
308 struct me4000_ai_context {
311 unsigned long ctrl_reg;
312 unsigned long status_reg;
313 unsigned long channel_list_reg;
314 unsigned long data_reg;
315 unsigned long chan_timer_reg;
316 unsigned long chan_pre_timer_reg;
317 unsigned long scan_timer_low_reg;
318 unsigned long scan_timer_high_reg;
319 unsigned long scan_pre_timer_low_reg;
320 unsigned long scan_pre_timer_high_reg;
321 unsigned long start_reg;
322 unsigned long irq_status_reg;
323 unsigned long sample_counter_reg;
326 struct me4000_dio_context {
327 unsigned long dir_reg;
328 unsigned long ctrl_reg;
329 unsigned long port_0_reg;
330 unsigned long port_1_reg;
331 unsigned long port_2_reg;
332 unsigned long port_3_reg;
335 struct me4000_cnt_context {
336 unsigned long ctrl_reg;
337 unsigned long counter_0_reg;
338 unsigned long counter_1_reg;
339 unsigned long counter_2_reg;
343 unsigned long plx_regbase; /* PLX configuration space base address */
344 unsigned long me4000_regbase; /* Base address of the ME4000 */
345 unsigned long timer_regbase; /* Base address of the timer circuit */
346 unsigned long program_regbase; /* Base address to set the program pin for the xilinx */
348 unsigned long plx_regbase_size; /* PLX register set space */
349 unsigned long me4000_regbase_size; /* ME4000 register set space */
350 unsigned long timer_regbase_size; /* Timer circuit register set space */
351 unsigned long program_regbase_size; /* Size of program base address of the ME4000 */
353 unsigned int serial_no; /* Serial number of the board */
354 unsigned char hw_revision; /* Hardware revision of the board */
355 unsigned short vendor_id; /* Meilhaus vendor id */
356 unsigned short device_id; /* Device id */
358 struct pci_dev *pci_dev_p; /* General PCI information */
360 unsigned int irq; /* IRQ assigned from the PCI BIOS */
362 struct me4000_ai_context ai_context; /* Analog input specific context */
363 struct me4000_ao_context ao_context[4]; /* Vector with analog output specific context */
364 struct me4000_dio_context dio_context; /* Digital I/O specific context */
365 struct me4000_cnt_context cnt_context; /* Counter specific context */
368 #define info ((struct me4000_info *)dev->private)
370 /*-----------------------------------------------------------------------------
371 Defines for analog input
372 ----------------------------------------------------------------------------*/
375 #define ME4000_AI_FIFO_COUNT 2048
377 #define ME4000_AI_MIN_TICKS 66
378 #define ME4000_AI_MIN_SAMPLE_TIME 2000 /* Minimum sample time [ns] */
379 #define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
381 /* Channel list defines and masks */
382 #define ME4000_AI_CHANNEL_LIST_COUNT 1024
384 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED 0x000
385 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL 0x020
387 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 0x000
388 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 0x040
389 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 0x080
390 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 0x0C0
392 #define ME4000_AI_LIST_LAST_ENTRY 0x100
394 /*-----------------------------------------------------------------------------
396 ----------------------------------------------------------------------------*/
398 #define ME4000_CNT_COUNTER_0 0x00
399 #define ME4000_CNT_COUNTER_1 0x40
400 #define ME4000_CNT_COUNTER_2 0x80
402 #define ME4000_CNT_MODE_0 0x00 /* Change state if zero crossing */
403 #define ME4000_CNT_MODE_1 0x02 /* Retriggerable One-Shot */
404 #define ME4000_CNT_MODE_2 0x04 /* Asymmetrical divider */
405 #define ME4000_CNT_MODE_3 0x06 /* Symmetrical divider */
406 #define ME4000_CNT_MODE_4 0x08 /* Counter start by software trigger */
407 #define ME4000_CNT_MODE_5 0x0A /* Counter start by hardware trigger */