2 * comedi/drivers/me_daq.c
3 * Hardware driver for Meilhaus data acquisition cards:
4 * ME-2000i, ME-2600i, ME-3000vm1
6 * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Meilhaus PCI data acquisition cards
22 * Devices: [Meilhaus] ME-2600i (me-2600i), ME-2000i (me-2000i)
23 * Author: Michael Hillmann <hillmann@syscongroup.de>
24 * Status: experimental
26 * Configuration options: not applicable, uses PCI auto config
29 * Analog Input, Analog Output, Digital I/O
32 #include <linux/module.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
36 #include "../comedi_pci.h"
40 #define ME2600_FIRMWARE "me2600_firmware.bin"
42 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
44 #define ME_CONTROL_1 0x0000 /* - | W */
45 #define INTERRUPT_ENABLE (1<<15)
46 #define COUNTER_B_IRQ (1<<12)
47 #define COUNTER_A_IRQ (1<<11)
48 #define CHANLIST_READY_IRQ (1<<10)
49 #define EXT_IRQ (1<<9)
50 #define ADFIFO_HALFFULL_IRQ (1<<8)
51 #define SCAN_COUNT_ENABLE (1<<5)
52 #define SIMULTANEOUS_ENABLE (1<<4)
53 #define TRIGGER_FALLING_EDGE (1<<3)
54 #define CONTINUOUS_MODE (1<<2)
55 #define DISABLE_ADC (0<<0)
56 #define SOFTWARE_TRIGGERED_ADC (1<<0)
57 #define SCAN_TRIGGERED_ADC (2<<0)
58 #define EXT_TRIGGERED_ADC (3<<0)
59 #define ME_ADC_START 0x0000 /* R | - */
60 #define ME_CONTROL_2 0x0002 /* - | W */
61 #define ENABLE_ADFIFO (1<<10)
62 #define ENABLE_CHANLIST (1<<9)
63 #define ENABLE_PORT_B (1<<7)
64 #define ENABLE_PORT_A (1<<6)
65 #define ENABLE_COUNTER_B (1<<4)
66 #define ENABLE_COUNTER_A (1<<3)
67 #define ENABLE_DAC (1<<1)
68 #define BUFFERED_DAC (1<<0)
69 #define ME_DAC_UPDATE 0x0002 /* R | - */
70 #define ME_STATUS 0x0004 /* R | - */
71 #define COUNTER_B_IRQ_PENDING (1<<12)
72 #define COUNTER_A_IRQ_PENDING (1<<11)
73 #define CHANLIST_READY_IRQ_PENDING (1<<10)
74 #define EXT_IRQ_PENDING (1<<9)
75 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
76 #define ADFIFO_FULL (1<<4)
77 #define ADFIFO_HALFFULL (1<<3)
78 #define ADFIFO_EMPTY (1<<2)
79 #define CHANLIST_FULL (1<<1)
80 #define FST_ACTIVE (1<<0)
81 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
82 #define ME_DIO_PORT_A 0x0006 /* R | W */
83 #define ME_DIO_PORT_B 0x0008 /* R | W */
84 #define ME_TIMER_DATA_0 0x000A /* - | W */
85 #define ME_TIMER_DATA_1 0x000C /* - | W */
86 #define ME_TIMER_DATA_2 0x000E /* - | W */
87 #define ME_CHANNEL_LIST 0x0010 /* - | W */
88 #define ADC_UNIPOLAR (1<<6)
89 #define ADC_GAIN_0 (0<<4)
90 #define ADC_GAIN_1 (1<<4)
91 #define ADC_GAIN_2 (2<<4)
92 #define ADC_GAIN_3 (3<<4)
93 #define ME_READ_AD_FIFO 0x0010 /* R | - */
94 #define ME_DAC_CONTROL 0x0012 /* - | W */
95 #define DAC_UNIPOLAR_D (0<<4)
96 #define DAC_BIPOLAR_D (1<<4)
97 #define DAC_UNIPOLAR_C (0<<5)
98 #define DAC_BIPOLAR_C (1<<5)
99 #define DAC_UNIPOLAR_B (0<<6)
100 #define DAC_BIPOLAR_B (1<<6)
101 #define DAC_UNIPOLAR_A (0<<7)
102 #define DAC_BIPOLAR_A (1<<7)
103 #define DAC_GAIN_0_D (0<<8)
104 #define DAC_GAIN_1_D (1<<8)
105 #define DAC_GAIN_0_C (0<<9)
106 #define DAC_GAIN_1_C (1<<9)
107 #define DAC_GAIN_0_B (0<<10)
108 #define DAC_GAIN_1_B (1<<10)
109 #define DAC_GAIN_0_A (0<<11)
110 #define DAC_GAIN_1_A (1<<11)
111 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
112 #define ME_DAC_DATA_A 0x0014 /* - | W */
113 #define ME_DAC_DATA_B 0x0016 /* - | W */
114 #define ME_DAC_DATA_C 0x0018 /* - | W */
115 #define ME_DAC_DATA_D 0x001A /* - | W */
116 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
117 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
118 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
119 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
120 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
121 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
123 static const struct comedi_lrange me_ai_range = {
136 static const struct comedi_lrange me_ao_range = {
155 static const struct me_board me_boards[] = {
166 struct me_private_data {
167 void __iomem *plx_regbase; /* PLX configuration base address */
169 unsigned short control_1; /* Mirror of CONTROL_1 register */
170 unsigned short control_2; /* Mirror of CONTROL_2 register */
171 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
174 static inline void sleep(unsigned sec)
176 schedule_timeout_interruptible(sec * HZ);
179 static int me_dio_insn_config(struct comedi_device *dev,
180 struct comedi_subdevice *s,
181 struct comedi_insn *insn,
184 struct me_private_data *devpriv = dev->private;
185 unsigned int chan = CR_CHAN(insn->chanspec);
194 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
198 if (s->io_bits & 0x0000ffff)
199 devpriv->control_2 |= ENABLE_PORT_A;
201 devpriv->control_2 &= ~ENABLE_PORT_A;
202 if (s->io_bits & 0xffff0000)
203 devpriv->control_2 |= ENABLE_PORT_B;
205 devpriv->control_2 &= ~ENABLE_PORT_B;
207 writew(devpriv->control_2, dev->mmio + ME_CONTROL_2);
212 static int me_dio_insn_bits(struct comedi_device *dev,
213 struct comedi_subdevice *s,
214 struct comedi_insn *insn,
217 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A;
218 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B;
222 mask = comedi_dio_update_state(s, data);
224 if (mask & 0x0000ffff)
225 writew((s->state & 0xffff), mmio_porta);
226 if (mask & 0xffff0000)
227 writew(((s->state >> 16) & 0xffff), mmio_portb);
230 if (s->io_bits & 0x0000ffff)
231 val = s->state & 0xffff;
233 val = readw(mmio_porta);
235 if (s->io_bits & 0xffff0000)
236 val |= (s->state & 0xffff0000);
238 val |= (readw(mmio_portb) << 16);
245 static int me_ai_eoc(struct comedi_device *dev,
246 struct comedi_subdevice *s,
247 struct comedi_insn *insn,
248 unsigned long context)
252 status = readw(dev->mmio + ME_STATUS);
253 if ((status & 0x0004) == 0)
258 static int me_ai_insn_read(struct comedi_device *dev,
259 struct comedi_subdevice *s,
260 struct comedi_insn *insn,
263 struct me_private_data *dev_private = dev->private;
264 unsigned int chan = CR_CHAN(insn->chanspec);
265 unsigned int rang = CR_RANGE(insn->chanspec);
266 unsigned int aref = CR_AREF(insn->chanspec);
270 /* stop any running conversion */
271 dev_private->control_1 &= 0xFFFC;
272 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
274 /* clear chanlist and ad fifo */
275 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
276 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
278 /* reset any pending interrupt */
279 writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
281 /* enable the chanlist and ADC fifo */
282 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
283 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
285 /* write to channel list fifo */
286 val = chan & 0x0f; /* b3:b0 channel */
287 val |= (rang & 0x03) << 4; /* b5:b4 gain */
288 val |= (rang & 0x04) << 4; /* b6 polarity */
289 val |= ((aref & AREF_DIFF) ? 0x80 : 0); /* b7 differential */
290 writew(val & 0xff, dev->mmio + ME_CHANNEL_LIST);
292 /* set ADC mode to software trigger */
293 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
294 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
296 /* start conversion by reading from ADC_START */
297 readw(dev->mmio + ME_ADC_START);
299 /* wait for ADC fifo not empty flag */
300 ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
304 /* get value from ADC fifo */
305 val = readw(dev->mmio + ME_READ_AD_FIFO);
306 val = (val ^ 0x800) & 0x0fff;
309 /* stop any running conversion */
310 dev_private->control_1 &= 0xFFFC;
311 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
316 static int me_ao_insn_write(struct comedi_device *dev,
317 struct comedi_subdevice *s,
318 struct comedi_insn *insn,
321 struct me_private_data *dev_private = dev->private;
322 unsigned int chan = CR_CHAN(insn->chanspec);
323 unsigned int rang = CR_RANGE(insn->chanspec);
324 unsigned int val = s->readback[chan];
328 dev_private->control_2 |= ENABLE_DAC;
329 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
331 /* and set DAC to "buffered" mode */
332 dev_private->control_2 |= BUFFERED_DAC;
333 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
335 /* Set dac-control register */
336 for (i = 0; i < insn->n; i++) {
337 /* clear bits for this channel */
338 dev_private->dac_control &= ~(0x0880 >> chan);
340 dev_private->dac_control |=
341 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
343 dev_private->dac_control |=
344 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
346 writew(dev_private->dac_control, dev->mmio + ME_DAC_CONTROL);
348 /* Update dac-control register */
349 readw(dev->mmio + ME_DAC_CONTROL_UPDATE);
351 /* Set data register */
352 for (i = 0; i < insn->n; i++) {
355 writew(val, dev->mmio + ME_DAC_DATA_A + (chan << 1));
357 s->readback[chan] = val;
359 /* Update dac with data registers */
360 readw(dev->mmio + ME_DAC_UPDATE);
365 static int me2600_xilinx_download(struct comedi_device *dev,
366 const u8 *data, size_t size,
367 unsigned long context)
369 struct me_private_data *dev_private = dev->private;
371 unsigned int file_length;
374 /* disable irq's on PLX */
375 writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
377 /* First, make a dummy read to reset xilinx */
378 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET);
380 /* Wait until reset is over */
383 /* Write a dummy value to Xilinx */
384 writeb(0x00, dev->mmio + 0x0);
388 * Format of the firmware
389 * Build longs from the byte-wise coded header
390 * Byte 1-3: length of the array
393 * Byte 12-15: reserved
398 file_length = (((unsigned int)data[0] & 0xff) << 24) +
399 (((unsigned int)data[1] & 0xff) << 16) +
400 (((unsigned int)data[2] & 0xff) << 8) +
401 ((unsigned int)data[3] & 0xff);
404 * Loop for writing firmware byte by byte to xilinx
405 * Firmware data start at offset 16
407 for (i = 0; i < file_length; i++)
408 writeb((data[16 + i] & 0xff), dev->mmio + 0x0);
410 /* Write 5 dummy values to xilinx */
411 for (i = 0; i < 5; i++)
412 writeb(0x00, dev->mmio + 0x0);
414 /* Test if there was an error during download -> INTB was thrown */
415 value = readl(dev_private->plx_regbase + PLX9052_INTCSR);
416 if (value & PLX9052_INTCSR_LI2STAT) {
417 /* Disable interrupt */
418 writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
419 dev_err(dev->class_dev, "Xilinx download failed\n");
423 /* Wait until the Xilinx is ready for real work */
426 /* Enable PLX-Interrupts */
427 writel(PLX9052_INTCSR_LI1ENAB |
428 PLX9052_INTCSR_LI1POL |
429 PLX9052_INTCSR_PCIENAB,
430 dev_private->plx_regbase + PLX9052_INTCSR);
435 static int me_reset(struct comedi_device *dev)
437 struct me_private_data *dev_private = dev->private;
440 writew(0x00, dev->mmio + ME_CONTROL_1);
441 writew(0x00, dev->mmio + ME_CONTROL_2);
442 writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
443 writew(0x00, dev->mmio + ME_DAC_CONTROL);
445 /* Save values in the board context */
446 dev_private->dac_control = 0;
447 dev_private->control_1 = 0;
448 dev_private->control_2 = 0;
453 static int me_auto_attach(struct comedi_device *dev,
454 unsigned long context)
456 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
457 const struct me_board *board = NULL;
458 struct me_private_data *dev_private;
459 struct comedi_subdevice *s;
462 if (context < ARRAY_SIZE(me_boards))
463 board = &me_boards[context];
466 dev->board_ptr = board;
467 dev->board_name = board->name;
469 dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private));
473 ret = comedi_pci_enable(dev);
477 dev_private->plx_regbase = pci_ioremap_bar(pcidev, 0);
478 if (!dev_private->plx_regbase)
481 dev->mmio = pci_ioremap_bar(pcidev, 2);
485 /* Download firmware and reset card */
486 if (board->needs_firmware) {
487 ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
489 me2600_xilinx_download, 0);
495 ret = comedi_alloc_subdevices(dev, 3);
499 s = &dev->subdevices[0];
500 s->type = COMEDI_SUBD_AI;
501 s->subdev_flags = SDF_READABLE | SDF_COMMON;
504 s->len_chanlist = 16;
505 s->range_table = &me_ai_range;
506 s->insn_read = me_ai_insn_read;
508 s = &dev->subdevices[1];
510 s->type = COMEDI_SUBD_AO;
511 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
515 s->range_table = &me_ao_range;
516 s->insn_write = me_ao_insn_write;
518 ret = comedi_alloc_subdev_readback(s);
522 s->type = COMEDI_SUBD_UNUSED;
525 s = &dev->subdevices[2];
526 s->type = COMEDI_SUBD_DIO;
527 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
530 s->len_chanlist = 32;
531 s->range_table = &range_digital;
532 s->insn_bits = me_dio_insn_bits;
533 s->insn_config = me_dio_insn_config;
538 static void me_detach(struct comedi_device *dev)
540 struct me_private_data *dev_private = dev->private;
545 if (dev_private->plx_regbase)
546 iounmap(dev_private->plx_regbase);
548 comedi_pci_detach(dev);
551 static struct comedi_driver me_daq_driver = {
552 .driver_name = "me_daq",
553 .module = THIS_MODULE,
554 .auto_attach = me_auto_attach,
558 static int me_daq_pci_probe(struct pci_dev *dev,
559 const struct pci_device_id *id)
561 return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
564 static const struct pci_device_id me_daq_pci_table[] = {
565 { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
566 { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
569 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
571 static struct pci_driver me_daq_pci_driver = {
573 .id_table = me_daq_pci_table,
574 .probe = me_daq_pci_probe,
575 .remove = comedi_pci_auto_unconfig,
577 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
579 MODULE_AUTHOR("Comedi http://www.comedi.org");
580 MODULE_DESCRIPTION("Comedi low-level driver");
581 MODULE_LICENSE("GPL");
582 MODULE_FIRMWARE(ME2600_FIRMWARE);