3 Hardware driver for NI Mite PCI interface chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 The PCI-MIO E series driver was originally written by
26 Tomasz Motylewski <...>, and ported to comedi by ds.
28 References for specifications:
30 321747b.pdf Register Level Programmer Manual (obsolete)
31 321747c.pdf Register Level Programmer Manual (new)
32 DAQ-STC reference manual
34 Other possibly relevant info:
36 320517c.pdf User manual (obsolete)
37 320517f.pdf User manual (new)
39 320906c.pdf maximum signal ratings
41 321791a.pdf discontinuation of at-mio-16e-10 rev. c
42 321808a.pdf about at-mio-16e-10 rev P
43 321837a.pdf discontinuation of at-mio-16de-10 rev d
44 321838a.pdf about at-mio-16de-10 rev N
50 /* #define USE_KMALLOC */
54 #include "comedi_fc.h"
55 #include "comedi_pci.h"
56 #include "../comedidev.h"
58 #include <asm/system.h>
60 #define PCI_MITE_SIZE 4096
61 #define PCI_DAQ_SIZE 4096
62 #define PCI_DAQ_SIZE_660X 8192
64 MODULE_LICENSE("GPL");
66 struct mite_struct *mite_devices;
67 EXPORT_SYMBOL(mite_devices);
69 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
73 struct pci_dev *pcidev;
74 struct mite_struct *mite;
76 for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
78 pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) {
79 if (pcidev->vendor == PCI_VENDOR_ID_NATINST) {
82 mite = kzalloc(sizeof(*mite), GFP_KERNEL);
84 printk(KERN_ERR "mite: allocation failed\n");
88 spin_lock_init(&mite->lock);
89 mite->pcidev = pci_dev_get(pcidev);
90 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
91 mite->channels[i].mite = mite;
92 mite->channels[i].channel = i;
93 mite->channels[i].done = 1;
95 mite->next = mite_devices;
101 static void dump_chip_signature(u32 csigr_bits)
103 printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
104 "interface mode = %i\n",
105 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
106 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
107 printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
108 "wins = %i, iowins = %i\n",
109 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
110 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
113 unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
115 unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
116 unsigned empty_count = (fcr_bits >> 16) & 0xff;
117 unsigned full_count = fcr_bits & 0xff;
118 return empty_count + full_count;
121 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
123 unsigned long length;
124 resource_size_t addr;
127 unsigned unknown_dma_burst_bits;
129 if (comedi_pci_enable(mite->pcidev, "mite")) {
130 printk(KERN_ERR "error enabling mite and requesting io regions\n");
133 pci_set_master(mite->pcidev);
135 addr = pci_resource_start(mite->pcidev, 0);
136 mite->mite_phys_addr = addr;
137 mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
138 if (!mite->mite_io_addr) {
139 printk(KERN_ERR "Failed to remap mite io memory address\n");
142 printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
143 (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
145 addr = pci_resource_start(mite->pcidev, 1);
146 mite->daq_phys_addr = addr;
147 length = pci_resource_len(mite->pcidev, 1);
149 * In case of a 660x board, DAQ size is 8k instead of 4k
150 * (see as shown by lspci output)
152 mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
153 if (!mite->daq_io_addr) {
154 printk(KERN_ERR "Failed to remap daq io memory address\n");
157 printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
158 (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
161 writel(0, mite->mite_io_addr + MITE_IODWBSR);
162 printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
163 writel(mite->daq_phys_addr | WENAB |
164 MITE_IODWBSR_1_WSIZE_bits(length),
165 mite->mite_io_addr + MITE_IODWBSR_1);
166 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
168 writel(mite->daq_phys_addr | WENAB,
169 mite->mite_io_addr + MITE_IODWBSR);
172 * make sure dma bursts work. I got this from running a bus analyzer
173 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
174 * of 0x61f and bursts worked. 6281 powered up with register value of
175 * 0x1f and bursts didn't work. The NI windows driver reads the
176 * register, then does a bitwise-or of 0x600 with it and writes it back.
178 unknown_dma_burst_bits =
179 readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
180 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
181 writel(unknown_dma_burst_bits,
182 mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
184 csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
185 mite->num_channels = mite_csigr_dmac(csigr_bits);
186 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
187 printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
188 "channels. Setting to %i.\n",
189 mite->num_channels, MAX_MITE_DMA_CHANNELS);
190 mite->num_channels = MAX_MITE_DMA_CHANNELS;
192 dump_chip_signature(csigr_bits);
193 for (i = 0; i < mite->num_channels; i++) {
194 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
195 /* disable interrupts */
196 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
197 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
198 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
199 mite->mite_io_addr + MITE_CHCR(i));
201 mite->fifo_size = mite_fifo_size(mite, 0);
202 printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
207 EXPORT_SYMBOL(mite_setup2);
209 int mite_setup(struct mite_struct *mite)
211 return mite_setup2(mite, 0);
213 EXPORT_SYMBOL(mite_setup);
215 void mite_cleanup(void)
217 struct mite_struct *mite, *next;
219 for (mite = mite_devices; mite; mite = next) {
220 pci_dev_put(mite->pcidev);
226 void mite_unsetup(struct mite_struct *mite)
228 /* unsigned long offset, start, length; */
233 if (mite->mite_io_addr) {
234 iounmap(mite->mite_io_addr);
235 mite->mite_io_addr = NULL;
237 if (mite->daq_io_addr) {
238 iounmap(mite->daq_io_addr);
239 mite->daq_io_addr = NULL;
241 if (mite->mite_phys_addr) {
242 comedi_pci_disable(mite->pcidev);
243 mite->mite_phys_addr = 0;
248 EXPORT_SYMBOL(mite_unsetup);
250 void mite_list_devices(void)
252 struct mite_struct *mite, *next;
254 printk(KERN_INFO "Available NI device IDs:");
256 for (mite = mite_devices; mite; mite = next) {
258 printk(KERN_INFO " 0x%04x", mite_device_id(mite));
260 printk(KERN_INFO "(used)");
262 printk(KERN_INFO "\n");
264 EXPORT_SYMBOL(mite_list_devices);
266 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
268 mite_dma_descriptor_ring
269 *ring, unsigned min_channel,
270 unsigned max_channel)
274 struct mite_channel *channel = NULL;
276 /* spin lock so mite_release_channel can be called safely
279 spin_lock_irqsave(&mite->lock, flags);
280 for (i = min_channel; i <= max_channel; ++i) {
281 if (mite->channel_allocated[i] == 0) {
282 mite->channel_allocated[i] = 1;
283 channel = &mite->channels[i];
284 channel->ring = ring;
288 spin_unlock_irqrestore(&mite->lock, flags);
291 EXPORT_SYMBOL(mite_request_channel_in_range);
293 void mite_release_channel(struct mite_channel *mite_chan)
295 struct mite_struct *mite = mite_chan->mite;
298 /* spin lock to prevent races with mite_request_channel */
299 spin_lock_irqsave(&mite->lock, flags);
300 if (mite->channel_allocated[mite_chan->channel]) {
301 mite_dma_disarm(mite_chan);
302 mite_dma_reset(mite_chan);
304 * disable all channel's interrupts (do it after disarm/reset so
305 * MITE_CHCR reg isn't changed while dma is still active!)
307 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
308 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
309 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
310 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
311 mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
312 mite->channel_allocated[mite_chan->channel] = 0;
313 mite_chan->ring = NULL;
316 spin_unlock_irqrestore(&mite->lock, flags);
318 EXPORT_SYMBOL(mite_release_channel);
320 void mite_dma_arm(struct mite_channel *mite_chan)
322 struct mite_struct *mite = mite_chan->mite;
326 MDPRINTK("mite_dma_arm ch%i\n", channel);
328 * memory barrier is intended to insure any twiddling with the buffer
329 * is done before writing to the mite to arm dma transfer
334 spin_lock_irqsave(&mite->lock, flags);
336 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
338 spin_unlock_irqrestore(&mite->lock, flags);
339 /* mite_dma_tcr(mite, channel); */
341 EXPORT_SYMBOL(mite_dma_arm);
343 /**************************************/
345 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
346 struct comedi_async *async)
348 unsigned int n_links;
351 if (ring->descriptors) {
352 dma_free_coherent(ring->hw_dev,
354 sizeof(struct mite_dma_descriptor),
356 ring->descriptors_dma_addr);
358 ring->descriptors = NULL;
359 ring->descriptors_dma_addr = 0;
362 if (async->prealloc_bufsz == 0)
365 n_links = async->prealloc_bufsz >> PAGE_SHIFT;
367 MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
370 dma_alloc_coherent(ring->hw_dev,
371 n_links * sizeof(struct mite_dma_descriptor),
372 &ring->descriptors_dma_addr, GFP_KERNEL);
373 if (!ring->descriptors) {
374 printk(KERN_ERR "mite: ring buffer allocation failed\n");
377 ring->n_links = n_links;
379 for (i = 0; i < n_links; i++) {
380 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
381 ring->descriptors[i].addr =
382 cpu_to_le32(async->buf_page_list[i].dma_addr);
383 ring->descriptors[i].next =
384 cpu_to_le32(ring->descriptors_dma_addr + (i +
386 sizeof(struct mite_dma_descriptor));
388 ring->descriptors[n_links - 1].next =
389 cpu_to_le32(ring->descriptors_dma_addr);
391 * barrier is meant to insure that all the writes to the dma descriptors
392 * have completed before the dma controller is commanded to read them
397 EXPORT_SYMBOL(mite_buf_change);
399 void mite_prep_dma(struct mite_channel *mite_chan,
400 unsigned int num_device_bits, unsigned int num_memory_bits)
402 unsigned int chor, chcr, mcr, dcr, lkcr;
403 struct mite_struct *mite = mite_chan->mite;
405 MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
407 /* reset DMA and FIFO */
408 chor = CHOR_DMARESET | CHOR_FRESET;
409 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
411 /* short link chaining mode */
412 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
415 * Link Complete Interrupt: interrupt every time a link
416 * in MITE_RING is completed. This can generate a lot of
417 * extra interrupts, but right now we update the values
418 * of buf_int_ptr and buf_int_count at each interrupt. A
419 * better method is to poll the MITE before each user
420 * "read()" to calculate the number of bytes available.
422 chcr |= CHCR_SET_LC_IE;
423 if (num_memory_bits == 32 && num_device_bits == 16) {
425 * Doing a combined 32 and 16 bit byteswap gets the 16 bit
426 * samples into the fifo in the right order. Tested doing 32 bit
427 * memory to 16 bit device transfers to the analog out of a
428 * pxi-6281, which has mite version = 1, type = 4. This also
429 * works for dma reads from the counters on e-series boards.
431 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
433 if (mite_chan->dir == COMEDI_INPUT)
434 chcr |= CHCR_DEV_TO_MEM;
436 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
439 mcr = CR_RL(64) | CR_ASEQUP;
440 switch (num_memory_bits) {
451 printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
455 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
458 dcr = CR_RL(64) | CR_ASEQUP;
459 dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
460 switch (num_device_bits) {
471 printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
475 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
478 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
480 /* the link is 32bits */
481 lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
482 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
484 /* starting address for link chaining */
485 writel(mite_chan->ring->descriptors_dma_addr,
486 mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
488 MDPRINTK("exit mite_prep_dma\n");
490 EXPORT_SYMBOL(mite_prep_dma);
492 u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
494 struct mite_struct *mite = mite_chan->mite;
495 return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
498 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
500 struct mite_struct *mite = mite_chan->mite;
501 return readl(mite->mite_io_addr +
502 MITE_FCR(mite_chan->channel)) & 0x000000FF;
504 EXPORT_SYMBOL(mite_bytes_in_transit);
506 /* returns lower bound for number of bytes transferred from device to memory */
507 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
509 u32 device_byte_count;
511 device_byte_count = mite_device_bytes_transferred(mite_chan);
512 return device_byte_count - mite_bytes_in_transit(mite_chan);
514 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
516 /* returns upper bound for number of bytes transferred from device to memory */
517 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
519 u32 in_transit_count;
521 in_transit_count = mite_bytes_in_transit(mite_chan);
522 return mite_device_bytes_transferred(mite_chan) - in_transit_count;
524 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
526 /* returns lower bound for number of bytes read from memory to device */
527 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
529 u32 device_byte_count;
531 device_byte_count = mite_device_bytes_transferred(mite_chan);
532 return device_byte_count + mite_bytes_in_transit(mite_chan);
534 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
536 /* returns upper bound for number of bytes read from memory to device */
537 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
539 u32 in_transit_count;
541 in_transit_count = mite_bytes_in_transit(mite_chan);
542 return mite_device_bytes_transferred(mite_chan) + in_transit_count;
544 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
546 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
548 struct mite_struct *mite = mite_chan->mite;
552 lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
553 tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
554 MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
559 EXPORT_SYMBOL(mite_dma_tcr);
561 void mite_dma_disarm(struct mite_channel *mite_chan)
563 struct mite_struct *mite = mite_chan->mite;
568 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
570 EXPORT_SYMBOL(mite_dma_disarm);
572 int mite_sync_input_dma(struct mite_channel *mite_chan,
573 struct comedi_async *async)
576 unsigned int nbytes, old_alloc_count;
577 const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
579 old_alloc_count = async->buf_write_alloc_count;
580 /* write alloc as much as we can */
581 comedi_buf_write_alloc(async, async->prealloc_bufsz);
583 nbytes = mite_bytes_written_to_memory_lb(mite_chan);
584 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
585 old_alloc_count) > 0) {
586 printk("mite: DMA overwrite of free area\n");
587 async->events |= COMEDI_CB_OVERFLOW;
591 count = nbytes - async->buf_write_count;
592 /* it's possible count will be negative due to
593 * conservative value returned by mite_bytes_written_to_memory_lb */
597 comedi_buf_write_free(async, count);
599 async->scan_progress += count;
600 if (async->scan_progress >= bytes_per_scan) {
601 async->scan_progress %= bytes_per_scan;
602 async->events |= COMEDI_CB_EOS;
604 async->events |= COMEDI_CB_BLOCK;
607 EXPORT_SYMBOL(mite_sync_input_dma);
609 int mite_sync_output_dma(struct mite_channel *mite_chan,
610 struct comedi_async *async)
613 u32 nbytes_ub, nbytes_lb;
614 unsigned int old_alloc_count;
616 async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
618 old_alloc_count = async->buf_read_alloc_count;
619 /* read alloc as much as we can */
620 comedi_buf_read_alloc(async, async->prealloc_bufsz);
621 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
622 if (async->cmd.stop_src == TRIG_COUNT &&
623 (int)(nbytes_lb - stop_count) > 0)
624 nbytes_lb = stop_count;
625 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
626 if (async->cmd.stop_src == TRIG_COUNT &&
627 (int)(nbytes_ub - stop_count) > 0)
628 nbytes_ub = stop_count;
629 if ((int)(nbytes_ub - old_alloc_count) > 0) {
630 printk(KERN_ERR "mite: DMA underrun\n");
631 async->events |= COMEDI_CB_OVERFLOW;
634 count = nbytes_lb - async->buf_read_count;
639 comedi_buf_read_free(async, count);
640 async->events |= COMEDI_CB_BLOCK;
644 EXPORT_SYMBOL(mite_sync_output_dma);
646 unsigned mite_get_status(struct mite_channel *mite_chan)
648 struct mite_struct *mite = mite_chan->mite;
652 spin_lock_irqsave(&mite->lock, flags);
653 status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
654 if (status & CHSR_DONE) {
657 mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
660 spin_unlock_irqrestore(&mite->lock, flags);
663 EXPORT_SYMBOL(mite_get_status);
665 int mite_done(struct mite_channel *mite_chan)
667 struct mite_struct *mite = mite_chan->mite;
671 mite_get_status(mite_chan);
672 spin_lock_irqsave(&mite->lock, flags);
673 done = mite_chan->done;
674 spin_unlock_irqrestore(&mite->lock, flags);
677 EXPORT_SYMBOL(mite_done);
681 static void mite_decode(char **bit_str, unsigned int bits);
683 /* names of bits in mite registers */
685 static const char *const mite_CHOR_strings[] = {
686 "start", "cont", "stop", "abort",
687 "freset", "clrlc", "clrrb", "clrdone",
688 "clr_lpause", "set_lpause", "clr_send_tc",
689 "set_send_tc", "12", "13", "14",
690 "15", "16", "17", "18",
691 "19", "20", "21", "22",
692 "23", "24", "25", "26",
693 "27", "28", "29", "30",
697 static const char *const mite_CHCR_strings[] = {
698 "continue", "ringbuff", "2", "3",
700 "8", "9", "10", "11",
701 "12", "13", "bursten", "fifodis",
702 "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
703 "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
704 "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
705 "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
708 static const char *const mite_MCR_strings[] = {
709 "amdevice", "1", "2", "3",
710 "4", "5", "portio", "portvxi",
711 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
712 "12", "13", "blocken", "berhand",
713 "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
714 "rd512", "rl1", "rl2", "rl8",
715 "24", "25", "26", "27",
716 "28", "29", "30", "stopen",
719 static const char *const mite_DCR_strings[] = {
720 "amdevice", "1", "2", "3",
721 "4", "5", "portio", "portvxi",
722 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
723 "aseqxp8", "13", "blocken", "berhand",
724 "reqsintlim", "reqs1", "reqs2", "rd32",
725 "rd512", "rl1", "rl2", "rl8",
726 "23", "24", "25", "27",
727 "28", "wsdevc", "wsdevs", "rwdevpack",
730 static const char *const mite_LKCR_strings[] = {
731 "amdevice", "1", "2", "3",
732 "4", "5", "portio", "portvxi",
733 "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
734 "12", "13", "14", "berhand",
735 "16", "17", "18", "rd32",
736 "rd512", "rl1", "rl2", "rl8",
737 "24", "25", "26", "27",
738 "28", "29", "30", "chngend",
741 static const char *const mite_CHSR_strings[] = {
742 "d.err0", "d.err1", "m.err0", "m.err1",
743 "l.err0", "l.err1", "drq0", "drq1",
744 "end", "xferr", "operr0", "operr1",
745 "stops", "habort", "sabort", "error",
746 "16", "conts_rb", "18", "linkc",
747 "20", "drdy", "22", "mrdy",
748 "24", "done", "26", "sars",
749 "28", "lpauses", "30", "int",
752 void mite_dump_regs(struct mite_channel *mite_chan)
754 unsigned long mite_io_addr =
755 (unsigned long)mite_chan->mite->mite_io_addr;
756 unsigned long addr = 0;
757 unsigned long temp = 0;
759 printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
760 printk(KERN_DEBUG "mite address is =0x%08lx\n", mite_io_addr);
762 addr = mite_io_addr + MITE_CHOR(channel);
763 printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
765 mite_decode(mite_CHOR_strings, temp);
766 addr = mite_io_addr + MITE_CHCR(channel);
767 printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
769 mite_decode(mite_CHCR_strings, temp);
770 addr = mite_io_addr + MITE_TCR(channel);
771 printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
773 addr = mite_io_addr + MITE_MCR(channel);
774 printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
776 mite_decode(mite_MCR_strings, temp);
778 addr = mite_io_addr + MITE_MAR(channel);
779 printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
781 addr = mite_io_addr + MITE_DCR(channel);
782 printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
784 mite_decode(mite_DCR_strings, temp);
785 addr = mite_io_addr + MITE_DAR(channel);
786 printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
788 addr = mite_io_addr + MITE_LKCR(channel);
789 printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
791 mite_decode(mite_LKCR_strings, temp);
792 addr = mite_io_addr + MITE_LKAR(channel);
793 printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
795 addr = mite_io_addr + MITE_CHSR(channel);
796 printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
798 mite_decode(mite_CHSR_strings, temp);
799 addr = mite_io_addr + MITE_FCR(channel);
800 printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
803 EXPORT_SYMBOL(mite_dump_regs);
805 static void mite_decode(char **bit_str, unsigned int bits)
809 for (i = 31; i >= 0; i--) {
811 printk(KERN_DEBUG " %s", bit_str[i]);
813 printk(KERN_DEBUG "\n");
815 EXPORT_SYMBOL(mite_decode);
819 int __init init_module(void)
827 void __exit cleanup_module(void)