drivers/staging/comedi/drivers/mite.c

   1 /*
   2     comedi/drivers/mite.c
   3     Hardware driver for NI Mite PCI interface chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18
  19 /*
  20         The PCI-MIO E series driver was originally written by
  21         Tomasz Motylewski <...>, and ported to comedi by ds.
  22
  23         References for specifications:
  24
  25            321747b.pdf  Register Level Programmer Manual (obsolete)
  26            321747c.pdf  Register Level Programmer Manual (new)
  27            DAQ-STC reference manual
  28
  29         Other possibly relevant info:
  30
  31            320517c.pdf  User manual (obsolete)
  32            320517f.pdf  User manual (new)
  33            320889a.pdf  delete
  34            320906c.pdf  maximum signal ratings
  35            321066a.pdf  about 16x
  36            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  37            321808a.pdf  about at-mio-16e-10 rev P
  38            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  39            321838a.pdf  about at-mio-16de-10 rev N
  40
  41         ISSUES:
  42
  43 */
  44
  45 /* #define USE_KMALLOC */
  46
  47 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  48
  49 #include <linux/module.h>
  50 #include <linux/pci.h>
  51
  52 #include "../comedidev.h"
  53
  54 #include "comedi_fc.h"
  55 #include "mite.h"
  56
  57 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  58
  59 struct mite_struct *mite_alloc(struct pci_dev *pcidev)
  60 {
  61         struct mite_struct *mite;
  62         unsigned int i;
  63
  64         mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  65         if (mite) {
  66                 spin_lock_init(&mite->lock);
  67                 mite->pcidev = pcidev;
  68                 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  69                         mite->channels[i].mite = mite;
  70                         mite->channels[i].channel = i;
  71                         mite->channels[i].done = 1;
  72                 }
  73         }
  74         return mite;
  75 }
  76 EXPORT_SYMBOL_GPL(mite_alloc);
  77
  78 static void dump_chip_signature(u32 csigr_bits)
  79 {
  80         pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
  81                 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
  82                 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
  83         pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
  84                 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
  85                 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
  86 }
  87
  88 static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
  89 {
  90         unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
  91         unsigned empty_count = (fcr_bits >> 16) & 0xff;
  92         unsigned full_count = fcr_bits & 0xff;
  93         return empty_count + full_count;
  94 }
  95
  96 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
  97 {
  98         unsigned long length;
  99         int i;
 100         u32 csigr_bits;
 101         unsigned unknown_dma_burst_bits;
 102
 103         pci_set_master(mite->pcidev);
 104
 105         mite->mite_io_addr = pci_ioremap_bar(mite->pcidev, 0);
 106         if (!mite->mite_io_addr) {
 107                 dev_err(&mite->pcidev->dev,
 108                         "Failed to remap mite io memory address\n");
 109                 return -ENOMEM;
 110         }
 111         mite->mite_phys_addr = pci_resource_start(mite->pcidev, 0);
 112
 113         mite->daq_io_addr = pci_ioremap_bar(mite->pcidev, 1);
 114         if (!mite->daq_io_addr) {
 115                 dev_err(&mite->pcidev->dev,
 116                         "Failed to remap daq io memory address\n");
 117                 return -ENOMEM;
 118         }
 119         mite->daq_phys_addr = pci_resource_start(mite->pcidev, 1);
 120         length = pci_resource_len(mite->pcidev, 1);
 121
 122         if (use_iodwbsr_1) {
 123                 writel(0, mite->mite_io_addr + MITE_IODWBSR);
 124                 dev_info(&mite->pcidev->dev,
 125                          "using I/O Window Base Size register 1\n");
 126                 writel(mite->daq_phys_addr | WENAB |
 127                        MITE_IODWBSR_1_WSIZE_bits(length),
 128                        mite->mite_io_addr + MITE_IODWBSR_1);
 129                 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
 130         } else {
 131                 writel(mite->daq_phys_addr | WENAB,
 132                        mite->mite_io_addr + MITE_IODWBSR);
 133         }
 134         /*
 135          * make sure dma bursts work. I got this from running a bus analyzer
 136          * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
 137          * of 0x61f and bursts worked. 6281 powered up with register value of
 138          * 0x1f and bursts didn't work. The NI windows driver reads the
 139          * register, then does a bitwise-or of 0x600 with it and writes it back.
 140          */
 141         unknown_dma_burst_bits =
 142             readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 143         unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
 144         writel(unknown_dma_burst_bits,
 145                mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 146
 147         csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
 148         mite->num_channels = mite_csigr_dmac(csigr_bits);
 149         if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
 150                 dev_warn(&mite->pcidev->dev,
 151                          "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
 152                          mite->num_channels, MAX_MITE_DMA_CHANNELS);
 153                 mite->num_channels = MAX_MITE_DMA_CHANNELS;
 154         }
 155         dump_chip_signature(csigr_bits);
 156         for (i = 0; i < mite->num_channels; i++) {
 157                 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
 158                 /* disable interrupts */
 159                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 160                        CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 161                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 162                        mite->mite_io_addr + MITE_CHCR(i));
 163         }
 164         mite->fifo_size = mite_fifo_size(mite, 0);
 165         dev_info(&mite->pcidev->dev, "fifo size is %i.\n", mite->fifo_size);
 166         return 0;
 167 }
 168 EXPORT_SYMBOL_GPL(mite_setup2);
 169
 170 int mite_setup(struct mite_struct *mite)
 171 {
 172         return mite_setup2(mite, 0);
 173 }
 174 EXPORT_SYMBOL_GPL(mite_setup);
 175
 176 void mite_unsetup(struct mite_struct *mite)
 177 {
 178         /* unsigned long offset, start, length; */
 179
 180         if (!mite)
 181                 return;
 182
 183         if (mite->mite_io_addr) {
 184                 iounmap(mite->mite_io_addr);
 185                 mite->mite_io_addr = NULL;
 186         }
 187         if (mite->daq_io_addr) {
 188                 iounmap(mite->daq_io_addr);
 189                 mite->daq_io_addr = NULL;
 190         }
 191         if (mite->mite_phys_addr)
 192                 mite->mite_phys_addr = 0;
 193 }
 194 EXPORT_SYMBOL_GPL(mite_unsetup);
 195
 196 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
 197 {
 198         struct mite_dma_descriptor_ring *ring =
 199             kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
 200
 201         if (ring == NULL)
 202                 return ring;
 203         ring->hw_dev = get_device(&mite->pcidev->dev);
 204         if (ring->hw_dev == NULL) {
 205                 kfree(ring);
 206                 return NULL;
 207         }
 208         ring->n_links = 0;
 209         ring->descriptors = NULL;
 210         ring->descriptors_dma_addr = 0;
 211         return ring;
 212 };
 213 EXPORT_SYMBOL_GPL(mite_alloc_ring);
 214
 215 void mite_free_ring(struct mite_dma_descriptor_ring *ring)
 216 {
 217         if (ring) {
 218                 if (ring->descriptors) {
 219                         dma_free_coherent(ring->hw_dev,
 220                                           ring->n_links *
 221                                           sizeof(struct mite_dma_descriptor),
 222                                           ring->descriptors,
 223                                           ring->descriptors_dma_addr);
 224                 }
 225                 put_device(ring->hw_dev);
 226                 kfree(ring);
 227         }
 228 };
 229 EXPORT_SYMBOL_GPL(mite_free_ring);
 230
 231 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
 232                                                    struct
 233                                                    mite_dma_descriptor_ring
 234                                                    *ring, unsigned min_channel,
 235                                                    unsigned max_channel)
 236 {
 237         int i;
 238         unsigned long flags;
 239         struct mite_channel *channel = NULL;
 240
 241         /* spin lock so mite_release_channel can be called safely
 242          * from interrupts
 243          */
 244         spin_lock_irqsave(&mite->lock, flags);
 245         for (i = min_channel; i <= max_channel; ++i) {
 246                 if (mite->channel_allocated[i] == 0) {
 247                         mite->channel_allocated[i] = 1;
 248                         channel = &mite->channels[i];
 249                         channel->ring = ring;
 250                         break;
 251                 }
 252         }
 253         spin_unlock_irqrestore(&mite->lock, flags);
 254         return channel;
 255 }
 256 EXPORT_SYMBOL_GPL(mite_request_channel_in_range);
 257
 258 void mite_release_channel(struct mite_channel *mite_chan)
 259 {
 260         struct mite_struct *mite = mite_chan->mite;
 261         unsigned long flags;
 262
 263         /*  spin lock to prevent races with mite_request_channel */
 264         spin_lock_irqsave(&mite->lock, flags);
 265         if (mite->channel_allocated[mite_chan->channel]) {
 266                 mite_dma_disarm(mite_chan);
 267                 mite_dma_reset(mite_chan);
 268         /*
 269          * disable all channel's interrupts (do it after disarm/reset so
 270          * MITE_CHCR reg isn't changed while dma is still active!)
 271          */
 272                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
 273                        CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
 274                        CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 275                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 276                        mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 277                 mite->channel_allocated[mite_chan->channel] = 0;
 278                 mite_chan->ring = NULL;
 279                 mmiowb();
 280         }
 281         spin_unlock_irqrestore(&mite->lock, flags);
 282 }
 283 EXPORT_SYMBOL_GPL(mite_release_channel);
 284
 285 void mite_dma_arm(struct mite_channel *mite_chan)
 286 {
 287         struct mite_struct *mite = mite_chan->mite;
 288         int chor;
 289         unsigned long flags;
 290
 291         MDPRINTK("mite_dma_arm ch%i\n", mite_chan->channel);
 292         /*
 293          * memory barrier is intended to insure any twiddling with the buffer
 294          * is done before writing to the mite to arm dma transfer
 295          */
 296         smp_mb();
 297         /* arm */
 298         chor = CHOR_START;
 299         spin_lock_irqsave(&mite->lock, flags);
 300         mite_chan->done = 0;
 301         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 302         mmiowb();
 303         spin_unlock_irqrestore(&mite->lock, flags);
 304 /*       mite_dma_tcr(mite, channel); */
 305 }
 306 EXPORT_SYMBOL_GPL(mite_dma_arm);
 307
 308 /**************************************/
 309
 310 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 311                     struct comedi_async *async)
 312 {
 313         unsigned int n_links;
 314         int i;
 315
 316         if (ring->descriptors) {
 317                 dma_free_coherent(ring->hw_dev,
 318                                   ring->n_links *
 319                                   sizeof(struct mite_dma_descriptor),
 320                                   ring->descriptors,
 321                                   ring->descriptors_dma_addr);
 322         }
 323         ring->descriptors = NULL;
 324         ring->descriptors_dma_addr = 0;
 325         ring->n_links = 0;
 326
 327         if (async->prealloc_bufsz == 0)
 328                 return 0;
 329
 330         n_links = async->prealloc_bufsz >> PAGE_SHIFT;
 331
 332         MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
 333
 334         ring->descriptors =
 335             dma_alloc_coherent(ring->hw_dev,
 336                                n_links * sizeof(struct mite_dma_descriptor),
 337                                &ring->descriptors_dma_addr, GFP_KERNEL);
 338         if (!ring->descriptors) {
 339                 dev_err(async->subdevice->device->class_dev,
 340                         "mite: ring buffer allocation failed\n");
 341                 return -ENOMEM;
 342         }
 343         ring->n_links = n_links;
 344
 345         for (i = 0; i < n_links; i++) {
 346                 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
 347                 ring->descriptors[i].addr =
 348                     cpu_to_le32(async->buf_page_list[i].dma_addr);
 349                 ring->descriptors[i].next =
 350                     cpu_to_le32(ring->descriptors_dma_addr + (i +
 351                                                               1) *
 352                                 sizeof(struct mite_dma_descriptor));
 353         }
 354         ring->descriptors[n_links - 1].next =
 355             cpu_to_le32(ring->descriptors_dma_addr);
 356         /*
 357          * barrier is meant to insure that all the writes to the dma descriptors
 358          * have completed before the dma controller is commanded to read them
 359          */
 360         smp_wmb();
 361         return 0;
 362 }
 363 EXPORT_SYMBOL_GPL(mite_buf_change);
 364
 365 void mite_prep_dma(struct mite_channel *mite_chan,
 366                    unsigned int num_device_bits, unsigned int num_memory_bits)
 367 {
 368         unsigned int chor, chcr, mcr, dcr, lkcr;
 369         struct mite_struct *mite = mite_chan->mite;
 370
 371         MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
 372
 373         /* reset DMA and FIFO */
 374         chor = CHOR_DMARESET | CHOR_FRESET;
 375         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 376
 377         /* short link chaining mode */
 378         chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
 379             CHCR_BURSTEN;
 380         /*
 381          * Link Complete Interrupt: interrupt every time a link
 382          * in MITE_RING is completed. This can generate a lot of
 383          * extra interrupts, but right now we update the values
 384          * of buf_int_ptr and buf_int_count at each interrupt. A
 385          * better method is to poll the MITE before each user
 386          * "read()" to calculate the number of bytes available.
 387          */
 388         chcr |= CHCR_SET_LC_IE;
 389         if (num_memory_bits == 32 && num_device_bits == 16) {
 390                 /*
 391                  * Doing a combined 32 and 16 bit byteswap gets the 16 bit
 392                  * samples into the fifo in the right order. Tested doing 32 bit
 393                  * memory to 16 bit device transfers to the analog out of a
 394                  * pxi-6281, which has mite version = 1, type = 4. This also
 395                  * works for dma reads from the counters on e-series boards.
 396                  */
 397                 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
 398         }
 399         if (mite_chan->dir == COMEDI_INPUT)
 400                 chcr |= CHCR_DEV_TO_MEM;
 401
 402         writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 403
 404         /* to/from memory */
 405         mcr = CR_RL(64) | CR_ASEQUP;
 406         switch (num_memory_bits) {
 407         case 8:
 408                 mcr |= CR_PSIZE8;
 409                 break;
 410         case 16:
 411                 mcr |= CR_PSIZE16;
 412                 break;
 413         case 32:
 414                 mcr |= CR_PSIZE32;
 415                 break;
 416         default:
 417                 pr_warn("bug! invalid mem bit width for dma transfer\n");
 418                 break;
 419         }
 420         writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
 421
 422         /* from/to device */
 423         dcr = CR_RL(64) | CR_ASEQUP;
 424         dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
 425         switch (num_device_bits) {
 426         case 8:
 427                 dcr |= CR_PSIZE8;
 428                 break;
 429         case 16:
 430                 dcr |= CR_PSIZE16;
 431                 break;
 432         case 32:
 433                 dcr |= CR_PSIZE32;
 434                 break;
 435         default:
 436                 pr_warn("bug! invalid dev bit width for dma transfer\n");
 437                 break;
 438         }
 439         writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
 440
 441         /* reset the DAR */
 442         writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 443
 444         /* the link is 32bits */
 445         lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
 446         writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
 447
 448         /* starting address for link chaining */
 449         writel(mite_chan->ring->descriptors_dma_addr,
 450                mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 451
 452         MDPRINTK("exit mite_prep_dma\n");
 453 }
 454 EXPORT_SYMBOL_GPL(mite_prep_dma);
 455
 456 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
 457 {
 458         struct mite_struct *mite = mite_chan->mite;
 459         return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 460 }
 461
 462 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
 463 {
 464         struct mite_struct *mite = mite_chan->mite;
 465         return readl(mite->mite_io_addr +
 466                      MITE_FCR(mite_chan->channel)) & 0x000000FF;
 467 }
 468 EXPORT_SYMBOL_GPL(mite_bytes_in_transit);
 469
 470 /* returns lower bound for number of bytes transferred from device to memory */
 471 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
 472 {
 473         u32 device_byte_count;
 474
 475         device_byte_count = mite_device_bytes_transferred(mite_chan);
 476         return device_byte_count - mite_bytes_in_transit(mite_chan);
 477 }
 478 EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_lb);
 479
 480 /* returns upper bound for number of bytes transferred from device to memory */
 481 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
 482 {
 483         u32 in_transit_count;
 484
 485         in_transit_count = mite_bytes_in_transit(mite_chan);
 486         return mite_device_bytes_transferred(mite_chan) - in_transit_count;
 487 }
 488 EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_ub);
 489
 490 /* returns lower bound for number of bytes read from memory to device */
 491 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
 492 {
 493         u32 device_byte_count;
 494
 495         device_byte_count = mite_device_bytes_transferred(mite_chan);
 496         return device_byte_count + mite_bytes_in_transit(mite_chan);
 497 }
 498 EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_lb);
 499
 500 /* returns upper bound for number of bytes read from memory to device */
 501 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
 502 {
 503         u32 in_transit_count;
 504
 505         in_transit_count = mite_bytes_in_transit(mite_chan);
 506         return mite_device_bytes_transferred(mite_chan) + in_transit_count;
 507 }
 508 EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_ub);
 509
 510 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
 511 {
 512         struct mite_struct *mite = mite_chan->mite;
 513         int tcr;
 514         int lkar;
 515
 516         lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 517         tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
 518         MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
 519                  lkar, tcr);
 520
 521         return tcr;
 522 }
 523 EXPORT_SYMBOL_GPL(mite_dma_tcr);
 524
 525 void mite_dma_disarm(struct mite_channel *mite_chan)
 526 {
 527         struct mite_struct *mite = mite_chan->mite;
 528         unsigned chor;
 529
 530         /* disarm */
 531         chor = CHOR_ABORT;
 532         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 533 }
 534 EXPORT_SYMBOL_GPL(mite_dma_disarm);
 535
 536 int mite_sync_input_dma(struct mite_channel *mite_chan,
 537                         struct comedi_async *async)
 538 {
 539         int count;
 540         unsigned int nbytes, old_alloc_count;
 541         const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
 542
 543         old_alloc_count = async->buf_write_alloc_count;
 544         /* write alloc as much as we can */
 545         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 546
 547         nbytes = mite_bytes_written_to_memory_lb(mite_chan);
 548         if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
 549                   old_alloc_count) > 0) {
 550                 dev_warn(async->subdevice->device->class_dev,
 551                          "mite: DMA overwrite of free area\n");
 552                 async->events |= COMEDI_CB_OVERFLOW;
 553                 return -1;
 554         }
 555
 556         count = nbytes - async->buf_write_count;
 557         /* it's possible count will be negative due to
 558          * conservative value returned by mite_bytes_written_to_memory_lb */
 559         if (count <= 0)
 560                 return 0;
 561
 562         comedi_buf_write_free(async, count);
 563
 564         async->scan_progress += count;
 565         if (async->scan_progress >= bytes_per_scan) {
 566                 async->scan_progress %= bytes_per_scan;
 567                 async->events |= COMEDI_CB_EOS;
 568         }
 569         async->events |= COMEDI_CB_BLOCK;
 570         return 0;
 571 }
 572 EXPORT_SYMBOL_GPL(mite_sync_input_dma);
 573
 574 int mite_sync_output_dma(struct mite_channel *mite_chan,
 575                          struct comedi_async *async)
 576 {
 577         int count;
 578         u32 nbytes_ub, nbytes_lb;
 579         unsigned int old_alloc_count;
 580         u32 stop_count =
 581             async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
 582
 583         old_alloc_count = async->buf_read_alloc_count;
 584         /*  read alloc as much as we can */
 585         comedi_buf_read_alloc(async, async->prealloc_bufsz);
 586         nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
 587         if (async->cmd.stop_src == TRIG_COUNT &&
 588             (int)(nbytes_lb - stop_count) > 0)
 589                 nbytes_lb = stop_count;
 590         nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
 591         if (async->cmd.stop_src == TRIG_COUNT &&
 592             (int)(nbytes_ub - stop_count) > 0)
 593                 nbytes_ub = stop_count;
 594         if ((int)(nbytes_ub - old_alloc_count) > 0) {
 595                 dev_warn(async->subdevice->device->class_dev,
 596                          "mite: DMA underrun\n");
 597                 async->events |= COMEDI_CB_OVERFLOW;
 598                 return -1;
 599         }
 600         count = nbytes_lb - async->buf_read_count;
 601         if (count <= 0)
 602                 return 0;
 603
 604         if (count) {
 605                 comedi_buf_read_free(async, count);
 606                 async->events |= COMEDI_CB_BLOCK;
 607         }
 608         return 0;
 609 }
 610 EXPORT_SYMBOL_GPL(mite_sync_output_dma);
 611
 612 unsigned mite_get_status(struct mite_channel *mite_chan)
 613 {
 614         struct mite_struct *mite = mite_chan->mite;
 615         unsigned status;
 616         unsigned long flags;
 617
 618         spin_lock_irqsave(&mite->lock, flags);
 619         status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 620         if (status & CHSR_DONE) {
 621                 mite_chan->done = 1;
 622                 writel(CHOR_CLRDONE,
 623                        mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 624         }
 625         mmiowb();
 626         spin_unlock_irqrestore(&mite->lock, flags);
 627         return status;
 628 }
 629 EXPORT_SYMBOL_GPL(mite_get_status);
 630
 631 int mite_done(struct mite_channel *mite_chan)
 632 {
 633         struct mite_struct *mite = mite_chan->mite;
 634         unsigned long flags;
 635         int done;
 636
 637         mite_get_status(mite_chan);
 638         spin_lock_irqsave(&mite->lock, flags);
 639         done = mite_chan->done;
 640         spin_unlock_irqrestore(&mite->lock, flags);
 641         return done;
 642 }
 643 EXPORT_SYMBOL_GPL(mite_done);
 644
 645 #ifdef DEBUG_MITE
 646
 647 /* names of bits in mite registers */
 648
 649 static const char *const mite_CHOR_strings[] = {
 650         "start", "cont", "stop", "abort",
 651         "freset", "clrlc", "clrrb", "clrdone",
 652         "clr_lpause", "set_lpause", "clr_send_tc",
 653         "set_send_tc", "12", "13", "14",
 654         "15", "16", "17", "18",
 655         "19", "20", "21", "22",
 656         "23", "24", "25", "26",
 657         "27", "28", "29", "30",
 658         "dmareset",
 659 };
 660
 661 static const char *const mite_CHCR_strings[] = {
 662         "continue", "ringbuff", "2", "3",
 663         "4", "5", "6", "7",
 664         "8", "9", "10", "11",
 665         "12", "13", "bursten", "fifodis",
 666         "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
 667         "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
 668         "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
 669         "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
 670 };
 671
 672 static const char *const mite_MCR_strings[] = {
 673         "amdevice", "1", "2", "3",
 674         "4", "5", "portio", "portvxi",
 675         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
 676         "12", "13", "blocken", "berhand",
 677         "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
 678         "rd512", "rl1", "rl2", "rl8",
 679         "24", "25", "26", "27",
 680         "28", "29", "30", "stopen",
 681 };
 682
 683 static const char *const mite_DCR_strings[] = {
 684         "amdevice", "1", "2", "3",
 685         "4", "5", "portio", "portvxi",
 686         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
 687         "aseqxp8", "13", "blocken", "berhand",
 688         "reqsintlim", "reqs1", "reqs2", "rd32",
 689         "rd512", "rl1", "rl2", "rl8",
 690         "23", "24", "25", "27",
 691         "28", "wsdevc", "wsdevs", "rwdevpack",
 692 };
 693
 694 static const char *const mite_LKCR_strings[] = {
 695         "amdevice", "1", "2", "3",
 696         "4", "5", "portio", "portvxi",
 697         "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
 698         "12", "13", "14", "berhand",
 699         "16", "17", "18", "rd32",
 700         "rd512", "rl1", "rl2", "rl8",
 701         "24", "25", "26", "27",
 702         "28", "29", "30", "chngend",
 703 };
 704
 705 static const char *const mite_CHSR_strings[] = {
 706         "d.err0", "d.err1", "m.err0", "m.err1",
 707         "l.err0", "l.err1", "drq0", "drq1",
 708         "end", "xferr", "operr0", "operr1",
 709         "stops", "habort", "sabort", "error",
 710         "16", "conts_rb", "18", "linkc",
 711         "20", "drdy", "22", "mrdy",
 712         "24", "done", "26", "sars",
 713         "28", "lpauses", "30", "int",
 714 };
 715
 716 static void mite_decode(const char *const *bit_str, unsigned int bits)
 717 {
 718         int i;
 719
 720         for (i = 31; i >= 0; i--) {
 721                 if (bits & (1 << i))
 722                         pr_debug(" %s\n", bit_str[i]);
 723         }
 724 }
 725
 726 void mite_dump_regs(struct mite_channel *mite_chan)
 727 {
 728         void __iomem *mite_io_addr = mite_chan->mite->mite_io_addr;
 729         unsigned int offset;
 730         unsigned int value;
 731         int channel = mite_chan->channel;
 732
 733         pr_debug("mite_dump_regs ch%i\n", channel);
 734         pr_debug("mite address is  =%p\n", mite_io_addr);
 735
 736         offset = MITE_CHOR(channel);
 737         value = readl(mite_io_addr + offset);
 738         pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset, value);
 739         mite_decode(mite_CHOR_strings, value);
 740         offset = MITE_CHCR(channel);
 741         value = readl(mite_io_addr + offset);
 742         pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset, value);
 743         mite_decode(mite_CHCR_strings, value);
 744         offset = MITE_TCR(channel);
 745         value = readl(mite_io_addr + offset);
 746         pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset, value);
 747         offset = MITE_MCR(channel);
 748         value = readl(mite_io_addr + offset);
 749         pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset, value);
 750         mite_decode(mite_MCR_strings, value);
 751         offset = MITE_MAR(channel);
 752         value = readl(mite_io_addr + offset);
 753         pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset, value);
 754         offset = MITE_DCR(channel);
 755         value = readl(mite_io_addr + offset);
 756         pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset, value);
 757         mite_decode(mite_DCR_strings, value);
 758         offset = MITE_DAR(channel);
 759         value = readl(mite_io_addr + offset);
 760         pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset, value);
 761         offset = MITE_LKCR(channel);
 762         value = readl(mite_io_addr + offset);
 763         pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset, value);
 764         mite_decode(mite_LKCR_strings, value);
 765         offset = MITE_LKAR(channel);
 766         value = readl(mite_io_addr + offset);
 767         pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset, value);
 768         offset = MITE_CHSR(channel);
 769         value = readl(mite_io_addr + offset);
 770         pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset, value);
 771         mite_decode(mite_CHSR_strings, value);
 772         offset = MITE_FCR(channel);
 773         value = readl(mite_io_addr + offset);
 774         pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset, value);
 775 }
 776 EXPORT_SYMBOL_GPL(mite_dump_regs);
 777 #endif
 778
 779 static int __init mite_module_init(void)
 780 {
 781         return 0;
 782 }
 783
 784 static void __exit mite_module_exit(void)
 785 {
 786 }
 787
 788 module_init(mite_module_init);
 789 module_exit(mite_module_exit);
 790
 791 MODULE_AUTHOR("Comedi http://www.comedi.org");
 792 MODULE_DESCRIPTION("Comedi low-level driver");
 793 MODULE_LICENSE("GPL");