drivers/staging/comedi/drivers/mite.c

   1 /*
   2     comedi/drivers/mite.c
   3     Hardware driver for NI Mite PCI interface chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 /*
  25         The PCI-MIO E series driver was originally written by
  26         Tomasz Motylewski <...>, and ported to comedi by ds.
  27
  28         References for specifications:
  29
  30            321747b.pdf  Register Level Programmer Manual (obsolete)
  31            321747c.pdf  Register Level Programmer Manual (new)
  32            DAQ-STC reference manual
  33
  34         Other possibly relevant info:
  35
  36            320517c.pdf  User manual (obsolete)
  37            320517f.pdf  User manual (new)
  38            320889a.pdf  delete
  39            320906c.pdf  maximum signal ratings
  40            321066a.pdf  about 16x
  41            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  42            321808a.pdf  about at-mio-16e-10 rev P
  43            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  44            321838a.pdf  about at-mio-16de-10 rev N
  45
  46         ISSUES:
  47
  48 */
  49
  50 /* #define USE_KMALLOC */
  51
  52 #include "mite.h"
  53
  54 #include "comedi_fc.h"
  55 #include "../comedidev.h"
  56
  57
  58 #define PCI_MITE_SIZE           4096
  59 #define PCI_DAQ_SIZE            4096
  60 #define PCI_DAQ_SIZE_660X       8192
  61
  62 struct mite_struct *mite_devices;
  63 EXPORT_SYMBOL(mite_devices);
  64
  65 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  66
  67 void mite_init(void)
  68 {
  69         struct pci_dev *pcidev = NULL;
  70         struct mite_struct *mite;
  71
  72         for_each_pci_dev(pcidev) {
  73                 if (pcidev->vendor == PCI_VENDOR_ID_NI) {
  74                         unsigned i;
  75
  76                         mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  77                         if (!mite) {
  78                                 printk(KERN_ERR "mite: allocation failed\n");
  79                                 pci_dev_put(pcidev);
  80                                 return;
  81                         }
  82                         spin_lock_init(&mite->lock);
  83                         mite->pcidev = pci_dev_get(pcidev);
  84                         for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  85                                 mite->channels[i].mite = mite;
  86                                 mite->channels[i].channel = i;
  87                                 mite->channels[i].done = 1;
  88                         }
  89                         mite->next = mite_devices;
  90                         mite_devices = mite;
  91                 }
  92         }
  93 }
  94
  95 static void dump_chip_signature(u32 csigr_bits)
  96 {
  97         printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
  98                "interface mode = %i\n",
  99                mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
 100                mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
 101         printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
 102                "wins = %i, iowins = %i\n",
 103                mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
 104                mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
 105 }
 106
 107 unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
 108 {
 109         unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
 110         unsigned empty_count = (fcr_bits >> 16) & 0xff;
 111         unsigned full_count = fcr_bits & 0xff;
 112         return empty_count + full_count;
 113 }
 114
 115 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
 116 {
 117         unsigned long length;
 118         resource_size_t addr;
 119         int i;
 120         u32 csigr_bits;
 121         unsigned unknown_dma_burst_bits;
 122
 123         if (comedi_pci_enable(mite->pcidev, "mite")) {
 124                 printk(KERN_ERR "error enabling mite and requesting io regions\n");
 125                 return -EIO;
 126         }
 127         pci_set_master(mite->pcidev);
 128
 129         addr = pci_resource_start(mite->pcidev, 0);
 130         mite->mite_phys_addr = addr;
 131         mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
 132         if (!mite->mite_io_addr) {
 133                 printk(KERN_ERR "Failed to remap mite io memory address\n");
 134                 return -ENOMEM;
 135         }
 136         printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
 137                (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
 138
 139         addr = pci_resource_start(mite->pcidev, 1);
 140         mite->daq_phys_addr = addr;
 141         length = pci_resource_len(mite->pcidev, 1);
 142         /*
 143          * In case of a 660x board, DAQ size is 8k instead of 4k
 144          * (see as shown by lspci output)
 145          */
 146         mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
 147         if (!mite->daq_io_addr) {
 148                 printk(KERN_ERR "Failed to remap daq io memory address\n");
 149                 return -ENOMEM;
 150         }
 151         printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
 152                (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
 153
 154         if (use_iodwbsr_1) {
 155                 writel(0, mite->mite_io_addr + MITE_IODWBSR);
 156                 printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
 157                 writel(mite->daq_phys_addr | WENAB |
 158                        MITE_IODWBSR_1_WSIZE_bits(length),
 159                        mite->mite_io_addr + MITE_IODWBSR_1);
 160                 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
 161         } else {
 162                 writel(mite->daq_phys_addr | WENAB,
 163                        mite->mite_io_addr + MITE_IODWBSR);
 164         }
 165         /*
 166          * make sure dma bursts work. I got this from running a bus analyzer
 167          * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
 168          * of 0x61f and bursts worked. 6281 powered up with register value of
 169          * 0x1f and bursts didn't work. The NI windows driver reads the
 170          * register, then does a bitwise-or of 0x600 with it and writes it back.
 171          */
 172         unknown_dma_burst_bits =
 173             readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 174         unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
 175         writel(unknown_dma_burst_bits,
 176                mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 177
 178         csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
 179         mite->num_channels = mite_csigr_dmac(csigr_bits);
 180         if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
 181                 printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
 182                        "channels. Setting to %i.\n",
 183                        mite->num_channels, MAX_MITE_DMA_CHANNELS);
 184                 mite->num_channels = MAX_MITE_DMA_CHANNELS;
 185         }
 186         dump_chip_signature(csigr_bits);
 187         for (i = 0; i < mite->num_channels; i++) {
 188                 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
 189                 /* disable interrupts */
 190                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 191                        CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 192                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 193                        mite->mite_io_addr + MITE_CHCR(i));
 194         }
 195         mite->fifo_size = mite_fifo_size(mite, 0);
 196         printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
 197         mite->used = 1;
 198
 199         return 0;
 200 }
 201 EXPORT_SYMBOL(mite_setup2);
 202
 203 int mite_setup(struct mite_struct *mite)
 204 {
 205         return mite_setup2(mite, 0);
 206 }
 207 EXPORT_SYMBOL(mite_setup);
 208
 209 void mite_cleanup(void)
 210 {
 211         struct mite_struct *mite, *next;
 212
 213         for (mite = mite_devices; mite; mite = next) {
 214                 pci_dev_put(mite->pcidev);
 215                 next = mite->next;
 216                 kfree(mite);
 217         }
 218 }
 219
 220 void mite_unsetup(struct mite_struct *mite)
 221 {
 222         /* unsigned long offset, start, length; */
 223
 224         if (!mite)
 225                 return;
 226
 227         if (mite->mite_io_addr) {
 228                 iounmap(mite->mite_io_addr);
 229                 mite->mite_io_addr = NULL;
 230         }
 231         if (mite->daq_io_addr) {
 232                 iounmap(mite->daq_io_addr);
 233                 mite->daq_io_addr = NULL;
 234         }
 235         if (mite->mite_phys_addr) {
 236                 comedi_pci_disable(mite->pcidev);
 237                 mite->mite_phys_addr = 0;
 238         }
 239
 240         mite->used = 0;
 241 }
 242 EXPORT_SYMBOL(mite_unsetup);
 243
 244 void mite_list_devices(void)
 245 {
 246         struct mite_struct *mite, *next;
 247
 248         printk(KERN_INFO "Available NI device IDs:");
 249         if (mite_devices)
 250                 for (mite = mite_devices; mite; mite = next) {
 251                         next = mite->next;
 252                         printk(KERN_INFO " 0x%04x", mite_device_id(mite));
 253                         if (mite->used)
 254                                 printk(KERN_INFO "(used)");
 255                 }
 256         printk(KERN_INFO "\n");
 257 }
 258 EXPORT_SYMBOL(mite_list_devices);
 259
 260 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
 261                                                    struct
 262                                                    mite_dma_descriptor_ring
 263                                                    *ring, unsigned min_channel,
 264                                                    unsigned max_channel)
 265 {
 266         int i;
 267         unsigned long flags;
 268         struct mite_channel *channel = NULL;
 269
 270         /* spin lock so mite_release_channel can be called safely
 271          * from interrupts
 272          */
 273         spin_lock_irqsave(&mite->lock, flags);
 274         for (i = min_channel; i <= max_channel; ++i) {
 275                 if (mite->channel_allocated[i] == 0) {
 276                         mite->channel_allocated[i] = 1;
 277                         channel = &mite->channels[i];
 278                         channel->ring = ring;
 279                         break;
 280                 }
 281         }
 282         spin_unlock_irqrestore(&mite->lock, flags);
 283         return channel;
 284 }
 285 EXPORT_SYMBOL(mite_request_channel_in_range);
 286
 287 void mite_release_channel(struct mite_channel *mite_chan)
 288 {
 289         struct mite_struct *mite = mite_chan->mite;
 290         unsigned long flags;
 291
 292         /*  spin lock to prevent races with mite_request_channel */
 293         spin_lock_irqsave(&mite->lock, flags);
 294         if (mite->channel_allocated[mite_chan->channel]) {
 295                 mite_dma_disarm(mite_chan);
 296                 mite_dma_reset(mite_chan);
 297         /*
 298          * disable all channel's interrupts (do it after disarm/reset so
 299          * MITE_CHCR reg isn't changed while dma is still active!)
 300          */
 301                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
 302                        CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
 303                        CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 304                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 305                        mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 306                 mite->channel_allocated[mite_chan->channel] = 0;
 307                 mite_chan->ring = NULL;
 308                 mmiowb();
 309         }
 310         spin_unlock_irqrestore(&mite->lock, flags);
 311 }
 312 EXPORT_SYMBOL(mite_release_channel);
 313
 314 void mite_dma_arm(struct mite_channel *mite_chan)
 315 {
 316         struct mite_struct *mite = mite_chan->mite;
 317         int chor;
 318         unsigned long flags;
 319
 320         MDPRINTK("mite_dma_arm ch%i\n", channel);
 321         /*
 322          * memory barrier is intended to insure any twiddling with the buffer
 323          * is done before writing to the mite to arm dma transfer
 324          */
 325         smp_mb();
 326         /* arm */
 327         chor = CHOR_START;
 328         spin_lock_irqsave(&mite->lock, flags);
 329         mite_chan->done = 0;
 330         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 331         mmiowb();
 332         spin_unlock_irqrestore(&mite->lock, flags);
 333 /*       mite_dma_tcr(mite, channel); */
 334 }
 335 EXPORT_SYMBOL(mite_dma_arm);
 336
 337 /**************************************/
 338
 339 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 340                     struct comedi_async *async)
 341 {
 342         unsigned int n_links;
 343         int i;
 344
 345         if (ring->descriptors) {
 346                 dma_free_coherent(ring->hw_dev,
 347                                   ring->n_links *
 348                                   sizeof(struct mite_dma_descriptor),
 349                                   ring->descriptors,
 350                                   ring->descriptors_dma_addr);
 351         }
 352         ring->descriptors = NULL;
 353         ring->descriptors_dma_addr = 0;
 354         ring->n_links = 0;
 355
 356         if (async->prealloc_bufsz == 0)
 357                 return 0;
 358
 359         n_links = async->prealloc_bufsz >> PAGE_SHIFT;
 360
 361         MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
 362
 363         ring->descriptors =
 364             dma_alloc_coherent(ring->hw_dev,
 365                                n_links * sizeof(struct mite_dma_descriptor),
 366                                &ring->descriptors_dma_addr, GFP_KERNEL);
 367         if (!ring->descriptors) {
 368                 printk(KERN_ERR "mite: ring buffer allocation failed\n");
 369                 return -ENOMEM;
 370         }
 371         ring->n_links = n_links;
 372
 373         for (i = 0; i < n_links; i++) {
 374                 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
 375                 ring->descriptors[i].addr =
 376                     cpu_to_le32(async->buf_page_list[i].dma_addr);
 377                 ring->descriptors[i].next =
 378                     cpu_to_le32(ring->descriptors_dma_addr + (i +
 379                                                               1) *
 380                                 sizeof(struct mite_dma_descriptor));
 381         }
 382         ring->descriptors[n_links - 1].next =
 383             cpu_to_le32(ring->descriptors_dma_addr);
 384         /*
 385          * barrier is meant to insure that all the writes to the dma descriptors
 386          * have completed before the dma controller is commanded to read them
 387          */
 388         smp_wmb();
 389         return 0;
 390 }
 391 EXPORT_SYMBOL(mite_buf_change);
 392
 393 void mite_prep_dma(struct mite_channel *mite_chan,
 394                    unsigned int num_device_bits, unsigned int num_memory_bits)
 395 {
 396         unsigned int chor, chcr, mcr, dcr, lkcr;
 397         struct mite_struct *mite = mite_chan->mite;
 398
 399         MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
 400
 401         /* reset DMA and FIFO */
 402         chor = CHOR_DMARESET | CHOR_FRESET;
 403         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 404
 405         /* short link chaining mode */
 406         chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
 407             CHCR_BURSTEN;
 408         /*
 409          * Link Complete Interrupt: interrupt every time a link
 410          * in MITE_RING is completed. This can generate a lot of
 411          * extra interrupts, but right now we update the values
 412          * of buf_int_ptr and buf_int_count at each interrupt. A
 413          * better method is to poll the MITE before each user
 414          * "read()" to calculate the number of bytes available.
 415          */
 416         chcr |= CHCR_SET_LC_IE;
 417         if (num_memory_bits == 32 && num_device_bits == 16) {
 418                 /*
 419                  * Doing a combined 32 and 16 bit byteswap gets the 16 bit
 420                  * samples into the fifo in the right order. Tested doing 32 bit
 421                  * memory to 16 bit device transfers to the analog out of a
 422                  * pxi-6281, which has mite version = 1, type = 4. This also
 423                  * works for dma reads from the counters on e-series boards.
 424                  */
 425                 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
 426         }
 427         if (mite_chan->dir == COMEDI_INPUT)
 428                 chcr |= CHCR_DEV_TO_MEM;
 429
 430         writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 431
 432         /* to/from memory */
 433         mcr = CR_RL(64) | CR_ASEQUP;
 434         switch (num_memory_bits) {
 435         case 8:
 436                 mcr |= CR_PSIZE8;
 437                 break;
 438         case 16:
 439                 mcr |= CR_PSIZE16;
 440                 break;
 441         case 32:
 442                 mcr |= CR_PSIZE32;
 443                 break;
 444         default:
 445                 printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
 446                        "transfer\n");
 447                 break;
 448         }
 449         writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
 450
 451         /* from/to device */
 452         dcr = CR_RL(64) | CR_ASEQUP;
 453         dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
 454         switch (num_device_bits) {
 455         case 8:
 456                 dcr |= CR_PSIZE8;
 457                 break;
 458         case 16:
 459                 dcr |= CR_PSIZE16;
 460                 break;
 461         case 32:
 462                 dcr |= CR_PSIZE32;
 463                 break;
 464         default:
 465                 printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
 466                        "transfer\n");
 467                 break;
 468         }
 469         writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
 470
 471         /* reset the DAR */
 472         writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 473
 474         /* the link is 32bits */
 475         lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
 476         writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
 477
 478         /* starting address for link chaining */
 479         writel(mite_chan->ring->descriptors_dma_addr,
 480                mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 481
 482         MDPRINTK("exit mite_prep_dma\n");
 483 }
 484 EXPORT_SYMBOL(mite_prep_dma);
 485
 486 u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
 487 {
 488         struct mite_struct *mite = mite_chan->mite;
 489         return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 490 }
 491
 492 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
 493 {
 494         struct mite_struct *mite = mite_chan->mite;
 495         return readl(mite->mite_io_addr +
 496                      MITE_FCR(mite_chan->channel)) & 0x000000FF;
 497 }
 498 EXPORT_SYMBOL(mite_bytes_in_transit);
 499
 500 /* returns lower bound for number of bytes transferred from device to memory */
 501 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
 502 {
 503         u32 device_byte_count;
 504
 505         device_byte_count = mite_device_bytes_transferred(mite_chan);
 506         return device_byte_count - mite_bytes_in_transit(mite_chan);
 507 }
 508 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
 509
 510 /* returns upper bound for number of bytes transferred from device to memory */
 511 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
 512 {
 513         u32 in_transit_count;
 514
 515         in_transit_count = mite_bytes_in_transit(mite_chan);
 516         return mite_device_bytes_transferred(mite_chan) - in_transit_count;
 517 }
 518 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
 519
 520 /* returns lower bound for number of bytes read from memory to device */
 521 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
 522 {
 523         u32 device_byte_count;
 524
 525         device_byte_count = mite_device_bytes_transferred(mite_chan);
 526         return device_byte_count + mite_bytes_in_transit(mite_chan);
 527 }
 528 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
 529
 530 /* returns upper bound for number of bytes read from memory to device */
 531 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
 532 {
 533         u32 in_transit_count;
 534
 535         in_transit_count = mite_bytes_in_transit(mite_chan);
 536         return mite_device_bytes_transferred(mite_chan) + in_transit_count;
 537 }
 538 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
 539
 540 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
 541 {
 542         struct mite_struct *mite = mite_chan->mite;
 543         int tcr;
 544         int lkar;
 545
 546         lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 547         tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
 548         MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
 549                  lkar, tcr);
 550
 551         return tcr;
 552 }
 553 EXPORT_SYMBOL(mite_dma_tcr);
 554
 555 void mite_dma_disarm(struct mite_channel *mite_chan)
 556 {
 557         struct mite_struct *mite = mite_chan->mite;
 558         unsigned chor;
 559
 560         /* disarm */
 561         chor = CHOR_ABORT;
 562         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 563 }
 564 EXPORT_SYMBOL(mite_dma_disarm);
 565
 566 int mite_sync_input_dma(struct mite_channel *mite_chan,
 567                         struct comedi_async *async)
 568 {
 569         int count;
 570         unsigned int nbytes, old_alloc_count;
 571         const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
 572
 573         old_alloc_count = async->buf_write_alloc_count;
 574         /* write alloc as much as we can */
 575         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 576
 577         nbytes = mite_bytes_written_to_memory_lb(mite_chan);
 578         if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
 579                   old_alloc_count) > 0) {
 580                 printk("mite: DMA overwrite of free area\n");
 581                 async->events |= COMEDI_CB_OVERFLOW;
 582                 return -1;
 583         }
 584
 585         count = nbytes - async->buf_write_count;
 586         /* it's possible count will be negative due to
 587          * conservative value returned by mite_bytes_written_to_memory_lb */
 588         if (count <= 0)
 589                 return 0;
 590
 591         comedi_buf_write_free(async, count);
 592
 593         async->scan_progress += count;
 594         if (async->scan_progress >= bytes_per_scan) {
 595                 async->scan_progress %= bytes_per_scan;
 596                 async->events |= COMEDI_CB_EOS;
 597         }
 598         async->events |= COMEDI_CB_BLOCK;
 599         return 0;
 600 }
 601 EXPORT_SYMBOL(mite_sync_input_dma);
 602
 603 int mite_sync_output_dma(struct mite_channel *mite_chan,
 604                          struct comedi_async *async)
 605 {
 606         int count;
 607         u32 nbytes_ub, nbytes_lb;
 608         unsigned int old_alloc_count;
 609         u32 stop_count =
 610             async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
 611
 612         old_alloc_count = async->buf_read_alloc_count;
 613         /*  read alloc as much as we can */
 614         comedi_buf_read_alloc(async, async->prealloc_bufsz);
 615         nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
 616         if (async->cmd.stop_src == TRIG_COUNT &&
 617             (int)(nbytes_lb - stop_count) > 0)
 618                 nbytes_lb = stop_count;
 619         nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
 620         if (async->cmd.stop_src == TRIG_COUNT &&
 621             (int)(nbytes_ub - stop_count) > 0)
 622                 nbytes_ub = stop_count;
 623         if ((int)(nbytes_ub - old_alloc_count) > 0) {
 624                 printk(KERN_ERR "mite: DMA underrun\n");
 625                 async->events |= COMEDI_CB_OVERFLOW;
 626                 return -1;
 627         }
 628         count = nbytes_lb - async->buf_read_count;
 629         if (count <= 0)
 630                 return 0;
 631
 632         if (count) {
 633                 comedi_buf_read_free(async, count);
 634                 async->events |= COMEDI_CB_BLOCK;
 635         }
 636         return 0;
 637 }
 638 EXPORT_SYMBOL(mite_sync_output_dma);
 639
 640 unsigned mite_get_status(struct mite_channel *mite_chan)
 641 {
 642         struct mite_struct *mite = mite_chan->mite;
 643         unsigned status;
 644         unsigned long flags;
 645
 646         spin_lock_irqsave(&mite->lock, flags);
 647         status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 648         if (status & CHSR_DONE) {
 649                 mite_chan->done = 1;
 650                 writel(CHOR_CLRDONE,
 651                        mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 652         }
 653         mmiowb();
 654         spin_unlock_irqrestore(&mite->lock, flags);
 655         return status;
 656 }
 657 EXPORT_SYMBOL(mite_get_status);
 658
 659 int mite_done(struct mite_channel *mite_chan)
 660 {
 661         struct mite_struct *mite = mite_chan->mite;
 662         unsigned long flags;
 663         int done;
 664
 665         mite_get_status(mite_chan);
 666         spin_lock_irqsave(&mite->lock, flags);
 667         done = mite_chan->done;
 668         spin_unlock_irqrestore(&mite->lock, flags);
 669         return done;
 670 }
 671 EXPORT_SYMBOL(mite_done);
 672
 673 #ifdef DEBUG_MITE
 674
 675 static void mite_decode(char **bit_str, unsigned int bits);
 676
 677 /* names of bits in mite registers */
 678
 679 static const char *const mite_CHOR_strings[] = {
 680         "start", "cont", "stop", "abort",
 681         "freset", "clrlc", "clrrb", "clrdone",
 682         "clr_lpause", "set_lpause", "clr_send_tc",
 683         "set_send_tc", "12", "13", "14",
 684         "15", "16", "17", "18",
 685         "19", "20", "21", "22",
 686         "23", "24", "25", "26",
 687         "27", "28", "29", "30",
 688         "dmareset",
 689 };
 690
 691 static const char *const mite_CHCR_strings[] = {
 692         "continue", "ringbuff", "2", "3",
 693         "4", "5", "6", "7",
 694         "8", "9", "10", "11",
 695         "12", "13", "bursten", "fifodis",
 696         "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
 697         "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
 698         "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
 699         "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
 700 };
 701
 702 static const char *const mite_MCR_strings[] = {
 703         "amdevice", "1", "2", "3",
 704         "4", "5", "portio", "portvxi",
 705         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
 706         "12", "13", "blocken", "berhand",
 707         "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
 708         "rd512", "rl1", "rl2", "rl8",
 709         "24", "25", "26", "27",
 710         "28", "29", "30", "stopen",
 711 };
 712
 713 static const char *const mite_DCR_strings[] = {
 714         "amdevice", "1", "2", "3",
 715         "4", "5", "portio", "portvxi",
 716         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
 717         "aseqxp8", "13", "blocken", "berhand",
 718         "reqsintlim", "reqs1", "reqs2", "rd32",
 719         "rd512", "rl1", "rl2", "rl8",
 720         "23", "24", "25", "27",
 721         "28", "wsdevc", "wsdevs", "rwdevpack",
 722 };
 723
 724 static const char *const mite_LKCR_strings[] = {
 725         "amdevice", "1", "2", "3",
 726         "4", "5", "portio", "portvxi",
 727         "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
 728         "12", "13", "14", "berhand",
 729         "16", "17", "18", "rd32",
 730         "rd512", "rl1", "rl2", "rl8",
 731         "24", "25", "26", "27",
 732         "28", "29", "30", "chngend",
 733 };
 734
 735 static const char *const mite_CHSR_strings[] = {
 736         "d.err0", "d.err1", "m.err0", "m.err1",
 737         "l.err0", "l.err1", "drq0", "drq1",
 738         "end", "xferr", "operr0", "operr1",
 739         "stops", "habort", "sabort", "error",
 740         "16", "conts_rb", "18", "linkc",
 741         "20", "drdy", "22", "mrdy",
 742         "24", "done", "26", "sars",
 743         "28", "lpauses", "30", "int",
 744 };
 745
 746 void mite_dump_regs(struct mite_channel *mite_chan)
 747 {
 748         unsigned long mite_io_addr =
 749             (unsigned long)mite_chan->mite->mite_io_addr;
 750         unsigned long addr = 0;
 751         unsigned long temp = 0;
 752
 753         printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
 754         printk(KERN_DEBUG "mite address is  =0x%08lx\n", mite_io_addr);
 755
 756         addr = mite_io_addr + MITE_CHOR(channel);
 757         printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
 758                temp = readl(addr));
 759         mite_decode(mite_CHOR_strings, temp);
 760         addr = mite_io_addr + MITE_CHCR(channel);
 761         printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
 762                temp = readl(addr));
 763         mite_decode(mite_CHCR_strings, temp);
 764         addr = mite_io_addr + MITE_TCR(channel);
 765         printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
 766                readl(addr));
 767         addr = mite_io_addr + MITE_MCR(channel);
 768         printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
 769                temp = readl(addr));
 770         mite_decode(mite_MCR_strings, temp);
 771
 772         addr = mite_io_addr + MITE_MAR(channel);
 773         printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
 774                readl(addr));
 775         addr = mite_io_addr + MITE_DCR(channel);
 776         printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
 777                temp = readl(addr));
 778         mite_decode(mite_DCR_strings, temp);
 779         addr = mite_io_addr + MITE_DAR(channel);
 780         printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
 781                readl(addr));
 782         addr = mite_io_addr + MITE_LKCR(channel);
 783         printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
 784                temp = readl(addr));
 785         mite_decode(mite_LKCR_strings, temp);
 786         addr = mite_io_addr + MITE_LKAR(channel);
 787         printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
 788                readl(addr));
 789         addr = mite_io_addr + MITE_CHSR(channel);
 790         printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
 791                temp = readl(addr));
 792         mite_decode(mite_CHSR_strings, temp);
 793         addr = mite_io_addr + MITE_FCR(channel);
 794         printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
 795                readl(addr));
 796 }
 797 EXPORT_SYMBOL(mite_dump_regs);
 798
 799 static void mite_decode(char **bit_str, unsigned int bits)
 800 {
 801         int i;
 802
 803         for (i = 31; i >= 0; i--) {
 804                 if (bits & (1 << i))
 805                         printk(KERN_DEBUG " %s", bit_str[i]);
 806         }
 807         printk(KERN_DEBUG "\n");
 808 }
 809 EXPORT_SYMBOL(mite_decode);
 810 #endif
 811
 812 #ifdef MODULE
 813 int __init init_module(void)
 814 {
 815         mite_init();
 816         mite_list_devices();
 817
 818         return 0;
 819 }
 820
 821 void __exit cleanup_module(void)
 822 {
 823         mite_cleanup();
 824 }
 825 #endif
 826
 827 MODULE_AUTHOR("Comedi http://www.comedi.org");
 828 MODULE_DESCRIPTION("Comedi low-level driver");
 829 MODULE_LICENSE("GPL");