2 * comedi/drivers/mite.c
3 * Hardware driver for NI Mite PCI interface chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 * The PCI-MIO E series driver was originally written by
21 * Tomasz Motylewski <...>, and ported to comedi by ds.
23 * References for specifications:
25 * 321747b.pdf Register Level Programmer Manual (obsolete)
26 * 321747c.pdf Register Level Programmer Manual (new)
27 * DAQ-STC reference manual
29 * Other possibly relevant info:
31 * 320517c.pdf User manual (obsolete)
32 * 320517f.pdf User manual (new)
34 * 320906c.pdf maximum signal ratings
35 * 321066a.pdf about 16x
36 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
37 * 321808a.pdf about at-mio-16e-10 rev P
38 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
39 * 321838a.pdf about at-mio-16de-10 rev N
45 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
47 #include <linux/module.h>
48 #include <linux/slab.h>
50 #include "../comedi_pci.h"
54 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
56 struct mite_struct *mite_alloc(struct pci_dev *pcidev)
58 struct mite_struct *mite;
61 mite = kzalloc(sizeof(*mite), GFP_KERNEL);
63 spin_lock_init(&mite->lock);
64 mite->pcidev = pcidev;
65 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
66 mite->channels[i].mite = mite;
67 mite->channels[i].channel = i;
68 mite->channels[i].done = 1;
73 EXPORT_SYMBOL_GPL(mite_alloc);
75 static void dump_chip_signature(u32 csigr_bits)
77 pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
78 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
79 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
80 pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
81 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
82 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
85 static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
87 unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
88 unsigned empty_count = (fcr_bits >> 16) & 0xff;
89 unsigned full_count = fcr_bits & 0xff;
91 return empty_count + full_count;
94 int mite_setup2(struct comedi_device *dev,
95 struct mite_struct *mite, bool use_win1)
100 unsigned unknown_dma_burst_bits;
102 pci_set_master(mite->pcidev);
104 mite->mite_io_addr = pci_ioremap_bar(mite->pcidev, 0);
105 if (!mite->mite_io_addr) {
106 dev_err(dev->class_dev,
107 "Failed to remap mite io memory address\n");
110 mite->mite_phys_addr = pci_resource_start(mite->pcidev, 0);
112 dev->mmio = pci_ioremap_bar(mite->pcidev, 1);
114 dev_err(dev->class_dev,
115 "Failed to remap daq io memory address\n");
118 mite->daq_phys_addr = pci_resource_start(mite->pcidev, 1);
119 length = pci_resource_len(mite->pcidev, 1);
122 writel(0, mite->mite_io_addr + MITE_IODWBSR);
123 dev_info(dev->class_dev,
124 "using I/O Window Base Size register 1\n");
125 writel(mite->daq_phys_addr | WENAB |
126 MITE_IODWBSR_1_WSIZE_bits(length),
127 mite->mite_io_addr + MITE_IODWBSR_1);
128 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
130 writel(mite->daq_phys_addr | WENAB,
131 mite->mite_io_addr + MITE_IODWBSR);
134 * Make sure dma bursts work. I got this from running a bus analyzer
135 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
136 * of 0x61f and bursts worked. 6281 powered up with register value of
137 * 0x1f and bursts didn't work. The NI windows driver reads the
138 * register, then does a bitwise-or of 0x600 with it and writes it back.
140 unknown_dma_burst_bits =
141 readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
142 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
143 writel(unknown_dma_burst_bits,
144 mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
146 csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
147 mite->num_channels = mite_csigr_dmac(csigr_bits);
148 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
149 dev_warn(dev->class_dev,
150 "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
151 mite->num_channels, MAX_MITE_DMA_CHANNELS);
152 mite->num_channels = MAX_MITE_DMA_CHANNELS;
154 dump_chip_signature(csigr_bits);
155 for (i = 0; i < mite->num_channels; i++) {
156 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
157 /* disable interrupts */
158 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
159 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
160 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
161 mite->mite_io_addr + MITE_CHCR(i));
163 mite->fifo_size = mite_fifo_size(mite, 0);
164 dev_info(dev->class_dev, "fifo size is %i.\n", mite->fifo_size);
167 EXPORT_SYMBOL_GPL(mite_setup2);
169 void mite_detach(struct mite_struct *mite)
174 if (mite->mite_io_addr)
175 iounmap(mite->mite_io_addr);
179 EXPORT_SYMBOL_GPL(mite_detach);
181 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
183 struct mite_dma_descriptor_ring *ring =
184 kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
188 ring->hw_dev = get_device(&mite->pcidev->dev);
194 ring->descriptors = NULL;
195 ring->descriptors_dma_addr = 0;
198 EXPORT_SYMBOL_GPL(mite_alloc_ring);
200 void mite_free_ring(struct mite_dma_descriptor_ring *ring)
203 if (ring->descriptors) {
204 dma_free_coherent(ring->hw_dev,
206 sizeof(struct mite_dma_descriptor),
208 ring->descriptors_dma_addr);
210 put_device(ring->hw_dev);
214 EXPORT_SYMBOL_GPL(mite_free_ring);
216 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
218 mite_dma_descriptor_ring
219 *ring, unsigned min_channel,
220 unsigned max_channel)
224 struct mite_channel *channel = NULL;
227 * spin lock so mite_release_channel can be called safely
230 spin_lock_irqsave(&mite->lock, flags);
231 for (i = min_channel; i <= max_channel; ++i) {
232 if (mite->channel_allocated[i] == 0) {
233 mite->channel_allocated[i] = 1;
234 channel = &mite->channels[i];
235 channel->ring = ring;
239 spin_unlock_irqrestore(&mite->lock, flags);
242 EXPORT_SYMBOL_GPL(mite_request_channel_in_range);
244 void mite_release_channel(struct mite_channel *mite_chan)
246 struct mite_struct *mite = mite_chan->mite;
249 /* spin lock to prevent races with mite_request_channel */
250 spin_lock_irqsave(&mite->lock, flags);
251 if (mite->channel_allocated[mite_chan->channel]) {
252 mite_dma_disarm(mite_chan);
253 mite_dma_reset(mite_chan);
255 * disable all channel's interrupts (do it after disarm/reset so
256 * MITE_CHCR reg isn't changed while dma is still active!)
258 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
259 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
260 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
261 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
262 mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
263 mite->channel_allocated[mite_chan->channel] = 0;
264 mite_chan->ring = NULL;
267 spin_unlock_irqrestore(&mite->lock, flags);
269 EXPORT_SYMBOL_GPL(mite_release_channel);
271 void mite_dma_arm(struct mite_channel *mite_chan)
273 struct mite_struct *mite = mite_chan->mite;
278 * memory barrier is intended to insure any twiddling with the buffer
279 * is done before writing to the mite to arm dma transfer
284 spin_lock_irqsave(&mite->lock, flags);
286 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
288 spin_unlock_irqrestore(&mite->lock, flags);
289 /* mite_dma_tcr(mite, channel); */
291 EXPORT_SYMBOL_GPL(mite_dma_arm);
293 /**************************************/
295 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
296 struct comedi_subdevice *s)
298 struct comedi_async *async = s->async;
299 unsigned int n_links;
302 if (ring->descriptors) {
303 dma_free_coherent(ring->hw_dev,
305 sizeof(struct mite_dma_descriptor),
307 ring->descriptors_dma_addr);
309 ring->descriptors = NULL;
310 ring->descriptors_dma_addr = 0;
313 if (async->prealloc_bufsz == 0)
316 n_links = async->prealloc_bufsz >> PAGE_SHIFT;
319 dma_alloc_coherent(ring->hw_dev,
320 n_links * sizeof(struct mite_dma_descriptor),
321 &ring->descriptors_dma_addr, GFP_KERNEL);
322 if (!ring->descriptors) {
323 dev_err(s->device->class_dev,
324 "mite: ring buffer allocation failed\n");
327 ring->n_links = n_links;
329 for (i = 0; i < n_links; i++) {
330 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
331 ring->descriptors[i].addr =
332 cpu_to_le32(async->buf_map->page_list[i].dma_addr);
333 ring->descriptors[i].next =
334 cpu_to_le32(ring->descriptors_dma_addr + (i +
336 sizeof(struct mite_dma_descriptor));
338 ring->descriptors[n_links - 1].next =
339 cpu_to_le32(ring->descriptors_dma_addr);
341 * barrier is meant to insure that all the writes to the dma descriptors
342 * have completed before the dma controller is commanded to read them
347 EXPORT_SYMBOL_GPL(mite_buf_change);
349 void mite_prep_dma(struct mite_channel *mite_chan,
350 unsigned int num_device_bits, unsigned int num_memory_bits)
352 unsigned int chor, chcr, mcr, dcr, lkcr;
353 struct mite_struct *mite = mite_chan->mite;
355 /* reset DMA and FIFO */
356 chor = CHOR_DMARESET | CHOR_FRESET;
357 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
359 /* short link chaining mode */
360 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
363 * Link Complete Interrupt: interrupt every time a link
364 * in MITE_RING is completed. This can generate a lot of
365 * extra interrupts, but right now we update the values
366 * of buf_int_ptr and buf_int_count at each interrupt. A
367 * better method is to poll the MITE before each user
368 * "read()" to calculate the number of bytes available.
370 chcr |= CHCR_SET_LC_IE;
371 if (num_memory_bits == 32 && num_device_bits == 16) {
373 * Doing a combined 32 and 16 bit byteswap gets the 16 bit
374 * samples into the fifo in the right order. Tested doing 32 bit
375 * memory to 16 bit device transfers to the analog out of a
376 * pxi-6281, which has mite version = 1, type = 4. This also
377 * works for dma reads from the counters on e-series boards.
379 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
381 if (mite_chan->dir == COMEDI_INPUT)
382 chcr |= CHCR_DEV_TO_MEM;
384 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
387 mcr = CR_RL(64) | CR_ASEQUP;
388 switch (num_memory_bits) {
399 pr_warn("bug! invalid mem bit width for dma transfer\n");
402 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
405 dcr = CR_RL(64) | CR_ASEQUP;
406 dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
407 switch (num_device_bits) {
418 pr_warn("bug! invalid dev bit width for dma transfer\n");
421 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
424 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
426 /* the link is 32bits */
427 lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
428 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
430 /* starting address for link chaining */
431 writel(mite_chan->ring->descriptors_dma_addr,
432 mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
434 EXPORT_SYMBOL_GPL(mite_prep_dma);
436 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
438 struct mite_struct *mite = mite_chan->mite;
440 return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
443 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
445 struct mite_struct *mite = mite_chan->mite;
447 return readl(mite->mite_io_addr +
448 MITE_FCR(mite_chan->channel)) & 0x000000FF;
450 EXPORT_SYMBOL_GPL(mite_bytes_in_transit);
452 /* returns lower bound for number of bytes transferred from device to memory */
453 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
455 u32 device_byte_count;
457 device_byte_count = mite_device_bytes_transferred(mite_chan);
458 return device_byte_count - mite_bytes_in_transit(mite_chan);
460 EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_lb);
462 /* returns upper bound for number of bytes transferred from device to memory */
463 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
465 u32 in_transit_count;
467 in_transit_count = mite_bytes_in_transit(mite_chan);
468 return mite_device_bytes_transferred(mite_chan) - in_transit_count;
470 EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_ub);
472 /* returns lower bound for number of bytes read from memory to device */
473 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
475 u32 device_byte_count;
477 device_byte_count = mite_device_bytes_transferred(mite_chan);
478 return device_byte_count + mite_bytes_in_transit(mite_chan);
480 EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_lb);
482 /* returns upper bound for number of bytes read from memory to device */
483 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
485 u32 in_transit_count;
487 in_transit_count = mite_bytes_in_transit(mite_chan);
488 return mite_device_bytes_transferred(mite_chan) + in_transit_count;
490 EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_ub);
492 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
494 struct mite_struct *mite = mite_chan->mite;
496 return readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
498 EXPORT_SYMBOL_GPL(mite_dma_tcr);
500 void mite_dma_disarm(struct mite_channel *mite_chan)
502 struct mite_struct *mite = mite_chan->mite;
507 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
509 EXPORT_SYMBOL_GPL(mite_dma_disarm);
511 int mite_sync_input_dma(struct mite_channel *mite_chan,
512 struct comedi_subdevice *s)
514 struct comedi_async *async = s->async;
516 unsigned int nbytes, old_alloc_count;
518 old_alloc_count = async->buf_write_alloc_count;
519 /* write alloc as much as we can */
520 comedi_buf_write_alloc(s, async->prealloc_bufsz);
522 nbytes = mite_bytes_written_to_memory_lb(mite_chan);
523 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
524 old_alloc_count) > 0) {
525 dev_warn(s->device->class_dev,
526 "mite: DMA overwrite of free area\n");
527 async->events |= COMEDI_CB_OVERFLOW;
531 count = nbytes - async->buf_write_count;
533 * it's possible count will be negative due to conservative value
534 * returned by mite_bytes_written_to_memory_lb
539 comedi_buf_write_free(s, count);
540 comedi_inc_scan_progress(s, count);
541 async->events |= COMEDI_CB_BLOCK;
544 EXPORT_SYMBOL_GPL(mite_sync_input_dma);
546 int mite_sync_output_dma(struct mite_channel *mite_chan,
547 struct comedi_subdevice *s)
549 struct comedi_async *async = s->async;
550 struct comedi_cmd *cmd = &async->cmd;
551 u32 stop_count = cmd->stop_arg * comedi_bytes_per_scan(s);
552 unsigned int old_alloc_count = async->buf_read_alloc_count;
553 u32 nbytes_ub, nbytes_lb;
556 /* read alloc as much as we can */
557 comedi_buf_read_alloc(s, async->prealloc_bufsz);
558 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
559 if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_lb - stop_count) > 0)
560 nbytes_lb = stop_count;
561 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
562 if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_ub - stop_count) > 0)
563 nbytes_ub = stop_count;
564 if ((int)(nbytes_ub - old_alloc_count) > 0) {
565 dev_warn(s->device->class_dev, "mite: DMA underrun\n");
566 async->events |= COMEDI_CB_OVERFLOW;
569 count = nbytes_lb - async->buf_read_count;
574 comedi_buf_read_free(s, count);
575 async->events |= COMEDI_CB_BLOCK;
579 EXPORT_SYMBOL_GPL(mite_sync_output_dma);
581 unsigned mite_get_status(struct mite_channel *mite_chan)
583 struct mite_struct *mite = mite_chan->mite;
587 spin_lock_irqsave(&mite->lock, flags);
588 status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
589 if (status & CHSR_DONE) {
592 mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
595 spin_unlock_irqrestore(&mite->lock, flags);
598 EXPORT_SYMBOL_GPL(mite_get_status);
600 int mite_done(struct mite_channel *mite_chan)
602 struct mite_struct *mite = mite_chan->mite;
606 mite_get_status(mite_chan);
607 spin_lock_irqsave(&mite->lock, flags);
608 done = mite_chan->done;
609 spin_unlock_irqrestore(&mite->lock, flags);
612 EXPORT_SYMBOL_GPL(mite_done);
614 static int __init mite_module_init(void)
619 static void __exit mite_module_exit(void)
623 module_init(mite_module_init);
624 module_exit(mite_module_exit);
626 MODULE_AUTHOR("Comedi http://www.comedi.org");
627 MODULE_DESCRIPTION("Comedi helper for NI Mite PCI interface chip");
628 MODULE_LICENSE("GPL");