drivers/staging/comedi/drivers/mite.c

   1 /*
   2     comedi/drivers/mite.c
   3     Hardware driver for NI Mite PCI interface chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 /*
  25         The PCI-MIO E series driver was originally written by
  26         Tomasz Motylewski <...>, and ported to comedi by ds.
  27
  28         References for specifications:
  29
  30            321747b.pdf  Register Level Programmer Manual (obsolete)
  31            321747c.pdf  Register Level Programmer Manual (new)
  32            DAQ-STC reference manual
  33
  34         Other possibly relevant info:
  35
  36            320517c.pdf  User manual (obsolete)
  37            320517f.pdf  User manual (new)
  38            320889a.pdf  delete
  39            320906c.pdf  maximum signal ratings
  40            321066a.pdf  about 16x
  41            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  42            321808a.pdf  about at-mio-16e-10 rev P
  43            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  44            321838a.pdf  about at-mio-16de-10 rev N
  45
  46         ISSUES:
  47
  48 */
  49
  50 /* #define USE_KMALLOC */
  51
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 #include <linux/pci.h>
  55
  56 #include "../comedidev.h"
  57
  58 #include "comedi_fc.h"
  59 #include "mite.h"
  60
  61 #define PCI_MITE_SIZE           4096
  62 #define PCI_DAQ_SIZE            4096
  63 #define PCI_DAQ_SIZE_660X       8192
  64
  65 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  66
  67 struct mite_struct *mite_alloc(struct pci_dev *pcidev)
  68 {
  69         struct mite_struct *mite;
  70         unsigned int i;
  71
  72         mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  73         if (mite) {
  74                 spin_lock_init(&mite->lock);
  75                 mite->pcidev = pcidev;
  76                 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  77                         mite->channels[i].mite = mite;
  78                         mite->channels[i].channel = i;
  79                         mite->channels[i].done = 1;
  80                 }
  81         }
  82         return mite;
  83 }
  84 EXPORT_SYMBOL(mite_alloc);
  85
  86 static void dump_chip_signature(u32 csigr_bits)
  87 {
  88         pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
  89                 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
  90                 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
  91         pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
  92                 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
  93                 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
  94 }
  95
  96 static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
  97 {
  98         unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
  99         unsigned empty_count = (fcr_bits >> 16) & 0xff;
 100         unsigned full_count = fcr_bits & 0xff;
 101         return empty_count + full_count;
 102 }
 103
 104 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
 105 {
 106         unsigned long length;
 107         resource_size_t addr;
 108         int i;
 109         u32 csigr_bits;
 110         unsigned unknown_dma_burst_bits;
 111
 112         if (comedi_pci_enable(mite->pcidev, "mite")) {
 113                 dev_err(&mite->pcidev->dev,
 114                         "error enabling mite and requesting io regions\n");
 115                 return -EIO;
 116         }
 117         pci_set_master(mite->pcidev);
 118
 119         addr = pci_resource_start(mite->pcidev, 0);
 120         mite->mite_phys_addr = addr;
 121         mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
 122         if (!mite->mite_io_addr) {
 123                 dev_err(&mite->pcidev->dev,
 124                         "Failed to remap mite io memory address\n");
 125                 return -ENOMEM;
 126         }
 127
 128         addr = pci_resource_start(mite->pcidev, 1);
 129         mite->daq_phys_addr = addr;
 130         length = pci_resource_len(mite->pcidev, 1);
 131         /*
 132          * In case of a 660x board, DAQ size is 8k instead of 4k
 133          * (see as shown by lspci output)
 134          */
 135         mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
 136         if (!mite->daq_io_addr) {
 137                 dev_err(&mite->pcidev->dev,
 138                         "Failed to remap daq io memory address\n");
 139                 return -ENOMEM;
 140         }
 141
 142         if (use_iodwbsr_1) {
 143                 writel(0, mite->mite_io_addr + MITE_IODWBSR);
 144                 dev_info(&mite->pcidev->dev,
 145                          "using I/O Window Base Size register 1\n");
 146                 writel(mite->daq_phys_addr | WENAB |
 147                        MITE_IODWBSR_1_WSIZE_bits(length),
 148                        mite->mite_io_addr + MITE_IODWBSR_1);
 149                 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
 150         } else {
 151                 writel(mite->daq_phys_addr | WENAB,
 152                        mite->mite_io_addr + MITE_IODWBSR);
 153         }
 154         /*
 155          * make sure dma bursts work. I got this from running a bus analyzer
 156          * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
 157          * of 0x61f and bursts worked. 6281 powered up with register value of
 158          * 0x1f and bursts didn't work. The NI windows driver reads the
 159          * register, then does a bitwise-or of 0x600 with it and writes it back.
 160          */
 161         unknown_dma_burst_bits =
 162             readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 163         unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
 164         writel(unknown_dma_burst_bits,
 165                mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 166
 167         csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
 168         mite->num_channels = mite_csigr_dmac(csigr_bits);
 169         if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
 170                 dev_warn(&mite->pcidev->dev,
 171                          "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
 172                          mite->num_channels, MAX_MITE_DMA_CHANNELS);
 173                 mite->num_channels = MAX_MITE_DMA_CHANNELS;
 174         }
 175         dump_chip_signature(csigr_bits);
 176         for (i = 0; i < mite->num_channels; i++) {
 177                 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
 178                 /* disable interrupts */
 179                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 180                        CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 181                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 182                        mite->mite_io_addr + MITE_CHCR(i));
 183         }
 184         mite->fifo_size = mite_fifo_size(mite, 0);
 185         dev_info(&mite->pcidev->dev, "fifo size is %i.\n", mite->fifo_size);
 186         return 0;
 187 }
 188 EXPORT_SYMBOL(mite_setup2);
 189
 190 int mite_setup(struct mite_struct *mite)
 191 {
 192         return mite_setup2(mite, 0);
 193 }
 194 EXPORT_SYMBOL(mite_setup);
 195
 196 void mite_unsetup(struct mite_struct *mite)
 197 {
 198         /* unsigned long offset, start, length; */
 199
 200         if (!mite)
 201                 return;
 202
 203         if (mite->mite_io_addr) {
 204                 iounmap(mite->mite_io_addr);
 205                 mite->mite_io_addr = NULL;
 206         }
 207         if (mite->daq_io_addr) {
 208                 iounmap(mite->daq_io_addr);
 209                 mite->daq_io_addr = NULL;
 210         }
 211         if (mite->mite_phys_addr)
 212                 mite->mite_phys_addr = 0;
 213 }
 214 EXPORT_SYMBOL(mite_unsetup);
 215
 216 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
 217 {
 218         struct mite_dma_descriptor_ring *ring =
 219             kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
 220
 221         if (ring == NULL)
 222                 return ring;
 223         ring->hw_dev = get_device(&mite->pcidev->dev);
 224         if (ring->hw_dev == NULL) {
 225                 kfree(ring);
 226                 return NULL;
 227         }
 228         ring->n_links = 0;
 229         ring->descriptors = NULL;
 230         ring->descriptors_dma_addr = 0;
 231         return ring;
 232 };
 233 EXPORT_SYMBOL(mite_alloc_ring);
 234
 235 void mite_free_ring(struct mite_dma_descriptor_ring *ring)
 236 {
 237         if (ring) {
 238                 if (ring->descriptors) {
 239                         dma_free_coherent(ring->hw_dev,
 240                                           ring->n_links *
 241                                           sizeof(struct mite_dma_descriptor),
 242                                           ring->descriptors,
 243                                           ring->descriptors_dma_addr);
 244                 }
 245                 put_device(ring->hw_dev);
 246                 kfree(ring);
 247         }
 248 };
 249 EXPORT_SYMBOL(mite_free_ring);
 250
 251 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
 252                                                    struct
 253                                                    mite_dma_descriptor_ring
 254                                                    *ring, unsigned min_channel,
 255                                                    unsigned max_channel)
 256 {
 257         int i;
 258         unsigned long flags;
 259         struct mite_channel *channel = NULL;
 260
 261         /* spin lock so mite_release_channel can be called safely
 262          * from interrupts
 263          */
 264         spin_lock_irqsave(&mite->lock, flags);
 265         for (i = min_channel; i <= max_channel; ++i) {
 266                 if (mite->channel_allocated[i] == 0) {
 267                         mite->channel_allocated[i] = 1;
 268                         channel = &mite->channels[i];
 269                         channel->ring = ring;
 270                         break;
 271                 }
 272         }
 273         spin_unlock_irqrestore(&mite->lock, flags);
 274         return channel;
 275 }
 276 EXPORT_SYMBOL(mite_request_channel_in_range);
 277
 278 void mite_release_channel(struct mite_channel *mite_chan)
 279 {
 280         struct mite_struct *mite = mite_chan->mite;
 281         unsigned long flags;
 282
 283         /*  spin lock to prevent races with mite_request_channel */
 284         spin_lock_irqsave(&mite->lock, flags);
 285         if (mite->channel_allocated[mite_chan->channel]) {
 286                 mite_dma_disarm(mite_chan);
 287                 mite_dma_reset(mite_chan);
 288         /*
 289          * disable all channel's interrupts (do it after disarm/reset so
 290          * MITE_CHCR reg isn't changed while dma is still active!)
 291          */
 292                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
 293                        CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
 294                        CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 295                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 296                        mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 297                 mite->channel_allocated[mite_chan->channel] = 0;
 298                 mite_chan->ring = NULL;
 299                 mmiowb();
 300         }
 301         spin_unlock_irqrestore(&mite->lock, flags);
 302 }
 303 EXPORT_SYMBOL(mite_release_channel);
 304
 305 void mite_dma_arm(struct mite_channel *mite_chan)
 306 {
 307         struct mite_struct *mite = mite_chan->mite;
 308         int chor;
 309         unsigned long flags;
 310
 311         MDPRINTK("mite_dma_arm ch%i\n", mite_chan->channel);
 312         /*
 313          * memory barrier is intended to insure any twiddling with the buffer
 314          * is done before writing to the mite to arm dma transfer
 315          */
 316         smp_mb();
 317         /* arm */
 318         chor = CHOR_START;
 319         spin_lock_irqsave(&mite->lock, flags);
 320         mite_chan->done = 0;
 321         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 322         mmiowb();
 323         spin_unlock_irqrestore(&mite->lock, flags);
 324 /*       mite_dma_tcr(mite, channel); */
 325 }
 326 EXPORT_SYMBOL(mite_dma_arm);
 327
 328 /**************************************/
 329
 330 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 331                     struct comedi_async *async)
 332 {
 333         unsigned int n_links;
 334         int i;
 335
 336         if (ring->descriptors) {
 337                 dma_free_coherent(ring->hw_dev,
 338                                   ring->n_links *
 339                                   sizeof(struct mite_dma_descriptor),
 340                                   ring->descriptors,
 341                                   ring->descriptors_dma_addr);
 342         }
 343         ring->descriptors = NULL;
 344         ring->descriptors_dma_addr = 0;
 345         ring->n_links = 0;
 346
 347         if (async->prealloc_bufsz == 0)
 348                 return 0;
 349
 350         n_links = async->prealloc_bufsz >> PAGE_SHIFT;
 351
 352         MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
 353
 354         ring->descriptors =
 355             dma_alloc_coherent(ring->hw_dev,
 356                                n_links * sizeof(struct mite_dma_descriptor),
 357                                &ring->descriptors_dma_addr, GFP_KERNEL);
 358         if (!ring->descriptors) {
 359                 dev_err(async->subdevice->device->class_dev,
 360                         "mite: ring buffer allocation failed\n");
 361                 return -ENOMEM;
 362         }
 363         ring->n_links = n_links;
 364
 365         for (i = 0; i < n_links; i++) {
 366                 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
 367                 ring->descriptors[i].addr =
 368                     cpu_to_le32(async->buf_page_list[i].dma_addr);
 369                 ring->descriptors[i].next =
 370                     cpu_to_le32(ring->descriptors_dma_addr + (i +
 371                                                               1) *
 372                                 sizeof(struct mite_dma_descriptor));
 373         }
 374         ring->descriptors[n_links - 1].next =
 375             cpu_to_le32(ring->descriptors_dma_addr);
 376         /*
 377          * barrier is meant to insure that all the writes to the dma descriptors
 378          * have completed before the dma controller is commanded to read them
 379          */
 380         smp_wmb();
 381         return 0;
 382 }
 383 EXPORT_SYMBOL(mite_buf_change);
 384
 385 void mite_prep_dma(struct mite_channel *mite_chan,
 386                    unsigned int num_device_bits, unsigned int num_memory_bits)
 387 {
 388         unsigned int chor, chcr, mcr, dcr, lkcr;
 389         struct mite_struct *mite = mite_chan->mite;
 390
 391         MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
 392
 393         /* reset DMA and FIFO */
 394         chor = CHOR_DMARESET | CHOR_FRESET;
 395         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 396
 397         /* short link chaining mode */
 398         chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
 399             CHCR_BURSTEN;
 400         /*
 401          * Link Complete Interrupt: interrupt every time a link
 402          * in MITE_RING is completed. This can generate a lot of
 403          * extra interrupts, but right now we update the values
 404          * of buf_int_ptr and buf_int_count at each interrupt. A
 405          * better method is to poll the MITE before each user
 406          * "read()" to calculate the number of bytes available.
 407          */
 408         chcr |= CHCR_SET_LC_IE;
 409         if (num_memory_bits == 32 && num_device_bits == 16) {
 410                 /*
 411                  * Doing a combined 32 and 16 bit byteswap gets the 16 bit
 412                  * samples into the fifo in the right order. Tested doing 32 bit
 413                  * memory to 16 bit device transfers to the analog out of a
 414                  * pxi-6281, which has mite version = 1, type = 4. This also
 415                  * works for dma reads from the counters on e-series boards.
 416                  */
 417                 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
 418         }
 419         if (mite_chan->dir == COMEDI_INPUT)
 420                 chcr |= CHCR_DEV_TO_MEM;
 421
 422         writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 423
 424         /* to/from memory */
 425         mcr = CR_RL(64) | CR_ASEQUP;
 426         switch (num_memory_bits) {
 427         case 8:
 428                 mcr |= CR_PSIZE8;
 429                 break;
 430         case 16:
 431                 mcr |= CR_PSIZE16;
 432                 break;
 433         case 32:
 434                 mcr |= CR_PSIZE32;
 435                 break;
 436         default:
 437                 pr_warn("bug! invalid mem bit width for dma transfer\n");
 438                 break;
 439         }
 440         writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
 441
 442         /* from/to device */
 443         dcr = CR_RL(64) | CR_ASEQUP;
 444         dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
 445         switch (num_device_bits) {
 446         case 8:
 447                 dcr |= CR_PSIZE8;
 448                 break;
 449         case 16:
 450                 dcr |= CR_PSIZE16;
 451                 break;
 452         case 32:
 453                 dcr |= CR_PSIZE32;
 454                 break;
 455         default:
 456                 pr_warn("bug! invalid dev bit width for dma transfer\n");
 457                 break;
 458         }
 459         writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
 460
 461         /* reset the DAR */
 462         writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 463
 464         /* the link is 32bits */
 465         lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
 466         writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
 467
 468         /* starting address for link chaining */
 469         writel(mite_chan->ring->descriptors_dma_addr,
 470                mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 471
 472         MDPRINTK("exit mite_prep_dma\n");
 473 }
 474 EXPORT_SYMBOL(mite_prep_dma);
 475
 476 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
 477 {
 478         struct mite_struct *mite = mite_chan->mite;
 479         return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 480 }
 481
 482 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
 483 {
 484         struct mite_struct *mite = mite_chan->mite;
 485         return readl(mite->mite_io_addr +
 486                      MITE_FCR(mite_chan->channel)) & 0x000000FF;
 487 }
 488 EXPORT_SYMBOL(mite_bytes_in_transit);
 489
 490 /* returns lower bound for number of bytes transferred from device to memory */
 491 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
 492 {
 493         u32 device_byte_count;
 494
 495         device_byte_count = mite_device_bytes_transferred(mite_chan);
 496         return device_byte_count - mite_bytes_in_transit(mite_chan);
 497 }
 498 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
 499
 500 /* returns upper bound for number of bytes transferred from device to memory */
 501 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
 502 {
 503         u32 in_transit_count;
 504
 505         in_transit_count = mite_bytes_in_transit(mite_chan);
 506         return mite_device_bytes_transferred(mite_chan) - in_transit_count;
 507 }
 508 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
 509
 510 /* returns lower bound for number of bytes read from memory to device */
 511 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
 512 {
 513         u32 device_byte_count;
 514
 515         device_byte_count = mite_device_bytes_transferred(mite_chan);
 516         return device_byte_count + mite_bytes_in_transit(mite_chan);
 517 }
 518 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
 519
 520 /* returns upper bound for number of bytes read from memory to device */
 521 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
 522 {
 523         u32 in_transit_count;
 524
 525         in_transit_count = mite_bytes_in_transit(mite_chan);
 526         return mite_device_bytes_transferred(mite_chan) + in_transit_count;
 527 }
 528 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
 529
 530 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
 531 {
 532         struct mite_struct *mite = mite_chan->mite;
 533         int tcr;
 534         int lkar;
 535
 536         lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 537         tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
 538         MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
 539                  lkar, tcr);
 540
 541         return tcr;
 542 }
 543 EXPORT_SYMBOL(mite_dma_tcr);
 544
 545 void mite_dma_disarm(struct mite_channel *mite_chan)
 546 {
 547         struct mite_struct *mite = mite_chan->mite;
 548         unsigned chor;
 549
 550         /* disarm */
 551         chor = CHOR_ABORT;
 552         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 553 }
 554 EXPORT_SYMBOL(mite_dma_disarm);
 555
 556 int mite_sync_input_dma(struct mite_channel *mite_chan,
 557                         struct comedi_async *async)
 558 {
 559         int count;
 560         unsigned int nbytes, old_alloc_count;
 561         const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
 562
 563         old_alloc_count = async->buf_write_alloc_count;
 564         /* write alloc as much as we can */
 565         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 566
 567         nbytes = mite_bytes_written_to_memory_lb(mite_chan);
 568         if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
 569                   old_alloc_count) > 0) {
 570                 dev_warn(async->subdevice->device->class_dev,
 571                          "mite: DMA overwrite of free area\n");
 572                 async->events |= COMEDI_CB_OVERFLOW;
 573                 return -1;
 574         }
 575
 576         count = nbytes - async->buf_write_count;
 577         /* it's possible count will be negative due to
 578          * conservative value returned by mite_bytes_written_to_memory_lb */
 579         if (count <= 0)
 580                 return 0;
 581
 582         comedi_buf_write_free(async, count);
 583
 584         async->scan_progress += count;
 585         if (async->scan_progress >= bytes_per_scan) {
 586                 async->scan_progress %= bytes_per_scan;
 587                 async->events |= COMEDI_CB_EOS;
 588         }
 589         async->events |= COMEDI_CB_BLOCK;
 590         return 0;
 591 }
 592 EXPORT_SYMBOL(mite_sync_input_dma);
 593
 594 int mite_sync_output_dma(struct mite_channel *mite_chan,
 595                          struct comedi_async *async)
 596 {
 597         int count;
 598         u32 nbytes_ub, nbytes_lb;
 599         unsigned int old_alloc_count;
 600         u32 stop_count =
 601             async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
 602
 603         old_alloc_count = async->buf_read_alloc_count;
 604         /*  read alloc as much as we can */
 605         comedi_buf_read_alloc(async, async->prealloc_bufsz);
 606         nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
 607         if (async->cmd.stop_src == TRIG_COUNT &&
 608             (int)(nbytes_lb - stop_count) > 0)
 609                 nbytes_lb = stop_count;
 610         nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
 611         if (async->cmd.stop_src == TRIG_COUNT &&
 612             (int)(nbytes_ub - stop_count) > 0)
 613                 nbytes_ub = stop_count;
 614         if ((int)(nbytes_ub - old_alloc_count) > 0) {
 615                 dev_warn(async->subdevice->device->class_dev,
 616                          "mite: DMA underrun\n");
 617                 async->events |= COMEDI_CB_OVERFLOW;
 618                 return -1;
 619         }
 620         count = nbytes_lb - async->buf_read_count;
 621         if (count <= 0)
 622                 return 0;
 623
 624         if (count) {
 625                 comedi_buf_read_free(async, count);
 626                 async->events |= COMEDI_CB_BLOCK;
 627         }
 628         return 0;
 629 }
 630 EXPORT_SYMBOL(mite_sync_output_dma);
 631
 632 unsigned mite_get_status(struct mite_channel *mite_chan)
 633 {
 634         struct mite_struct *mite = mite_chan->mite;
 635         unsigned status;
 636         unsigned long flags;
 637
 638         spin_lock_irqsave(&mite->lock, flags);
 639         status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 640         if (status & CHSR_DONE) {
 641                 mite_chan->done = 1;
 642                 writel(CHOR_CLRDONE,
 643                        mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 644         }
 645         mmiowb();
 646         spin_unlock_irqrestore(&mite->lock, flags);
 647         return status;
 648 }
 649 EXPORT_SYMBOL(mite_get_status);
 650
 651 int mite_done(struct mite_channel *mite_chan)
 652 {
 653         struct mite_struct *mite = mite_chan->mite;
 654         unsigned long flags;
 655         int done;
 656
 657         mite_get_status(mite_chan);
 658         spin_lock_irqsave(&mite->lock, flags);
 659         done = mite_chan->done;
 660         spin_unlock_irqrestore(&mite->lock, flags);
 661         return done;
 662 }
 663 EXPORT_SYMBOL(mite_done);
 664
 665 #ifdef DEBUG_MITE
 666
 667 /* names of bits in mite registers */
 668
 669 static const char *const mite_CHOR_strings[] = {
 670         "start", "cont", "stop", "abort",
 671         "freset", "clrlc", "clrrb", "clrdone",
 672         "clr_lpause", "set_lpause", "clr_send_tc",
 673         "set_send_tc", "12", "13", "14",
 674         "15", "16", "17", "18",
 675         "19", "20", "21", "22",
 676         "23", "24", "25", "26",
 677         "27", "28", "29", "30",
 678         "dmareset",
 679 };
 680
 681 static const char *const mite_CHCR_strings[] = {
 682         "continue", "ringbuff", "2", "3",
 683         "4", "5", "6", "7",
 684         "8", "9", "10", "11",
 685         "12", "13", "bursten", "fifodis",
 686         "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
 687         "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
 688         "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
 689         "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
 690 };
 691
 692 static const char *const mite_MCR_strings[] = {
 693         "amdevice", "1", "2", "3",
 694         "4", "5", "portio", "portvxi",
 695         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
 696         "12", "13", "blocken", "berhand",
 697         "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
 698         "rd512", "rl1", "rl2", "rl8",
 699         "24", "25", "26", "27",
 700         "28", "29", "30", "stopen",
 701 };
 702
 703 static const char *const mite_DCR_strings[] = {
 704         "amdevice", "1", "2", "3",
 705         "4", "5", "portio", "portvxi",
 706         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
 707         "aseqxp8", "13", "blocken", "berhand",
 708         "reqsintlim", "reqs1", "reqs2", "rd32",
 709         "rd512", "rl1", "rl2", "rl8",
 710         "23", "24", "25", "27",
 711         "28", "wsdevc", "wsdevs", "rwdevpack",
 712 };
 713
 714 static const char *const mite_LKCR_strings[] = {
 715         "amdevice", "1", "2", "3",
 716         "4", "5", "portio", "portvxi",
 717         "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
 718         "12", "13", "14", "berhand",
 719         "16", "17", "18", "rd32",
 720         "rd512", "rl1", "rl2", "rl8",
 721         "24", "25", "26", "27",
 722         "28", "29", "30", "chngend",
 723 };
 724
 725 static const char *const mite_CHSR_strings[] = {
 726         "d.err0", "d.err1", "m.err0", "m.err1",
 727         "l.err0", "l.err1", "drq0", "drq1",
 728         "end", "xferr", "operr0", "operr1",
 729         "stops", "habort", "sabort", "error",
 730         "16", "conts_rb", "18", "linkc",
 731         "20", "drdy", "22", "mrdy",
 732         "24", "done", "26", "sars",
 733         "28", "lpauses", "30", "int",
 734 };
 735
 736 static void mite_decode(const char *const *bit_str, unsigned int bits)
 737 {
 738         int i;
 739
 740         for (i = 31; i >= 0; i--) {
 741                 if (bits & (1 << i))
 742                         pr_debug(" %s\n", bit_str[i]);
 743         }
 744 }
 745
 746 void mite_dump_regs(struct mite_channel *mite_chan)
 747 {
 748         void __iomem *mite_io_addr = mite_chan->mite->mite_io_addr;
 749         unsigned int offset;
 750         unsigned int value;
 751         int channel = mite_chan->channel;
 752
 753         pr_debug("mite_dump_regs ch%i\n", channel);
 754         pr_debug("mite address is  =%p\n", mite_io_addr);
 755
 756         offset = MITE_CHOR(channel);
 757         value = readl(mite_io_addr + offset);
 758         pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset, value);
 759         mite_decode(mite_CHOR_strings, value);
 760         offset = MITE_CHCR(channel);
 761         value = readl(mite_io_addr + offset);
 762         pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset, value);
 763         mite_decode(mite_CHCR_strings, value);
 764         offset = MITE_TCR(channel);
 765         value = readl(mite_io_addr + offset);
 766         pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset, value);
 767         offset = MITE_MCR(channel);
 768         value = readl(mite_io_addr + offset);
 769         pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset, value);
 770         mite_decode(mite_MCR_strings, value);
 771         offset = MITE_MAR(channel);
 772         value = readl(mite_io_addr + offset);
 773         pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset, value);
 774         offset = MITE_DCR(channel);
 775         value = readl(mite_io_addr + offset);
 776         pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset, value);
 777         mite_decode(mite_DCR_strings, value);
 778         offset = MITE_DAR(channel);
 779         value = readl(mite_io_addr + offset);
 780         pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset, value);
 781         offset = MITE_LKCR(channel);
 782         value = readl(mite_io_addr + offset);
 783         pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset, value);
 784         mite_decode(mite_LKCR_strings, value);
 785         offset = MITE_LKAR(channel);
 786         value = readl(mite_io_addr + offset);
 787         pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset, value);
 788         offset = MITE_CHSR(channel);
 789         value = readl(mite_io_addr + offset);
 790         pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset, value);
 791         mite_decode(mite_CHSR_strings, value);
 792         offset = MITE_FCR(channel);
 793         value = readl(mite_io_addr + offset);
 794         pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset, value);
 795 }
 796 EXPORT_SYMBOL(mite_dump_regs);
 797 #endif
 798
 799 static int __init mite_module_init(void)
 800 {
 801         return 0;
 802 }
 803
 804 static void __exit mite_module_exit(void)
 805 {
 806 }
 807
 808 module_init(mite_module_init);
 809 module_exit(mite_module_exit);
 810
 811 MODULE_AUTHOR("Comedi http://www.comedi.org");
 812 MODULE_DESCRIPTION("Comedi low-level driver");
 813 MODULE_LICENSE("GPL");