3 Hardware driver for NI Mite PCI interface chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
22 #include <linux/pci.h>
23 #include <linux/log2.h>
24 #include "../comedidev.h"
26 /* #define DEBUG_MITE */
30 #define MDPRINTK(format, args...) pr_debug(format , ## args)
32 #define MDPRINTK(format, args...) do { } while (0)
35 #define MAX_MITE_DMA_CHANNELS 8
37 struct mite_dma_descriptor {
44 struct mite_dma_descriptor_ring {
45 struct device *hw_dev;
47 struct mite_dma_descriptor *descriptors;
48 dma_addr_t descriptors_dma_addr;
52 struct mite_struct *mite;
56 struct mite_dma_descriptor_ring *ring;
60 struct pci_dev *pcidev;
61 resource_size_t mite_phys_addr;
62 void __iomem *mite_io_addr;
63 resource_size_t daq_phys_addr;
64 void __iomem *daq_io_addr;
65 struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
66 short channel_allocated[MAX_MITE_DMA_CHANNELS];
72 struct mite_struct *mite_alloc(struct pci_dev *pcidev);
74 static inline void mite_free(struct mite_struct *mite)
79 static inline unsigned int mite_irq(struct mite_struct *mite)
81 return mite->pcidev->irq;
84 static inline unsigned int mite_device_id(struct mite_struct *mite)
86 return mite->pcidev->device;
89 int mite_setup(struct mite_struct *mite);
90 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
91 void mite_unsetup(struct mite_struct *mite);
92 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite);
93 void mite_free_ring(struct mite_dma_descriptor_ring *ring);
94 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
96 mite_dma_descriptor_ring
97 *ring, unsigned min_channel,
98 unsigned max_channel);
99 static inline struct mite_channel *mite_request_channel(struct mite_struct
102 mite_dma_descriptor_ring
105 return mite_request_channel_in_range(mite, ring, 0,
106 mite->num_channels - 1);
109 void mite_release_channel(struct mite_channel *mite_chan);
111 unsigned mite_dma_tcr(struct mite_channel *mite_chan);
112 void mite_dma_arm(struct mite_channel *mite_chan);
113 void mite_dma_disarm(struct mite_channel *mite_chan);
114 int mite_sync_input_dma(struct mite_channel *mite_chan,
115 struct comedi_async *async);
116 int mite_sync_output_dma(struct mite_channel *mite_chan,
117 struct comedi_async *async);
118 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
119 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
120 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
121 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
122 u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
123 unsigned mite_get_status(struct mite_channel *mite_chan);
124 int mite_done(struct mite_channel *mite_chan);
126 void mite_prep_dma(struct mite_channel *mite_chan,
127 unsigned int num_device_bits, unsigned int num_memory_bits);
128 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
129 struct comedi_async *async);
132 void mite_print_chsr(unsigned int chsr);
133 void mite_dump_regs(struct mite_channel *mite_chan);
136 static inline int CHAN_OFFSET(int channel)
138 return 0x500 + 0x100 * channel;
141 enum mite_registers {
142 /* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
143 written and read back. The bits 0x1f always read as 1.
144 The rest always read as zero. */
145 MITE_UNKNOWN_DMA_BURST_REG = 0x28,
146 MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */
147 MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */
148 MITE_IODWCR_1 = 0xf4,
149 MITE_PCI_CONFIG_OFFSET = 0x300,
150 MITE_CSIGR = 0x460 /* chip signature */
152 static inline int MITE_CHOR(int channel)
153 { /* channel operation */
154 return CHAN_OFFSET(channel) + 0x0;
157 static inline int MITE_CHCR(int channel)
158 { /* channel control */
159 return CHAN_OFFSET(channel) + 0x4;
162 static inline int MITE_TCR(int channel)
163 { /* transfer count */
164 return CHAN_OFFSET(channel) + 0x8;
167 static inline int MITE_MCR(int channel)
168 { /* memory configuration */
169 return CHAN_OFFSET(channel) + 0xc;
172 static inline int MITE_MAR(int channel)
173 { /* memory address */
174 return CHAN_OFFSET(channel) + 0x10;
177 static inline int MITE_DCR(int channel)
178 { /* device configuration */
179 return CHAN_OFFSET(channel) + 0x14;
182 static inline int MITE_DAR(int channel)
183 { /* device address */
184 return CHAN_OFFSET(channel) + 0x18;
187 static inline int MITE_LKCR(int channel)
188 { /* link configuration */
189 return CHAN_OFFSET(channel) + 0x1c;
192 static inline int MITE_LKAR(int channel)
194 return CHAN_OFFSET(channel) + 0x20;
197 static inline int MITE_LLKAR(int channel)
198 { /* see mite section of tnt5002 manual */
199 return CHAN_OFFSET(channel) + 0x24;
202 static inline int MITE_BAR(int channel)
204 return CHAN_OFFSET(channel) + 0x28;
207 static inline int MITE_BCR(int channel)
209 return CHAN_OFFSET(channel) + 0x2c;
212 static inline int MITE_SAR(int channel)
214 return CHAN_OFFSET(channel) + 0x30;
217 static inline int MITE_WSCR(int channel)
219 return CHAN_OFFSET(channel) + 0x34;
222 static inline int MITE_WSER(int channel)
224 return CHAN_OFFSET(channel) + 0x38;
227 static inline int MITE_CHSR(int channel)
228 { /* channel status */
229 return CHAN_OFFSET(channel) + 0x3c;
232 static inline int MITE_FCR(int channel)
234 return CHAN_OFFSET(channel) + 0x40;
237 enum MITE_IODWBSR_bits {
238 WENAB = 0x80, /* window enable */
241 static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
248 return (order - 1) & 0x1f;
251 enum MITE_UNKNOWN_DMA_BURST_bits {
252 UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
255 static inline int mite_csigr_version(u32 csigr_bits)
257 return csigr_bits & 0xf;
260 static inline int mite_csigr_type(u32 csigr_bits)
261 { /* original mite = 0, minimite = 1 */
262 return (csigr_bits >> 4) & 0xf;
265 static inline int mite_csigr_mmode(u32 csigr_bits)
266 { /* mite mode, minimite = 1 */
267 return (csigr_bits >> 8) & 0x3;
270 static inline int mite_csigr_imode(u32 csigr_bits)
271 { /* cpu port interface mode, pci = 0x3 */
272 return (csigr_bits >> 12) & 0x3;
275 static inline int mite_csigr_dmac(u32 csigr_bits)
276 { /* number of dma channels */
277 return (csigr_bits >> 16) & 0xf;
280 static inline int mite_csigr_wpdep(u32 csigr_bits)
281 { /* write post fifo depth */
282 unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
286 return 1 << (wpdep_bits - 1);
289 static inline int mite_csigr_wins(u32 csigr_bits)
291 return (csigr_bits >> 24) & 0x1f;
294 static inline int mite_csigr_iowins(u32 csigr_bits)
295 { /* number of io windows */
296 return (csigr_bits >> 29) & 0x7;
304 DCR_NORMAL = (1 << 29),
308 enum MITE_CHOR_bits {
309 CHOR_DMARESET = (1 << 31),
310 CHOR_SET_SEND_TC = (1 << 11),
311 CHOR_CLR_SEND_TC = (1 << 10),
312 CHOR_SET_LPAUSE = (1 << 9),
313 CHOR_CLR_LPAUSE = (1 << 8),
314 CHOR_CLRDONE = (1 << 7),
315 CHOR_CLRRB = (1 << 6),
316 CHOR_CLRLC = (1 << 5),
317 CHOR_FRESET = (1 << 4),
318 CHOR_ABORT = (1 << 3), /* stop without emptying fifo */
319 CHOR_STOP = (1 << 2), /* stop after emptying fifo */
320 CHOR_CONT = (1 << 1),
321 CHOR_START = (1 << 0),
322 CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
325 enum MITE_CHCR_bits {
326 CHCR_SET_DMA_IE = (1 << 31),
327 CHCR_CLR_DMA_IE = (1 << 30),
328 CHCR_SET_LINKP_IE = (1 << 29),
329 CHCR_CLR_LINKP_IE = (1 << 28),
330 CHCR_SET_SAR_IE = (1 << 27),
331 CHCR_CLR_SAR_IE = (1 << 26),
332 CHCR_SET_DONE_IE = (1 << 25),
333 CHCR_CLR_DONE_IE = (1 << 24),
334 CHCR_SET_MRDY_IE = (1 << 23),
335 CHCR_CLR_MRDY_IE = (1 << 22),
336 CHCR_SET_DRDY_IE = (1 << 21),
337 CHCR_CLR_DRDY_IE = (1 << 20),
338 CHCR_SET_LC_IE = (1 << 19),
339 CHCR_CLR_LC_IE = (1 << 18),
340 CHCR_SET_CONT_RB_IE = (1 << 17),
341 CHCR_CLR_CONT_RB_IE = (1 << 16),
342 CHCR_FIFODIS = (1 << 15),
344 CHCR_BURSTEN = (1 << 14),
346 CHCR_BYTE_SWAP_DEVICE = (1 << 6),
347 CHCR_BYTE_SWAP_MEMORY = (1 << 4),
349 CHCR_DEV_TO_MEM = CHCR_DIR,
351 CHCR_NORMAL = (0 << 0),
352 CHCR_CONTINUE = (1 << 0),
353 CHCR_RINGBUFF = (2 << 0),
354 CHCR_LINKSHORT = (4 << 0),
355 CHCR_LINKLONG = (5 << 0),
357 (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
358 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
359 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
362 enum ConfigRegister_bits {
363 CR_REQS_MASK = 0x7 << 16,
364 CR_ASEQDONT = 0x0 << 10,
365 CR_ASEQUP = 0x1 << 10,
366 CR_ASEQDOWN = 0x2 << 10,
367 CR_ASEQ_MASK = 0x3 << 10,
368 CR_PSIZE8 = (1 << 8),
369 CR_PSIZE16 = (2 << 8),
370 CR_PSIZE32 = (3 << 8),
371 CR_PORTCPU = (0 << 6),
372 CR_PORTIO = (1 << 6),
373 CR_PORTVXI = (2 << 6),
374 CR_PORTMXI = (3 << 6),
375 CR_AMDEVICE = (1 << 0),
377 static inline int CR_REQS(int source)
379 return (source & 0x7) << 16;
382 static inline int CR_REQSDRQ(unsigned drq_line)
384 /* This also works on m-series when
385 using channels (drq_line) 4 or 5. */
386 return CR_REQS((drq_line & 0x3) | 0x4);
389 static inline int CR_RL(unsigned int retry_limit)
394 value = 1 + ilog2(retry_limit);
397 return (value & 0x7) << 21;
401 CHSR_INT = (1 << 31),
402 CHSR_LPAUSES = (1 << 29),
403 CHSR_SARS = (1 << 27),
404 CHSR_DONE = (1 << 25),
405 CHSR_MRDY = (1 << 23),
406 CHSR_DRDY = (1 << 21),
407 CHSR_LINKC = (1 << 19),
408 CHSR_CONTS_RB = (1 << 17),
409 CHSR_ERROR = (1 << 15),
410 CHSR_SABORT = (1 << 14),
411 CHSR_HABORT = (1 << 13),
412 CHSR_STOPS = (1 << 12),
413 CHSR_OPERR_mask = (3 << 10),
414 CHSR_OPERR_NOERROR = (0 << 10),
415 CHSR_OPERR_FIFOERROR = (1 << 10),
416 CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */
417 CHSR_XFERR = (1 << 9),
419 CHSR_DRQ1 = (1 << 7),
420 CHSR_DRQ0 = (1 << 6),
421 CHSR_LxERR_mask = (3 << 4),
422 CHSR_LBERR = (1 << 4),
423 CHSR_LRERR = (2 << 4),
424 CHSR_LOERR = (3 << 4),
425 CHSR_MxERR_mask = (3 << 2),
426 CHSR_MBERR = (1 << 2),
427 CHSR_MRERR = (2 << 2),
428 CHSR_MOERR = (3 << 2),
429 CHSR_DxERR_mask = (3 << 0),
430 CHSR_DBERR = (1 << 0),
431 CHSR_DRERR = (2 << 0),
432 CHSR_DOERR = (3 << 0),
435 static inline void mite_dma_reset(struct mite_channel *mite_chan)
437 writel(CHOR_DMARESET | CHOR_FRESET,
438 mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));