drivers/staging/comedi/drivers/ni_6527.c

   1 /*
   2     comedi/drivers/ni_6527.c
   3     driver for National Instruments PCI-6527
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23 /*
  24 Driver: ni_6527
  25 Description: National Instruments 6527
  26 Author: ds
  27 Status: works
  28 Devices: [National Instruments] PCI-6527 (ni6527), PXI-6527
  29 Updated: Sat, 25 Jan 2003 13:24:40 -0800
  30
  31
  32 */
  33
  34 /*
  35    Manuals (available from ftp://ftp.natinst.com/support/manuals)
  36
  37         370106b.pdf     6527 Register Level Programmer Manual
  38
  39  */
  40
  41 #define DEBUG 1
  42 #define DEBUG_FLAGS
  43
  44 #include <linux/pci.h>
  45 #include <linux/interrupt.h>
  46
  47 #include "../comedidev.h"
  48
  49 #include "comedi_fc.h"
  50 #include "mite.h"
  51
  52 #define DRIVER_NAME "ni_6527"
  53
  54 #define NI6527_DIO_SIZE 4096
  55 #define NI6527_MITE_SIZE 4096
  56
  57 #define Port_Register(x)                        (0x00+(x))
  58 #define ID_Register                             0x06
  59
  60 #define Clear_Register                          0x07
  61 #define ClrEdge                         0x08
  62 #define ClrOverflow                     0x04
  63 #define ClrFilter                       0x02
  64 #define ClrInterval                     0x01
  65
  66 #define Filter_Interval(x)                      (0x08+(x))
  67 #define Filter_Enable(x)                        (0x0c+(x))
  68
  69 #define Change_Status                           0x14
  70 #define MasterInterruptStatus           0x04
  71 #define Overflow                        0x02
  72 #define EdgeStatus                      0x01
  73
  74 #define Master_Interrupt_Control                0x15
  75 #define FallingEdgeIntEnable            0x10
  76 #define RisingEdgeIntEnable             0x08
  77 #define MasterInterruptEnable           0x04
  78 #define OverflowIntEnable               0x02
  79 #define EdgeIntEnable                   0x01
  80
  81 #define Rising_Edge_Detection_Enable(x)         (0x018+(x))
  82 #define Falling_Edge_Detection_Enable(x)        (0x020+(x))
  83
  84 enum ni6527_boardid {
  85         BOARD_PCI6527,
  86         BOARD_PXI6527,
  87 };
  88
  89 struct ni6527_board {
  90         const char *name;
  91 };
  92
  93 static const struct ni6527_board ni6527_boards[] = {
  94         [BOARD_PCI6527] = {
  95                 .name           = "pci-6527",
  96         },
  97         [BOARD_PXI6527] = {
  98                 .name           = "pxi-6527",
  99         },
 100 };
 101
 102 struct ni6527_private {
 103         struct mite_struct *mite;
 104         unsigned int filter_interval;
 105         unsigned int filter_enable;
 106 };
 107
 108 static int ni6527_di_insn_config(struct comedi_device *dev,
 109                                  struct comedi_subdevice *s,
 110                                  struct comedi_insn *insn, unsigned int *data)
 111 {
 112         struct ni6527_private *devpriv = dev->private;
 113         int chan = CR_CHAN(insn->chanspec);
 114         unsigned int interval;
 115
 116         if (insn->n != 2)
 117                 return -EINVAL;
 118
 119         if (data[0] != INSN_CONFIG_FILTER)
 120                 return -EINVAL;
 121
 122         if (data[1]) {
 123                 interval = (data[1] + 100) / 200;
 124                 data[1] = interval * 200;
 125
 126                 if (interval != devpriv->filter_interval) {
 127                         writeb(interval & 0xff,
 128                                devpriv->mite->daq_io_addr + Filter_Interval(0));
 129                         writeb((interval >> 8) & 0xff,
 130                                devpriv->mite->daq_io_addr + Filter_Interval(1));
 131                         writeb((interval >> 16) & 0x0f,
 132                                devpriv->mite->daq_io_addr + Filter_Interval(2));
 133
 134                         writeb(ClrInterval,
 135                                devpriv->mite->daq_io_addr + Clear_Register);
 136
 137                         devpriv->filter_interval = interval;
 138                 }
 139
 140                 devpriv->filter_enable |= 1 << chan;
 141         } else {
 142                 devpriv->filter_enable &= ~(1 << chan);
 143         }
 144
 145         writeb(devpriv->filter_enable,
 146                devpriv->mite->daq_io_addr + Filter_Enable(0));
 147         writeb(devpriv->filter_enable >> 8,
 148                devpriv->mite->daq_io_addr + Filter_Enable(1));
 149         writeb(devpriv->filter_enable >> 16,
 150                devpriv->mite->daq_io_addr + Filter_Enable(2));
 151
 152         return 2;
 153 }
 154
 155 static int ni6527_di_insn_bits(struct comedi_device *dev,
 156                                struct comedi_subdevice *s,
 157                                struct comedi_insn *insn, unsigned int *data)
 158 {
 159         struct ni6527_private *devpriv = dev->private;
 160
 161         data[1] = readb(devpriv->mite->daq_io_addr + Port_Register(0));
 162         data[1] |= readb(devpriv->mite->daq_io_addr + Port_Register(1)) << 8;
 163         data[1] |= readb(devpriv->mite->daq_io_addr + Port_Register(2)) << 16;
 164
 165         return insn->n;
 166 }
 167
 168 static int ni6527_do_insn_bits(struct comedi_device *dev,
 169                                struct comedi_subdevice *s,
 170                                struct comedi_insn *insn, unsigned int *data)
 171 {
 172         struct ni6527_private *devpriv = dev->private;
 173
 174         if (data[0]) {
 175                 s->state &= ~data[0];
 176                 s->state |= (data[0] & data[1]);
 177
 178                 /* The open relay state on the board cooresponds to 1,
 179                  * but in Comedi, it is represented by 0. */
 180                 if (data[0] & 0x0000ff) {
 181                         writeb((s->state ^ 0xff),
 182                                devpriv->mite->daq_io_addr + Port_Register(3));
 183                 }
 184                 if (data[0] & 0x00ff00) {
 185                         writeb((s->state >> 8) ^ 0xff,
 186                                devpriv->mite->daq_io_addr + Port_Register(4));
 187                 }
 188                 if (data[0] & 0xff0000) {
 189                         writeb((s->state >> 16) ^ 0xff,
 190                                devpriv->mite->daq_io_addr + Port_Register(5));
 191                 }
 192         }
 193         data[1] = s->state;
 194
 195         return insn->n;
 196 }
 197
 198 static irqreturn_t ni6527_interrupt(int irq, void *d)
 199 {
 200         struct comedi_device *dev = d;
 201         struct ni6527_private *devpriv = dev->private;
 202         struct comedi_subdevice *s = &dev->subdevices[2];
 203         unsigned int status;
 204
 205         status = readb(devpriv->mite->daq_io_addr + Change_Status);
 206         if ((status & MasterInterruptStatus) == 0)
 207                 return IRQ_NONE;
 208         if ((status & EdgeStatus) == 0)
 209                 return IRQ_NONE;
 210
 211         writeb(ClrEdge | ClrOverflow,
 212                devpriv->mite->daq_io_addr + Clear_Register);
 213
 214         comedi_buf_put(s->async, 0);
 215         s->async->events |= COMEDI_CB_EOS;
 216         comedi_event(dev, s);
 217         return IRQ_HANDLED;
 218 }
 219
 220 static int ni6527_intr_cmdtest(struct comedi_device *dev,
 221                                struct comedi_subdevice *s,
 222                                struct comedi_cmd *cmd)
 223 {
 224         int err = 0;
 225
 226         /* Step 1 : check if triggers are trivially valid */
 227
 228         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
 229         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
 230         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
 231         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 232         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
 233
 234         if (err)
 235                 return 1;
 236
 237         /* Step 2a : make sure trigger sources are unique */
 238         /* Step 2b : and mutually compatible */
 239
 240         if (err)
 241                 return 2;
 242
 243         /* Step 3: check if arguments are trivially valid */
 244
 245         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
 246         err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
 247         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
 248         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
 249         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
 250
 251         if (err)
 252                 return 3;
 253
 254         /* step 4: fix up any arguments */
 255
 256         if (err)
 257                 return 4;
 258
 259         return 0;
 260 }
 261
 262 static int ni6527_intr_cmd(struct comedi_device *dev,
 263                            struct comedi_subdevice *s)
 264 {
 265         struct ni6527_private *devpriv = dev->private;
 266         /* struct comedi_cmd *cmd = &s->async->cmd; */
 267
 268         writeb(ClrEdge | ClrOverflow,
 269                devpriv->mite->daq_io_addr + Clear_Register);
 270         writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
 271                MasterInterruptEnable | EdgeIntEnable,
 272                devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 273
 274         return 0;
 275 }
 276
 277 static int ni6527_intr_cancel(struct comedi_device *dev,
 278                               struct comedi_subdevice *s)
 279 {
 280         struct ni6527_private *devpriv = dev->private;
 281
 282         writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 283
 284         return 0;
 285 }
 286
 287 static int ni6527_intr_insn_bits(struct comedi_device *dev,
 288                                  struct comedi_subdevice *s,
 289                                  struct comedi_insn *insn, unsigned int *data)
 290 {
 291         data[1] = 0;
 292         return insn->n;
 293 }
 294
 295 static int ni6527_intr_insn_config(struct comedi_device *dev,
 296                                    struct comedi_subdevice *s,
 297                                    struct comedi_insn *insn, unsigned int *data)
 298 {
 299         struct ni6527_private *devpriv = dev->private;
 300
 301         if (insn->n < 1)
 302                 return -EINVAL;
 303         if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
 304                 return -EINVAL;
 305
 306         writeb(data[1],
 307                devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(0));
 308         writeb(data[1] >> 8,
 309                devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(1));
 310         writeb(data[1] >> 16,
 311                devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(2));
 312
 313         writeb(data[2],
 314                devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(0));
 315         writeb(data[2] >> 8,
 316                devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(1));
 317         writeb(data[2] >> 16,
 318                devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(2));
 319
 320         return 2;
 321 }
 322
 323 static int ni6527_auto_attach(struct comedi_device *dev,
 324                               unsigned long context)
 325 {
 326         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 327         const struct ni6527_board *board = NULL;
 328         struct ni6527_private *devpriv;
 329         struct comedi_subdevice *s;
 330         int ret;
 331
 332         if (context < ARRAY_SIZE(ni6527_boards))
 333                 board = &ni6527_boards[context];
 334         if (!board)
 335                 return -ENODEV;
 336         dev->board_ptr = board;
 337         dev->board_name = board->name;
 338
 339         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 340         if (!devpriv)
 341                 return -ENOMEM;
 342         dev->private = devpriv;
 343
 344         devpriv->mite = mite_alloc(pcidev);
 345         if (!devpriv->mite)
 346                 return -ENOMEM;
 347
 348         ret = mite_setup(devpriv->mite);
 349         if (ret < 0) {
 350                 dev_err(dev->class_dev, "error setting up mite\n");
 351                 return ret;
 352         }
 353         dev->iobase = 1;
 354
 355         dev_info(dev->class_dev, "board: %s, ID=0x%02x\n", dev->board_name,
 356                  readb(devpriv->mite->daq_io_addr + ID_Register));
 357
 358         ret = comedi_alloc_subdevices(dev, 3);
 359         if (ret)
 360                 return ret;
 361
 362         s = &dev->subdevices[0];
 363         s->type = COMEDI_SUBD_DI;
 364         s->subdev_flags = SDF_READABLE;
 365         s->n_chan = 24;
 366         s->range_table = &range_digital;
 367         s->maxdata = 1;
 368         s->insn_config = ni6527_di_insn_config;
 369         s->insn_bits = ni6527_di_insn_bits;
 370
 371         s = &dev->subdevices[1];
 372         s->type = COMEDI_SUBD_DO;
 373         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
 374         s->n_chan = 24;
 375         s->range_table = &range_unknown;  /* FIXME: actually conductance */
 376         s->maxdata = 1;
 377         s->insn_bits = ni6527_do_insn_bits;
 378
 379         s = &dev->subdevices[2];
 380         dev->read_subdev = s;
 381         s->type = COMEDI_SUBD_DI;
 382         s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
 383         s->n_chan = 1;
 384         s->range_table = &range_unknown;
 385         s->maxdata = 1;
 386         s->do_cmdtest = ni6527_intr_cmdtest;
 387         s->do_cmd = ni6527_intr_cmd;
 388         s->cancel = ni6527_intr_cancel;
 389         s->insn_bits = ni6527_intr_insn_bits;
 390         s->insn_config = ni6527_intr_insn_config;
 391
 392         writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(0));
 393         writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(1));
 394         writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(2));
 395
 396         writeb(ClrEdge | ClrOverflow | ClrFilter | ClrInterval,
 397                devpriv->mite->daq_io_addr + Clear_Register);
 398         writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 399
 400         ret = request_irq(mite_irq(devpriv->mite), ni6527_interrupt,
 401                           IRQF_SHARED, DRIVER_NAME, dev);
 402         if (ret < 0)
 403                 dev_warn(dev->class_dev, "irq not available\n");
 404         else
 405                 dev->irq = mite_irq(devpriv->mite);
 406
 407         return 0;
 408 }
 409
 410 static void ni6527_detach(struct comedi_device *dev)
 411 {
 412         struct ni6527_private *devpriv = dev->private;
 413
 414         if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr)
 415                 writeb(0x00,
 416                        devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 417         if (dev->irq)
 418                 free_irq(dev->irq, dev);
 419         if (devpriv && devpriv->mite) {
 420                 mite_unsetup(devpriv->mite);
 421                 mite_free(devpriv->mite);
 422         }
 423         comedi_pci_disable(dev);
 424 }
 425
 426 static struct comedi_driver ni6527_driver = {
 427         .driver_name = DRIVER_NAME,
 428         .module = THIS_MODULE,
 429         .auto_attach = ni6527_auto_attach,
 430         .detach = ni6527_detach,
 431 };
 432
 433 static int ni6527_pci_probe(struct pci_dev *dev,
 434                             const struct pci_device_id *id)
 435 {
 436         return comedi_pci_auto_config(dev, &ni6527_driver, id->driver_data);
 437 }
 438
 439 static DEFINE_PCI_DEVICE_TABLE(ni6527_pci_table) = {
 440         { PCI_VDEVICE(NI, 0x2b10), BOARD_PXI6527 },
 441         { PCI_VDEVICE(NI, 0x2b20), BOARD_PCI6527 },
 442         { 0 }
 443 };
 444 MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
 445
 446 static struct pci_driver ni6527_pci_driver = {
 447         .name           = DRIVER_NAME,
 448         .id_table       = ni6527_pci_table,
 449         .probe          = ni6527_pci_probe,
 450         .remove         = comedi_pci_auto_unconfig,
 451 };
 452 module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
 453
 454 MODULE_AUTHOR("Comedi http://www.comedi.org");
 455 MODULE_DESCRIPTION("Comedi low-level driver");
 456 MODULE_LICENSE("GPL");