2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Description: National Instruments 65xx static dio boards
29 Author: Jon Grierson <jd@renko.co.uk>, Frank Mori Hess <fmhess@users.sourceforge.net>
31 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510, PCI-6511,
32 PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514, PXI-6514, PCI-6515,
33 PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519, PCI-6520, PCI-6521, PXI-6521,
35 Updated: Wed Oct 18 08:59:11 EDT 2006
37 Based on the PCI-6527 driver by ds.
38 The interrupt subdevice (subdevice 3) is probably broken for all boards
39 except maybe the 6514.
44 Manuals (available from ftp://ftp.natinst.com/support/manuals)
46 370106b.pdf 6514 Register Level Programmer Manual
53 #include <linux/interrupt.h>
54 #include "../comedidev.h"
58 #define NI6514_DIO_SIZE 4096
59 #define NI6514_MITE_SIZE 4096
61 #define NI_65XX_MAX_NUM_PORTS 12
62 static const unsigned ni_65xx_channels_per_port = 8;
63 static const unsigned ni_65xx_port_offset = 0x10;
65 static inline unsigned Port_Data(unsigned port)
67 return 0x40 + port * ni_65xx_port_offset;
70 static inline unsigned Port_Select(unsigned port)
72 return 0x41 + port * ni_65xx_port_offset;
75 static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
77 return 0x42 + port * ni_65xx_port_offset;
80 static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
82 return 0x43 + port * ni_65xx_port_offset;
85 static inline unsigned Filter_Enable(unsigned port)
87 return 0x44 + port * ni_65xx_port_offset;
90 #define ID_Register 0x00
92 #define Clear_Register 0x01
94 #define ClrOverflow 0x04
96 #define Filter_Interval 0x08
98 #define Change_Status 0x02
99 #define MasterInterruptStatus 0x04
100 #define Overflow 0x02
101 #define EdgeStatus 0x01
103 #define Master_Interrupt_Control 0x03
104 #define FallingEdgeIntEnable 0x10
105 #define RisingEdgeIntEnable 0x08
106 #define MasterInterruptEnable 0x04
107 #define OverflowIntEnable 0x02
108 #define EdgeIntEnable 0x01
110 static int ni_65xx_attach(struct comedi_device *dev,
111 struct comedi_devconfig *it);
112 static int ni_65xx_detach(struct comedi_device *dev);
113 static struct comedi_driver driver_ni_65xx = {
114 .driver_name = "ni_65xx",
115 .module = THIS_MODULE,
116 .attach = ni_65xx_attach,
117 .detach = ni_65xx_detach,
120 struct ni_65xx_board {
124 unsigned num_dio_ports;
125 unsigned num_di_ports;
126 unsigned num_do_ports;
127 unsigned invert_outputs:1;
130 static const struct ni_65xx_board ni_65xx_boards[] = {
135 .invert_outputs = 0},
140 .invert_outputs = 0},
165 .invert_outputs = 1},
170 .invert_outputs = 1},
176 .invert_outputs = 1},
182 .invert_outputs = 1},
188 .invert_outputs = 1},
194 .invert_outputs = 1},
199 .invert_outputs = 1},
204 .invert_outputs = 1},
210 .invert_outputs = 1},
216 .invert_outputs = 1},
249 #define n_ni_65xx_boards ARRAY_SIZE(ni_65xx_boards)
250 static inline const struct ni_65xx_board *board(struct comedi_device *dev)
252 return dev->board_ptr;
255 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
257 return channel / ni_65xx_channels_per_port;
260 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
263 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
266 static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table) = {
268 PCI_VENDOR_ID_NATINST, 0x1710, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
269 PCI_VENDOR_ID_NATINST, 0x7085, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
270 PCI_VENDOR_ID_NATINST, 0x7086, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
271 PCI_VENDOR_ID_NATINST, 0x7087, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
272 PCI_VENDOR_ID_NATINST, 0x7088, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
273 PCI_VENDOR_ID_NATINST, 0x70a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
274 PCI_VENDOR_ID_NATINST, 0x70c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
275 PCI_VENDOR_ID_NATINST, 0x70c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
276 PCI_VENDOR_ID_NATINST, 0x70c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
277 PCI_VENDOR_ID_NATINST, 0x70cc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
278 PCI_VENDOR_ID_NATINST, 0x70CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
279 PCI_VENDOR_ID_NATINST, 0x70d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
280 PCI_VENDOR_ID_NATINST, 0x70d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
281 PCI_VENDOR_ID_NATINST, 0x70d3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
282 PCI_VENDOR_ID_NATINST, 0x7124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
283 PCI_VENDOR_ID_NATINST, 0x7125, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
284 PCI_VENDOR_ID_NATINST, 0x7126, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
285 PCI_VENDOR_ID_NATINST, 0x7127, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
286 PCI_VENDOR_ID_NATINST, 0x7128, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
287 PCI_VENDOR_ID_NATINST, 0x718b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
288 PCI_VENDOR_ID_NATINST, 0x718c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
289 PCI_VENDOR_ID_NATINST, 0x71c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
293 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
295 struct ni_65xx_private {
296 struct mite_struct *mite;
297 unsigned int filter_interval;
298 unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
299 unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
300 unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
303 static inline struct ni_65xx_private *private(struct comedi_device *dev)
308 struct ni_65xx_subdevice_private {
312 static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
315 return subdev->private;
318 static struct ni_65xx_subdevice_private *ni_65xx_alloc_subdevice_private(void)
320 struct ni_65xx_subdevice_private *subdev_private =
321 kzalloc(sizeof(struct ni_65xx_subdevice_private), GFP_KERNEL);
322 if (subdev_private == NULL)
324 return subdev_private;
327 static int ni_65xx_find_device(struct comedi_device *dev, int bus, int slot);
329 static int ni_65xx_config_filter(struct comedi_device *dev,
330 struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data)
333 const unsigned chan = CR_CHAN(insn->chanspec);
334 const unsigned port =
335 sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
337 if (data[0] != INSN_CONFIG_FILTER)
340 static const unsigned filter_resolution_ns = 200;
341 static const unsigned max_filter_interval = 0xfffff;
344 (filter_resolution_ns / 2)) / filter_resolution_ns;
345 if (interval > max_filter_interval)
346 interval = max_filter_interval;
347 data[1] = interval * filter_resolution_ns;
349 if (interval != private(dev)->filter_interval) {
351 private(dev)->mite->daq_io_addr +
353 private(dev)->filter_interval = interval;
356 private(dev)->filter_enable[port] |=
357 1 << (chan % ni_65xx_channels_per_port);
359 private(dev)->filter_enable[port] &=
360 ~(1 << (chan % ni_65xx_channels_per_port));
363 writeb(private(dev)->filter_enable[port],
364 private(dev)->mite->daq_io_addr + Filter_Enable(port));
369 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
370 struct comedi_subdevice *s,
371 struct comedi_insn *insn, unsigned int *data)
377 port = sprivate(s)->base_port +
378 ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
380 case INSN_CONFIG_FILTER:
381 return ni_65xx_config_filter(dev, s, insn, data);
383 case INSN_CONFIG_DIO_OUTPUT:
384 if (s->type != COMEDI_SUBD_DIO)
386 private(dev)->dio_direction[port] = COMEDI_OUTPUT;
387 writeb(0, private(dev)->mite->daq_io_addr + Port_Select(port));
390 case INSN_CONFIG_DIO_INPUT:
391 if (s->type != COMEDI_SUBD_DIO)
393 private(dev)->dio_direction[port] = COMEDI_INPUT;
394 writeb(1, private(dev)->mite->daq_io_addr + Port_Select(port));
397 case INSN_CONFIG_DIO_QUERY:
398 if (s->type != COMEDI_SUBD_DIO)
400 data[1] = private(dev)->dio_direction[port];
409 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
410 struct comedi_subdevice *s,
411 struct comedi_insn *insn, unsigned int *data)
413 unsigned base_bitfield_channel;
414 const unsigned max_ports_per_bitfield = 5;
415 unsigned read_bits = 0;
419 base_bitfield_channel = CR_CHAN(insn->chanspec);
420 for (j = 0; j < max_ports_per_bitfield; ++j) {
421 const unsigned port_offset = ni_65xx_port_by_channel(base_bitfield_channel) + j;
422 const unsigned port =
423 sprivate(s)->base_port + port_offset;
424 unsigned base_port_channel;
425 unsigned port_mask, port_data, port_read_bits;
427 if (port >= ni_65xx_total_num_ports(board(dev)))
429 base_port_channel = port_offset * ni_65xx_channels_per_port;
432 bitshift = base_port_channel - base_bitfield_channel;
433 if (bitshift >= 32 || bitshift <= -32)
436 port_mask >>= bitshift;
437 port_data >>= bitshift;
439 port_mask <<= -bitshift;
440 port_data <<= -bitshift;
446 private(dev)->output_bits[port] &= ~port_mask;
447 private(dev)->output_bits[port] |=
448 port_data & port_mask;
449 bits = private(dev)->output_bits[port];
450 if (board(dev)->invert_outputs)
453 private(dev)->mite->daq_io_addr +
455 /* printk("wrote 0x%x to port %i\n", bits, port); */
458 readb(private(dev)->mite->daq_io_addr + Port_Data(port));
459 /* printk("read 0x%x from port %i\n", port_read_bits, port); */
460 if (s->type == COMEDI_SUBD_DO && board(dev)->invert_outputs) {
461 /* Outputs inverted, so invert value read back from
462 * DO subdevice. (Does not apply to boards with DIO
464 port_read_bits ^= 0xFF;
467 port_read_bits <<= bitshift;
469 port_read_bits >>= -bitshift;
471 read_bits |= port_read_bits;
477 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
479 struct comedi_device *dev = d;
480 struct comedi_subdevice *s = dev->subdevices + 2;
483 status = readb(private(dev)->mite->daq_io_addr + Change_Status);
484 if ((status & MasterInterruptStatus) == 0)
486 if ((status & EdgeStatus) == 0)
489 writeb(ClrEdge | ClrOverflow,
490 private(dev)->mite->daq_io_addr + Clear_Register);
492 comedi_buf_put(s->async, 0);
493 s->async->events |= COMEDI_CB_EOS;
494 comedi_event(dev, s);
498 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
499 struct comedi_subdevice *s,
500 struct comedi_cmd *cmd)
505 /* step 1: make sure trigger sources are trivially valid */
507 tmp = cmd->start_src;
508 cmd->start_src &= TRIG_NOW;
509 if (!cmd->start_src || tmp != cmd->start_src)
512 tmp = cmd->scan_begin_src;
513 cmd->scan_begin_src &= TRIG_OTHER;
514 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
517 tmp = cmd->convert_src;
518 cmd->convert_src &= TRIG_FOLLOW;
519 if (!cmd->convert_src || tmp != cmd->convert_src)
522 tmp = cmd->scan_end_src;
523 cmd->scan_end_src &= TRIG_COUNT;
524 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
528 cmd->stop_src &= TRIG_COUNT;
529 if (!cmd->stop_src || tmp != cmd->stop_src)
535 /* step 2: make sure trigger sources are unique and mutually compatible */
540 /* step 3: make sure arguments are trivially compatible */
542 if (cmd->start_arg != 0) {
546 if (cmd->scan_begin_arg != 0) {
547 cmd->scan_begin_arg = 0;
550 if (cmd->convert_arg != 0) {
551 cmd->convert_arg = 0;
555 if (cmd->scan_end_arg != 1) {
556 cmd->scan_end_arg = 1;
559 if (cmd->stop_arg != 0) {
567 /* step 4: fix up any arguments */
575 static int ni_65xx_intr_cmd(struct comedi_device *dev,
576 struct comedi_subdevice *s)
578 /* struct comedi_cmd *cmd = &s->async->cmd; */
580 writeb(ClrEdge | ClrOverflow,
581 private(dev)->mite->daq_io_addr + Clear_Register);
582 writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
583 MasterInterruptEnable | EdgeIntEnable,
584 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
589 static int ni_65xx_intr_cancel(struct comedi_device *dev,
590 struct comedi_subdevice *s)
593 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
598 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
599 struct comedi_subdevice *s,
600 struct comedi_insn *insn, unsigned int *data)
609 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
610 struct comedi_subdevice *s,
611 struct comedi_insn *insn,
616 if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
620 private(dev)->mite->daq_io_addr +
621 Rising_Edge_Detection_Enable(0));
623 private(dev)->mite->daq_io_addr +
624 Rising_Edge_Detection_Enable(0x10));
625 writeb(data[1] >> 16,
626 private(dev)->mite->daq_io_addr +
627 Rising_Edge_Detection_Enable(0x20));
628 writeb(data[1] >> 24,
629 private(dev)->mite->daq_io_addr +
630 Rising_Edge_Detection_Enable(0x30));
633 private(dev)->mite->daq_io_addr +
634 Falling_Edge_Detection_Enable(0));
636 private(dev)->mite->daq_io_addr +
637 Falling_Edge_Detection_Enable(0x10));
638 writeb(data[2] >> 16,
639 private(dev)->mite->daq_io_addr +
640 Falling_Edge_Detection_Enable(0x20));
641 writeb(data[2] >> 24,
642 private(dev)->mite->daq_io_addr +
643 Falling_Edge_Detection_Enable(0x30));
648 static int ni_65xx_attach(struct comedi_device *dev,
649 struct comedi_devconfig *it)
651 struct comedi_subdevice *s;
655 printk("comedi%d: ni_65xx:", dev->minor);
657 ret = alloc_private(dev, sizeof(struct ni_65xx_private));
661 ret = ni_65xx_find_device(dev, it->options[0], it->options[1]);
665 ret = mite_setup(private(dev)->mite);
667 printk("error setting up mite\n");
671 dev->board_name = board(dev)->name;
672 dev->irq = mite_irq(private(dev)->mite);
673 printk(" %s", dev->board_name);
676 readb(private(dev)->mite->daq_io_addr + ID_Register));
678 ret = alloc_subdevices(dev, 4);
682 s = dev->subdevices + 0;
683 if (board(dev)->num_di_ports) {
684 s->type = COMEDI_SUBD_DI;
685 s->subdev_flags = SDF_READABLE;
687 board(dev)->num_di_ports * ni_65xx_channels_per_port;
688 s->range_table = &range_digital;
690 s->insn_config = ni_65xx_dio_insn_config;
691 s->insn_bits = ni_65xx_dio_insn_bits;
692 s->private = ni_65xx_alloc_subdevice_private();
693 if (s->private == NULL)
695 sprivate(s)->base_port = 0;
697 s->type = COMEDI_SUBD_UNUSED;
700 s = dev->subdevices + 1;
701 if (board(dev)->num_do_ports) {
702 s->type = COMEDI_SUBD_DO;
703 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
705 board(dev)->num_do_ports * ni_65xx_channels_per_port;
706 s->range_table = &range_digital;
708 s->insn_bits = ni_65xx_dio_insn_bits;
709 s->private = ni_65xx_alloc_subdevice_private();
710 if (s->private == NULL)
712 sprivate(s)->base_port = board(dev)->num_di_ports;
714 s->type = COMEDI_SUBD_UNUSED;
717 s = dev->subdevices + 2;
718 if (board(dev)->num_dio_ports) {
719 s->type = COMEDI_SUBD_DIO;
720 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
722 board(dev)->num_dio_ports * ni_65xx_channels_per_port;
723 s->range_table = &range_digital;
725 s->insn_config = ni_65xx_dio_insn_config;
726 s->insn_bits = ni_65xx_dio_insn_bits;
727 s->private = ni_65xx_alloc_subdevice_private();
728 if (s->private == NULL)
730 sprivate(s)->base_port = 0;
731 for (i = 0; i < board(dev)->num_dio_ports; ++i) {
732 /* configure all ports for input */
734 private(dev)->mite->daq_io_addr +
738 s->type = COMEDI_SUBD_UNUSED;
741 s = dev->subdevices + 3;
742 dev->read_subdev = s;
743 s->type = COMEDI_SUBD_DI;
744 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
746 s->range_table = &range_unknown;
748 s->do_cmdtest = ni_65xx_intr_cmdtest;
749 s->do_cmd = ni_65xx_intr_cmd;
750 s->cancel = ni_65xx_intr_cancel;
751 s->insn_bits = ni_65xx_intr_insn_bits;
752 s->insn_config = ni_65xx_intr_insn_config;
754 for (i = 0; i < ni_65xx_total_num_ports(board(dev)); ++i) {
756 private(dev)->mite->daq_io_addr + Filter_Enable(i));
757 if (board(dev)->invert_outputs)
759 private(dev)->mite->daq_io_addr + Port_Data(i));
762 private(dev)->mite->daq_io_addr + Port_Data(i));
764 writeb(ClrEdge | ClrOverflow,
765 private(dev)->mite->daq_io_addr + Clear_Register);
767 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
769 /* Set filter interval to 0 (32bit reg) */
770 writeb(0x00000000, private(dev)->mite->daq_io_addr + Filter_Interval);
772 ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
776 printk(" irq not available");
784 static int ni_65xx_detach(struct comedi_device *dev)
786 if (private(dev) && private(dev)->mite
787 && private(dev)->mite->daq_io_addr) {
789 private(dev)->mite->daq_io_addr +
790 Master_Interrupt_Control);
794 free_irq(dev->irq, dev);
799 for (i = 0; i < dev->n_subdevices; ++i) {
800 if (dev->subdevices[i].private) {
801 kfree(dev->subdevices[i].private);
802 dev->subdevices[i].private = NULL;
805 if (private(dev)->mite) {
806 mite_unsetup(private(dev)->mite);
812 static int ni_65xx_find_device(struct comedi_device *dev, int bus, int slot)
814 struct mite_struct *mite;
817 for (mite = mite_devices; mite; mite = mite->next) {
821 if (bus != mite->pcidev->bus->number ||
822 slot != PCI_SLOT(mite->pcidev->devfn))
825 for (i = 0; i < n_ni_65xx_boards; i++) {
826 if (mite_device_id(mite) == ni_65xx_boards[i].dev_id) {
827 dev->board_ptr = ni_65xx_boards + i;
828 private(dev)->mite = mite;
833 printk("no device found\n");
838 COMEDI_PCI_INITCLEANUP(driver_ni_65xx, ni_65xx_pci_table);