drivers/staging/comedi/drivers/ni_65xx.c

   1 /*
   2     comedi/drivers/ni_6514.c
   3     driver for National Instruments PCI-6514
   4
   5     Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
   6     Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   7
   8     COMEDI - Linux Control and Measurement Device Interface
   9     Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
  10
  11     This program is free software; you can redistribute it and/or modify
  12     it under the terms of the GNU General Public License as published by
  13     the Free Software Foundation; either version 2 of the License, or
  14     (at your option) any later version.
  15
  16     This program is distributed in the hope that it will be useful,
  17     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19     GNU General Public License for more details.
  20
  21     You should have received a copy of the GNU General Public License
  22     along with this program; if not, write to the Free Software
  23     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24
  25 */
  26 /*
  27 Driver: ni_65xx
  28 Description: National Instruments 65xx static dio boards
  29 Author: Jon Grierson <jd@renko.co.uk>,
  30         Frank Mori Hess <fmhess@users.sourceforge.net>
  31 Status: testing
  32 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
  33   PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
  34   PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
  35   PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
  36 Updated: Wed Oct 18 08:59:11 EDT 2006
  37
  38 Based on the PCI-6527 driver by ds.
  39 The interrupt subdevice (subdevice 3) is probably broken for all boards
  40 except maybe the 6514.
  41
  42 */
  43
  44 /*
  45    Manuals (available from ftp://ftp.natinst.com/support/manuals)
  46
  47         370106b.pdf     6514 Register Level Programmer Manual
  48
  49  */
  50
  51 #define DEBUG 1
  52 #define DEBUG_FLAGS
  53
  54 #include <linux/pci.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/slab.h>
  57
  58 #include "../comedidev.h"
  59
  60 #include "comedi_fc.h"
  61 #include "mite.h"
  62
  63 #define NI6514_DIO_SIZE 4096
  64 #define NI6514_MITE_SIZE 4096
  65
  66 #define NI_65XX_MAX_NUM_PORTS 12
  67 static const unsigned ni_65xx_channels_per_port = 8;
  68 static const unsigned ni_65xx_port_offset = 0x10;
  69
  70 static inline unsigned Port_Data(unsigned port)
  71 {
  72         return 0x40 + port * ni_65xx_port_offset;
  73 }
  74
  75 static inline unsigned Port_Select(unsigned port)
  76 {
  77         return 0x41 + port * ni_65xx_port_offset;
  78 }
  79
  80 static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
  81 {
  82         return 0x42 + port * ni_65xx_port_offset;
  83 }
  84
  85 static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
  86 {
  87         return 0x43 + port * ni_65xx_port_offset;
  88 }
  89
  90 static inline unsigned Filter_Enable(unsigned port)
  91 {
  92         return 0x44 + port * ni_65xx_port_offset;
  93 }
  94
  95 #define ID_Register                             0x00
  96
  97 #define Clear_Register                          0x01
  98 #define ClrEdge                         0x08
  99 #define ClrOverflow                     0x04
 100
 101 #define Filter_Interval                 0x08
 102
 103 #define Change_Status                           0x02
 104 #define MasterInterruptStatus           0x04
 105 #define Overflow                        0x02
 106 #define EdgeStatus                      0x01
 107
 108 #define Master_Interrupt_Control                0x03
 109 #define FallingEdgeIntEnable            0x10
 110 #define RisingEdgeIntEnable             0x08
 111 #define MasterInterruptEnable           0x04
 112 #define OverflowIntEnable               0x02
 113 #define EdgeIntEnable                   0x01
 114
 115 struct ni_65xx_board {
 116         int dev_id;
 117         const char *name;
 118         unsigned num_dio_ports;
 119         unsigned num_di_ports;
 120         unsigned num_do_ports;
 121         unsigned invert_outputs:1;
 122 };
 123
 124 static const struct ni_65xx_board ni_65xx_boards[] = {
 125         {
 126          .dev_id = 0x7085,
 127          .name = "pci-6509",
 128          .num_dio_ports = 12,
 129          .invert_outputs = 0},
 130         {
 131          .dev_id = 0x1710,
 132          .name = "pxi-6509",
 133          .num_dio_ports = 12,
 134          .invert_outputs = 0},
 135         {
 136          .dev_id = 0x7124,
 137          .name = "pci-6510",
 138          .num_di_ports = 4},
 139         {
 140          .dev_id = 0x70c3,
 141          .name = "pci-6511",
 142          .num_di_ports = 8},
 143         {
 144          .dev_id = 0x70d3,
 145          .name = "pxi-6511",
 146          .num_di_ports = 8},
 147         {
 148          .dev_id = 0x70cc,
 149          .name = "pci-6512",
 150          .num_do_ports = 8},
 151         {
 152          .dev_id = 0x70d2,
 153          .name = "pxi-6512",
 154          .num_do_ports = 8},
 155         {
 156          .dev_id = 0x70c8,
 157          .name = "pci-6513",
 158          .num_do_ports = 8,
 159          .invert_outputs = 1},
 160         {
 161          .dev_id = 0x70d1,
 162          .name = "pxi-6513",
 163          .num_do_ports = 8,
 164          .invert_outputs = 1},
 165         {
 166          .dev_id = 0x7088,
 167          .name = "pci-6514",
 168          .num_di_ports = 4,
 169          .num_do_ports = 4,
 170          .invert_outputs = 1},
 171         {
 172          .dev_id = 0x70CD,
 173          .name = "pxi-6514",
 174          .num_di_ports = 4,
 175          .num_do_ports = 4,
 176          .invert_outputs = 1},
 177         {
 178          .dev_id = 0x7087,
 179          .name = "pci-6515",
 180          .num_di_ports = 4,
 181          .num_do_ports = 4,
 182          .invert_outputs = 1},
 183         {
 184          .dev_id = 0x70c9,
 185          .name = "pxi-6515",
 186          .num_di_ports = 4,
 187          .num_do_ports = 4,
 188          .invert_outputs = 1},
 189         {
 190          .dev_id = 0x7125,
 191          .name = "pci-6516",
 192          .num_do_ports = 4,
 193          .invert_outputs = 1},
 194         {
 195          .dev_id = 0x7126,
 196          .name = "pci-6517",
 197          .num_do_ports = 4,
 198          .invert_outputs = 1},
 199         {
 200          .dev_id = 0x7127,
 201          .name = "pci-6518",
 202          .num_di_ports = 2,
 203          .num_do_ports = 2,
 204          .invert_outputs = 1},
 205         {
 206          .dev_id = 0x7128,
 207          .name = "pci-6519",
 208          .num_di_ports = 2,
 209          .num_do_ports = 2,
 210          .invert_outputs = 1},
 211         {
 212          .dev_id = 0x71c5,
 213          .name = "pci-6520",
 214          .num_di_ports = 1,
 215          .num_do_ports = 1,
 216          },
 217         {
 218          .dev_id = 0x718b,
 219          .name = "pci-6521",
 220          .num_di_ports = 1,
 221          .num_do_ports = 1,
 222          },
 223         {
 224          .dev_id = 0x718c,
 225          .name = "pxi-6521",
 226          .num_di_ports = 1,
 227          .num_do_ports = 1,
 228          },
 229         {
 230          .dev_id = 0x70a9,
 231          .name = "pci-6528",
 232          .num_di_ports = 3,
 233          .num_do_ports = 3,
 234          },
 235         {
 236          .dev_id = 0x7086,
 237          .name = "pxi-6528",
 238          .num_di_ports = 3,
 239          .num_do_ports = 3,
 240          },
 241 };
 242
 243 #define n_ni_65xx_boards ARRAY_SIZE(ni_65xx_boards)
 244 static inline const struct ni_65xx_board *board(struct comedi_device *dev)
 245 {
 246         return dev->board_ptr;
 247 }
 248
 249 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
 250 {
 251         return channel / ni_65xx_channels_per_port;
 252 }
 253
 254 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
 255                                                *board)
 256 {
 257         return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
 258 }
 259
 260 static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table) = {
 261         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1710)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7085)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7086)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7087)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7088)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70a9)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c3)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c8)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c9)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70cc)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70CD)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70d1)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70d2)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70d3)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7124)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7125)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7126)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7127)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x7128)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x718b)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x718c)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71c5)},
 283         {0}
 284 };
 285
 286 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
 287
 288 struct ni_65xx_private {
 289         struct mite_struct *mite;
 290         unsigned int filter_interval;
 291         unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
 292         unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
 293         unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
 294 };
 295
 296 struct ni_65xx_subdevice_private {
 297         unsigned base_port;
 298 };
 299
 300 static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
 301                                                          *subdev)
 302 {
 303         return subdev->private;
 304 }
 305
 306 static struct ni_65xx_subdevice_private *ni_65xx_alloc_subdevice_private(void)
 307 {
 308         struct ni_65xx_subdevice_private *subdev_private =
 309             kzalloc(sizeof(struct ni_65xx_subdevice_private), GFP_KERNEL);
 310         if (subdev_private == NULL)
 311                 return NULL;
 312         return subdev_private;
 313 }
 314
 315 static int ni_65xx_config_filter(struct comedi_device *dev,
 316                                  struct comedi_subdevice *s,
 317                                  struct comedi_insn *insn, unsigned int *data)
 318 {
 319         struct ni_65xx_private *devpriv = dev->private;
 320         const unsigned chan = CR_CHAN(insn->chanspec);
 321         const unsigned port =
 322             sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
 323
 324         if (data[0] != INSN_CONFIG_FILTER)
 325                 return -EINVAL;
 326         if (data[1]) {
 327                 static const unsigned filter_resolution_ns = 200;
 328                 static const unsigned max_filter_interval = 0xfffff;
 329                 unsigned interval =
 330                     (data[1] +
 331                      (filter_resolution_ns / 2)) / filter_resolution_ns;
 332                 if (interval > max_filter_interval)
 333                         interval = max_filter_interval;
 334                 data[1] = interval * filter_resolution_ns;
 335
 336                 if (interval != devpriv->filter_interval) {
 337                         writeb(interval,
 338                                devpriv->mite->daq_io_addr +
 339                                Filter_Interval);
 340                         devpriv->filter_interval = interval;
 341                 }
 342
 343                 devpriv->filter_enable[port] |=
 344                     1 << (chan % ni_65xx_channels_per_port);
 345         } else {
 346                 devpriv->filter_enable[port] &=
 347                     ~(1 << (chan % ni_65xx_channels_per_port));
 348         }
 349
 350         writeb(devpriv->filter_enable[port],
 351                devpriv->mite->daq_io_addr + Filter_Enable(port));
 352
 353         return 2;
 354 }
 355
 356 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
 357                                    struct comedi_subdevice *s,
 358                                    struct comedi_insn *insn, unsigned int *data)
 359 {
 360         struct ni_65xx_private *devpriv = dev->private;
 361         unsigned port;
 362
 363         if (insn->n < 1)
 364                 return -EINVAL;
 365         port = sprivate(s)->base_port +
 366             ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
 367         switch (data[0]) {
 368         case INSN_CONFIG_FILTER:
 369                 return ni_65xx_config_filter(dev, s, insn, data);
 370                 break;
 371         case INSN_CONFIG_DIO_OUTPUT:
 372                 if (s->type != COMEDI_SUBD_DIO)
 373                         return -EINVAL;
 374                 devpriv->dio_direction[port] = COMEDI_OUTPUT;
 375                 writeb(0, devpriv->mite->daq_io_addr + Port_Select(port));
 376                 return 1;
 377                 break;
 378         case INSN_CONFIG_DIO_INPUT:
 379                 if (s->type != COMEDI_SUBD_DIO)
 380                         return -EINVAL;
 381                 devpriv->dio_direction[port] = COMEDI_INPUT;
 382                 writeb(1, devpriv->mite->daq_io_addr + Port_Select(port));
 383                 return 1;
 384                 break;
 385         case INSN_CONFIG_DIO_QUERY:
 386                 if (s->type != COMEDI_SUBD_DIO)
 387                         return -EINVAL;
 388                 data[1] = devpriv->dio_direction[port];
 389                 return insn->n;
 390                 break;
 391         default:
 392                 break;
 393         }
 394         return -EINVAL;
 395 }
 396
 397 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
 398                                  struct comedi_subdevice *s,
 399                                  struct comedi_insn *insn, unsigned int *data)
 400 {
 401         struct ni_65xx_private *devpriv = dev->private;
 402         unsigned base_bitfield_channel;
 403         const unsigned max_ports_per_bitfield = 5;
 404         unsigned read_bits = 0;
 405         unsigned j;
 406
 407         base_bitfield_channel = CR_CHAN(insn->chanspec);
 408         for (j = 0; j < max_ports_per_bitfield; ++j) {
 409                 const unsigned port_offset =
 410                         ni_65xx_port_by_channel(base_bitfield_channel) + j;
 411                 const unsigned port =
 412                         sprivate(s)->base_port + port_offset;
 413                 unsigned base_port_channel;
 414                 unsigned port_mask, port_data, port_read_bits;
 415                 int bitshift;
 416                 if (port >= ni_65xx_total_num_ports(board(dev)))
 417                         break;
 418                 base_port_channel = port_offset * ni_65xx_channels_per_port;
 419                 port_mask = data[0];
 420                 port_data = data[1];
 421                 bitshift = base_port_channel - base_bitfield_channel;
 422                 if (bitshift >= 32 || bitshift <= -32)
 423                         break;
 424                 if (bitshift > 0) {
 425                         port_mask >>= bitshift;
 426                         port_data >>= bitshift;
 427                 } else {
 428                         port_mask <<= -bitshift;
 429                         port_data <<= -bitshift;
 430                 }
 431                 port_mask &= 0xff;
 432                 port_data &= 0xff;
 433                 if (port_mask) {
 434                         unsigned bits;
 435                         devpriv->output_bits[port] &= ~port_mask;
 436                         devpriv->output_bits[port] |=
 437                             port_data & port_mask;
 438                         bits = devpriv->output_bits[port];
 439                         if (board(dev)->invert_outputs)
 440                                 bits = ~bits;
 441                         writeb(bits,
 442                                devpriv->mite->daq_io_addr +
 443                                Port_Data(port));
 444                 }
 445                 port_read_bits =
 446                     readb(devpriv->mite->daq_io_addr + Port_Data(port));
 447                 if (s->type == COMEDI_SUBD_DO && board(dev)->invert_outputs) {
 448                         /* Outputs inverted, so invert value read back from
 449                          * DO subdevice.  (Does not apply to boards with DIO
 450                          * subdevice.) */
 451                         port_read_bits ^= 0xFF;
 452                 }
 453                 if (bitshift > 0)
 454                         port_read_bits <<= bitshift;
 455                 else
 456                         port_read_bits >>= -bitshift;
 457
 458                 read_bits |= port_read_bits;
 459         }
 460         data[1] = read_bits;
 461         return insn->n;
 462 }
 463
 464 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
 465 {
 466         struct comedi_device *dev = d;
 467         struct ni_65xx_private *devpriv = dev->private;
 468         struct comedi_subdevice *s = &dev->subdevices[2];
 469         unsigned int status;
 470
 471         status = readb(devpriv->mite->daq_io_addr + Change_Status);
 472         if ((status & MasterInterruptStatus) == 0)
 473                 return IRQ_NONE;
 474         if ((status & EdgeStatus) == 0)
 475                 return IRQ_NONE;
 476
 477         writeb(ClrEdge | ClrOverflow,
 478                devpriv->mite->daq_io_addr + Clear_Register);
 479
 480         comedi_buf_put(s->async, 0);
 481         s->async->events |= COMEDI_CB_EOS;
 482         comedi_event(dev, s);
 483         return IRQ_HANDLED;
 484 }
 485
 486 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
 487                                 struct comedi_subdevice *s,
 488                                 struct comedi_cmd *cmd)
 489 {
 490         int err = 0;
 491
 492         /* Step 1 : check if triggers are trivially valid */
 493
 494         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
 495         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
 496         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
 497         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 498         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
 499
 500         if (err)
 501                 return 1;
 502
 503         /* Step 2a : make sure trigger sources are unique */
 504         /* Step 2b : and mutually compatible */
 505
 506         if (err)
 507                 return 2;
 508
 509         /* Step 3: check if arguments are trivially valid */
 510
 511         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
 512         err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
 513         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
 514         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
 515         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
 516
 517         if (err)
 518                 return 3;
 519
 520         /* step 4: fix up any arguments */
 521
 522         if (err)
 523                 return 4;
 524
 525         return 0;
 526 }
 527
 528 static int ni_65xx_intr_cmd(struct comedi_device *dev,
 529                             struct comedi_subdevice *s)
 530 {
 531         struct ni_65xx_private *devpriv = dev->private;
 532         /* struct comedi_cmd *cmd = &s->async->cmd; */
 533
 534         writeb(ClrEdge | ClrOverflow,
 535                devpriv->mite->daq_io_addr + Clear_Register);
 536         writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
 537                MasterInterruptEnable | EdgeIntEnable,
 538                devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 539
 540         return 0;
 541 }
 542
 543 static int ni_65xx_intr_cancel(struct comedi_device *dev,
 544                                struct comedi_subdevice *s)
 545 {
 546         struct ni_65xx_private *devpriv = dev->private;
 547
 548         writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 549
 550         return 0;
 551 }
 552
 553 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
 554                                   struct comedi_subdevice *s,
 555                                   struct comedi_insn *insn, unsigned int *data)
 556 {
 557         data[1] = 0;
 558         return insn->n;
 559 }
 560
 561 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
 562                                     struct comedi_subdevice *s,
 563                                     struct comedi_insn *insn,
 564                                     unsigned int *data)
 565 {
 566         struct ni_65xx_private *devpriv = dev->private;
 567
 568         if (insn->n < 1)
 569                 return -EINVAL;
 570         if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
 571                 return -EINVAL;
 572
 573         writeb(data[1],
 574                devpriv->mite->daq_io_addr +
 575                Rising_Edge_Detection_Enable(0));
 576         writeb(data[1] >> 8,
 577                devpriv->mite->daq_io_addr +
 578                Rising_Edge_Detection_Enable(0x10));
 579         writeb(data[1] >> 16,
 580                devpriv->mite->daq_io_addr +
 581                Rising_Edge_Detection_Enable(0x20));
 582         writeb(data[1] >> 24,
 583                devpriv->mite->daq_io_addr +
 584                Rising_Edge_Detection_Enable(0x30));
 585
 586         writeb(data[2],
 587                devpriv->mite->daq_io_addr +
 588                Falling_Edge_Detection_Enable(0));
 589         writeb(data[2] >> 8,
 590                devpriv->mite->daq_io_addr +
 591                Falling_Edge_Detection_Enable(0x10));
 592         writeb(data[2] >> 16,
 593                devpriv->mite->daq_io_addr +
 594                Falling_Edge_Detection_Enable(0x20));
 595         writeb(data[2] >> 24,
 596                devpriv->mite->daq_io_addr +
 597                Falling_Edge_Detection_Enable(0x30));
 598
 599         return 2;
 600 }
 601
 602 static const struct ni_65xx_board *
 603 ni_65xx_find_boardinfo(struct pci_dev *pcidev)
 604 {
 605         unsigned int dev_id = pcidev->device;
 606         unsigned int n;
 607
 608         for (n = 0; n < ARRAY_SIZE(ni_65xx_boards); n++) {
 609                 const struct ni_65xx_board *board = &ni_65xx_boards[n];
 610                 if (board->dev_id == dev_id)
 611                         return board;
 612         }
 613         return NULL;
 614 }
 615
 616 static int ni_65xx_auto_attach(struct comedi_device *dev,
 617                                          unsigned long context_unused)
 618 {
 619         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 620         struct ni_65xx_private *devpriv;
 621         struct comedi_subdevice *s;
 622         unsigned i;
 623         int ret;
 624
 625         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 626         if (!devpriv)
 627                 return -ENOMEM;
 628         dev->private = devpriv;
 629
 630         dev->board_ptr = ni_65xx_find_boardinfo(pcidev);
 631         if (!dev->board_ptr)
 632                 return -ENODEV;
 633
 634         devpriv->mite = mite_alloc(pcidev);
 635         if (!devpriv->mite)
 636                 return -ENOMEM;
 637
 638         ret = mite_setup(devpriv->mite);
 639         if (ret < 0) {
 640                 dev_warn(dev->class_dev, "error setting up mite\n");
 641                 return ret;
 642         }
 643
 644         dev->board_name = board(dev)->name;
 645         dev->irq = mite_irq(devpriv->mite);
 646         dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
 647                readb(devpriv->mite->daq_io_addr + ID_Register));
 648
 649         ret = comedi_alloc_subdevices(dev, 4);
 650         if (ret)
 651                 return ret;
 652
 653         s = &dev->subdevices[0];
 654         if (board(dev)->num_di_ports) {
 655                 s->type = COMEDI_SUBD_DI;
 656                 s->subdev_flags = SDF_READABLE;
 657                 s->n_chan =
 658                     board(dev)->num_di_ports * ni_65xx_channels_per_port;
 659                 s->range_table = &range_digital;
 660                 s->maxdata = 1;
 661                 s->insn_config = ni_65xx_dio_insn_config;
 662                 s->insn_bits = ni_65xx_dio_insn_bits;
 663                 s->private = ni_65xx_alloc_subdevice_private();
 664                 if (s->private == NULL)
 665                         return -ENOMEM;
 666                 sprivate(s)->base_port = 0;
 667         } else {
 668                 s->type = COMEDI_SUBD_UNUSED;
 669         }
 670
 671         s = &dev->subdevices[1];
 672         if (board(dev)->num_do_ports) {
 673                 s->type = COMEDI_SUBD_DO;
 674                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
 675                 s->n_chan =
 676                     board(dev)->num_do_ports * ni_65xx_channels_per_port;
 677                 s->range_table = &range_digital;
 678                 s->maxdata = 1;
 679                 s->insn_bits = ni_65xx_dio_insn_bits;
 680                 s->private = ni_65xx_alloc_subdevice_private();
 681                 if (s->private == NULL)
 682                         return -ENOMEM;
 683                 sprivate(s)->base_port = board(dev)->num_di_ports;
 684         } else {
 685                 s->type = COMEDI_SUBD_UNUSED;
 686         }
 687
 688         s = &dev->subdevices[2];
 689         if (board(dev)->num_dio_ports) {
 690                 s->type = COMEDI_SUBD_DIO;
 691                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
 692                 s->n_chan =
 693                     board(dev)->num_dio_ports * ni_65xx_channels_per_port;
 694                 s->range_table = &range_digital;
 695                 s->maxdata = 1;
 696                 s->insn_config = ni_65xx_dio_insn_config;
 697                 s->insn_bits = ni_65xx_dio_insn_bits;
 698                 s->private = ni_65xx_alloc_subdevice_private();
 699                 if (s->private == NULL)
 700                         return -ENOMEM;
 701                 sprivate(s)->base_port = 0;
 702                 for (i = 0; i < board(dev)->num_dio_ports; ++i) {
 703                         /*  configure all ports for input */
 704                         writeb(0x1,
 705                                devpriv->mite->daq_io_addr +
 706                                Port_Select(i));
 707                 }
 708         } else {
 709                 s->type = COMEDI_SUBD_UNUSED;
 710         }
 711
 712         s = &dev->subdevices[3];
 713         dev->read_subdev = s;
 714         s->type = COMEDI_SUBD_DI;
 715         s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
 716         s->n_chan = 1;
 717         s->range_table = &range_unknown;
 718         s->maxdata = 1;
 719         s->do_cmdtest = ni_65xx_intr_cmdtest;
 720         s->do_cmd = ni_65xx_intr_cmd;
 721         s->cancel = ni_65xx_intr_cancel;
 722         s->insn_bits = ni_65xx_intr_insn_bits;
 723         s->insn_config = ni_65xx_intr_insn_config;
 724
 725         for (i = 0; i < ni_65xx_total_num_ports(board(dev)); ++i) {
 726                 writeb(0x00,
 727                        devpriv->mite->daq_io_addr + Filter_Enable(i));
 728                 if (board(dev)->invert_outputs)
 729                         writeb(0x01,
 730                                devpriv->mite->daq_io_addr + Port_Data(i));
 731                 else
 732                         writeb(0x00,
 733                                devpriv->mite->daq_io_addr + Port_Data(i));
 734         }
 735         writeb(ClrEdge | ClrOverflow,
 736                devpriv->mite->daq_io_addr + Clear_Register);
 737         writeb(0x00,
 738                devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 739
 740         /* Set filter interval to 0  (32bit reg) */
 741         writeb(0x00000000, devpriv->mite->daq_io_addr + Filter_Interval);
 742
 743         ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
 744                           "ni_65xx", dev);
 745         if (ret < 0) {
 746                 dev->irq = 0;
 747                 dev_warn(dev->class_dev, "irq not available\n");
 748         }
 749
 750         return 0;
 751 }
 752
 753 static void ni_65xx_detach(struct comedi_device *dev)
 754 {
 755         struct ni_65xx_private *devpriv = dev->private;
 756
 757         if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr) {
 758                 writeb(0x00,
 759                        devpriv->mite->daq_io_addr +
 760                        Master_Interrupt_Control);
 761         }
 762         if (dev->irq)
 763                 free_irq(dev->irq, dev);
 764         if (devpriv) {
 765                 struct comedi_subdevice *s;
 766                 unsigned i;
 767
 768                 for (i = 0; i < dev->n_subdevices; ++i) {
 769                         s = &dev->subdevices[i];
 770                         kfree(s->private);
 771                         s->private = NULL;
 772                 }
 773                 if (devpriv->mite) {
 774                         mite_unsetup(devpriv->mite);
 775                         mite_free(devpriv->mite);
 776                 }
 777         }
 778 }
 779
 780 static struct comedi_driver ni_65xx_driver = {
 781         .driver_name = "ni_65xx",
 782         .module = THIS_MODULE,
 783         .auto_attach = ni_65xx_auto_attach,
 784         .detach = ni_65xx_detach,
 785 };
 786
 787 static int ni_65xx_pci_probe(struct pci_dev *dev,
 788                                        const struct pci_device_id *ent)
 789 {
 790         return comedi_pci_auto_config(dev, &ni_65xx_driver);
 791 }
 792
 793 static struct pci_driver ni_65xx_pci_driver = {
 794         .name = "ni_65xx",
 795         .id_table = ni_65xx_pci_table,
 796         .probe = ni_65xx_pci_probe,
 797         .remove         = comedi_pci_auto_unconfig,
 798 };
 799 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
 800
 801 MODULE_AUTHOR("Comedi http://www.comedi.org");
 802 MODULE_DESCRIPTION("Comedi low-level driver");
 803 MODULE_LICENSE("GPL");