drivers/staging/comedi/drivers/ni_660x.c

   1 /*
   2   comedi/drivers/ni_660x.c
   3   Hardware driver for NI 660x devices
   4
   5   This program is free software; you can redistribute it and/or modify
   6   it under the terms of the GNU General Public License as published by
   7   the Free Software Foundation; either version 2 of the License, or
   8   (at your option) any later version.
   9
  10   This program is distributed in the hope that it will be useful,
  11   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13   GNU General Public License for more details.
  14 */
  15
  16 /*
  17  * Driver: ni_660x
  18  * Description: National Instruments 660x counter/timer boards
  19  * Devices: [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
  20  *   PXI-6608, PXI-6624
  21  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  22  *   Herman.Bruyninckx@mech.kuleuven.ac.be,
  23  *   Wim.Meeussen@mech.kuleuven.ac.be,
  24  *   Klaas.Gadeyne@mech.kuleuven.ac.be,
  25  *   Frank Mori Hess <fmhess@users.sourceforge.net>
  26  * Updated: Fri, 15 Mar 2013 10:47:56 +0000
  27  * Status: experimental
  28  *
  29  * Encoders work.  PulseGeneration (both single pulse and pulse train)
  30  * works.  Buffered commands work for input but not output.
  31  *
  32  * References:
  33  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  34  * DAQ 6601/6602 User Manual (NI 322137B-01)
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/pci.h>
  39 #include <linux/interrupt.h>
  40
  41 #include "../comedidev.h"
  42
  43 #include "mite.h"
  44 #include "ni_tio.h"
  45
  46 enum ni_660x_constants {
  47         min_counter_pfi_chan = 8,
  48         max_dio_pfi_chan = 31,
  49         counters_per_chip = 4
  50 };
  51
  52 #define NUM_PFI_CHANNELS 40
  53 /* really there are only up to 3 dma channels, but the register layout allows
  54 for 4 */
  55 #define MAX_DMA_CHANNEL 4
  56
  57 /* See Register-Level Programmer Manual page 3.1 */
  58 enum NI_660x_Register {
  59         G0InterruptAcknowledge,
  60         G0StatusRegister,
  61         G1InterruptAcknowledge,
  62         G1StatusRegister,
  63         G01StatusRegister,
  64         G0CommandRegister,
  65         STCDIOParallelInput,
  66         G1CommandRegister,
  67         G0HWSaveRegister,
  68         G1HWSaveRegister,
  69         STCDIOOutput,
  70         STCDIOControl,
  71         G0SWSaveRegister,
  72         G1SWSaveRegister,
  73         G0ModeRegister,
  74         G01JointStatus1Register,
  75         G1ModeRegister,
  76         STCDIOSerialInput,
  77         G0LoadARegister,
  78         G01JointStatus2Register,
  79         G0LoadBRegister,
  80         G1LoadARegister,
  81         G1LoadBRegister,
  82         G0InputSelectRegister,
  83         G1InputSelectRegister,
  84         G0AutoincrementRegister,
  85         G1AutoincrementRegister,
  86         G01JointResetRegister,
  87         G0InterruptEnable,
  88         G1InterruptEnable,
  89         G0CountingModeRegister,
  90         G1CountingModeRegister,
  91         G0SecondGateRegister,
  92         G1SecondGateRegister,
  93         G0DMAConfigRegister,
  94         G0DMAStatusRegister,
  95         G1DMAConfigRegister,
  96         G1DMAStatusRegister,
  97         G2InterruptAcknowledge,
  98         G2StatusRegister,
  99         G3InterruptAcknowledge,
 100         G3StatusRegister,
 101         G23StatusRegister,
 102         G2CommandRegister,
 103         G3CommandRegister,
 104         G2HWSaveRegister,
 105         G3HWSaveRegister,
 106         G2SWSaveRegister,
 107         G3SWSaveRegister,
 108         G2ModeRegister,
 109         G23JointStatus1Register,
 110         G3ModeRegister,
 111         G2LoadARegister,
 112         G23JointStatus2Register,
 113         G2LoadBRegister,
 114         G3LoadARegister,
 115         G3LoadBRegister,
 116         G2InputSelectRegister,
 117         G3InputSelectRegister,
 118         G2AutoincrementRegister,
 119         G3AutoincrementRegister,
 120         G23JointResetRegister,
 121         G2InterruptEnable,
 122         G3InterruptEnable,
 123         G2CountingModeRegister,
 124         G3CountingModeRegister,
 125         G3SecondGateRegister,
 126         G2SecondGateRegister,
 127         G2DMAConfigRegister,
 128         G2DMAStatusRegister,
 129         G3DMAConfigRegister,
 130         G3DMAStatusRegister,
 131         DIO32Input,
 132         DIO32Output,
 133         ClockConfigRegister,
 134         GlobalInterruptStatusRegister,
 135         DMAConfigRegister,
 136         GlobalInterruptConfigRegister,
 137         IOConfigReg0_1,
 138         IOConfigReg2_3,
 139         IOConfigReg4_5,
 140         IOConfigReg6_7,
 141         IOConfigReg8_9,
 142         IOConfigReg10_11,
 143         IOConfigReg12_13,
 144         IOConfigReg14_15,
 145         IOConfigReg16_17,
 146         IOConfigReg18_19,
 147         IOConfigReg20_21,
 148         IOConfigReg22_23,
 149         IOConfigReg24_25,
 150         IOConfigReg26_27,
 151         IOConfigReg28_29,
 152         IOConfigReg30_31,
 153         IOConfigReg32_33,
 154         IOConfigReg34_35,
 155         IOConfigReg36_37,
 156         IOConfigReg38_39,
 157         NumRegisters,
 158 };
 159
 160 static inline unsigned IOConfigReg(unsigned pfi_channel)
 161 {
 162         unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
 163         BUG_ON(reg > IOConfigReg38_39);
 164         return reg;
 165 }
 166
 167 enum ni_660x_register_width {
 168         DATA_1B,
 169         DATA_2B,
 170         DATA_4B
 171 };
 172
 173 enum ni_660x_register_direction {
 174         NI_660x_READ,
 175         NI_660x_WRITE,
 176         NI_660x_READ_WRITE
 177 };
 178
 179 enum ni_660x_pfi_output_select {
 180         pfi_output_select_high_Z = 0,
 181         pfi_output_select_counter = 1,
 182         pfi_output_select_do = 2,
 183         num_pfi_output_selects
 184 };
 185
 186 enum ni_660x_subdevices {
 187         NI_660X_DIO_SUBDEV = 1,
 188         NI_660X_GPCT_SUBDEV_0 = 2
 189 };
 190 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
 191 {
 192         return NI_660X_GPCT_SUBDEV_0 + index;
 193 }
 194
 195 struct NI_660xRegisterData {
 196
 197         const char *name;       /*  Register Name */
 198         int offset;             /*  Offset from base address from GPCT chip */
 199         enum ni_660x_register_direction direction;
 200         enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
 201 };
 202
 203 static const struct NI_660xRegisterData registerData[NumRegisters] = {
 204         {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
 205         {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
 206         {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
 207         {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
 208         {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
 209         {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
 210         {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
 211         {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
 212         {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
 213         {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
 214         {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
 215         {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
 216         {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
 217         {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
 218         {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
 219         {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
 220         {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
 221         {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
 222         {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
 223         {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
 224         {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
 225         {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
 226         {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
 227         {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
 228         {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
 229         {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
 230         {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
 231         {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
 232         {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
 233         {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
 234         {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
 235         {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
 236         {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
 237         {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
 238         {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
 239         {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
 240         {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
 241         {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
 242         {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
 243         {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
 244         {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
 245         {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
 246         {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
 247         {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
 248         {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
 249         {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
 250         {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
 251         {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
 252         {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
 253         {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
 254         {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
 255         {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
 256         {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
 257         {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
 258         {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
 259         {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
 260         {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
 261         {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
 262         {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
 263         {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
 264         {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
 265         {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
 266         {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
 267         {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
 268         {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
 269         {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
 270         {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
 271         {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
 272         {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
 273         {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
 274         {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
 275         {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
 276         {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
 277         {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
 278         {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
 279         {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
 280         {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
 281         {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
 282         {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
 283         {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
 284         {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
 285         {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
 286         {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
 287         {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
 288         {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
 289         {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
 290         {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
 291         {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
 292         {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
 293         {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
 294         {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
 295         {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
 296         {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
 297         {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
 298         {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
 299         {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
 300         {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
 301         {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
 302 };
 303
 304 /* kind of ENABLE for the second counter */
 305 enum clock_config_register_bits {
 306         CounterSwap = 0x1 << 21
 307 };
 308
 309 /* ioconfigreg */
 310 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
 311 {
 312         if (pfi_channel % 2)
 313                 return 0;
 314         else
 315                 return 8;
 316 }
 317
 318 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
 319 {
 320         return 0x3 << ioconfig_bitshift(pfi_channel);
 321 }
 322
 323 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
 324                                               unsigned output_select)
 325 {
 326         return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
 327 }
 328
 329 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
 330 {
 331         return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
 332 }
 333
 334 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
 335                                              unsigned input_select)
 336 {
 337         return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
 338 }
 339
 340 /* dma configuration register bits */
 341 static inline unsigned dma_select_mask(unsigned dma_channel)
 342 {
 343         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 344         return 0x1f << (8 * dma_channel);
 345 }
 346
 347 enum dma_selection {
 348         dma_selection_none = 0x1f,
 349 };
 350 static inline unsigned dma_selection_counter(unsigned counter_index)
 351 {
 352         BUG_ON(counter_index >= counters_per_chip);
 353         return counter_index;
 354 }
 355
 356 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
 357 {
 358         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 359         return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
 360 }
 361
 362 static inline unsigned dma_reset_bit(unsigned dma_channel)
 363 {
 364         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 365         return 0x80 << (8 * dma_channel);
 366 }
 367
 368 enum global_interrupt_status_register_bits {
 369         Counter_0_Int_Bit = 0x100,
 370         Counter_1_Int_Bit = 0x200,
 371         Counter_2_Int_Bit = 0x400,
 372         Counter_3_Int_Bit = 0x800,
 373         Cascade_Int_Bit = 0x20000000,
 374         Global_Int_Bit = 0x80000000
 375 };
 376
 377 enum global_interrupt_config_register_bits {
 378         Cascade_Int_Enable_Bit = 0x20000000,
 379         Global_Int_Polarity_Bit = 0x40000000,
 380         Global_Int_Enable_Bit = 0x80000000
 381 };
 382
 383 /* Offset of the GPCT chips from the base-address of the card */
 384 /* First chip is at base-address + 0x00, etc. */
 385 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
 386
 387 enum ni_660x_boardid {
 388         BOARD_PCI6601,
 389         BOARD_PCI6602,
 390         BOARD_PXI6602,
 391         BOARD_PXI6608,
 392         BOARD_PXI6624
 393 };
 394
 395 struct ni_660x_board {
 396         const char *name;
 397         unsigned n_chips;       /* total number of TIO chips */
 398 };
 399
 400 static const struct ni_660x_board ni_660x_boards[] = {
 401         [BOARD_PCI6601] = {
 402                 .name           = "PCI-6601",
 403                 .n_chips        = 1,
 404         },
 405         [BOARD_PCI6602] = {
 406                 .name           = "PCI-6602",
 407                 .n_chips        = 2,
 408         },
 409         [BOARD_PXI6602] = {
 410                 .name           = "PXI-6602",
 411                 .n_chips        = 2,
 412         },
 413         [BOARD_PXI6608] = {
 414                 .name           = "PXI-6608",
 415                 .n_chips        = 2,
 416         },
 417         [BOARD_PXI6624] = {
 418                 .name           = "PXI-6624",
 419                 .n_chips        = 2,
 420         },
 421 };
 422
 423 #define NI_660X_MAX_NUM_CHIPS 2
 424 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
 425
 426 struct ni_660x_private {
 427         struct mite_struct *mite;
 428         struct ni_gpct_device *counter_dev;
 429         uint64_t pfi_direction_bits;
 430         struct mite_dma_descriptor_ring
 431         *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
 432         spinlock_t mite_channel_lock;
 433         /* interrupt_lock prevents races between interrupt and comedi_poll */
 434         spinlock_t interrupt_lock;
 435         unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
 436         spinlock_t soft_reg_copy_lock;
 437         unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
 438 };
 439
 440 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
 441 {
 442         const struct ni_660x_board *board = comedi_board(dev);
 443
 444         return board->n_chips * counters_per_chip;
 445 }
 446
 447 static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
 448 {
 449         enum NI_660x_Register ni_660x_register;
 450         switch (reg) {
 451         case NITIO_G0_Autoincrement_Reg:
 452                 ni_660x_register = G0AutoincrementRegister;
 453                 break;
 454         case NITIO_G1_Autoincrement_Reg:
 455                 ni_660x_register = G1AutoincrementRegister;
 456                 break;
 457         case NITIO_G2_Autoincrement_Reg:
 458                 ni_660x_register = G2AutoincrementRegister;
 459                 break;
 460         case NITIO_G3_Autoincrement_Reg:
 461                 ni_660x_register = G3AutoincrementRegister;
 462                 break;
 463         case NITIO_G0_Command_Reg:
 464                 ni_660x_register = G0CommandRegister;
 465                 break;
 466         case NITIO_G1_Command_Reg:
 467                 ni_660x_register = G1CommandRegister;
 468                 break;
 469         case NITIO_G2_Command_Reg:
 470                 ni_660x_register = G2CommandRegister;
 471                 break;
 472         case NITIO_G3_Command_Reg:
 473                 ni_660x_register = G3CommandRegister;
 474                 break;
 475         case NITIO_G0_HW_Save_Reg:
 476                 ni_660x_register = G0HWSaveRegister;
 477                 break;
 478         case NITIO_G1_HW_Save_Reg:
 479                 ni_660x_register = G1HWSaveRegister;
 480                 break;
 481         case NITIO_G2_HW_Save_Reg:
 482                 ni_660x_register = G2HWSaveRegister;
 483                 break;
 484         case NITIO_G3_HW_Save_Reg:
 485                 ni_660x_register = G3HWSaveRegister;
 486                 break;
 487         case NITIO_G0_SW_Save_Reg:
 488                 ni_660x_register = G0SWSaveRegister;
 489                 break;
 490         case NITIO_G1_SW_Save_Reg:
 491                 ni_660x_register = G1SWSaveRegister;
 492                 break;
 493         case NITIO_G2_SW_Save_Reg:
 494                 ni_660x_register = G2SWSaveRegister;
 495                 break;
 496         case NITIO_G3_SW_Save_Reg:
 497                 ni_660x_register = G3SWSaveRegister;
 498                 break;
 499         case NITIO_G0_Mode_Reg:
 500                 ni_660x_register = G0ModeRegister;
 501                 break;
 502         case NITIO_G1_Mode_Reg:
 503                 ni_660x_register = G1ModeRegister;
 504                 break;
 505         case NITIO_G2_Mode_Reg:
 506                 ni_660x_register = G2ModeRegister;
 507                 break;
 508         case NITIO_G3_Mode_Reg:
 509                 ni_660x_register = G3ModeRegister;
 510                 break;
 511         case NITIO_G0_LoadA_Reg:
 512                 ni_660x_register = G0LoadARegister;
 513                 break;
 514         case NITIO_G1_LoadA_Reg:
 515                 ni_660x_register = G1LoadARegister;
 516                 break;
 517         case NITIO_G2_LoadA_Reg:
 518                 ni_660x_register = G2LoadARegister;
 519                 break;
 520         case NITIO_G3_LoadA_Reg:
 521                 ni_660x_register = G3LoadARegister;
 522                 break;
 523         case NITIO_G0_LoadB_Reg:
 524                 ni_660x_register = G0LoadBRegister;
 525                 break;
 526         case NITIO_G1_LoadB_Reg:
 527                 ni_660x_register = G1LoadBRegister;
 528                 break;
 529         case NITIO_G2_LoadB_Reg:
 530                 ni_660x_register = G2LoadBRegister;
 531                 break;
 532         case NITIO_G3_LoadB_Reg:
 533                 ni_660x_register = G3LoadBRegister;
 534                 break;
 535         case NITIO_G0_Input_Select_Reg:
 536                 ni_660x_register = G0InputSelectRegister;
 537                 break;
 538         case NITIO_G1_Input_Select_Reg:
 539                 ni_660x_register = G1InputSelectRegister;
 540                 break;
 541         case NITIO_G2_Input_Select_Reg:
 542                 ni_660x_register = G2InputSelectRegister;
 543                 break;
 544         case NITIO_G3_Input_Select_Reg:
 545                 ni_660x_register = G3InputSelectRegister;
 546                 break;
 547         case NITIO_G01_Status_Reg:
 548                 ni_660x_register = G01StatusRegister;
 549                 break;
 550         case NITIO_G23_Status_Reg:
 551                 ni_660x_register = G23StatusRegister;
 552                 break;
 553         case NITIO_G01_Joint_Reset_Reg:
 554                 ni_660x_register = G01JointResetRegister;
 555                 break;
 556         case NITIO_G23_Joint_Reset_Reg:
 557                 ni_660x_register = G23JointResetRegister;
 558                 break;
 559         case NITIO_G01_Joint_Status1_Reg:
 560                 ni_660x_register = G01JointStatus1Register;
 561                 break;
 562         case NITIO_G23_Joint_Status1_Reg:
 563                 ni_660x_register = G23JointStatus1Register;
 564                 break;
 565         case NITIO_G01_Joint_Status2_Reg:
 566                 ni_660x_register = G01JointStatus2Register;
 567                 break;
 568         case NITIO_G23_Joint_Status2_Reg:
 569                 ni_660x_register = G23JointStatus2Register;
 570                 break;
 571         case NITIO_G0_Counting_Mode_Reg:
 572                 ni_660x_register = G0CountingModeRegister;
 573                 break;
 574         case NITIO_G1_Counting_Mode_Reg:
 575                 ni_660x_register = G1CountingModeRegister;
 576                 break;
 577         case NITIO_G2_Counting_Mode_Reg:
 578                 ni_660x_register = G2CountingModeRegister;
 579                 break;
 580         case NITIO_G3_Counting_Mode_Reg:
 581                 ni_660x_register = G3CountingModeRegister;
 582                 break;
 583         case NITIO_G0_Second_Gate_Reg:
 584                 ni_660x_register = G0SecondGateRegister;
 585                 break;
 586         case NITIO_G1_Second_Gate_Reg:
 587                 ni_660x_register = G1SecondGateRegister;
 588                 break;
 589         case NITIO_G2_Second_Gate_Reg:
 590                 ni_660x_register = G2SecondGateRegister;
 591                 break;
 592         case NITIO_G3_Second_Gate_Reg:
 593                 ni_660x_register = G3SecondGateRegister;
 594                 break;
 595         case NITIO_G0_DMA_Config_Reg:
 596                 ni_660x_register = G0DMAConfigRegister;
 597                 break;
 598         case NITIO_G0_DMA_Status_Reg:
 599                 ni_660x_register = G0DMAStatusRegister;
 600                 break;
 601         case NITIO_G1_DMA_Config_Reg:
 602                 ni_660x_register = G1DMAConfigRegister;
 603                 break;
 604         case NITIO_G1_DMA_Status_Reg:
 605                 ni_660x_register = G1DMAStatusRegister;
 606                 break;
 607         case NITIO_G2_DMA_Config_Reg:
 608                 ni_660x_register = G2DMAConfigRegister;
 609                 break;
 610         case NITIO_G2_DMA_Status_Reg:
 611                 ni_660x_register = G2DMAStatusRegister;
 612                 break;
 613         case NITIO_G3_DMA_Config_Reg:
 614                 ni_660x_register = G3DMAConfigRegister;
 615                 break;
 616         case NITIO_G3_DMA_Status_Reg:
 617                 ni_660x_register = G3DMAStatusRegister;
 618                 break;
 619         case NITIO_G0_Interrupt_Acknowledge_Reg:
 620                 ni_660x_register = G0InterruptAcknowledge;
 621                 break;
 622         case NITIO_G1_Interrupt_Acknowledge_Reg:
 623                 ni_660x_register = G1InterruptAcknowledge;
 624                 break;
 625         case NITIO_G2_Interrupt_Acknowledge_Reg:
 626                 ni_660x_register = G2InterruptAcknowledge;
 627                 break;
 628         case NITIO_G3_Interrupt_Acknowledge_Reg:
 629                 ni_660x_register = G3InterruptAcknowledge;
 630                 break;
 631         case NITIO_G0_Status_Reg:
 632                 ni_660x_register = G0StatusRegister;
 633                 break;
 634         case NITIO_G1_Status_Reg:
 635                 ni_660x_register = G1StatusRegister;
 636                 break;
 637         case NITIO_G2_Status_Reg:
 638                 ni_660x_register = G2StatusRegister;
 639                 break;
 640         case NITIO_G3_Status_Reg:
 641                 ni_660x_register = G3StatusRegister;
 642                 break;
 643         case NITIO_G0_Interrupt_Enable_Reg:
 644                 ni_660x_register = G0InterruptEnable;
 645                 break;
 646         case NITIO_G1_Interrupt_Enable_Reg:
 647                 ni_660x_register = G1InterruptEnable;
 648                 break;
 649         case NITIO_G2_Interrupt_Enable_Reg:
 650                 ni_660x_register = G2InterruptEnable;
 651                 break;
 652         case NITIO_G3_Interrupt_Enable_Reg:
 653                 ni_660x_register = G3InterruptEnable;
 654                 break;
 655         default:
 656                 BUG();
 657                 return 0;
 658                 break;
 659         }
 660         return ni_660x_register;
 661 }
 662
 663 static inline void ni_660x_write_register(struct comedi_device *dev,
 664                                           unsigned chip_index, unsigned bits,
 665                                           enum NI_660x_Register reg)
 666 {
 667         struct ni_660x_private *devpriv = dev->private;
 668         void __iomem *write_address =
 669             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 670             registerData[reg].offset;
 671
 672         switch (registerData[reg].size) {
 673         case DATA_2B:
 674                 writew(bits, write_address);
 675                 break;
 676         case DATA_4B:
 677                 writel(bits, write_address);
 678                 break;
 679         default:
 680                 BUG();
 681                 break;
 682         }
 683 }
 684
 685 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
 686                                              unsigned chip_index,
 687                                              enum NI_660x_Register reg)
 688 {
 689         struct ni_660x_private *devpriv = dev->private;
 690         void __iomem *read_address =
 691             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 692             registerData[reg].offset;
 693
 694         switch (registerData[reg].size) {
 695         case DATA_2B:
 696                 return readw(read_address);
 697                 break;
 698         case DATA_4B:
 699                 return readl(read_address);
 700                 break;
 701         default:
 702                 BUG();
 703                 break;
 704         }
 705         return 0;
 706 }
 707
 708 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
 709                                    enum ni_gpct_register reg)
 710 {
 711         struct comedi_device *dev = counter->counter_dev->dev;
 712         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 713         ni_660x_write_register(dev, counter->chip_index, bits,
 714                                ni_660x_register);
 715 }
 716
 717 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
 718                                       enum ni_gpct_register reg)
 719 {
 720         struct comedi_device *dev = counter->counter_dev->dev;
 721         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 722         return ni_660x_read_register(dev, counter->chip_index,
 723                                      ni_660x_register);
 724 }
 725
 726 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
 727                                                          *priv,
 728                                                          struct ni_gpct
 729                                                          *counter)
 730 {
 731         return priv->mite_rings[counter->chip_index][counter->counter_index];
 732 }
 733
 734 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
 735                                            unsigned mite_channel,
 736                                            struct ni_gpct *counter)
 737 {
 738         struct ni_660x_private *devpriv = dev->private;
 739         unsigned long flags;
 740
 741         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 742         devpriv->dma_configuration_soft_copies[counter->chip_index] &=
 743             ~dma_select_mask(mite_channel);
 744         devpriv->dma_configuration_soft_copies[counter->chip_index] |=
 745             dma_select_bits(mite_channel,
 746                             dma_selection_counter(counter->counter_index));
 747         ni_660x_write_register(dev, counter->chip_index,
 748                                devpriv->dma_configuration_soft_copies
 749                                [counter->chip_index] |
 750                                dma_reset_bit(mite_channel), DMAConfigRegister);
 751         mmiowb();
 752         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 753 }
 754
 755 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
 756                                              unsigned mite_channel,
 757                                              struct ni_gpct *counter)
 758 {
 759         struct ni_660x_private *devpriv = dev->private;
 760         unsigned long flags;
 761
 762         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 763         devpriv->dma_configuration_soft_copies[counter->chip_index] &=
 764             ~dma_select_mask(mite_channel);
 765         devpriv->dma_configuration_soft_copies[counter->chip_index] |=
 766             dma_select_bits(mite_channel, dma_selection_none);
 767         ni_660x_write_register(dev, counter->chip_index,
 768                                devpriv->dma_configuration_soft_copies
 769                                [counter->chip_index], DMAConfigRegister);
 770         mmiowb();
 771         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 772 }
 773
 774 static int ni_660x_request_mite_channel(struct comedi_device *dev,
 775                                         struct ni_gpct *counter,
 776                                         enum comedi_io_direction direction)
 777 {
 778         struct ni_660x_private *devpriv = dev->private;
 779         unsigned long flags;
 780         struct mite_channel *mite_chan;
 781
 782         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 783         BUG_ON(counter->mite_chan);
 784         mite_chan = mite_request_channel(devpriv->mite,
 785                                          mite_ring(devpriv, counter));
 786         if (mite_chan == NULL) {
 787                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 788                 comedi_error(dev,
 789                              "failed to reserve mite dma channel for counter.");
 790                 return -EBUSY;
 791         }
 792         mite_chan->dir = direction;
 793         ni_tio_set_mite_channel(counter, mite_chan);
 794         ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
 795         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 796         return 0;
 797 }
 798
 799 static void ni_660x_release_mite_channel(struct comedi_device *dev,
 800                                          struct ni_gpct *counter)
 801 {
 802         struct ni_660x_private *devpriv = dev->private;
 803         unsigned long flags;
 804
 805         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 806         if (counter->mite_chan) {
 807                 struct mite_channel *mite_chan = counter->mite_chan;
 808
 809                 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
 810                 ni_tio_set_mite_channel(counter, NULL);
 811                 mite_release_channel(mite_chan);
 812         }
 813         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 814 }
 815
 816 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 817 {
 818         int retval;
 819
 820         struct ni_gpct *counter = subdev_to_counter(s);
 821 /* const struct comedi_cmd *cmd = &s->async->cmd; */
 822
 823         retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
 824         if (retval) {
 825                 comedi_error(dev,
 826                              "no dma channel available for use by counter");
 827                 return retval;
 828         }
 829         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
 830         retval = ni_tio_cmd(counter, s->async);
 831
 832         return retval;
 833 }
 834
 835 static int ni_660x_cmdtest(struct comedi_device *dev,
 836                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
 837 {
 838         struct ni_gpct *counter = subdev_to_counter(s);
 839
 840         return ni_tio_cmdtest(counter, cmd);
 841 }
 842
 843 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
 844 {
 845         struct ni_gpct *counter = subdev_to_counter(s);
 846         int retval;
 847
 848         retval = ni_tio_cancel(counter);
 849         ni_660x_release_mite_channel(dev, counter);
 850         return retval;
 851 }
 852
 853 static void set_tio_counterswap(struct comedi_device *dev, int chipset)
 854 {
 855         /* See P. 3.5 of the Register-Level Programming manual.  The
 856            CounterSwap bit has to be set on the second chip, otherwise
 857            it will try to use the same pins as the first chip.
 858          */
 859         if (chipset)
 860                 ni_660x_write_register(dev, chipset, CounterSwap,
 861                                        ClockConfigRegister);
 862         else
 863                 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
 864 }
 865
 866 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
 867                                           struct comedi_subdevice *s)
 868 {
 869         ni_tio_handle_interrupt(subdev_to_counter(s), s);
 870         if (s->async->events) {
 871                 if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
 872                                         COMEDI_CB_OVERFLOW)) {
 873                         ni_660x_cancel(dev, s);
 874                 }
 875                 comedi_event(dev, s);
 876         }
 877 }
 878
 879 static irqreturn_t ni_660x_interrupt(int irq, void *d)
 880 {
 881         struct comedi_device *dev = d;
 882         struct ni_660x_private *devpriv = dev->private;
 883         struct comedi_subdevice *s;
 884         unsigned i;
 885         unsigned long flags;
 886
 887         if (!dev->attached)
 888                 return IRQ_NONE;
 889         /* lock to avoid race with comedi_poll */
 890         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
 891         smp_mb();
 892         for (i = 0; i < ni_660x_num_counters(dev); ++i) {
 893                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
 894                 ni_660x_handle_gpct_interrupt(dev, s);
 895         }
 896         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
 897         return IRQ_HANDLED;
 898 }
 899
 900 static int ni_660x_input_poll(struct comedi_device *dev,
 901                               struct comedi_subdevice *s)
 902 {
 903         struct ni_660x_private *devpriv = dev->private;
 904         unsigned long flags;
 905
 906         /* lock to avoid race with comedi_poll */
 907         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
 908         mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
 909         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
 910         return comedi_buf_read_n_available(s->async);
 911 }
 912
 913 static int ni_660x_buf_change(struct comedi_device *dev,
 914                               struct comedi_subdevice *s,
 915                               unsigned long new_size)
 916 {
 917         struct ni_660x_private *devpriv = dev->private;
 918         int ret;
 919
 920         ret = mite_buf_change(mite_ring(devpriv, subdev_to_counter(s)),
 921                               s->async);
 922         if (ret < 0)
 923                 return ret;
 924
 925         return 0;
 926 }
 927
 928 static int ni_660x_allocate_private(struct comedi_device *dev)
 929 {
 930         struct ni_660x_private *devpriv;
 931         unsigned i;
 932
 933         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 934         if (!devpriv)
 935                 return -ENOMEM;
 936
 937         spin_lock_init(&devpriv->mite_channel_lock);
 938         spin_lock_init(&devpriv->interrupt_lock);
 939         spin_lock_init(&devpriv->soft_reg_copy_lock);
 940         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
 941                 devpriv->pfi_output_selects[i] = pfi_output_select_counter;
 942
 943         return 0;
 944 }
 945
 946 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
 947 {
 948         const struct ni_660x_board *board = comedi_board(dev);
 949         struct ni_660x_private *devpriv = dev->private;
 950         unsigned i;
 951         unsigned j;
 952
 953         for (i = 0; i < board->n_chips; ++i) {
 954                 for (j = 0; j < counters_per_chip; ++j) {
 955                         devpriv->mite_rings[i][j] =
 956                             mite_alloc_ring(devpriv->mite);
 957                         if (devpriv->mite_rings[i][j] == NULL)
 958                                 return -ENOMEM;
 959                 }
 960         }
 961         return 0;
 962 }
 963
 964 static void ni_660x_free_mite_rings(struct comedi_device *dev)
 965 {
 966         const struct ni_660x_board *board = comedi_board(dev);
 967         struct ni_660x_private *devpriv = dev->private;
 968         unsigned i;
 969         unsigned j;
 970
 971         for (i = 0; i < board->n_chips; ++i) {
 972                 for (j = 0; j < counters_per_chip; ++j)
 973                         mite_free_ring(devpriv->mite_rings[i][j]);
 974         }
 975 }
 976
 977 static int
 978 ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 979                    struct comedi_insn *insn, unsigned int *data)
 980 {
 981         return ni_tio_rinsn(subdev_to_counter(s), insn, data);
 982 }
 983
 984 static void init_tio_chip(struct comedi_device *dev, int chipset)
 985 {
 986         struct ni_660x_private *devpriv = dev->private;
 987         unsigned i;
 988
 989         /*  init dma configuration register */
 990         devpriv->dma_configuration_soft_copies[chipset] = 0;
 991         for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
 992                 devpriv->dma_configuration_soft_copies[chipset] |=
 993                     dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
 994         }
 995         ni_660x_write_register(dev, chipset,
 996                                devpriv->dma_configuration_soft_copies[chipset],
 997                                DMAConfigRegister);
 998         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
 999                 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1000 }
1001
1002 static int
1003 ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1004                          struct comedi_insn *insn, unsigned int *data)
1005 {
1006         return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1007 }
1008
1009 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1010                               struct comedi_subdevice *s,
1011                               struct comedi_insn *insn, unsigned int *data)
1012 {
1013         return ni_tio_winsn(subdev_to_counter(s), insn, data);
1014 }
1015
1016 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1017                                  struct comedi_subdevice *s,
1018                                  struct comedi_insn *insn, unsigned int *data)
1019 {
1020         unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1021
1022         /*  Check if we have to write some bits */
1023         if (data[0]) {
1024                 s->state &= ~(data[0] << base_bitfield_channel);
1025                 s->state |= (data[0] & data[1]) << base_bitfield_channel;
1026                 /* Write out the new digital output lines */
1027                 ni_660x_write_register(dev, 0, s->state, DIO32Output);
1028         }
1029         /* on return, data[1] contains the value of the digital
1030          * input and output lines. */
1031         data[1] =
1032             (ni_660x_read_register(dev, 0,
1033                                    DIO32Input) >> base_bitfield_channel);
1034         return insn->n;
1035 }
1036
1037 static void ni_660x_select_pfi_output(struct comedi_device *dev,
1038                                       unsigned pfi_channel,
1039                                       unsigned output_select)
1040 {
1041         const struct ni_660x_board *board = comedi_board(dev);
1042         static const unsigned counter_4_7_first_pfi = 8;
1043         static const unsigned counter_4_7_last_pfi = 23;
1044         unsigned active_chipset = 0;
1045         unsigned idle_chipset = 0;
1046         unsigned active_bits;
1047         unsigned idle_bits;
1048
1049         if (board->n_chips > 1) {
1050                 if (output_select == pfi_output_select_counter &&
1051                     pfi_channel >= counter_4_7_first_pfi &&
1052                     pfi_channel <= counter_4_7_last_pfi) {
1053                         active_chipset = 1;
1054                         idle_chipset = 0;
1055                 } else {
1056                         active_chipset = 0;
1057                         idle_chipset = 1;
1058                 }
1059         }
1060
1061         if (idle_chipset != active_chipset) {
1062                 idle_bits =
1063                     ni_660x_read_register(dev, idle_chipset,
1064                                           IOConfigReg(pfi_channel));
1065                 idle_bits &= ~pfi_output_select_mask(pfi_channel);
1066                 idle_bits |=
1067                     pfi_output_select_bits(pfi_channel,
1068                                            pfi_output_select_high_Z);
1069                 ni_660x_write_register(dev, idle_chipset, idle_bits,
1070                                        IOConfigReg(pfi_channel));
1071         }
1072
1073         active_bits =
1074             ni_660x_read_register(dev, active_chipset,
1075                                   IOConfigReg(pfi_channel));
1076         active_bits &= ~pfi_output_select_mask(pfi_channel);
1077         active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1078         ni_660x_write_register(dev, active_chipset, active_bits,
1079                                IOConfigReg(pfi_channel));
1080 }
1081
1082 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1083                                    unsigned source)
1084 {
1085         struct ni_660x_private *devpriv = dev->private;
1086
1087         if (source > num_pfi_output_selects)
1088                 return -EINVAL;
1089         if (source == pfi_output_select_high_Z)
1090                 return -EINVAL;
1091         if (chan < min_counter_pfi_chan) {
1092                 if (source == pfi_output_select_counter)
1093                         return -EINVAL;
1094         } else if (chan > max_dio_pfi_chan) {
1095                 if (source == pfi_output_select_do)
1096                         return -EINVAL;
1097         }
1098
1099         devpriv->pfi_output_selects[chan] = source;
1100         if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan))
1101                 ni_660x_select_pfi_output(dev, chan,
1102                                           devpriv->pfi_output_selects[chan]);
1103         return 0;
1104 }
1105
1106 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1107                                    struct comedi_subdevice *s,
1108                                    struct comedi_insn *insn,
1109                                    unsigned int *data)
1110 {
1111         struct ni_660x_private *devpriv = dev->private;
1112         unsigned int chan = CR_CHAN(insn->chanspec);
1113         uint64_t bit = 1ULL << chan;
1114         unsigned int val;
1115         int ret;
1116
1117         switch (data[0]) {
1118         case INSN_CONFIG_DIO_OUTPUT:
1119                 devpriv->pfi_direction_bits |= bit;
1120                 ni_660x_select_pfi_output(dev, chan,
1121                                           devpriv->pfi_output_selects[chan]);
1122                 break;
1123
1124         case INSN_CONFIG_DIO_INPUT:
1125                 devpriv->pfi_direction_bits &= ~bit;
1126                 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1127                 break;
1128
1129         case INSN_CONFIG_DIO_QUERY:
1130                 data[1] = (devpriv->pfi_direction_bits & bit) ? COMEDI_OUTPUT
1131                                                               : COMEDI_INPUT;
1132                 break;
1133
1134         case INSN_CONFIG_SET_ROUTING:
1135                 ret = ni_660x_set_pfi_routing(dev, chan, data[1]);
1136                 if (ret)
1137                         return ret;
1138                 break;
1139
1140         case INSN_CONFIG_GET_ROUTING:
1141                 data[1] = devpriv->pfi_output_selects[chan];
1142                 break;
1143
1144         case INSN_CONFIG_FILTER:
1145                 val = ni_660x_read_register(dev, 0, IOConfigReg(chan));
1146                 val &= ~pfi_input_select_mask(chan);
1147                 val |= pfi_input_select_bits(chan, data[1]);
1148                 ni_660x_write_register(dev, 0, val, IOConfigReg(chan));
1149                 break;
1150
1151         default:
1152                 return -EINVAL;
1153         }
1154
1155         return insn->n;
1156 }
1157
1158 static int ni_660x_auto_attach(struct comedi_device *dev,
1159                                unsigned long context)
1160 {
1161         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1162         const struct ni_660x_board *board = NULL;
1163         struct ni_660x_private *devpriv;
1164         struct comedi_subdevice *s;
1165         int ret;
1166         unsigned i;
1167         unsigned global_interrupt_config_bits;
1168
1169         if (context < ARRAY_SIZE(ni_660x_boards))
1170                 board = &ni_660x_boards[context];
1171         if (!board)
1172                 return -ENODEV;
1173         dev->board_ptr = board;
1174         dev->board_name = board->name;
1175
1176         ret = comedi_pci_enable(dev);
1177         if (ret)
1178                 return ret;
1179
1180         ret = ni_660x_allocate_private(dev);
1181         if (ret < 0)
1182                 return ret;
1183         devpriv = dev->private;
1184
1185         devpriv->mite = mite_alloc(pcidev);
1186         if (!devpriv->mite)
1187                 return -ENOMEM;
1188
1189         ret = mite_setup2(devpriv->mite, 1);
1190         if (ret < 0) {
1191                 dev_warn(dev->class_dev, "error setting up mite\n");
1192                 return ret;
1193         }
1194
1195         ret = ni_660x_alloc_mite_rings(dev);
1196         if (ret < 0)
1197                 return ret;
1198
1199         ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS);
1200         if (ret)
1201                 return ret;
1202
1203         s = &dev->subdevices[0];
1204         /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1205         s->type = COMEDI_SUBD_UNUSED;
1206
1207         s = &dev->subdevices[NI_660X_DIO_SUBDEV];
1208         /* DIGITAL I/O SUBDEVICE */
1209         s->type = COMEDI_SUBD_DIO;
1210         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1211         s->n_chan = NUM_PFI_CHANNELS;
1212         s->maxdata = 1;
1213         s->range_table = &range_digital;
1214         s->insn_bits = ni_660x_dio_insn_bits;
1215         s->insn_config = ni_660x_dio_insn_config;
1216         /*  we use the ioconfig registers to control dio direction, so zero
1217         output enables in stc dio control reg */
1218         ni_660x_write_register(dev, 0, 0, STCDIOControl);
1219
1220         devpriv->counter_dev = ni_gpct_device_construct(dev,
1221                                                      &ni_gpct_write_register,
1222                                                      &ni_gpct_read_register,
1223                                                      ni_gpct_variant_660x,
1224                                                      ni_660x_num_counters
1225                                                      (dev));
1226         if (devpriv->counter_dev == NULL)
1227                 return -ENOMEM;
1228         for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1229                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
1230                 if (i < ni_660x_num_counters(dev)) {
1231                         s->type = COMEDI_SUBD_COUNTER;
1232                         s->subdev_flags =
1233                             SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1234                             SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1235                         s->n_chan = 3;
1236                         s->maxdata = 0xffffffff;
1237                         s->insn_read = ni_660x_GPCT_rinsn;
1238                         s->insn_write = ni_660x_GPCT_winsn;
1239                         s->insn_config = ni_660x_GPCT_insn_config;
1240                         s->do_cmd = &ni_660x_cmd;
1241                         s->len_chanlist = 1;
1242                         s->do_cmdtest = &ni_660x_cmdtest;
1243                         s->cancel = &ni_660x_cancel;
1244                         s->poll = &ni_660x_input_poll;
1245                         s->async_dma_dir = DMA_BIDIRECTIONAL;
1246                         s->buf_change = &ni_660x_buf_change;
1247                         s->private = &devpriv->counter_dev->counters[i];
1248
1249                         devpriv->counter_dev->counters[i].chip_index =
1250                             i / counters_per_chip;
1251                         devpriv->counter_dev->counters[i].counter_index =
1252                             i % counters_per_chip;
1253                 } else {
1254                         s->type = COMEDI_SUBD_UNUSED;
1255                 }
1256         }
1257         for (i = 0; i < board->n_chips; ++i)
1258                 init_tio_chip(dev, i);
1259
1260         for (i = 0; i < ni_660x_num_counters(dev); ++i)
1261                 ni_tio_init_counter(&devpriv->counter_dev->counters[i]);
1262
1263         for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1264                 if (i < min_counter_pfi_chan)
1265                         ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1266                 else
1267                         ni_660x_set_pfi_routing(dev, i,
1268                                                 pfi_output_select_counter);
1269                 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1270         }
1271         /* to be safe, set counterswap bits on tio chips after all the counter
1272            outputs have been set to high impedance mode */
1273         for (i = 0; i < board->n_chips; ++i)
1274                 set_tio_counterswap(dev, i);
1275
1276         ret = request_irq(mite_irq(devpriv->mite), ni_660x_interrupt,
1277                           IRQF_SHARED, "ni_660x", dev);
1278         if (ret < 0) {
1279                 dev_warn(dev->class_dev, " irq not available\n");
1280                 return ret;
1281         }
1282         dev->irq = mite_irq(devpriv->mite);
1283         global_interrupt_config_bits = Global_Int_Enable_Bit;
1284         if (board->n_chips > 1)
1285                 global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1286         ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1287                                GlobalInterruptConfigRegister);
1288         dev_info(dev->class_dev, "ni_660x: %s attached\n", dev->board_name);
1289         return 0;
1290 }
1291
1292 static void ni_660x_detach(struct comedi_device *dev)
1293 {
1294         struct ni_660x_private *devpriv = dev->private;
1295
1296         if (dev->irq)
1297                 free_irq(dev->irq, dev);
1298         if (devpriv) {
1299                 if (devpriv->counter_dev)
1300                         ni_gpct_device_destroy(devpriv->counter_dev);
1301                 if (devpriv->mite) {
1302                         ni_660x_free_mite_rings(dev);
1303                         mite_unsetup(devpriv->mite);
1304                         mite_free(devpriv->mite);
1305                 }
1306         }
1307         comedi_pci_disable(dev);
1308 }
1309
1310 static struct comedi_driver ni_660x_driver = {
1311         .driver_name    = "ni_660x",
1312         .module         = THIS_MODULE,
1313         .auto_attach    = ni_660x_auto_attach,
1314         .detach         = ni_660x_detach,
1315 };
1316
1317 static int ni_660x_pci_probe(struct pci_dev *dev,
1318                              const struct pci_device_id *id)
1319 {
1320         return comedi_pci_auto_config(dev, &ni_660x_driver, id->driver_data);
1321 }
1322
1323 static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
1324         { PCI_VDEVICE(NI, 0x1310), BOARD_PCI6602 },
1325         { PCI_VDEVICE(NI, 0x1360), BOARD_PXI6602 },
1326         { PCI_VDEVICE(NI, 0x2c60), BOARD_PCI6601 },
1327         { PCI_VDEVICE(NI, 0x2cc0), BOARD_PXI6608 },
1328         { PCI_VDEVICE(NI, 0x1e40), BOARD_PXI6624 },
1329         { 0 }
1330 };
1331 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
1332
1333 static struct pci_driver ni_660x_pci_driver = {
1334         .name           = "ni_660x",
1335         .id_table       = ni_660x_pci_table,
1336         .probe          = ni_660x_pci_probe,
1337         .remove         = comedi_pci_auto_unconfig,
1338 };
1339 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
1340
1341 MODULE_AUTHOR("Comedi http://www.comedi.org");
1342 MODULE_DESCRIPTION("Comedi low-level driver");
1343 MODULE_LICENSE("GPL");