2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 ************************************************************************
24 Description: National Instruments Lab-PC (& compatibles)
25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
30 Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31 and analog references will work, the available ranges/arefs will
32 depend on how you have configured the jumpers on your board
33 (see your owner's manual).
35 Kernel-level ISA plug-and-play support for the lab-pc-1200
37 yet been added to the driver, mainly due to the fact that
38 I don't know the device id numbers. If you have one
40 please file a bug report at https://bugs.comedi.org/
41 so I can get the necessary information from you.
43 The 1200 series boards have onboard calibration dacs for correcting
44 analog input/output offsets and gains. The proper settings for these
45 caldacs are stored on the board's eeprom. To read the caldac values
46 from the eeprom and store them into a file that can be then be used by
47 comedilib, use the comedi_calibrate program.
49 Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
54 Configuration options - PCI boards:
58 The Lab-pc+ has quirky chanlist requirements
59 when scanning multiple channels. Multiple channel scan
60 sequence must start at highest channel, then decrement down to
61 channel 0. The rest of the cards can scan down like lab-pc+ or scan
62 up from channel zero. Chanlists consisting of all one channel
63 are also legal, and allow you to pace conversions in bursts.
70 341309a (labpc-1200 register manual)
77 /* #define LABPC_DEBUG enable debugging messages */
79 #include <linux/interrupt.h>
80 #include "../comedidev.h"
82 #include <linux/delay.h>
88 #include "comedi_fc.h"
91 #define DRV_NAME "ni_labpc"
93 /* size of io region used by board */
95 /* 2 MHz master clock */
96 #define LABPC_TIMER_BASE 500
98 /* Registers for the lab-pc+ */
100 /* write-only registers */
101 #define COMMAND1_REG 0x0
102 #define ADC_GAIN_MASK (0x7 << 4)
103 #define ADC_CHAN_BITS(x) ((x) & 0x7)
104 /* enables multi channel scans */
105 #define ADC_SCAN_EN_BIT 0x80
106 #define COMMAND2_REG 0x1
107 /* enable pretriggering (used in conjunction with SWTRIG) */
108 #define PRETRIG_BIT 0x1
109 /* enable paced conversions on external trigger */
110 #define HWTRIG_BIT 0x2
111 /* enable paced conversions */
112 #define SWTRIG_BIT 0x4
113 /* use two cascaded counters for pacing */
114 #define CASCADE_BIT 0x8
115 #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
116 #define COMMAND3_REG 0x2
117 /* enable dma transfers */
118 #define DMA_EN_BIT 0x1
119 /* enable interrupts for 8255 */
120 #define DIO_INTR_EN_BIT 0x2
121 /* enable dma terminal count interrupt */
122 #define DMATC_INTR_EN_BIT 0x4
123 /* enable timer interrupt */
124 #define TIMER_INTR_EN_BIT 0x8
125 /* enable error interrupt */
126 #define ERR_INTR_EN_BIT 0x10
127 /* enable fifo not empty interrupt */
128 #define ADC_FNE_INTR_EN_BIT 0x20
129 #define ADC_CONVERT_REG 0x3
130 #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
131 #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
132 #define ADC_CLEAR_REG 0x8
133 #define DMATC_CLEAR_REG 0xa
134 #define TIMER_CLEAR_REG 0xc
135 /* 1200 boards only */
136 #define COMMAND6_REG 0xe
137 /* select ground or common-mode reference */
138 #define ADC_COMMON_BIT 0x1
140 #define ADC_UNIP_BIT 0x2
142 #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
143 /* enable fifo half full interrupt */
144 #define ADC_FHF_INTR_EN_BIT 0x20
145 /* enable interrupt on end of hardware count */
146 #define A1_INTR_EN_BIT 0x40
147 /* scan up from channel zero instead of down to zero */
148 #define ADC_SCAN_UP_BIT 0x80
149 #define COMMAND4_REG 0xf
150 /* enables 'interval' scanning */
151 #define INTERVAL_SCAN_EN_BIT 0x1
152 /* enables external signal on counter b1 output to trigger scan */
153 #define EXT_SCAN_EN_BIT 0x2
154 /* chooses direction (output or input) for EXTCONV* line */
155 #define EXT_CONVERT_OUT_BIT 0x4
156 /* chooses differential inputs for adc (in conjunction with board jumper) */
157 #define ADC_DIFF_BIT 0x8
158 #define EXT_CONVERT_DISABLE_BIT 0x10
159 /* 1200 boards only, calibration stuff */
160 #define COMMAND5_REG 0x1c
161 /* enable eeprom for write */
162 #define EEPROM_WRITE_UNPROTECT_BIT 0x4
163 /* enable dithering */
164 #define DITHER_EN_BIT 0x8
165 /* load calibration dac */
166 #define CALDAC_LOAD_BIT 0x10
167 /* serial clock - rising edge writes, falling edge reads */
168 #define SCLOCK_BIT 0x20
169 /* serial data bit for writing to eeprom or calibration dacs */
170 #define SDATA_BIT 0x40
171 /* enable eeprom for read/write */
172 #define EEPROM_EN_BIT 0x80
173 #define INTERVAL_COUNT_REG 0x1e
174 #define INTERVAL_LOAD_REG 0x1f
175 #define INTERVAL_LOAD_BITS 0x1
177 /* read-only registers */
178 #define STATUS1_REG 0x0
179 /* data is available in fifo */
180 #define DATA_AVAIL_BIT 0x1
181 /* overrun has occurred */
182 #define OVERRUN_BIT 0x2
184 #define OVERFLOW_BIT 0x4
185 /* timer interrupt has occured */
186 #define TIMER_BIT 0x8
187 /* dma terminal count has occured */
188 #define DMATC_BIT 0x10
189 /* external trigger has occured */
190 #define EXT_TRIG_BIT 0x40
191 /* 1200 boards only */
192 #define STATUS2_REG 0x1d
193 /* programmable eeprom serial output */
194 #define EEPROM_OUT_BIT 0x1
195 /* counter A1 terminal count */
196 #define A1_TC_BIT 0x2
197 /* fifo not half full */
199 #define ADC_FIFO_REG 0xa
201 #define DIO_BASE_REG 0x10
202 #define COUNTER_A_BASE_REG 0x14
203 #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
204 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
205 #define INIT_A0_BITS 0x14
206 /* put hardware conversion counter output in harmless state (a1 mode 0) */
207 #define INIT_A1_BITS 0x70
208 #define COUNTER_B_BASE_REG 0x18
210 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it);
211 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
212 static irqreturn_t labpc_interrupt(int irq, void *d);
213 static int labpc_drain_fifo(struct comedi_device *dev);
214 static void labpc_drain_dma(struct comedi_device *dev);
215 static void handle_isa_dma(struct comedi_device *dev);
216 static void labpc_drain_dregs(struct comedi_device *dev);
217 static int labpc_ai_cmdtest(struct comedi_device *dev,
218 struct comedi_subdevice *s, struct comedi_cmd *cmd);
219 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
220 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
221 struct comedi_insn *insn, unsigned int *data);
222 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
223 struct comedi_insn *insn, unsigned int *data);
224 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
225 struct comedi_insn *insn, unsigned int *data);
226 static int labpc_calib_read_insn(struct comedi_device *dev,
227 struct comedi_subdevice *s,
228 struct comedi_insn *insn, unsigned int *data);
229 static int labpc_calib_write_insn(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 struct comedi_insn *insn, unsigned int *data);
232 static int labpc_eeprom_read_insn(struct comedi_device *dev,
233 struct comedi_subdevice *s,
234 struct comedi_insn *insn, unsigned int *data);
235 static int labpc_eeprom_write_insn(struct comedi_device *dev,
236 struct comedi_subdevice *s,
237 struct comedi_insn *insn,
239 static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd);
240 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
241 #ifdef CONFIG_COMEDI_PCI
242 static int labpc_find_device(struct comedi_device *dev, int bus, int slot);
244 static int labpc_dio_mem_callback(int dir, int port, int data,
246 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
247 unsigned int num_bits);
248 static unsigned int labpc_serial_in(struct comedi_device *dev);
249 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
250 unsigned int address);
251 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
252 static unsigned int labpc_eeprom_write(struct comedi_device *dev,
253 unsigned int address,
255 static void write_caldac(struct comedi_device *dev, unsigned int channel,
260 MODE_SINGLE_CHAN_INTERVAL,
265 /* analog input ranges */
266 #define NUM_LABPC_PLUS_AI_RANGES 16
267 /* indicates unipolar ranges */
268 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
287 /* map range index to gain bits */
288 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
307 static const struct comedi_lrange range_labpc_plus_ai = {
308 NUM_LABPC_PLUS_AI_RANGES,
329 #define NUM_LABPC_1200_AI_RANGES 14
330 /* indicates unipolar ranges */
331 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
348 /* map range index to gain bits */
349 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
366 const struct comedi_lrange range_labpc_1200_ai = {
367 NUM_LABPC_1200_AI_RANGES,
386 /* analog output ranges */
387 #define AO_RANGE_IS_UNIPOLAR 0x1
388 static const struct comedi_lrange range_labpc_ao = {
396 /* functions that do inb/outb and readb/writeb so we can use
397 * function pointers to decide which to use */
398 static inline unsigned int labpc_inb(unsigned long address)
403 static inline void labpc_outb(unsigned int byte, unsigned long address)
408 static inline unsigned int labpc_readb(unsigned long address)
410 return readb((void *)address);
413 static inline void labpc_writeb(unsigned int byte, unsigned long address)
415 writeb(byte, (void *)address);
418 static const struct labpc_board_struct labpc_boards[] = {
420 .name = "lab-pc-1200",
422 .bustype = isa_bustype,
423 .register_layout = labpc_1200_layout,
425 .ai_range_table = &range_labpc_1200_ai,
426 .ai_range_code = labpc_1200_ai_gain_bits,
427 .ai_range_is_unipolar = labpc_1200_is_unipolar,
429 .memory_mapped_io = 0,
432 .name = "lab-pc-1200ai",
434 .bustype = isa_bustype,
435 .register_layout = labpc_1200_layout,
437 .ai_range_table = &range_labpc_1200_ai,
438 .ai_range_code = labpc_1200_ai_gain_bits,
439 .ai_range_is_unipolar = labpc_1200_is_unipolar,
441 .memory_mapped_io = 0,
446 .bustype = isa_bustype,
447 .register_layout = labpc_plus_layout,
449 .ai_range_table = &range_labpc_plus_ai,
450 .ai_range_code = labpc_plus_ai_gain_bits,
451 .ai_range_is_unipolar = labpc_plus_is_unipolar,
453 .memory_mapped_io = 0,
455 #ifdef CONFIG_COMEDI_PCI
460 .bustype = pci_bustype,
461 .register_layout = labpc_1200_layout,
463 .ai_range_table = &range_labpc_1200_ai,
464 .ai_range_code = labpc_1200_ai_gain_bits,
465 .ai_range_is_unipolar = labpc_1200_is_unipolar,
467 .memory_mapped_io = 1,
469 /* dummy entry so pci board works when comedi_config is passed driver name */
472 .bustype = pci_bustype,
478 * Useful for shorthand access to the particular board structure
480 #define thisboard ((struct labpc_board_struct *)dev->board_ptr)
482 /* size in bytes of dma buffer */
483 static const int dma_buffer_size = 0xff00;
484 /* 2 bytes per sample */
485 static const int sample_size = 2;
487 #define devpriv ((struct labpc_private *)dev->private)
489 static struct comedi_driver driver_labpc = {
490 .driver_name = DRV_NAME,
491 .module = THIS_MODULE,
492 .attach = labpc_attach,
493 .detach = labpc_common_detach,
494 .num_names = ARRAY_SIZE(labpc_boards),
495 .board_name = &labpc_boards[0].name,
496 .offset = sizeof(struct labpc_board_struct),
499 #ifdef CONFIG_COMEDI_PCI
500 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
502 PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
506 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
507 #endif /* CONFIG_COMEDI_PCI */
509 static inline int labpc_counter_load(struct comedi_device *dev,
510 unsigned long base_address,
511 unsigned int counter_number,
512 unsigned int count, unsigned int mode)
514 if (thisboard->memory_mapped_io)
515 return i8254_mm_load((void *)base_address, 0, counter_number,
518 return i8254_load(base_address, 0, counter_number, count, mode);
521 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
522 unsigned int irq, unsigned int dma_chan)
524 struct comedi_subdevice *s;
526 unsigned long dma_flags, isr_flags;
529 printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name,
532 printk(", irq %u", irq);
534 printk(", dma %u", dma_chan);
538 printk("io base address is zero!\n");
541 /* request io regions for isa boards */
542 if (thisboard->bustype == isa_bustype) {
543 /* check if io addresses are available */
544 if (!request_region(iobase, LABPC_SIZE,
545 driver_labpc.driver_name)) {
546 printk("I/O port conflict\n");
550 dev->iobase = iobase;
552 if (thisboard->memory_mapped_io) {
553 devpriv->read_byte = labpc_readb;
554 devpriv->write_byte = labpc_writeb;
556 devpriv->read_byte = labpc_inb;
557 devpriv->write_byte = labpc_outb;
559 /* initialize board's command registers */
560 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
561 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
562 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
563 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
564 if (thisboard->register_layout == labpc_1200_layout) {
565 devpriv->write_byte(devpriv->command5_bits,
566 dev->iobase + COMMAND5_REG);
567 devpriv->write_byte(devpriv->command6_bits,
568 dev->iobase + COMMAND6_REG);
574 if (thisboard->bustype == pci_bustype)
575 isr_flags |= IRQF_SHARED;
576 if (request_irq(irq, labpc_interrupt, isr_flags,
577 driver_labpc.driver_name, dev)) {
578 printk("unable to allocate irq %u\n", irq);
584 /* grab dma channel */
586 printk(" invalid dma channel %u\n", dma_chan);
588 } else if (dma_chan) {
589 /* allocate dma buffer */
590 devpriv->dma_buffer =
591 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
592 if (devpriv->dma_buffer == NULL) {
593 printk(" failed to allocate dma buffer\n");
596 if (request_dma(dma_chan, driver_labpc.driver_name)) {
597 printk(" failed to allocate dma channel %u\n",
601 devpriv->dma_chan = dma_chan;
602 dma_flags = claim_dma_lock();
603 disable_dma(devpriv->dma_chan);
604 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
605 release_dma_lock(dma_flags);
608 dev->board_name = thisboard->name;
610 if (alloc_subdevices(dev, 5) < 0)
613 /* analog input subdevice */
614 s = dev->subdevices + 0;
615 dev->read_subdev = s;
616 s->type = COMEDI_SUBD_AI;
618 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
621 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
622 s->range_table = thisboard->ai_range_table;
623 s->do_cmd = labpc_ai_cmd;
624 s->do_cmdtest = labpc_ai_cmdtest;
625 s->insn_read = labpc_ai_rinsn;
626 s->cancel = labpc_cancel;
629 s = dev->subdevices + 1;
630 if (thisboard->has_ao) {
632 * Could provide command support, except it only has a
633 * one sample hardware buffer for analog output and no
636 s->type = COMEDI_SUBD_AO;
637 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
638 s->n_chan = NUM_AO_CHAN;
639 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
640 s->range_table = &range_labpc_ao;
641 s->insn_read = labpc_ao_rinsn;
642 s->insn_write = labpc_ao_winsn;
643 /* initialize analog outputs to a known value */
644 for (i = 0; i < s->n_chan; i++) {
645 devpriv->ao_value[i] = s->maxdata / 2;
646 lsb = devpriv->ao_value[i] & 0xff;
647 msb = (devpriv->ao_value[i] >> 8) & 0xff;
648 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
649 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
652 s->type = COMEDI_SUBD_UNUSED;
656 s = dev->subdevices + 2;
657 /* if board uses io memory we have to give a custom callback
658 * function to the 8255 driver */
659 if (thisboard->memory_mapped_io)
660 subdev_8255_init(dev, s, labpc_dio_mem_callback,
661 (unsigned long)(dev->iobase + DIO_BASE_REG));
663 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
665 /* calibration subdevices for boards that have one */
666 s = dev->subdevices + 3;
667 if (thisboard->register_layout == labpc_1200_layout) {
668 s->type = COMEDI_SUBD_CALIB;
669 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
672 s->insn_read = labpc_calib_read_insn;
673 s->insn_write = labpc_calib_write_insn;
675 for (i = 0; i < s->n_chan; i++)
676 write_caldac(dev, i, s->maxdata / 2);
678 s->type = COMEDI_SUBD_UNUSED;
681 s = dev->subdevices + 4;
682 if (thisboard->register_layout == labpc_1200_layout) {
683 s->type = COMEDI_SUBD_MEMORY;
684 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
685 s->n_chan = EEPROM_SIZE;
687 s->insn_read = labpc_eeprom_read_insn;
688 s->insn_write = labpc_eeprom_write_insn;
690 for (i = 0; i < EEPROM_SIZE; i++)
691 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
694 for (i = 0; i < EEPROM_SIZE; i++)
695 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]);
699 s->type = COMEDI_SUBD_UNUSED;
704 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
706 unsigned long iobase = 0;
707 unsigned int irq = 0;
708 unsigned int dma_chan = 0;
709 #ifdef CONFIG_COMEDI_PCI
713 /* allocate and initialize dev->private */
714 if (alloc_private(dev, sizeof(struct labpc_private)) < 0)
717 /* get base address, irq etc. based on bustype */
718 switch (thisboard->bustype) {
720 iobase = it->options[0];
721 irq = it->options[1];
722 dma_chan = it->options[2];
725 #ifdef CONFIG_COMEDI_PCI
726 retval = labpc_find_device(dev, it->options[0], it->options[1]);
729 retval = mite_setup(devpriv->mite);
732 iobase = (unsigned long)devpriv->mite->daq_io_addr;
733 irq = mite_irq(devpriv->mite);
735 printk(" this driver has not been built with PCI support.\n");
741 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n");
745 printk("bug! couldn't determine board type\n");
750 return labpc_common_attach(dev, iobase, irq, dma_chan);
753 /* adapted from ni_pcimio for finding mite based boards (pc-1200) */
754 #ifdef CONFIG_COMEDI_PCI
755 static int labpc_find_device(struct comedi_device *dev, int bus, int slot)
757 struct mite_struct *mite;
759 for (mite = mite_devices; mite; mite = mite->next) {
762 /* if bus/slot are specified then make sure we have the right bus/slot */
764 if (bus != mite->pcidev->bus->number
765 || slot != PCI_SLOT(mite->pcidev->devfn))
768 for (i = 0; i < driver_labpc.num_names; i++) {
769 if (labpc_boards[i].bustype != pci_bustype)
771 if (mite_device_id(mite) == labpc_boards[i].device_id) {
772 devpriv->mite = mite;
773 /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */
774 dev->board_ptr = &labpc_boards[i];
779 printk("no device found\n");
785 int labpc_common_detach(struct comedi_device *dev)
787 printk("comedi%d: ni_labpc: detach\n", dev->minor);
790 subdev_8255_cleanup(dev, dev->subdevices + 2);
792 /* only free stuff if it has been allocated by _attach */
793 if (devpriv->dma_buffer)
794 kfree(devpriv->dma_buffer);
795 if (devpriv->dma_chan)
796 free_dma(devpriv->dma_chan);
798 free_irq(dev->irq, dev);
799 if (thisboard->bustype == isa_bustype && dev->iobase)
800 release_region(dev->iobase, LABPC_SIZE);
801 #ifdef CONFIG_COMEDI_PCI
803 mite_unsetup(devpriv->mite);
809 static void labpc_clear_adc_fifo(const struct comedi_device *dev)
811 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
812 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
813 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
816 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
820 spin_lock_irqsave(&dev->spinlock, flags);
821 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
822 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
823 spin_unlock_irqrestore(&dev->spinlock, flags);
825 devpriv->command3_bits = 0;
826 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
831 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
833 if (cmd->chanlist_len == 1)
834 return MODE_SINGLE_CHAN;
836 /* chanlist may be NULL during cmdtest. */
837 if (cmd->chanlist == NULL)
838 return MODE_MULT_CHAN_UP;
840 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
841 return MODE_SINGLE_CHAN_INTERVAL;
843 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
844 return MODE_MULT_CHAN_UP;
846 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
847 return MODE_MULT_CHAN_DOWN;
849 printk("ni_labpc: bug! this should never happen\n");
854 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
855 const struct comedi_cmd *cmd)
857 int mode, channel, range, aref, i;
859 if (cmd->chanlist == NULL)
862 mode = labpc_ai_scan_mode(cmd);
864 if (mode == MODE_SINGLE_CHAN)
867 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
868 if (cmd->chanlist_len > 0xff) {
870 "ni_labpc: chanlist too long for single channel interval mode\n");
875 channel = CR_CHAN(cmd->chanlist[0]);
876 range = CR_RANGE(cmd->chanlist[0]);
877 aref = CR_AREF(cmd->chanlist[0]);
879 for (i = 0; i < cmd->chanlist_len; i++) {
882 case MODE_SINGLE_CHAN_INTERVAL:
883 if (CR_CHAN(cmd->chanlist[i]) != channel) {
885 "channel scanning order specified in chanlist is not supported by hardware.\n");
889 case MODE_MULT_CHAN_UP:
890 if (CR_CHAN(cmd->chanlist[i]) != i) {
892 "channel scanning order specified in chanlist is not supported by hardware.\n");
896 case MODE_MULT_CHAN_DOWN:
897 if (CR_CHAN(cmd->chanlist[i]) !=
898 cmd->chanlist_len - i - 1) {
900 "channel scanning order specified in chanlist is not supported by hardware.\n");
905 printk("ni_labpc: bug! in chanlist check\n");
910 if (CR_RANGE(cmd->chanlist[i]) != range) {
912 "entries in chanlist must all have the same range\n");
916 if (CR_AREF(cmd->chanlist[i]) != aref) {
918 "entries in chanlist must all have the same reference\n");
926 static int labpc_use_continuous_mode(const struct comedi_cmd *cmd)
928 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
931 if (cmd->scan_begin_src == TRIG_FOLLOW)
937 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd)
939 if (cmd->convert_src != TRIG_TIMER)
942 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
943 cmd->scan_begin_src == TRIG_TIMER)
944 return cmd->scan_begin_arg;
946 return cmd->convert_arg;
949 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns)
951 if (cmd->convert_src != TRIG_TIMER)
954 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
955 cmd->scan_begin_src == TRIG_TIMER) {
956 cmd->scan_begin_arg = ns;
957 if (cmd->convert_arg > cmd->scan_begin_arg)
958 cmd->convert_arg = cmd->scan_begin_arg;
960 cmd->convert_arg = ns;
963 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd)
965 if (cmd->scan_begin_src != TRIG_TIMER)
968 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
969 cmd->convert_src == TRIG_TIMER)
972 return cmd->scan_begin_arg;
975 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns)
977 if (cmd->scan_begin_src != TRIG_TIMER)
980 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
981 cmd->convert_src == TRIG_TIMER)
984 cmd->scan_begin_arg = ns;
987 static int labpc_ai_cmdtest(struct comedi_device *dev,
988 struct comedi_subdevice *s, struct comedi_cmd *cmd)
994 /* step 1: make sure trigger sources are trivially valid */
996 tmp = cmd->start_src;
997 cmd->start_src &= TRIG_NOW | TRIG_EXT;
998 if (!cmd->start_src || tmp != cmd->start_src)
1001 tmp = cmd->scan_begin_src;
1002 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
1003 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1006 tmp = cmd->convert_src;
1007 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1008 if (!cmd->convert_src || tmp != cmd->convert_src)
1011 tmp = cmd->scan_end_src;
1012 cmd->scan_end_src &= TRIG_COUNT;
1013 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1016 tmp = cmd->stop_src;
1017 stop_mask = TRIG_COUNT | TRIG_NONE;
1018 if (thisboard->register_layout == labpc_1200_layout)
1019 stop_mask |= TRIG_EXT;
1020 cmd->stop_src &= stop_mask;
1021 if (!cmd->stop_src || tmp != cmd->stop_src)
1027 /* step 2: make sure trigger sources are unique and mutually compatible */
1029 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
1031 if (cmd->scan_begin_src != TRIG_TIMER &&
1032 cmd->scan_begin_src != TRIG_FOLLOW &&
1033 cmd->scan_begin_src != TRIG_EXT)
1035 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1037 if (cmd->stop_src != TRIG_COUNT &&
1038 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
1041 /* can't have external stop and start triggers at once */
1042 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1048 /* step 3: make sure arguments are trivially compatible */
1050 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
1055 if (!cmd->chanlist_len)
1058 if (cmd->scan_end_arg != cmd->chanlist_len) {
1059 cmd->scan_end_arg = cmd->chanlist_len;
1063 if (cmd->convert_src == TRIG_TIMER) {
1064 if (cmd->convert_arg < thisboard->ai_speed) {
1065 cmd->convert_arg = thisboard->ai_speed;
1069 /* make sure scan timing is not too fast */
1070 if (cmd->scan_begin_src == TRIG_TIMER) {
1071 if (cmd->convert_src == TRIG_TIMER &&
1072 cmd->scan_begin_arg <
1073 cmd->convert_arg * cmd->chanlist_len) {
1074 cmd->scan_begin_arg =
1075 cmd->convert_arg * cmd->chanlist_len;
1078 if (cmd->scan_begin_arg <
1079 thisboard->ai_speed * cmd->chanlist_len) {
1080 cmd->scan_begin_arg =
1081 thisboard->ai_speed * cmd->chanlist_len;
1086 switch (cmd->stop_src) {
1088 if (!cmd->stop_arg) {
1094 if (cmd->stop_arg != 0) {
1099 /* TRIG_EXT doesn't care since it doesn't trigger off a numbered channel */
1107 /* step 4: fix up any arguments */
1109 tmp = cmd->convert_arg;
1110 tmp2 = cmd->scan_begin_arg;
1111 labpc_adc_timing(dev, cmd);
1112 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1118 if (labpc_ai_chanlist_invalid(dev, cmd))
1124 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1126 int channel, range, aref;
1127 unsigned long irq_flags;
1129 struct comedi_async *async = s->async;
1130 struct comedi_cmd *cmd = &async->cmd;
1131 enum transfer_type xfer;
1132 unsigned long flags;
1135 comedi_error(dev, "no irq assigned, cannot perform command");
1139 range = CR_RANGE(cmd->chanlist[0]);
1140 aref = CR_AREF(cmd->chanlist[0]);
1142 /* make sure board is disabled before setting up aquisition */
1143 spin_lock_irqsave(&dev->spinlock, flags);
1144 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1145 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1146 spin_unlock_irqrestore(&dev->spinlock, flags);
1148 devpriv->command3_bits = 0;
1149 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1151 /* initialize software conversion count */
1152 if (cmd->stop_src == TRIG_COUNT)
1153 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1155 /* setup hardware conversion counter */
1156 if (cmd->stop_src == TRIG_EXT) {
1157 /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */
1158 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1161 comedi_error(dev, "error loading counter a1");
1164 } else /* otherwise, just put a1 in mode 0 with no count to set its output low */
1165 devpriv->write_byte(INIT_A1_BITS,
1166 dev->iobase + COUNTER_A_CONTROL_REG);
1168 /* figure out what method we will use to transfer data */
1169 if (devpriv->dma_chan && /* need a dma channel allocated */
1170 /* dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for */
1171 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1172 /* only available on the isa boards */
1173 thisboard->bustype == isa_bustype) {
1174 xfer = isa_dma_transfer;
1175 } else if (thisboard->register_layout == labpc_1200_layout && /* pc-plus has no fifo-half full interrupt */
1176 /* wake-end-of-scan should interrupt on fifo not empty */
1177 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1178 /* make sure we are taking more than just a few points */
1179 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1180 xfer = fifo_half_full_transfer;
1182 xfer = fifo_not_empty_transfer;
1183 devpriv->current_transfer = xfer;
1185 /* setup command6 register for 1200 boards */
1186 if (thisboard->register_layout == labpc_1200_layout) {
1187 /* reference inputs to ground or common? */
1188 if (aref != AREF_GROUND)
1189 devpriv->command6_bits |= ADC_COMMON_BIT;
1191 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1192 /* bipolar or unipolar range? */
1193 if (thisboard->ai_range_is_unipolar[range])
1194 devpriv->command6_bits |= ADC_UNIP_BIT;
1196 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1197 /* interrupt on fifo half full? */
1198 if (xfer == fifo_half_full_transfer)
1199 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1201 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1202 /* enable interrupt on counter a1 terminal count? */
1203 if (cmd->stop_src == TRIG_EXT)
1204 devpriv->command6_bits |= A1_INTR_EN_BIT;
1206 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1207 /* are we scanning up or down through channels? */
1208 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1209 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1211 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1212 /* write to register */
1213 devpriv->write_byte(devpriv->command6_bits,
1214 dev->iobase + COMMAND6_REG);
1217 /* setup channel list, etc (command1 register) */
1218 devpriv->command1_bits = 0;
1219 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1220 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1222 channel = CR_CHAN(cmd->chanlist[0]);
1223 /* munge channel bits for differential / scan disabled mode */
1224 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1226 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1227 devpriv->command1_bits |= thisboard->ai_range_code[range];
1228 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1229 /* manual says to set scan enable bit on second pass */
1230 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
1231 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
1232 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1233 /* need a brief delay before enabling scan, or scan
1234 * list will get screwed when you switch
1235 * between scan up to scan down mode - dunno why */
1237 devpriv->write_byte(devpriv->command1_bits,
1238 dev->iobase + COMMAND1_REG);
1240 /* setup any external triggering/pacing (command4 register) */
1241 devpriv->command4_bits = 0;
1242 if (cmd->convert_src != TRIG_EXT)
1243 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1244 /* XXX should discard first scan when using interval scanning
1245 * since manual says it is not synced with scan clock */
1246 if (labpc_use_continuous_mode(cmd) == 0) {
1247 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1248 if (cmd->scan_begin_src == TRIG_EXT)
1249 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1251 /* single-ended/differential */
1252 if (aref == AREF_DIFF)
1253 devpriv->command4_bits |= ADC_DIFF_BIT;
1254 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1256 devpriv->write_byte(cmd->chanlist_len,
1257 dev->iobase + INTERVAL_COUNT_REG);
1259 devpriv->write_byte(INTERVAL_LOAD_BITS,
1260 dev->iobase + INTERVAL_LOAD_REG);
1262 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1264 labpc_adc_timing(dev, cmd);
1265 /* load counter b0 in mode 3 */
1266 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1267 0, devpriv->divisor_b0, 3);
1269 comedi_error(dev, "error loading counter b0");
1273 /* set up conversion pacing */
1274 if (labpc_ai_convert_period(cmd)) {
1275 /* load counter a0 in mode 2 */
1276 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1277 0, devpriv->divisor_a0, 2);
1279 comedi_error(dev, "error loading counter a0");
1283 devpriv->write_byte(INIT_A0_BITS,
1284 dev->iobase + COUNTER_A_CONTROL_REG);
1286 /* set up scan pacing */
1287 if (labpc_ai_scan_period(cmd)) {
1288 /* load counter b1 in mode 2 */
1289 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1290 1, devpriv->divisor_b1, 2);
1292 comedi_error(dev, "error loading counter b1");
1297 labpc_clear_adc_fifo(dev);
1299 /* set up dma transfer */
1300 if (xfer == isa_dma_transfer) {
1301 irq_flags = claim_dma_lock();
1302 disable_dma(devpriv->dma_chan);
1303 /* clear flip-flop to make sure 2-byte registers for
1304 * count and address get set correctly */
1305 clear_dma_ff(devpriv->dma_chan);
1306 set_dma_addr(devpriv->dma_chan,
1307 virt_to_bus(devpriv->dma_buffer));
1308 /* set appropriate size of transfer */
1309 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1310 if (cmd->stop_src == TRIG_COUNT &&
1311 devpriv->count * sample_size < devpriv->dma_transfer_size) {
1312 devpriv->dma_transfer_size =
1313 devpriv->count * sample_size;
1315 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1316 enable_dma(devpriv->dma_chan);
1317 release_dma_lock(irq_flags);
1318 /* enable board's dma */
1319 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1321 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1323 /* enable error interrupts */
1324 devpriv->command3_bits |= ERR_INTR_EN_BIT;
1325 /* enable fifo not empty interrupt? */
1326 if (xfer == fifo_not_empty_transfer)
1327 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1329 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1330 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1332 /* startup aquisition */
1335 /* use 2 cascaded counters for pacing */
1336 spin_lock_irqsave(&dev->spinlock, flags);
1337 devpriv->command2_bits |= CASCADE_BIT;
1338 switch (cmd->start_src) {
1340 devpriv->command2_bits |= HWTRIG_BIT;
1341 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1344 devpriv->command2_bits |= SWTRIG_BIT;
1345 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1348 comedi_error(dev, "bug with start_src");
1352 switch (cmd->stop_src) {
1354 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1360 comedi_error(dev, "bug with stop_src");
1363 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1364 spin_unlock_irqrestore(&dev->spinlock, flags);
1369 /* interrupt service routine */
1370 static irqreturn_t labpc_interrupt(int irq, void *d)
1372 struct comedi_device *dev = d;
1373 struct comedi_subdevice *s = dev->read_subdev;
1374 struct comedi_async *async;
1375 struct comedi_cmd *cmd;
1377 if (dev->attached == 0) {
1378 comedi_error(dev, "premature interrupt");
1386 /* read board status */
1387 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1388 if (thisboard->register_layout == labpc_1200_layout)
1389 devpriv->status2_bits =
1390 devpriv->read_byte(dev->iobase + STATUS2_REG);
1392 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1393 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1394 && (devpriv->status2_bits & A1_TC_BIT) == 0
1395 && (devpriv->status2_bits & FNHF_BIT)) {
1399 if (devpriv->status1_bits & OVERRUN_BIT) {
1400 /* clear error interrupt */
1401 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1402 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1403 comedi_event(dev, s);
1404 comedi_error(dev, "overrun");
1408 if (devpriv->current_transfer == isa_dma_transfer) {
1410 * if a dma terminal count of external stop trigger
1413 if (devpriv->status1_bits & DMATC_BIT ||
1414 (thisboard->register_layout == labpc_1200_layout
1415 && devpriv->status2_bits & A1_TC_BIT)) {
1416 handle_isa_dma(dev);
1419 labpc_drain_fifo(dev);
1421 if (devpriv->status1_bits & TIMER_BIT) {
1422 comedi_error(dev, "handled timer interrupt?");
1424 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1427 if (devpriv->status1_bits & OVERFLOW_BIT) {
1428 /* clear error interrupt */
1429 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1430 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1431 comedi_event(dev, s);
1432 comedi_error(dev, "overflow");
1435 /* handle external stop trigger */
1436 if (cmd->stop_src == TRIG_EXT) {
1437 if (devpriv->status2_bits & A1_TC_BIT) {
1438 labpc_drain_dregs(dev);
1439 labpc_cancel(dev, s);
1440 async->events |= COMEDI_CB_EOA;
1444 /* TRIG_COUNT end of acquisition */
1445 if (cmd->stop_src == TRIG_COUNT) {
1446 if (devpriv->count == 0) {
1447 labpc_cancel(dev, s);
1448 async->events |= COMEDI_CB_EOA;
1452 comedi_event(dev, s);
1456 /* read all available samples from ai fifo */
1457 static int labpc_drain_fifo(struct comedi_device *dev)
1459 unsigned int lsb, msb;
1461 struct comedi_async *async = dev->read_subdev->async;
1462 const int timeout = 10000;
1465 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1467 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1469 /* quit if we have all the data we want */
1470 if (async->cmd.stop_src == TRIG_COUNT) {
1471 if (devpriv->count == 0)
1475 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1476 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1477 data = (msb << 8) | lsb;
1478 cfc_write_to_buffer(dev->read_subdev, data);
1479 devpriv->status1_bits =
1480 devpriv->read_byte(dev->iobase + STATUS1_REG);
1483 comedi_error(dev, "ai timeout, fifo never empties");
1484 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1491 static void labpc_drain_dma(struct comedi_device *dev)
1493 struct comedi_subdevice *s = dev->read_subdev;
1494 struct comedi_async *async = s->async;
1496 unsigned long flags;
1497 unsigned int max_points, num_points, residue, leftover;
1500 status = devpriv->status1_bits;
1502 flags = claim_dma_lock();
1503 disable_dma(devpriv->dma_chan);
1504 /* clear flip-flop to make sure 2-byte registers for
1505 * count and address get set correctly */
1506 clear_dma_ff(devpriv->dma_chan);
1508 /* figure out how many points to read */
1509 max_points = devpriv->dma_transfer_size / sample_size;
1510 /* residue is the number of points left to be done on the dma
1511 * transfer. It should always be zero at this point unless
1512 * the stop_src is set to external triggering.
1514 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1515 num_points = max_points - residue;
1516 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1517 num_points = devpriv->count;
1519 /* figure out how many points will be stored next time */
1521 if (async->cmd.stop_src != TRIG_COUNT) {
1522 leftover = devpriv->dma_transfer_size / sample_size;
1523 } else if (devpriv->count > num_points) {
1524 leftover = devpriv->count - num_points;
1525 if (leftover > max_points)
1526 leftover = max_points;
1529 /* write data to comedi buffer */
1530 for (i = 0; i < num_points; i++)
1531 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1533 if (async->cmd.stop_src == TRIG_COUNT)
1534 devpriv->count -= num_points;
1536 /* set address and count for next transfer */
1537 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1538 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1539 release_dma_lock(flags);
1541 async->events |= COMEDI_CB_BLOCK;
1544 static void handle_isa_dma(struct comedi_device *dev)
1546 labpc_drain_dma(dev);
1548 enable_dma(devpriv->dma_chan);
1550 /* clear dma tc interrupt */
1551 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1554 /* makes sure all data acquired by board is transfered to comedi (used
1555 * when aquisition is terminated by stop_src == TRIG_EXT). */
1556 static void labpc_drain_dregs(struct comedi_device *dev)
1558 if (devpriv->current_transfer == isa_dma_transfer)
1559 labpc_drain_dma(dev);
1561 labpc_drain_fifo(dev);
1564 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1565 struct comedi_insn *insn, unsigned int *data)
1571 unsigned long flags;
1573 /* disable timed conversions */
1574 spin_lock_irqsave(&dev->spinlock, flags);
1575 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1576 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1577 spin_unlock_irqrestore(&dev->spinlock, flags);
1579 /* disable interrupt generation and dma */
1580 devpriv->command3_bits = 0;
1581 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1583 /* set gain and channel */
1584 devpriv->command1_bits = 0;
1585 chan = CR_CHAN(insn->chanspec);
1586 range = CR_RANGE(insn->chanspec);
1587 devpriv->command1_bits |= thisboard->ai_range_code[range];
1588 /* munge channel bits for differential/scan disabled mode */
1589 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1591 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1592 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1594 /* setup command6 register for 1200 boards */
1595 if (thisboard->register_layout == labpc_1200_layout) {
1596 /* reference inputs to ground or common? */
1597 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1598 devpriv->command6_bits |= ADC_COMMON_BIT;
1600 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1601 /* bipolar or unipolar range? */
1602 if (thisboard->ai_range_is_unipolar[range])
1603 devpriv->command6_bits |= ADC_UNIP_BIT;
1605 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1606 /* don't interrupt on fifo half full */
1607 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1608 /* don't enable interrupt on counter a1 terminal count? */
1609 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1610 /* write to register */
1611 devpriv->write_byte(devpriv->command6_bits,
1612 dev->iobase + COMMAND6_REG);
1614 /* setup command4 register */
1615 devpriv->command4_bits = 0;
1616 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1617 /* single-ended/differential */
1618 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1619 devpriv->command4_bits |= ADC_DIFF_BIT;
1620 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1622 /* initialize pacer counter output to make sure it doesn't cause any problems */
1623 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1625 labpc_clear_adc_fifo(dev);
1627 for (n = 0; n < insn->n; n++) {
1628 /* trigger conversion */
1629 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1631 for (i = 0; i < timeout; i++) {
1632 if (devpriv->read_byte(dev->iobase +
1633 STATUS1_REG) & DATA_AVAIL_BIT)
1638 comedi_error(dev, "timeout");
1641 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1642 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1643 data[n] = (msb << 8) | lsb;
1649 /* analog output insn */
1650 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1651 struct comedi_insn *insn, unsigned int *data)
1654 unsigned long flags;
1657 channel = CR_CHAN(insn->chanspec);
1659 /* turn off pacing of analog output channel */
1660 /* note: hardware bug in daqcard-1200 means pacing cannot
1661 * be independently enabled/disabled for its the two channels */
1662 spin_lock_irqsave(&dev->spinlock, flags);
1663 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1664 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1665 spin_unlock_irqrestore(&dev->spinlock, flags);
1668 if (thisboard->register_layout == labpc_1200_layout) {
1669 range = CR_RANGE(insn->chanspec);
1670 if (range & AO_RANGE_IS_UNIPOLAR)
1671 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1673 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1674 /* write to register */
1675 devpriv->write_byte(devpriv->command6_bits,
1676 dev->iobase + COMMAND6_REG);
1679 lsb = data[0] & 0xff;
1680 msb = (data[0] >> 8) & 0xff;
1681 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1682 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1684 /* remember value for readback */
1685 devpriv->ao_value[channel] = data[0];
1690 /* analog output readback insn */
1691 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1692 struct comedi_insn *insn, unsigned int *data)
1694 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1699 static int labpc_calib_read_insn(struct comedi_device *dev,
1700 struct comedi_subdevice *s,
1701 struct comedi_insn *insn, unsigned int *data)
1703 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1708 static int labpc_calib_write_insn(struct comedi_device *dev,
1709 struct comedi_subdevice *s,
1710 struct comedi_insn *insn, unsigned int *data)
1712 int channel = CR_CHAN(insn->chanspec);
1714 write_caldac(dev, channel, data[0]);
1718 static int labpc_eeprom_read_insn(struct comedi_device *dev,
1719 struct comedi_subdevice *s,
1720 struct comedi_insn *insn, unsigned int *data)
1722 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1727 static int labpc_eeprom_write_insn(struct comedi_device *dev,
1728 struct comedi_subdevice *s,
1729 struct comedi_insn *insn, unsigned int *data)
1731 int channel = CR_CHAN(insn->chanspec);
1734 /* only allow writes to user area of eeprom */
1735 if (channel < 16 || channel > 127) {
1737 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)");
1741 ret = labpc_eeprom_write(dev, channel, data[0]);
1748 /* utility function that suggests a dma transfer size in bytes */
1749 static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd)
1754 if (cmd.convert_src == TRIG_TIMER)
1755 freq = 1000000000 / cmd.convert_arg;
1756 /* return some default value */
1760 /* make buffer fill in no more than 1/3 second */
1761 size = (freq / 3) * sample_size;
1763 /* set a minimum and maximum size allowed */
1764 if (size > dma_buffer_size)
1765 size = dma_buffer_size - dma_buffer_size % sample_size;
1766 else if (size < sample_size)
1772 /* figures out what counter values to use based on command */
1773 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1775 /* max value for 16 bit counter in mode 2 */
1776 const int max_counter_value = 0x10000;
1777 /* min value for 16 bit counter in mode 2 */
1778 const int min_counter_value = 2;
1779 unsigned int base_period;
1782 * if both convert and scan triggers are TRIG_TIMER, then they
1783 * both rely on counter b0
1785 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
1787 * pick the lowest b0 divisor value we can (for maximum input
1788 * clock speed on convert and scan counters)
1790 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
1791 (LABPC_TIMER_BASE * max_counter_value) + 1;
1792 if (devpriv->divisor_b0 < min_counter_value)
1793 devpriv->divisor_b0 = min_counter_value;
1794 if (devpriv->divisor_b0 > max_counter_value)
1795 devpriv->divisor_b0 = max_counter_value;
1797 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1799 /* set a0 for conversion frequency and b1 for scan frequency */
1800 switch (cmd->flags & TRIG_ROUND_MASK) {
1802 case TRIG_ROUND_NEAREST:
1803 devpriv->divisor_a0 =
1804 (labpc_ai_convert_period(cmd) +
1805 (base_period / 2)) / base_period;
1806 devpriv->divisor_b1 =
1807 (labpc_ai_scan_period(cmd) +
1808 (base_period / 2)) / base_period;
1811 devpriv->divisor_a0 =
1812 (labpc_ai_convert_period(cmd) + (base_period -
1814 devpriv->divisor_b1 =
1815 (labpc_ai_scan_period(cmd) + (base_period -
1818 case TRIG_ROUND_DOWN:
1819 devpriv->divisor_a0 =
1820 labpc_ai_convert_period(cmd) / base_period;
1821 devpriv->divisor_b1 =
1822 labpc_ai_scan_period(cmd) / base_period;
1825 /* make sure a0 and b1 values are acceptable */
1826 if (devpriv->divisor_a0 < min_counter_value)
1827 devpriv->divisor_a0 = min_counter_value;
1828 if (devpriv->divisor_a0 > max_counter_value)
1829 devpriv->divisor_a0 = max_counter_value;
1830 if (devpriv->divisor_b1 < min_counter_value)
1831 devpriv->divisor_b1 = min_counter_value;
1832 if (devpriv->divisor_b1 > max_counter_value)
1833 devpriv->divisor_b1 = max_counter_value;
1834 /* write corrected timings to command */
1835 labpc_set_ai_convert_period(cmd,
1836 base_period * devpriv->divisor_a0);
1837 labpc_set_ai_scan_period(cmd,
1838 base_period * devpriv->divisor_b1);
1840 * if only one TRIG_TIMER is used, we can employ the generic
1841 * cascaded timing functions
1843 } else if (labpc_ai_scan_period(cmd)) {
1844 unsigned int scan_period;
1846 scan_period = labpc_ai_scan_period(cmd);
1847 /* calculate cascaded counter values that give desired scan timing */
1848 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1849 &(devpriv->divisor_b1),
1850 &(devpriv->divisor_b0),
1852 cmd->flags & TRIG_ROUND_MASK);
1853 labpc_set_ai_scan_period(cmd, scan_period);
1854 } else if (labpc_ai_convert_period(cmd)) {
1855 unsigned int convert_period;
1857 convert_period = labpc_ai_convert_period(cmd);
1858 /* calculate cascaded counter values that give desired conversion timing */
1859 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1860 &(devpriv->divisor_a0),
1861 &(devpriv->divisor_b0),
1863 cmd->flags & TRIG_ROUND_MASK);
1864 labpc_set_ai_convert_period(cmd, convert_period);
1868 static int labpc_dio_mem_callback(int dir, int port, int data,
1869 unsigned long iobase)
1872 writeb(data, (void *)(iobase + port));
1875 return readb((void *)(iobase + port));
1879 /* lowlevel write to eeprom/dac */
1880 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1881 unsigned int value_width)
1885 for (i = 1; i <= value_width; i++) {
1886 /* clear serial clock */
1887 devpriv->command5_bits &= ~SCLOCK_BIT;
1888 /* send bits most significant bit first */
1889 if (value & (1 << (value_width - i)))
1890 devpriv->command5_bits |= SDATA_BIT;
1892 devpriv->command5_bits &= ~SDATA_BIT;
1894 devpriv->write_byte(devpriv->command5_bits,
1895 dev->iobase + COMMAND5_REG);
1896 /* set clock to load bit */
1897 devpriv->command5_bits |= SCLOCK_BIT;
1899 devpriv->write_byte(devpriv->command5_bits,
1900 dev->iobase + COMMAND5_REG);
1904 /* lowlevel read from eeprom */
1905 static unsigned int labpc_serial_in(struct comedi_device *dev)
1907 unsigned int value = 0;
1909 const int value_width = 8; /* number of bits wide values are */
1911 for (i = 1; i <= value_width; i++) {
1912 /* set serial clock */
1913 devpriv->command5_bits |= SCLOCK_BIT;
1915 devpriv->write_byte(devpriv->command5_bits,
1916 dev->iobase + COMMAND5_REG);
1917 /* clear clock bit */
1918 devpriv->command5_bits &= ~SCLOCK_BIT;
1920 devpriv->write_byte(devpriv->command5_bits,
1921 dev->iobase + COMMAND5_REG);
1922 /* read bits most significant bit first */
1924 devpriv->status2_bits =
1925 devpriv->read_byte(dev->iobase + STATUS2_REG);
1926 if (devpriv->status2_bits & EEPROM_OUT_BIT)
1927 value |= 1 << (value_width - i);
1933 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1934 unsigned int address)
1937 /* bits to tell eeprom to expect a read */
1938 const int read_instruction = 0x3;
1939 /* 8 bit write lengths to eeprom */
1940 const int write_length = 8;
1942 /* enable read/write to eeprom */
1943 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1945 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1946 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1948 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1950 /* send read instruction */
1951 labpc_serial_out(dev, read_instruction, write_length);
1952 /* send 8 bit address to read from */
1953 labpc_serial_out(dev, address, write_length);
1955 value = labpc_serial_in(dev);
1957 /* disable read/write to eeprom */
1958 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1960 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1965 static unsigned int labpc_eeprom_write(struct comedi_device *dev,
1966 unsigned int address, unsigned int value)
1968 const int write_enable_instruction = 0x6;
1969 const int write_instruction = 0x2;
1970 const int write_length = 8; /* 8 bit write lengths to eeprom */
1971 const int write_in_progress_bit = 0x1;
1972 const int timeout = 10000;
1975 /* make sure there isn't already a write in progress */
1976 for (i = 0; i < timeout; i++) {
1977 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1982 comedi_error(dev, "eeprom write timed out");
1985 /* update software copy of eeprom */
1986 devpriv->eeprom_data[address] = value;
1988 /* enable read/write to eeprom */
1989 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1991 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1992 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1994 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1996 /* send write_enable instruction */
1997 labpc_serial_out(dev, write_enable_instruction, write_length);
1998 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2000 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2002 /* send write instruction */
2003 devpriv->command5_bits |= EEPROM_EN_BIT;
2005 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2006 labpc_serial_out(dev, write_instruction, write_length);
2007 /* send 8 bit address to write to */
2008 labpc_serial_out(dev, address, write_length);
2010 labpc_serial_out(dev, value, write_length);
2011 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2013 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2015 /* disable read/write to eeprom */
2016 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2018 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2023 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
2026 const int read_status_instruction = 0x5;
2027 const int write_length = 8; /* 8 bit write lengths to eeprom */
2029 /* enable read/write to eeprom */
2030 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2032 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2033 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2035 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2037 /* send read status instruction */
2038 labpc_serial_out(dev, read_status_instruction, write_length);
2040 value = labpc_serial_in(dev);
2042 /* disable read/write to eeprom */
2043 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2045 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2050 /* writes to 8 bit calibration dacs */
2051 static void write_caldac(struct comedi_device *dev, unsigned int channel,
2054 if (value == devpriv->caldac[channel])
2056 devpriv->caldac[channel] = value;
2058 /* clear caldac load bit and make sure we don't write to eeprom */
2059 devpriv->command5_bits &=
2060 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2062 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2064 /* write 4 bit channel */
2065 labpc_serial_out(dev, channel, 4);
2066 /* write 8 bit caldac value */
2067 labpc_serial_out(dev, value, 8);
2069 /* set and clear caldac bit to load caldac value */
2070 devpriv->command5_bits |= CALDAC_LOAD_BIT;
2072 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2073 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
2075 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2078 #ifdef CONFIG_COMEDI_PCI
2079 COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table);
2081 COMEDI_INITCLEANUP(driver_labpc);
2084 EXPORT_SYMBOL_GPL(labpc_common_attach);
2085 EXPORT_SYMBOL_GPL(labpc_common_detach);
2086 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
2087 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
2088 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);