drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60
  61 /* A timeout count */
  62 #define NI_TIMEOUT 1000
  63
  64 /* Note: this table must match the ai_gain_* definitions */
  65 static const short ni_gainlkup[][16] = {
  66         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  67                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  68         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  69         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  70                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  71         [ai_gain_4] = {0, 1, 4, 7},
  72         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  73                           0x003, 0x004, 0x005, 0x006},
  74         [ai_gain_622x] = {0, 1, 4, 5},
  75         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  76         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  77 };
  78
  79 static const struct comedi_lrange range_ni_E_ai = {
  80         16, {
  81                 BIP_RANGE(10),
  82                 BIP_RANGE(5),
  83                 BIP_RANGE(2.5),
  84                 BIP_RANGE(1),
  85                 BIP_RANGE(0.5),
  86                 BIP_RANGE(0.25),
  87                 BIP_RANGE(0.1),
  88                 BIP_RANGE(0.05),
  89                 UNI_RANGE(20),
  90                 UNI_RANGE(10),
  91                 UNI_RANGE(5),
  92                 UNI_RANGE(2),
  93                 UNI_RANGE(1),
  94                 UNI_RANGE(0.5),
  95                 UNI_RANGE(0.2),
  96                 UNI_RANGE(0.1)
  97         }
  98 };
  99
 100 static const struct comedi_lrange range_ni_E_ai_limited = {
 101         8, {
 102                 BIP_RANGE(10),
 103                 BIP_RANGE(5),
 104                 BIP_RANGE(1),
 105                 BIP_RANGE(0.1),
 106                 UNI_RANGE(10),
 107                 UNI_RANGE(5),
 108                 UNI_RANGE(1),
 109                 UNI_RANGE(0.1)
 110         }
 111 };
 112
 113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 114         14, {
 115                 BIP_RANGE(10),
 116                 BIP_RANGE(5),
 117                 BIP_RANGE(2),
 118                 BIP_RANGE(1),
 119                 BIP_RANGE(0.5),
 120                 BIP_RANGE(0.2),
 121                 BIP_RANGE(0.1),
 122                 UNI_RANGE(10),
 123                 UNI_RANGE(5),
 124                 UNI_RANGE(2),
 125                 UNI_RANGE(1),
 126                 UNI_RANGE(0.5),
 127                 UNI_RANGE(0.2),
 128                 UNI_RANGE(0.1)
 129         }
 130 };
 131
 132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 133         4, {
 134                 BIP_RANGE(10),
 135                 BIP_RANGE(5),
 136                 BIP_RANGE(0.5),
 137                 BIP_RANGE(0.05)
 138         }
 139 };
 140
 141 static const struct comedi_lrange range_ni_E_ai_611x = {
 142         8, {
 143                 BIP_RANGE(50),
 144                 BIP_RANGE(20),
 145                 BIP_RANGE(10),
 146                 BIP_RANGE(5),
 147                 BIP_RANGE(2),
 148                 BIP_RANGE(1),
 149                 BIP_RANGE(0.5),
 150                 BIP_RANGE(0.2)
 151         }
 152 };
 153
 154 static const struct comedi_lrange range_ni_M_ai_622x = {
 155         4, {
 156                 BIP_RANGE(10),
 157                 BIP_RANGE(5),
 158                 BIP_RANGE(1),
 159                 BIP_RANGE(0.2)
 160         }
 161 };
 162
 163 static const struct comedi_lrange range_ni_M_ai_628x = {
 164         7, {
 165                 BIP_RANGE(10),
 166                 BIP_RANGE(5),
 167                 BIP_RANGE(2),
 168                 BIP_RANGE(1),
 169                 BIP_RANGE(0.5),
 170                 BIP_RANGE(0.2),
 171                 BIP_RANGE(0.1)
 172         }
 173 };
 174
 175 static const struct comedi_lrange range_ni_E_ao_ext = {
 176         4, {
 177                 BIP_RANGE(10),
 178                 UNI_RANGE(10),
 179                 RANGE_ext(-1, 1),
 180                 RANGE_ext(0, 1)
 181         }
 182 };
 183
 184 static const struct comedi_lrange *const ni_range_lkup[] = {
 185         [ai_gain_16] = &range_ni_E_ai,
 186         [ai_gain_8] = &range_ni_E_ai_limited,
 187         [ai_gain_14] = &range_ni_E_ai_limited14,
 188         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 189         [ai_gain_611x] = &range_ni_E_ai_611x,
 190         [ai_gain_622x] = &range_ni_M_ai_622x,
 191         [ai_gain_628x] = &range_ni_M_ai_628x,
 192         [ai_gain_6143] = &range_bipolar5
 193 };
 194
 195 enum aimodes {
 196         AIMODE_NONE = 0,
 197         AIMODE_HALF_FULL = 1,
 198         AIMODE_SCAN = 2,
 199         AIMODE_SAMPLE = 3,
 200 };
 201
 202 enum ni_common_subdevices {
 203         NI_AI_SUBDEV,
 204         NI_AO_SUBDEV,
 205         NI_DIO_SUBDEV,
 206         NI_8255_DIO_SUBDEV,
 207         NI_UNUSED_SUBDEV,
 208         NI_CALIBRATION_SUBDEV,
 209         NI_EEPROM_SUBDEV,
 210         NI_PFI_DIO_SUBDEV,
 211         NI_CS5529_CALIBRATION_SUBDEV,
 212         NI_SERIAL_SUBDEV,
 213         NI_RTSI_SUBDEV,
 214         NI_GPCT0_SUBDEV,
 215         NI_GPCT1_SUBDEV,
 216         NI_FREQ_OUT_SUBDEV,
 217         NI_NUM_SUBDEVICES
 218 };
 219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 220 {
 221         switch (counter_index) {
 222         case 0:
 223                 return NI_GPCT0_SUBDEV;
 224         case 1:
 225                 return NI_GPCT1_SUBDEV;
 226         default:
 227                 break;
 228         }
 229         BUG();
 230         return NI_GPCT0_SUBDEV;
 231 }
 232
 233 enum timebase_nanoseconds {
 234         TIMEBASE_1_NS = 50,
 235         TIMEBASE_2_NS = 10000
 236 };
 237
 238 #define SERIAL_DISABLED         0
 239 #define SERIAL_600NS            600
 240 #define SERIAL_1_2US            1200
 241 #define SERIAL_10US                     10000
 242
 243 static const int num_adc_stages_611x = 3;
 244
 245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
 246 {
 247         if (dev->mmio)
 248                 writel(data, dev->mmio + reg);
 249
 250         outl(data, dev->iobase + reg);
 251 }
 252
 253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
 254 {
 255         if (dev->mmio)
 256                 writew(data, dev->mmio + reg);
 257
 258         outw(data, dev->iobase + reg);
 259 }
 260
 261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
 262 {
 263         if (dev->mmio)
 264                 writeb(data, dev->mmio + reg);
 265
 266         outb(data, dev->iobase + reg);
 267 }
 268
 269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
 270 {
 271         if (dev->mmio)
 272                 return readl(dev->mmio + reg);
 273
 274         return inl(dev->iobase + reg);
 275 }
 276
 277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
 278 {
 279         if (dev->mmio)
 280                 return readw(dev->mmio + reg);
 281
 282         return inw(dev->iobase + reg);
 283 }
 284
 285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
 286 {
 287         if (dev->mmio)
 288                 return readb(dev->mmio + reg);
 289
 290         return inb(dev->iobase + reg);
 291 }
 292
 293 /*
 294  * We automatically take advantage of STC registers that can be
 295  * read/written directly in the I/O space of the board.
 296  *
 297  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 298  * iobase+reg*2.
 299  *
 300  * Most PCIMIO devices also map the low 8 STC registers but the
 301  * 611x devices map the read registers to iobase+(addr-1)*2.
 302  * For now non-windowed STC access is disabled if a PCIMIO device
 303  * is detected (devpriv->mite has been initialized).
 304  *
 305  * The M series devices do not used windowed registers for the
 306  * STC registers. The functions below handle the mapping of the
 307  * windowed STC registers to the m series register offsets.
 308  */
 309
 310 struct mio_regmap {
 311         unsigned int mio_reg;
 312         int size;
 313 };
 314
 315 static const struct mio_regmap m_series_stc_write_regmap[] = {
 316         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 317         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 318         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 319         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 320         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 321         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 322         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 323         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 324         /*
 325          * NISTC_DIO_OUT_REG maps to:
 326          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 327          */
 328         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 329         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 330         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 331         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 332         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 333         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 334         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 335         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 336         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 337         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 338         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 339         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 340         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 341         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 342         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 343         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 344         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 345         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 346         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 347         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 348         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 349         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 350         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 351         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 352         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 353         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 354         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 355         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 356         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 357         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 358         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 359         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 360         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 361         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 362         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 363         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 364         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 365         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 366         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 367         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 368         [NISTC_RESET_REG]               = { 0x190, 2 },
 369         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 370         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 371         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 372         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 373         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 374         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 375         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 376         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 377         [NISTC_RTSI_BOARD_REG]          = { 0, 0 }, /* Unknown */
 378         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 379         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 380         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 381         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 382         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 383 };
 384
 385 static void m_series_stc_write(struct comedi_device *dev,
 386                                unsigned int data, unsigned int reg)
 387 {
 388         const struct mio_regmap *regmap;
 389
 390         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 391                 regmap = &m_series_stc_write_regmap[reg];
 392         } else {
 393                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 394                          __func__, reg);
 395                 return;
 396         }
 397
 398         switch (regmap->size) {
 399         case 4:
 400                 ni_writel(dev, data, regmap->mio_reg);
 401                 break;
 402         case 2:
 403                 ni_writew(dev, data, regmap->mio_reg);
 404                 break;
 405         default:
 406                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 407                          __func__, reg);
 408                 break;
 409         }
 410 }
 411
 412 static const struct mio_regmap m_series_stc_read_regmap[] = {
 413         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 414         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 415         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 416         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 417         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 418         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 419         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 420         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 421         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 422         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 423         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 424         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 425         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 426         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 427         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 428         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 429         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 430         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 431 };
 432
 433 static unsigned int m_series_stc_read(struct comedi_device *dev,
 434                                       unsigned int reg)
 435 {
 436         const struct mio_regmap *regmap;
 437
 438         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 439                 regmap = &m_series_stc_read_regmap[reg];
 440         } else {
 441                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 442                          __func__, reg);
 443                 return 0;
 444         }
 445
 446         switch (regmap->size) {
 447         case 4:
 448                 return ni_readl(dev, regmap->mio_reg);
 449         case 2:
 450                 return ni_readw(dev, regmap->mio_reg);
 451         case 1:
 452                 return ni_readb(dev, regmap->mio_reg);
 453         default:
 454                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 455                          __func__, reg);
 456                 return 0;
 457         }
 458 }
 459
 460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
 461 {
 462         struct ni_private *devpriv = dev->private;
 463         unsigned long flags;
 464
 465         if (devpriv->is_m_series) {
 466                 m_series_stc_write(dev, data, reg);
 467         } else {
 468                 spin_lock_irqsave(&devpriv->window_lock, flags);
 469                 if (!devpriv->mite && reg < 8) {
 470                         ni_writew(dev, data, reg * 2);
 471                 } else {
 472                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 473                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 474                 }
 475                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 476         }
 477 }
 478
 479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
 480 {
 481         struct ni_private *devpriv = dev->private;
 482
 483         if (devpriv->is_m_series) {
 484                 m_series_stc_write(dev, data, reg);
 485         } else {
 486                 ni_stc_writew(dev, data >> 16, reg);
 487                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 488         }
 489 }
 490
 491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
 492 {
 493         struct ni_private *devpriv = dev->private;
 494         unsigned long flags;
 495         uint16_t val;
 496
 497         if (devpriv->is_m_series) {
 498                 val = m_series_stc_read(dev, reg);
 499         } else {
 500                 spin_lock_irqsave(&devpriv->window_lock, flags);
 501                 if (!devpriv->mite && reg < 8) {
 502                         val = ni_readw(dev, reg * 2);
 503                 } else {
 504                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 505                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 506                 }
 507                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 508         }
 509         return val;
 510 }
 511
 512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
 513 {
 514         struct ni_private *devpriv = dev->private;
 515         uint32_t val;
 516
 517         if (devpriv->is_m_series) {
 518                 val = m_series_stc_read(dev, reg);
 519         } else {
 520                 val = ni_stc_readw(dev, reg) << 16;
 521                 val |= ni_stc_readw(dev, reg + 1);
 522         }
 523         return val;
 524 }
 525
 526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 527                                    unsigned bit_mask, unsigned bit_values)
 528 {
 529         struct ni_private *devpriv = dev->private;
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 533         switch (reg) {
 534         case NISTC_INTA_ENA_REG:
 535                 devpriv->int_a_enable_reg &= ~bit_mask;
 536                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 537                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 538                 break;
 539         case NISTC_INTB_ENA_REG:
 540                 devpriv->int_b_enable_reg &= ~bit_mask;
 541                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 542                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 543                 break;
 544         case NISTC_IO_BIDIR_PIN_REG:
 545                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 546                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 547                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 548                 break;
 549         case NI_E_DMA_AI_AO_SEL_REG:
 550                 devpriv->ai_ao_select_reg &= ~bit_mask;
 551                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 552                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 553                 break;
 554         case NI_E_DMA_G0_G1_SEL_REG:
 555                 devpriv->g0_g1_select_reg &= ~bit_mask;
 556                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 557                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 558                 break;
 559         default:
 560                 dev_err(dev->class_dev, "called with invalid register %d\n",
 561                         reg);
 562                 break;
 563         }
 564         mmiowb();
 565         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 566 }
 567
 568 #ifdef PCIDMA
 569 /* DMA channel setup */
 570 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
 571 {
 572         if (channel < 4)
 573                 return 1 << channel;
 574         if (channel == 4)
 575                 return 0x3;
 576         if (channel == 5)
 577                 return 0x5;
 578         BUG();
 579         return 0;
 580 }
 581
 582 static inline void ni_set_ai_dma_channel(struct comedi_device *dev,
 583                                          unsigned channel)
 584 {
 585         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 586
 587         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 588                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 589 }
 590
 591 static inline void ni_set_ai_dma_no_channel(struct comedi_device *dev)
 592 {
 593         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AI_SEL_MASK, 0);
 594 }
 595
 596 static inline void ni_set_ao_dma_channel(struct comedi_device *dev,
 597                                          unsigned channel)
 598 {
 599         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 600
 601         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 602                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 603 }
 604
 605 static inline void ni_set_ao_dma_no_channel(struct comedi_device *dev)
 606 {
 607         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AO_SEL_MASK, 0);
 608 }
 609
 610 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 611                                            unsigned gpct_index,
 612                                            unsigned channel)
 613 {
 614         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 615
 616         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 617                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 618                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 619 }
 620
 621 static inline void ni_set_gpct_dma_no_channel(struct comedi_device *dev,
 622                                               unsigned gpct_index)
 623 {
 624         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 625                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
 626 }
 627
 628 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 629                                           unsigned mite_channel)
 630 {
 631         struct ni_private *devpriv = dev->private;
 632         unsigned long flags;
 633         unsigned bits;
 634
 635         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 636         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 637         /*
 638          * XXX just guessing ni_stc_dma_channel_select_bitfield()
 639          * returns the right bits, under the assumption the cdio dma
 640          * selection works just like ai/ao/gpct.
 641          * Definitely works for dma channels 0 and 1.
 642          */
 643         bits = ni_stc_dma_channel_select_bitfield(mite_channel);
 644         devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
 645         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 646         mmiowb();
 647         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 648 }
 649
 650 static inline void ni_set_cdo_dma_no_channel(struct comedi_device *dev)
 651 {
 652         struct ni_private *devpriv = dev->private;
 653         unsigned long flags;
 654
 655         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 656         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 657         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 658         mmiowb();
 659         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 660 }
 661
 662 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 663 {
 664         struct ni_private *devpriv = dev->private;
 665         unsigned long flags;
 666
 667         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 668         BUG_ON(devpriv->ai_mite_chan);
 669         devpriv->ai_mite_chan =
 670             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 671         if (!devpriv->ai_mite_chan) {
 672                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 673                 dev_err(dev->class_dev,
 674                         "failed to reserve mite dma channel for analog input\n");
 675                 return -EBUSY;
 676         }
 677         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 678         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 679         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 680         return 0;
 681 }
 682
 683 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 684 {
 685         struct ni_private *devpriv = dev->private;
 686         unsigned long flags;
 687
 688         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 689         BUG_ON(devpriv->ao_mite_chan);
 690         devpriv->ao_mite_chan =
 691             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 692         if (!devpriv->ao_mite_chan) {
 693                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 694                 dev_err(dev->class_dev,
 695                         "failed to reserve mite dma channel for analog outut\n");
 696                 return -EBUSY;
 697         }
 698         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 699         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 700         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 701         return 0;
 702 }
 703
 704 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 705                                         unsigned gpct_index,
 706                                         enum comedi_io_direction direction)
 707 {
 708         struct ni_private *devpriv = dev->private;
 709         unsigned long flags;
 710         struct mite_channel *mite_chan;
 711
 712         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 713         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 714         mite_chan =
 715             mite_request_channel(devpriv->mite,
 716                                  devpriv->gpct_mite_ring[gpct_index]);
 717         if (!mite_chan) {
 718                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 719                 dev_err(dev->class_dev,
 720                         "failed to reserve mite dma channel for counter\n");
 721                 return -EBUSY;
 722         }
 723         mite_chan->dir = direction;
 724         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 725                                 mite_chan);
 726         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 727         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 728         return 0;
 729 }
 730
 731 #endif /*  PCIDMA */
 732
 733 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 734 {
 735 #ifdef PCIDMA
 736         struct ni_private *devpriv = dev->private;
 737         unsigned long flags;
 738
 739         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 740         BUG_ON(devpriv->cdo_mite_chan);
 741         devpriv->cdo_mite_chan =
 742             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 743         if (!devpriv->cdo_mite_chan) {
 744                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 745                 dev_err(dev->class_dev,
 746                         "failed to reserve mite dma channel for correlated digital output\n");
 747                 return -EBUSY;
 748         }
 749         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 750         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 751         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 752 #endif /*  PCIDMA */
 753         return 0;
 754 }
 755
 756 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 757 {
 758 #ifdef PCIDMA
 759         struct ni_private *devpriv = dev->private;
 760         unsigned long flags;
 761
 762         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 763         if (devpriv->ai_mite_chan) {
 764                 ni_set_ai_dma_no_channel(dev);
 765                 mite_release_channel(devpriv->ai_mite_chan);
 766                 devpriv->ai_mite_chan = NULL;
 767         }
 768         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 769 #endif /*  PCIDMA */
 770 }
 771
 772 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 773 {
 774 #ifdef PCIDMA
 775         struct ni_private *devpriv = dev->private;
 776         unsigned long flags;
 777
 778         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 779         if (devpriv->ao_mite_chan) {
 780                 ni_set_ao_dma_no_channel(dev);
 781                 mite_release_channel(devpriv->ao_mite_chan);
 782                 devpriv->ao_mite_chan = NULL;
 783         }
 784         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 785 #endif /*  PCIDMA */
 786 }
 787
 788 #ifdef PCIDMA
 789 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 790                                          unsigned gpct_index)
 791 {
 792         struct ni_private *devpriv = dev->private;
 793         unsigned long flags;
 794
 795         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 796         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 797                 struct mite_channel *mite_chan =
 798                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 799
 800                 ni_set_gpct_dma_no_channel(dev, gpct_index);
 801                 ni_tio_set_mite_channel(&devpriv->
 802                                         counter_dev->counters[gpct_index],
 803                                         NULL);
 804                 mite_release_channel(mite_chan);
 805         }
 806         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 807 }
 808 #endif /*  PCIDMA */
 809
 810 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 811 {
 812 #ifdef PCIDMA
 813         struct ni_private *devpriv = dev->private;
 814         unsigned long flags;
 815
 816         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 817         if (devpriv->cdo_mite_chan) {
 818                 ni_set_cdo_dma_no_channel(dev);
 819                 mite_release_channel(devpriv->cdo_mite_chan);
 820                 devpriv->cdo_mite_chan = NULL;
 821         }
 822         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 823 #endif /*  PCIDMA */
 824 }
 825
 826 #ifdef PCIDMA
 827 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 828                                           unsigned gpct_index, short enable)
 829 {
 830         struct ni_private *devpriv = dev->private;
 831         uint16_t val = 0;
 832         int reg;
 833
 834         if (devpriv->is_m_series || gpct_index > 1)
 835                 return;
 836
 837         /*
 838          * e-series boards use the second irq signals to generate
 839          * dma requests for their counters
 840          */
 841         if (gpct_index == 0) {
 842                 reg = NISTC_INTA2_ENA_REG;
 843                 if (enable)
 844                         val = NISTC_INTA_ENA_G0_GATE;
 845         } else {
 846                 reg = NISTC_INTB2_ENA_REG;
 847                 if (enable)
 848                         val = NISTC_INTB_ENA_G1_GATE;
 849         }
 850         ni_stc_writew(dev, val, reg);
 851 }
 852 #endif /*  PCIDMA */
 853
 854 static void ni_clear_ai_fifo(struct comedi_device *dev)
 855 {
 856         struct ni_private *devpriv = dev->private;
 857         static const int timeout = 10000;
 858         int i;
 859
 860         if (devpriv->is_6143) {
 861                 /*  Flush the 6143 data FIFO */
 862                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 863                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 864                 /*  Wait for complete */
 865                 for (i = 0; i < timeout; i++) {
 866                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 867                                 break;
 868                         udelay(1);
 869                 }
 870                 if (i == timeout)
 871                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 872         } else {
 873                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 874                 if (devpriv->is_625x) {
 875                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 876                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 877 #if 0
 878                         /* the NI example code does 3 convert pulses for 625x boards,
 879                            but that appears to be wrong in practice. */
 880                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 881                                       NISTC_AI_CMD1_REG);
 882                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 883                                       NISTC_AI_CMD1_REG);
 884                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 885                                       NISTC_AI_CMD1_REG);
 886 #endif
 887                 }
 888         }
 889 }
 890
 891 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 892                                   int addr)
 893 {
 894         struct ni_private *devpriv = dev->private;
 895         unsigned long flags;
 896
 897         spin_lock_irqsave(&devpriv->window_lock, flags);
 898         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 899         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 900         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 901 }
 902
 903 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 904                                   int addr)
 905 {
 906         struct ni_private *devpriv = dev->private;
 907         unsigned long flags;
 908
 909         spin_lock_irqsave(&devpriv->window_lock, flags);
 910         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 911         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 912         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 913 }
 914
 915 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 916 {
 917         struct ni_private *devpriv = dev->private;
 918         unsigned long flags;
 919         unsigned short data;
 920
 921         spin_lock_irqsave(&devpriv->window_lock, flags);
 922         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 923         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 924         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 925         return data;
 926 }
 927
 928 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 929 * share registers (such as Interrupt_A_Register) without interfering with
 930 * each other.
 931 *
 932 * NOTE: the switch/case statements are optimized out for a constant argument
 933 * so this is actually quite fast---  If you must wrap another function around this
 934 * make it inline to avoid a large speed penalty.
 935 *
 936 * value should only be 1 or 0.
 937 */
 938 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 939                                unsigned bits, unsigned value)
 940 {
 941         unsigned bit_values;
 942
 943         if (value)
 944                 bit_values = bits;
 945         else
 946                 bit_values = 0;
 947         ni_set_bitfield(dev, reg, bits, bit_values);
 948 }
 949
 950 #ifdef PCIDMA
 951 static void ni_sync_ai_dma(struct comedi_device *dev)
 952 {
 953         struct ni_private *devpriv = dev->private;
 954         struct comedi_subdevice *s = dev->read_subdev;
 955         unsigned long flags;
 956
 957         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 958         if (devpriv->ai_mite_chan)
 959                 mite_sync_input_dma(devpriv->ai_mite_chan, s);
 960         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 961 }
 962
 963 static int ni_ai_drain_dma(struct comedi_device *dev)
 964 {
 965         struct ni_private *devpriv = dev->private;
 966         int i;
 967         static const int timeout = 10000;
 968         unsigned long flags;
 969         int retval = 0;
 970
 971         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 972         if (devpriv->ai_mite_chan) {
 973                 for (i = 0; i < timeout; i++) {
 974                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 975                              NISTC_AI_STATUS1_FIFO_E)
 976                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
 977                             0)
 978                                 break;
 979                         udelay(5);
 980                 }
 981                 if (i == timeout) {
 982                         dev_err(dev->class_dev, "timed out\n");
 983                         dev_err(dev->class_dev,
 984                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 985                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 986                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 987                         retval = -1;
 988                 }
 989         }
 990         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 991
 992         ni_sync_ai_dma(dev);
 993
 994         return retval;
 995 }
 996
 997 static void mite_handle_b_linkc(struct mite_struct *mite,
 998                                 struct comedi_device *dev)
 999 {
1000         struct ni_private *devpriv = dev->private;
1001         struct comedi_subdevice *s = dev->write_subdev;
1002         unsigned long flags;
1003
1004         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1005         if (devpriv->ao_mite_chan)
1006                 mite_sync_output_dma(devpriv->ao_mite_chan, s);
1007         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1008 }
1009
1010 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
1011 {
1012         static const int timeout = 10000;
1013         int i;
1014
1015         for (i = 0; i < timeout; i++) {
1016                 unsigned short b_status;
1017
1018                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
1019                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
1020                         break;
1021                 /* if we poll too often, the pci bus activity seems
1022                    to slow the dma transfer down */
1023                 udelay(10);
1024         }
1025         if (i == timeout) {
1026                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1027                 return -EPIPE;
1028         }
1029         return 0;
1030 }
1031 #endif /* PCIDMA */
1032
1033 #ifndef PCIDMA
1034
1035 static void ni_ao_fifo_load(struct comedi_device *dev,
1036                             struct comedi_subdevice *s, int n)
1037 {
1038         struct ni_private *devpriv = dev->private;
1039         int i;
1040         unsigned short d;
1041         u32 packed_data;
1042
1043         for (i = 0; i < n; i++) {
1044                 comedi_buf_read_samples(s, &d, 1);
1045
1046                 if (devpriv->is_6xxx) {
1047                         packed_data = d & 0xffff;
1048                         /* 6711 only has 16 bit wide ao fifo */
1049                         if (!devpriv->is_6711) {
1050                                 comedi_buf_read_samples(s, &d, 1);
1051                                 i++;
1052                                 packed_data |= (d << 16) & 0xffff0000;
1053                         }
1054                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
1055                 } else {
1056                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
1057                 }
1058         }
1059 }
1060
1061 /*
1062  *  There's a small problem if the FIFO gets really low and we
1063  *  don't have the data to fill it.  Basically, if after we fill
1064  *  the FIFO with all the data available, the FIFO is _still_
1065  *  less than half full, we never clear the interrupt.  If the
1066  *  IRQ is in edge mode, we never get another interrupt, because
1067  *  this one wasn't cleared.  If in level mode, we get flooded
1068  *  with interrupts that we can't fulfill, because nothing ever
1069  *  gets put into the buffer.
1070  *
1071  *  This kind of situation is recoverable, but it is easier to
1072  *  just pretend we had a FIFO underrun, since there is a good
1073  *  chance it will happen anyway.  This is _not_ the case for
1074  *  RT code, as RT code might purposely be running close to the
1075  *  metal.  Needs to be fixed eventually.
1076  */
1077 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1078                                  struct comedi_subdevice *s)
1079 {
1080         const struct ni_board_struct *board = dev->board_ptr;
1081         unsigned int nbytes;
1082         unsigned int nsamples;
1083
1084         nbytes = comedi_buf_read_n_available(s);
1085         if (nbytes == 0) {
1086                 s->async->events |= COMEDI_CB_OVERFLOW;
1087                 return 0;
1088         }
1089
1090         nsamples = comedi_bytes_to_samples(s, nbytes);
1091         if (nsamples > board->ao_fifo_depth / 2)
1092                 nsamples = board->ao_fifo_depth / 2;
1093
1094         ni_ao_fifo_load(dev, s, nsamples);
1095
1096         return 1;
1097 }
1098
1099 static int ni_ao_prep_fifo(struct comedi_device *dev,
1100                            struct comedi_subdevice *s)
1101 {
1102         const struct ni_board_struct *board = dev->board_ptr;
1103         struct ni_private *devpriv = dev->private;
1104         unsigned int nbytes;
1105         unsigned int nsamples;
1106
1107         /* reset fifo */
1108         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1109         if (devpriv->is_6xxx)
1110                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1111
1112         /* load some data */
1113         nbytes = comedi_buf_read_n_available(s);
1114         if (nbytes == 0)
1115                 return 0;
1116
1117         nsamples = comedi_bytes_to_samples(s, nbytes);
1118         if (nsamples > board->ao_fifo_depth)
1119                 nsamples = board->ao_fifo_depth;
1120
1121         ni_ao_fifo_load(dev, s, nsamples);
1122
1123         return nsamples;
1124 }
1125
1126 static void ni_ai_fifo_read(struct comedi_device *dev,
1127                             struct comedi_subdevice *s, int n)
1128 {
1129         struct ni_private *devpriv = dev->private;
1130         struct comedi_async *async = s->async;
1131         u32 dl;
1132         unsigned short data;
1133         int i;
1134
1135         if (devpriv->is_611x) {
1136                 for (i = 0; i < n / 2; i++) {
1137                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1138                         /* This may get the hi/lo data in the wrong order */
1139                         data = (dl >> 16) & 0xffff;
1140                         comedi_buf_write_samples(s, &data, 1);
1141                         data = dl & 0xffff;
1142                         comedi_buf_write_samples(s, &data, 1);
1143                 }
1144                 /* Check if there's a single sample stuck in the FIFO */
1145                 if (n % 2) {
1146                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1147                         data = dl & 0xffff;
1148                         comedi_buf_write_samples(s, &data, 1);
1149                 }
1150         } else if (devpriv->is_6143) {
1151                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1152                 for (i = 0; i < n / 2; i++) {
1153                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1154
1155                         data = (dl >> 16) & 0xffff;
1156                         comedi_buf_write_samples(s, &data, 1);
1157                         data = dl & 0xffff;
1158                         comedi_buf_write_samples(s, &data, 1);
1159                 }
1160                 if (n % 2) {
1161                         /* Assume there is a single sample stuck in the FIFO */
1162                         /* Get stranded sample into FIFO */
1163                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1164                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1165                         data = (dl >> 16) & 0xffff;
1166                         comedi_buf_write_samples(s, &data, 1);
1167                 }
1168         } else {
1169                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1170                     sizeof(devpriv->ai_fifo_buffer[0])) {
1171                         dev_err(dev->class_dev,
1172                                 "bug! ai_fifo_buffer too small\n");
1173                         async->events |= COMEDI_CB_ERROR;
1174                         return;
1175                 }
1176                 for (i = 0; i < n; i++) {
1177                         devpriv->ai_fifo_buffer[i] =
1178                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1179                 }
1180                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1181         }
1182 }
1183
1184 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1185 {
1186         const struct ni_board_struct *board = dev->board_ptr;
1187         struct comedi_subdevice *s = dev->read_subdev;
1188         int n;
1189
1190         n = board->ai_fifo_depth / 2;
1191
1192         ni_ai_fifo_read(dev, s, n);
1193 }
1194 #endif
1195
1196 /*
1197    Empties the AI fifo
1198 */
1199 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1200 {
1201         struct ni_private *devpriv = dev->private;
1202         struct comedi_subdevice *s = dev->read_subdev;
1203         u32 dl;
1204         unsigned short data;
1205         unsigned short fifo_empty;
1206         int i;
1207
1208         if (devpriv->is_611x) {
1209                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1210                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1211                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1212
1213                         /* This may get the hi/lo data in the wrong order */
1214                         data = dl >> 16;
1215                         comedi_buf_write_samples(s, &data, 1);
1216                         data = dl & 0xffff;
1217                         comedi_buf_write_samples(s, &data, 1);
1218                 }
1219         } else if (devpriv->is_6143) {
1220                 i = 0;
1221                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1222                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1223
1224                         /* This may get the hi/lo data in the wrong order */
1225                         data = dl >> 16;
1226                         comedi_buf_write_samples(s, &data, 1);
1227                         data = dl & 0xffff;
1228                         comedi_buf_write_samples(s, &data, 1);
1229                         i += 2;
1230                 }
1231                 /*  Check if stranded sample is present */
1232                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1233                         /* Get stranded sample into FIFO */
1234                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1235                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1236                         data = (dl >> 16) & 0xffff;
1237                         comedi_buf_write_samples(s, &data, 1);
1238                 }
1239
1240         } else {
1241                 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1242                              NISTC_AI_STATUS1_FIFO_E;
1243                 while (fifo_empty == 0) {
1244                         for (i = 0;
1245                              i <
1246                              sizeof(devpriv->ai_fifo_buffer) /
1247                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1248                                 fifo_empty = ni_stc_readw(dev,
1249                                                           NISTC_AI_STATUS1_REG) &
1250                                                 NISTC_AI_STATUS1_FIFO_E;
1251                                 if (fifo_empty)
1252                                         break;
1253                                 devpriv->ai_fifo_buffer[i] =
1254                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1255                         }
1256                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1257                 }
1258         }
1259 }
1260
1261 static void get_last_sample_611x(struct comedi_device *dev)
1262 {
1263         struct ni_private *devpriv = dev->private;
1264         struct comedi_subdevice *s = dev->read_subdev;
1265         unsigned short data;
1266         u32 dl;
1267
1268         if (!devpriv->is_611x)
1269                 return;
1270
1271         /* Check if there's a single sample stuck in the FIFO */
1272         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1273                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1274                 data = dl & 0xffff;
1275                 comedi_buf_write_samples(s, &data, 1);
1276         }
1277 }
1278
1279 static void get_last_sample_6143(struct comedi_device *dev)
1280 {
1281         struct ni_private *devpriv = dev->private;
1282         struct comedi_subdevice *s = dev->read_subdev;
1283         unsigned short data;
1284         u32 dl;
1285
1286         if (!devpriv->is_6143)
1287                 return;
1288
1289         /* Check if there's a single sample stuck in the FIFO */
1290         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1291                 /* Get stranded sample into FIFO */
1292                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1293                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1294
1295                 /* This may get the hi/lo data in the wrong order */
1296                 data = (dl >> 16) & 0xffff;
1297                 comedi_buf_write_samples(s, &data, 1);
1298         }
1299 }
1300
1301 static void shutdown_ai_command(struct comedi_device *dev)
1302 {
1303         struct comedi_subdevice *s = dev->read_subdev;
1304
1305 #ifdef PCIDMA
1306         ni_ai_drain_dma(dev);
1307 #endif
1308         ni_handle_fifo_dregs(dev);
1309         get_last_sample_611x(dev);
1310         get_last_sample_6143(dev);
1311
1312         s->async->events |= COMEDI_CB_EOA;
1313 }
1314
1315 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1316 {
1317         struct ni_private *devpriv = dev->private;
1318
1319         if (devpriv->aimode == AIMODE_SCAN) {
1320 #ifdef PCIDMA
1321                 static const int timeout = 10;
1322                 int i;
1323
1324                 for (i = 0; i < timeout; i++) {
1325                         ni_sync_ai_dma(dev);
1326                         if ((s->async->events & COMEDI_CB_EOS))
1327                                 break;
1328                         udelay(1);
1329                 }
1330 #else
1331                 ni_handle_fifo_dregs(dev);
1332                 s->async->events |= COMEDI_CB_EOS;
1333 #endif
1334         }
1335         /* handle special case of single scan */
1336         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1337                 shutdown_ai_command(dev);
1338 }
1339
1340 static void handle_gpct_interrupt(struct comedi_device *dev,
1341                                   unsigned short counter_index)
1342 {
1343 #ifdef PCIDMA
1344         struct ni_private *devpriv = dev->private;
1345         struct comedi_subdevice *s;
1346
1347         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1348
1349         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1350                                 s);
1351         comedi_handle_events(dev, s);
1352 #endif
1353 }
1354
1355 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1356 {
1357         unsigned short ack = 0;
1358
1359         if (a_status & NISTC_AI_STATUS1_SC_TC)
1360                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1361         if (a_status & NISTC_AI_STATUS1_START1)
1362                 ack |= NISTC_INTA_ACK_AI_START1;
1363         if (a_status & NISTC_AI_STATUS1_START)
1364                 ack |= NISTC_INTA_ACK_AI_START;
1365         if (a_status & NISTC_AI_STATUS1_STOP)
1366                 ack |= NISTC_INTA_ACK_AI_STOP;
1367         if (ack)
1368                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1369 }
1370
1371 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1372                                unsigned ai_mite_status)
1373 {
1374         struct comedi_subdevice *s = dev->read_subdev;
1375         struct comedi_cmd *cmd = &s->async->cmd;
1376
1377         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1378         if (s->type == COMEDI_SUBD_UNUSED)
1379                 return;
1380
1381 #ifdef PCIDMA
1382         if (ai_mite_status & CHSR_LINKC)
1383                 ni_sync_ai_dma(dev);
1384
1385         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1386                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1387                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1388                 dev_err(dev->class_dev,
1389                         "unknown mite interrupt (ai_mite_status=%08x)\n",
1390                         ai_mite_status);
1391                 s->async->events |= COMEDI_CB_ERROR;
1392                 /* disable_irq(dev->irq); */
1393         }
1394 #endif
1395
1396         /* test for all uncommon interrupt events at the same time */
1397         if (status & (NISTC_AI_STATUS1_ERR |
1398                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1399                 if (status == 0xffff) {
1400                         dev_err(dev->class_dev, "Card removed?\n");
1401                         /* we probably aren't even running a command now,
1402                          * so it's a good idea to be careful. */
1403                         if (comedi_is_subdevice_running(s)) {
1404                                 s->async->events |= COMEDI_CB_ERROR;
1405                                 comedi_handle_events(dev, s);
1406                         }
1407                         return;
1408                 }
1409                 if (status & NISTC_AI_STATUS1_ERR) {
1410                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1411                                 status);
1412
1413                         shutdown_ai_command(dev);
1414
1415                         s->async->events |= COMEDI_CB_ERROR;
1416                         if (status & NISTC_AI_STATUS1_OVER)
1417                                 s->async->events |= COMEDI_CB_OVERFLOW;
1418
1419                         comedi_handle_events(dev, s);
1420                         return;
1421                 }
1422                 if (status & NISTC_AI_STATUS1_SC_TC) {
1423                         if (cmd->stop_src == TRIG_COUNT)
1424                                 shutdown_ai_command(dev);
1425                 }
1426         }
1427 #ifndef PCIDMA
1428         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1429                 int i;
1430                 static const int timeout = 10;
1431                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1432                  *fail to get the fifo less than half full, so loop to be sure.*/
1433                 for (i = 0; i < timeout; ++i) {
1434                         ni_handle_fifo_half_full(dev);
1435                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1436                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1437                                 break;
1438                 }
1439         }
1440 #endif /*  !PCIDMA */
1441
1442         if (status & NISTC_AI_STATUS1_STOP)
1443                 ni_handle_eos(dev, s);
1444
1445         comedi_handle_events(dev, s);
1446 }
1447
1448 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1449 {
1450         unsigned short ack = 0;
1451
1452         if (b_status & NISTC_AO_STATUS1_BC_TC)
1453                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1454         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1455                 ack |= NISTC_INTB_ACK_AO_ERR;
1456         if (b_status & NISTC_AO_STATUS1_START)
1457                 ack |= NISTC_INTB_ACK_AO_START;
1458         if (b_status & NISTC_AO_STATUS1_START1)
1459                 ack |= NISTC_INTB_ACK_AO_START1;
1460         if (b_status & NISTC_AO_STATUS1_UC_TC)
1461                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1462         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1463                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1464         if (b_status & NISTC_AO_STATUS1_UPDATE)
1465                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1466         if (ack)
1467                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1468 }
1469
1470 static void handle_b_interrupt(struct comedi_device *dev,
1471                                unsigned short b_status, unsigned ao_mite_status)
1472 {
1473         struct comedi_subdevice *s = dev->write_subdev;
1474         /* unsigned short ack=0; */
1475
1476 #ifdef PCIDMA
1477         /* Currently, mite.c requires us to handle LINKC */
1478         if (ao_mite_status & CHSR_LINKC) {
1479                 struct ni_private *devpriv = dev->private;
1480
1481                 mite_handle_b_linkc(devpriv->mite, dev);
1482         }
1483
1484         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1485                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1486                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1487                 dev_err(dev->class_dev,
1488                         "unknown mite interrupt (ao_mite_status=%08x)\n",
1489                         ao_mite_status);
1490                 s->async->events |= COMEDI_CB_ERROR;
1491         }
1492 #endif
1493
1494         if (b_status == 0xffff)
1495                 return;
1496         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1497                 dev_err(dev->class_dev,
1498                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1499                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1500                 s->async->events |= COMEDI_CB_OVERFLOW;
1501         }
1502
1503         if (b_status & NISTC_AO_STATUS1_BC_TC)
1504                 s->async->events |= COMEDI_CB_EOA;
1505
1506 #ifndef PCIDMA
1507         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1508                 int ret;
1509
1510                 ret = ni_ao_fifo_half_empty(dev, s);
1511                 if (!ret) {
1512                         dev_err(dev->class_dev, "AO buffer underrun\n");
1513                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1514                                     NISTC_INTB_ENA_AO_FIFO |
1515                                     NISTC_INTB_ENA_AO_ERR, 0);
1516                         s->async->events |= COMEDI_CB_OVERFLOW;
1517                 }
1518         }
1519 #endif
1520
1521         comedi_handle_events(dev, s);
1522 }
1523
1524 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1525                         void *data, unsigned int num_bytes,
1526                         unsigned int chan_index)
1527 {
1528         struct ni_private *devpriv = dev->private;
1529         struct comedi_async *async = s->async;
1530         struct comedi_cmd *cmd = &async->cmd;
1531         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1532         unsigned short *array = data;
1533         unsigned int *larray = data;
1534         unsigned int i;
1535 #ifdef PCIDMA
1536         __le16 *barray = data;
1537         __le32 *blarray = data;
1538 #endif
1539
1540         for (i = 0; i < nsamples; i++) {
1541 #ifdef PCIDMA
1542                 if (s->subdev_flags & SDF_LSAMPL)
1543                         larray[i] = le32_to_cpu(blarray[i]);
1544                 else
1545                         array[i] = le16_to_cpu(barray[i]);
1546 #endif
1547                 if (s->subdev_flags & SDF_LSAMPL)
1548                         larray[i] += devpriv->ai_offset[chan_index];
1549                 else
1550                         array[i] += devpriv->ai_offset[chan_index];
1551                 chan_index++;
1552                 chan_index %= cmd->chanlist_len;
1553         }
1554 }
1555
1556 #ifdef PCIDMA
1557
1558 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1559 {
1560         struct ni_private *devpriv = dev->private;
1561         struct comedi_subdevice *s = dev->read_subdev;
1562         int retval;
1563         unsigned long flags;
1564
1565         retval = ni_request_ai_mite_channel(dev);
1566         if (retval)
1567                 return retval;
1568
1569         /* write alloc the entire buffer */
1570         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1571
1572         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1573         if (!devpriv->ai_mite_chan) {
1574                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1575                 return -EIO;
1576         }
1577
1578         if (devpriv->is_611x || devpriv->is_6143)
1579                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1580         else if (devpriv->is_628x)
1581                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1582         else
1583                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1584
1585         /*start the MITE */
1586         mite_dma_arm(devpriv->ai_mite_chan);
1587         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1588
1589         return 0;
1590 }
1591
1592 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1593 {
1594         struct ni_private *devpriv = dev->private;
1595         struct comedi_subdevice *s = dev->write_subdev;
1596         int retval;
1597         unsigned long flags;
1598
1599         retval = ni_request_ao_mite_channel(dev);
1600         if (retval)
1601                 return retval;
1602
1603         /* read alloc the entire buffer */
1604         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1605
1606         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1607         if (devpriv->ao_mite_chan) {
1608                 if (devpriv->is_611x || devpriv->is_6713) {
1609                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1610                 } else {
1611                         /* doing 32 instead of 16 bit wide transfers from memory
1612                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1613                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1614                 }
1615                 mite_dma_arm(devpriv->ao_mite_chan);
1616         } else {
1617                 retval = -EIO;
1618         }
1619         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1620
1621         return retval;
1622 }
1623
1624 #endif /*  PCIDMA */
1625
1626 /*
1627    used for both cancel ioctl and board initialization
1628
1629    this is pretty harsh for a cancel, but it works...
1630  */
1631
1632 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1633 {
1634         struct ni_private *devpriv = dev->private;
1635         unsigned ai_personal;
1636         unsigned ai_out_ctrl;
1637
1638         ni_release_ai_mite_channel(dev);
1639         /* ai configuration */
1640         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1641                       NISTC_RESET_REG);
1642
1643         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1644
1645         ni_clear_ai_fifo(dev);
1646
1647         if (!devpriv->is_6143)
1648                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1649
1650         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1651         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1652                            NISTC_AI_MODE1_RSVD
1653                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1654                       NISTC_AI_MODE1_REG);
1655         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1656         /* generate FIFO interrupts on non-empty */
1657         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1658                       NISTC_AI_MODE3_REG);
1659
1660         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1661                       NISTC_AI_PERSONAL_SOC_POLARITY |
1662                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1663         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1664                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1665                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1666                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1667         if (devpriv->is_611x) {
1668                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1669         } else if (devpriv->is_6143) {
1670                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1671         } else {
1672                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1673                 if (devpriv->is_622x)
1674                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1675                 else
1676                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1677         }
1678         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1679         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1680
1681         /* the following registers should not be changed, because there
1682          * are no backup registers in devpriv.  If you want to change
1683          * any of these, add a backup register and other appropriate code:
1684          *      NISTC_AI_MODE1_REG
1685          *      NISTC_AI_MODE3_REG
1686          *      NISTC_AI_PERSONAL_REG
1687          *      NISTC_AI_OUT_CTRL_REG
1688          */
1689
1690         /* clear interrupts */
1691         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1692
1693         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1694
1695         return 0;
1696 }
1697
1698 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1699 {
1700         unsigned long flags;
1701         int count;
1702
1703         /*  lock to avoid race with interrupt handler */
1704         spin_lock_irqsave(&dev->spinlock, flags);
1705 #ifndef PCIDMA
1706         ni_handle_fifo_dregs(dev);
1707 #else
1708         ni_sync_ai_dma(dev);
1709 #endif
1710         count = comedi_buf_n_bytes_ready(s);
1711         spin_unlock_irqrestore(&dev->spinlock, flags);
1712
1713         return count;
1714 }
1715
1716 static void ni_prime_channelgain_list(struct comedi_device *dev)
1717 {
1718         int i;
1719
1720         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1721         for (i = 0; i < NI_TIMEOUT; ++i) {
1722                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1723                       NISTC_AI_STATUS1_FIFO_E)) {
1724                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1725                         return;
1726                 }
1727                 udelay(1);
1728         }
1729         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1730 }
1731
1732 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1733                                               unsigned int n_chan,
1734                                               unsigned int *list)
1735 {
1736         const struct ni_board_struct *board = dev->board_ptr;
1737         struct ni_private *devpriv = dev->private;
1738         unsigned int chan, range, aref;
1739         unsigned int i;
1740         unsigned int dither;
1741         unsigned range_code;
1742
1743         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1744
1745         if ((list[0] & CR_ALT_SOURCE)) {
1746                 unsigned bypass_bits;
1747
1748                 chan = CR_CHAN(list[0]);
1749                 range = CR_RANGE(list[0]);
1750                 range_code = ni_gainlkup[board->gainlkup][range];
1751                 dither = (list[0] & CR_ALT_FILTER) != 0;
1752                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1753                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1754                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1755                               devpriv->ai_calib_source;
1756                 if (dither)
1757                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1758                 /*  don't use 2's complement encoding */
1759                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1760                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1761         } else {
1762                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1763         }
1764         for (i = 0; i < n_chan; i++) {
1765                 unsigned config_bits = 0;
1766
1767                 chan = CR_CHAN(list[i]);
1768                 aref = CR_AREF(list[i]);
1769                 range = CR_RANGE(list[i]);
1770                 dither = (list[i] & CR_ALT_FILTER) != 0;
1771
1772                 range_code = ni_gainlkup[board->gainlkup][range];
1773                 devpriv->ai_offset[i] = 0;
1774                 switch (aref) {
1775                 case AREF_DIFF:
1776                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1777                         break;
1778                 case AREF_COMMON:
1779                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1780                         break;
1781                 case AREF_GROUND:
1782                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1783                         break;
1784                 case AREF_OTHER:
1785                         break;
1786                 }
1787                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1788                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1789                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1790                 if (i == n_chan - 1)
1791                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1792                 if (dither)
1793                         config_bits |= NI_M_AI_CFG_DITHER;
1794                 /*  don't use 2's complement encoding */
1795                 config_bits |= NI_M_AI_CFG_POLARITY;
1796                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1797         }
1798         ni_prime_channelgain_list(dev);
1799 }
1800
1801 /*
1802  * Notes on the 6110 and 6111:
1803  * These boards a slightly different than the rest of the series, since
1804  * they have multiple A/D converters.
1805  * From the driver side, the configuration memory is a
1806  * little different.
1807  * Configuration Memory Low:
1808  *   bits 15-9: same
1809  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1810  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1811  *       1001 gain=0.1 (+/- 50)
1812  *       1010 0.2
1813  *       1011 0.1
1814  *       0001 1
1815  *       0010 2
1816  *       0011 5
1817  *       0100 10
1818  *       0101 20
1819  *       0110 50
1820  * Configuration Memory High:
1821  *   bits 12-14: Channel Type
1822  *       001 for differential
1823  *       000 for calibration
1824  *   bit 11: coupling  (this is not currently handled)
1825  *       1 AC coupling
1826  *       0 DC coupling
1827  *   bits 0-2: channel
1828  *       valid channels are 0-3
1829  */
1830 static void ni_load_channelgain_list(struct comedi_device *dev,
1831                                      struct comedi_subdevice *s,
1832                                      unsigned int n_chan, unsigned int *list)
1833 {
1834         const struct ni_board_struct *board = dev->board_ptr;
1835         struct ni_private *devpriv = dev->private;
1836         unsigned int offset = (s->maxdata + 1) >> 1;
1837         unsigned int chan, range, aref;
1838         unsigned int i;
1839         unsigned int hi, lo;
1840         unsigned int dither;
1841
1842         if (devpriv->is_m_series) {
1843                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1844                 return;
1845         }
1846         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1847                 if (devpriv->changain_state
1848                     && devpriv->changain_spec == list[0]) {
1849                         /*  ready to go. */
1850                         return;
1851                 }
1852                 devpriv->changain_state = 1;
1853                 devpriv->changain_spec = list[0];
1854         } else {
1855                 devpriv->changain_state = 0;
1856         }
1857
1858         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1859
1860         /*  Set up Calibration mode if required */
1861         if (devpriv->is_6143) {
1862                 if ((list[0] & CR_ALT_SOURCE)
1863                     && !devpriv->ai_calib_source_enabled) {
1864                         /*  Strobe Relay enable bit */
1865                         ni_writew(dev, devpriv->ai_calib_source |
1866                                        NI6143_CALIB_CHAN_RELAY_ON,
1867                                   NI6143_CALIB_CHAN_REG);
1868                         ni_writew(dev, devpriv->ai_calib_source,
1869                                   NI6143_CALIB_CHAN_REG);
1870                         devpriv->ai_calib_source_enabled = 1;
1871                         msleep_interruptible(100);      /*  Allow relays to change */
1872                 } else if (!(list[0] & CR_ALT_SOURCE)
1873                            && devpriv->ai_calib_source_enabled) {
1874                         /*  Strobe Relay disable bit */
1875                         ni_writew(dev, devpriv->ai_calib_source |
1876                                        NI6143_CALIB_CHAN_RELAY_OFF,
1877                                   NI6143_CALIB_CHAN_REG);
1878                         ni_writew(dev, devpriv->ai_calib_source,
1879                                   NI6143_CALIB_CHAN_REG);
1880                         devpriv->ai_calib_source_enabled = 0;
1881                         msleep_interruptible(100);      /*  Allow relays to change */
1882                 }
1883         }
1884
1885         for (i = 0; i < n_chan; i++) {
1886                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1887                         chan = devpriv->ai_calib_source;
1888                 else
1889                         chan = CR_CHAN(list[i]);
1890                 aref = CR_AREF(list[i]);
1891                 range = CR_RANGE(list[i]);
1892                 dither = (list[i] & CR_ALT_FILTER) != 0;
1893
1894                 /* fix the external/internal range differences */
1895                 range = ni_gainlkup[board->gainlkup][range];
1896                 if (devpriv->is_611x)
1897                         devpriv->ai_offset[i] = offset;
1898                 else
1899                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1900
1901                 hi = 0;
1902                 if ((list[i] & CR_ALT_SOURCE)) {
1903                         if (devpriv->is_611x)
1904                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1905                                           NI611X_CALIB_CHAN_SEL_REG);
1906                 } else {
1907                         if (devpriv->is_611x)
1908                                 aref = AREF_DIFF;
1909                         else if (devpriv->is_6143)
1910                                 aref = AREF_OTHER;
1911                         switch (aref) {
1912                         case AREF_DIFF:
1913                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1914                                 break;
1915                         case AREF_COMMON:
1916                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1917                                 break;
1918                         case AREF_GROUND:
1919                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1920                                 break;
1921                         case AREF_OTHER:
1922                                 break;
1923                         }
1924                 }
1925                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1926
1927                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1928
1929                 if (!devpriv->is_6143) {
1930                         lo = NI_E_AI_CFG_LO_GAIN(range);
1931
1932                         if (i == n_chan - 1)
1933                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1934                         if (dither)
1935                                 lo |= NI_E_AI_CFG_LO_DITHER;
1936
1937                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1938                 }
1939         }
1940
1941         /* prime the channel/gain list */
1942         if (!devpriv->is_611x && !devpriv->is_6143)
1943                 ni_prime_channelgain_list(dev);
1944 }
1945
1946 static int ni_ai_insn_read(struct comedi_device *dev,
1947                            struct comedi_subdevice *s,
1948                            struct comedi_insn *insn,
1949                            unsigned int *data)
1950 {
1951         struct ni_private *devpriv = dev->private;
1952         unsigned int mask = (s->maxdata + 1) >> 1;
1953         int i, n;
1954         unsigned signbits;
1955         unsigned int d;
1956         unsigned long dl;
1957
1958         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1959
1960         ni_clear_ai_fifo(dev);
1961
1962         signbits = devpriv->ai_offset[0];
1963         if (devpriv->is_611x) {
1964                 for (n = 0; n < num_adc_stages_611x; n++) {
1965                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1966                                       NISTC_AI_CMD1_REG);
1967                         udelay(1);
1968                 }
1969                 for (n = 0; n < insn->n; n++) {
1970                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1971                                       NISTC_AI_CMD1_REG);
1972                         /* The 611x has screwy 32-bit FIFOs. */
1973                         d = 0;
1974                         for (i = 0; i < NI_TIMEOUT; i++) {
1975                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1976                                         d = ni_readl(dev,
1977                                                      NI611X_AI_FIFO_DATA_REG);
1978                                         d >>= 16;
1979                                         d &= 0xffff;
1980                                         break;
1981                                 }
1982                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1983                                       NISTC_AI_STATUS1_FIFO_E)) {
1984                                         d = ni_readl(dev,
1985                                                      NI611X_AI_FIFO_DATA_REG);
1986                                         d &= 0xffff;
1987                                         break;
1988                                 }
1989                         }
1990                         if (i == NI_TIMEOUT) {
1991                                 dev_err(dev->class_dev, "timeout\n");
1992                                 return -ETIME;
1993                         }
1994                         d += signbits;
1995                         data[n] = d;
1996                 }
1997         } else if (devpriv->is_6143) {
1998                 for (n = 0; n < insn->n; n++) {
1999                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2000                                       NISTC_AI_CMD1_REG);
2001
2002                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
2003                         dl = 0;
2004                         for (i = 0; i < NI_TIMEOUT; i++) {
2005                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
2006                                     0x01) {
2007                                         /* Get stranded sample into FIFO */
2008                                         ni_writel(dev, 0x01,
2009                                                   NI6143_AI_FIFO_CTRL_REG);
2010                                         dl = ni_readl(dev,
2011                                                       NI6143_AI_FIFO_DATA_REG);
2012                                         break;
2013                                 }
2014                         }
2015                         if (i == NI_TIMEOUT) {
2016                                 dev_err(dev->class_dev, "timeout\n");
2017                                 return -ETIME;
2018                         }
2019                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2020                 }
2021         } else {
2022                 for (n = 0; n < insn->n; n++) {
2023                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2024                                       NISTC_AI_CMD1_REG);
2025                         for (i = 0; i < NI_TIMEOUT; i++) {
2026                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
2027                                       NISTC_AI_STATUS1_FIFO_E))
2028                                         break;
2029                         }
2030                         if (i == NI_TIMEOUT) {
2031                                 dev_err(dev->class_dev, "timeout\n");
2032                                 return -ETIME;
2033                         }
2034                         if (devpriv->is_m_series) {
2035                                 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2036                                 dl &= mask;
2037                                 data[n] = dl;
2038                         } else {
2039                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2040                                 d += signbits;  /* subtle: needs to be short addition */
2041                                 data[n] = d;
2042                         }
2043                 }
2044         }
2045         return insn->n;
2046 }
2047
2048 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2049                           unsigned int flags)
2050 {
2051         struct ni_private *devpriv = dev->private;
2052         int divider;
2053
2054         switch (flags & CMDF_ROUND_MASK) {
2055         case CMDF_ROUND_NEAREST:
2056         default:
2057                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2058                 break;
2059         case CMDF_ROUND_DOWN:
2060                 divider = (nanosec) / devpriv->clock_ns;
2061                 break;
2062         case CMDF_ROUND_UP:
2063                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2064                 break;
2065         }
2066         return divider - 1;
2067 }
2068
2069 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2070 {
2071         struct ni_private *devpriv = dev->private;
2072
2073         return devpriv->clock_ns * (timer + 1);
2074 }
2075
2076 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2077                                          unsigned num_channels)
2078 {
2079         const struct ni_board_struct *board = dev->board_ptr;
2080         struct ni_private *devpriv = dev->private;
2081
2082         /* simultaneously-sampled inputs */
2083         if (devpriv->is_611x || devpriv->is_6143)
2084                 return board->ai_speed;
2085
2086         /* multiplexed inputs */
2087         return board->ai_speed * num_channels;
2088 }
2089
2090 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2091                          struct comedi_cmd *cmd)
2092 {
2093         const struct ni_board_struct *board = dev->board_ptr;
2094         struct ni_private *devpriv = dev->private;
2095         int err = 0;
2096         unsigned int tmp;
2097         unsigned int sources;
2098
2099         /* Step 1 : check if triggers are trivially valid */
2100
2101         err |= comedi_check_trigger_src(&cmd->start_src,
2102                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2103         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2104                                         TRIG_TIMER | TRIG_EXT);
2105
2106         sources = TRIG_TIMER | TRIG_EXT;
2107         if (devpriv->is_611x || devpriv->is_6143)
2108                 sources |= TRIG_NOW;
2109         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2110
2111         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2112         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2113
2114         if (err)
2115                 return 1;
2116
2117         /* Step 2a : make sure trigger sources are unique */
2118
2119         err |= comedi_check_trigger_is_unique(cmd->start_src);
2120         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2121         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2122         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2123
2124         /* Step 2b : and mutually compatible */
2125
2126         if (err)
2127                 return 2;
2128
2129         /* Step 3: check if arguments are trivially valid */
2130
2131         switch (cmd->start_src) {
2132         case TRIG_NOW:
2133         case TRIG_INT:
2134                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2135                 break;
2136         case TRIG_EXT:
2137                 tmp = CR_CHAN(cmd->start_arg);
2138
2139                 if (tmp > 16)
2140                         tmp = 16;
2141                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2142                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2143                 break;
2144         }
2145
2146         if (cmd->scan_begin_src == TRIG_TIMER) {
2147                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2148                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2149                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2150                                                     devpriv->clock_ns *
2151                                                     0xffffff);
2152         } else if (cmd->scan_begin_src == TRIG_EXT) {
2153                 /* external trigger */
2154                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2155
2156                 if (tmp > 16)
2157                         tmp = 16;
2158                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2159                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2160         } else {                /* TRIG_OTHER */
2161                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2162         }
2163
2164         if (cmd->convert_src == TRIG_TIMER) {
2165                 if (devpriv->is_611x || devpriv->is_6143) {
2166                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2167                                                            0);
2168                 } else {
2169                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2170                                                             board->ai_speed);
2171                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2172                                                             devpriv->clock_ns *
2173                                                             0xffff);
2174                 }
2175         } else if (cmd->convert_src == TRIG_EXT) {
2176                 /* external trigger */
2177                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2178
2179                 if (tmp > 16)
2180                         tmp = 16;
2181                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2182                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2183         } else if (cmd->convert_src == TRIG_NOW) {
2184                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2185         }
2186
2187         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2188                                            cmd->chanlist_len);
2189
2190         if (cmd->stop_src == TRIG_COUNT) {
2191                 unsigned int max_count = 0x01000000;
2192
2193                 if (devpriv->is_611x)
2194                         max_count -= num_adc_stages_611x;
2195                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2196                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2197         } else {
2198                 /* TRIG_NONE */
2199                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2200         }
2201
2202         if (err)
2203                 return 3;
2204
2205         /* step 4: fix up any arguments */
2206
2207         if (cmd->scan_begin_src == TRIG_TIMER) {
2208                 tmp = cmd->scan_begin_arg;
2209                 cmd->scan_begin_arg =
2210                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2211                                                        cmd->scan_begin_arg,
2212                                                        cmd->flags));
2213                 if (tmp != cmd->scan_begin_arg)
2214                         err++;
2215         }
2216         if (cmd->convert_src == TRIG_TIMER) {
2217                 if (!devpriv->is_611x && !devpriv->is_6143) {
2218                         tmp = cmd->convert_arg;
2219                         cmd->convert_arg =
2220                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2221                                                                cmd->convert_arg,
2222                                                                cmd->flags));
2223                         if (tmp != cmd->convert_arg)
2224                                 err++;
2225                         if (cmd->scan_begin_src == TRIG_TIMER &&
2226                             cmd->scan_begin_arg <
2227                             cmd->convert_arg * cmd->scan_end_arg) {
2228                                 cmd->scan_begin_arg =
2229                                     cmd->convert_arg * cmd->scan_end_arg;
2230                                 err++;
2231                         }
2232                 }
2233         }
2234
2235         if (err)
2236                 return 4;
2237
2238         return 0;
2239 }
2240
2241 static int ni_ai_inttrig(struct comedi_device *dev,
2242                          struct comedi_subdevice *s,
2243                          unsigned int trig_num)
2244 {
2245         struct ni_private *devpriv = dev->private;
2246         struct comedi_cmd *cmd = &s->async->cmd;
2247
2248         if (trig_num != cmd->start_arg)
2249                 return -EINVAL;
2250
2251         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2252                       NISTC_AI_CMD2_REG);
2253         s->async->inttrig = NULL;
2254
2255         return 1;
2256 }
2257
2258 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2259 {
2260         struct ni_private *devpriv = dev->private;
2261         const struct comedi_cmd *cmd = &s->async->cmd;
2262         int timer;
2263         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2264         int mode2 = 0;
2265         int start_stop_select = 0;
2266         unsigned int stop_count;
2267         int interrupt_a_enable = 0;
2268         unsigned ai_trig;
2269
2270         if (dev->irq == 0) {
2271                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2272                 return -EIO;
2273         }
2274         ni_clear_ai_fifo(dev);
2275
2276         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2277
2278         /* start configuration */
2279         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2280
2281         /* disable analog triggering for now, since it
2282          * interferes with the use of pfi0 */
2283         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2284         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2285
2286         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2287         switch (cmd->start_src) {
2288         case TRIG_INT:
2289         case TRIG_NOW:
2290                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2291                            NISTC_AI_TRIG_START1_SEL(0);
2292                 break;
2293         case TRIG_EXT:
2294                 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2295                                                     1);
2296
2297                 if (cmd->start_arg & CR_INVERT)
2298                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2299                 if (cmd->start_arg & CR_EDGE)
2300                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2301                 break;
2302         }
2303         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2304
2305         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2306         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2307         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2308         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2309
2310         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2311                 /* logic low */
2312                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2313                                      NISTC_AI_STOP_SEL(31) |
2314                                      NISTC_AI_STOP_SYNC;
2315         } else {
2316                 /*  ai configuration memory */
2317                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2318         }
2319         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2320
2321         devpriv->ai_cmd2 = 0;
2322         switch (cmd->stop_src) {
2323         case TRIG_COUNT:
2324                 stop_count = cmd->stop_arg - 1;
2325
2326                 if (devpriv->is_611x) {
2327                         /*  have to take 3 stage adc pipeline into account */
2328                         stop_count += num_adc_stages_611x;
2329                 }
2330                 /* stage number of scans */
2331                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2332
2333                 mode1 |= NISTC_AI_MODE1_START_STOP |
2334                          NISTC_AI_MODE1_RSVD |
2335                          NISTC_AI_MODE1_TRIGGER_ONCE;
2336                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2337                 /* load SC (Scan Count) */
2338                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2339
2340                 if (stop_count == 0) {
2341                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2342                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2343                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2344                         if (cmd->chanlist_len > 1)
2345                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2346                                                      NISTC_AI_STOP_EDGE;
2347                 }
2348                 break;
2349         case TRIG_NONE:
2350                 /* stage number of scans */
2351                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2352
2353                 mode1 |= NISTC_AI_MODE1_START_STOP |
2354                          NISTC_AI_MODE1_RSVD |
2355                          NISTC_AI_MODE1_CONTINUOUS;
2356                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2357
2358                 /* load SC (Scan Count) */
2359                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2360                 break;
2361         }
2362
2363         switch (cmd->scan_begin_src) {
2364         case TRIG_TIMER:
2365                 /*
2366                  * stop bits for non 611x boards
2367                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2368                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2369                  * NISTC_AI_START_STOP_REG:
2370                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2371                  * NISTC_AI_START_EDGE=1        edge triggered
2372                  * NISTC_AI_START_SYNC=1        (?)
2373                  * NISTC_AI_START_SEL=0         SI_TC
2374                  * NISTC_AI_STOP_POLARITY=0     rising edge
2375                  * NISTC_AI_STOP_EDGE=0         level
2376                  * NISTC_AI_STOP_SYNC=1
2377                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2378                  */
2379                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2380                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2381
2382                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2383                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2384                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2385                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2386
2387                 /* load SI */
2388                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2389                                        CMDF_ROUND_NEAREST);
2390                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2391                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2392                 break;
2393         case TRIG_EXT:
2394                 if (cmd->scan_begin_arg & CR_EDGE)
2395                         start_stop_select |= NISTC_AI_START_EDGE;
2396                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2397                         start_stop_select |= NISTC_AI_START_POLARITY;
2398                 if (cmd->scan_begin_src != cmd->convert_src ||
2399                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2400                     (cmd->convert_arg & ~CR_EDGE))
2401                         start_stop_select |= NISTC_AI_START_SYNC;
2402                 start_stop_select |=
2403                     NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2404                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2405                 break;
2406         }
2407
2408         switch (cmd->convert_src) {
2409         case TRIG_TIMER:
2410         case TRIG_NOW:
2411                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2412                         timer = 1;
2413                 else
2414                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2415                                                CMDF_ROUND_NEAREST);
2416                 /* 0,0 does not work */
2417                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2418                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2419
2420                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2421                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2422                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2423
2424                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2425
2426                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2427                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2428                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2429                 break;
2430         case TRIG_EXT:
2431                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
2432                 if ((cmd->convert_arg & CR_INVERT) == 0)
2433                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2434                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2435
2436                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2437                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2438                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2439
2440                 break;
2441         }
2442
2443         if (dev->irq) {
2444                 /* interrupt on FIFO, errors, SC_TC */
2445                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2446                                       NISTC_INTA_ENA_AI_SC_TC;
2447
2448 #ifndef PCIDMA
2449                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2450 #endif
2451
2452                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2453                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2454                         /* wake on end-of-scan */
2455                         devpriv->aimode = AIMODE_SCAN;
2456                 } else {
2457                         devpriv->aimode = AIMODE_HALF_FULL;
2458                 }
2459
2460                 switch (devpriv->aimode) {
2461                 case AIMODE_HALF_FULL:
2462                         /*generate FIFO interrupts and DMA requests on half-full */
2463 #ifdef PCIDMA
2464                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2465                                       NISTC_AI_MODE3_REG);
2466 #else
2467                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2468                                       NISTC_AI_MODE3_REG);
2469 #endif
2470                         break;
2471                 case AIMODE_SAMPLE:
2472                         /*generate FIFO interrupts on non-empty */
2473                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2474                                       NISTC_AI_MODE3_REG);
2475                         break;
2476                 case AIMODE_SCAN:
2477 #ifdef PCIDMA
2478                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2479                                       NISTC_AI_MODE3_REG);
2480 #else
2481                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2482                                       NISTC_AI_MODE3_REG);
2483 #endif
2484                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2485                         break;
2486                 default:
2487                         break;
2488                 }
2489
2490                 /* clear interrupts */
2491                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2492
2493                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2494         } else {
2495                 /* interrupt on nothing */
2496                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2497
2498                 /* XXX start polling if necessary */
2499         }
2500
2501         /* end configuration */
2502         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2503
2504         switch (cmd->scan_begin_src) {
2505         case TRIG_TIMER:
2506                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2507                                    NISTC_AI_CMD1_SI_ARM |
2508                                    NISTC_AI_CMD1_DIV_ARM |
2509                                    NISTC_AI_CMD1_SC_ARM,
2510                               NISTC_AI_CMD1_REG);
2511                 break;
2512         case TRIG_EXT:
2513                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2514                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2515                                    NISTC_AI_CMD1_DIV_ARM |
2516                                    NISTC_AI_CMD1_SC_ARM,
2517                               NISTC_AI_CMD1_REG);
2518                 break;
2519         }
2520
2521 #ifdef PCIDMA
2522         {
2523                 int retval = ni_ai_setup_MITE_dma(dev);
2524
2525                 if (retval)
2526                         return retval;
2527         }
2528 #endif
2529
2530         if (cmd->start_src == TRIG_NOW) {
2531                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2532                                    devpriv->ai_cmd2,
2533                               NISTC_AI_CMD2_REG);
2534                 s->async->inttrig = NULL;
2535         } else if (cmd->start_src == TRIG_EXT) {
2536                 s->async->inttrig = NULL;
2537         } else {        /* TRIG_INT */
2538                 s->async->inttrig = ni_ai_inttrig;
2539         }
2540
2541         return 0;
2542 }
2543
2544 static int ni_ai_insn_config(struct comedi_device *dev,
2545                              struct comedi_subdevice *s,
2546                              struct comedi_insn *insn, unsigned int *data)
2547 {
2548         struct ni_private *devpriv = dev->private;
2549
2550         if (insn->n < 1)
2551                 return -EINVAL;
2552
2553         switch (data[0]) {
2554         case INSN_CONFIG_ALT_SOURCE:
2555                 if (devpriv->is_m_series) {
2556                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2557                                 return -EINVAL;
2558                         devpriv->ai_calib_source = data[1];
2559                 } else if (devpriv->is_6143) {
2560                         unsigned int calib_source;
2561
2562                         calib_source = data[1] & 0xf;
2563
2564                         devpriv->ai_calib_source = calib_source;
2565                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2566                 } else {
2567                         unsigned int calib_source;
2568                         unsigned int calib_source_adjust;
2569
2570                         calib_source = data[1] & 0xf;
2571                         calib_source_adjust = (data[1] >> 4) & 0xff;
2572
2573                         if (calib_source >= 8)
2574                                 return -EINVAL;
2575                         devpriv->ai_calib_source = calib_source;
2576                         if (devpriv->is_611x) {
2577                                 ni_writeb(dev, calib_source_adjust,
2578                                           NI611X_CAL_GAIN_SEL_REG);
2579                         }
2580                 }
2581                 return 2;
2582         default:
2583                 break;
2584         }
2585
2586         return -EINVAL;
2587 }
2588
2589 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2590                         void *data, unsigned int num_bytes,
2591                         unsigned int chan_index)
2592 {
2593         struct comedi_cmd *cmd = &s->async->cmd;
2594         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2595         unsigned short *array = data;
2596         unsigned int i;
2597 #ifdef PCIDMA
2598         __le16 buf, *barray = data;
2599 #endif
2600
2601         for (i = 0; i < nsamples; i++) {
2602                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2603                 unsigned short val = array[i];
2604
2605                 /*
2606                  * Munge data from unsigned to two's complement for
2607                  * bipolar ranges.
2608                  */
2609                 if (comedi_range_is_bipolar(s, range))
2610                         val = comedi_offset_munge(s, val);
2611 #ifdef PCIDMA
2612                 buf = cpu_to_le16(val);
2613                 barray[i] = buf;
2614 #else
2615                 array[i] = val;
2616 #endif
2617                 chan_index++;
2618                 chan_index %= cmd->chanlist_len;
2619         }
2620 }
2621
2622 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2623                                           struct comedi_subdevice *s,
2624                                           unsigned int chanspec[],
2625                                           unsigned int n_chans, int timed)
2626 {
2627         struct ni_private *devpriv = dev->private;
2628         unsigned int range;
2629         unsigned int chan;
2630         unsigned int conf;
2631         int i;
2632         int invert = 0;
2633
2634         if (timed) {
2635                 for (i = 0; i < s->n_chan; ++i) {
2636                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2637                         ni_writeb(dev, devpriv->ao_conf[i],
2638                                   NI_M_AO_CFG_BANK_REG(i));
2639                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2640                 }
2641         }
2642         for (i = 0; i < n_chans; i++) {
2643                 const struct comedi_krange *krange;
2644
2645                 chan = CR_CHAN(chanspec[i]);
2646                 range = CR_RANGE(chanspec[i]);
2647                 krange = s->range_table->range + range;
2648                 invert = 0;
2649                 conf = 0;
2650                 switch (krange->max - krange->min) {
2651                 case 20000000:
2652                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2653                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2654                         break;
2655                 case 10000000:
2656                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2657                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2658                         break;
2659                 case 4000000:
2660                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2661                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2662                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2663                         break;
2664                 case 2000000:
2665                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2666                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2667                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2668                         break;
2669                 default:
2670                         dev_err(dev->class_dev,
2671                                 "bug! unhandled ao reference voltage\n");
2672                         break;
2673                 }
2674                 switch (krange->max + krange->min) {
2675                 case 0:
2676                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2677                         break;
2678                 case 10000000:
2679                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2680                         break;
2681                 default:
2682                         dev_err(dev->class_dev,
2683                                 "bug! unhandled ao offset voltage\n");
2684                         break;
2685                 }
2686                 if (timed)
2687                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2688                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2689                 devpriv->ao_conf[chan] = conf;
2690                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2691         }
2692         return invert;
2693 }
2694
2695 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2696                                      struct comedi_subdevice *s,
2697                                      unsigned int chanspec[],
2698                                      unsigned int n_chans)
2699 {
2700         struct ni_private *devpriv = dev->private;
2701         unsigned int range;
2702         unsigned int chan;
2703         unsigned int conf;
2704         int i;
2705         int invert = 0;
2706
2707         for (i = 0; i < n_chans; i++) {
2708                 chan = CR_CHAN(chanspec[i]);
2709                 range = CR_RANGE(chanspec[i]);
2710                 conf = NI_E_AO_DACSEL(chan);
2711
2712                 if (comedi_range_is_bipolar(s, range)) {
2713                         conf |= NI_E_AO_CFG_BIP;
2714                         invert = (s->maxdata + 1) >> 1;
2715                 } else {
2716                         invert = 0;
2717                 }
2718                 if (comedi_range_is_external(s, range))
2719                         conf |= NI_E_AO_EXT_REF;
2720
2721                 /* not all boards can deglitch, but this shouldn't hurt */
2722                 if (chanspec[i] & CR_DEGLITCH)
2723                         conf |= NI_E_AO_DEGLITCH;
2724
2725                 /* analog reference */
2726                 /* AREF_OTHER connects AO ground to AI ground, i think */
2727                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2728                         conf |= NI_E_AO_GROUND_REF;
2729
2730                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2731                 devpriv->ao_conf[chan] = conf;
2732         }
2733         return invert;
2734 }
2735
2736 static int ni_ao_config_chanlist(struct comedi_device *dev,
2737                                  struct comedi_subdevice *s,
2738                                  unsigned int chanspec[], unsigned int n_chans,
2739                                  int timed)
2740 {
2741         struct ni_private *devpriv = dev->private;
2742
2743         if (devpriv->is_m_series)
2744                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2745                                                       timed);
2746         else
2747                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2748 }
2749
2750 static int ni_ao_insn_write(struct comedi_device *dev,
2751                             struct comedi_subdevice *s,
2752                             struct comedi_insn *insn,
2753                             unsigned int *data)
2754 {
2755         struct ni_private *devpriv = dev->private;
2756         unsigned int chan = CR_CHAN(insn->chanspec);
2757         unsigned int range = CR_RANGE(insn->chanspec);
2758         int reg;
2759         int i;
2760
2761         if (devpriv->is_6xxx) {
2762                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2763
2764                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2765         } else if (devpriv->is_m_series) {
2766                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2767         } else {
2768                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2769         }
2770
2771         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2772
2773         for (i = 0; i < insn->n; i++) {
2774                 unsigned int val = data[i];
2775
2776                 s->readback[chan] = val;
2777
2778                 if (devpriv->is_6xxx) {
2779                         /*
2780                          * 6xxx boards have bipolar outputs, munge the
2781                          * unsigned comedi values to 2's complement
2782                          */
2783                         val = comedi_offset_munge(s, val);
2784
2785                         ni_ao_win_outw(dev, val, reg);
2786                 } else if (devpriv->is_m_series) {
2787                         /*
2788                          * M-series boards use offset binary values for
2789                          * bipolar and uinpolar outputs
2790                          */
2791                         ni_writew(dev, val, reg);
2792                 } else {
2793                         /*
2794                          * Non-M series boards need two's complement values
2795                          * for bipolar ranges.
2796                          */
2797                         if (comedi_range_is_bipolar(s, range))
2798                                 val = comedi_offset_munge(s, val);
2799
2800                         ni_writew(dev, val, reg);
2801                 }
2802         }
2803
2804         return insn->n;
2805 }
2806
2807 static int ni_ao_insn_config(struct comedi_device *dev,
2808                              struct comedi_subdevice *s,
2809                              struct comedi_insn *insn, unsigned int *data)
2810 {
2811         const struct ni_board_struct *board = dev->board_ptr;
2812         struct ni_private *devpriv = dev->private;
2813         unsigned int nbytes;
2814
2815         switch (data[0]) {
2816         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2817                 switch (data[1]) {
2818                 case COMEDI_OUTPUT:
2819                         nbytes = comedi_samples_to_bytes(s,
2820                                                          board->ao_fifo_depth);
2821                         data[2] = 1 + nbytes;
2822                         if (devpriv->mite)
2823                                 data[2] += devpriv->mite->fifo_size;
2824                         break;
2825                 case COMEDI_INPUT:
2826                         data[2] = 0;
2827                         break;
2828                 default:
2829                         return -EINVAL;
2830                 }
2831                 return 0;
2832         default:
2833                 break;
2834         }
2835
2836         return -EINVAL;
2837 }
2838
2839 static int ni_ao_inttrig(struct comedi_device *dev,
2840                          struct comedi_subdevice *s,
2841                          unsigned int trig_num)
2842 {
2843         struct ni_private *devpriv = dev->private;
2844         struct comedi_cmd *cmd = &s->async->cmd;
2845         int ret;
2846         int interrupt_b_bits;
2847         int i;
2848         static const int timeout = 1000;
2849
2850         if (trig_num != cmd->start_arg)
2851                 return -EINVAL;
2852
2853         /* Null trig at beginning prevent ao start trigger from executing more than
2854            once per command (and doing things like trying to allocate the ao dma channel
2855            multiple times) */
2856         s->async->inttrig = NULL;
2857
2858         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2859                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2860         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2861 #ifdef PCIDMA
2862         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2863         if (devpriv->is_6xxx)
2864                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2865         ret = ni_ao_setup_MITE_dma(dev);
2866         if (ret)
2867                 return ret;
2868         ret = ni_ao_wait_for_dma_load(dev);
2869         if (ret < 0)
2870                 return ret;
2871 #else
2872         ret = ni_ao_prep_fifo(dev, s);
2873         if (ret == 0)
2874                 return -EPIPE;
2875
2876         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2877 #endif
2878
2879         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2880                       NISTC_AO_MODE3_REG);
2881         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2882         /* wait for DACs to be loaded */
2883         for (i = 0; i < timeout; i++) {
2884                 udelay(1);
2885                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2886                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2887                         break;
2888         }
2889         if (i == timeout) {
2890                 dev_err(dev->class_dev,
2891                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2892                 return -EIO;
2893         }
2894         /*
2895          * stc manual says we are need to clear error interrupt after
2896          * AO_TMRDACWRs_In_Progress_St clears
2897          */
2898         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2899
2900         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2901
2902         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2903                            NISTC_AO_CMD1_UC_ARM |
2904                            NISTC_AO_CMD1_BC_ARM |
2905                            NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2906                            NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2907                            devpriv->ao_cmd1,
2908                       NISTC_AO_CMD1_REG);
2909
2910         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2911                       NISTC_AO_CMD2_REG);
2912
2913         return 0;
2914 }
2915
2916 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2917 {
2918         const struct ni_board_struct *board = dev->board_ptr;
2919         struct ni_private *devpriv = dev->private;
2920         const struct comedi_cmd *cmd = &s->async->cmd;
2921         int bits;
2922         int i;
2923         unsigned trigvar;
2924         unsigned val;
2925
2926         if (dev->irq == 0) {
2927                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2928                 return -EIO;
2929         }
2930
2931         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2932
2933         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
2934
2935         if (devpriv->is_6xxx) {
2936                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
2937                                NI611X_AO_MISC_REG);
2938
2939                 bits = 0;
2940                 for (i = 0; i < cmd->chanlist_len; i++) {
2941                         int chan;
2942
2943                         chan = CR_CHAN(cmd->chanlist[i]);
2944                         bits |= 1 << chan;
2945                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
2946                 }
2947                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
2948         }
2949
2950         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2951
2952         if (cmd->stop_src == TRIG_NONE) {
2953                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2954                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2955         } else {
2956                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2957                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2958         }
2959         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2960
2961         val = devpriv->ao_trigger_select;
2962         switch (cmd->start_src) {
2963         case TRIG_INT:
2964         case TRIG_NOW:
2965                 val &= ~(NISTC_AO_TRIG_START1_POLARITY |
2966                          NISTC_AO_TRIG_START1_SEL_MASK);
2967                 val |= NISTC_AO_TRIG_START1_EDGE |
2968                        NISTC_AO_TRIG_START1_SYNC;
2969                 break;
2970         case TRIG_EXT:
2971                 val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2972                 if (cmd->start_arg & CR_INVERT) {
2973                         /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2974                         val |= NISTC_AO_TRIG_START1_POLARITY;
2975                 }
2976                 if (cmd->start_arg & CR_EDGE) {
2977                         /* 0=edge detection disabled, 1=enabled */
2978                         val |= NISTC_AO_TRIG_START1_EDGE;
2979                 }
2980                 ni_stc_writew(dev, devpriv->ao_trigger_select,
2981                               NISTC_AO_TRIG_SEL_REG);
2982                 break;
2983         default:
2984                 BUG();
2985                 break;
2986         }
2987         devpriv->ao_trigger_select = val;
2988         ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG);
2989
2990         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2991         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2992
2993         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2994         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2995         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2996         if (cmd->stop_src == TRIG_NONE)
2997                 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
2998         else
2999                 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
3000         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3001         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3002         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3003         switch (cmd->stop_src) {
3004         case TRIG_COUNT:
3005                 if (devpriv->is_m_series) {
3006                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3007                         ni_stc_writel(dev, cmd->stop_arg - 1,
3008                                       NISTC_AO_UC_LOADA_REG);
3009                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3010                                       NISTC_AO_CMD1_REG);
3011                 } else {
3012                         ni_stc_writel(dev, cmd->stop_arg,
3013                                       NISTC_AO_UC_LOADA_REG);
3014                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3015                                       NISTC_AO_CMD1_REG);
3016                         ni_stc_writel(dev, cmd->stop_arg - 1,
3017                                       NISTC_AO_UC_LOADA_REG);
3018                 }
3019                 break;
3020         case TRIG_NONE:
3021                 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3022                 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3023                 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3024                 break;
3025         default:
3026                 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
3027                 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3028                 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
3029         }
3030
3031         devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
3032                                NISTC_AO_MODE1_UI_SRC_MASK |
3033                                NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3034                                NISTC_AO_MODE1_UI_SRC_POLARITY);
3035         switch (cmd->scan_begin_src) {
3036         case TRIG_TIMER:
3037                 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3038                 trigvar =
3039                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3040                                    CMDF_ROUND_NEAREST);
3041                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3042                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3043                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3044                 break;
3045         case TRIG_EXT:
3046                 devpriv->ao_mode1 |=
3047                     NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
3048                 if (cmd->scan_begin_arg & CR_INVERT)
3049                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3050                 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3051                 break;
3052         default:
3053                 BUG();
3054                 break;
3055         }
3056         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3057         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3058         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3059                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3060         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3061
3062         if (cmd->scan_end_arg > 1) {
3063                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3064                 ni_stc_writew(dev,
3065                               NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
3066                               NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
3067                               NISTC_AO_OUT_CTRL_REG);
3068         } else {
3069                 unsigned bits;
3070
3071                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3072                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3073                 if (devpriv->is_m_series || devpriv->is_6xxx) {
3074                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3075                 } else {
3076                         bits |=
3077                             NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
3078                 }
3079                 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3080         }
3081         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3082
3083         ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3084                            NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3085                       NISTC_AO_CMD1_REG);
3086
3087         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3088         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3089
3090         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3091 #ifdef PCIDMA
3092         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3093 #else
3094         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3095 #endif
3096         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3097         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3098
3099         bits = NISTC_AO_PERSONAL_BC_SRC_SEL |
3100                NISTC_AO_PERSONAL_UPDATE_PW |
3101                NISTC_AO_PERSONAL_TMRDACWR_PW;
3102         if (board->ao_fifo_depth)
3103                 bits |= NISTC_AO_PERSONAL_FIFO_ENA;
3104         else
3105                 bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL;
3106 #if 0
3107         /*
3108          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit
3109          * for 6281, verified with bus analyzer.
3110          */
3111         if (devpriv->is_m_series)
3112                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
3113 #endif
3114         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
3115         /*  enable sending of ao dma requests */
3116         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3117
3118         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3119
3120         if (cmd->stop_src == TRIG_COUNT) {
3121                 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3122                               NISTC_INTB_ACK_REG);
3123                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3124                             NISTC_INTB_ENA_AO_BC_TC, 1);
3125         }
3126
3127         s->async->inttrig = ni_ao_inttrig;
3128
3129         return 0;
3130 }
3131
3132 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3133                          struct comedi_cmd *cmd)
3134 {
3135         const struct ni_board_struct *board = dev->board_ptr;
3136         struct ni_private *devpriv = dev->private;
3137         int err = 0;
3138         unsigned int tmp;
3139
3140         /* Step 1 : check if triggers are trivially valid */
3141
3142         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3143         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3144                                         TRIG_TIMER | TRIG_EXT);
3145         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3146         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3147         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3148
3149         if (err)
3150                 return 1;
3151
3152         /* Step 2a : make sure trigger sources are unique */
3153
3154         err |= comedi_check_trigger_is_unique(cmd->start_src);
3155         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3156         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3157
3158         /* Step 2b : and mutually compatible */
3159
3160         if (err)
3161                 return 2;
3162
3163         /* Step 3: check if arguments are trivially valid */
3164
3165         switch (cmd->start_src) {
3166         case TRIG_INT:
3167                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3168                 break;
3169         case TRIG_EXT:
3170                 tmp = CR_CHAN(cmd->start_arg);
3171
3172                 if (tmp > 18)
3173                         tmp = 18;
3174                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3175                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3176                 break;
3177         }
3178
3179         if (cmd->scan_begin_src == TRIG_TIMER) {
3180                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3181                                                     board->ao_speed);
3182                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3183                                                     devpriv->clock_ns *
3184                                                     0xffffff);
3185         }
3186
3187         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3188         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3189                                            cmd->chanlist_len);
3190
3191         if (cmd->stop_src == TRIG_COUNT)
3192                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3193         else    /* TRIG_NONE */
3194                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3195
3196         if (err)
3197                 return 3;
3198
3199         /* step 4: fix up any arguments */
3200         if (cmd->scan_begin_src == TRIG_TIMER) {
3201                 tmp = cmd->scan_begin_arg;
3202                 cmd->scan_begin_arg =
3203                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3204                                                        cmd->scan_begin_arg,
3205                                                        cmd->flags));
3206                 if (tmp != cmd->scan_begin_arg)
3207                         err++;
3208         }
3209         if (err)
3210                 return 4;
3211
3212         return 0;
3213 }
3214
3215 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3216 {
3217         struct ni_private *devpriv = dev->private;
3218
3219         ni_release_ao_mite_channel(dev);
3220
3221         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3222         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3223         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3224         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3225         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3226         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL |
3227                            NISTC_AO_PERSONAL_UPDATE_PW |
3228                            NISTC_AO_PERSONAL_TMRDACWR_PW,
3229                       NISTC_AO_PERSONAL_REG);
3230         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3231         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3232         devpriv->ao_cmd1 = 0;
3233         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3234         devpriv->ao_cmd2 = 0;
3235         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3236         devpriv->ao_mode1 = 0;
3237         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3238         devpriv->ao_mode2 = 0;
3239         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3240         if (devpriv->is_m_series)
3241                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3242         else
3243                 devpriv->ao_mode3 = 0;
3244         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3245         devpriv->ao_trigger_select = 0;
3246         ni_stc_writew(dev, devpriv->ao_trigger_select,
3247                       NISTC_AO_TRIG_SEL_REG);
3248         if (devpriv->is_6xxx) {
3249                 unsigned immediate_bits = 0;
3250                 unsigned i;
3251
3252                 for (i = 0; i < s->n_chan; ++i)
3253                         immediate_bits |= 1 << i;
3254                 ni_ao_win_outw(dev, immediate_bits, NI671X_AO_IMMEDIATE_REG);
3255                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3256                                NI611X_AO_MISC_REG);
3257         }
3258         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3259
3260         return 0;
3261 }
3262
3263 /* digital io */
3264
3265 static int ni_dio_insn_config(struct comedi_device *dev,
3266                               struct comedi_subdevice *s,
3267                               struct comedi_insn *insn,
3268                               unsigned int *data)
3269 {
3270         struct ni_private *devpriv = dev->private;
3271         int ret;
3272
3273         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3274         if (ret)
3275                 return ret;
3276
3277         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3278         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3279         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3280
3281         return insn->n;
3282 }
3283
3284 static int ni_dio_insn_bits(struct comedi_device *dev,
3285                             struct comedi_subdevice *s,
3286                             struct comedi_insn *insn,
3287                             unsigned int *data)
3288 {
3289         struct ni_private *devpriv = dev->private;
3290
3291         /* Make sure we're not using the serial part of the dio */
3292         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3293             devpriv->serial_interval_ns)
3294                 return -EBUSY;
3295
3296         if (comedi_dio_update_state(s, data)) {
3297                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3298                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3299                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3300         }
3301
3302         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3303
3304         return insn->n;
3305 }
3306
3307 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3308                                        struct comedi_subdevice *s,
3309                                        struct comedi_insn *insn,
3310                                        unsigned int *data)
3311 {
3312         int ret;
3313
3314         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3315         if (ret)
3316                 return ret;
3317
3318         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3319
3320         return insn->n;
3321 }
3322
3323 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3324                                      struct comedi_subdevice *s,
3325                                      struct comedi_insn *insn,
3326                                      unsigned int *data)
3327 {
3328         if (comedi_dio_update_state(s, data))
3329                 ni_writel(dev, s->state, NI_M_DIO_REG);
3330
3331         data[1] = ni_readl(dev, NI_M_DIO_REG);
3332
3333         return insn->n;
3334 }
3335
3336 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3337                                   struct comedi_subdevice *s,
3338                                   struct comedi_cmd *cmd)
3339 {
3340         int i;
3341
3342         for (i = 0; i < cmd->chanlist_len; ++i) {
3343                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3344
3345                 if (chan != i)
3346                         return -EINVAL;
3347         }
3348
3349         return 0;
3350 }
3351
3352 static int ni_cdio_cmdtest(struct comedi_device *dev,
3353                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3354 {
3355         int err = 0;
3356         int tmp;
3357
3358         /* Step 1 : check if triggers are trivially valid */
3359
3360         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3361         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3362         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3363         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3364         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3365
3366         if (err)
3367                 return 1;
3368
3369         /* Step 2a : make sure trigger sources are unique */
3370         /* Step 2b : and mutually compatible */
3371
3372         /* Step 3: check if arguments are trivially valid */
3373
3374         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3375
3376         tmp = cmd->scan_begin_arg;
3377         tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3378         if (tmp != cmd->scan_begin_arg)
3379                 err |= -EINVAL;
3380
3381         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3382         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3383                                            cmd->chanlist_len);
3384         err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3385
3386         if (err)
3387                 return 3;
3388
3389         /* Step 4: fix up any arguments */
3390
3391         /* Step 5: check channel list if it exists */
3392
3393         if (cmd->chanlist && cmd->chanlist_len > 0)
3394                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3395
3396         if (err)
3397                 return 5;
3398
3399         return 0;
3400 }
3401
3402 static int ni_cdo_inttrig(struct comedi_device *dev,
3403                           struct comedi_subdevice *s,
3404                           unsigned int trig_num)
3405 {
3406         struct comedi_cmd *cmd = &s->async->cmd;
3407         const unsigned timeout = 1000;
3408         int retval = 0;
3409         unsigned i;
3410 #ifdef PCIDMA
3411         struct ni_private *devpriv = dev->private;
3412         unsigned long flags;
3413 #endif
3414
3415         if (trig_num != cmd->start_arg)
3416                 return -EINVAL;
3417
3418         s->async->inttrig = NULL;
3419
3420         /* read alloc the entire buffer */
3421         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3422
3423 #ifdef PCIDMA
3424         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3425         if (devpriv->cdo_mite_chan) {
3426                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3427                 mite_dma_arm(devpriv->cdo_mite_chan);
3428         } else {
3429                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3430                 retval = -EIO;
3431         }
3432         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3433         if (retval < 0)
3434                 return retval;
3435 #endif
3436         /*
3437          * XXX not sure what interrupt C group does
3438          * wait for dma to fill output fifo
3439          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3440          */
3441         for (i = 0; i < timeout; ++i) {
3442                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3443                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3444                         break;
3445                 udelay(10);
3446         }
3447         if (i == timeout) {
3448                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3449                 s->cancel(dev, s);
3450                 return -EIO;
3451         }
3452         ni_writel(dev, NI_M_CDO_CMD_ARM |
3453                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3454                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3455                   NI_M_CDIO_CMD_REG);
3456         return retval;
3457 }
3458
3459 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3460 {
3461         const struct comedi_cmd *cmd = &s->async->cmd;
3462         unsigned cdo_mode_bits;
3463         int retval;
3464
3465         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3466         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3467                         NI_M_CDO_MODE_HALT_ON_ERROR |
3468                         NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3469         if (cmd->scan_begin_arg & CR_INVERT)
3470                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3471         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3472         if (s->io_bits) {
3473                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3474                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3475                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3476         } else {
3477                 dev_err(dev->class_dev,
3478                         "attempted to run digital output command with no lines configured as outputs\n");
3479                 return -EIO;
3480         }
3481         retval = ni_request_cdo_mite_channel(dev);
3482         if (retval < 0)
3483                 return retval;
3484
3485         s->async->inttrig = ni_cdo_inttrig;
3486
3487         return 0;
3488 }
3489
3490 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3491 {
3492         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3493                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3494                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3495                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3496                   NI_M_CDIO_CMD_REG);
3497         /*
3498          * XXX not sure what interrupt C group does
3499          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3500          */
3501         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3502         ni_release_cdo_mite_channel(dev);
3503         return 0;
3504 }
3505
3506 static void handle_cdio_interrupt(struct comedi_device *dev)
3507 {
3508         struct ni_private *devpriv = dev->private;
3509         unsigned cdio_status;
3510         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3511 #ifdef PCIDMA
3512         unsigned long flags;
3513 #endif
3514
3515         if (!devpriv->is_m_series)
3516                 return;
3517 #ifdef PCIDMA
3518         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3519         if (devpriv->cdo_mite_chan) {
3520                 unsigned cdo_mite_status =
3521                     mite_get_status(devpriv->cdo_mite_chan);
3522                 if (cdo_mite_status & CHSR_LINKC) {
3523                         writel(CHOR_CLRLC,
3524                                devpriv->mite->mite_io_addr +
3525                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3526                 }
3527                 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3528         }
3529         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3530 #endif
3531
3532         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3533         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3534                 /* XXX just guessing this is needed and does something useful */
3535                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3536                           NI_M_CDIO_CMD_REG);
3537                 s->async->events |= COMEDI_CB_OVERFLOW;
3538         }
3539         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3540                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3541                           NI_M_CDIO_CMD_REG);
3542                 /* s->async->events |= COMEDI_CB_EOA; */
3543         }
3544         comedi_handle_events(dev, s);
3545 }
3546
3547 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3548                                    struct comedi_subdevice *s,
3549                                    unsigned char data_out,
3550                                    unsigned char *data_in)
3551 {
3552         struct ni_private *devpriv = dev->private;
3553         unsigned int status1;
3554         int err = 0, count = 20;
3555
3556         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3557         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3558         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3559
3560         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3561         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3562                 err = -EBUSY;
3563                 goto Error;
3564         }
3565
3566         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3567         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3568         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3569
3570         /* Wait until STC says we're done, but don't loop infinitely. */
3571         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3572                NISTC_STATUS1_SERIO_IN_PROG) {
3573                 /* Delay one bit per loop */
3574                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3575                 if (--count < 0) {
3576                         dev_err(dev->class_dev,
3577                                 "SPI serial I/O didn't finish in time!\n");
3578                         err = -ETIME;
3579                         goto Error;
3580                 }
3581         }
3582
3583         /*
3584          * Delay for last bit. This delay is absolutely necessary, because
3585          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3586          */
3587         udelay((devpriv->serial_interval_ns + 999) / 1000);
3588
3589         if (data_in)
3590                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3591
3592 Error:
3593         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3594
3595         return err;
3596 }
3597
3598 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3599                                    struct comedi_subdevice *s,
3600                                    unsigned char data_out,
3601                                    unsigned char *data_in)
3602 {
3603         struct ni_private *devpriv = dev->private;
3604         unsigned char mask, input = 0;
3605
3606         /* Wait for one bit before transfer */
3607         udelay((devpriv->serial_interval_ns + 999) / 1000);
3608
3609         for (mask = 0x80; mask; mask >>= 1) {
3610                 /* Output current bit; note that we cannot touch s->state
3611                    because it is a per-subdevice field, and serial is
3612                    a separate subdevice from DIO. */
3613                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3614                 if (data_out & mask)
3615                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3616                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3617
3618                 /* Assert SDCLK (active low, inverted), wait for half of
3619                    the delay, deassert SDCLK, and wait for the other half. */
3620                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3621                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3622
3623                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3624
3625                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3626                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3627
3628                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3629
3630                 /* Input current bit */
3631                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3632                         input |= mask;
3633         }
3634
3635         if (data_in)
3636                 *data_in = input;
3637
3638         return 0;
3639 }
3640
3641 static int ni_serial_insn_config(struct comedi_device *dev,
3642                                  struct comedi_subdevice *s,
3643                                  struct comedi_insn *insn,
3644                                  unsigned int *data)
3645 {
3646         struct ni_private *devpriv = dev->private;
3647         unsigned clk_fout = devpriv->clock_and_fout;
3648         int err = insn->n;
3649         unsigned char byte_out, byte_in = 0;
3650
3651         if (insn->n != 2)
3652                 return -EINVAL;
3653
3654         switch (data[0]) {
3655         case INSN_CONFIG_SERIAL_CLOCK:
3656                 devpriv->serial_hw_mode = 1;
3657                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3658
3659                 if (data[1] == SERIAL_DISABLED) {
3660                         devpriv->serial_hw_mode = 0;
3661                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3662                                                   NISTC_DIO_SDCLK);
3663                         data[1] = SERIAL_DISABLED;
3664                         devpriv->serial_interval_ns = data[1];
3665                 } else if (data[1] <= SERIAL_600NS) {
3666                         /* Warning: this clock speed is too fast to reliably
3667                            control SCXI. */
3668                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3669                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3670                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3671                         data[1] = SERIAL_600NS;
3672                         devpriv->serial_interval_ns = data[1];
3673                 } else if (data[1] <= SERIAL_1_2US) {
3674                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3675                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3676                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3677                         data[1] = SERIAL_1_2US;
3678                         devpriv->serial_interval_ns = data[1];
3679                 } else if (data[1] <= SERIAL_10US) {
3680                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3681                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3682                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3683                         /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3684                            600ns/1.2us. If you turn divide_by_2 off with the
3685                            slow clock, you will still get 10us, except then
3686                            all your delays are wrong. */
3687                         data[1] = SERIAL_10US;
3688                         devpriv->serial_interval_ns = data[1];
3689                 } else {
3690                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3691                                                   NISTC_DIO_SDCLK);
3692                         devpriv->serial_hw_mode = 0;
3693                         data[1] = (data[1] / 1000) * 1000;
3694                         devpriv->serial_interval_ns = data[1];
3695                 }
3696                 devpriv->clock_and_fout = clk_fout;
3697
3698                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3699                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3700                 return 1;
3701
3702         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3703
3704                 if (devpriv->serial_interval_ns == 0)
3705                         return -EINVAL;
3706
3707                 byte_out = data[1] & 0xFF;
3708
3709                 if (devpriv->serial_hw_mode) {
3710                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3711                                                       &byte_in);
3712                 } else if (devpriv->serial_interval_ns > 0) {
3713                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3714                                                       &byte_in);
3715                 } else {
3716                         dev_err(dev->class_dev, "serial disabled!\n");
3717                         return -EINVAL;
3718                 }
3719                 if (err < 0)
3720                         return err;
3721                 data[1] = byte_in & 0xFF;
3722                 return insn->n;
3723
3724                 break;
3725         default:
3726                 return -EINVAL;
3727         }
3728 }
3729
3730 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3731 {
3732         int i;
3733
3734         for (i = 0; i < s->n_chan; i++) {
3735                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3736                                NI67XX_AO_CFG2_REG);
3737         }
3738         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3739 }
3740
3741 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3742         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3743         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
3744         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3745         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3746         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
3747         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
3748         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
3749         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
3750         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3751         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3752         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3753         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3754         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3755         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3756         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3757         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3758         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3759         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3760         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3761         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3762         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
3763         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
3764         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
3765         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
3766         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3767         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3768         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3769         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3770         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3771         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3772         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3773         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3774         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
3775         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
3776         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
3777         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
3778 };
3779
3780 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3781                                             enum ni_gpct_register reg)
3782 {
3783         const struct mio_regmap *regmap;
3784
3785         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3786                 regmap = &ni_gpct_to_stc_regmap[reg];
3787         } else {
3788                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3789                          __func__, reg);
3790                 return 0;
3791         }
3792
3793         return regmap->mio_reg;
3794 }
3795
3796 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3797                                    enum ni_gpct_register reg)
3798 {
3799         struct comedi_device *dev = counter->counter_dev->dev;
3800         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3801         static const unsigned gpct_interrupt_a_enable_mask =
3802             NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
3803         static const unsigned gpct_interrupt_b_enable_mask =
3804             NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
3805
3806         if (stc_register == 0)
3807                 return;
3808
3809         switch (reg) {
3810                 /* m-series only registers */
3811         case NITIO_G0_CNT_MODE:
3812         case NITIO_G1_CNT_MODE:
3813         case NITIO_G0_GATE2:
3814         case NITIO_G1_GATE2:
3815         case NITIO_G0_DMA_CFG:
3816         case NITIO_G1_DMA_CFG:
3817         case NITIO_G0_ABZ:
3818         case NITIO_G1_ABZ:
3819                 ni_writew(dev, bits, stc_register);
3820                 break;
3821
3822                 /* 32 bit registers */
3823         case NITIO_G0_LOADA:
3824         case NITIO_G1_LOADA:
3825         case NITIO_G0_LOADB:
3826         case NITIO_G1_LOADB:
3827                 ni_stc_writel(dev, bits, stc_register);
3828                 break;
3829
3830                 /* 16 bit registers */
3831         case NITIO_G0_INT_ENA:
3832                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3833                 ni_set_bitfield(dev, stc_register,
3834                                 gpct_interrupt_a_enable_mask, bits);
3835                 break;
3836         case NITIO_G1_INT_ENA:
3837                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3838                 ni_set_bitfield(dev, stc_register,
3839                                 gpct_interrupt_b_enable_mask, bits);
3840                 break;
3841         case NITIO_G01_RESET:
3842                 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
3843                 /* fall-through */
3844         default:
3845                 ni_stc_writew(dev, bits, stc_register);
3846         }
3847 }
3848
3849 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3850                                       enum ni_gpct_register reg)
3851 {
3852         struct comedi_device *dev = counter->counter_dev->dev;
3853         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3854
3855         if (stc_register == 0)
3856                 return 0;
3857
3858         switch (reg) {
3859                 /* m-series only registers */
3860         case NITIO_G0_DMA_STATUS:
3861         case NITIO_G1_DMA_STATUS:
3862                 return ni_readw(dev, stc_register);
3863
3864                 /* 32 bit registers */
3865         case NITIO_G0_HW_SAVE:
3866         case NITIO_G1_HW_SAVE:
3867         case NITIO_G0_SW_SAVE:
3868         case NITIO_G1_SW_SAVE:
3869                 return ni_stc_readl(dev, stc_register);
3870
3871                 /* 16 bit registers */
3872         default:
3873                 return ni_stc_readw(dev, stc_register);
3874         }
3875 }
3876
3877 static int ni_freq_out_insn_read(struct comedi_device *dev,
3878                                  struct comedi_subdevice *s,
3879                                  struct comedi_insn *insn,
3880                                  unsigned int *data)
3881 {
3882         struct ni_private *devpriv = dev->private;
3883         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
3884         int i;
3885
3886         for (i = 0; i < insn->n; i++)
3887                 data[i] = val;
3888
3889         return insn->n;
3890 }
3891
3892 static int ni_freq_out_insn_write(struct comedi_device *dev,
3893                                   struct comedi_subdevice *s,
3894                                   struct comedi_insn *insn,
3895                                   unsigned int *data)
3896 {
3897         struct ni_private *devpriv = dev->private;
3898
3899         if (insn->n) {
3900                 unsigned int val = data[insn->n - 1];
3901
3902                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
3903                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3904                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
3905
3906                 /* use the last data value to set the fout divider */
3907                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
3908
3909                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
3910                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3911         }
3912         return insn->n;
3913 }
3914
3915 static int ni_freq_out_insn_config(struct comedi_device *dev,
3916                                    struct comedi_subdevice *s,
3917                                    struct comedi_insn *insn,
3918                                    unsigned int *data)
3919 {
3920         struct ni_private *devpriv = dev->private;
3921
3922         switch (data[0]) {
3923         case INSN_CONFIG_SET_CLOCK_SRC:
3924                 switch (data[1]) {
3925                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3926                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
3927                         break;
3928                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3929                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
3930                         break;
3931                 default:
3932                         return -EINVAL;
3933                 }
3934                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3935                 break;
3936         case INSN_CONFIG_GET_CLOCK_SRC:
3937                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
3938                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3939                         data[2] = TIMEBASE_2_NS;
3940                 } else {
3941                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3942                         data[2] = TIMEBASE_1_NS * 2;
3943                 }
3944                 break;
3945         default:
3946                 return -EINVAL;
3947         }
3948         return insn->n;
3949 }
3950
3951 static int ni_8255_callback(struct comedi_device *dev,
3952                             int dir, int port, int data, unsigned long iobase)
3953 {
3954         if (dir) {
3955                 ni_writeb(dev, data, iobase + 2 * port);
3956                 return 0;
3957         }
3958
3959         return ni_readb(dev, iobase + 2 * port);
3960 }
3961
3962 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3963 {
3964         struct ni_private *devpriv = dev->private;
3965
3966         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3967         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3968         return 3;
3969 }
3970
3971 static int ni_m_series_pwm_config(struct comedi_device *dev,
3972                                   struct comedi_subdevice *s,
3973                                   struct comedi_insn *insn,
3974                                   unsigned int *data)
3975 {
3976         struct ni_private *devpriv = dev->private;
3977         unsigned up_count, down_count;
3978
3979         switch (data[0]) {
3980         case INSN_CONFIG_PWM_OUTPUT:
3981                 switch (data[1]) {
3982                 case CMDF_ROUND_NEAREST:
3983                         up_count =
3984                             (data[2] +
3985                              devpriv->clock_ns / 2) / devpriv->clock_ns;
3986                         break;
3987                 case CMDF_ROUND_DOWN:
3988                         up_count = data[2] / devpriv->clock_ns;
3989                         break;
3990                 case CMDF_ROUND_UP:
3991                         up_count =
3992                             (data[2] + devpriv->clock_ns -
3993                              1) / devpriv->clock_ns;
3994                         break;
3995                 default:
3996                         return -EINVAL;
3997                 }
3998                 switch (data[3]) {
3999                 case CMDF_ROUND_NEAREST:
4000                         down_count =
4001                             (data[4] +
4002                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4003                         break;
4004                 case CMDF_ROUND_DOWN:
4005                         down_count = data[4] / devpriv->clock_ns;
4006                         break;
4007                 case CMDF_ROUND_UP:
4008                         down_count =
4009                             (data[4] + devpriv->clock_ns -
4010                              1) / devpriv->clock_ns;
4011                         break;
4012                 default:
4013                         return -EINVAL;
4014                 }
4015                 if (up_count * devpriv->clock_ns != data[2] ||
4016                     down_count * devpriv->clock_ns != data[4]) {
4017                         data[2] = up_count * devpriv->clock_ns;
4018                         data[4] = down_count * devpriv->clock_ns;
4019                         return -EAGAIN;
4020                 }
4021                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4022                                NI_M_CAL_PWM_LOW_TIME(down_count),
4023                           NI_M_CAL_PWM_REG);
4024                 devpriv->pwm_up_count = up_count;
4025                 devpriv->pwm_down_count = down_count;
4026                 return 5;
4027         case INSN_CONFIG_GET_PWM_OUTPUT:
4028                 return ni_get_pwm_config(dev, data);
4029         default:
4030                 return -EINVAL;
4031         }
4032         return 0;
4033 }
4034
4035 static int ni_6143_pwm_config(struct comedi_device *dev,
4036                               struct comedi_subdevice *s,
4037                               struct comedi_insn *insn,
4038                               unsigned int *data)
4039 {
4040         struct ni_private *devpriv = dev->private;
4041         unsigned up_count, down_count;
4042
4043         switch (data[0]) {
4044         case INSN_CONFIG_PWM_OUTPUT:
4045                 switch (data[1]) {
4046                 case CMDF_ROUND_NEAREST:
4047                         up_count =
4048                             (data[2] +
4049                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4050                         break;
4051                 case CMDF_ROUND_DOWN:
4052                         up_count = data[2] / devpriv->clock_ns;
4053                         break;
4054                 case CMDF_ROUND_UP:
4055                         up_count =
4056                             (data[2] + devpriv->clock_ns -
4057                              1) / devpriv->clock_ns;
4058                         break;
4059                 default:
4060                         return -EINVAL;
4061                 }
4062                 switch (data[3]) {
4063                 case CMDF_ROUND_NEAREST:
4064                         down_count =
4065                             (data[4] +
4066                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4067                         break;
4068                 case CMDF_ROUND_DOWN:
4069                         down_count = data[4] / devpriv->clock_ns;
4070                         break;
4071                 case CMDF_ROUND_UP:
4072                         down_count =
4073                             (data[4] + devpriv->clock_ns -
4074                              1) / devpriv->clock_ns;
4075                         break;
4076                 default:
4077                         return -EINVAL;
4078                 }
4079                 if (up_count * devpriv->clock_ns != data[2] ||
4080                     down_count * devpriv->clock_ns != data[4]) {
4081                         data[2] = up_count * devpriv->clock_ns;
4082                         data[4] = down_count * devpriv->clock_ns;
4083                         return -EAGAIN;
4084                 }
4085                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4086                 devpriv->pwm_up_count = up_count;
4087                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4088                 devpriv->pwm_down_count = down_count;
4089                 return 5;
4090         case INSN_CONFIG_GET_PWM_OUTPUT:
4091                 return ni_get_pwm_config(dev, data);
4092         default:
4093                 return -EINVAL;
4094         }
4095         return 0;
4096 }
4097
4098 static int pack_mb88341(int addr, int val, int *bitstring)
4099 {
4100         /*
4101            Fujitsu MB 88341
4102            Note that address bits are reversed.  Thanks to
4103            Ingo Keen for noticing this.
4104
4105            Note also that the 88341 expects address values from
4106            1-12, whereas we use channel numbers 0-11.  The NI
4107            docs use 1-12, also, so be careful here.
4108          */
4109         addr++;
4110         *bitstring = ((addr & 0x1) << 11) |
4111             ((addr & 0x2) << 9) |
4112             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4113         return 12;
4114 }
4115
4116 static int pack_dac8800(int addr, int val, int *bitstring)
4117 {
4118         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4119         return 11;
4120 }
4121
4122 static int pack_dac8043(int addr, int val, int *bitstring)
4123 {
4124         *bitstring = val & 0xfff;
4125         return 12;
4126 }
4127
4128 static int pack_ad8522(int addr, int val, int *bitstring)
4129 {
4130         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4131         return 16;
4132 }
4133
4134 static int pack_ad8804(int addr, int val, int *bitstring)
4135 {
4136         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4137         return 12;
4138 }
4139
4140 static int pack_ad8842(int addr, int val, int *bitstring)
4141 {
4142         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4143         return 12;
4144 }
4145
4146 struct caldac_struct {
4147         int n_chans;
4148         int n_bits;
4149         int (*packbits)(int, int, int *);
4150 };
4151
4152 static struct caldac_struct caldacs[] = {
4153         [mb88341] = {12, 8, pack_mb88341},
4154         [dac8800] = {8, 8, pack_dac8800},
4155         [dac8043] = {1, 12, pack_dac8043},
4156         [ad8522] = {2, 12, pack_ad8522},
4157         [ad8804] = {12, 8, pack_ad8804},
4158         [ad8842] = {8, 8, pack_ad8842},
4159         [ad8804_debug] = {16, 8, pack_ad8804},
4160 };
4161
4162 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4163 {
4164         const struct ni_board_struct *board = dev->board_ptr;
4165         struct ni_private *devpriv = dev->private;
4166         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4167         unsigned int cmd;
4168         int i;
4169         int type;
4170
4171         if (devpriv->caldacs[addr] == val)
4172                 return;
4173         devpriv->caldacs[addr] = val;
4174
4175         for (i = 0; i < 3; i++) {
4176                 type = board->caldac[i];
4177                 if (type == caldac_none)
4178                         break;
4179                 if (addr < caldacs[type].n_chans) {
4180                         bits = caldacs[type].packbits(addr, val, &bitstring);
4181                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4182                         break;
4183                 }
4184                 addr -= caldacs[type].n_chans;
4185         }
4186
4187         /* bits will be 0 if there is no caldac for the given addr */
4188         if (bits == 0)
4189                 return;
4190
4191         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4192                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4193                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4194                 udelay(1);
4195                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4196                 udelay(1);
4197         }
4198         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4199         udelay(1);
4200         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4201 }
4202
4203 static int ni_calib_insn_write(struct comedi_device *dev,
4204                                struct comedi_subdevice *s,
4205                                struct comedi_insn *insn,
4206                                unsigned int *data)
4207 {
4208         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4209
4210         return 1;
4211 }
4212
4213 static int ni_calib_insn_read(struct comedi_device *dev,
4214                               struct comedi_subdevice *s,
4215                               struct comedi_insn *insn,
4216                               unsigned int *data)
4217 {
4218         struct ni_private *devpriv = dev->private;
4219
4220         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4221
4222         return 1;
4223 }
4224
4225 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4226 {
4227         const struct ni_board_struct *board = dev->board_ptr;
4228         struct ni_private *devpriv = dev->private;
4229         int i, j;
4230         int n_dacs;
4231         int n_chans = 0;
4232         int n_bits;
4233         int diffbits = 0;
4234         int type;
4235         int chan;
4236
4237         type = board->caldac[0];
4238         if (type == caldac_none)
4239                 return;
4240         n_bits = caldacs[type].n_bits;
4241         for (i = 0; i < 3; i++) {
4242                 type = board->caldac[i];
4243                 if (type == caldac_none)
4244                         break;
4245                 if (caldacs[type].n_bits != n_bits)
4246                         diffbits = 1;
4247                 n_chans += caldacs[type].n_chans;
4248         }
4249         n_dacs = i;
4250         s->n_chan = n_chans;
4251
4252         if (diffbits) {
4253                 unsigned int *maxdata_list;
4254
4255                 if (n_chans > MAX_N_CALDACS)
4256                         dev_err(dev->class_dev,
4257                                 "BUG! MAX_N_CALDACS too small\n");
4258                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4259                 chan = 0;
4260                 for (i = 0; i < n_dacs; i++) {
4261                         type = board->caldac[i];
4262                         for (j = 0; j < caldacs[type].n_chans; j++) {
4263                                 maxdata_list[chan] =
4264                                     (1 << caldacs[type].n_bits) - 1;
4265                                 chan++;
4266                         }
4267                 }
4268
4269                 for (chan = 0; chan < s->n_chan; chan++)
4270                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4271         } else {
4272                 type = board->caldac[0];
4273                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4274
4275                 for (chan = 0; chan < s->n_chan; chan++)
4276                         ni_write_caldac(dev, i, s->maxdata / 2);
4277         }
4278 }
4279
4280 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4281 {
4282         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4283         int bit;
4284         int bitstring;
4285
4286         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4287         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4288         for (bit = 0x8000; bit; bit >>= 1) {
4289                 if (bit & bitstring)
4290                         cmd |= NI_E_SERIAL_CMD_SDATA;
4291                 else
4292                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4293
4294                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4295                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4296         }
4297         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4298         bitstring = 0;
4299         for (bit = 0x80; bit; bit >>= 1) {
4300                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4301                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4302                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4303                         bitstring |= bit;
4304         }
4305         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4306
4307         return bitstring;
4308 }
4309
4310 static int ni_eeprom_insn_read(struct comedi_device *dev,
4311                                struct comedi_subdevice *s,
4312                                struct comedi_insn *insn,
4313                                unsigned int *data)
4314 {
4315         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4316
4317         return 1;
4318 }
4319
4320 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4321                                         struct comedi_subdevice *s,
4322                                         struct comedi_insn *insn,
4323                                         unsigned int *data)
4324 {
4325         struct ni_private *devpriv = dev->private;
4326
4327         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4328
4329         return 1;
4330 }
4331
4332 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4333                                        unsigned chan)
4334 {
4335         /*  pre-m-series boards have fixed signals on pfi pins */
4336         switch (chan) {
4337         case 0:
4338                 return NI_PFI_OUTPUT_AI_START1;
4339         case 1:
4340                 return NI_PFI_OUTPUT_AI_START2;
4341         case 2:
4342                 return NI_PFI_OUTPUT_AI_CONVERT;
4343         case 3:
4344                 return NI_PFI_OUTPUT_G_SRC1;
4345         case 4:
4346                 return NI_PFI_OUTPUT_G_GATE1;
4347         case 5:
4348                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4349         case 6:
4350                 return NI_PFI_OUTPUT_AO_START1;
4351         case 7:
4352                 return NI_PFI_OUTPUT_AI_START_PULSE;
4353         case 8:
4354                 return NI_PFI_OUTPUT_G_SRC0;
4355         case 9:
4356                 return NI_PFI_OUTPUT_G_GATE0;
4357         default:
4358                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4359                 break;
4360         }
4361         return 0;
4362 }
4363
4364 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4365                                   unsigned chan, unsigned source)
4366 {
4367         /*  pre-m-series boards have fixed signals on pfi pins */
4368         if (source != ni_old_get_pfi_routing(dev, chan))
4369                 return -EINVAL;
4370         return 2;
4371 }
4372
4373 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4374                                             unsigned chan)
4375 {
4376         struct ni_private *devpriv = dev->private;
4377         const unsigned array_offset = chan / 3;
4378
4379         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4380                                 devpriv->pfi_output_select_reg[array_offset]);
4381 }
4382
4383 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4384                                        unsigned chan, unsigned source)
4385 {
4386         struct ni_private *devpriv = dev->private;
4387         unsigned index = chan / 3;
4388         unsigned short val = devpriv->pfi_output_select_reg[index];
4389
4390         if ((source & 0x1f) != source)
4391                 return -EINVAL;
4392
4393         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4394         val |= NI_M_PFI_OUT_SEL(chan, source);
4395         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4396         devpriv->pfi_output_select_reg[index] = val;
4397
4398         return 2;
4399 }
4400
4401 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4402 {
4403         struct ni_private *devpriv = dev->private;
4404
4405         return (devpriv->is_m_series)
4406                         ? ni_m_series_get_pfi_routing(dev, chan)
4407                         : ni_old_get_pfi_routing(dev, chan);
4408 }
4409
4410 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4411                               unsigned source)
4412 {
4413         struct ni_private *devpriv = dev->private;
4414
4415         return (devpriv->is_m_series)
4416                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4417                         : ni_old_set_pfi_routing(dev, chan, source);
4418 }
4419
4420 static int ni_config_filter(struct comedi_device *dev,
4421                             unsigned pfi_channel,
4422                             enum ni_pfi_filter_select filter)
4423 {
4424         struct ni_private *devpriv = dev->private;
4425         unsigned bits;
4426
4427         if (!devpriv->is_m_series)
4428                 return -ENOTSUPP;
4429
4430         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4431         bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4432         bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4433         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4434         return 0;
4435 }
4436
4437 static int ni_pfi_insn_config(struct comedi_device *dev,
4438                               struct comedi_subdevice *s,
4439                               struct comedi_insn *insn,
4440                               unsigned int *data)
4441 {
4442         struct ni_private *devpriv = dev->private;
4443         unsigned int chan;
4444
4445         if (insn->n < 1)
4446                 return -EINVAL;
4447
4448         chan = CR_CHAN(insn->chanspec);
4449
4450         switch (data[0]) {
4451         case COMEDI_OUTPUT:
4452                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4453                 break;
4454         case COMEDI_INPUT:
4455                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4456                 break;
4457         case INSN_CONFIG_DIO_QUERY:
4458                 data[1] =
4459                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4460                     COMEDI_OUTPUT : COMEDI_INPUT;
4461                 return 0;
4462         case INSN_CONFIG_SET_ROUTING:
4463                 return ni_set_pfi_routing(dev, chan, data[1]);
4464         case INSN_CONFIG_GET_ROUTING:
4465                 data[1] = ni_get_pfi_routing(dev, chan);
4466                 break;
4467         case INSN_CONFIG_FILTER:
4468                 return ni_config_filter(dev, chan, data[1]);
4469         default:
4470                 return -EINVAL;
4471         }
4472         return 0;
4473 }
4474
4475 static int ni_pfi_insn_bits(struct comedi_device *dev,
4476                             struct comedi_subdevice *s,
4477                             struct comedi_insn *insn,
4478                             unsigned int *data)
4479 {
4480         struct ni_private *devpriv = dev->private;
4481
4482         if (!devpriv->is_m_series)
4483                 return -ENOTSUPP;
4484
4485         if (comedi_dio_update_state(s, data))
4486                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4487
4488         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4489
4490         return insn->n;
4491 }
4492
4493 static int cs5529_wait_for_idle(struct comedi_device *dev)
4494 {
4495         unsigned short status;
4496         const int timeout = HZ;
4497         int i;
4498
4499         for (i = 0; i < timeout; i++) {
4500                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4501                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4502                         break;
4503                 set_current_state(TASK_INTERRUPTIBLE);
4504                 if (schedule_timeout(1))
4505                         return -EIO;
4506         }
4507         if (i == timeout) {
4508                 dev_err(dev->class_dev, "timeout\n");
4509                 return -ETIME;
4510         }
4511         return 0;
4512 }
4513
4514 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4515 {
4516         static const int timeout = 100;
4517         int i;
4518
4519         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4520         /* give time for command to start being serially clocked into cs5529.
4521          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4522          * set before we exit this function.
4523          */
4524         for (i = 0; i < timeout; i++) {
4525                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4526                     NI67XX_CAL_STATUS_BUSY)
4527                         break;
4528                 udelay(1);
4529         }
4530         if (i == timeout)
4531                 dev_err(dev->class_dev,
4532                         "possible problem - never saw adc go busy?\n");
4533 }
4534
4535 static int cs5529_do_conversion(struct comedi_device *dev,
4536                                 unsigned short *data)
4537 {
4538         int retval;
4539         unsigned short status;
4540
4541         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4542         retval = cs5529_wait_for_idle(dev);
4543         if (retval) {
4544                 dev_err(dev->class_dev,
4545                         "timeout or signal in cs5529_do_conversion()\n");
4546                 return -ETIME;
4547         }
4548         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4549         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4550                 dev_err(dev->class_dev,
4551                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4552                 return -EIO;
4553         }
4554         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4555                 dev_err(dev->class_dev,
4556                         "cs5529 conversion error, overrange (ignoring)\n");
4557         }
4558         if (data) {
4559                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4560                 /* cs5529 returns 16 bit signed data in bipolar mode */
4561                 *data ^= (1 << 15);
4562         }
4563         return 0;
4564 }
4565
4566 static int cs5529_ai_insn_read(struct comedi_device *dev,
4567                                struct comedi_subdevice *s,
4568                                struct comedi_insn *insn,
4569                                unsigned int *data)
4570 {
4571         int n, retval;
4572         unsigned short sample;
4573         unsigned int channel_select;
4574         const unsigned int INTERNAL_REF = 0x1000;
4575
4576         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4577          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4578          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4579         if (insn->chanspec & CR_ALT_SOURCE)
4580                 channel_select = INTERNAL_REF;
4581         else
4582                 channel_select = CR_CHAN(insn->chanspec);
4583         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4584
4585         for (n = 0; n < insn->n; n++) {
4586                 retval = cs5529_do_conversion(dev, &sample);
4587                 if (retval < 0)
4588                         return retval;
4589                 data[n] = sample;
4590         }
4591         return insn->n;
4592 }
4593
4594 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4595                                 unsigned int reg_select_bits)
4596 {
4597         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4598         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4599         reg_select_bits &= CS5529_CMD_REG_MASK;
4600         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4601         if (cs5529_wait_for_idle(dev))
4602                 dev_err(dev->class_dev,
4603                         "timeout or signal in %s\n", __func__);
4604 }
4605
4606 static int init_cs5529(struct comedi_device *dev)
4607 {
4608         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4609                                    CS5529_CFG_WORD_RATE_2180;
4610
4611 #if 1
4612         /* do self-calibration */
4613         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4614                             CS5529_CFG_REG);
4615         /* need to force a conversion for calibration to run */
4616         cs5529_do_conversion(dev, NULL);
4617 #else
4618         /* force gain calibration to 1 */
4619         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4620         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4621                             CS5529_CFG_REG);
4622         if (cs5529_wait_for_idle(dev))
4623                 dev_err(dev->class_dev,
4624                         "timeout or signal in %s\n", __func__);
4625 #endif
4626         return 0;
4627 }
4628
4629 /*
4630  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4631  * given an arbitrary frequency input clock.
4632  */
4633 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4634                                          unsigned *freq_divider,
4635                                          unsigned *freq_multiplier,
4636                                          unsigned *actual_period_ns)
4637 {
4638         unsigned div;
4639         unsigned best_div = 1;
4640         unsigned mult;
4641         unsigned best_mult = 1;
4642         static const unsigned pico_per_nano = 1000;
4643
4644         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4645         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4646          * 20 MHz for most timing clocks */
4647         static const unsigned target_picosec = 12500;
4648         static const unsigned fudge_factor_80_to_20Mhz = 4;
4649         int best_period_picosec = 0;
4650
4651         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4652                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4653                         unsigned new_period_ps =
4654                             (reference_picosec * div) / mult;
4655                         if (abs(new_period_ps - target_picosec) <
4656                             abs(best_period_picosec - target_picosec)) {
4657                                 best_period_picosec = new_period_ps;
4658                                 best_div = div;
4659                                 best_mult = mult;
4660                         }
4661                 }
4662         }
4663         if (best_period_picosec == 0)
4664                 return -EIO;
4665
4666         *freq_divider = best_div;
4667         *freq_multiplier = best_mult;
4668         *actual_period_ns =
4669             (best_period_picosec * fudge_factor_80_to_20Mhz +
4670              (pico_per_nano / 2)) / pico_per_nano;
4671         return 0;
4672 }
4673
4674 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4675                                            unsigned source, unsigned period_ns)
4676 {
4677         struct ni_private *devpriv = dev->private;
4678         static const unsigned min_period_ns = 50;
4679         static const unsigned max_period_ns = 1000;
4680         static const unsigned timeout = 1000;
4681         unsigned pll_control_bits;
4682         unsigned freq_divider;
4683         unsigned freq_multiplier;
4684         unsigned rtsi;
4685         unsigned i;
4686         int retval;
4687
4688         if (source == NI_MIO_PLL_PXI10_CLOCK)
4689                 period_ns = 100;
4690         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4691         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4692                 dev_err(dev->class_dev,
4693                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4694                         __func__, min_period_ns, max_period_ns);
4695                 return -EINVAL;
4696         }
4697         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4698         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4699                       NISTC_RTSI_TRIG_DIR_REG);
4700         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4701         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4702                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4703         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4704         switch (source) {
4705         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4706                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4707                 break;
4708         case NI_MIO_PLL_PXI10_CLOCK:
4709                 /* pxi clock is 10MHz */
4710                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4711                 break;
4712         default:
4713                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4714                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4715                                 devpriv->clock_and_fout2 |=
4716                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4717                                 break;
4718                         }
4719                 }
4720                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4721                         return -EINVAL;
4722                 break;
4723         }
4724         retval = ni_mseries_get_pll_parameters(period_ns,
4725                                                &freq_divider,
4726                                                &freq_multiplier,
4727                                                &devpriv->clock_ns);
4728         if (retval < 0) {
4729                 dev_err(dev->class_dev,
4730                         "bug, failed to find pll parameters\n");
4731                 return retval;
4732         }
4733
4734         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4735         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4736                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4737
4738         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4739         devpriv->clock_source = source;
4740         /* it seems to typically take a few hundred microseconds for PLL to lock */
4741         for (i = 0; i < timeout; ++i) {
4742                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4743                         break;
4744                 udelay(1);
4745         }
4746         if (i == timeout) {
4747                 dev_err(dev->class_dev,
4748                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4749                         __func__, source, period_ns);
4750                 return -ETIMEDOUT;
4751         }
4752         return 3;
4753 }
4754
4755 static int ni_set_master_clock(struct comedi_device *dev,
4756                                unsigned source, unsigned period_ns)
4757 {
4758         struct ni_private *devpriv = dev->private;
4759
4760         if (source == NI_MIO_INTERNAL_CLOCK) {
4761                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4762                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4763                               NISTC_RTSI_TRIG_DIR_REG);
4764                 devpriv->clock_ns = TIMEBASE_1_NS;
4765                 if (devpriv->is_m_series) {
4766                         devpriv->clock_and_fout2 &=
4767                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4768                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4769                         ni_writew(dev, devpriv->clock_and_fout2,
4770                                   NI_M_CLK_FOUT2_REG);
4771                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4772                 }
4773                 devpriv->clock_source = source;
4774         } else {
4775                 if (devpriv->is_m_series) {
4776                         return ni_mseries_set_pll_master_clock(dev, source,
4777                                                                period_ns);
4778                 } else {
4779                         if (source == NI_MIO_RTSI_CLOCK) {
4780                                 devpriv->rtsi_trig_direction_reg |=
4781                                     NISTC_RTSI_TRIG_USE_CLK;
4782                                 ni_stc_writew(dev,
4783                                               devpriv->rtsi_trig_direction_reg,
4784                                               NISTC_RTSI_TRIG_DIR_REG);
4785                                 if (period_ns == 0) {
4786                                         dev_err(dev->class_dev,
4787                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
4788                                         return -EINVAL;
4789                                 }
4790                                 devpriv->clock_ns = period_ns;
4791                                 devpriv->clock_source = source;
4792                         } else {
4793                                 return -EINVAL;
4794                         }
4795                 }
4796         }
4797         return 3;
4798 }
4799
4800 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4801                                        unsigned chan, unsigned source)
4802 {
4803         struct ni_private *devpriv = dev->private;
4804
4805         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4806                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4807                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4808                                 return 1;
4809
4810                         dev_err(dev->class_dev,
4811                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4812                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4813                         return 0;
4814                 }
4815                 return 0;
4816         }
4817         switch (source) {
4818         case NI_RTSI_OUTPUT_ADR_START1:
4819         case NI_RTSI_OUTPUT_ADR_START2:
4820         case NI_RTSI_OUTPUT_SCLKG:
4821         case NI_RTSI_OUTPUT_DACUPDN:
4822         case NI_RTSI_OUTPUT_DA_START1:
4823         case NI_RTSI_OUTPUT_G_SRC0:
4824         case NI_RTSI_OUTPUT_G_GATE0:
4825         case NI_RTSI_OUTPUT_RGOUT0:
4826         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4827                 return 1;
4828         case NI_RTSI_OUTPUT_RTSI_OSC:
4829                 return (devpriv->is_m_series) ? 1 : 0;
4830         default:
4831                 return 0;
4832         }
4833 }
4834
4835 static int ni_set_rtsi_routing(struct comedi_device *dev,
4836                                unsigned chan, unsigned src)
4837 {
4838         struct ni_private *devpriv = dev->private;
4839
4840         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4841                 return -EINVAL;
4842         if (chan < 4) {
4843                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4844                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
4845                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4846                               NISTC_RTSI_TRIGA_OUT_REG);
4847         } else if (chan < 8) {
4848                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4849                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
4850                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4851                               NISTC_RTSI_TRIGB_OUT_REG);
4852         }
4853         return 2;
4854 }
4855
4856 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4857 {
4858         struct ni_private *devpriv = dev->private;
4859
4860         if (chan < 4) {
4861                 return NISTC_RTSI_TRIG_TO_SRC(chan,
4862                                               devpriv->rtsi_trig_a_output_reg);
4863         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4864                 return NISTC_RTSI_TRIG_TO_SRC(chan,
4865                                               devpriv->rtsi_trig_b_output_reg);
4866         } else {
4867                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
4868                         return NI_RTSI_OUTPUT_RTSI_OSC;
4869                 dev_err(dev->class_dev, "bug! should never get here?\n");
4870                 return 0;
4871         }
4872 }
4873
4874 static int ni_rtsi_insn_config(struct comedi_device *dev,
4875                                struct comedi_subdevice *s,
4876                                struct comedi_insn *insn,
4877                                unsigned int *data)
4878 {
4879         struct ni_private *devpriv = dev->private;
4880         unsigned int chan = CR_CHAN(insn->chanspec);
4881         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
4882
4883         switch (data[0]) {
4884         case INSN_CONFIG_DIO_OUTPUT:
4885                 if (chan < max_chan) {
4886                         devpriv->rtsi_trig_direction_reg |=
4887                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4888                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4889                         devpriv->rtsi_trig_direction_reg |=
4890                             NISTC_RTSI_TRIG_DRV_CLK;
4891                 }
4892                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4893                               NISTC_RTSI_TRIG_DIR_REG);
4894                 break;
4895         case INSN_CONFIG_DIO_INPUT:
4896                 if (chan < max_chan) {
4897                         devpriv->rtsi_trig_direction_reg &=
4898                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4899                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4900                         devpriv->rtsi_trig_direction_reg &=
4901                             ~NISTC_RTSI_TRIG_DRV_CLK;
4902                 }
4903                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4904                               NISTC_RTSI_TRIG_DIR_REG);
4905                 break;
4906         case INSN_CONFIG_DIO_QUERY:
4907                 if (chan < max_chan) {
4908                         data[1] =
4909                             (devpriv->rtsi_trig_direction_reg &
4910                              NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
4911                                 ? INSN_CONFIG_DIO_OUTPUT
4912                                 : INSN_CONFIG_DIO_INPUT;
4913                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4914                         data[1] = (devpriv->rtsi_trig_direction_reg &
4915                                    NISTC_RTSI_TRIG_DRV_CLK)
4916                                   ? INSN_CONFIG_DIO_OUTPUT
4917                                   : INSN_CONFIG_DIO_INPUT;
4918                 }
4919                 return 2;
4920         case INSN_CONFIG_SET_CLOCK_SRC:
4921                 return ni_set_master_clock(dev, data[1], data[2]);
4922         case INSN_CONFIG_GET_CLOCK_SRC:
4923                 data[1] = devpriv->clock_source;
4924                 data[2] = devpriv->clock_ns;
4925                 return 3;
4926         case INSN_CONFIG_SET_ROUTING:
4927                 return ni_set_rtsi_routing(dev, chan, data[1]);
4928         case INSN_CONFIG_GET_ROUTING:
4929                 data[1] = ni_get_rtsi_routing(dev, chan);
4930                 return 2;
4931         default:
4932                 return -EINVAL;
4933         }
4934         return 1;
4935 }
4936
4937 static int ni_rtsi_insn_bits(struct comedi_device *dev,
4938                              struct comedi_subdevice *s,
4939                              struct comedi_insn *insn,
4940                              unsigned int *data)
4941 {
4942         data[1] = 0;
4943
4944         return insn->n;
4945 }
4946
4947 static void ni_rtsi_init(struct comedi_device *dev)
4948 {
4949         struct ni_private *devpriv = dev->private;
4950
4951         /*  Initialises the RTSI bus signal switch to a default state */
4952
4953         /*
4954          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4955          * to have no effect, at least on pxi-6281, which always uses
4956          * 20MHz rtsi clock frequency
4957          */
4958         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
4959         /*  Set clock mode to internal */
4960         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4961                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
4962         /*  default internal lines routing to RTSI bus lines */
4963         devpriv->rtsi_trig_a_output_reg =
4964             NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
4965             NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
4966             NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
4967             NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
4968         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4969                       NISTC_RTSI_TRIGA_OUT_REG);
4970         devpriv->rtsi_trig_b_output_reg =
4971             NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
4972             NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
4973             NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
4974         if (devpriv->is_m_series)
4975                 devpriv->rtsi_trig_b_output_reg |=
4976                     NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
4977         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4978                       NISTC_RTSI_TRIGB_OUT_REG);
4979
4980         /*
4981          * Sets the source and direction of the 4 on board lines
4982          * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
4983          */
4984 }
4985
4986 #ifdef PCIDMA
4987 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4988 {
4989         struct ni_gpct *counter = s->private;
4990         int retval;
4991
4992         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4993                                               COMEDI_INPUT);
4994         if (retval) {
4995                 dev_err(dev->class_dev,
4996                         "no dma channel available for use by counter\n");
4997                 return retval;
4998         }
4999         ni_tio_acknowledge(counter);
5000         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5001
5002         return ni_tio_cmd(dev, s);
5003 }
5004
5005 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5006 {
5007         struct ni_gpct *counter = s->private;
5008         int retval;
5009
5010         retval = ni_tio_cancel(counter);
5011         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5012         ni_release_gpct_mite_channel(dev, counter->counter_index);
5013         return retval;
5014 }
5015 #endif
5016
5017 static irqreturn_t ni_E_interrupt(int irq, void *d)
5018 {
5019         struct comedi_device *dev = d;
5020         unsigned short a_status;
5021         unsigned short b_status;
5022         unsigned int ai_mite_status = 0;
5023         unsigned int ao_mite_status = 0;
5024         unsigned long flags;
5025 #ifdef PCIDMA
5026         struct ni_private *devpriv = dev->private;
5027         struct mite_struct *mite = devpriv->mite;
5028 #endif
5029
5030         if (!dev->attached)
5031                 return IRQ_NONE;
5032         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
5033
5034         /*  lock to avoid race with comedi_poll */
5035         spin_lock_irqsave(&dev->spinlock, flags);
5036         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5037         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5038 #ifdef PCIDMA
5039         if (mite) {
5040                 struct ni_private *devpriv = dev->private;
5041                 unsigned long flags_too;
5042
5043                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5044                 if (devpriv->ai_mite_chan) {
5045                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5046                         if (ai_mite_status & CHSR_LINKC)
5047                                 writel(CHOR_CLRLC,
5048                                        devpriv->mite->mite_io_addr +
5049                                        MITE_CHOR(devpriv->
5050                                                  ai_mite_chan->channel));
5051                 }
5052                 if (devpriv->ao_mite_chan) {
5053                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5054                         if (ao_mite_status & CHSR_LINKC)
5055                                 writel(CHOR_CLRLC,
5056                                        mite->mite_io_addr +
5057                                        MITE_CHOR(devpriv->
5058                                                  ao_mite_chan->channel));
5059                 }
5060                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5061         }
5062 #endif
5063         ack_a_interrupt(dev, a_status);
5064         ack_b_interrupt(dev, b_status);
5065         if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
5066                 handle_a_interrupt(dev, a_status, ai_mite_status);
5067         if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
5068                 handle_b_interrupt(dev, b_status, ao_mite_status);
5069         handle_gpct_interrupt(dev, 0);
5070         handle_gpct_interrupt(dev, 1);
5071         handle_cdio_interrupt(dev);
5072
5073         spin_unlock_irqrestore(&dev->spinlock, flags);
5074         return IRQ_HANDLED;
5075 }
5076
5077 static int ni_alloc_private(struct comedi_device *dev)
5078 {
5079         struct ni_private *devpriv;
5080
5081         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5082         if (!devpriv)
5083                 return -ENOMEM;
5084
5085         spin_lock_init(&devpriv->window_lock);
5086         spin_lock_init(&devpriv->soft_reg_copy_lock);
5087         spin_lock_init(&devpriv->mite_channel_lock);
5088
5089         return 0;
5090 }
5091
5092 static int ni_E_init(struct comedi_device *dev,
5093                      unsigned interrupt_pin, unsigned irq_polarity)
5094 {
5095         const struct ni_board_struct *board = dev->board_ptr;
5096         struct ni_private *devpriv = dev->private;
5097         struct comedi_subdevice *s;
5098         int ret;
5099         int i;
5100
5101         if (board->n_aochan > MAX_N_AO_CHAN) {
5102                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5103                 return -EINVAL;
5104         }
5105
5106         /* initialize clock dividers */
5107         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5108                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
5109                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5110                                   NISTC_CLK_FOUT_TO_BOARD;
5111         if (!devpriv->is_6xxx) {
5112                 /* BEAM is this needed for PCI-6143 ?? */
5113                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5114                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
5115         }
5116         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5117
5118         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5119         if (ret)
5120                 return ret;
5121
5122         /* Analog Input subdevice */
5123         s = &dev->subdevices[NI_AI_SUBDEV];
5124         if (board->n_adchan) {
5125                 s->type         = COMEDI_SUBD_AI;
5126                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5127                 if (!devpriv->is_611x)
5128                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5129                 if (board->ai_maxdata > 0xffff)
5130                         s->subdev_flags |= SDF_LSAMPL;
5131                 if (devpriv->is_m_series)
5132                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5133                 s->n_chan       = board->n_adchan;
5134                 s->maxdata      = board->ai_maxdata;
5135                 s->range_table  = ni_range_lkup[board->gainlkup];
5136                 s->insn_read    = ni_ai_insn_read;
5137                 s->insn_config  = ni_ai_insn_config;
5138                 if (dev->irq) {
5139                         dev->read_subdev = s;
5140                         s->subdev_flags |= SDF_CMD_READ;
5141                         s->len_chanlist = 512;
5142                         s->do_cmdtest   = ni_ai_cmdtest;
5143                         s->do_cmd       = ni_ai_cmd;
5144                         s->cancel       = ni_ai_reset;
5145                         s->poll         = ni_ai_poll;
5146                         s->munge        = ni_ai_munge;
5147
5148                         if (devpriv->mite)
5149                                 s->async_dma_dir = DMA_FROM_DEVICE;
5150                 }
5151
5152                 /* reset the analog input configuration */
5153                 ni_ai_reset(dev, s);
5154         } else {
5155                 s->type         = COMEDI_SUBD_UNUSED;
5156         }
5157
5158         /* Analog Output subdevice */
5159         s = &dev->subdevices[NI_AO_SUBDEV];
5160         if (board->n_aochan) {
5161                 s->type         = COMEDI_SUBD_AO;
5162                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5163                 if (devpriv->is_m_series)
5164                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5165                 s->n_chan       = board->n_aochan;
5166                 s->maxdata      = board->ao_maxdata;
5167                 s->range_table  = board->ao_range_table;
5168                 s->insn_config  = ni_ao_insn_config;
5169                 s->insn_write   = ni_ao_insn_write;
5170
5171                 ret = comedi_alloc_subdev_readback(s);
5172                 if (ret)
5173                         return ret;
5174
5175                 /*
5176                  * Along with the IRQ we need either a FIFO or DMA for
5177                  * async command support.
5178                  */
5179                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5180                         dev->write_subdev = s;
5181                         s->subdev_flags |= SDF_CMD_WRITE;
5182                         s->len_chanlist = s->n_chan;
5183                         s->do_cmdtest   = ni_ao_cmdtest;
5184                         s->do_cmd       = ni_ao_cmd;
5185                         s->cancel       = ni_ao_reset;
5186                         if (!devpriv->is_m_series)
5187                                 s->munge        = ni_ao_munge;
5188
5189                         if (devpriv->mite)
5190                                 s->async_dma_dir = DMA_TO_DEVICE;
5191                 }
5192
5193                 if (devpriv->is_67xx)
5194                         init_ao_67xx(dev, s);
5195
5196                 /* reset the analog output configuration */
5197                 ni_ao_reset(dev, s);
5198         } else {
5199                 s->type         = COMEDI_SUBD_UNUSED;
5200         }
5201
5202         /* Digital I/O subdevice */
5203         s = &dev->subdevices[NI_DIO_SUBDEV];
5204         s->type         = COMEDI_SUBD_DIO;
5205         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5206         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5207         s->maxdata      = 1;
5208         s->range_table  = &range_digital;
5209         if (devpriv->is_m_series) {
5210                 s->subdev_flags |= SDF_LSAMPL;
5211                 s->insn_bits    = ni_m_series_dio_insn_bits;
5212                 s->insn_config  = ni_m_series_dio_insn_config;
5213                 if (dev->irq) {
5214                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5215                         s->len_chanlist = s->n_chan;
5216                         s->do_cmdtest   = ni_cdio_cmdtest;
5217                         s->do_cmd       = ni_cdio_cmd;
5218                         s->cancel       = ni_cdio_cancel;
5219
5220                         /* M-series boards use DMA */
5221                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5222                 }
5223
5224                 /* reset DIO and set all channels to inputs */
5225                 ni_writel(dev, NI_M_CDO_CMD_RESET |
5226                                NI_M_CDI_CMD_RESET,
5227                           NI_M_CDIO_CMD_REG);
5228                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5229         } else {
5230                 s->insn_bits    = ni_dio_insn_bits;
5231                 s->insn_config  = ni_dio_insn_config;
5232
5233                 /* set all channels to inputs */
5234                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5235                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5236         }
5237
5238         /* 8255 device */
5239         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5240         if (board->has_8255) {
5241                 ret = subdev_8255_init(dev, s, ni_8255_callback,
5242                                        NI_E_8255_BASE);
5243                 if (ret)
5244                         return ret;
5245         } else {
5246                 s->type = COMEDI_SUBD_UNUSED;
5247         }
5248
5249         /* formerly general purpose counter/timer device, but no longer used */
5250         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5251         s->type = COMEDI_SUBD_UNUSED;
5252
5253         /* Calibration subdevice */
5254         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5255         s->type         = COMEDI_SUBD_CALIB;
5256         s->subdev_flags = SDF_INTERNAL;
5257         s->n_chan       = 1;
5258         s->maxdata      = 0;
5259         if (devpriv->is_m_series) {
5260                 /* internal PWM output used for AI nonlinearity calibration */
5261                 s->insn_config  = ni_m_series_pwm_config;
5262
5263                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5264         } else if (devpriv->is_6143) {
5265                 /* internal PWM output used for AI nonlinearity calibration */
5266                 s->insn_config  = ni_6143_pwm_config;
5267         } else {
5268                 s->subdev_flags |= SDF_WRITABLE;
5269                 s->insn_read    = ni_calib_insn_read;
5270                 s->insn_write   = ni_calib_insn_write;
5271
5272                 /* setup the caldacs and find the real n_chan and maxdata */
5273                 caldac_setup(dev, s);
5274         }
5275
5276         /* EEPROM subdevice */
5277         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5278         s->type         = COMEDI_SUBD_MEMORY;
5279         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5280         s->maxdata      = 0xff;
5281         if (devpriv->is_m_series) {
5282                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5283                 s->insn_read    = ni_m_series_eeprom_insn_read;
5284         } else {
5285                 s->n_chan       = 512;
5286                 s->insn_read    = ni_eeprom_insn_read;
5287         }
5288
5289         /* Digital I/O (PFI) subdevice */
5290         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5291         s->type         = COMEDI_SUBD_DIO;
5292         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5293         s->maxdata      = 1;
5294         if (devpriv->is_m_series) {
5295                 s->n_chan       = 16;
5296                 s->insn_bits    = ni_pfi_insn_bits;
5297
5298                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5299                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5300                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5301                                   NI_M_PFI_OUT_SEL_REG(i));
5302                 }
5303         } else {
5304                 s->n_chan       = 10;
5305         }
5306         s->insn_config  = ni_pfi_insn_config;
5307
5308         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5309
5310         /* cs5529 calibration adc */
5311         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5312         if (devpriv->is_67xx) {
5313                 s->type = COMEDI_SUBD_AI;
5314                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5315                 /*  one channel for each analog output channel */
5316                 s->n_chan = board->n_aochan;
5317                 s->maxdata = (1 << 16) - 1;
5318                 s->range_table = &range_unknown;        /* XXX */
5319                 s->insn_read = cs5529_ai_insn_read;
5320                 s->insn_config = NULL;
5321                 init_cs5529(dev);
5322         } else {
5323                 s->type = COMEDI_SUBD_UNUSED;
5324         }
5325
5326         /* Serial */
5327         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5328         s->type = COMEDI_SUBD_SERIAL;
5329         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5330         s->n_chan = 1;
5331         s->maxdata = 0xff;
5332         s->insn_config = ni_serial_insn_config;
5333         devpriv->serial_interval_ns = 0;
5334         devpriv->serial_hw_mode = 0;
5335
5336         /* RTSI */
5337         s = &dev->subdevices[NI_RTSI_SUBDEV];
5338         s->type = COMEDI_SUBD_DIO;
5339         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5340         s->n_chan = 8;
5341         s->maxdata = 1;
5342         s->insn_bits = ni_rtsi_insn_bits;
5343         s->insn_config = ni_rtsi_insn_config;
5344         ni_rtsi_init(dev);
5345
5346         /* allocate and initialize the gpct counter device */
5347         devpriv->counter_dev = ni_gpct_device_construct(dev,
5348                                         ni_gpct_write_register,
5349                                         ni_gpct_read_register,
5350                                         (devpriv->is_m_series)
5351                                                 ? ni_gpct_variant_m_series
5352                                                 : ni_gpct_variant_e_series,
5353                                         NUM_GPCT);
5354         if (!devpriv->counter_dev)
5355                 return -ENOMEM;
5356
5357         /* Counter (gpct) subdevices */
5358         for (i = 0; i < NUM_GPCT; ++i) {
5359                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5360
5361                 /* setup and initialize the counter */
5362                 gpct->chip_index = 0;
5363                 gpct->counter_index = i;
5364                 ni_tio_init_counter(gpct);
5365
5366                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5367                 s->type         = COMEDI_SUBD_COUNTER;
5368                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5369                 s->n_chan       = 3;
5370                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5371                                                          : 0x00ffffff;
5372                 s->insn_read    = ni_tio_insn_read;
5373                 s->insn_write   = ni_tio_insn_read;
5374                 s->insn_config  = ni_tio_insn_config;
5375 #ifdef PCIDMA
5376                 if (dev->irq && devpriv->mite) {
5377                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5378                         s->len_chanlist = 1;
5379                         s->do_cmdtest   = ni_tio_cmdtest;
5380                         s->do_cmd       = ni_gpct_cmd;
5381                         s->cancel       = ni_gpct_cancel;
5382
5383                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5384                 }
5385 #endif
5386                 s->private      = gpct;
5387         }
5388
5389         /* Frequency output subdevice */
5390         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5391         s->type         = COMEDI_SUBD_COUNTER;
5392         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5393         s->n_chan       = 1;
5394         s->maxdata      = 0xf;
5395         s->insn_read    = ni_freq_out_insn_read;
5396         s->insn_write   = ni_freq_out_insn_write;
5397         s->insn_config  = ni_freq_out_insn_config;
5398
5399         if (dev->irq) {
5400                 ni_stc_writew(dev,
5401                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5402                               (NISTC_INT_CTRL_3PIN_INT & 0) |
5403                               NISTC_INT_CTRL_INTA_ENA |
5404                               NISTC_INT_CTRL_INTB_ENA |
5405                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5406                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5407                               NISTC_INT_CTRL_REG);
5408         }
5409
5410         /* DMA setup */
5411         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5412         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5413
5414         if (devpriv->is_6xxx) {
5415                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5416         } else if (devpriv->is_m_series) {
5417                 int channel;
5418
5419                 for (channel = 0; channel < board->n_aochan; ++channel) {
5420                         ni_writeb(dev, 0xf,
5421                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
5422                         ni_writeb(dev, 0x0,
5423                                   NI_M_AO_REF_ATTENUATION_REG(channel));
5424                 }
5425                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5426         }
5427
5428         return 0;
5429 }
5430
5431 static void mio_common_detach(struct comedi_device *dev)
5432 {
5433         struct ni_private *devpriv = dev->private;
5434
5435         if (devpriv) {
5436                 if (devpriv->counter_dev)
5437                         ni_gpct_device_destroy(devpriv->counter_dev);
5438         }
5439 }