drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60
  61 /* A timeout count */
  62 #define NI_TIMEOUT 1000
  63
  64 /* Note: this table must match the ai_gain_* definitions */
  65 static const short ni_gainlkup[][16] = {
  66         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  67                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  68         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  69         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  70                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  71         [ai_gain_4] = {0, 1, 4, 7},
  72         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  73                           0x003, 0x004, 0x005, 0x006},
  74         [ai_gain_622x] = {0, 1, 4, 5},
  75         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  76         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  77 };
  78
  79 static const struct comedi_lrange range_ni_E_ai = {
  80         16, {
  81                 BIP_RANGE(10),
  82                 BIP_RANGE(5),
  83                 BIP_RANGE(2.5),
  84                 BIP_RANGE(1),
  85                 BIP_RANGE(0.5),
  86                 BIP_RANGE(0.25),
  87                 BIP_RANGE(0.1),
  88                 BIP_RANGE(0.05),
  89                 UNI_RANGE(20),
  90                 UNI_RANGE(10),
  91                 UNI_RANGE(5),
  92                 UNI_RANGE(2),
  93                 UNI_RANGE(1),
  94                 UNI_RANGE(0.5),
  95                 UNI_RANGE(0.2),
  96                 UNI_RANGE(0.1)
  97         }
  98 };
  99
 100 static const struct comedi_lrange range_ni_E_ai_limited = {
 101         8, {
 102                 BIP_RANGE(10),
 103                 BIP_RANGE(5),
 104                 BIP_RANGE(1),
 105                 BIP_RANGE(0.1),
 106                 UNI_RANGE(10),
 107                 UNI_RANGE(5),
 108                 UNI_RANGE(1),
 109                 UNI_RANGE(0.1)
 110         }
 111 };
 112
 113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 114         14, {
 115                 BIP_RANGE(10),
 116                 BIP_RANGE(5),
 117                 BIP_RANGE(2),
 118                 BIP_RANGE(1),
 119                 BIP_RANGE(0.5),
 120                 BIP_RANGE(0.2),
 121                 BIP_RANGE(0.1),
 122                 UNI_RANGE(10),
 123                 UNI_RANGE(5),
 124                 UNI_RANGE(2),
 125                 UNI_RANGE(1),
 126                 UNI_RANGE(0.5),
 127                 UNI_RANGE(0.2),
 128                 UNI_RANGE(0.1)
 129         }
 130 };
 131
 132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 133         4, {
 134                 BIP_RANGE(10),
 135                 BIP_RANGE(5),
 136                 BIP_RANGE(0.5),
 137                 BIP_RANGE(0.05)
 138         }
 139 };
 140
 141 static const struct comedi_lrange range_ni_E_ai_611x = {
 142         8, {
 143                 BIP_RANGE(50),
 144                 BIP_RANGE(20),
 145                 BIP_RANGE(10),
 146                 BIP_RANGE(5),
 147                 BIP_RANGE(2),
 148                 BIP_RANGE(1),
 149                 BIP_RANGE(0.5),
 150                 BIP_RANGE(0.2)
 151         }
 152 };
 153
 154 static const struct comedi_lrange range_ni_M_ai_622x = {
 155         4, {
 156                 BIP_RANGE(10),
 157                 BIP_RANGE(5),
 158                 BIP_RANGE(1),
 159                 BIP_RANGE(0.2)
 160         }
 161 };
 162
 163 static const struct comedi_lrange range_ni_M_ai_628x = {
 164         7, {
 165                 BIP_RANGE(10),
 166                 BIP_RANGE(5),
 167                 BIP_RANGE(2),
 168                 BIP_RANGE(1),
 169                 BIP_RANGE(0.5),
 170                 BIP_RANGE(0.2),
 171                 BIP_RANGE(0.1)
 172         }
 173 };
 174
 175 static const struct comedi_lrange range_ni_E_ao_ext = {
 176         4, {
 177                 BIP_RANGE(10),
 178                 UNI_RANGE(10),
 179                 RANGE_ext(-1, 1),
 180                 RANGE_ext(0, 1)
 181         }
 182 };
 183
 184 static const struct comedi_lrange *const ni_range_lkup[] = {
 185         [ai_gain_16] = &range_ni_E_ai,
 186         [ai_gain_8] = &range_ni_E_ai_limited,
 187         [ai_gain_14] = &range_ni_E_ai_limited14,
 188         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 189         [ai_gain_611x] = &range_ni_E_ai_611x,
 190         [ai_gain_622x] = &range_ni_M_ai_622x,
 191         [ai_gain_628x] = &range_ni_M_ai_628x,
 192         [ai_gain_6143] = &range_bipolar5
 193 };
 194
 195 enum aimodes {
 196         AIMODE_NONE = 0,
 197         AIMODE_HALF_FULL = 1,
 198         AIMODE_SCAN = 2,
 199         AIMODE_SAMPLE = 3,
 200 };
 201
 202 enum ni_common_subdevices {
 203         NI_AI_SUBDEV,
 204         NI_AO_SUBDEV,
 205         NI_DIO_SUBDEV,
 206         NI_8255_DIO_SUBDEV,
 207         NI_UNUSED_SUBDEV,
 208         NI_CALIBRATION_SUBDEV,
 209         NI_EEPROM_SUBDEV,
 210         NI_PFI_DIO_SUBDEV,
 211         NI_CS5529_CALIBRATION_SUBDEV,
 212         NI_SERIAL_SUBDEV,
 213         NI_RTSI_SUBDEV,
 214         NI_GPCT0_SUBDEV,
 215         NI_GPCT1_SUBDEV,
 216         NI_FREQ_OUT_SUBDEV,
 217         NI_NUM_SUBDEVICES
 218 };
 219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 220 {
 221         switch (counter_index) {
 222         case 0:
 223                 return NI_GPCT0_SUBDEV;
 224         case 1:
 225                 return NI_GPCT1_SUBDEV;
 226         default:
 227                 break;
 228         }
 229         BUG();
 230         return NI_GPCT0_SUBDEV;
 231 }
 232
 233 enum timebase_nanoseconds {
 234         TIMEBASE_1_NS = 50,
 235         TIMEBASE_2_NS = 10000
 236 };
 237
 238 #define SERIAL_DISABLED         0
 239 #define SERIAL_600NS            600
 240 #define SERIAL_1_2US            1200
 241 #define SERIAL_10US                     10000
 242
 243 static const int num_adc_stages_611x = 3;
 244
 245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
 246 {
 247         if (dev->mmio)
 248                 writel(data, dev->mmio + reg);
 249
 250         outl(data, dev->iobase + reg);
 251 }
 252
 253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
 254 {
 255         if (dev->mmio)
 256                 writew(data, dev->mmio + reg);
 257
 258         outw(data, dev->iobase + reg);
 259 }
 260
 261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
 262 {
 263         if (dev->mmio)
 264                 writeb(data, dev->mmio + reg);
 265
 266         outb(data, dev->iobase + reg);
 267 }
 268
 269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
 270 {
 271         if (dev->mmio)
 272                 return readl(dev->mmio + reg);
 273
 274         return inl(dev->iobase + reg);
 275 }
 276
 277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
 278 {
 279         if (dev->mmio)
 280                 return readw(dev->mmio + reg);
 281
 282         return inw(dev->iobase + reg);
 283 }
 284
 285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
 286 {
 287         if (dev->mmio)
 288                 return readb(dev->mmio + reg);
 289
 290         return inb(dev->iobase + reg);
 291 }
 292
 293 /*
 294  * We automatically take advantage of STC registers that can be
 295  * read/written directly in the I/O space of the board.
 296  *
 297  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 298  * iobase+reg*2.
 299  *
 300  * Most PCIMIO devices also map the low 8 STC registers but the
 301  * 611x devices map the read registers to iobase+(addr-1)*2.
 302  * For now non-windowed STC access is disabled if a PCIMIO device
 303  * is detected (devpriv->mite has been initialized).
 304  *
 305  * The M series devices do not used windowed registers for the
 306  * STC registers. The functions below handle the mapping of the
 307  * windowed STC registers to the m series register offsets.
 308  */
 309
 310 struct mio_regmap {
 311         unsigned int mio_reg;
 312         int size;
 313 };
 314
 315 static const struct mio_regmap m_series_stc_write_regmap[] = {
 316         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 317         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 318         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 319         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 320         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 321         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 322         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 323         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 324         /*
 325          * NISTC_DIO_OUT_REG maps to:
 326          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 327          */
 328         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 329         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 330         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 331         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 332         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 333         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 334         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 335         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 336         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 337         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 338         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 339         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 340         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 341         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 342         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 343         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 344         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 345         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 346         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 347         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 348         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 349         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 350         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 351         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 352         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 353         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 354         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 355         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 356         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 357         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 358         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 359         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 360         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 361         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 362         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 363         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 364         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 365         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 366         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 367         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 368         [NISTC_RESET_REG]               = { 0x190, 2 },
 369         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 370         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 371         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 372         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 373         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 374         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 375         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 376         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 377         [NISTC_RTSI_BOARD_REG]          = { 0, 0 }, /* Unknown */
 378         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 379         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 380         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 381         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 382         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 383 };
 384
 385 static void m_series_stc_write(struct comedi_device *dev,
 386                                unsigned int data, unsigned int reg)
 387 {
 388         const struct mio_regmap *regmap;
 389
 390         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 391                 regmap = &m_series_stc_write_regmap[reg];
 392         } else {
 393                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 394                          __func__, reg);
 395                 return;
 396         }
 397
 398         switch (regmap->size) {
 399         case 4:
 400                 ni_writel(dev, data, regmap->mio_reg);
 401                 break;
 402         case 2:
 403                 ni_writew(dev, data, regmap->mio_reg);
 404                 break;
 405         default:
 406                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 407                          __func__, reg);
 408                 break;
 409         }
 410 }
 411
 412 static const struct mio_regmap m_series_stc_read_regmap[] = {
 413         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 414         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 415         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 416         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 417         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 418         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 419         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 420         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 421         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 422         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 423         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 424         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 425         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 426         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 427         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 428         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 429         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 430         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 431 };
 432
 433 static unsigned int m_series_stc_read(struct comedi_device *dev,
 434                                       unsigned int reg)
 435 {
 436         const struct mio_regmap *regmap;
 437
 438         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 439                 regmap = &m_series_stc_read_regmap[reg];
 440         } else {
 441                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 442                          __func__, reg);
 443                 return 0;
 444         }
 445
 446         switch (regmap->size) {
 447         case 4:
 448                 return ni_readl(dev, regmap->mio_reg);
 449         case 2:
 450                 return ni_readw(dev, regmap->mio_reg);
 451         case 1:
 452                 return ni_readb(dev, regmap->mio_reg);
 453         default:
 454                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 455                          __func__, reg);
 456                 return 0;
 457         }
 458 }
 459
 460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
 461 {
 462         struct ni_private *devpriv = dev->private;
 463         unsigned long flags;
 464
 465         if (devpriv->is_m_series) {
 466                 m_series_stc_write(dev, data, reg);
 467         } else {
 468                 spin_lock_irqsave(&devpriv->window_lock, flags);
 469                 if (!devpriv->mite && reg < 8) {
 470                         ni_writew(dev, data, reg * 2);
 471                 } else {
 472                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 473                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 474                 }
 475                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 476         }
 477 }
 478
 479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
 480 {
 481         struct ni_private *devpriv = dev->private;
 482
 483         if (devpriv->is_m_series) {
 484                 m_series_stc_write(dev, data, reg);
 485         } else {
 486                 ni_stc_writew(dev, data >> 16, reg);
 487                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 488         }
 489 }
 490
 491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
 492 {
 493         struct ni_private *devpriv = dev->private;
 494         unsigned long flags;
 495         uint16_t val;
 496
 497         if (devpriv->is_m_series) {
 498                 val = m_series_stc_read(dev, reg);
 499         } else {
 500                 spin_lock_irqsave(&devpriv->window_lock, flags);
 501                 if (!devpriv->mite && reg < 8) {
 502                         val = ni_readw(dev, reg * 2);
 503                 } else {
 504                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 505                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 506                 }
 507                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 508         }
 509         return val;
 510 }
 511
 512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
 513 {
 514         struct ni_private *devpriv = dev->private;
 515         uint32_t val;
 516
 517         if (devpriv->is_m_series) {
 518                 val = m_series_stc_read(dev, reg);
 519         } else {
 520                 val = ni_stc_readw(dev, reg) << 16;
 521                 val |= ni_stc_readw(dev, reg + 1);
 522         }
 523         return val;
 524 }
 525
 526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 527                                    unsigned bit_mask, unsigned bit_values)
 528 {
 529         struct ni_private *devpriv = dev->private;
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 533         switch (reg) {
 534         case NISTC_INTA_ENA_REG:
 535                 devpriv->int_a_enable_reg &= ~bit_mask;
 536                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 537                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 538                 break;
 539         case NISTC_INTB_ENA_REG:
 540                 devpriv->int_b_enable_reg &= ~bit_mask;
 541                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 542                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 543                 break;
 544         case NISTC_IO_BIDIR_PIN_REG:
 545                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 546                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 547                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 548                 break;
 549         case NI_E_DMA_AI_AO_SEL_REG:
 550                 devpriv->ai_ao_select_reg &= ~bit_mask;
 551                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 552                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 553                 break;
 554         case NI_E_DMA_G0_G1_SEL_REG:
 555                 devpriv->g0_g1_select_reg &= ~bit_mask;
 556                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 557                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 558                 break;
 559         default:
 560                 dev_err(dev->class_dev, "called with invalid register %d\n",
 561                         reg);
 562                 break;
 563         }
 564         mmiowb();
 565         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 566 }
 567
 568 #ifdef PCIDMA
 569 /* DMA channel setup */
 570 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
 571 {
 572         if (channel < 4)
 573                 return 1 << channel;
 574         if (channel == 4)
 575                 return 0x3;
 576         if (channel == 5)
 577                 return 0x5;
 578         BUG();
 579         return 0;
 580 }
 581
 582 static inline void ni_set_ai_dma_channel(struct comedi_device *dev,
 583                                          unsigned channel)
 584 {
 585         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 586
 587         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 588                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 589 }
 590
 591 static inline void ni_set_ai_dma_no_channel(struct comedi_device *dev)
 592 {
 593         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AI_SEL_MASK, 0);
 594 }
 595
 596 static inline void ni_set_ao_dma_channel(struct comedi_device *dev,
 597                                          unsigned channel)
 598 {
 599         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 600
 601         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 602                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 603 }
 604
 605 static inline void ni_set_ao_dma_no_channel(struct comedi_device *dev)
 606 {
 607         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AO_SEL_MASK, 0);
 608 }
 609
 610 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 611                                            unsigned gpct_index,
 612                                            unsigned channel)
 613 {
 614         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 615
 616         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 617                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 618                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 619 }
 620
 621 static inline void ni_set_gpct_dma_no_channel(struct comedi_device *dev,
 622                                               unsigned gpct_index)
 623 {
 624         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 625                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
 626 }
 627
 628 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 629                                           unsigned mite_channel)
 630 {
 631         struct ni_private *devpriv = dev->private;
 632         unsigned long flags;
 633         unsigned bits;
 634
 635         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 636         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 637         /*
 638          * XXX just guessing ni_stc_dma_channel_select_bitfield()
 639          * returns the right bits, under the assumption the cdio dma
 640          * selection works just like ai/ao/gpct.
 641          * Definitely works for dma channels 0 and 1.
 642          */
 643         bits = ni_stc_dma_channel_select_bitfield(mite_channel);
 644         devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
 645         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 646         mmiowb();
 647         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 648 }
 649
 650 static inline void ni_set_cdo_dma_no_channel(struct comedi_device *dev)
 651 {
 652         struct ni_private *devpriv = dev->private;
 653         unsigned long flags;
 654
 655         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 656         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 657         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 658         mmiowb();
 659         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 660 }
 661
 662 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 663 {
 664         struct ni_private *devpriv = dev->private;
 665         unsigned long flags;
 666
 667         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 668         BUG_ON(devpriv->ai_mite_chan);
 669         devpriv->ai_mite_chan =
 670             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 671         if (!devpriv->ai_mite_chan) {
 672                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 673                 dev_err(dev->class_dev,
 674                         "failed to reserve mite dma channel for analog input\n");
 675                 return -EBUSY;
 676         }
 677         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 678         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 679         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 680         return 0;
 681 }
 682
 683 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 684 {
 685         struct ni_private *devpriv = dev->private;
 686         unsigned long flags;
 687
 688         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 689         BUG_ON(devpriv->ao_mite_chan);
 690         devpriv->ao_mite_chan =
 691             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 692         if (!devpriv->ao_mite_chan) {
 693                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 694                 dev_err(dev->class_dev,
 695                         "failed to reserve mite dma channel for analog outut\n");
 696                 return -EBUSY;
 697         }
 698         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 699         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 700         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 701         return 0;
 702 }
 703
 704 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 705                                         unsigned gpct_index,
 706                                         enum comedi_io_direction direction)
 707 {
 708         struct ni_private *devpriv = dev->private;
 709         unsigned long flags;
 710         struct mite_channel *mite_chan;
 711
 712         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 713         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 714         mite_chan =
 715             mite_request_channel(devpriv->mite,
 716                                  devpriv->gpct_mite_ring[gpct_index]);
 717         if (!mite_chan) {
 718                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 719                 dev_err(dev->class_dev,
 720                         "failed to reserve mite dma channel for counter\n");
 721                 return -EBUSY;
 722         }
 723         mite_chan->dir = direction;
 724         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 725                                 mite_chan);
 726         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 727         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 728         return 0;
 729 }
 730
 731 #endif /*  PCIDMA */
 732
 733 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 734 {
 735 #ifdef PCIDMA
 736         struct ni_private *devpriv = dev->private;
 737         unsigned long flags;
 738
 739         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 740         BUG_ON(devpriv->cdo_mite_chan);
 741         devpriv->cdo_mite_chan =
 742             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 743         if (!devpriv->cdo_mite_chan) {
 744                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 745                 dev_err(dev->class_dev,
 746                         "failed to reserve mite dma channel for correlated digital output\n");
 747                 return -EBUSY;
 748         }
 749         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 750         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 751         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 752 #endif /*  PCIDMA */
 753         return 0;
 754 }
 755
 756 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 757 {
 758 #ifdef PCIDMA
 759         struct ni_private *devpriv = dev->private;
 760         unsigned long flags;
 761
 762         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 763         if (devpriv->ai_mite_chan) {
 764                 ni_set_ai_dma_no_channel(dev);
 765                 mite_release_channel(devpriv->ai_mite_chan);
 766                 devpriv->ai_mite_chan = NULL;
 767         }
 768         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 769 #endif /*  PCIDMA */
 770 }
 771
 772 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 773 {
 774 #ifdef PCIDMA
 775         struct ni_private *devpriv = dev->private;
 776         unsigned long flags;
 777
 778         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 779         if (devpriv->ao_mite_chan) {
 780                 ni_set_ao_dma_no_channel(dev);
 781                 mite_release_channel(devpriv->ao_mite_chan);
 782                 devpriv->ao_mite_chan = NULL;
 783         }
 784         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 785 #endif /*  PCIDMA */
 786 }
 787
 788 #ifdef PCIDMA
 789 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 790                                          unsigned gpct_index)
 791 {
 792         struct ni_private *devpriv = dev->private;
 793         unsigned long flags;
 794
 795         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 796         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 797                 struct mite_channel *mite_chan =
 798                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 799
 800                 ni_set_gpct_dma_no_channel(dev, gpct_index);
 801                 ni_tio_set_mite_channel(&devpriv->
 802                                         counter_dev->counters[gpct_index],
 803                                         NULL);
 804                 mite_release_channel(mite_chan);
 805         }
 806         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 807 }
 808 #endif /*  PCIDMA */
 809
 810 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 811 {
 812 #ifdef PCIDMA
 813         struct ni_private *devpriv = dev->private;
 814         unsigned long flags;
 815
 816         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 817         if (devpriv->cdo_mite_chan) {
 818                 ni_set_cdo_dma_no_channel(dev);
 819                 mite_release_channel(devpriv->cdo_mite_chan);
 820                 devpriv->cdo_mite_chan = NULL;
 821         }
 822         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 823 #endif /*  PCIDMA */
 824 }
 825
 826 #ifdef PCIDMA
 827 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 828                                           unsigned gpct_index, short enable)
 829 {
 830         struct ni_private *devpriv = dev->private;
 831         uint16_t val = 0;
 832         int reg;
 833
 834         if (devpriv->is_m_series || gpct_index > 1)
 835                 return;
 836
 837         /*
 838          * e-series boards use the second irq signals to generate
 839          * dma requests for their counters
 840          */
 841         if (gpct_index == 0) {
 842                 reg = NISTC_INTA2_ENA_REG;
 843                 if (enable)
 844                         val = NISTC_INTA_ENA_G0_GATE;
 845         } else {
 846                 reg = NISTC_INTB2_ENA_REG;
 847                 if (enable)
 848                         val = NISTC_INTB_ENA_G1_GATE;
 849         }
 850         ni_stc_writew(dev, val, reg);
 851 }
 852 #endif /*  PCIDMA */
 853
 854 static void ni_clear_ai_fifo(struct comedi_device *dev)
 855 {
 856         struct ni_private *devpriv = dev->private;
 857         static const int timeout = 10000;
 858         int i;
 859
 860         if (devpriv->is_6143) {
 861                 /*  Flush the 6143 data FIFO */
 862                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 863                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 864                 /*  Wait for complete */
 865                 for (i = 0; i < timeout; i++) {
 866                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 867                                 break;
 868                         udelay(1);
 869                 }
 870                 if (i == timeout)
 871                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 872         } else {
 873                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 874                 if (devpriv->is_625x) {
 875                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 876                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 877 #if 0
 878                         /* the NI example code does 3 convert pulses for 625x boards,
 879                            but that appears to be wrong in practice. */
 880                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 881                                       NISTC_AI_CMD1_REG);
 882                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 883                                       NISTC_AI_CMD1_REG);
 884                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 885                                       NISTC_AI_CMD1_REG);
 886 #endif
 887                 }
 888         }
 889 }
 890
 891 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 892                                   int addr)
 893 {
 894         struct ni_private *devpriv = dev->private;
 895         unsigned long flags;
 896
 897         spin_lock_irqsave(&devpriv->window_lock, flags);
 898         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 899         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 900         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 901 }
 902
 903 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 904                                   int addr)
 905 {
 906         struct ni_private *devpriv = dev->private;
 907         unsigned long flags;
 908
 909         spin_lock_irqsave(&devpriv->window_lock, flags);
 910         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 911         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 912         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 913 }
 914
 915 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 916 {
 917         struct ni_private *devpriv = dev->private;
 918         unsigned long flags;
 919         unsigned short data;
 920
 921         spin_lock_irqsave(&devpriv->window_lock, flags);
 922         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 923         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 924         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 925         return data;
 926 }
 927
 928 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 929 * share registers (such as Interrupt_A_Register) without interfering with
 930 * each other.
 931 *
 932 * NOTE: the switch/case statements are optimized out for a constant argument
 933 * so this is actually quite fast---  If you must wrap another function around this
 934 * make it inline to avoid a large speed penalty.
 935 *
 936 * value should only be 1 or 0.
 937 */
 938 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 939                                unsigned bits, unsigned value)
 940 {
 941         unsigned bit_values;
 942
 943         if (value)
 944                 bit_values = bits;
 945         else
 946                 bit_values = 0;
 947         ni_set_bitfield(dev, reg, bits, bit_values);
 948 }
 949
 950 #ifdef PCIDMA
 951 static void ni_sync_ai_dma(struct comedi_device *dev)
 952 {
 953         struct ni_private *devpriv = dev->private;
 954         struct comedi_subdevice *s = dev->read_subdev;
 955         unsigned long flags;
 956
 957         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 958         if (devpriv->ai_mite_chan)
 959                 mite_sync_input_dma(devpriv->ai_mite_chan, s);
 960         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 961 }
 962
 963 static int ni_ai_drain_dma(struct comedi_device *dev)
 964 {
 965         struct ni_private *devpriv = dev->private;
 966         int i;
 967         static const int timeout = 10000;
 968         unsigned long flags;
 969         int retval = 0;
 970
 971         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 972         if (devpriv->ai_mite_chan) {
 973                 for (i = 0; i < timeout; i++) {
 974                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 975                              NISTC_AI_STATUS1_FIFO_E)
 976                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
 977                             0)
 978                                 break;
 979                         udelay(5);
 980                 }
 981                 if (i == timeout) {
 982                         dev_err(dev->class_dev, "timed out\n");
 983                         dev_err(dev->class_dev,
 984                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 985                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 986                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 987                         retval = -1;
 988                 }
 989         }
 990         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 991
 992         ni_sync_ai_dma(dev);
 993
 994         return retval;
 995 }
 996
 997 static void mite_handle_b_linkc(struct mite_struct *mite,
 998                                 struct comedi_device *dev)
 999 {
1000         struct ni_private *devpriv = dev->private;
1001         struct comedi_subdevice *s = dev->write_subdev;
1002         unsigned long flags;
1003
1004         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1005         if (devpriv->ao_mite_chan)
1006                 mite_sync_output_dma(devpriv->ao_mite_chan, s);
1007         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1008 }
1009
1010 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
1011 {
1012         static const int timeout = 10000;
1013         int i;
1014
1015         for (i = 0; i < timeout; i++) {
1016                 unsigned short b_status;
1017
1018                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
1019                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
1020                         break;
1021                 /* if we poll too often, the pci bus activity seems
1022                    to slow the dma transfer down */
1023                 udelay(10);
1024         }
1025         if (i == timeout) {
1026                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1027                 return -EPIPE;
1028         }
1029         return 0;
1030 }
1031 #endif /* PCIDMA */
1032
1033 #ifndef PCIDMA
1034
1035 static void ni_ao_fifo_load(struct comedi_device *dev,
1036                             struct comedi_subdevice *s, int n)
1037 {
1038         struct ni_private *devpriv = dev->private;
1039         int i;
1040         unsigned short d;
1041         u32 packed_data;
1042
1043         for (i = 0; i < n; i++) {
1044                 comedi_buf_read_samples(s, &d, 1);
1045
1046                 if (devpriv->is_6xxx) {
1047                         packed_data = d & 0xffff;
1048                         /* 6711 only has 16 bit wide ao fifo */
1049                         if (!devpriv->is_6711) {
1050                                 comedi_buf_read_samples(s, &d, 1);
1051                                 i++;
1052                                 packed_data |= (d << 16) & 0xffff0000;
1053                         }
1054                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
1055                 } else {
1056                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
1057                 }
1058         }
1059 }
1060
1061 /*
1062  *  There's a small problem if the FIFO gets really low and we
1063  *  don't have the data to fill it.  Basically, if after we fill
1064  *  the FIFO with all the data available, the FIFO is _still_
1065  *  less than half full, we never clear the interrupt.  If the
1066  *  IRQ is in edge mode, we never get another interrupt, because
1067  *  this one wasn't cleared.  If in level mode, we get flooded
1068  *  with interrupts that we can't fulfill, because nothing ever
1069  *  gets put into the buffer.
1070  *
1071  *  This kind of situation is recoverable, but it is easier to
1072  *  just pretend we had a FIFO underrun, since there is a good
1073  *  chance it will happen anyway.  This is _not_ the case for
1074  *  RT code, as RT code might purposely be running close to the
1075  *  metal.  Needs to be fixed eventually.
1076  */
1077 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1078                                  struct comedi_subdevice *s)
1079 {
1080         const struct ni_board_struct *board = dev->board_ptr;
1081         unsigned int nbytes;
1082         unsigned int nsamples;
1083
1084         nbytes = comedi_buf_read_n_available(s);
1085         if (nbytes == 0) {
1086                 s->async->events |= COMEDI_CB_OVERFLOW;
1087                 return 0;
1088         }
1089
1090         nsamples = comedi_bytes_to_samples(s, nbytes);
1091         if (nsamples > board->ao_fifo_depth / 2)
1092                 nsamples = board->ao_fifo_depth / 2;
1093
1094         ni_ao_fifo_load(dev, s, nsamples);
1095
1096         return 1;
1097 }
1098
1099 static int ni_ao_prep_fifo(struct comedi_device *dev,
1100                            struct comedi_subdevice *s)
1101 {
1102         const struct ni_board_struct *board = dev->board_ptr;
1103         struct ni_private *devpriv = dev->private;
1104         unsigned int nbytes;
1105         unsigned int nsamples;
1106
1107         /* reset fifo */
1108         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1109         if (devpriv->is_6xxx)
1110                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1111
1112         /* load some data */
1113         nbytes = comedi_buf_read_n_available(s);
1114         if (nbytes == 0)
1115                 return 0;
1116
1117         nsamples = comedi_bytes_to_samples(s, nbytes);
1118         if (nsamples > board->ao_fifo_depth)
1119                 nsamples = board->ao_fifo_depth;
1120
1121         ni_ao_fifo_load(dev, s, nsamples);
1122
1123         return nsamples;
1124 }
1125
1126 static void ni_ai_fifo_read(struct comedi_device *dev,
1127                             struct comedi_subdevice *s, int n)
1128 {
1129         struct ni_private *devpriv = dev->private;
1130         struct comedi_async *async = s->async;
1131         u32 dl;
1132         unsigned short data;
1133         int i;
1134
1135         if (devpriv->is_611x) {
1136                 for (i = 0; i < n / 2; i++) {
1137                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1138                         /* This may get the hi/lo data in the wrong order */
1139                         data = (dl >> 16) & 0xffff;
1140                         comedi_buf_write_samples(s, &data, 1);
1141                         data = dl & 0xffff;
1142                         comedi_buf_write_samples(s, &data, 1);
1143                 }
1144                 /* Check if there's a single sample stuck in the FIFO */
1145                 if (n % 2) {
1146                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1147                         data = dl & 0xffff;
1148                         comedi_buf_write_samples(s, &data, 1);
1149                 }
1150         } else if (devpriv->is_6143) {
1151                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1152                 for (i = 0; i < n / 2; i++) {
1153                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1154
1155                         data = (dl >> 16) & 0xffff;
1156                         comedi_buf_write_samples(s, &data, 1);
1157                         data = dl & 0xffff;
1158                         comedi_buf_write_samples(s, &data, 1);
1159                 }
1160                 if (n % 2) {
1161                         /* Assume there is a single sample stuck in the FIFO */
1162                         /* Get stranded sample into FIFO */
1163                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1164                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1165                         data = (dl >> 16) & 0xffff;
1166                         comedi_buf_write_samples(s, &data, 1);
1167                 }
1168         } else {
1169                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1170                     sizeof(devpriv->ai_fifo_buffer[0])) {
1171                         dev_err(dev->class_dev,
1172                                 "bug! ai_fifo_buffer too small\n");
1173                         async->events |= COMEDI_CB_ERROR;
1174                         return;
1175                 }
1176                 for (i = 0; i < n; i++) {
1177                         devpriv->ai_fifo_buffer[i] =
1178                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1179                 }
1180                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1181         }
1182 }
1183
1184 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1185 {
1186         const struct ni_board_struct *board = dev->board_ptr;
1187         struct comedi_subdevice *s = dev->read_subdev;
1188         int n;
1189
1190         n = board->ai_fifo_depth / 2;
1191
1192         ni_ai_fifo_read(dev, s, n);
1193 }
1194 #endif
1195
1196 /*
1197    Empties the AI fifo
1198 */
1199 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1200 {
1201         struct ni_private *devpriv = dev->private;
1202         struct comedi_subdevice *s = dev->read_subdev;
1203         u32 dl;
1204         unsigned short data;
1205         unsigned short fifo_empty;
1206         int i;
1207
1208         if (devpriv->is_611x) {
1209                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1210                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1211                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1212
1213                         /* This may get the hi/lo data in the wrong order */
1214                         data = dl >> 16;
1215                         comedi_buf_write_samples(s, &data, 1);
1216                         data = dl & 0xffff;
1217                         comedi_buf_write_samples(s, &data, 1);
1218                 }
1219         } else if (devpriv->is_6143) {
1220                 i = 0;
1221                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1222                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1223
1224                         /* This may get the hi/lo data in the wrong order */
1225                         data = dl >> 16;
1226                         comedi_buf_write_samples(s, &data, 1);
1227                         data = dl & 0xffff;
1228                         comedi_buf_write_samples(s, &data, 1);
1229                         i += 2;
1230                 }
1231                 /*  Check if stranded sample is present */
1232                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1233                         /* Get stranded sample into FIFO */
1234                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1235                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1236                         data = (dl >> 16) & 0xffff;
1237                         comedi_buf_write_samples(s, &data, 1);
1238                 }
1239
1240         } else {
1241                 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1242                              NISTC_AI_STATUS1_FIFO_E;
1243                 while (fifo_empty == 0) {
1244                         for (i = 0;
1245                              i <
1246                              sizeof(devpriv->ai_fifo_buffer) /
1247                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1248                                 fifo_empty = ni_stc_readw(dev,
1249                                                           NISTC_AI_STATUS1_REG) &
1250                                                 NISTC_AI_STATUS1_FIFO_E;
1251                                 if (fifo_empty)
1252                                         break;
1253                                 devpriv->ai_fifo_buffer[i] =
1254                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1255                         }
1256                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1257                 }
1258         }
1259 }
1260
1261 static void get_last_sample_611x(struct comedi_device *dev)
1262 {
1263         struct ni_private *devpriv = dev->private;
1264         struct comedi_subdevice *s = dev->read_subdev;
1265         unsigned short data;
1266         u32 dl;
1267
1268         if (!devpriv->is_611x)
1269                 return;
1270
1271         /* Check if there's a single sample stuck in the FIFO */
1272         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1273                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1274                 data = dl & 0xffff;
1275                 comedi_buf_write_samples(s, &data, 1);
1276         }
1277 }
1278
1279 static void get_last_sample_6143(struct comedi_device *dev)
1280 {
1281         struct ni_private *devpriv = dev->private;
1282         struct comedi_subdevice *s = dev->read_subdev;
1283         unsigned short data;
1284         u32 dl;
1285
1286         if (!devpriv->is_6143)
1287                 return;
1288
1289         /* Check if there's a single sample stuck in the FIFO */
1290         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1291                 /* Get stranded sample into FIFO */
1292                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1293                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1294
1295                 /* This may get the hi/lo data in the wrong order */
1296                 data = (dl >> 16) & 0xffff;
1297                 comedi_buf_write_samples(s, &data, 1);
1298         }
1299 }
1300
1301 static void shutdown_ai_command(struct comedi_device *dev)
1302 {
1303         struct comedi_subdevice *s = dev->read_subdev;
1304
1305 #ifdef PCIDMA
1306         ni_ai_drain_dma(dev);
1307 #endif
1308         ni_handle_fifo_dregs(dev);
1309         get_last_sample_611x(dev);
1310         get_last_sample_6143(dev);
1311
1312         s->async->events |= COMEDI_CB_EOA;
1313 }
1314
1315 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1316 {
1317         struct ni_private *devpriv = dev->private;
1318
1319         if (devpriv->aimode == AIMODE_SCAN) {
1320 #ifdef PCIDMA
1321                 static const int timeout = 10;
1322                 int i;
1323
1324                 for (i = 0; i < timeout; i++) {
1325                         ni_sync_ai_dma(dev);
1326                         if ((s->async->events & COMEDI_CB_EOS))
1327                                 break;
1328                         udelay(1);
1329                 }
1330 #else
1331                 ni_handle_fifo_dregs(dev);
1332                 s->async->events |= COMEDI_CB_EOS;
1333 #endif
1334         }
1335         /* handle special case of single scan */
1336         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1337                 shutdown_ai_command(dev);
1338 }
1339
1340 static void handle_gpct_interrupt(struct comedi_device *dev,
1341                                   unsigned short counter_index)
1342 {
1343 #ifdef PCIDMA
1344         struct ni_private *devpriv = dev->private;
1345         struct comedi_subdevice *s;
1346
1347         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1348
1349         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1350                                 s);
1351         comedi_handle_events(dev, s);
1352 #endif
1353 }
1354
1355 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1356 {
1357         unsigned short ack = 0;
1358
1359         if (a_status & NISTC_AI_STATUS1_SC_TC)
1360                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1361         if (a_status & NISTC_AI_STATUS1_START1)
1362                 ack |= NISTC_INTA_ACK_AI_START1;
1363         if (a_status & NISTC_AI_STATUS1_START)
1364                 ack |= NISTC_INTA_ACK_AI_START;
1365         if (a_status & NISTC_AI_STATUS1_STOP)
1366                 ack |= NISTC_INTA_ACK_AI_STOP;
1367         if (ack)
1368                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1369 }
1370
1371 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1372                                unsigned ai_mite_status)
1373 {
1374         struct comedi_subdevice *s = dev->read_subdev;
1375         struct comedi_cmd *cmd = &s->async->cmd;
1376
1377         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1378         if (s->type == COMEDI_SUBD_UNUSED)
1379                 return;
1380
1381 #ifdef PCIDMA
1382         if (ai_mite_status & CHSR_LINKC)
1383                 ni_sync_ai_dma(dev);
1384
1385         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1386                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1387                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1388                 dev_err(dev->class_dev,
1389                         "unknown mite interrupt (ai_mite_status=%08x)\n",
1390                         ai_mite_status);
1391                 s->async->events |= COMEDI_CB_ERROR;
1392                 /* disable_irq(dev->irq); */
1393         }
1394 #endif
1395
1396         /* test for all uncommon interrupt events at the same time */
1397         if (status & (NISTC_AI_STATUS1_ERR |
1398                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1399                 if (status == 0xffff) {
1400                         dev_err(dev->class_dev, "Card removed?\n");
1401                         /* we probably aren't even running a command now,
1402                          * so it's a good idea to be careful. */
1403                         if (comedi_is_subdevice_running(s)) {
1404                                 s->async->events |= COMEDI_CB_ERROR;
1405                                 comedi_handle_events(dev, s);
1406                         }
1407                         return;
1408                 }
1409                 if (status & NISTC_AI_STATUS1_ERR) {
1410                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1411                                 status);
1412
1413                         shutdown_ai_command(dev);
1414
1415                         s->async->events |= COMEDI_CB_ERROR;
1416                         if (status & NISTC_AI_STATUS1_OVER)
1417                                 s->async->events |= COMEDI_CB_OVERFLOW;
1418
1419                         comedi_handle_events(dev, s);
1420                         return;
1421                 }
1422                 if (status & NISTC_AI_STATUS1_SC_TC) {
1423                         if (cmd->stop_src == TRIG_COUNT)
1424                                 shutdown_ai_command(dev);
1425                 }
1426         }
1427 #ifndef PCIDMA
1428         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1429                 int i;
1430                 static const int timeout = 10;
1431                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1432                  *fail to get the fifo less than half full, so loop to be sure.*/
1433                 for (i = 0; i < timeout; ++i) {
1434                         ni_handle_fifo_half_full(dev);
1435                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1436                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1437                                 break;
1438                 }
1439         }
1440 #endif /*  !PCIDMA */
1441
1442         if (status & NISTC_AI_STATUS1_STOP)
1443                 ni_handle_eos(dev, s);
1444
1445         comedi_handle_events(dev, s);
1446 }
1447
1448 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1449 {
1450         unsigned short ack = 0;
1451
1452         if (b_status & NISTC_AO_STATUS1_BC_TC)
1453                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1454         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1455                 ack |= NISTC_INTB_ACK_AO_ERR;
1456         if (b_status & NISTC_AO_STATUS1_START)
1457                 ack |= NISTC_INTB_ACK_AO_START;
1458         if (b_status & NISTC_AO_STATUS1_START1)
1459                 ack |= NISTC_INTB_ACK_AO_START1;
1460         if (b_status & NISTC_AO_STATUS1_UC_TC)
1461                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1462         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1463                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1464         if (b_status & NISTC_AO_STATUS1_UPDATE)
1465                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1466         if (ack)
1467                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1468 }
1469
1470 static void handle_b_interrupt(struct comedi_device *dev,
1471                                unsigned short b_status, unsigned ao_mite_status)
1472 {
1473         struct comedi_subdevice *s = dev->write_subdev;
1474         /* unsigned short ack=0; */
1475
1476 #ifdef PCIDMA
1477         /* Currently, mite.c requires us to handle LINKC */
1478         if (ao_mite_status & CHSR_LINKC) {
1479                 struct ni_private *devpriv = dev->private;
1480
1481                 mite_handle_b_linkc(devpriv->mite, dev);
1482         }
1483
1484         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1485                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1486                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1487                 dev_err(dev->class_dev,
1488                         "unknown mite interrupt (ao_mite_status=%08x)\n",
1489                         ao_mite_status);
1490                 s->async->events |= COMEDI_CB_ERROR;
1491         }
1492 #endif
1493
1494         if (b_status == 0xffff)
1495                 return;
1496         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1497                 dev_err(dev->class_dev,
1498                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1499                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1500                 s->async->events |= COMEDI_CB_OVERFLOW;
1501         }
1502
1503         if (s->async->cmd.stop_src != TRIG_NONE &&
1504             b_status & NISTC_AO_STATUS1_BC_TC)
1505                 s->async->events |= COMEDI_CB_EOA;
1506
1507 #ifndef PCIDMA
1508         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1509                 int ret;
1510
1511                 ret = ni_ao_fifo_half_empty(dev, s);
1512                 if (!ret) {
1513                         dev_err(dev->class_dev, "AO buffer underrun\n");
1514                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1515                                     NISTC_INTB_ENA_AO_FIFO |
1516                                     NISTC_INTB_ENA_AO_ERR, 0);
1517                         s->async->events |= COMEDI_CB_OVERFLOW;
1518                 }
1519         }
1520 #endif
1521
1522         comedi_handle_events(dev, s);
1523 }
1524
1525 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1526                         void *data, unsigned int num_bytes,
1527                         unsigned int chan_index)
1528 {
1529         struct ni_private *devpriv = dev->private;
1530         struct comedi_async *async = s->async;
1531         struct comedi_cmd *cmd = &async->cmd;
1532         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1533         unsigned short *array = data;
1534         unsigned int *larray = data;
1535         unsigned int i;
1536 #ifdef PCIDMA
1537         __le16 *barray = data;
1538         __le32 *blarray = data;
1539 #endif
1540
1541         for (i = 0; i < nsamples; i++) {
1542 #ifdef PCIDMA
1543                 if (s->subdev_flags & SDF_LSAMPL)
1544                         larray[i] = le32_to_cpu(blarray[i]);
1545                 else
1546                         array[i] = le16_to_cpu(barray[i]);
1547 #endif
1548                 if (s->subdev_flags & SDF_LSAMPL)
1549                         larray[i] += devpriv->ai_offset[chan_index];
1550                 else
1551                         array[i] += devpriv->ai_offset[chan_index];
1552                 chan_index++;
1553                 chan_index %= cmd->chanlist_len;
1554         }
1555 }
1556
1557 #ifdef PCIDMA
1558
1559 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1560 {
1561         struct ni_private *devpriv = dev->private;
1562         struct comedi_subdevice *s = dev->read_subdev;
1563         int retval;
1564         unsigned long flags;
1565
1566         retval = ni_request_ai_mite_channel(dev);
1567         if (retval)
1568                 return retval;
1569
1570         /* write alloc the entire buffer */
1571         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1572
1573         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1574         if (!devpriv->ai_mite_chan) {
1575                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1576                 return -EIO;
1577         }
1578
1579         if (devpriv->is_611x || devpriv->is_6143)
1580                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1581         else if (devpriv->is_628x)
1582                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1583         else
1584                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1585
1586         /*start the MITE */
1587         mite_dma_arm(devpriv->ai_mite_chan);
1588         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1589
1590         return 0;
1591 }
1592
1593 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1594 {
1595         struct ni_private *devpriv = dev->private;
1596         struct comedi_subdevice *s = dev->write_subdev;
1597         int retval;
1598         unsigned long flags;
1599
1600         retval = ni_request_ao_mite_channel(dev);
1601         if (retval)
1602                 return retval;
1603
1604         /* read alloc the entire buffer */
1605         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1606
1607         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1608         if (devpriv->ao_mite_chan) {
1609                 if (devpriv->is_611x || devpriv->is_6713) {
1610                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1611                 } else {
1612                         /* doing 32 instead of 16 bit wide transfers from memory
1613                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1614                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1615                 }
1616                 mite_dma_arm(devpriv->ao_mite_chan);
1617         } else {
1618                 retval = -EIO;
1619         }
1620         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1621
1622         return retval;
1623 }
1624
1625 #endif /*  PCIDMA */
1626
1627 /*
1628    used for both cancel ioctl and board initialization
1629
1630    this is pretty harsh for a cancel, but it works...
1631  */
1632
1633 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1634 {
1635         struct ni_private *devpriv = dev->private;
1636         unsigned ai_personal;
1637         unsigned ai_out_ctrl;
1638
1639         ni_release_ai_mite_channel(dev);
1640         /* ai configuration */
1641         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1642                       NISTC_RESET_REG);
1643
1644         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1645
1646         ni_clear_ai_fifo(dev);
1647
1648         if (!devpriv->is_6143)
1649                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1650
1651         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1652         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1653                            NISTC_AI_MODE1_RSVD
1654                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1655                       NISTC_AI_MODE1_REG);
1656         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1657         /* generate FIFO interrupts on non-empty */
1658         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1659                       NISTC_AI_MODE3_REG);
1660
1661         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1662                       NISTC_AI_PERSONAL_SOC_POLARITY |
1663                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1664         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1665                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1666                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1667                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1668         if (devpriv->is_611x) {
1669                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1670         } else if (devpriv->is_6143) {
1671                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1672         } else {
1673                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1674                 if (devpriv->is_622x)
1675                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1676                 else
1677                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1678         }
1679         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1680         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1681
1682         /* the following registers should not be changed, because there
1683          * are no backup registers in devpriv.  If you want to change
1684          * any of these, add a backup register and other appropriate code:
1685          *      NISTC_AI_MODE1_REG
1686          *      NISTC_AI_MODE3_REG
1687          *      NISTC_AI_PERSONAL_REG
1688          *      NISTC_AI_OUT_CTRL_REG
1689          */
1690
1691         /* clear interrupts */
1692         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1693
1694         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1695
1696         return 0;
1697 }
1698
1699 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1700 {
1701         unsigned long flags;
1702         int count;
1703
1704         /*  lock to avoid race with interrupt handler */
1705         spin_lock_irqsave(&dev->spinlock, flags);
1706 #ifndef PCIDMA
1707         ni_handle_fifo_dregs(dev);
1708 #else
1709         ni_sync_ai_dma(dev);
1710 #endif
1711         count = comedi_buf_n_bytes_ready(s);
1712         spin_unlock_irqrestore(&dev->spinlock, flags);
1713
1714         return count;
1715 }
1716
1717 static void ni_prime_channelgain_list(struct comedi_device *dev)
1718 {
1719         int i;
1720
1721         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1722         for (i = 0; i < NI_TIMEOUT; ++i) {
1723                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1724                       NISTC_AI_STATUS1_FIFO_E)) {
1725                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1726                         return;
1727                 }
1728                 udelay(1);
1729         }
1730         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1731 }
1732
1733 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1734                                               unsigned int n_chan,
1735                                               unsigned int *list)
1736 {
1737         const struct ni_board_struct *board = dev->board_ptr;
1738         struct ni_private *devpriv = dev->private;
1739         unsigned int chan, range, aref;
1740         unsigned int i;
1741         unsigned int dither;
1742         unsigned range_code;
1743
1744         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1745
1746         if ((list[0] & CR_ALT_SOURCE)) {
1747                 unsigned bypass_bits;
1748
1749                 chan = CR_CHAN(list[0]);
1750                 range = CR_RANGE(list[0]);
1751                 range_code = ni_gainlkup[board->gainlkup][range];
1752                 dither = (list[0] & CR_ALT_FILTER) != 0;
1753                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1754                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1755                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1756                               devpriv->ai_calib_source;
1757                 if (dither)
1758                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1759                 /*  don't use 2's complement encoding */
1760                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1761                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1762         } else {
1763                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1764         }
1765         for (i = 0; i < n_chan; i++) {
1766                 unsigned config_bits = 0;
1767
1768                 chan = CR_CHAN(list[i]);
1769                 aref = CR_AREF(list[i]);
1770                 range = CR_RANGE(list[i]);
1771                 dither = (list[i] & CR_ALT_FILTER) != 0;
1772
1773                 range_code = ni_gainlkup[board->gainlkup][range];
1774                 devpriv->ai_offset[i] = 0;
1775                 switch (aref) {
1776                 case AREF_DIFF:
1777                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1778                         break;
1779                 case AREF_COMMON:
1780                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1781                         break;
1782                 case AREF_GROUND:
1783                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1784                         break;
1785                 case AREF_OTHER:
1786                         break;
1787                 }
1788                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1789                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1790                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1791                 if (i == n_chan - 1)
1792                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1793                 if (dither)
1794                         config_bits |= NI_M_AI_CFG_DITHER;
1795                 /*  don't use 2's complement encoding */
1796                 config_bits |= NI_M_AI_CFG_POLARITY;
1797                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1798         }
1799         ni_prime_channelgain_list(dev);
1800 }
1801
1802 /*
1803  * Notes on the 6110 and 6111:
1804  * These boards a slightly different than the rest of the series, since
1805  * they have multiple A/D converters.
1806  * From the driver side, the configuration memory is a
1807  * little different.
1808  * Configuration Memory Low:
1809  *   bits 15-9: same
1810  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1811  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1812  *       1001 gain=0.1 (+/- 50)
1813  *       1010 0.2
1814  *       1011 0.1
1815  *       0001 1
1816  *       0010 2
1817  *       0011 5
1818  *       0100 10
1819  *       0101 20
1820  *       0110 50
1821  * Configuration Memory High:
1822  *   bits 12-14: Channel Type
1823  *       001 for differential
1824  *       000 for calibration
1825  *   bit 11: coupling  (this is not currently handled)
1826  *       1 AC coupling
1827  *       0 DC coupling
1828  *   bits 0-2: channel
1829  *       valid channels are 0-3
1830  */
1831 static void ni_load_channelgain_list(struct comedi_device *dev,
1832                                      struct comedi_subdevice *s,
1833                                      unsigned int n_chan, unsigned int *list)
1834 {
1835         const struct ni_board_struct *board = dev->board_ptr;
1836         struct ni_private *devpriv = dev->private;
1837         unsigned int offset = (s->maxdata + 1) >> 1;
1838         unsigned int chan, range, aref;
1839         unsigned int i;
1840         unsigned int hi, lo;
1841         unsigned int dither;
1842
1843         if (devpriv->is_m_series) {
1844                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1845                 return;
1846         }
1847         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1848                 if (devpriv->changain_state
1849                     && devpriv->changain_spec == list[0]) {
1850                         /*  ready to go. */
1851                         return;
1852                 }
1853                 devpriv->changain_state = 1;
1854                 devpriv->changain_spec = list[0];
1855         } else {
1856                 devpriv->changain_state = 0;
1857         }
1858
1859         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1860
1861         /*  Set up Calibration mode if required */
1862         if (devpriv->is_6143) {
1863                 if ((list[0] & CR_ALT_SOURCE)
1864                     && !devpriv->ai_calib_source_enabled) {
1865                         /*  Strobe Relay enable bit */
1866                         ni_writew(dev, devpriv->ai_calib_source |
1867                                        NI6143_CALIB_CHAN_RELAY_ON,
1868                                   NI6143_CALIB_CHAN_REG);
1869                         ni_writew(dev, devpriv->ai_calib_source,
1870                                   NI6143_CALIB_CHAN_REG);
1871                         devpriv->ai_calib_source_enabled = 1;
1872                         msleep_interruptible(100);      /*  Allow relays to change */
1873                 } else if (!(list[0] & CR_ALT_SOURCE)
1874                            && devpriv->ai_calib_source_enabled) {
1875                         /*  Strobe Relay disable bit */
1876                         ni_writew(dev, devpriv->ai_calib_source |
1877                                        NI6143_CALIB_CHAN_RELAY_OFF,
1878                                   NI6143_CALIB_CHAN_REG);
1879                         ni_writew(dev, devpriv->ai_calib_source,
1880                                   NI6143_CALIB_CHAN_REG);
1881                         devpriv->ai_calib_source_enabled = 0;
1882                         msleep_interruptible(100);      /*  Allow relays to change */
1883                 }
1884         }
1885
1886         for (i = 0; i < n_chan; i++) {
1887                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1888                         chan = devpriv->ai_calib_source;
1889                 else
1890                         chan = CR_CHAN(list[i]);
1891                 aref = CR_AREF(list[i]);
1892                 range = CR_RANGE(list[i]);
1893                 dither = (list[i] & CR_ALT_FILTER) != 0;
1894
1895                 /* fix the external/internal range differences */
1896                 range = ni_gainlkup[board->gainlkup][range];
1897                 if (devpriv->is_611x)
1898                         devpriv->ai_offset[i] = offset;
1899                 else
1900                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1901
1902                 hi = 0;
1903                 if ((list[i] & CR_ALT_SOURCE)) {
1904                         if (devpriv->is_611x)
1905                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1906                                           NI611X_CALIB_CHAN_SEL_REG);
1907                 } else {
1908                         if (devpriv->is_611x)
1909                                 aref = AREF_DIFF;
1910                         else if (devpriv->is_6143)
1911                                 aref = AREF_OTHER;
1912                         switch (aref) {
1913                         case AREF_DIFF:
1914                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1915                                 break;
1916                         case AREF_COMMON:
1917                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1918                                 break;
1919                         case AREF_GROUND:
1920                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1921                                 break;
1922                         case AREF_OTHER:
1923                                 break;
1924                         }
1925                 }
1926                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1927
1928                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1929
1930                 if (!devpriv->is_6143) {
1931                         lo = NI_E_AI_CFG_LO_GAIN(range);
1932
1933                         if (i == n_chan - 1)
1934                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1935                         if (dither)
1936                                 lo |= NI_E_AI_CFG_LO_DITHER;
1937
1938                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1939                 }
1940         }
1941
1942         /* prime the channel/gain list */
1943         if (!devpriv->is_611x && !devpriv->is_6143)
1944                 ni_prime_channelgain_list(dev);
1945 }
1946
1947 static int ni_ai_insn_read(struct comedi_device *dev,
1948                            struct comedi_subdevice *s,
1949                            struct comedi_insn *insn,
1950                            unsigned int *data)
1951 {
1952         struct ni_private *devpriv = dev->private;
1953         unsigned int mask = (s->maxdata + 1) >> 1;
1954         int i, n;
1955         unsigned signbits;
1956         unsigned int d;
1957         unsigned long dl;
1958
1959         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1960
1961         ni_clear_ai_fifo(dev);
1962
1963         signbits = devpriv->ai_offset[0];
1964         if (devpriv->is_611x) {
1965                 for (n = 0; n < num_adc_stages_611x; n++) {
1966                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1967                                       NISTC_AI_CMD1_REG);
1968                         udelay(1);
1969                 }
1970                 for (n = 0; n < insn->n; n++) {
1971                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1972                                       NISTC_AI_CMD1_REG);
1973                         /* The 611x has screwy 32-bit FIFOs. */
1974                         d = 0;
1975                         for (i = 0; i < NI_TIMEOUT; i++) {
1976                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1977                                         d = ni_readl(dev,
1978                                                      NI611X_AI_FIFO_DATA_REG);
1979                                         d >>= 16;
1980                                         d &= 0xffff;
1981                                         break;
1982                                 }
1983                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1984                                       NISTC_AI_STATUS1_FIFO_E)) {
1985                                         d = ni_readl(dev,
1986                                                      NI611X_AI_FIFO_DATA_REG);
1987                                         d &= 0xffff;
1988                                         break;
1989                                 }
1990                         }
1991                         if (i == NI_TIMEOUT) {
1992                                 dev_err(dev->class_dev, "timeout\n");
1993                                 return -ETIME;
1994                         }
1995                         d += signbits;
1996                         data[n] = d;
1997                 }
1998         } else if (devpriv->is_6143) {
1999                 for (n = 0; n < insn->n; n++) {
2000                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2001                                       NISTC_AI_CMD1_REG);
2002
2003                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
2004                         dl = 0;
2005                         for (i = 0; i < NI_TIMEOUT; i++) {
2006                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
2007                                     0x01) {
2008                                         /* Get stranded sample into FIFO */
2009                                         ni_writel(dev, 0x01,
2010                                                   NI6143_AI_FIFO_CTRL_REG);
2011                                         dl = ni_readl(dev,
2012                                                       NI6143_AI_FIFO_DATA_REG);
2013                                         break;
2014                                 }
2015                         }
2016                         if (i == NI_TIMEOUT) {
2017                                 dev_err(dev->class_dev, "timeout\n");
2018                                 return -ETIME;
2019                         }
2020                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2021                 }
2022         } else {
2023                 for (n = 0; n < insn->n; n++) {
2024                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2025                                       NISTC_AI_CMD1_REG);
2026                         for (i = 0; i < NI_TIMEOUT; i++) {
2027                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
2028                                       NISTC_AI_STATUS1_FIFO_E))
2029                                         break;
2030                         }
2031                         if (i == NI_TIMEOUT) {
2032                                 dev_err(dev->class_dev, "timeout\n");
2033                                 return -ETIME;
2034                         }
2035                         if (devpriv->is_m_series) {
2036                                 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2037                                 dl &= mask;
2038                                 data[n] = dl;
2039                         } else {
2040                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2041                                 d += signbits;  /* subtle: needs to be short addition */
2042                                 data[n] = d;
2043                         }
2044                 }
2045         }
2046         return insn->n;
2047 }
2048
2049 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2050                           unsigned int flags)
2051 {
2052         struct ni_private *devpriv = dev->private;
2053         int divider;
2054
2055         switch (flags & CMDF_ROUND_MASK) {
2056         case CMDF_ROUND_NEAREST:
2057         default:
2058                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2059                 break;
2060         case CMDF_ROUND_DOWN:
2061                 divider = (nanosec) / devpriv->clock_ns;
2062                 break;
2063         case CMDF_ROUND_UP:
2064                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2065                 break;
2066         }
2067         return divider - 1;
2068 }
2069
2070 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2071 {
2072         struct ni_private *devpriv = dev->private;
2073
2074         return devpriv->clock_ns * (timer + 1);
2075 }
2076
2077 static void ni_cmd_set_mite_transfer(struct mite_dma_descriptor_ring *ring,
2078                                      struct comedi_subdevice *sdev,
2079                                      const struct comedi_cmd *cmd,
2080                                      unsigned int max_count) {
2081 #ifdef PCIDMA
2082         unsigned int nbytes = max_count;
2083
2084         if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
2085                 nbytes = cmd->stop_arg;
2086         nbytes *= comedi_bytes_per_scan(sdev);
2087
2088         if (nbytes > sdev->async->prealloc_bufsz) {
2089                 if (cmd->stop_arg > 0)
2090                         dev_err(sdev->device->class_dev,
2091                                 "ni_cmd_set_mite_transfer: tried exact data transfer limits greater than buffer size\n");
2092
2093                 /*
2094                  * we can only transfer up to the size of the buffer.  In this
2095                  * case, the user is expected to continue to write into the
2096                  * comedi buffer (already implemented as a ring buffer).
2097                  */
2098                 nbytes = sdev->async->prealloc_bufsz;
2099         }
2100
2101         mite_init_ring_descriptors(ring, sdev, nbytes);
2102 #else
2103         dev_err(sdev->device->class_dev,
2104                 "ni_cmd_set_mite_transfer: exact data transfer limits not implemented yet without DMA\n");
2105 #endif
2106 }
2107
2108 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2109                                          unsigned num_channels)
2110 {
2111         const struct ni_board_struct *board = dev->board_ptr;
2112         struct ni_private *devpriv = dev->private;
2113
2114         /* simultaneously-sampled inputs */
2115         if (devpriv->is_611x || devpriv->is_6143)
2116                 return board->ai_speed;
2117
2118         /* multiplexed inputs */
2119         return board->ai_speed * num_channels;
2120 }
2121
2122 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2123                          struct comedi_cmd *cmd)
2124 {
2125         const struct ni_board_struct *board = dev->board_ptr;
2126         struct ni_private *devpriv = dev->private;
2127         int err = 0;
2128         unsigned int tmp;
2129         unsigned int sources;
2130
2131         /* Step 1 : check if triggers are trivially valid */
2132
2133         err |= comedi_check_trigger_src(&cmd->start_src,
2134                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2135         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2136                                         TRIG_TIMER | TRIG_EXT);
2137
2138         sources = TRIG_TIMER | TRIG_EXT;
2139         if (devpriv->is_611x || devpriv->is_6143)
2140                 sources |= TRIG_NOW;
2141         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2142
2143         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2144         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2145
2146         if (err)
2147                 return 1;
2148
2149         /* Step 2a : make sure trigger sources are unique */
2150
2151         err |= comedi_check_trigger_is_unique(cmd->start_src);
2152         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2153         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2154         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2155
2156         /* Step 2b : and mutually compatible */
2157
2158         if (err)
2159                 return 2;
2160
2161         /* Step 3: check if arguments are trivially valid */
2162
2163         switch (cmd->start_src) {
2164         case TRIG_NOW:
2165         case TRIG_INT:
2166                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2167                 break;
2168         case TRIG_EXT:
2169                 tmp = CR_CHAN(cmd->start_arg);
2170
2171                 if (tmp > 16)
2172                         tmp = 16;
2173                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2174                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2175                 break;
2176         }
2177
2178         if (cmd->scan_begin_src == TRIG_TIMER) {
2179                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2180                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2181                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2182                                                     devpriv->clock_ns *
2183                                                     0xffffff);
2184         } else if (cmd->scan_begin_src == TRIG_EXT) {
2185                 /* external trigger */
2186                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2187
2188                 if (tmp > 16)
2189                         tmp = 16;
2190                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2191                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2192         } else {                /* TRIG_OTHER */
2193                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2194         }
2195
2196         if (cmd->convert_src == TRIG_TIMER) {
2197                 if (devpriv->is_611x || devpriv->is_6143) {
2198                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2199                                                            0);
2200                 } else {
2201                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2202                                                             board->ai_speed);
2203                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2204                                                             devpriv->clock_ns *
2205                                                             0xffff);
2206                 }
2207         } else if (cmd->convert_src == TRIG_EXT) {
2208                 /* external trigger */
2209                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2210
2211                 if (tmp > 16)
2212                         tmp = 16;
2213                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2214                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2215         } else if (cmd->convert_src == TRIG_NOW) {
2216                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2217         }
2218
2219         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2220                                            cmd->chanlist_len);
2221
2222         if (cmd->stop_src == TRIG_COUNT) {
2223                 unsigned int max_count = 0x01000000;
2224
2225                 if (devpriv->is_611x)
2226                         max_count -= num_adc_stages_611x;
2227                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2228                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2229         } else {
2230                 /* TRIG_NONE */
2231                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2232         }
2233
2234         if (err)
2235                 return 3;
2236
2237         /* step 4: fix up any arguments */
2238
2239         if (cmd->scan_begin_src == TRIG_TIMER) {
2240                 tmp = cmd->scan_begin_arg;
2241                 cmd->scan_begin_arg =
2242                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2243                                                        cmd->scan_begin_arg,
2244                                                        cmd->flags));
2245                 if (tmp != cmd->scan_begin_arg)
2246                         err++;
2247         }
2248         if (cmd->convert_src == TRIG_TIMER) {
2249                 if (!devpriv->is_611x && !devpriv->is_6143) {
2250                         tmp = cmd->convert_arg;
2251                         cmd->convert_arg =
2252                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2253                                                                cmd->convert_arg,
2254                                                                cmd->flags));
2255                         if (tmp != cmd->convert_arg)
2256                                 err++;
2257                         if (cmd->scan_begin_src == TRIG_TIMER &&
2258                             cmd->scan_begin_arg <
2259                             cmd->convert_arg * cmd->scan_end_arg) {
2260                                 cmd->scan_begin_arg =
2261                                     cmd->convert_arg * cmd->scan_end_arg;
2262                                 err++;
2263                         }
2264                 }
2265         }
2266
2267         if (err)
2268                 return 4;
2269
2270         return 0;
2271 }
2272
2273 static int ni_ai_inttrig(struct comedi_device *dev,
2274                          struct comedi_subdevice *s,
2275                          unsigned int trig_num)
2276 {
2277         struct ni_private *devpriv = dev->private;
2278         struct comedi_cmd *cmd = &s->async->cmd;
2279
2280         if (trig_num != cmd->start_arg)
2281                 return -EINVAL;
2282
2283         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2284                       NISTC_AI_CMD2_REG);
2285         s->async->inttrig = NULL;
2286
2287         return 1;
2288 }
2289
2290 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2291 {
2292         struct ni_private *devpriv = dev->private;
2293         const struct comedi_cmd *cmd = &s->async->cmd;
2294         int timer;
2295         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2296         int mode2 = 0;
2297         int start_stop_select = 0;
2298         unsigned int stop_count;
2299         int interrupt_a_enable = 0;
2300         unsigned ai_trig;
2301
2302         if (dev->irq == 0) {
2303                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2304                 return -EIO;
2305         }
2306         ni_clear_ai_fifo(dev);
2307
2308         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2309
2310         /* start configuration */
2311         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2312
2313         /* disable analog triggering for now, since it
2314          * interferes with the use of pfi0 */
2315         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2316         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2317
2318         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2319         switch (cmd->start_src) {
2320         case TRIG_INT:
2321         case TRIG_NOW:
2322                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2323                            NISTC_AI_TRIG_START1_SEL(0);
2324                 break;
2325         case TRIG_EXT:
2326                 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2327                                                     1);
2328
2329                 if (cmd->start_arg & CR_INVERT)
2330                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2331                 if (cmd->start_arg & CR_EDGE)
2332                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2333                 break;
2334         }
2335         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2336
2337         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2338         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2339         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2340         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2341
2342         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2343                 /* logic low */
2344                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2345                                      NISTC_AI_STOP_SEL(31) |
2346                                      NISTC_AI_STOP_SYNC;
2347         } else {
2348                 /*  ai configuration memory */
2349                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2350         }
2351         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2352
2353         devpriv->ai_cmd2 = 0;
2354         switch (cmd->stop_src) {
2355         case TRIG_COUNT:
2356                 stop_count = cmd->stop_arg - 1;
2357
2358                 if (devpriv->is_611x) {
2359                         /*  have to take 3 stage adc pipeline into account */
2360                         stop_count += num_adc_stages_611x;
2361                 }
2362                 /* stage number of scans */
2363                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2364
2365                 mode1 |= NISTC_AI_MODE1_START_STOP |
2366                          NISTC_AI_MODE1_RSVD |
2367                          NISTC_AI_MODE1_TRIGGER_ONCE;
2368                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2369                 /* load SC (Scan Count) */
2370                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2371
2372                 if (stop_count == 0) {
2373                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2374                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2375                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2376                         if (cmd->chanlist_len > 1)
2377                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2378                                                      NISTC_AI_STOP_EDGE;
2379                 }
2380                 break;
2381         case TRIG_NONE:
2382                 /* stage number of scans */
2383                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2384
2385                 mode1 |= NISTC_AI_MODE1_START_STOP |
2386                          NISTC_AI_MODE1_RSVD |
2387                          NISTC_AI_MODE1_CONTINUOUS;
2388                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2389
2390                 /* load SC (Scan Count) */
2391                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2392                 break;
2393         }
2394
2395         switch (cmd->scan_begin_src) {
2396         case TRIG_TIMER:
2397                 /*
2398                  * stop bits for non 611x boards
2399                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2400                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2401                  * NISTC_AI_START_STOP_REG:
2402                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2403                  * NISTC_AI_START_EDGE=1        edge triggered
2404                  * NISTC_AI_START_SYNC=1        (?)
2405                  * NISTC_AI_START_SEL=0         SI_TC
2406                  * NISTC_AI_STOP_POLARITY=0     rising edge
2407                  * NISTC_AI_STOP_EDGE=0         level
2408                  * NISTC_AI_STOP_SYNC=1
2409                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2410                  */
2411                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2412                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2413
2414                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2415                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2416                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2417                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2418
2419                 /* load SI */
2420                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2421                                        CMDF_ROUND_NEAREST);
2422                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2423                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2424                 break;
2425         case TRIG_EXT:
2426                 if (cmd->scan_begin_arg & CR_EDGE)
2427                         start_stop_select |= NISTC_AI_START_EDGE;
2428                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2429                         start_stop_select |= NISTC_AI_START_POLARITY;
2430                 if (cmd->scan_begin_src != cmd->convert_src ||
2431                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2432                     (cmd->convert_arg & ~CR_EDGE))
2433                         start_stop_select |= NISTC_AI_START_SYNC;
2434                 start_stop_select |=
2435                     NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2436                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2437                 break;
2438         }
2439
2440         switch (cmd->convert_src) {
2441         case TRIG_TIMER:
2442         case TRIG_NOW:
2443                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2444                         timer = 1;
2445                 else
2446                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2447                                                CMDF_ROUND_NEAREST);
2448                 /* 0,0 does not work */
2449                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2450                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2451
2452                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2453                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2454                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2455
2456                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2457
2458                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2459                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2460                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2461                 break;
2462         case TRIG_EXT:
2463                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 +
2464                                                     CR_CHAN(cmd->convert_arg));
2465                 if ((cmd->convert_arg & CR_INVERT) == 0)
2466                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2467                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2468
2469                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2470                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2471                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2472
2473                 break;
2474         }
2475
2476         if (dev->irq) {
2477                 /* interrupt on FIFO, errors, SC_TC */
2478                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2479                                       NISTC_INTA_ENA_AI_SC_TC;
2480
2481 #ifndef PCIDMA
2482                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2483 #endif
2484
2485                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2486                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2487                         /* wake on end-of-scan */
2488                         devpriv->aimode = AIMODE_SCAN;
2489                 } else {
2490                         devpriv->aimode = AIMODE_HALF_FULL;
2491                 }
2492
2493                 switch (devpriv->aimode) {
2494                 case AIMODE_HALF_FULL:
2495                         /*generate FIFO interrupts and DMA requests on half-full */
2496 #ifdef PCIDMA
2497                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2498                                       NISTC_AI_MODE3_REG);
2499 #else
2500                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2501                                       NISTC_AI_MODE3_REG);
2502 #endif
2503                         break;
2504                 case AIMODE_SAMPLE:
2505                         /*generate FIFO interrupts on non-empty */
2506                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2507                                       NISTC_AI_MODE3_REG);
2508                         break;
2509                 case AIMODE_SCAN:
2510 #ifdef PCIDMA
2511                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2512                                       NISTC_AI_MODE3_REG);
2513 #else
2514                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2515                                       NISTC_AI_MODE3_REG);
2516 #endif
2517                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2518                         break;
2519                 default:
2520                         break;
2521                 }
2522
2523                 /* clear interrupts */
2524                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2525
2526                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2527         } else {
2528                 /* interrupt on nothing */
2529                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2530
2531                 /* XXX start polling if necessary */
2532         }
2533
2534         /* end configuration */
2535         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2536
2537         switch (cmd->scan_begin_src) {
2538         case TRIG_TIMER:
2539                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2540                                    NISTC_AI_CMD1_SI_ARM |
2541                                    NISTC_AI_CMD1_DIV_ARM |
2542                                    NISTC_AI_CMD1_SC_ARM,
2543                               NISTC_AI_CMD1_REG);
2544                 break;
2545         case TRIG_EXT:
2546                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2547                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2548                                    NISTC_AI_CMD1_DIV_ARM |
2549                                    NISTC_AI_CMD1_SC_ARM,
2550                               NISTC_AI_CMD1_REG);
2551                 break;
2552         }
2553
2554 #ifdef PCIDMA
2555         {
2556                 int retval = ni_ai_setup_MITE_dma(dev);
2557
2558                 if (retval)
2559                         return retval;
2560         }
2561 #endif
2562
2563         if (cmd->start_src == TRIG_NOW) {
2564                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2565                                    devpriv->ai_cmd2,
2566                               NISTC_AI_CMD2_REG);
2567                 s->async->inttrig = NULL;
2568         } else if (cmd->start_src == TRIG_EXT) {
2569                 s->async->inttrig = NULL;
2570         } else {        /* TRIG_INT */
2571                 s->async->inttrig = ni_ai_inttrig;
2572         }
2573
2574         return 0;
2575 }
2576
2577 static int ni_ai_insn_config(struct comedi_device *dev,
2578                              struct comedi_subdevice *s,
2579                              struct comedi_insn *insn, unsigned int *data)
2580 {
2581         struct ni_private *devpriv = dev->private;
2582
2583         if (insn->n < 1)
2584                 return -EINVAL;
2585
2586         switch (data[0]) {
2587         case INSN_CONFIG_ALT_SOURCE:
2588                 if (devpriv->is_m_series) {
2589                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2590                                 return -EINVAL;
2591                         devpriv->ai_calib_source = data[1];
2592                 } else if (devpriv->is_6143) {
2593                         unsigned int calib_source;
2594
2595                         calib_source = data[1] & 0xf;
2596
2597                         devpriv->ai_calib_source = calib_source;
2598                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2599                 } else {
2600                         unsigned int calib_source;
2601                         unsigned int calib_source_adjust;
2602
2603                         calib_source = data[1] & 0xf;
2604                         calib_source_adjust = (data[1] >> 4) & 0xff;
2605
2606                         if (calib_source >= 8)
2607                                 return -EINVAL;
2608                         devpriv->ai_calib_source = calib_source;
2609                         if (devpriv->is_611x) {
2610                                 ni_writeb(dev, calib_source_adjust,
2611                                           NI611X_CAL_GAIN_SEL_REG);
2612                         }
2613                 }
2614                 return 2;
2615         default:
2616                 break;
2617         }
2618
2619         return -EINVAL;
2620 }
2621
2622 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2623                         void *data, unsigned int num_bytes,
2624                         unsigned int chan_index)
2625 {
2626         struct comedi_cmd *cmd = &s->async->cmd;
2627         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2628         unsigned short *array = data;
2629         unsigned int i;
2630 #ifdef PCIDMA
2631         __le16 buf, *barray = data;
2632 #endif
2633
2634         for (i = 0; i < nsamples; i++) {
2635                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2636                 unsigned short val = array[i];
2637
2638                 /*
2639                  * Munge data from unsigned to two's complement for
2640                  * bipolar ranges.
2641                  */
2642                 if (comedi_range_is_bipolar(s, range))
2643                         val = comedi_offset_munge(s, val);
2644 #ifdef PCIDMA
2645                 buf = cpu_to_le16(val);
2646                 barray[i] = buf;
2647 #else
2648                 array[i] = val;
2649 #endif
2650                 chan_index++;
2651                 chan_index %= cmd->chanlist_len;
2652         }
2653 }
2654
2655 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2656                                           struct comedi_subdevice *s,
2657                                           unsigned int chanspec[],
2658                                           unsigned int n_chans, int timed)
2659 {
2660         struct ni_private *devpriv = dev->private;
2661         unsigned int range;
2662         unsigned int chan;
2663         unsigned int conf;
2664         int i;
2665         int invert = 0;
2666
2667         if (timed) {
2668                 for (i = 0; i < s->n_chan; ++i) {
2669                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2670                         ni_writeb(dev, devpriv->ao_conf[i],
2671                                   NI_M_AO_CFG_BANK_REG(i));
2672                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2673                 }
2674         }
2675         for (i = 0; i < n_chans; i++) {
2676                 const struct comedi_krange *krange;
2677
2678                 chan = CR_CHAN(chanspec[i]);
2679                 range = CR_RANGE(chanspec[i]);
2680                 krange = s->range_table->range + range;
2681                 invert = 0;
2682                 conf = 0;
2683                 switch (krange->max - krange->min) {
2684                 case 20000000:
2685                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2686                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2687                         break;
2688                 case 10000000:
2689                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2690                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2691                         break;
2692                 case 4000000:
2693                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2694                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2695                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2696                         break;
2697                 case 2000000:
2698                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2699                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2700                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2701                         break;
2702                 default:
2703                         dev_err(dev->class_dev,
2704                                 "bug! unhandled ao reference voltage\n");
2705                         break;
2706                 }
2707                 switch (krange->max + krange->min) {
2708                 case 0:
2709                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2710                         break;
2711                 case 10000000:
2712                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2713                         break;
2714                 default:
2715                         dev_err(dev->class_dev,
2716                                 "bug! unhandled ao offset voltage\n");
2717                         break;
2718                 }
2719                 if (timed)
2720                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2721                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2722                 devpriv->ao_conf[chan] = conf;
2723                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2724         }
2725         return invert;
2726 }
2727
2728 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2729                                      struct comedi_subdevice *s,
2730                                      unsigned int chanspec[],
2731                                      unsigned int n_chans)
2732 {
2733         struct ni_private *devpriv = dev->private;
2734         unsigned int range;
2735         unsigned int chan;
2736         unsigned int conf;
2737         int i;
2738         int invert = 0;
2739
2740         for (i = 0; i < n_chans; i++) {
2741                 chan = CR_CHAN(chanspec[i]);
2742                 range = CR_RANGE(chanspec[i]);
2743                 conf = NI_E_AO_DACSEL(chan);
2744
2745                 if (comedi_range_is_bipolar(s, range)) {
2746                         conf |= NI_E_AO_CFG_BIP;
2747                         invert = (s->maxdata + 1) >> 1;
2748                 } else {
2749                         invert = 0;
2750                 }
2751                 if (comedi_range_is_external(s, range))
2752                         conf |= NI_E_AO_EXT_REF;
2753
2754                 /* not all boards can deglitch, but this shouldn't hurt */
2755                 if (chanspec[i] & CR_DEGLITCH)
2756                         conf |= NI_E_AO_DEGLITCH;
2757
2758                 /* analog reference */
2759                 /* AREF_OTHER connects AO ground to AI ground, i think */
2760                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2761                         conf |= NI_E_AO_GROUND_REF;
2762
2763                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2764                 devpriv->ao_conf[chan] = conf;
2765         }
2766         return invert;
2767 }
2768
2769 static int ni_ao_config_chanlist(struct comedi_device *dev,
2770                                  struct comedi_subdevice *s,
2771                                  unsigned int chanspec[], unsigned int n_chans,
2772                                  int timed)
2773 {
2774         struct ni_private *devpriv = dev->private;
2775
2776         if (devpriv->is_m_series)
2777                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2778                                                       timed);
2779         else
2780                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2781 }
2782
2783 static int ni_ao_insn_write(struct comedi_device *dev,
2784                             struct comedi_subdevice *s,
2785                             struct comedi_insn *insn,
2786                             unsigned int *data)
2787 {
2788         struct ni_private *devpriv = dev->private;
2789         unsigned int chan = CR_CHAN(insn->chanspec);
2790         unsigned int range = CR_RANGE(insn->chanspec);
2791         int reg;
2792         int i;
2793
2794         if (devpriv->is_6xxx) {
2795                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2796
2797                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2798         } else if (devpriv->is_m_series) {
2799                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2800         } else {
2801                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2802         }
2803
2804         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2805
2806         for (i = 0; i < insn->n; i++) {
2807                 unsigned int val = data[i];
2808
2809                 s->readback[chan] = val;
2810
2811                 if (devpriv->is_6xxx) {
2812                         /*
2813                          * 6xxx boards have bipolar outputs, munge the
2814                          * unsigned comedi values to 2's complement
2815                          */
2816                         val = comedi_offset_munge(s, val);
2817
2818                         ni_ao_win_outw(dev, val, reg);
2819                 } else if (devpriv->is_m_series) {
2820                         /*
2821                          * M-series boards use offset binary values for
2822                          * bipolar and uinpolar outputs
2823                          */
2824                         ni_writew(dev, val, reg);
2825                 } else {
2826                         /*
2827                          * Non-M series boards need two's complement values
2828                          * for bipolar ranges.
2829                          */
2830                         if (comedi_range_is_bipolar(s, range))
2831                                 val = comedi_offset_munge(s, val);
2832
2833                         ni_writew(dev, val, reg);
2834                 }
2835         }
2836
2837         return insn->n;
2838 }
2839
2840 static int ni_ao_insn_config(struct comedi_device *dev,
2841                              struct comedi_subdevice *s,
2842                              struct comedi_insn *insn, unsigned int *data)
2843 {
2844         const struct ni_board_struct *board = dev->board_ptr;
2845         struct ni_private *devpriv = dev->private;
2846         unsigned int nbytes;
2847
2848         switch (data[0]) {
2849         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2850                 switch (data[1]) {
2851                 case COMEDI_OUTPUT:
2852                         nbytes = comedi_samples_to_bytes(s,
2853                                                          board->ao_fifo_depth);
2854                         data[2] = 1 + nbytes;
2855                         if (devpriv->mite)
2856                                 data[2] += devpriv->mite->fifo_size;
2857                         break;
2858                 case COMEDI_INPUT:
2859                         data[2] = 0;
2860                         break;
2861                 default:
2862                         return -EINVAL;
2863                 }
2864                 return 0;
2865         default:
2866                 break;
2867         }
2868
2869         return -EINVAL;
2870 }
2871
2872 static int ni_ao_inttrig(struct comedi_device *dev,
2873                          struct comedi_subdevice *s,
2874                          unsigned int trig_num)
2875 {
2876         struct ni_private *devpriv = dev->private;
2877         struct comedi_cmd *cmd = &s->async->cmd;
2878         int ret;
2879         int interrupt_b_bits;
2880         int i;
2881         static const int timeout = 1000;
2882
2883         if (trig_num != cmd->start_arg)
2884                 return -EINVAL;
2885
2886         /* Null trig at beginning prevent ao start trigger from executing more than
2887            once per command (and doing things like trying to allocate the ao dma channel
2888            multiple times) */
2889         s->async->inttrig = NULL;
2890
2891         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2892                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2893         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2894 #ifdef PCIDMA
2895         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2896         if (devpriv->is_6xxx)
2897                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2898         ret = ni_ao_setup_MITE_dma(dev);
2899         if (ret)
2900                 return ret;
2901         ret = ni_ao_wait_for_dma_load(dev);
2902         if (ret < 0)
2903                 return ret;
2904 #else
2905         ret = ni_ao_prep_fifo(dev, s);
2906         if (ret == 0)
2907                 return -EPIPE;
2908
2909         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2910 #endif
2911
2912         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2913                       NISTC_AO_MODE3_REG);
2914         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2915         /* wait for DACs to be loaded */
2916         for (i = 0; i < timeout; i++) {
2917                 udelay(1);
2918                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2919                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2920                         break;
2921         }
2922         if (i == timeout) {
2923                 dev_err(dev->class_dev,
2924                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2925                 return -EIO;
2926         }
2927         /*
2928          * stc manual says we are need to clear error interrupt after
2929          * AO_TMRDACWRs_In_Progress_St clears
2930          */
2931         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2932
2933         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2934
2935         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2936                            NISTC_AO_CMD1_UC_ARM |
2937                            NISTC_AO_CMD1_BC_ARM |
2938                            devpriv->ao_cmd1,
2939                       NISTC_AO_CMD1_REG);
2940
2941         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2942                       NISTC_AO_CMD2_REG);
2943
2944         return 0;
2945 }
2946
2947 /*
2948  * begin ni_ao_cmd.
2949  * Organized similar to NI-STC and MHDDK examples.
2950  * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2951  */
2952
2953 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2954                                   const struct comedi_cmd *cmd)
2955 {
2956         const struct ni_board_struct *board = dev->board_ptr;
2957         unsigned bits;
2958
2959         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2960
2961         bits =
2962           /* fast CPU interface--only eseries */
2963           /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2964           NISTC_AO_PERSONAL_BC_SRC_SEL  |
2965           0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2966           /*
2967            * FIXME:  start setting following bit when appropriate.  Need to
2968            * determine whether board is E4 or E1.
2969            * FROM MHHDK:
2970            * if board is E4 or E1
2971            *   Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2972            * else
2973            *   set it to 1
2974            */
2975           NISTC_AO_PERSONAL_UPDATE_PW   |
2976           /* FIXME:  when should we set following bit to zero? */
2977           NISTC_AO_PERSONAL_TMRDACWR_PW |
2978           (board->ao_fifo_depth ?
2979             NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2980           ;
2981 #if 0
2982         /*
2983          * FIXME:
2984          * add something like ".has_individual_dacs = 0" to ni_board_struct
2985          * since, as F Hess pointed out, not all in m series have singles.  not
2986          * sure if e-series all have duals...
2987          */
2988
2989         /*
2990          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2991          * 6281, verified with bus analyzer.
2992          */
2993         if (devpriv->is_m_series)
2994                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2995 #endif
2996         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2997
2998         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2999 }
3000
3001 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
3002                                   const struct comedi_cmd *cmd)
3003 {
3004         struct ni_private *devpriv = dev->private;
3005
3006         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3007
3008         /* sync */
3009         if (cmd->stop_src == TRIG_NONE) {
3010                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
3011                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
3012         } else {
3013                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
3014                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
3015         }
3016         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3017
3018         {
3019                 unsigned int trigsel = devpriv->ao_trigger_select;
3020
3021                 switch (cmd->start_src) {
3022                 case TRIG_INT:
3023                 case TRIG_NOW:
3024                         trigsel &= ~(NISTC_AO_TRIG_START1_POLARITY |
3025                                      NISTC_AO_TRIG_START1_SEL_MASK);
3026                         trigsel |= NISTC_AO_TRIG_START1_EDGE |
3027                                    NISTC_AO_TRIG_START1_SYNC;
3028                         break;
3029                 case TRIG_EXT:
3030                         trigsel = NISTC_AO_TRIG_START1_SEL(
3031                                         CR_CHAN(cmd->start_arg) + 1);
3032                         if (cmd->start_arg & CR_INVERT)
3033                                 /*
3034                                  * 0=active high, 1=active low.
3035                                  * see daq-stc 3-24 (p186)
3036                                  */
3037                                 trigsel |= NISTC_AO_TRIG_START1_POLARITY;
3038                         if (cmd->start_arg & CR_EDGE)
3039                                 /* 0=edge detection disabled, 1=enabled */
3040                                 trigsel |= NISTC_AO_TRIG_START1_EDGE;
3041                         break;
3042                 default:
3043                         BUG();
3044                         break;
3045                 }
3046
3047                 devpriv->ao_trigger_select = trigsel;
3048                 ni_stc_writew(dev, devpriv->ao_trigger_select,
3049                               NISTC_AO_TRIG_SEL_REG);
3050         }
3051         /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
3052
3053         /* sync */
3054         /* select DA_START1 as PFI6/AO_START1 when configured as an output */
3055         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
3056         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3057
3058         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3059 }
3060
3061 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
3062                                    const struct comedi_cmd *cmd)
3063 {
3064         struct ni_private *devpriv = dev->private;
3065         /* Not supporting 'waveform staging' or 'local buffer with pauses' */
3066
3067         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3068         /*
3069          * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
3070          * set_trigger above.  It is unclear whether we really need to re-write
3071          * this register with these values.  The mhddk examples for e-series
3072          * show writing this in both places, but the examples for m-series show
3073          * a single write in the set_counters function (here).
3074          */
3075         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3076
3077         /* sync (upload number of buffer iterations -1) */
3078         /* indicate that we want to use BC_Load_A_Register as the source */
3079         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3080         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3081
3082         /*
3083          * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3084          * ignoring BC_TC, then we will need to find a way to ignore that
3085          * interrupt in continuous mode.
3086          */
3087         ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3088
3089         /* sync (issue command to load number of buffer iterations -1) */
3090         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3091
3092         /* sync (upload number of updates in buffer) */
3093         /* indicate that we want to use UC_Load_A_Register as the source */
3094         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3095         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3096
3097         /*
3098          * if a user specifies '0', this automatically assumes the entire 24bit
3099          * address space is available for the (multiple iterations of single
3100          * buffer) MISB.  Otherwise, stop_arg specifies the MISB length that
3101          * will be used, regardless of whether we are in continuous mode or not.
3102          * In continuous mode, the output will just iterate indefinitely over
3103          * the MISB.
3104          */
3105         {
3106                 unsigned int stop_arg = cmd->stop_arg > 0 ?
3107                         (cmd->stop_arg & 0xffffff) : 0xffffff;
3108
3109                 if (devpriv->is_m_series) {
3110                         /*
3111                          * this is how the NI example code does it for m-series
3112                          * boards, verified correct with 6259
3113                          */
3114                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3115
3116                         /* sync (issue cmd to load number of updates in MISB) */
3117                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3118                                       NISTC_AO_CMD1_REG);
3119                 } else {
3120                         ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3121
3122                         /* sync (issue cmd to load number of updates in MISB) */
3123                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3124                                       NISTC_AO_CMD1_REG);
3125
3126                         /*
3127                          * sync (upload number of updates-1 in MISB)
3128                          * --eseries only?
3129                          */
3130                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3131                 }
3132         }
3133
3134         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3135 }
3136
3137 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3138                                  const struct comedi_cmd *cmd)
3139 {
3140         struct ni_private *devpriv = dev->private;
3141
3142         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3143
3144         /*
3145          * zero out these bit fields to be set below. Does an ao-reset do this
3146          * automatically?
3147          */
3148         devpriv->ao_mode1 &= ~(
3149           NISTC_AO_MODE1_UI_SRC_MASK         |
3150           NISTC_AO_MODE1_UI_SRC_POLARITY     |
3151           NISTC_AO_MODE1_UPDATE_SRC_MASK     |
3152           NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3153         );
3154
3155         switch (cmd->scan_begin_src) {
3156         case TRIG_TIMER:
3157                 devpriv->ao_cmd2  &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3158
3159                 /*
3160                  * NOTE: there are several other ways of configuring internal
3161                  * updates, but we'll only support one for now:  using
3162                  * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3163                  * START1 and first update, and also w/o local buffer mode w/
3164                  * pauses.
3165                  */
3166
3167                 /*
3168                  * This is already done above:
3169                  * devpriv->ao_mode1 &= ~(
3170                  *   // set UPDATE_Source to UI_TC:
3171                  *   NISTC_AO_MODE1_UPDATE_SRC_MASK |
3172                  *   // set UPDATE_Source_Polarity to rising (required?)
3173                  *   NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3174                  *   // set UI_Source to AO_IN_TIMEBASE1:
3175                  *   NISTC_AO_MODE1_UI_SRC_MASK     |
3176                  *   // set UI_Source_Polarity to rising (required?)
3177                  *   NISTC_AO_MODE1_UI_SRC_POLARITY
3178                  * );
3179                  */
3180
3181                 /*
3182                  * TODO:  use ao_ui_clock_source to allow all possible signals
3183                  * to be routed to UI_Source_Select.  See tSTC.h for
3184                  * eseries/ni67xx and tMSeries.h for mseries.
3185                  */
3186
3187                 {
3188                         unsigned trigvar = ni_ns_to_timer(dev,
3189                                                           cmd->scan_begin_arg,
3190                                                           CMDF_ROUND_NEAREST);
3191
3192                         /*
3193                          * Wait N TB3 ticks after the start trigger before
3194                          * clocking(N must be >=2).
3195                          */
3196                         /* following line: 2-1 per STC */
3197                         ni_stc_writel(dev, 1,           NISTC_AO_UI_LOADA_REG);
3198                         ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD,
3199                                       NISTC_AO_CMD1_REG);
3200                         /* following line: N-1 per STC */
3201                         ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG);
3202                 }
3203                 break;
3204         case TRIG_EXT:
3205                 /* FIXME:  assert scan_begin_arg != 0, ret failure otherwise */
3206                 devpriv->ao_cmd2  |= NISTC_AO_CMD2_BC_GATE_ENA;
3207                 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3208                                         CR_CHAN(cmd->scan_begin_arg));
3209                 if (cmd->scan_begin_arg & CR_INVERT)
3210                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3211                 break;
3212         default:
3213                 BUG();
3214                 break;
3215         }
3216
3217         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3218         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3219         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3220                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3221         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3222
3223         /* Configure DAQ-STC for Timed update mode */
3224         devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3225                             NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3226         /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3227         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3228
3229         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3230 }
3231
3232 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3233                                    struct comedi_subdevice *s)
3234 {
3235         struct ni_private *devpriv = dev->private;
3236         const struct comedi_cmd *cmd = &s->async->cmd;
3237         unsigned bits = 0;
3238
3239         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3240
3241         if (devpriv->is_6xxx) {
3242                 unsigned int i;
3243
3244                 bits = 0;
3245                 for (i = 0; i < cmd->chanlist_len; ++i) {
3246                         int chan = CR_CHAN(cmd->chanlist[i]);
3247
3248                         bits |= 1 << chan;
3249                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3250                 }
3251                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3252         }
3253
3254         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3255
3256         if (cmd->scan_end_arg > 1) {
3257                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3258                 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3259                                  | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3260
3261         } else {
3262                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3263                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3264                 if (devpriv->is_m_series | devpriv->is_6xxx)
3265                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3266                 else
3267                         bits |= NISTC_AO_OUT_CTRL_CHANS(
3268                                         CR_CHAN(cmd->chanlist[0]));
3269         }
3270
3271         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3272         ni_stc_writew(dev, bits,              NISTC_AO_OUT_CTRL_REG);
3273
3274         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3275 }
3276
3277 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3278                                           const struct comedi_cmd *cmd)
3279 {
3280         struct ni_private *devpriv = dev->private;
3281
3282         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3283
3284         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3285         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3286
3287         /*
3288          * Since we are not supporting waveform staging, we ignore these errors:
3289          * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3290          * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3291          */
3292
3293         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3294 }
3295
3296 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3297 {
3298         struct ni_private *devpriv = dev->private;
3299
3300         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3301
3302         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3303 #ifdef PCIDMA
3304         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3305 #else
3306         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3307 #endif
3308         /* NOTE:  this is where use_onboard_memory=True would be implemented */
3309         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3310         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3311
3312         /* enable sending of ao fifo requests (dma request) */
3313         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3314
3315         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3316
3317         /* we are not supporting boards with virtual fifos */
3318 }
3319
3320 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3321                                      struct comedi_subdevice *s)
3322 {
3323         if (s->async->cmd.stop_src == TRIG_COUNT)
3324                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3325                             NISTC_INTB_ENA_AO_BC_TC, 1);
3326
3327         s->async->inttrig = ni_ao_inttrig;
3328 }
3329
3330 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3331 {
3332         struct ni_private *devpriv = dev->private;
3333         const struct comedi_cmd *cmd = &s->async->cmd;
3334
3335         if (dev->irq == 0) {
3336                 dev_err(dev->class_dev, "cannot run command without an irq");
3337                 return -EIO;
3338         }
3339
3340         /* ni_ao_reset should have already been done */
3341         ni_ao_cmd_personalize(dev, cmd);
3342         /* clearing fifo and preload happens elsewhere */
3343
3344         ni_ao_cmd_set_trigger(dev, cmd);
3345         ni_ao_cmd_set_counters(dev, cmd);
3346         ni_ao_cmd_set_update(dev, cmd);
3347         ni_ao_cmd_set_channels(dev, s);
3348         ni_ao_cmd_set_stop_conditions(dev, cmd);
3349         ni_ao_cmd_set_fifo_mode(dev);
3350         ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3351         ni_ao_cmd_set_interrupts(dev, s);
3352
3353         /*
3354          * arm(ing) and star(ting) happen in ni_ao_inttrig, which _must_ be
3355          * called for ao commands since 1) TRIG_NOW is not supported and 2) DMA
3356          * must be setup and initially written to before arm/start happen.
3357          */
3358         return 0;
3359 }
3360
3361 /* end ni_ao_cmd */
3362
3363 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3364                          struct comedi_cmd *cmd)
3365 {
3366         const struct ni_board_struct *board = dev->board_ptr;
3367         struct ni_private *devpriv = dev->private;
3368         int err = 0;
3369         unsigned int tmp;
3370
3371         /* Step 1 : check if triggers are trivially valid */
3372
3373         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3374         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3375                                         TRIG_TIMER | TRIG_EXT);
3376         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3377         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3378         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3379
3380         if (err)
3381                 return 1;
3382
3383         /* Step 2a : make sure trigger sources are unique */
3384
3385         err |= comedi_check_trigger_is_unique(cmd->start_src);
3386         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3387         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3388
3389         /* Step 2b : and mutually compatible */
3390
3391         if (err)
3392                 return 2;
3393
3394         /* Step 3: check if arguments are trivially valid */
3395
3396         switch (cmd->start_src) {
3397         case TRIG_INT:
3398                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3399                 break;
3400         case TRIG_EXT:
3401                 tmp = CR_CHAN(cmd->start_arg);
3402
3403                 if (tmp > 18)
3404                         tmp = 18;
3405                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3406                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3407                 break;
3408         }
3409
3410         if (cmd->scan_begin_src == TRIG_TIMER) {
3411                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3412                                                     board->ao_speed);
3413                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3414                                                     devpriv->clock_ns *
3415                                                     0xffffff);
3416         }
3417
3418         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3419         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3420                                            cmd->chanlist_len);
3421         err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3422
3423         if (err)
3424                 return 3;
3425
3426         /* step 4: fix up any arguments */
3427         if (cmd->scan_begin_src == TRIG_TIMER) {
3428                 tmp = cmd->scan_begin_arg;
3429                 cmd->scan_begin_arg =
3430                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3431                                                        cmd->scan_begin_arg,
3432                                                        cmd->flags));
3433                 if (tmp != cmd->scan_begin_arg)
3434                         err++;
3435         }
3436         if (err)
3437                 return 4;
3438
3439         return 0;
3440 }
3441
3442 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3443 {
3444         /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3445
3446         /*
3447          * In the following, the "--sync" comments are meant to denote
3448          * asynchronous boundaries for setting the registers as described in the
3449          * DAQ-STC mostly in the order also described in the DAQ-STC.
3450          */
3451
3452         struct ni_private *devpriv = dev->private;
3453
3454         ni_release_ao_mite_channel(dev);
3455
3456         /* --sync (reset AO) */
3457         if (devpriv->is_m_series)
3458                 /* following example in mhddk for m-series */
3459                 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3460
3461         /*--sync (start config) */
3462         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3463
3464         /*--sync (Disarm) */
3465         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3466
3467         /*
3468          * --sync
3469          * (clear bunch of registers--mseries mhddk examples do not include
3470          * this)
3471          */
3472         devpriv->ao_cmd1  = 0;
3473         devpriv->ao_cmd2  = 0;
3474         devpriv->ao_mode1 = 0;
3475         devpriv->ao_mode2 = 0;
3476         if (devpriv->is_m_series)
3477                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3478         else
3479                 devpriv->ao_mode3 = 0;
3480         devpriv->ao_trigger_select = 0;
3481
3482         ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3483         ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3484         ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3485         ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3486         ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3487         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3488         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3489         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3490         ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3491
3492         /*--sync (disable interrupts) */
3493         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3494
3495         /*--sync (ack) */
3496         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3497         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3498
3499         /*--not in DAQ-STC.  which doc? */
3500         if (devpriv->is_6xxx) {
3501                 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3502                                NI671X_AO_IMMEDIATE_REG);
3503                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3504                                NI611X_AO_MISC_REG);
3505         }
3506         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3507         /*--end */
3508
3509         return 0;
3510 }
3511
3512 /* digital io */
3513
3514 static int ni_dio_insn_config(struct comedi_device *dev,
3515                               struct comedi_subdevice *s,
3516                               struct comedi_insn *insn,
3517                               unsigned int *data)
3518 {
3519         struct ni_private *devpriv = dev->private;
3520         int ret;
3521
3522         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3523         if (ret)
3524                 return ret;
3525
3526         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3527         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3528         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3529
3530         return insn->n;
3531 }
3532
3533 static int ni_dio_insn_bits(struct comedi_device *dev,
3534                             struct comedi_subdevice *s,
3535                             struct comedi_insn *insn,
3536                             unsigned int *data)
3537 {
3538         struct ni_private *devpriv = dev->private;
3539
3540         /* Make sure we're not using the serial part of the dio */
3541         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3542             devpriv->serial_interval_ns)
3543                 return -EBUSY;
3544
3545         if (comedi_dio_update_state(s, data)) {
3546                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3547                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3548                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3549         }
3550
3551         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3552
3553         return insn->n;
3554 }
3555
3556 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3557                                        struct comedi_subdevice *s,
3558                                        struct comedi_insn *insn,
3559                                        unsigned int *data)
3560 {
3561         int ret;
3562
3563         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3564         if (ret)
3565                 return ret;
3566
3567         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3568
3569         return insn->n;
3570 }
3571
3572 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3573                                      struct comedi_subdevice *s,
3574                                      struct comedi_insn *insn,
3575                                      unsigned int *data)
3576 {
3577         if (comedi_dio_update_state(s, data))
3578                 ni_writel(dev, s->state, NI_M_DIO_REG);
3579
3580         data[1] = ni_readl(dev, NI_M_DIO_REG);
3581
3582         return insn->n;
3583 }
3584
3585 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3586                                   struct comedi_subdevice *s,
3587                                   struct comedi_cmd *cmd)
3588 {
3589         int i;
3590
3591         for (i = 0; i < cmd->chanlist_len; ++i) {
3592                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3593
3594                 if (chan != i)
3595                         return -EINVAL;
3596         }
3597
3598         return 0;
3599 }
3600
3601 static int ni_cdio_cmdtest(struct comedi_device *dev,
3602                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3603 {
3604         int err = 0;
3605         int tmp;
3606
3607         /* Step 1 : check if triggers are trivially valid */
3608
3609         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3610         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3611         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3612         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3613         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3614
3615         if (err)
3616                 return 1;
3617
3618         /* Step 2a : make sure trigger sources are unique */
3619         /* Step 2b : and mutually compatible */
3620
3621         /* Step 3: check if arguments are trivially valid */
3622
3623         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3624
3625         tmp = cmd->scan_begin_arg;
3626         tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3627         if (tmp != cmd->scan_begin_arg)
3628                 err |= -EINVAL;
3629
3630         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3631         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3632                                            cmd->chanlist_len);
3633         err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3634                                             s->async->prealloc_bufsz /
3635                                             comedi_bytes_per_scan(s));
3636
3637         if (err)
3638                 return 3;
3639
3640         /* Step 4: fix up any arguments */
3641
3642         /* Step 5: check channel list if it exists */
3643
3644         if (cmd->chanlist && cmd->chanlist_len > 0)
3645                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3646
3647         if (err)
3648                 return 5;
3649
3650         return 0;
3651 }
3652
3653 static int ni_cdo_inttrig(struct comedi_device *dev,
3654                           struct comedi_subdevice *s,
3655                           unsigned int trig_num)
3656 {
3657         struct comedi_cmd *cmd = &s->async->cmd;
3658         const unsigned timeout = 1000;
3659         int retval = 0;
3660         unsigned i;
3661 #ifdef PCIDMA
3662         struct ni_private *devpriv = dev->private;
3663         unsigned long flags;
3664 #endif
3665
3666         if (trig_num != cmd->start_arg)
3667                 return -EINVAL;
3668
3669         s->async->inttrig = NULL;
3670
3671         /* read alloc the entire buffer */
3672         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3673
3674 #ifdef PCIDMA
3675         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3676         if (devpriv->cdo_mite_chan) {
3677                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3678                 mite_dma_arm(devpriv->cdo_mite_chan);
3679         } else {
3680                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3681                 retval = -EIO;
3682         }
3683         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3684         if (retval < 0)
3685                 return retval;
3686 #endif
3687         /*
3688          * XXX not sure what interrupt C group does
3689          * wait for dma to fill output fifo
3690          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3691          */
3692         for (i = 0; i < timeout; ++i) {
3693                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3694                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3695                         break;
3696                 udelay(10);
3697         }
3698         if (i == timeout) {
3699                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3700                 s->cancel(dev, s);
3701                 return -EIO;
3702         }
3703         ni_writel(dev, NI_M_CDO_CMD_ARM |
3704                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3705                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3706                   NI_M_CDIO_CMD_REG);
3707         return retval;
3708 }
3709
3710 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3711 {
3712         struct ni_private *devpriv = dev->private;
3713         const struct comedi_cmd *cmd = &s->async->cmd;
3714         unsigned cdo_mode_bits;
3715         int retval;
3716
3717         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3718         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3719                         NI_M_CDO_MODE_HALT_ON_ERROR |
3720                         NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3721         if (cmd->scan_begin_arg & CR_INVERT)
3722                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3723         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3724         if (s->io_bits) {
3725                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3726                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3727                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3728         } else {
3729                 dev_err(dev->class_dev,
3730                         "attempted to run digital output command with no lines configured as outputs\n");
3731                 return -EIO;
3732         }
3733         retval = ni_request_cdo_mite_channel(dev);
3734         if (retval < 0)
3735                 return retval;
3736
3737         ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3738                                  s->async->prealloc_bufsz /
3739                                  comedi_bytes_per_scan(s));
3740
3741         s->async->inttrig = ni_cdo_inttrig;
3742
3743         return 0;
3744 }
3745
3746 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3747 {
3748         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3749                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3750                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3751                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3752                   NI_M_CDIO_CMD_REG);
3753         /*
3754          * XXX not sure what interrupt C group does
3755          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3756          */
3757         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3758         ni_release_cdo_mite_channel(dev);
3759         return 0;
3760 }
3761
3762 static void handle_cdio_interrupt(struct comedi_device *dev)
3763 {
3764         struct ni_private *devpriv = dev->private;
3765         unsigned cdio_status;
3766         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3767 #ifdef PCIDMA
3768         unsigned long flags;
3769 #endif
3770
3771         if (!devpriv->is_m_series)
3772                 return;
3773 #ifdef PCIDMA
3774         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3775         if (devpriv->cdo_mite_chan) {
3776                 unsigned cdo_mite_status =
3777                     mite_get_status(devpriv->cdo_mite_chan);
3778                 if (cdo_mite_status & CHSR_LINKC) {
3779                         writel(CHOR_CLRLC,
3780                                devpriv->mite->mite_io_addr +
3781                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3782                 }
3783                 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3784         }
3785         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3786 #endif
3787
3788         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3789         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3790                 /* XXX just guessing this is needed and does something useful */
3791                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3792                           NI_M_CDIO_CMD_REG);
3793                 s->async->events |= COMEDI_CB_OVERFLOW;
3794         }
3795         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3796                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3797                           NI_M_CDIO_CMD_REG);
3798                 /* s->async->events |= COMEDI_CB_EOA; */
3799         }
3800         comedi_handle_events(dev, s);
3801 }
3802
3803 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3804                                    struct comedi_subdevice *s,
3805                                    unsigned char data_out,
3806                                    unsigned char *data_in)
3807 {
3808         struct ni_private *devpriv = dev->private;
3809         unsigned int status1;
3810         int err = 0, count = 20;
3811
3812         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3813         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3814         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3815
3816         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3817         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3818                 err = -EBUSY;
3819                 goto Error;
3820         }
3821
3822         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3823         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3824         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3825
3826         /* Wait until STC says we're done, but don't loop infinitely. */
3827         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3828                NISTC_STATUS1_SERIO_IN_PROG) {
3829                 /* Delay one bit per loop */
3830                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3831                 if (--count < 0) {
3832                         dev_err(dev->class_dev,
3833                                 "SPI serial I/O didn't finish in time!\n");
3834                         err = -ETIME;
3835                         goto Error;
3836                 }
3837         }
3838
3839         /*
3840          * Delay for last bit. This delay is absolutely necessary, because
3841          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3842          */
3843         udelay((devpriv->serial_interval_ns + 999) / 1000);
3844
3845         if (data_in)
3846                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3847
3848 Error:
3849         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3850
3851         return err;
3852 }
3853
3854 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3855                                    struct comedi_subdevice *s,
3856                                    unsigned char data_out,
3857                                    unsigned char *data_in)
3858 {
3859         struct ni_private *devpriv = dev->private;
3860         unsigned char mask, input = 0;
3861
3862         /* Wait for one bit before transfer */
3863         udelay((devpriv->serial_interval_ns + 999) / 1000);
3864
3865         for (mask = 0x80; mask; mask >>= 1) {
3866                 /* Output current bit; note that we cannot touch s->state
3867                    because it is a per-subdevice field, and serial is
3868                    a separate subdevice from DIO. */
3869                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3870                 if (data_out & mask)
3871                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3872                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3873
3874                 /* Assert SDCLK (active low, inverted), wait for half of
3875                    the delay, deassert SDCLK, and wait for the other half. */
3876                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3877                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3878
3879                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3880
3881                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3882                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3883
3884                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3885
3886                 /* Input current bit */
3887                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3888                         input |= mask;
3889         }
3890
3891         if (data_in)
3892                 *data_in = input;
3893
3894         return 0;
3895 }
3896
3897 static int ni_serial_insn_config(struct comedi_device *dev,
3898                                  struct comedi_subdevice *s,
3899                                  struct comedi_insn *insn,
3900                                  unsigned int *data)
3901 {
3902         struct ni_private *devpriv = dev->private;
3903         unsigned clk_fout = devpriv->clock_and_fout;
3904         int err = insn->n;
3905         unsigned char byte_out, byte_in = 0;
3906
3907         if (insn->n != 2)
3908                 return -EINVAL;
3909
3910         switch (data[0]) {
3911         case INSN_CONFIG_SERIAL_CLOCK:
3912                 devpriv->serial_hw_mode = 1;
3913                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3914
3915                 if (data[1] == SERIAL_DISABLED) {
3916                         devpriv->serial_hw_mode = 0;
3917                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3918                                                   NISTC_DIO_SDCLK);
3919                         data[1] = SERIAL_DISABLED;
3920                         devpriv->serial_interval_ns = data[1];
3921                 } else if (data[1] <= SERIAL_600NS) {
3922                         /* Warning: this clock speed is too fast to reliably
3923                            control SCXI. */
3924                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3925                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3926                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3927                         data[1] = SERIAL_600NS;
3928                         devpriv->serial_interval_ns = data[1];
3929                 } else if (data[1] <= SERIAL_1_2US) {
3930                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3931                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3932                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3933                         data[1] = SERIAL_1_2US;
3934                         devpriv->serial_interval_ns = data[1];
3935                 } else if (data[1] <= SERIAL_10US) {
3936                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3937                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3938                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3939                         /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3940                            600ns/1.2us. If you turn divide_by_2 off with the
3941                            slow clock, you will still get 10us, except then
3942                            all your delays are wrong. */
3943                         data[1] = SERIAL_10US;
3944                         devpriv->serial_interval_ns = data[1];
3945                 } else {
3946                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3947                                                   NISTC_DIO_SDCLK);
3948                         devpriv->serial_hw_mode = 0;
3949                         data[1] = (data[1] / 1000) * 1000;
3950                         devpriv->serial_interval_ns = data[1];
3951                 }
3952                 devpriv->clock_and_fout = clk_fout;
3953
3954                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3955                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3956                 return 1;
3957
3958         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3959
3960                 if (devpriv->serial_interval_ns == 0)
3961                         return -EINVAL;
3962
3963                 byte_out = data[1] & 0xFF;
3964
3965                 if (devpriv->serial_hw_mode) {
3966                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3967                                                       &byte_in);
3968                 } else if (devpriv->serial_interval_ns > 0) {
3969                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3970                                                       &byte_in);
3971                 } else {
3972                         dev_err(dev->class_dev, "serial disabled!\n");
3973                         return -EINVAL;
3974                 }
3975                 if (err < 0)
3976                         return err;
3977                 data[1] = byte_in & 0xFF;
3978                 return insn->n;
3979
3980                 break;
3981         default:
3982                 return -EINVAL;
3983         }
3984 }
3985
3986 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3987 {
3988         int i;
3989
3990         for (i = 0; i < s->n_chan; i++) {
3991                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3992                                NI67XX_AO_CFG2_REG);
3993         }
3994         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3995 }
3996
3997 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3998         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3999         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
4000         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
4001         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
4002         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
4003         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
4004         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
4005         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
4006         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
4007         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
4008         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
4009         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
4010         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
4011         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
4012         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
4013         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
4014         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
4015         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
4016         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
4017         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
4018         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
4019         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
4020         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
4021         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
4022         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
4023         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
4024         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
4025         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
4026         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
4027         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
4028         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
4029         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
4030         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
4031         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
4032         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
4033         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
4034 };
4035
4036 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
4037                                             enum ni_gpct_register reg)
4038 {
4039         const struct mio_regmap *regmap;
4040
4041         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
4042                 regmap = &ni_gpct_to_stc_regmap[reg];
4043         } else {
4044                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
4045                          __func__, reg);
4046                 return 0;
4047         }
4048
4049         return regmap->mio_reg;
4050 }
4051
4052 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4053                                    enum ni_gpct_register reg)
4054 {
4055         struct comedi_device *dev = counter->counter_dev->dev;
4056         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4057         static const unsigned gpct_interrupt_a_enable_mask =
4058             NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
4059         static const unsigned gpct_interrupt_b_enable_mask =
4060             NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
4061
4062         if (stc_register == 0)
4063                 return;
4064
4065         switch (reg) {
4066                 /* m-series only registers */
4067         case NITIO_G0_CNT_MODE:
4068         case NITIO_G1_CNT_MODE:
4069         case NITIO_G0_GATE2:
4070         case NITIO_G1_GATE2:
4071         case NITIO_G0_DMA_CFG:
4072         case NITIO_G1_DMA_CFG:
4073         case NITIO_G0_ABZ:
4074         case NITIO_G1_ABZ:
4075                 ni_writew(dev, bits, stc_register);
4076                 break;
4077
4078                 /* 32 bit registers */
4079         case NITIO_G0_LOADA:
4080         case NITIO_G1_LOADA:
4081         case NITIO_G0_LOADB:
4082         case NITIO_G1_LOADB:
4083                 ni_stc_writel(dev, bits, stc_register);
4084                 break;
4085
4086                 /* 16 bit registers */
4087         case NITIO_G0_INT_ENA:
4088                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4089                 ni_set_bitfield(dev, stc_register,
4090                                 gpct_interrupt_a_enable_mask, bits);
4091                 break;
4092         case NITIO_G1_INT_ENA:
4093                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4094                 ni_set_bitfield(dev, stc_register,
4095                                 gpct_interrupt_b_enable_mask, bits);
4096                 break;
4097         case NITIO_G01_RESET:
4098                 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
4099                 /* fall-through */
4100         default:
4101                 ni_stc_writew(dev, bits, stc_register);
4102         }
4103 }
4104
4105 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4106                                       enum ni_gpct_register reg)
4107 {
4108         struct comedi_device *dev = counter->counter_dev->dev;
4109         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4110
4111         if (stc_register == 0)
4112                 return 0;
4113
4114         switch (reg) {
4115                 /* m-series only registers */
4116         case NITIO_G0_DMA_STATUS:
4117         case NITIO_G1_DMA_STATUS:
4118                 return ni_readw(dev, stc_register);
4119
4120                 /* 32 bit registers */
4121         case NITIO_G0_HW_SAVE:
4122         case NITIO_G1_HW_SAVE:
4123         case NITIO_G0_SW_SAVE:
4124         case NITIO_G1_SW_SAVE:
4125                 return ni_stc_readl(dev, stc_register);
4126
4127                 /* 16 bit registers */
4128         default:
4129                 return ni_stc_readw(dev, stc_register);
4130         }
4131 }
4132
4133 static int ni_freq_out_insn_read(struct comedi_device *dev,
4134                                  struct comedi_subdevice *s,
4135                                  struct comedi_insn *insn,
4136                                  unsigned int *data)
4137 {
4138         struct ni_private *devpriv = dev->private;
4139         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4140         int i;
4141
4142         for (i = 0; i < insn->n; i++)
4143                 data[i] = val;
4144
4145         return insn->n;
4146 }
4147
4148 static int ni_freq_out_insn_write(struct comedi_device *dev,
4149                                   struct comedi_subdevice *s,
4150                                   struct comedi_insn *insn,
4151                                   unsigned int *data)
4152 {
4153         struct ni_private *devpriv = dev->private;
4154
4155         if (insn->n) {
4156                 unsigned int val = data[insn->n - 1];
4157
4158                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4159                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4160                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4161
4162                 /* use the last data value to set the fout divider */
4163                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4164
4165                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4166                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4167         }
4168         return insn->n;
4169 }
4170
4171 static int ni_freq_out_insn_config(struct comedi_device *dev,
4172                                    struct comedi_subdevice *s,
4173                                    struct comedi_insn *insn,
4174                                    unsigned int *data)
4175 {
4176         struct ni_private *devpriv = dev->private;
4177
4178         switch (data[0]) {
4179         case INSN_CONFIG_SET_CLOCK_SRC:
4180                 switch (data[1]) {
4181                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4182                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4183                         break;
4184                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4185                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4186                         break;
4187                 default:
4188                         return -EINVAL;
4189                 }
4190                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4191                 break;
4192         case INSN_CONFIG_GET_CLOCK_SRC:
4193                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4194                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4195                         data[2] = TIMEBASE_2_NS;
4196                 } else {
4197                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4198                         data[2] = TIMEBASE_1_NS * 2;
4199                 }
4200                 break;
4201         default:
4202                 return -EINVAL;
4203         }
4204         return insn->n;
4205 }
4206
4207 static int ni_8255_callback(struct comedi_device *dev,
4208                             int dir, int port, int data, unsigned long iobase)
4209 {
4210         if (dir) {
4211                 ni_writeb(dev, data, iobase + 2 * port);
4212                 return 0;
4213         }
4214
4215         return ni_readb(dev, iobase + 2 * port);
4216 }
4217
4218 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4219 {
4220         struct ni_private *devpriv = dev->private;
4221
4222         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4223         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4224         return 3;
4225 }
4226
4227 static int ni_m_series_pwm_config(struct comedi_device *dev,
4228                                   struct comedi_subdevice *s,
4229                                   struct comedi_insn *insn,
4230                                   unsigned int *data)
4231 {
4232         struct ni_private *devpriv = dev->private;
4233         unsigned up_count, down_count;
4234
4235         switch (data[0]) {
4236         case INSN_CONFIG_PWM_OUTPUT:
4237                 switch (data[1]) {
4238                 case CMDF_ROUND_NEAREST:
4239                         up_count =
4240                             (data[2] +
4241                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4242                         break;
4243                 case CMDF_ROUND_DOWN:
4244                         up_count = data[2] / devpriv->clock_ns;
4245                         break;
4246                 case CMDF_ROUND_UP:
4247                         up_count =
4248                             (data[2] + devpriv->clock_ns -
4249                              1) / devpriv->clock_ns;
4250                         break;
4251                 default:
4252                         return -EINVAL;
4253                 }
4254                 switch (data[3]) {
4255                 case CMDF_ROUND_NEAREST:
4256                         down_count =
4257                             (data[4] +
4258                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4259                         break;
4260                 case CMDF_ROUND_DOWN:
4261                         down_count = data[4] / devpriv->clock_ns;
4262                         break;
4263                 case CMDF_ROUND_UP:
4264                         down_count =
4265                             (data[4] + devpriv->clock_ns -
4266                              1) / devpriv->clock_ns;
4267                         break;
4268                 default:
4269                         return -EINVAL;
4270                 }
4271                 if (up_count * devpriv->clock_ns != data[2] ||
4272                     down_count * devpriv->clock_ns != data[4]) {
4273                         data[2] = up_count * devpriv->clock_ns;
4274                         data[4] = down_count * devpriv->clock_ns;
4275                         return -EAGAIN;
4276                 }
4277                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4278                                NI_M_CAL_PWM_LOW_TIME(down_count),
4279                           NI_M_CAL_PWM_REG);
4280                 devpriv->pwm_up_count = up_count;
4281                 devpriv->pwm_down_count = down_count;
4282                 return 5;
4283         case INSN_CONFIG_GET_PWM_OUTPUT:
4284                 return ni_get_pwm_config(dev, data);
4285         default:
4286                 return -EINVAL;
4287         }
4288         return 0;
4289 }
4290
4291 static int ni_6143_pwm_config(struct comedi_device *dev,
4292                               struct comedi_subdevice *s,
4293                               struct comedi_insn *insn,
4294                               unsigned int *data)
4295 {
4296         struct ni_private *devpriv = dev->private;
4297         unsigned up_count, down_count;
4298
4299         switch (data[0]) {
4300         case INSN_CONFIG_PWM_OUTPUT:
4301                 switch (data[1]) {
4302                 case CMDF_ROUND_NEAREST:
4303                         up_count =
4304                             (data[2] +
4305                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4306                         break;
4307                 case CMDF_ROUND_DOWN:
4308                         up_count = data[2] / devpriv->clock_ns;
4309                         break;
4310                 case CMDF_ROUND_UP:
4311                         up_count =
4312                             (data[2] + devpriv->clock_ns -
4313                              1) / devpriv->clock_ns;
4314                         break;
4315                 default:
4316                         return -EINVAL;
4317                 }
4318                 switch (data[3]) {
4319                 case CMDF_ROUND_NEAREST:
4320                         down_count =
4321                             (data[4] +
4322                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4323                         break;
4324                 case CMDF_ROUND_DOWN:
4325                         down_count = data[4] / devpriv->clock_ns;
4326                         break;
4327                 case CMDF_ROUND_UP:
4328                         down_count =
4329                             (data[4] + devpriv->clock_ns -
4330                              1) / devpriv->clock_ns;
4331                         break;
4332                 default:
4333                         return -EINVAL;
4334                 }
4335                 if (up_count * devpriv->clock_ns != data[2] ||
4336                     down_count * devpriv->clock_ns != data[4]) {
4337                         data[2] = up_count * devpriv->clock_ns;
4338                         data[4] = down_count * devpriv->clock_ns;
4339                         return -EAGAIN;
4340                 }
4341                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4342                 devpriv->pwm_up_count = up_count;
4343                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4344                 devpriv->pwm_down_count = down_count;
4345                 return 5;
4346         case INSN_CONFIG_GET_PWM_OUTPUT:
4347                 return ni_get_pwm_config(dev, data);
4348         default:
4349                 return -EINVAL;
4350         }
4351         return 0;
4352 }
4353
4354 static int pack_mb88341(int addr, int val, int *bitstring)
4355 {
4356         /*
4357            Fujitsu MB 88341
4358            Note that address bits are reversed.  Thanks to
4359            Ingo Keen for noticing this.
4360
4361            Note also that the 88341 expects address values from
4362            1-12, whereas we use channel numbers 0-11.  The NI
4363            docs use 1-12, also, so be careful here.
4364          */
4365         addr++;
4366         *bitstring = ((addr & 0x1) << 11) |
4367             ((addr & 0x2) << 9) |
4368             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4369         return 12;
4370 }
4371
4372 static int pack_dac8800(int addr, int val, int *bitstring)
4373 {
4374         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4375         return 11;
4376 }
4377
4378 static int pack_dac8043(int addr, int val, int *bitstring)
4379 {
4380         *bitstring = val & 0xfff;
4381         return 12;
4382 }
4383
4384 static int pack_ad8522(int addr, int val, int *bitstring)
4385 {
4386         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4387         return 16;
4388 }
4389
4390 static int pack_ad8804(int addr, int val, int *bitstring)
4391 {
4392         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4393         return 12;
4394 }
4395
4396 static int pack_ad8842(int addr, int val, int *bitstring)
4397 {
4398         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4399         return 12;
4400 }
4401
4402 struct caldac_struct {
4403         int n_chans;
4404         int n_bits;
4405         int (*packbits)(int, int, int *);
4406 };
4407
4408 static struct caldac_struct caldacs[] = {
4409         [mb88341] = {12, 8, pack_mb88341},
4410         [dac8800] = {8, 8, pack_dac8800},
4411         [dac8043] = {1, 12, pack_dac8043},
4412         [ad8522] = {2, 12, pack_ad8522},
4413         [ad8804] = {12, 8, pack_ad8804},
4414         [ad8842] = {8, 8, pack_ad8842},
4415         [ad8804_debug] = {16, 8, pack_ad8804},
4416 };
4417
4418 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4419 {
4420         const struct ni_board_struct *board = dev->board_ptr;
4421         struct ni_private *devpriv = dev->private;
4422         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4423         unsigned int cmd;
4424         int i;
4425         int type;
4426
4427         if (devpriv->caldacs[addr] == val)
4428                 return;
4429         devpriv->caldacs[addr] = val;
4430
4431         for (i = 0; i < 3; i++) {
4432                 type = board->caldac[i];
4433                 if (type == caldac_none)
4434                         break;
4435                 if (addr < caldacs[type].n_chans) {
4436                         bits = caldacs[type].packbits(addr, val, &bitstring);
4437                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4438                         break;
4439                 }
4440                 addr -= caldacs[type].n_chans;
4441         }
4442
4443         /* bits will be 0 if there is no caldac for the given addr */
4444         if (bits == 0)
4445                 return;
4446
4447         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4448                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4449                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4450                 udelay(1);
4451                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4452                 udelay(1);
4453         }
4454         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4455         udelay(1);
4456         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4457 }
4458
4459 static int ni_calib_insn_write(struct comedi_device *dev,
4460                                struct comedi_subdevice *s,
4461                                struct comedi_insn *insn,
4462                                unsigned int *data)
4463 {
4464         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4465
4466         return 1;
4467 }
4468
4469 static int ni_calib_insn_read(struct comedi_device *dev,
4470                               struct comedi_subdevice *s,
4471                               struct comedi_insn *insn,
4472                               unsigned int *data)
4473 {
4474         struct ni_private *devpriv = dev->private;
4475
4476         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4477
4478         return 1;
4479 }
4480
4481 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4482 {
4483         const struct ni_board_struct *board = dev->board_ptr;
4484         struct ni_private *devpriv = dev->private;
4485         int i, j;
4486         int n_dacs;
4487         int n_chans = 0;
4488         int n_bits;
4489         int diffbits = 0;
4490         int type;
4491         int chan;
4492
4493         type = board->caldac[0];
4494         if (type == caldac_none)
4495                 return;
4496         n_bits = caldacs[type].n_bits;
4497         for (i = 0; i < 3; i++) {
4498                 type = board->caldac[i];
4499                 if (type == caldac_none)
4500                         break;
4501                 if (caldacs[type].n_bits != n_bits)
4502                         diffbits = 1;
4503                 n_chans += caldacs[type].n_chans;
4504         }
4505         n_dacs = i;
4506         s->n_chan = n_chans;
4507
4508         if (diffbits) {
4509                 unsigned int *maxdata_list;
4510
4511                 if (n_chans > MAX_N_CALDACS)
4512                         dev_err(dev->class_dev,
4513                                 "BUG! MAX_N_CALDACS too small\n");
4514                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4515                 chan = 0;
4516                 for (i = 0; i < n_dacs; i++) {
4517                         type = board->caldac[i];
4518                         for (j = 0; j < caldacs[type].n_chans; j++) {
4519                                 maxdata_list[chan] =
4520                                     (1 << caldacs[type].n_bits) - 1;
4521                                 chan++;
4522                         }
4523                 }
4524
4525                 for (chan = 0; chan < s->n_chan; chan++)
4526                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4527         } else {
4528                 type = board->caldac[0];
4529                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4530
4531                 for (chan = 0; chan < s->n_chan; chan++)
4532                         ni_write_caldac(dev, i, s->maxdata / 2);
4533         }
4534 }
4535
4536 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4537 {
4538         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4539         int bit;
4540         int bitstring;
4541
4542         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4543         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4544         for (bit = 0x8000; bit; bit >>= 1) {
4545                 if (bit & bitstring)
4546                         cmd |= NI_E_SERIAL_CMD_SDATA;
4547                 else
4548                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4549
4550                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4551                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4552         }
4553         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4554         bitstring = 0;
4555         for (bit = 0x80; bit; bit >>= 1) {
4556                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4557                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4558                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4559                         bitstring |= bit;
4560         }
4561         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4562
4563         return bitstring;
4564 }
4565
4566 static int ni_eeprom_insn_read(struct comedi_device *dev,
4567                                struct comedi_subdevice *s,
4568                                struct comedi_insn *insn,
4569                                unsigned int *data)
4570 {
4571         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4572
4573         return 1;
4574 }
4575
4576 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4577                                         struct comedi_subdevice *s,
4578                                         struct comedi_insn *insn,
4579                                         unsigned int *data)
4580 {
4581         struct ni_private *devpriv = dev->private;
4582
4583         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4584
4585         return 1;
4586 }
4587
4588 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4589                                        unsigned chan)
4590 {
4591         /*  pre-m-series boards have fixed signals on pfi pins */
4592         switch (chan) {
4593         case 0:
4594                 return NI_PFI_OUTPUT_AI_START1;
4595         case 1:
4596                 return NI_PFI_OUTPUT_AI_START2;
4597         case 2:
4598                 return NI_PFI_OUTPUT_AI_CONVERT;
4599         case 3:
4600                 return NI_PFI_OUTPUT_G_SRC1;
4601         case 4:
4602                 return NI_PFI_OUTPUT_G_GATE1;
4603         case 5:
4604                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4605         case 6:
4606                 return NI_PFI_OUTPUT_AO_START1;
4607         case 7:
4608                 return NI_PFI_OUTPUT_AI_START_PULSE;
4609         case 8:
4610                 return NI_PFI_OUTPUT_G_SRC0;
4611         case 9:
4612                 return NI_PFI_OUTPUT_G_GATE0;
4613         default:
4614                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4615                 break;
4616         }
4617         return 0;
4618 }
4619
4620 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4621                                   unsigned chan, unsigned source)
4622 {
4623         /*  pre-m-series boards have fixed signals on pfi pins */
4624         if (source != ni_old_get_pfi_routing(dev, chan))
4625                 return -EINVAL;
4626         return 2;
4627 }
4628
4629 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4630                                             unsigned chan)
4631 {
4632         struct ni_private *devpriv = dev->private;
4633         const unsigned array_offset = chan / 3;
4634
4635         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4636                                 devpriv->pfi_output_select_reg[array_offset]);
4637 }
4638
4639 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4640                                        unsigned chan, unsigned source)
4641 {
4642         struct ni_private *devpriv = dev->private;
4643         unsigned index = chan / 3;
4644         unsigned short val = devpriv->pfi_output_select_reg[index];
4645
4646         if ((source & 0x1f) != source)
4647                 return -EINVAL;
4648
4649         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4650         val |= NI_M_PFI_OUT_SEL(chan, source);
4651         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4652         devpriv->pfi_output_select_reg[index] = val;
4653
4654         return 2;
4655 }
4656
4657 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4658 {
4659         struct ni_private *devpriv = dev->private;
4660
4661         return (devpriv->is_m_series)
4662                         ? ni_m_series_get_pfi_routing(dev, chan)
4663                         : ni_old_get_pfi_routing(dev, chan);
4664 }
4665
4666 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4667                               unsigned source)
4668 {
4669         struct ni_private *devpriv = dev->private;
4670
4671         return (devpriv->is_m_series)
4672                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4673                         : ni_old_set_pfi_routing(dev, chan, source);
4674 }
4675
4676 static int ni_config_filter(struct comedi_device *dev,
4677                             unsigned pfi_channel,
4678                             enum ni_pfi_filter_select filter)
4679 {
4680         struct ni_private *devpriv = dev->private;
4681         unsigned bits;
4682
4683         if (!devpriv->is_m_series)
4684                 return -ENOTSUPP;
4685
4686         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4687         bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4688         bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4689         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4690         return 0;
4691 }
4692
4693 static int ni_pfi_insn_config(struct comedi_device *dev,
4694                               struct comedi_subdevice *s,
4695                               struct comedi_insn *insn,
4696                               unsigned int *data)
4697 {
4698         struct ni_private *devpriv = dev->private;
4699         unsigned int chan;
4700
4701         if (insn->n < 1)
4702                 return -EINVAL;
4703
4704         chan = CR_CHAN(insn->chanspec);
4705
4706         switch (data[0]) {
4707         case COMEDI_OUTPUT:
4708                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4709                 break;
4710         case COMEDI_INPUT:
4711                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4712                 break;
4713         case INSN_CONFIG_DIO_QUERY:
4714                 data[1] =
4715                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4716                     COMEDI_OUTPUT : COMEDI_INPUT;
4717                 return 0;
4718         case INSN_CONFIG_SET_ROUTING:
4719                 return ni_set_pfi_routing(dev, chan, data[1]);
4720         case INSN_CONFIG_GET_ROUTING:
4721                 data[1] = ni_get_pfi_routing(dev, chan);
4722                 break;
4723         case INSN_CONFIG_FILTER:
4724                 return ni_config_filter(dev, chan, data[1]);
4725         default:
4726                 return -EINVAL;
4727         }
4728         return 0;
4729 }
4730
4731 static int ni_pfi_insn_bits(struct comedi_device *dev,
4732                             struct comedi_subdevice *s,
4733                             struct comedi_insn *insn,
4734                             unsigned int *data)
4735 {
4736         struct ni_private *devpriv = dev->private;
4737
4738         if (!devpriv->is_m_series)
4739                 return -ENOTSUPP;
4740
4741         if (comedi_dio_update_state(s, data))
4742                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4743
4744         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4745
4746         return insn->n;
4747 }
4748
4749 static int cs5529_wait_for_idle(struct comedi_device *dev)
4750 {
4751         unsigned short status;
4752         const int timeout = HZ;
4753         int i;
4754
4755         for (i = 0; i < timeout; i++) {
4756                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4757                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4758                         break;
4759                 set_current_state(TASK_INTERRUPTIBLE);
4760                 if (schedule_timeout(1))
4761                         return -EIO;
4762         }
4763         if (i == timeout) {
4764                 dev_err(dev->class_dev, "timeout\n");
4765                 return -ETIME;
4766         }
4767         return 0;
4768 }
4769
4770 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4771 {
4772         static const int timeout = 100;
4773         int i;
4774
4775         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4776         /* give time for command to start being serially clocked into cs5529.
4777          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4778          * set before we exit this function.
4779          */
4780         for (i = 0; i < timeout; i++) {
4781                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4782                     NI67XX_CAL_STATUS_BUSY)
4783                         break;
4784                 udelay(1);
4785         }
4786         if (i == timeout)
4787                 dev_err(dev->class_dev,
4788                         "possible problem - never saw adc go busy?\n");
4789 }
4790
4791 static int cs5529_do_conversion(struct comedi_device *dev,
4792                                 unsigned short *data)
4793 {
4794         int retval;
4795         unsigned short status;
4796
4797         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4798         retval = cs5529_wait_for_idle(dev);
4799         if (retval) {
4800                 dev_err(dev->class_dev,
4801                         "timeout or signal in cs5529_do_conversion()\n");
4802                 return -ETIME;
4803         }
4804         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4805         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4806                 dev_err(dev->class_dev,
4807                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4808                 return -EIO;
4809         }
4810         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4811                 dev_err(dev->class_dev,
4812                         "cs5529 conversion error, overrange (ignoring)\n");
4813         }
4814         if (data) {
4815                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4816                 /* cs5529 returns 16 bit signed data in bipolar mode */
4817                 *data ^= (1 << 15);
4818         }
4819         return 0;
4820 }
4821
4822 static int cs5529_ai_insn_read(struct comedi_device *dev,
4823                                struct comedi_subdevice *s,
4824                                struct comedi_insn *insn,
4825                                unsigned int *data)
4826 {
4827         int n, retval;
4828         unsigned short sample;
4829         unsigned int channel_select;
4830         const unsigned int INTERNAL_REF = 0x1000;
4831
4832         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4833          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4834          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4835         if (insn->chanspec & CR_ALT_SOURCE)
4836                 channel_select = INTERNAL_REF;
4837         else
4838                 channel_select = CR_CHAN(insn->chanspec);
4839         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4840
4841         for (n = 0; n < insn->n; n++) {
4842                 retval = cs5529_do_conversion(dev, &sample);
4843                 if (retval < 0)
4844                         return retval;
4845                 data[n] = sample;
4846         }
4847         return insn->n;
4848 }
4849
4850 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4851                                 unsigned int reg_select_bits)
4852 {
4853         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4854         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4855         reg_select_bits &= CS5529_CMD_REG_MASK;
4856         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4857         if (cs5529_wait_for_idle(dev))
4858                 dev_err(dev->class_dev,
4859                         "timeout or signal in %s\n", __func__);
4860 }
4861
4862 static int init_cs5529(struct comedi_device *dev)
4863 {
4864         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4865                                    CS5529_CFG_WORD_RATE_2180;
4866
4867 #if 1
4868         /* do self-calibration */
4869         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4870                             CS5529_CFG_REG);
4871         /* need to force a conversion for calibration to run */
4872         cs5529_do_conversion(dev, NULL);
4873 #else
4874         /* force gain calibration to 1 */
4875         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4876         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4877                             CS5529_CFG_REG);
4878         if (cs5529_wait_for_idle(dev))
4879                 dev_err(dev->class_dev,
4880                         "timeout or signal in %s\n", __func__);
4881 #endif
4882         return 0;
4883 }
4884
4885 /*
4886  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4887  * given an arbitrary frequency input clock.
4888  */
4889 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4890                                          unsigned *freq_divider,
4891                                          unsigned *freq_multiplier,
4892                                          unsigned *actual_period_ns)
4893 {
4894         unsigned div;
4895         unsigned best_div = 1;
4896         unsigned mult;
4897         unsigned best_mult = 1;
4898         static const unsigned pico_per_nano = 1000;
4899
4900         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4901         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4902          * 20 MHz for most timing clocks */
4903         static const unsigned target_picosec = 12500;
4904         static const unsigned fudge_factor_80_to_20Mhz = 4;
4905         int best_period_picosec = 0;
4906
4907         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4908                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4909                         unsigned new_period_ps =
4910                             (reference_picosec * div) / mult;
4911                         if (abs(new_period_ps - target_picosec) <
4912                             abs(best_period_picosec - target_picosec)) {
4913                                 best_period_picosec = new_period_ps;
4914                                 best_div = div;
4915                                 best_mult = mult;
4916                         }
4917                 }
4918         }
4919         if (best_period_picosec == 0)
4920                 return -EIO;
4921
4922         *freq_divider = best_div;
4923         *freq_multiplier = best_mult;
4924         *actual_period_ns =
4925             (best_period_picosec * fudge_factor_80_to_20Mhz +
4926              (pico_per_nano / 2)) / pico_per_nano;
4927         return 0;
4928 }
4929
4930 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4931                                            unsigned source, unsigned period_ns)
4932 {
4933         struct ni_private *devpriv = dev->private;
4934         static const unsigned min_period_ns = 50;
4935         static const unsigned max_period_ns = 1000;
4936         static const unsigned timeout = 1000;
4937         unsigned pll_control_bits;
4938         unsigned freq_divider;
4939         unsigned freq_multiplier;
4940         unsigned rtsi;
4941         unsigned i;
4942         int retval;
4943
4944         if (source == NI_MIO_PLL_PXI10_CLOCK)
4945                 period_ns = 100;
4946         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4947         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4948                 dev_err(dev->class_dev,
4949                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4950                         __func__, min_period_ns, max_period_ns);
4951                 return -EINVAL;
4952         }
4953         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4954         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4955                       NISTC_RTSI_TRIG_DIR_REG);
4956         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4957         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4958                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4959         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4960         switch (source) {
4961         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4962                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4963                 break;
4964         case NI_MIO_PLL_PXI10_CLOCK:
4965                 /* pxi clock is 10MHz */
4966                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4967                 break;
4968         default:
4969                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4970                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4971                                 devpriv->clock_and_fout2 |=
4972                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4973                                 break;
4974                         }
4975                 }
4976                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4977                         return -EINVAL;
4978                 break;
4979         }
4980         retval = ni_mseries_get_pll_parameters(period_ns,
4981                                                &freq_divider,
4982                                                &freq_multiplier,
4983                                                &devpriv->clock_ns);
4984         if (retval < 0) {
4985                 dev_err(dev->class_dev,
4986                         "bug, failed to find pll parameters\n");
4987                 return retval;
4988         }
4989
4990         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4991         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4992                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4993
4994         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4995         devpriv->clock_source = source;
4996         /* it seems to typically take a few hundred microseconds for PLL to lock */
4997         for (i = 0; i < timeout; ++i) {
4998                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4999                         break;
5000                 udelay(1);
5001         }
5002         if (i == timeout) {
5003                 dev_err(dev->class_dev,
5004                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
5005                         __func__, source, period_ns);
5006                 return -ETIMEDOUT;
5007         }
5008         return 3;
5009 }
5010
5011 static int ni_set_master_clock(struct comedi_device *dev,
5012                                unsigned source, unsigned period_ns)
5013 {
5014         struct ni_private *devpriv = dev->private;
5015
5016         if (source == NI_MIO_INTERNAL_CLOCK) {
5017                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
5018                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5019                               NISTC_RTSI_TRIG_DIR_REG);
5020                 devpriv->clock_ns = TIMEBASE_1_NS;
5021                 if (devpriv->is_m_series) {
5022                         devpriv->clock_and_fout2 &=
5023                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
5024                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
5025                         ni_writew(dev, devpriv->clock_and_fout2,
5026                                   NI_M_CLK_FOUT2_REG);
5027                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
5028                 }
5029                 devpriv->clock_source = source;
5030         } else {
5031                 if (devpriv->is_m_series) {
5032                         return ni_mseries_set_pll_master_clock(dev, source,
5033                                                                period_ns);
5034                 } else {
5035                         if (source == NI_MIO_RTSI_CLOCK) {
5036                                 devpriv->rtsi_trig_direction_reg |=
5037                                     NISTC_RTSI_TRIG_USE_CLK;
5038                                 ni_stc_writew(dev,
5039                                               devpriv->rtsi_trig_direction_reg,
5040                                               NISTC_RTSI_TRIG_DIR_REG);
5041                                 if (period_ns == 0) {
5042                                         dev_err(dev->class_dev,
5043                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
5044                                         return -EINVAL;
5045                                 }
5046                                 devpriv->clock_ns = period_ns;
5047                                 devpriv->clock_source = source;
5048                         } else {
5049                                 return -EINVAL;
5050                         }
5051                 }
5052         }
5053         return 3;
5054 }
5055
5056 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
5057                                        unsigned chan, unsigned source)
5058 {
5059         struct ni_private *devpriv = dev->private;
5060
5061         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5062                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5063                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5064                                 return 1;
5065
5066                         dev_err(dev->class_dev,
5067                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
5068                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
5069                         return 0;
5070                 }
5071                 return 0;
5072         }
5073         switch (source) {
5074         case NI_RTSI_OUTPUT_ADR_START1:
5075         case NI_RTSI_OUTPUT_ADR_START2:
5076         case NI_RTSI_OUTPUT_SCLKG:
5077         case NI_RTSI_OUTPUT_DACUPDN:
5078         case NI_RTSI_OUTPUT_DA_START1:
5079         case NI_RTSI_OUTPUT_G_SRC0:
5080         case NI_RTSI_OUTPUT_G_GATE0:
5081         case NI_RTSI_OUTPUT_RGOUT0:
5082         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5083                 return 1;
5084         case NI_RTSI_OUTPUT_RTSI_OSC:
5085                 return (devpriv->is_m_series) ? 1 : 0;
5086         default:
5087                 return 0;
5088         }
5089 }
5090
5091 static int ni_set_rtsi_routing(struct comedi_device *dev,
5092                                unsigned chan, unsigned src)
5093 {
5094         struct ni_private *devpriv = dev->private;
5095
5096         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5097                 return -EINVAL;
5098         if (chan < 4) {
5099                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5100                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5101                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5102                               NISTC_RTSI_TRIGA_OUT_REG);
5103         } else if (chan < 8) {
5104                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5105                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5106                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5107                               NISTC_RTSI_TRIGB_OUT_REG);
5108         }
5109         return 2;
5110 }
5111
5112 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5113 {
5114         struct ni_private *devpriv = dev->private;
5115
5116         if (chan < 4) {
5117                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5118                                               devpriv->rtsi_trig_a_output_reg);
5119         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5120                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5121                                               devpriv->rtsi_trig_b_output_reg);
5122         } else {
5123                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
5124                         return NI_RTSI_OUTPUT_RTSI_OSC;
5125                 dev_err(dev->class_dev, "bug! should never get here?\n");
5126                 return 0;
5127         }
5128 }
5129
5130 static int ni_rtsi_insn_config(struct comedi_device *dev,
5131                                struct comedi_subdevice *s,
5132                                struct comedi_insn *insn,
5133                                unsigned int *data)
5134 {
5135         struct ni_private *devpriv = dev->private;
5136         unsigned int chan = CR_CHAN(insn->chanspec);
5137         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5138
5139         switch (data[0]) {
5140         case INSN_CONFIG_DIO_OUTPUT:
5141                 if (chan < max_chan) {
5142                         devpriv->rtsi_trig_direction_reg |=
5143                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5144                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5145                         devpriv->rtsi_trig_direction_reg |=
5146                             NISTC_RTSI_TRIG_DRV_CLK;
5147                 }
5148                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5149                               NISTC_RTSI_TRIG_DIR_REG);
5150                 break;
5151         case INSN_CONFIG_DIO_INPUT:
5152                 if (chan < max_chan) {
5153                         devpriv->rtsi_trig_direction_reg &=
5154                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5155                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5156                         devpriv->rtsi_trig_direction_reg &=
5157                             ~NISTC_RTSI_TRIG_DRV_CLK;
5158                 }
5159                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5160                               NISTC_RTSI_TRIG_DIR_REG);
5161                 break;
5162         case INSN_CONFIG_DIO_QUERY:
5163                 if (chan < max_chan) {
5164                         data[1] =
5165                             (devpriv->rtsi_trig_direction_reg &
5166                              NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5167                                 ? INSN_CONFIG_DIO_OUTPUT
5168                                 : INSN_CONFIG_DIO_INPUT;
5169                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5170                         data[1] = (devpriv->rtsi_trig_direction_reg &
5171                                    NISTC_RTSI_TRIG_DRV_CLK)
5172                                   ? INSN_CONFIG_DIO_OUTPUT
5173                                   : INSN_CONFIG_DIO_INPUT;
5174                 }
5175                 return 2;
5176         case INSN_CONFIG_SET_CLOCK_SRC:
5177                 return ni_set_master_clock(dev, data[1], data[2]);
5178         case INSN_CONFIG_GET_CLOCK_SRC:
5179                 data[1] = devpriv->clock_source;
5180                 data[2] = devpriv->clock_ns;
5181                 return 3;
5182         case INSN_CONFIG_SET_ROUTING:
5183                 return ni_set_rtsi_routing(dev, chan, data[1]);
5184         case INSN_CONFIG_GET_ROUTING:
5185                 data[1] = ni_get_rtsi_routing(dev, chan);
5186                 return 2;
5187         default:
5188                 return -EINVAL;
5189         }
5190         return 1;
5191 }
5192
5193 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5194                              struct comedi_subdevice *s,
5195                              struct comedi_insn *insn,
5196                              unsigned int *data)
5197 {
5198         data[1] = 0;
5199
5200         return insn->n;
5201 }
5202
5203 static void ni_rtsi_init(struct comedi_device *dev)
5204 {
5205         struct ni_private *devpriv = dev->private;
5206
5207         /*  Initialises the RTSI bus signal switch to a default state */
5208
5209         /*
5210          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5211          * to have no effect, at least on pxi-6281, which always uses
5212          * 20MHz rtsi clock frequency
5213          */
5214         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5215         /*  Set clock mode to internal */
5216         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5217                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5218         /*  default internal lines routing to RTSI bus lines */
5219         devpriv->rtsi_trig_a_output_reg =
5220             NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
5221             NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
5222             NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
5223             NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
5224         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5225                       NISTC_RTSI_TRIGA_OUT_REG);
5226         devpriv->rtsi_trig_b_output_reg =
5227             NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
5228             NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
5229             NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
5230         if (devpriv->is_m_series)
5231                 devpriv->rtsi_trig_b_output_reg |=
5232                     NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
5233         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5234                       NISTC_RTSI_TRIGB_OUT_REG);
5235
5236         /*
5237          * Sets the source and direction of the 4 on board lines
5238          * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
5239          */
5240 }
5241
5242 #ifdef PCIDMA
5243 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5244 {
5245         struct ni_gpct *counter = s->private;
5246         int retval;
5247
5248         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5249                                               COMEDI_INPUT);
5250         if (retval) {
5251                 dev_err(dev->class_dev,
5252                         "no dma channel available for use by counter\n");
5253                 return retval;
5254         }
5255         ni_tio_acknowledge(counter);
5256         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5257
5258         return ni_tio_cmd(dev, s);
5259 }
5260
5261 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5262 {
5263         struct ni_gpct *counter = s->private;
5264         int retval;
5265
5266         retval = ni_tio_cancel(counter);
5267         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5268         ni_release_gpct_mite_channel(dev, counter->counter_index);
5269         return retval;
5270 }
5271 #endif
5272
5273 static irqreturn_t ni_E_interrupt(int irq, void *d)
5274 {
5275         struct comedi_device *dev = d;
5276         unsigned short a_status;
5277         unsigned short b_status;
5278         unsigned int ai_mite_status = 0;
5279         unsigned int ao_mite_status = 0;
5280         unsigned long flags;
5281 #ifdef PCIDMA
5282         struct ni_private *devpriv = dev->private;
5283 #endif
5284
5285         if (!dev->attached)
5286                 return IRQ_NONE;
5287         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
5288
5289         /*  lock to avoid race with comedi_poll */
5290         spin_lock_irqsave(&dev->spinlock, flags);
5291         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5292         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5293 #ifdef PCIDMA
5294         if (devpriv->mite) {
5295                 unsigned long flags_too;
5296
5297                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5298                 if (devpriv->ai_mite_chan) {
5299                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5300                         if (ai_mite_status & CHSR_LINKC)
5301                                 writel(CHOR_CLRLC,
5302                                        devpriv->mite->mite_io_addr +
5303                                        MITE_CHOR(devpriv->
5304                                                  ai_mite_chan->channel));
5305                 }
5306                 if (devpriv->ao_mite_chan) {
5307                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5308                         if (ao_mite_status & CHSR_LINKC)
5309                                 writel(CHOR_CLRLC,
5310                                        devpriv->mite->mite_io_addr +
5311                                        MITE_CHOR(devpriv->
5312                                                  ao_mite_chan->channel));
5313                 }
5314                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5315         }
5316 #endif
5317         ack_a_interrupt(dev, a_status);
5318         ack_b_interrupt(dev, b_status);
5319         if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
5320                 handle_a_interrupt(dev, a_status, ai_mite_status);
5321         if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
5322                 handle_b_interrupt(dev, b_status, ao_mite_status);
5323         handle_gpct_interrupt(dev, 0);
5324         handle_gpct_interrupt(dev, 1);
5325         handle_cdio_interrupt(dev);
5326
5327         spin_unlock_irqrestore(&dev->spinlock, flags);
5328         return IRQ_HANDLED;
5329 }
5330
5331 static int ni_alloc_private(struct comedi_device *dev)
5332 {
5333         struct ni_private *devpriv;
5334
5335         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5336         if (!devpriv)
5337                 return -ENOMEM;
5338
5339         spin_lock_init(&devpriv->window_lock);
5340         spin_lock_init(&devpriv->soft_reg_copy_lock);
5341         spin_lock_init(&devpriv->mite_channel_lock);
5342
5343         return 0;
5344 }
5345
5346 static int ni_E_init(struct comedi_device *dev,
5347                      unsigned interrupt_pin, unsigned irq_polarity)
5348 {
5349         const struct ni_board_struct *board = dev->board_ptr;
5350         struct ni_private *devpriv = dev->private;
5351         struct comedi_subdevice *s;
5352         int ret;
5353         int i;
5354
5355         if (board->n_aochan > MAX_N_AO_CHAN) {
5356                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5357                 return -EINVAL;
5358         }
5359
5360         /* initialize clock dividers */
5361         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5362                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
5363                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5364                                   NISTC_CLK_FOUT_TO_BOARD;
5365         if (!devpriv->is_6xxx) {
5366                 /* BEAM is this needed for PCI-6143 ?? */
5367                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5368                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
5369         }
5370         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5371
5372         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5373         if (ret)
5374                 return ret;
5375
5376         /* Analog Input subdevice */
5377         s = &dev->subdevices[NI_AI_SUBDEV];
5378         if (board->n_adchan) {
5379                 s->type         = COMEDI_SUBD_AI;
5380                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5381                 if (!devpriv->is_611x)
5382                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5383                 if (board->ai_maxdata > 0xffff)
5384                         s->subdev_flags |= SDF_LSAMPL;
5385                 if (devpriv->is_m_series)
5386                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5387                 s->n_chan       = board->n_adchan;
5388                 s->maxdata      = board->ai_maxdata;
5389                 s->range_table  = ni_range_lkup[board->gainlkup];
5390                 s->insn_read    = ni_ai_insn_read;
5391                 s->insn_config  = ni_ai_insn_config;
5392                 if (dev->irq) {
5393                         dev->read_subdev = s;
5394                         s->subdev_flags |= SDF_CMD_READ;
5395                         s->len_chanlist = 512;
5396                         s->do_cmdtest   = ni_ai_cmdtest;
5397                         s->do_cmd       = ni_ai_cmd;
5398                         s->cancel       = ni_ai_reset;
5399                         s->poll         = ni_ai_poll;
5400                         s->munge        = ni_ai_munge;
5401
5402                         if (devpriv->mite)
5403                                 s->async_dma_dir = DMA_FROM_DEVICE;
5404                 }
5405
5406                 /* reset the analog input configuration */
5407                 ni_ai_reset(dev, s);
5408         } else {
5409                 s->type         = COMEDI_SUBD_UNUSED;
5410         }
5411
5412         /* Analog Output subdevice */
5413         s = &dev->subdevices[NI_AO_SUBDEV];
5414         if (board->n_aochan) {
5415                 s->type         = COMEDI_SUBD_AO;
5416                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5417                 if (devpriv->is_m_series)
5418                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5419                 s->n_chan       = board->n_aochan;
5420                 s->maxdata      = board->ao_maxdata;
5421                 s->range_table  = board->ao_range_table;
5422                 s->insn_config  = ni_ao_insn_config;
5423                 s->insn_write   = ni_ao_insn_write;
5424
5425                 ret = comedi_alloc_subdev_readback(s);
5426                 if (ret)
5427                         return ret;
5428
5429                 /*
5430                  * Along with the IRQ we need either a FIFO or DMA for
5431                  * async command support.
5432                  */
5433                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5434                         dev->write_subdev = s;
5435                         s->subdev_flags |= SDF_CMD_WRITE;
5436                         s->len_chanlist = s->n_chan;
5437                         s->do_cmdtest   = ni_ao_cmdtest;
5438                         s->do_cmd       = ni_ao_cmd;
5439                         s->cancel       = ni_ao_reset;
5440                         if (!devpriv->is_m_series)
5441                                 s->munge        = ni_ao_munge;
5442
5443                         if (devpriv->mite)
5444                                 s->async_dma_dir = DMA_TO_DEVICE;
5445                 }
5446
5447                 if (devpriv->is_67xx)
5448                         init_ao_67xx(dev, s);
5449
5450                 /* reset the analog output configuration */
5451                 ni_ao_reset(dev, s);
5452         } else {
5453                 s->type         = COMEDI_SUBD_UNUSED;
5454         }
5455
5456         /* Digital I/O subdevice */
5457         s = &dev->subdevices[NI_DIO_SUBDEV];
5458         s->type         = COMEDI_SUBD_DIO;
5459         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5460         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5461         s->maxdata      = 1;
5462         s->range_table  = &range_digital;
5463         if (devpriv->is_m_series) {
5464                 s->subdev_flags |= SDF_LSAMPL;
5465                 s->insn_bits    = ni_m_series_dio_insn_bits;
5466                 s->insn_config  = ni_m_series_dio_insn_config;
5467                 if (dev->irq) {
5468                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5469                         s->len_chanlist = s->n_chan;
5470                         s->do_cmdtest   = ni_cdio_cmdtest;
5471                         s->do_cmd       = ni_cdio_cmd;
5472                         s->cancel       = ni_cdio_cancel;
5473
5474                         /* M-series boards use DMA */
5475                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5476                 }
5477
5478                 /* reset DIO and set all channels to inputs */
5479                 ni_writel(dev, NI_M_CDO_CMD_RESET |
5480                                NI_M_CDI_CMD_RESET,
5481                           NI_M_CDIO_CMD_REG);
5482                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5483         } else {
5484                 s->insn_bits    = ni_dio_insn_bits;
5485                 s->insn_config  = ni_dio_insn_config;
5486
5487                 /* set all channels to inputs */
5488                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5489                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5490         }
5491
5492         /* 8255 device */
5493         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5494         if (board->has_8255) {
5495                 ret = subdev_8255_init(dev, s, ni_8255_callback,
5496                                        NI_E_8255_BASE);
5497                 if (ret)
5498                         return ret;
5499         } else {
5500                 s->type = COMEDI_SUBD_UNUSED;
5501         }
5502
5503         /* formerly general purpose counter/timer device, but no longer used */
5504         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5505         s->type = COMEDI_SUBD_UNUSED;
5506
5507         /* Calibration subdevice */
5508         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5509         s->type         = COMEDI_SUBD_CALIB;
5510         s->subdev_flags = SDF_INTERNAL;
5511         s->n_chan       = 1;
5512         s->maxdata      = 0;
5513         if (devpriv->is_m_series) {
5514                 /* internal PWM output used for AI nonlinearity calibration */
5515                 s->insn_config  = ni_m_series_pwm_config;
5516
5517                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5518         } else if (devpriv->is_6143) {
5519                 /* internal PWM output used for AI nonlinearity calibration */
5520                 s->insn_config  = ni_6143_pwm_config;
5521         } else {
5522                 s->subdev_flags |= SDF_WRITABLE;
5523                 s->insn_read    = ni_calib_insn_read;
5524                 s->insn_write   = ni_calib_insn_write;
5525
5526                 /* setup the caldacs and find the real n_chan and maxdata */
5527                 caldac_setup(dev, s);
5528         }
5529
5530         /* EEPROM subdevice */
5531         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5532         s->type         = COMEDI_SUBD_MEMORY;
5533         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5534         s->maxdata      = 0xff;
5535         if (devpriv->is_m_series) {
5536                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5537                 s->insn_read    = ni_m_series_eeprom_insn_read;
5538         } else {
5539                 s->n_chan       = 512;
5540                 s->insn_read    = ni_eeprom_insn_read;
5541         }
5542
5543         /* Digital I/O (PFI) subdevice */
5544         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5545         s->type         = COMEDI_SUBD_DIO;
5546         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5547         s->maxdata      = 1;
5548         if (devpriv->is_m_series) {
5549                 s->n_chan       = 16;
5550                 s->insn_bits    = ni_pfi_insn_bits;
5551
5552                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5553                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5554                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5555                                   NI_M_PFI_OUT_SEL_REG(i));
5556                 }
5557         } else {
5558                 s->n_chan       = 10;
5559         }
5560         s->insn_config  = ni_pfi_insn_config;
5561
5562         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5563
5564         /* cs5529 calibration adc */
5565         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5566         if (devpriv->is_67xx) {
5567                 s->type = COMEDI_SUBD_AI;
5568                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5569                 /*  one channel for each analog output channel */
5570                 s->n_chan = board->n_aochan;
5571                 s->maxdata = (1 << 16) - 1;
5572                 s->range_table = &range_unknown;        /* XXX */
5573                 s->insn_read = cs5529_ai_insn_read;
5574                 s->insn_config = NULL;
5575                 init_cs5529(dev);
5576         } else {
5577                 s->type = COMEDI_SUBD_UNUSED;
5578         }
5579
5580         /* Serial */
5581         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5582         s->type = COMEDI_SUBD_SERIAL;
5583         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5584         s->n_chan = 1;
5585         s->maxdata = 0xff;
5586         s->insn_config = ni_serial_insn_config;
5587         devpriv->serial_interval_ns = 0;
5588         devpriv->serial_hw_mode = 0;
5589
5590         /* RTSI */
5591         s = &dev->subdevices[NI_RTSI_SUBDEV];
5592         s->type = COMEDI_SUBD_DIO;
5593         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5594         s->n_chan = 8;
5595         s->maxdata = 1;
5596         s->insn_bits = ni_rtsi_insn_bits;
5597         s->insn_config = ni_rtsi_insn_config;
5598         ni_rtsi_init(dev);
5599
5600         /* allocate and initialize the gpct counter device */
5601         devpriv->counter_dev = ni_gpct_device_construct(dev,
5602                                         ni_gpct_write_register,
5603                                         ni_gpct_read_register,
5604                                         (devpriv->is_m_series)
5605                                                 ? ni_gpct_variant_m_series
5606                                                 : ni_gpct_variant_e_series,
5607                                         NUM_GPCT);
5608         if (!devpriv->counter_dev)
5609                 return -ENOMEM;
5610
5611         /* Counter (gpct) subdevices */
5612         for (i = 0; i < NUM_GPCT; ++i) {
5613                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5614
5615                 /* setup and initialize the counter */
5616                 gpct->chip_index = 0;
5617                 gpct->counter_index = i;
5618                 ni_tio_init_counter(gpct);
5619
5620                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5621                 s->type         = COMEDI_SUBD_COUNTER;
5622                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5623                 s->n_chan       = 3;
5624                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5625                                                          : 0x00ffffff;
5626                 s->insn_read    = ni_tio_insn_read;
5627                 s->insn_write   = ni_tio_insn_read;
5628                 s->insn_config  = ni_tio_insn_config;
5629 #ifdef PCIDMA
5630                 if (dev->irq && devpriv->mite) {
5631                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5632                         s->len_chanlist = 1;
5633                         s->do_cmdtest   = ni_tio_cmdtest;
5634                         s->do_cmd       = ni_gpct_cmd;
5635                         s->cancel       = ni_gpct_cancel;
5636
5637                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5638                 }
5639 #endif
5640                 s->private      = gpct;
5641         }
5642
5643         /* Frequency output subdevice */
5644         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5645         s->type         = COMEDI_SUBD_COUNTER;
5646         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5647         s->n_chan       = 1;
5648         s->maxdata      = 0xf;
5649         s->insn_read    = ni_freq_out_insn_read;
5650         s->insn_write   = ni_freq_out_insn_write;
5651         s->insn_config  = ni_freq_out_insn_config;
5652
5653         if (dev->irq) {
5654                 ni_stc_writew(dev,
5655                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5656                               (NISTC_INT_CTRL_3PIN_INT & 0) |
5657                               NISTC_INT_CTRL_INTA_ENA |
5658                               NISTC_INT_CTRL_INTB_ENA |
5659                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5660                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5661                               NISTC_INT_CTRL_REG);
5662         }
5663
5664         /* DMA setup */
5665         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5666         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5667
5668         if (devpriv->is_6xxx) {
5669                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5670         } else if (devpriv->is_m_series) {
5671                 int channel;
5672
5673                 for (channel = 0; channel < board->n_aochan; ++channel) {
5674                         ni_writeb(dev, 0xf,
5675                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
5676                         ni_writeb(dev, 0x0,
5677                                   NI_M_AO_REF_ATTENUATION_REG(channel));
5678                 }
5679                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5680         }
5681
5682         return 0;
5683 }
5684
5685 static void mio_common_detach(struct comedi_device *dev)
5686 {
5687         struct ni_private *devpriv = dev->private;
5688
5689         if (devpriv) {
5690                 if (devpriv->counter_dev)
5691                         ni_gpct_device_destroy(devpriv->counter_dev);
5692         }
5693 }