drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 /* #define DEBUG_INTERRUPT */
  61 /* #define DEBUG_STATUS_A */
  62 /* #define DEBUG_STATUS_B */
  63
  64 #include <linux/interrupt.h>
  65 #include <linux/sched.h>
  66 #include "8255.h"
  67 #include "mite.h"
  68 #include "comedi_fc.h"
  69
  70 #ifndef MDPRINTK
  71 #define MDPRINTK(format, args...)
  72 #endif
  73
  74 /* A timeout count */
  75 #define NI_TIMEOUT 1000
  76 static const unsigned old_RTSI_clock_channel = 7;
  77
  78 /* Note: this table must match the ai_gain_* definitions */
  79 static const short ni_gainlkup[][16] = {
  80         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  81                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  82         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  83         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  84                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  85         [ai_gain_4] = {0, 1, 4, 7},
  86         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  87                           0x003, 0x004, 0x005, 0x006},
  88         [ai_gain_622x] = {0, 1, 4, 5},
  89         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  90         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  91 };
  92
  93 static const struct comedi_lrange range_ni_E_ai = { 16, {
  94                                                          RANGE(-10, 10),
  95                                                          RANGE(-5, 5),
  96                                                          RANGE(-2.5, 2.5),
  97                                                          RANGE(-1, 1),
  98                                                          RANGE(-0.5, 0.5),
  99                                                          RANGE(-0.25, 0.25),
 100                                                          RANGE(-0.1, 0.1),
 101                                                          RANGE(-0.05, 0.05),
 102                                                          RANGE(0, 20),
 103                                                          RANGE(0, 10),
 104                                                          RANGE(0, 5),
 105                                                          RANGE(0, 2),
 106                                                          RANGE(0, 1),
 107                                                          RANGE(0, 0.5),
 108                                                          RANGE(0, 0.2),
 109                                                          RANGE(0, 0.1),
 110                                                          }
 111 };
 112
 113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
 114                                                                 RANGE(-10, 10),
 115                                                                 RANGE(-5, 5),
 116                                                                 RANGE(-1, 1),
 117                                                                 RANGE(-0.1,
 118                                                                       0.1),
 119                                                                 RANGE(0, 10),
 120                                                                 RANGE(0, 5),
 121                                                                 RANGE(0, 1),
 122                                                                 RANGE(0, 0.1),
 123                                                                 }
 124 };
 125
 126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
 127                                                                    RANGE(-10,
 128                                                                          10),
 129                                                                    RANGE(-5, 5),
 130                                                                    RANGE(-2, 2),
 131                                                                    RANGE(-1, 1),
 132                                                                    RANGE(-0.5,
 133                                                                          0.5),
 134                                                                    RANGE(-0.2,
 135                                                                          0.2),
 136                                                                    RANGE(-0.1,
 137                                                                          0.1),
 138                                                                    RANGE(0, 10),
 139                                                                    RANGE(0, 5),
 140                                                                    RANGE(0, 2),
 141                                                                    RANGE(0, 1),
 142                                                                    RANGE(0,
 143                                                                          0.5),
 144                                                                    RANGE(0,
 145                                                                          0.2),
 146                                                                    RANGE(0,
 147                                                                          0.1),
 148                                                                    }
 149 };
 150
 151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
 152                                                                  RANGE(-10, 10),
 153                                                                  RANGE(-5, 5),
 154                                                                  RANGE(-0.5,
 155                                                                        0.5),
 156                                                                  RANGE(-0.05,
 157                                                                        0.05),
 158                                                                  }
 159 };
 160
 161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
 162                                                              RANGE(-50, 50),
 163                                                              RANGE(-20, 20),
 164                                                              RANGE(-10, 10),
 165                                                              RANGE(-5, 5),
 166                                                              RANGE(-2, 2),
 167                                                              RANGE(-1, 1),
 168                                                              RANGE(-0.5, 0.5),
 169                                                              RANGE(-0.2, 0.2),
 170                                                              }
 171 };
 172
 173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
 174                                                              RANGE(-10, 10),
 175                                                              RANGE(-5, 5),
 176                                                              RANGE(-1, 1),
 177                                                              RANGE(-0.2, 0.2),
 178                                                              }
 179 };
 180
 181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
 182                                                              RANGE(-10, 10),
 183                                                              RANGE(-5, 5),
 184                                                              RANGE(-2, 2),
 185                                                              RANGE(-1, 1),
 186                                                              RANGE(-0.5, 0.5),
 187                                                              RANGE(-0.2, 0.2),
 188                                                              RANGE(-0.1, 0.1),
 189                                                              }
 190 };
 191
 192 static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
 193                                                              RANGE(-5, +5),
 194                                                              }
 195 };
 196
 197 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
 198                                                             RANGE(-10, 10),
 199                                                             RANGE(0, 10),
 200                                                             RANGE_ext(-1, 1),
 201                                                             RANGE_ext(0, 1),
 202                                                             }
 203 };
 204
 205 static const struct comedi_lrange *const ni_range_lkup[] = {
 206         [ai_gain_16] = &range_ni_E_ai,
 207         [ai_gain_8] = &range_ni_E_ai_limited,
 208         [ai_gain_14] = &range_ni_E_ai_limited14,
 209         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 210         [ai_gain_611x] = &range_ni_E_ai_611x,
 211         [ai_gain_622x] = &range_ni_M_ai_622x,
 212         [ai_gain_628x] = &range_ni_M_ai_628x,
 213         [ai_gain_6143] = &range_ni_S_ai_6143
 214 };
 215
 216 static int ni_dio_insn_config(struct comedi_device *dev,
 217                               struct comedi_subdevice *s,
 218                               struct comedi_insn *insn, unsigned int *data);
 219 static int ni_dio_insn_bits(struct comedi_device *dev,
 220                             struct comedi_subdevice *s,
 221                             struct comedi_insn *insn, unsigned int *data);
 222 static int ni_cdio_cmdtest(struct comedi_device *dev,
 223                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 224 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 225 static int ni_cdio_cancel(struct comedi_device *dev,
 226                           struct comedi_subdevice *s);
 227 static void handle_cdio_interrupt(struct comedi_device *dev);
 228 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 229                           unsigned int trignum);
 230
 231 static int ni_serial_insn_config(struct comedi_device *dev,
 232                                  struct comedi_subdevice *s,
 233                                  struct comedi_insn *insn, unsigned int *data);
 234 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 235                                    struct comedi_subdevice *s,
 236                                    unsigned char data_out,
 237                                    unsigned char *data_in);
 238 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 239                                    struct comedi_subdevice *s,
 240                                    unsigned char data_out,
 241                                    unsigned char *data_in);
 242
 243 static int ni_calib_insn_read(struct comedi_device *dev,
 244                               struct comedi_subdevice *s,
 245                               struct comedi_insn *insn, unsigned int *data);
 246 static int ni_calib_insn_write(struct comedi_device *dev,
 247                                struct comedi_subdevice *s,
 248                                struct comedi_insn *insn, unsigned int *data);
 249
 250 static int ni_eeprom_insn_read(struct comedi_device *dev,
 251                                struct comedi_subdevice *s,
 252                                struct comedi_insn *insn, unsigned int *data);
 253 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 254                                         struct comedi_subdevice *s,
 255                                         struct comedi_insn *insn,
 256                                         unsigned int *data);
 257
 258 static int ni_pfi_insn_bits(struct comedi_device *dev,
 259                             struct comedi_subdevice *s,
 260                             struct comedi_insn *insn, unsigned int *data);
 261 static int ni_pfi_insn_config(struct comedi_device *dev,
 262                               struct comedi_subdevice *s,
 263                               struct comedi_insn *insn, unsigned int *data);
 264 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 265                                        unsigned chan);
 266
 267 static void ni_rtsi_init(struct comedi_device *dev);
 268 static int ni_rtsi_insn_bits(struct comedi_device *dev,
 269                              struct comedi_subdevice *s,
 270                              struct comedi_insn *insn, unsigned int *data);
 271 static int ni_rtsi_insn_config(struct comedi_device *dev,
 272                                struct comedi_subdevice *s,
 273                                struct comedi_insn *insn, unsigned int *data);
 274
 275 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 276 static int ni_read_eeprom(struct comedi_device *dev, int addr);
 277
 278 #ifdef DEBUG_STATUS_A
 279 static void ni_mio_print_status_a(int status);
 280 #else
 281 #define ni_mio_print_status_a(a)
 282 #endif
 283 #ifdef DEBUG_STATUS_B
 284 static void ni_mio_print_status_b(int status);
 285 #else
 286 #define ni_mio_print_status_b(a)
 287 #endif
 288
 289 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 290 #ifndef PCIDMA
 291 static void ni_handle_fifo_half_full(struct comedi_device *dev);
 292 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 293                                  struct comedi_subdevice *s);
 294 #endif
 295 static void ni_handle_fifo_dregs(struct comedi_device *dev);
 296 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 297                          unsigned int trignum);
 298 static void ni_load_channelgain_list(struct comedi_device *dev,
 299                                      unsigned int n_chan, unsigned int *list);
 300 static void shutdown_ai_command(struct comedi_device *dev);
 301
 302 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 303                          unsigned int trignum);
 304
 305 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 306
 307 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 308
 309 static int ni_gpct_insn_write(struct comedi_device *dev,
 310                               struct comedi_subdevice *s,
 311                               struct comedi_insn *insn, unsigned int *data);
 312 static int ni_gpct_insn_read(struct comedi_device *dev,
 313                              struct comedi_subdevice *s,
 314                              struct comedi_insn *insn, unsigned int *data);
 315 static int ni_gpct_insn_config(struct comedi_device *dev,
 316                                struct comedi_subdevice *s,
 317                                struct comedi_insn *insn, unsigned int *data);
 318 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 319 static int ni_gpct_cmdtest(struct comedi_device *dev,
 320                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 321 static int ni_gpct_cancel(struct comedi_device *dev,
 322                           struct comedi_subdevice *s);
 323 static void handle_gpct_interrupt(struct comedi_device *dev,
 324                                   unsigned short counter_index);
 325
 326 static int init_cs5529(struct comedi_device *dev);
 327 static int cs5529_do_conversion(struct comedi_device *dev,
 328                                 unsigned short *data);
 329 static int cs5529_ai_insn_read(struct comedi_device *dev,
 330                                struct comedi_subdevice *s,
 331                                struct comedi_insn *insn, unsigned int *data);
 332 #ifdef NI_CS5529_DEBUG
 333 static unsigned int cs5529_config_read(struct comedi_device *dev,
 334                                        unsigned int reg_select_bits);
 335 #endif
 336 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 337                                 unsigned int reg_select_bits);
 338
 339 static int ni_m_series_pwm_config(struct comedi_device *dev,
 340                                   struct comedi_subdevice *s,
 341                                   struct comedi_insn *insn, unsigned int *data);
 342 static int ni_6143_pwm_config(struct comedi_device *dev,
 343                               struct comedi_subdevice *s,
 344                               struct comedi_insn *insn, unsigned int *data);
 345
 346 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 347                                unsigned period_ns);
 348 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 349 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 350
 351 enum aimodes {
 352         AIMODE_NONE = 0,
 353         AIMODE_HALF_FULL = 1,
 354         AIMODE_SCAN = 2,
 355         AIMODE_SAMPLE = 3,
 356 };
 357
 358 enum ni_common_subdevices {
 359         NI_AI_SUBDEV,
 360         NI_AO_SUBDEV,
 361         NI_DIO_SUBDEV,
 362         NI_8255_DIO_SUBDEV,
 363         NI_UNUSED_SUBDEV,
 364         NI_CALIBRATION_SUBDEV,
 365         NI_EEPROM_SUBDEV,
 366         NI_PFI_DIO_SUBDEV,
 367         NI_CS5529_CALIBRATION_SUBDEV,
 368         NI_SERIAL_SUBDEV,
 369         NI_RTSI_SUBDEV,
 370         NI_GPCT0_SUBDEV,
 371         NI_GPCT1_SUBDEV,
 372         NI_FREQ_OUT_SUBDEV,
 373         NI_NUM_SUBDEVICES
 374 };
 375 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 376 {
 377         switch (counter_index) {
 378         case 0:
 379                 return NI_GPCT0_SUBDEV;
 380                 break;
 381         case 1:
 382                 return NI_GPCT1_SUBDEV;
 383                 break;
 384         default:
 385                 break;
 386         }
 387         BUG();
 388         return NI_GPCT0_SUBDEV;
 389 }
 390
 391 enum timebase_nanoseconds {
 392         TIMEBASE_1_NS = 50,
 393         TIMEBASE_2_NS = 10000
 394 };
 395
 396 #define SERIAL_DISABLED         0
 397 #define SERIAL_600NS            600
 398 #define SERIAL_1_2US            1200
 399 #define SERIAL_10US                     10000
 400
 401 static const int num_adc_stages_611x = 3;
 402
 403 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 404                                unsigned ai_mite_status);
 405 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 406                                unsigned ao_mite_status);
 407 static void get_last_sample_611x(struct comedi_device *dev);
 408 static void get_last_sample_6143(struct comedi_device *dev);
 409
 410 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 411                                    unsigned bit_mask, unsigned bit_values)
 412 {
 413         struct ni_private *devpriv = dev->private;
 414         unsigned long flags;
 415
 416         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 417         switch (reg) {
 418         case Interrupt_A_Enable_Register:
 419                 devpriv->int_a_enable_reg &= ~bit_mask;
 420                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 421                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 422                                     Interrupt_A_Enable_Register);
 423                 break;
 424         case Interrupt_B_Enable_Register:
 425                 devpriv->int_b_enable_reg &= ~bit_mask;
 426                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 427                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 428                                     Interrupt_B_Enable_Register);
 429                 break;
 430         case IO_Bidirection_Pin_Register:
 431                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 432                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 433                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 434                                     IO_Bidirection_Pin_Register);
 435                 break;
 436         case AI_AO_Select:
 437                 devpriv->ai_ao_select_reg &= ~bit_mask;
 438                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 439                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 440                 break;
 441         case G0_G1_Select:
 442                 devpriv->g0_g1_select_reg &= ~bit_mask;
 443                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 444                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 445                 break;
 446         default:
 447                 printk("Warning %s() called with invalid register\n", __func__);
 448                 printk("reg is %d\n", reg);
 449                 break;
 450         }
 451         mmiowb();
 452         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 453 }
 454
 455 #ifdef PCIDMA
 456 static int ni_ai_drain_dma(struct comedi_device *dev);
 457
 458 /* DMA channel setup */
 459
 460 /* negative channel means no channel */
 461 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 462 {
 463         unsigned bitfield;
 464
 465         if (channel >= 0) {
 466                 bitfield =
 467                     (ni_stc_dma_channel_select_bitfield(channel) <<
 468                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 469         } else {
 470                 bitfield = 0;
 471         }
 472         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 473 }
 474
 475 /* negative channel means no channel */
 476 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 477 {
 478         unsigned bitfield;
 479
 480         if (channel >= 0) {
 481                 bitfield =
 482                     (ni_stc_dma_channel_select_bitfield(channel) <<
 483                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 484         } else {
 485                 bitfield = 0;
 486         }
 487         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 488 }
 489
 490 /* negative mite_channel means no channel */
 491 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 492                                            unsigned gpct_index,
 493                                            int mite_channel)
 494 {
 495         unsigned bitfield;
 496
 497         if (mite_channel >= 0) {
 498                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 499         } else {
 500                 bitfield = 0;
 501         }
 502         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 503                         bitfield);
 504 }
 505
 506 /* negative mite_channel means no channel */
 507 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 508                                           int mite_channel)
 509 {
 510         struct ni_private *devpriv = dev->private;
 511         unsigned long flags;
 512
 513         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 514         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 515         if (mite_channel >= 0) {
 516                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 517                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 518                    Definitely works for dma channels 0 and 1. */
 519                 devpriv->cdio_dma_select_reg |=
 520                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 521                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 522         }
 523         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 524         mmiowb();
 525         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 526 }
 527
 528 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 529 {
 530         struct ni_private *devpriv = dev->private;
 531         unsigned long flags;
 532
 533         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 534         BUG_ON(devpriv->ai_mite_chan);
 535         devpriv->ai_mite_chan =
 536             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 537         if (devpriv->ai_mite_chan == NULL) {
 538                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 539                 comedi_error(dev,
 540                              "failed to reserve mite dma channel for analog input.");
 541                 return -EBUSY;
 542         }
 543         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 544         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 545         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 546         return 0;
 547 }
 548
 549 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 550 {
 551         struct ni_private *devpriv = dev->private;
 552         unsigned long flags;
 553
 554         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 555         BUG_ON(devpriv->ao_mite_chan);
 556         devpriv->ao_mite_chan =
 557             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 558         if (devpriv->ao_mite_chan == NULL) {
 559                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 560                 comedi_error(dev,
 561                              "failed to reserve mite dma channel for analog outut.");
 562                 return -EBUSY;
 563         }
 564         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 565         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 566         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 567         return 0;
 568 }
 569
 570 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 571                                         unsigned gpct_index,
 572                                         enum comedi_io_direction direction)
 573 {
 574         struct ni_private *devpriv = dev->private;
 575         unsigned long flags;
 576         struct mite_channel *mite_chan;
 577
 578         BUG_ON(gpct_index >= NUM_GPCT);
 579         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 580         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 581         mite_chan =
 582             mite_request_channel(devpriv->mite,
 583                                  devpriv->gpct_mite_ring[gpct_index]);
 584         if (mite_chan == NULL) {
 585                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 586                 comedi_error(dev,
 587                              "failed to reserve mite dma channel for counter.");
 588                 return -EBUSY;
 589         }
 590         mite_chan->dir = direction;
 591         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 592                                 mite_chan);
 593         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 594         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 595         return 0;
 596 }
 597
 598 #endif /*  PCIDMA */
 599
 600 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 601 {
 602 #ifdef PCIDMA
 603         struct ni_private *devpriv = dev->private;
 604         unsigned long flags;
 605
 606         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 607         BUG_ON(devpriv->cdo_mite_chan);
 608         devpriv->cdo_mite_chan =
 609             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 610         if (devpriv->cdo_mite_chan == NULL) {
 611                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 612                 comedi_error(dev,
 613                              "failed to reserve mite dma channel for correlated digital outut.");
 614                 return -EBUSY;
 615         }
 616         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 617         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 618         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 619 #endif /*  PCIDMA */
 620         return 0;
 621 }
 622
 623 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 624 {
 625 #ifdef PCIDMA
 626         struct ni_private *devpriv = dev->private;
 627         unsigned long flags;
 628
 629         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 630         if (devpriv->ai_mite_chan) {
 631                 ni_set_ai_dma_channel(dev, -1);
 632                 mite_release_channel(devpriv->ai_mite_chan);
 633                 devpriv->ai_mite_chan = NULL;
 634         }
 635         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 636 #endif /*  PCIDMA */
 637 }
 638
 639 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 640 {
 641 #ifdef PCIDMA
 642         struct ni_private *devpriv = dev->private;
 643         unsigned long flags;
 644
 645         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 646         if (devpriv->ao_mite_chan) {
 647                 ni_set_ao_dma_channel(dev, -1);
 648                 mite_release_channel(devpriv->ao_mite_chan);
 649                 devpriv->ao_mite_chan = NULL;
 650         }
 651         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 652 #endif /*  PCIDMA */
 653 }
 654
 655 #ifdef PCIDMA
 656 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 657                                          unsigned gpct_index)
 658 {
 659         struct ni_private *devpriv = dev->private;
 660         unsigned long flags;
 661
 662         BUG_ON(gpct_index >= NUM_GPCT);
 663         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 664         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 665                 struct mite_channel *mite_chan =
 666                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 667
 668                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 669                 ni_tio_set_mite_channel(&devpriv->
 670                                         counter_dev->counters[gpct_index],
 671                                         NULL);
 672                 mite_release_channel(mite_chan);
 673         }
 674         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 675 }
 676 #endif /*  PCIDMA */
 677
 678 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 679 {
 680 #ifdef PCIDMA
 681         struct ni_private *devpriv = dev->private;
 682         unsigned long flags;
 683
 684         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 685         if (devpriv->cdo_mite_chan) {
 686                 ni_set_cdo_dma_channel(dev, -1);
 687                 mite_release_channel(devpriv->cdo_mite_chan);
 688                 devpriv->cdo_mite_chan = NULL;
 689         }
 690         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 691 #endif /*  PCIDMA */
 692 }
 693
 694 /* e-series boards use the second irq signals to generate dma requests for their counters */
 695 #ifdef PCIDMA
 696 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 697                                           unsigned gpct_index, short enable)
 698 {
 699         struct ni_private *devpriv = dev->private;
 700
 701         if (boardtype.reg_type & ni_reg_m_series_mask)
 702                 return;
 703         switch (gpct_index) {
 704         case 0:
 705                 if (enable) {
 706                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 707                                             Second_IRQ_A_Enable_Register);
 708                 } else {
 709                         devpriv->stc_writew(dev, 0,
 710                                             Second_IRQ_A_Enable_Register);
 711                 }
 712                 break;
 713         case 1:
 714                 if (enable) {
 715                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 716                                             Second_IRQ_B_Enable_Register);
 717                 } else {
 718                         devpriv->stc_writew(dev, 0,
 719                                             Second_IRQ_B_Enable_Register);
 720                 }
 721                 break;
 722         default:
 723                 BUG();
 724                 break;
 725         }
 726 }
 727 #endif /*  PCIDMA */
 728
 729 static void ni_clear_ai_fifo(struct comedi_device *dev)
 730 {
 731         struct ni_private *devpriv = dev->private;
 732
 733         if (boardtype.reg_type == ni_reg_6143) {
 734                 /*  Flush the 6143 data FIFO */
 735                 ni_writel(0x10, AIFIFO_Control_6143);   /*  Flush fifo */
 736                 ni_writel(0x00, AIFIFO_Control_6143);   /*  Flush fifo */
 737                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   /*  Wait for complete */
 738         } else {
 739                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 740                 if (boardtype.reg_type == ni_reg_625x) {
 741                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 742                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 743 #if 0
 744                         /* the NI example code does 3 convert pulses for 625x boards,
 745                            but that appears to be wrong in practice. */
 746                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 747                                             AI_Command_1_Register);
 748                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 749                                             AI_Command_1_Register);
 750                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 751                                             AI_Command_1_Register);
 752 #endif
 753                 }
 754         }
 755 }
 756
 757 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 758 {
 759         struct ni_private *devpriv = dev->private;
 760
 761         devpriv->stc_writew(dev, data >> 16, reg);
 762         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 763 }
 764
 765 static uint32_t win_in2(struct comedi_device *dev, int reg)
 766 {
 767         struct ni_private *devpriv = dev->private;
 768         uint32_t bits;
 769
 770         bits = devpriv->stc_readw(dev, reg) << 16;
 771         bits |= devpriv->stc_readw(dev, reg + 1);
 772         return bits;
 773 }
 774
 775 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 776 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 777                                   int addr)
 778 {
 779         struct ni_private *devpriv = dev->private;
 780         unsigned long flags;
 781
 782         spin_lock_irqsave(&devpriv->window_lock, flags);
 783         ni_writew(addr, AO_Window_Address_611x);
 784         ni_writew(data, AO_Window_Data_611x);
 785         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 786 }
 787
 788 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 789                                   int addr)
 790 {
 791         struct ni_private *devpriv = dev->private;
 792         unsigned long flags;
 793
 794         spin_lock_irqsave(&devpriv->window_lock, flags);
 795         ni_writew(addr, AO_Window_Address_611x);
 796         ni_writel(data, AO_Window_Data_611x);
 797         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 798 }
 799
 800 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 801 {
 802         struct ni_private *devpriv = dev->private;
 803         unsigned long flags;
 804         unsigned short data;
 805
 806         spin_lock_irqsave(&devpriv->window_lock, flags);
 807         ni_writew(addr, AO_Window_Address_611x);
 808         data = ni_readw(AO_Window_Data_611x);
 809         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 810         return data;
 811 }
 812
 813 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 814 * share registers (such as Interrupt_A_Register) without interfering with
 815 * each other.
 816 *
 817 * NOTE: the switch/case statements are optimized out for a constant argument
 818 * so this is actually quite fast---  If you must wrap another function around this
 819 * make it inline to avoid a large speed penalty.
 820 *
 821 * value should only be 1 or 0.
 822 */
 823 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 824                                unsigned bits, unsigned value)
 825 {
 826         unsigned bit_values;
 827
 828         if (value)
 829                 bit_values = bits;
 830         else
 831                 bit_values = 0;
 832         ni_set_bitfield(dev, reg, bits, bit_values);
 833 }
 834
 835 static irqreturn_t ni_E_interrupt(int irq, void *d)
 836 {
 837         struct comedi_device *dev = d;
 838         struct ni_private *devpriv = dev->private;
 839         unsigned short a_status;
 840         unsigned short b_status;
 841         unsigned int ai_mite_status = 0;
 842         unsigned int ao_mite_status = 0;
 843         unsigned long flags;
 844 #ifdef PCIDMA
 845         struct mite_struct *mite = devpriv->mite;
 846 #endif
 847
 848         if (dev->attached == 0)
 849                 return IRQ_NONE;
 850         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
 851
 852         /*  lock to avoid race with comedi_poll */
 853         spin_lock_irqsave(&dev->spinlock, flags);
 854         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 855         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 856 #ifdef PCIDMA
 857         if (mite) {
 858                 unsigned long flags_too;
 859
 860                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 861                 if (devpriv->ai_mite_chan) {
 862                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 863                         if (ai_mite_status & CHSR_LINKC)
 864                                 writel(CHOR_CLRLC,
 865                                        devpriv->mite->mite_io_addr +
 866                                        MITE_CHOR(devpriv->
 867                                                  ai_mite_chan->channel));
 868                 }
 869                 if (devpriv->ao_mite_chan) {
 870                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 871                         if (ao_mite_status & CHSR_LINKC)
 872                                 writel(CHOR_CLRLC,
 873                                        mite->mite_io_addr +
 874                                        MITE_CHOR(devpriv->
 875                                                  ao_mite_chan->channel));
 876                 }
 877                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 878         }
 879 #endif
 880         ack_a_interrupt(dev, a_status);
 881         ack_b_interrupt(dev, b_status);
 882         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 883                 handle_a_interrupt(dev, a_status, ai_mite_status);
 884         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 885                 handle_b_interrupt(dev, b_status, ao_mite_status);
 886         handle_gpct_interrupt(dev, 0);
 887         handle_gpct_interrupt(dev, 1);
 888         handle_cdio_interrupt(dev);
 889
 890         spin_unlock_irqrestore(&dev->spinlock, flags);
 891         return IRQ_HANDLED;
 892 }
 893
 894 #ifdef PCIDMA
 895 static void ni_sync_ai_dma(struct comedi_device *dev)
 896 {
 897         struct ni_private *devpriv = dev->private;
 898         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 899         unsigned long flags;
 900
 901         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 902         if (devpriv->ai_mite_chan)
 903                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 904         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 905 }
 906
 907 static void mite_handle_b_linkc(struct mite_struct *mite,
 908                                 struct comedi_device *dev)
 909 {
 910         struct ni_private *devpriv = dev->private;
 911         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
 912         unsigned long flags;
 913
 914         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 915         if (devpriv->ao_mite_chan) {
 916                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 917         }
 918         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 919 }
 920
 921 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 922 {
 923         struct ni_private *devpriv = dev->private;
 924         static const int timeout = 10000;
 925         int i;
 926         for (i = 0; i < timeout; i++) {
 927                 unsigned short b_status;
 928
 929                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 930                 if (b_status & AO_FIFO_Half_Full_St)
 931                         break;
 932                 /* if we poll too often, the pci bus activity seems
 933                    to slow the dma transfer down */
 934                 udelay(10);
 935         }
 936         if (i == timeout) {
 937                 comedi_error(dev, "timed out waiting for dma load");
 938                 return -EPIPE;
 939         }
 940         return 0;
 941 }
 942
 943 #endif /* PCIDMA */
 944 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 945 {
 946         struct ni_private *devpriv = dev->private;
 947
 948         if (devpriv->aimode == AIMODE_SCAN) {
 949 #ifdef PCIDMA
 950                 static const int timeout = 10;
 951                 int i;
 952
 953                 for (i = 0; i < timeout; i++) {
 954                         ni_sync_ai_dma(dev);
 955                         if ((s->async->events & COMEDI_CB_EOS))
 956                                 break;
 957                         udelay(1);
 958                 }
 959 #else
 960                 ni_handle_fifo_dregs(dev);
 961                 s->async->events |= COMEDI_CB_EOS;
 962 #endif
 963         }
 964         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 965         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 966                 shutdown_ai_command(dev);
 967         }
 968 }
 969
 970 static void shutdown_ai_command(struct comedi_device *dev)
 971 {
 972         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 973
 974 #ifdef PCIDMA
 975         ni_ai_drain_dma(dev);
 976 #endif
 977         ni_handle_fifo_dregs(dev);
 978         get_last_sample_611x(dev);
 979         get_last_sample_6143(dev);
 980
 981         s->async->events |= COMEDI_CB_EOA;
 982 }
 983
 984 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
 985 {
 986         if (s->
 987             async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
 988                              COMEDI_CB_EOA)) {
 989                 switch (s->index) {
 990                 case NI_AI_SUBDEV:
 991                         ni_ai_reset(dev, s);
 992                         break;
 993                 case NI_AO_SUBDEV:
 994                         ni_ao_reset(dev, s);
 995                         break;
 996                 case NI_GPCT0_SUBDEV:
 997                 case NI_GPCT1_SUBDEV:
 998                         ni_gpct_cancel(dev, s);
 999                         break;
1000                 case NI_DIO_SUBDEV:
1001                         ni_cdio_cancel(dev, s);
1002                         break;
1003                 default:
1004                         break;
1005                 }
1006         }
1007         comedi_event(dev, s);
1008 }
1009
1010 static void handle_gpct_interrupt(struct comedi_device *dev,
1011                                   unsigned short counter_index)
1012 {
1013 #ifdef PCIDMA
1014         struct ni_private *devpriv = dev->private;
1015         struct comedi_subdevice *s;
1016
1017         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1018
1019         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1020                                 s);
1021         if (s->async->events)
1022                 ni_event(dev, s);
1023 #endif
1024 }
1025
1026 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1027 {
1028         struct ni_private *devpriv = dev->private;
1029         unsigned short ack = 0;
1030
1031         if (a_status & AI_SC_TC_St) {
1032                 ack |= AI_SC_TC_Interrupt_Ack;
1033         }
1034         if (a_status & AI_START1_St) {
1035                 ack |= AI_START1_Interrupt_Ack;
1036         }
1037         if (a_status & AI_START_St) {
1038                 ack |= AI_START_Interrupt_Ack;
1039         }
1040         if (a_status & AI_STOP_St) {
1041                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1042                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1043         }
1044         if (ack)
1045                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1046 }
1047
1048 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1049                                unsigned ai_mite_status)
1050 {
1051         struct ni_private *devpriv = dev->private;
1052         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1053
1054         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1055         if (s->type == COMEDI_SUBD_UNUSED)
1056                 return;
1057
1058 #ifdef DEBUG_INTERRUPT
1059         printk
1060             ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1061              status, ai_mite_status);
1062         ni_mio_print_status_a(status);
1063 #endif
1064 #ifdef PCIDMA
1065         if (ai_mite_status & CHSR_LINKC) {
1066                 ni_sync_ai_dma(dev);
1067         }
1068
1069         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1070                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1071                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1072                 printk
1073                     ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1074                      ai_mite_status);
1075                 /* mite_print_chsr(ai_mite_status); */
1076                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1077                 /* disable_irq(dev->irq); */
1078         }
1079 #endif
1080
1081         /* test for all uncommon interrupt events at the same time */
1082         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1083                       AI_SC_TC_St | AI_START1_St)) {
1084                 if (status == 0xffff) {
1085                         printk
1086                             ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1087                         /* we probably aren't even running a command now,
1088                          * so it's a good idea to be careful. */
1089                         if (comedi_is_subdevice_running(s)) {
1090                                 s->async->events |=
1091                                     COMEDI_CB_ERROR | COMEDI_CB_EOA;
1092                                 ni_event(dev, s);
1093                         }
1094                         return;
1095                 }
1096                 if (status & (AI_Overrun_St | AI_Overflow_St |
1097                               AI_SC_TC_Error_St)) {
1098                         printk("ni_mio_common: ai error a_status=%04x\n",
1099                                status);
1100                         ni_mio_print_status_a(status);
1101
1102                         shutdown_ai_command(dev);
1103
1104                         s->async->events |= COMEDI_CB_ERROR;
1105                         if (status & (AI_Overrun_St | AI_Overflow_St))
1106                                 s->async->events |= COMEDI_CB_OVERFLOW;
1107
1108                         ni_event(dev, s);
1109
1110                         return;
1111                 }
1112                 if (status & AI_SC_TC_St) {
1113 #ifdef DEBUG_INTERRUPT
1114                         printk("ni_mio_common: SC_TC interrupt\n");
1115 #endif
1116                         if (!devpriv->ai_continuous) {
1117                                 shutdown_ai_command(dev);
1118                         }
1119                 }
1120         }
1121 #ifndef PCIDMA
1122         if (status & AI_FIFO_Half_Full_St) {
1123                 int i;
1124                 static const int timeout = 10;
1125                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1126                  *fail to get the fifo less than half full, so loop to be sure.*/
1127                 for (i = 0; i < timeout; ++i) {
1128                         ni_handle_fifo_half_full(dev);
1129                         if ((devpriv->stc_readw(dev,
1130                                                 AI_Status_1_Register) &
1131                              AI_FIFO_Half_Full_St) == 0)
1132                                 break;
1133                 }
1134         }
1135 #endif /*  !PCIDMA */
1136
1137         if ((status & AI_STOP_St)) {
1138                 ni_handle_eos(dev, s);
1139         }
1140
1141         ni_event(dev, s);
1142
1143 #ifdef DEBUG_INTERRUPT
1144         status = devpriv->stc_readw(dev, AI_Status_1_Register);
1145         if (status & Interrupt_A_St) {
1146                 printk
1147                     ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1148                      status);
1149         }
1150 #endif
1151 }
1152
1153 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1154 {
1155         struct ni_private *devpriv = dev->private;
1156         unsigned short ack = 0;
1157
1158         if (b_status & AO_BC_TC_St) {
1159                 ack |= AO_BC_TC_Interrupt_Ack;
1160         }
1161         if (b_status & AO_Overrun_St) {
1162                 ack |= AO_Error_Interrupt_Ack;
1163         }
1164         if (b_status & AO_START_St) {
1165                 ack |= AO_START_Interrupt_Ack;
1166         }
1167         if (b_status & AO_START1_St) {
1168                 ack |= AO_START1_Interrupt_Ack;
1169         }
1170         if (b_status & AO_UC_TC_St) {
1171                 ack |= AO_UC_TC_Interrupt_Ack;
1172         }
1173         if (b_status & AO_UI2_TC_St) {
1174                 ack |= AO_UI2_TC_Interrupt_Ack;
1175         }
1176         if (b_status & AO_UPDATE_St) {
1177                 ack |= AO_UPDATE_Interrupt_Ack;
1178         }
1179         if (ack)
1180                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1181 }
1182
1183 static void handle_b_interrupt(struct comedi_device *dev,
1184                                unsigned short b_status, unsigned ao_mite_status)
1185 {
1186         struct ni_private *devpriv = dev->private;
1187         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1188         /* unsigned short ack=0; */
1189
1190 #ifdef DEBUG_INTERRUPT
1191         printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1192                b_status, ao_mite_status);
1193         ni_mio_print_status_b(b_status);
1194 #endif
1195
1196 #ifdef PCIDMA
1197         /* Currently, mite.c requires us to handle LINKC */
1198         if (ao_mite_status & CHSR_LINKC) {
1199                 mite_handle_b_linkc(devpriv->mite, dev);
1200         }
1201
1202         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1203                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1204                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1205                 printk
1206                     ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1207                      ao_mite_status);
1208                 /* mite_print_chsr(ao_mite_status); */
1209                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1210         }
1211 #endif
1212
1213         if (b_status == 0xffff)
1214                 return;
1215         if (b_status & AO_Overrun_St) {
1216                 printk
1217                     ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1218                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1219                 s->async->events |= COMEDI_CB_OVERFLOW;
1220         }
1221
1222         if (b_status & AO_BC_TC_St) {
1223                 MDPRINTK
1224                     ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1225                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1226                 s->async->events |= COMEDI_CB_EOA;
1227         }
1228 #ifndef PCIDMA
1229         if (b_status & AO_FIFO_Request_St) {
1230                 int ret;
1231
1232                 ret = ni_ao_fifo_half_empty(dev, s);
1233                 if (!ret) {
1234                         printk("ni_mio_common: AO buffer underrun\n");
1235                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1236                                     AO_FIFO_Interrupt_Enable |
1237                                     AO_Error_Interrupt_Enable, 0);
1238                         s->async->events |= COMEDI_CB_OVERFLOW;
1239                 }
1240         }
1241 #endif
1242
1243         ni_event(dev, s);
1244 }
1245
1246 #ifdef DEBUG_STATUS_A
1247 static const char *const status_a_strings[] = {
1248         "passthru0", "fifo", "G0_gate", "G0_TC",
1249         "stop", "start", "sc_tc", "start1",
1250         "start2", "sc_tc_error", "overflow", "overrun",
1251         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1252 };
1253
1254 static void ni_mio_print_status_a(int status)
1255 {
1256         int i;
1257
1258         printk("A status:");
1259         for (i = 15; i >= 0; i--) {
1260                 if (status & (1 << i)) {
1261                         printk(" %s", status_a_strings[i]);
1262                 }
1263         }
1264         printk("\n");
1265 }
1266 #endif
1267
1268 #ifdef DEBUG_STATUS_B
1269 static const char *const status_b_strings[] = {
1270         "passthru1", "fifo", "G1_gate", "G1_TC",
1271         "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1272         "start1", "overrun", "start", "bc_tc_error",
1273         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1274 };
1275
1276 static void ni_mio_print_status_b(int status)
1277 {
1278         int i;
1279
1280         printk("B status:");
1281         for (i = 15; i >= 0; i--) {
1282                 if (status & (1 << i)) {
1283                         printk(" %s", status_b_strings[i]);
1284                 }
1285         }
1286         printk("\n");
1287 }
1288 #endif
1289
1290 #ifndef PCIDMA
1291
1292 static void ni_ao_fifo_load(struct comedi_device *dev,
1293                             struct comedi_subdevice *s, int n)
1294 {
1295         struct comedi_async *async = s->async;
1296         struct comedi_cmd *cmd = &async->cmd;
1297         int chan;
1298         int i;
1299         short d;
1300         u32 packed_data;
1301         int range;
1302         int err = 1;
1303
1304         chan = async->cur_chan;
1305         for (i = 0; i < n; i++) {
1306                 err &= comedi_buf_get(async, &d);
1307                 if (err == 0)
1308                         break;
1309
1310                 range = CR_RANGE(cmd->chanlist[chan]);
1311
1312                 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1313                         packed_data = d & 0xffff;
1314                         /* 6711 only has 16 bit wide ao fifo */
1315                         if (boardtype.reg_type != ni_reg_6711) {
1316                                 err &= comedi_buf_get(async, &d);
1317                                 if (err == 0)
1318                                         break;
1319                                 chan++;
1320                                 i++;
1321                                 packed_data |= (d << 16) & 0xffff0000;
1322                         }
1323                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1324                 } else {
1325                         ni_writew(d, DAC_FIFO_Data);
1326                 }
1327                 chan++;
1328                 chan %= cmd->chanlist_len;
1329         }
1330         async->cur_chan = chan;
1331         if (err == 0) {
1332                 async->events |= COMEDI_CB_OVERFLOW;
1333         }
1334 }
1335
1336 /*
1337  *  There's a small problem if the FIFO gets really low and we
1338  *  don't have the data to fill it.  Basically, if after we fill
1339  *  the FIFO with all the data available, the FIFO is _still_
1340  *  less than half full, we never clear the interrupt.  If the
1341  *  IRQ is in edge mode, we never get another interrupt, because
1342  *  this one wasn't cleared.  If in level mode, we get flooded
1343  *  with interrupts that we can't fulfill, because nothing ever
1344  *  gets put into the buffer.
1345  *
1346  *  This kind of situation is recoverable, but it is easier to
1347  *  just pretend we had a FIFO underrun, since there is a good
1348  *  chance it will happen anyway.  This is _not_ the case for
1349  *  RT code, as RT code might purposely be running close to the
1350  *  metal.  Needs to be fixed eventually.
1351  */
1352 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1353                                  struct comedi_subdevice *s)
1354 {
1355         int n;
1356
1357         n = comedi_buf_read_n_available(s->async);
1358         if (n == 0) {
1359                 s->async->events |= COMEDI_CB_OVERFLOW;
1360                 return 0;
1361         }
1362
1363         n /= sizeof(short);
1364         if (n > boardtype.ao_fifo_depth / 2)
1365                 n = boardtype.ao_fifo_depth / 2;
1366
1367         ni_ao_fifo_load(dev, s, n);
1368
1369         s->async->events |= COMEDI_CB_BLOCK;
1370
1371         return 1;
1372 }
1373
1374 static int ni_ao_prep_fifo(struct comedi_device *dev,
1375                            struct comedi_subdevice *s)
1376 {
1377         struct ni_private *devpriv = dev->private;
1378         int n;
1379
1380         /* reset fifo */
1381         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1382         if (boardtype.reg_type & ni_reg_6xxx_mask)
1383                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1384
1385         /* load some data */
1386         n = comedi_buf_read_n_available(s->async);
1387         if (n == 0)
1388                 return 0;
1389
1390         n /= sizeof(short);
1391         if (n > boardtype.ao_fifo_depth)
1392                 n = boardtype.ao_fifo_depth;
1393
1394         ni_ao_fifo_load(dev, s, n);
1395
1396         return n;
1397 }
1398
1399 static void ni_ai_fifo_read(struct comedi_device *dev,
1400                             struct comedi_subdevice *s, int n)
1401 {
1402         struct ni_private *devpriv = dev->private;
1403         struct comedi_async *async = s->async;
1404         int i;
1405
1406         if (boardtype.reg_type == ni_reg_611x) {
1407                 short data[2];
1408                 u32 dl;
1409
1410                 for (i = 0; i < n / 2; i++) {
1411                         dl = ni_readl(ADC_FIFO_Data_611x);
1412                         /* This may get the hi/lo data in the wrong order */
1413                         data[0] = (dl >> 16) & 0xffff;
1414                         data[1] = dl & 0xffff;
1415                         cfc_write_array_to_buffer(s, data, sizeof(data));
1416                 }
1417                 /* Check if there's a single sample stuck in the FIFO */
1418                 if (n % 2) {
1419                         dl = ni_readl(ADC_FIFO_Data_611x);
1420                         data[0] = dl & 0xffff;
1421                         cfc_write_to_buffer(s, data[0]);
1422                 }
1423         } else if (boardtype.reg_type == ni_reg_6143) {
1424                 short data[2];
1425                 u32 dl;
1426
1427                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1428                 for (i = 0; i < n / 2; i++) {
1429                         dl = ni_readl(AIFIFO_Data_6143);
1430
1431                         data[0] = (dl >> 16) & 0xffff;
1432                         data[1] = dl & 0xffff;
1433                         cfc_write_array_to_buffer(s, data, sizeof(data));
1434                 }
1435                 if (n % 2) {
1436                         /* Assume there is a single sample stuck in the FIFO */
1437                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1438                         dl = ni_readl(AIFIFO_Data_6143);
1439                         data[0] = (dl >> 16) & 0xffff;
1440                         cfc_write_to_buffer(s, data[0]);
1441                 }
1442         } else {
1443                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1444                     sizeof(devpriv->ai_fifo_buffer[0])) {
1445                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1446                         async->events |= COMEDI_CB_ERROR;
1447                         return;
1448                 }
1449                 for (i = 0; i < n; i++) {
1450                         devpriv->ai_fifo_buffer[i] =
1451                             ni_readw(ADC_FIFO_Data_Register);
1452                 }
1453                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1454                                           n *
1455                                           sizeof(devpriv->ai_fifo_buffer[0]));
1456         }
1457 }
1458
1459 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1460 {
1461         int n;
1462         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1463
1464         n = boardtype.ai_fifo_depth / 2;
1465
1466         ni_ai_fifo_read(dev, s, n);
1467 }
1468 #endif
1469
1470 #ifdef PCIDMA
1471 static int ni_ai_drain_dma(struct comedi_device *dev)
1472 {
1473         struct ni_private *devpriv = dev->private;
1474         int i;
1475         static const int timeout = 10000;
1476         unsigned long flags;
1477         int retval = 0;
1478
1479         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1480         if (devpriv->ai_mite_chan) {
1481                 for (i = 0; i < timeout; i++) {
1482                         if ((devpriv->stc_readw(dev,
1483                                                 AI_Status_1_Register) &
1484                              AI_FIFO_Empty_St)
1485                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1486                             0)
1487                                 break;
1488                         udelay(5);
1489                 }
1490                 if (i == timeout) {
1491                         printk("ni_mio_common: wait for dma drain timed out\n");
1492                         printk
1493                             ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1494                              mite_bytes_in_transit(devpriv->ai_mite_chan),
1495                              devpriv->stc_readw(dev, AI_Status_1_Register));
1496                         retval = -1;
1497                 }
1498         }
1499         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1500
1501         ni_sync_ai_dma(dev);
1502
1503         return retval;
1504 }
1505 #endif
1506 /*
1507    Empties the AI fifo
1508 */
1509 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1510 {
1511         struct ni_private *devpriv = dev->private;
1512         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1513         short data[2];
1514         u32 dl;
1515         short fifo_empty;
1516         int i;
1517
1518         if (boardtype.reg_type == ni_reg_611x) {
1519                 while ((devpriv->stc_readw(dev,
1520                                            AI_Status_1_Register) &
1521                         AI_FIFO_Empty_St) == 0) {
1522                         dl = ni_readl(ADC_FIFO_Data_611x);
1523
1524                         /* This may get the hi/lo data in the wrong order */
1525                         data[0] = (dl >> 16);
1526                         data[1] = (dl & 0xffff);
1527                         cfc_write_array_to_buffer(s, data, sizeof(data));
1528                 }
1529         } else if (boardtype.reg_type == ni_reg_6143) {
1530                 i = 0;
1531                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1532                         dl = ni_readl(AIFIFO_Data_6143);
1533
1534                         /* This may get the hi/lo data in the wrong order */
1535                         data[0] = (dl >> 16);
1536                         data[1] = (dl & 0xffff);
1537                         cfc_write_array_to_buffer(s, data, sizeof(data));
1538                         i += 2;
1539                 }
1540                 /*  Check if stranded sample is present */
1541                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1542                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1543                         dl = ni_readl(AIFIFO_Data_6143);
1544                         data[0] = (dl >> 16) & 0xffff;
1545                         cfc_write_to_buffer(s, data[0]);
1546                 }
1547
1548         } else {
1549                 fifo_empty =
1550                     devpriv->stc_readw(dev,
1551                                        AI_Status_1_Register) & AI_FIFO_Empty_St;
1552                 while (fifo_empty == 0) {
1553                         for (i = 0;
1554                              i <
1555                              sizeof(devpriv->ai_fifo_buffer) /
1556                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1557                                 fifo_empty =
1558                                     devpriv->stc_readw(dev,
1559                                                        AI_Status_1_Register) &
1560                                     AI_FIFO_Empty_St;
1561                                 if (fifo_empty)
1562                                         break;
1563                                 devpriv->ai_fifo_buffer[i] =
1564                                     ni_readw(ADC_FIFO_Data_Register);
1565                         }
1566                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1567                                                   i *
1568                                                   sizeof(devpriv->
1569                                                          ai_fifo_buffer[0]));
1570                 }
1571         }
1572 }
1573
1574 static void get_last_sample_611x(struct comedi_device *dev)
1575 {
1576         struct ni_private *devpriv __maybe_unused = dev->private;
1577         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1578         short data;
1579         u32 dl;
1580
1581         if (boardtype.reg_type != ni_reg_611x)
1582                 return;
1583
1584         /* Check if there's a single sample stuck in the FIFO */
1585         if (ni_readb(XXX_Status) & 0x80) {
1586                 dl = ni_readl(ADC_FIFO_Data_611x);
1587                 data = (dl & 0xffff);
1588                 cfc_write_to_buffer(s, data);
1589         }
1590 }
1591
1592 static void get_last_sample_6143(struct comedi_device *dev)
1593 {
1594         struct ni_private *devpriv __maybe_unused = dev->private;
1595         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1596         short data;
1597         u32 dl;
1598
1599         if (boardtype.reg_type != ni_reg_6143)
1600                 return;
1601
1602         /* Check if there's a single sample stuck in the FIFO */
1603         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1604                 ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1605                 dl = ni_readl(AIFIFO_Data_6143);
1606
1607                 /* This may get the hi/lo data in the wrong order */
1608                 data = (dl >> 16) & 0xffff;
1609                 cfc_write_to_buffer(s, data);
1610         }
1611 }
1612
1613 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1614                         void *data, unsigned int num_bytes,
1615                         unsigned int chan_index)
1616 {
1617         struct ni_private *devpriv = dev->private;
1618         struct comedi_async *async = s->async;
1619         unsigned int i;
1620         unsigned int length = num_bytes / bytes_per_sample(s);
1621         short *array = data;
1622         unsigned int *larray = data;
1623
1624         for (i = 0; i < length; i++) {
1625 #ifdef PCIDMA
1626                 if (s->subdev_flags & SDF_LSAMPL)
1627                         larray[i] = le32_to_cpu(larray[i]);
1628                 else
1629                         array[i] = le16_to_cpu(array[i]);
1630 #endif
1631                 if (s->subdev_flags & SDF_LSAMPL)
1632                         larray[i] += devpriv->ai_offset[chan_index];
1633                 else
1634                         array[i] += devpriv->ai_offset[chan_index];
1635                 chan_index++;
1636                 chan_index %= async->cmd.chanlist_len;
1637         }
1638 }
1639
1640 #ifdef PCIDMA
1641
1642 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1643 {
1644         struct ni_private *devpriv = dev->private;
1645         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1646         int retval;
1647         unsigned long flags;
1648
1649         retval = ni_request_ai_mite_channel(dev);
1650         if (retval)
1651                 return retval;
1652 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1653
1654         /* write alloc the entire buffer */
1655         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1656
1657         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1658         if (devpriv->ai_mite_chan == NULL) {
1659                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1660                 return -EIO;
1661         }
1662
1663         switch (boardtype.reg_type) {
1664         case ni_reg_611x:
1665         case ni_reg_6143:
1666                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1667                 break;
1668         case ni_reg_628x:
1669                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1670                 break;
1671         default:
1672                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1673                 break;
1674         }
1675         /*start the MITE */
1676         mite_dma_arm(devpriv->ai_mite_chan);
1677         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1678
1679         return 0;
1680 }
1681
1682 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1683 {
1684         struct ni_private *devpriv = dev->private;
1685         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1686         int retval;
1687         unsigned long flags;
1688
1689         retval = ni_request_ao_mite_channel(dev);
1690         if (retval)
1691                 return retval;
1692
1693         /* read alloc the entire buffer */
1694         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1695
1696         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1697         if (devpriv->ao_mite_chan) {
1698                 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1699                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1700                 } else {
1701                         /* doing 32 instead of 16 bit wide transfers from memory
1702                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1703                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1704                 }
1705                 mite_dma_arm(devpriv->ao_mite_chan);
1706         } else
1707                 retval = -EIO;
1708         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1709
1710         return retval;
1711 }
1712
1713 #endif /*  PCIDMA */
1714
1715 /*
1716    used for both cancel ioctl and board initialization
1717
1718    this is pretty harsh for a cancel, but it works...
1719  */
1720
1721 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1722 {
1723         struct ni_private *devpriv = dev->private;
1724
1725         ni_release_ai_mite_channel(dev);
1726         /* ai configuration */
1727         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1728                             Joint_Reset_Register);
1729
1730         ni_set_bits(dev, Interrupt_A_Enable_Register,
1731                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1732                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1733                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1734                     AI_FIFO_Interrupt_Enable, 0);
1735
1736         ni_clear_ai_fifo(dev);
1737
1738         if (boardtype.reg_type != ni_reg_6143)
1739                 ni_writeb(0, Misc_Command);
1740
1741         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1742         devpriv->stc_writew(dev,
1743                             AI_Start_Stop | AI_Mode_1_Reserved
1744                             /*| AI_Trigger_Once */ ,
1745                             AI_Mode_1_Register);
1746         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1747         /* generate FIFO interrupts on non-empty */
1748         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1749         if (boardtype.reg_type == ni_reg_611x) {
1750                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1751                                     AI_SOC_Polarity |
1752                                     AI_LOCALMUX_CLK_Pulse_Width,
1753                                     AI_Personal_Register);
1754                 devpriv->stc_writew(dev,
1755                                     AI_SCAN_IN_PROG_Output_Select(3) |
1756                                     AI_EXTMUX_CLK_Output_Select(0) |
1757                                     AI_LOCALMUX_CLK_Output_Select(2) |
1758                                     AI_SC_TC_Output_Select(3) |
1759                                     AI_CONVERT_Output_Select
1760                                     (AI_CONVERT_Output_Enable_High),
1761                                     AI_Output_Control_Register);
1762         } else if (boardtype.reg_type == ni_reg_6143) {
1763                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1764                                     AI_SOC_Polarity |
1765                                     AI_LOCALMUX_CLK_Pulse_Width,
1766                                     AI_Personal_Register);
1767                 devpriv->stc_writew(dev,
1768                                     AI_SCAN_IN_PROG_Output_Select(3) |
1769                                     AI_EXTMUX_CLK_Output_Select(0) |
1770                                     AI_LOCALMUX_CLK_Output_Select(2) |
1771                                     AI_SC_TC_Output_Select(3) |
1772                                     AI_CONVERT_Output_Select
1773                                     (AI_CONVERT_Output_Enable_Low),
1774                                     AI_Output_Control_Register);
1775         } else {
1776                 unsigned ai_output_control_bits;
1777                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1778                                     AI_SOC_Polarity |
1779                                     AI_CONVERT_Pulse_Width |
1780                                     AI_LOCALMUX_CLK_Pulse_Width,
1781                                     AI_Personal_Register);
1782                 ai_output_control_bits =
1783                     AI_SCAN_IN_PROG_Output_Select(3) |
1784                     AI_EXTMUX_CLK_Output_Select(0) |
1785                     AI_LOCALMUX_CLK_Output_Select(2) |
1786                     AI_SC_TC_Output_Select(3);
1787                 if (boardtype.reg_type == ni_reg_622x)
1788                         ai_output_control_bits |=
1789                             AI_CONVERT_Output_Select
1790                             (AI_CONVERT_Output_Enable_High);
1791                 else
1792                         ai_output_control_bits |=
1793                             AI_CONVERT_Output_Select
1794                             (AI_CONVERT_Output_Enable_Low);
1795                 devpriv->stc_writew(dev, ai_output_control_bits,
1796                                     AI_Output_Control_Register);
1797         }
1798         /* the following registers should not be changed, because there
1799          * are no backup registers in devpriv.  If you want to change
1800          * any of these, add a backup register and other appropriate code:
1801          *      AI_Mode_1_Register
1802          *      AI_Mode_3_Register
1803          *      AI_Personal_Register
1804          *      AI_Output_Control_Register
1805          */
1806         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1807
1808         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1809
1810         return 0;
1811 }
1812
1813 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1814 {
1815         unsigned long flags;
1816         int count;
1817
1818         /*  lock to avoid race with interrupt handler */
1819         spin_lock_irqsave(&dev->spinlock, flags);
1820 #ifndef PCIDMA
1821         ni_handle_fifo_dregs(dev);
1822 #else
1823         ni_sync_ai_dma(dev);
1824 #endif
1825         count = s->async->buf_write_count - s->async->buf_read_count;
1826         spin_unlock_irqrestore(&dev->spinlock, flags);
1827
1828         return count;
1829 }
1830
1831 static int ni_ai_insn_read(struct comedi_device *dev,
1832                            struct comedi_subdevice *s, struct comedi_insn *insn,
1833                            unsigned int *data)
1834 {
1835         struct ni_private *devpriv = dev->private;
1836         int i, n;
1837         const unsigned int mask = (1 << boardtype.adbits) - 1;
1838         unsigned signbits;
1839         unsigned short d;
1840         unsigned long dl;
1841
1842         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1843
1844         ni_clear_ai_fifo(dev);
1845
1846         signbits = devpriv->ai_offset[0];
1847         if (boardtype.reg_type == ni_reg_611x) {
1848                 for (n = 0; n < num_adc_stages_611x; n++) {
1849                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1850                                             AI_Command_1_Register);
1851                         udelay(1);
1852                 }
1853                 for (n = 0; n < insn->n; n++) {
1854                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1855                                             AI_Command_1_Register);
1856                         /* The 611x has screwy 32-bit FIFOs. */
1857                         d = 0;
1858                         for (i = 0; i < NI_TIMEOUT; i++) {
1859                                 if (ni_readb(XXX_Status) & 0x80) {
1860                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1861                                             & 0xffff;
1862                                         break;
1863                                 }
1864                                 if (!(devpriv->stc_readw(dev,
1865                                                          AI_Status_1_Register) &
1866                                       AI_FIFO_Empty_St)) {
1867                                         d = ni_readl(ADC_FIFO_Data_611x) &
1868                                             0xffff;
1869                                         break;
1870                                 }
1871                         }
1872                         if (i == NI_TIMEOUT) {
1873                                 printk
1874                                     ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1875                                 return -ETIME;
1876                         }
1877                         d += signbits;
1878                         data[n] = d;
1879                 }
1880         } else if (boardtype.reg_type == ni_reg_6143) {
1881                 for (n = 0; n < insn->n; n++) {
1882                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1883                                             AI_Command_1_Register);
1884
1885                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1886                         dl = 0;
1887                         for (i = 0; i < NI_TIMEOUT; i++) {
1888                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1889                                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1890                                         dl = ni_readl(AIFIFO_Data_6143);
1891                                         break;
1892                                 }
1893                         }
1894                         if (i == NI_TIMEOUT) {
1895                                 printk
1896                                     ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1897                                 return -ETIME;
1898                         }
1899                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1900                 }
1901         } else {
1902                 for (n = 0; n < insn->n; n++) {
1903                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1904                                             AI_Command_1_Register);
1905                         for (i = 0; i < NI_TIMEOUT; i++) {
1906                                 if (!(devpriv->stc_readw(dev,
1907                                                          AI_Status_1_Register) &
1908                                       AI_FIFO_Empty_St))
1909                                         break;
1910                         }
1911                         if (i == NI_TIMEOUT) {
1912                                 printk
1913                                     ("ni_mio_common: timeout in ni_ai_insn_read\n");
1914                                 return -ETIME;
1915                         }
1916                         if (boardtype.reg_type & ni_reg_m_series_mask) {
1917                                 data[n] =
1918                                     ni_readl(M_Offset_AI_FIFO_Data) & mask;
1919                         } else {
1920                                 d = ni_readw(ADC_FIFO_Data_Register);
1921                                 d += signbits;  /* subtle: needs to be short addition */
1922                                 data[n] = d;
1923                         }
1924                 }
1925         }
1926         return insn->n;
1927 }
1928
1929 static void ni_prime_channelgain_list(struct comedi_device *dev)
1930 {
1931         struct ni_private *devpriv = dev->private;
1932         int i;
1933
1934         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1935         for (i = 0; i < NI_TIMEOUT; ++i) {
1936                 if (!(devpriv->stc_readw(dev,
1937                                          AI_Status_1_Register) &
1938                       AI_FIFO_Empty_St)) {
1939                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1940                         return;
1941                 }
1942                 udelay(1);
1943         }
1944         printk("ni_mio_common: timeout loading channel/gain list\n");
1945 }
1946
1947 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1948                                               unsigned int n_chan,
1949                                               unsigned int *list)
1950 {
1951         struct ni_private *devpriv = dev->private;
1952         unsigned int chan, range, aref;
1953         unsigned int i;
1954         unsigned offset;
1955         unsigned int dither;
1956         unsigned range_code;
1957
1958         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1959
1960 /* offset = 1 << (boardtype.adbits - 1); */
1961         if ((list[0] & CR_ALT_SOURCE)) {
1962                 unsigned bypass_bits;
1963                 chan = CR_CHAN(list[0]);
1964                 range = CR_RANGE(list[0]);
1965                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1966                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1967                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1968                 bypass_bits |= chan;
1969                 bypass_bits |=
1970                     (devpriv->ai_calib_source) &
1971                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1972                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1973                      MSeries_AI_Bypass_Mode_Mux_Mask |
1974                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1975                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1976                 if (dither)
1977                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1978                 /*  don't use 2's complement encoding */
1979                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1980                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1981         } else {
1982                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1983         }
1984         offset = 0;
1985         for (i = 0; i < n_chan; i++) {
1986                 unsigned config_bits = 0;
1987                 chan = CR_CHAN(list[i]);
1988                 aref = CR_AREF(list[i]);
1989                 range = CR_RANGE(list[i]);
1990                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1991
1992                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1993                 devpriv->ai_offset[i] = offset;
1994                 switch (aref) {
1995                 case AREF_DIFF:
1996                         config_bits |=
1997                             MSeries_AI_Config_Channel_Type_Differential_Bits;
1998                         break;
1999                 case AREF_COMMON:
2000                         config_bits |=
2001                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2002                         break;
2003                 case AREF_GROUND:
2004                         config_bits |=
2005                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2006                         break;
2007                 case AREF_OTHER:
2008                         break;
2009                 }
2010                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2011                 config_bits |=
2012                     MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
2013                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2014                 if (i == n_chan - 1)
2015                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2016                 if (dither)
2017                         config_bits |= MSeries_AI_Config_Dither_Bit;
2018                 /*  don't use 2's complement encoding */
2019                 config_bits |= MSeries_AI_Config_Polarity_Bit;
2020                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2021         }
2022         ni_prime_channelgain_list(dev);
2023 }
2024
2025 /*
2026  * Notes on the 6110 and 6111:
2027  * These boards a slightly different than the rest of the series, since
2028  * they have multiple A/D converters.
2029  * From the driver side, the configuration memory is a
2030  * little different.
2031  * Configuration Memory Low:
2032  *   bits 15-9: same
2033  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
2034  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
2035  *       1001 gain=0.1 (+/- 50)
2036  *       1010 0.2
2037  *       1011 0.1
2038  *       0001 1
2039  *       0010 2
2040  *       0011 5
2041  *       0100 10
2042  *       0101 20
2043  *       0110 50
2044  * Configuration Memory High:
2045  *   bits 12-14: Channel Type
2046  *       001 for differential
2047  *       000 for calibration
2048  *   bit 11: coupling  (this is not currently handled)
2049  *       1 AC coupling
2050  *       0 DC coupling
2051  *   bits 0-2: channel
2052  *       valid channels are 0-3
2053  */
2054 static void ni_load_channelgain_list(struct comedi_device *dev,
2055                                      unsigned int n_chan, unsigned int *list)
2056 {
2057         struct ni_private *devpriv = dev->private;
2058         unsigned int chan, range, aref;
2059         unsigned int i;
2060         unsigned int hi, lo;
2061         unsigned offset;
2062         unsigned int dither;
2063
2064         if (boardtype.reg_type & ni_reg_m_series_mask) {
2065                 ni_m_series_load_channelgain_list(dev, n_chan, list);
2066                 return;
2067         }
2068         if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
2069             && (boardtype.reg_type != ni_reg_6143)) {
2070                 if (devpriv->changain_state
2071                     && devpriv->changain_spec == list[0]) {
2072                         /*  ready to go. */
2073                         return;
2074                 }
2075                 devpriv->changain_state = 1;
2076                 devpriv->changain_spec = list[0];
2077         } else {
2078                 devpriv->changain_state = 0;
2079         }
2080
2081         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2082
2083         /*  Set up Calibration mode if required */
2084         if (boardtype.reg_type == ni_reg_6143) {
2085                 if ((list[0] & CR_ALT_SOURCE)
2086                     && !devpriv->ai_calib_source_enabled) {
2087                         /*  Strobe Relay enable bit */
2088                         ni_writew(devpriv->ai_calib_source |
2089                                   Calibration_Channel_6143_RelayOn,
2090                                   Calibration_Channel_6143);
2091                         ni_writew(devpriv->ai_calib_source,
2092                                   Calibration_Channel_6143);
2093                         devpriv->ai_calib_source_enabled = 1;
2094                         msleep_interruptible(100);      /*  Allow relays to change */
2095                 } else if (!(list[0] & CR_ALT_SOURCE)
2096                            && devpriv->ai_calib_source_enabled) {
2097                         /*  Strobe Relay disable bit */
2098                         ni_writew(devpriv->ai_calib_source |
2099                                   Calibration_Channel_6143_RelayOff,
2100                                   Calibration_Channel_6143);
2101                         ni_writew(devpriv->ai_calib_source,
2102                                   Calibration_Channel_6143);
2103                         devpriv->ai_calib_source_enabled = 0;
2104                         msleep_interruptible(100);      /*  Allow relays to change */
2105                 }
2106         }
2107
2108         offset = 1 << (boardtype.adbits - 1);
2109         for (i = 0; i < n_chan; i++) {
2110                 if ((boardtype.reg_type != ni_reg_6143)
2111                     && (list[i] & CR_ALT_SOURCE)) {
2112                         chan = devpriv->ai_calib_source;
2113                 } else {
2114                         chan = CR_CHAN(list[i]);
2115                 }
2116                 aref = CR_AREF(list[i]);
2117                 range = CR_RANGE(list[i]);
2118                 dither = ((list[i] & CR_ALT_FILTER) != 0);
2119
2120                 /* fix the external/internal range differences */
2121                 range = ni_gainlkup[boardtype.gainlkup][range];
2122                 if (boardtype.reg_type == ni_reg_611x)
2123                         devpriv->ai_offset[i] = offset;
2124                 else
2125                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2126
2127                 hi = 0;
2128                 if ((list[i] & CR_ALT_SOURCE)) {
2129                         if (boardtype.reg_type == ni_reg_611x)
2130                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2131                                           Calibration_Channel_Select_611x);
2132                 } else {
2133                         if (boardtype.reg_type == ni_reg_611x)
2134                                 aref = AREF_DIFF;
2135                         else if (boardtype.reg_type == ni_reg_6143)
2136                                 aref = AREF_OTHER;
2137                         switch (aref) {
2138                         case AREF_DIFF:
2139                                 hi |= AI_DIFFERENTIAL;
2140                                 break;
2141                         case AREF_COMMON:
2142                                 hi |= AI_COMMON;
2143                                 break;
2144                         case AREF_GROUND:
2145                                 hi |= AI_GROUND;
2146                                 break;
2147                         case AREF_OTHER:
2148                                 break;
2149                         }
2150                 }
2151                 hi |= AI_CONFIG_CHANNEL(chan);
2152
2153                 ni_writew(hi, Configuration_Memory_High);
2154
2155                 if (boardtype.reg_type != ni_reg_6143) {
2156                         lo = range;
2157                         if (i == n_chan - 1)
2158                                 lo |= AI_LAST_CHANNEL;
2159                         if (dither)
2160                                 lo |= AI_DITHER;
2161
2162                         ni_writew(lo, Configuration_Memory_Low);
2163                 }
2164         }
2165
2166         /* prime the channel/gain list */
2167         if ((boardtype.reg_type != ni_reg_611x)
2168             && (boardtype.reg_type != ni_reg_6143)) {
2169                 ni_prime_channelgain_list(dev);
2170         }
2171 }
2172
2173 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2174                           int round_mode)
2175 {
2176         struct ni_private *devpriv = dev->private;
2177         int divider;
2178
2179         switch (round_mode) {
2180         case TRIG_ROUND_NEAREST:
2181         default:
2182                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2183                 break;
2184         case TRIG_ROUND_DOWN:
2185                 divider = (nanosec) / devpriv->clock_ns;
2186                 break;
2187         case TRIG_ROUND_UP:
2188                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2189                 break;
2190         }
2191         return divider - 1;
2192 }
2193
2194 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2195 {
2196         struct ni_private *devpriv = dev->private;
2197
2198         return devpriv->clock_ns * (timer + 1);
2199 }
2200
2201 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2202                                          unsigned num_channels)
2203 {
2204         switch (boardtype.reg_type) {
2205         case ni_reg_611x:
2206         case ni_reg_6143:
2207                 /*  simultaneously-sampled inputs */
2208                 return boardtype.ai_speed;
2209                 break;
2210         default:
2211                 /*  multiplexed inputs */
2212                 break;
2213         }
2214         return boardtype.ai_speed * num_channels;
2215 }
2216
2217 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2218                          struct comedi_cmd *cmd)
2219 {
2220         struct ni_private *devpriv = dev->private;
2221         int err = 0;
2222         int tmp;
2223         unsigned int sources;
2224
2225         /* Step 1 : check if triggers are trivially valid */
2226
2227         if ((cmd->flags & CMDF_WRITE))
2228                 cmd->flags &= ~CMDF_WRITE;
2229
2230         err |= cfc_check_trigger_src(&cmd->start_src,
2231                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2232         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2233                                         TRIG_TIMER | TRIG_EXT);
2234
2235         sources = TRIG_TIMER | TRIG_EXT;
2236         if (boardtype.reg_type == ni_reg_611x ||
2237             boardtype.reg_type == ni_reg_6143)
2238                 sources |= TRIG_NOW;
2239         err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2240
2241         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2242         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2243
2244         if (err)
2245                 return 1;
2246
2247         /* Step 2a : make sure trigger sources are unique */
2248
2249         err |= cfc_check_trigger_is_unique(cmd->start_src);
2250         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2251         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2252         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2253
2254         /* Step 2b : and mutually compatible */
2255
2256         if (err)
2257                 return 2;
2258
2259         /* Step 3: check if arguments are trivially valid */
2260
2261         if (cmd->start_src == TRIG_EXT) {
2262                 /* external trigger */
2263                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2264
2265                 if (tmp > 16)
2266                         tmp = 16;
2267                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2268                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2269         } else {
2270                 /* true for both TRIG_NOW and TRIG_INT */
2271                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2272         }
2273
2274         if (cmd->scan_begin_src == TRIG_TIMER) {
2275                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2276                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2277                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2278                                                  devpriv->clock_ns * 0xffffff);
2279         } else if (cmd->scan_begin_src == TRIG_EXT) {
2280                 /* external trigger */
2281                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2282
2283                 if (tmp > 16)
2284                         tmp = 16;
2285                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2286                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2287         } else {                /* TRIG_OTHER */
2288                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2289         }
2290
2291         if (cmd->convert_src == TRIG_TIMER) {
2292                 if ((boardtype.reg_type == ni_reg_611x)
2293                     || (boardtype.reg_type == ni_reg_6143)) {
2294                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2295                 } else {
2296                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2297                                                          boardtype.ai_speed);
2298                         err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2299                                                 devpriv->clock_ns * 0xffff);
2300                 }
2301         } else if (cmd->convert_src == TRIG_EXT) {
2302                 /* external trigger */
2303                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2304
2305                 if (tmp > 16)
2306                         tmp = 16;
2307                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2308                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2309         } else if (cmd->convert_src == TRIG_NOW) {
2310                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2311         }
2312
2313         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2314
2315         if (cmd->stop_src == TRIG_COUNT) {
2316                 unsigned int max_count = 0x01000000;
2317
2318                 if (boardtype.reg_type == ni_reg_611x)
2319                         max_count -= num_adc_stages_611x;
2320                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2321                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2322         } else {
2323                 /* TRIG_NONE */
2324                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2325         }
2326
2327         if (err)
2328                 return 3;
2329
2330         /* step 4: fix up any arguments */
2331
2332         if (cmd->scan_begin_src == TRIG_TIMER) {
2333                 tmp = cmd->scan_begin_arg;
2334                 cmd->scan_begin_arg =
2335                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2336                                                        cmd->scan_begin_arg,
2337                                                        cmd->
2338                                                        flags &
2339                                                        TRIG_ROUND_MASK));
2340                 if (tmp != cmd->scan_begin_arg)
2341                         err++;
2342         }
2343         if (cmd->convert_src == TRIG_TIMER) {
2344                 if ((boardtype.reg_type != ni_reg_611x)
2345                     && (boardtype.reg_type != ni_reg_6143)) {
2346                         tmp = cmd->convert_arg;
2347                         cmd->convert_arg =
2348                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2349                                                                cmd->convert_arg,
2350                                                                cmd->
2351                                                                flags &
2352                                                                TRIG_ROUND_MASK));
2353                         if (tmp != cmd->convert_arg)
2354                                 err++;
2355                         if (cmd->scan_begin_src == TRIG_TIMER &&
2356                             cmd->scan_begin_arg <
2357                             cmd->convert_arg * cmd->scan_end_arg) {
2358                                 cmd->scan_begin_arg =
2359                                     cmd->convert_arg * cmd->scan_end_arg;
2360                                 err++;
2361                         }
2362                 }
2363         }
2364
2365         if (err)
2366                 return 4;
2367
2368         return 0;
2369 }
2370
2371 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2372 {
2373         struct ni_private *devpriv = dev->private;
2374         const struct comedi_cmd *cmd = &s->async->cmd;
2375         int timer;
2376         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2377         int mode2 = 0;
2378         int start_stop_select = 0;
2379         unsigned int stop_count;
2380         int interrupt_a_enable = 0;
2381
2382         MDPRINTK("ni_ai_cmd\n");
2383         if (dev->irq == 0) {
2384                 comedi_error(dev, "cannot run command without an irq");
2385                 return -EIO;
2386         }
2387         ni_clear_ai_fifo(dev);
2388
2389         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2390
2391         /* start configuration */
2392         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2393
2394         /* disable analog triggering for now, since it
2395          * interferes with the use of pfi0 */
2396         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2397         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2398                             Analog_Trigger_Etc_Register);
2399
2400         switch (cmd->start_src) {
2401         case TRIG_INT:
2402         case TRIG_NOW:
2403                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2404                                     AI_START1_Sync | AI_START1_Edge |
2405                                     AI_START1_Select(0),
2406                                     AI_Trigger_Select_Register);
2407                 break;
2408         case TRIG_EXT:
2409                 {
2410                         int chan = CR_CHAN(cmd->start_arg);
2411                         unsigned int bits = AI_START2_Select(0) |
2412                             AI_START1_Sync | AI_START1_Select(chan + 1);
2413
2414                         if (cmd->start_arg & CR_INVERT)
2415                                 bits |= AI_START1_Polarity;
2416                         if (cmd->start_arg & CR_EDGE)
2417                                 bits |= AI_START1_Edge;
2418                         devpriv->stc_writew(dev, bits,
2419                                             AI_Trigger_Select_Register);
2420                         break;
2421                 }
2422         }
2423
2424         mode2 &= ~AI_Pre_Trigger;
2425         mode2 &= ~AI_SC_Initial_Load_Source;
2426         mode2 &= ~AI_SC_Reload_Mode;
2427         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2428
2429         if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2430             || (boardtype.reg_type == ni_reg_6143)) {
2431                 start_stop_select |= AI_STOP_Polarity;
2432                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2433                 start_stop_select |= AI_STOP_Sync;
2434         } else {
2435                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2436         }
2437         devpriv->stc_writew(dev, start_stop_select,
2438                             AI_START_STOP_Select_Register);
2439
2440         devpriv->ai_cmd2 = 0;
2441         switch (cmd->stop_src) {
2442         case TRIG_COUNT:
2443                 stop_count = cmd->stop_arg - 1;
2444
2445                 if (boardtype.reg_type == ni_reg_611x) {
2446                         /*  have to take 3 stage adc pipeline into account */
2447                         stop_count += num_adc_stages_611x;
2448                 }
2449                 /* stage number of scans */
2450                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2451
2452                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2453                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2454                 /* load SC (Scan Count) */
2455                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2456
2457                 devpriv->ai_continuous = 0;
2458                 if (stop_count == 0) {
2459                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2460                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2461                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2462                         if (cmd->chanlist_len > 1)
2463                                 start_stop_select |=
2464                                     AI_STOP_Polarity | AI_STOP_Edge;
2465                 }
2466                 break;
2467         case TRIG_NONE:
2468                 /* stage number of scans */
2469                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2470
2471                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2472                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2473
2474                 /* load SC (Scan Count) */
2475                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2476
2477                 devpriv->ai_continuous = 1;
2478
2479                 break;
2480         }
2481
2482         switch (cmd->scan_begin_src) {
2483         case TRIG_TIMER:
2484                 /*
2485                    stop bits for non 611x boards
2486                    AI_SI_Special_Trigger_Delay=0
2487                    AI_Pre_Trigger=0
2488                    AI_START_STOP_Select_Register:
2489                    AI_START_Polarity=0 (?)      rising edge
2490                    AI_START_Edge=1              edge triggered
2491                    AI_START_Sync=1 (?)
2492                    AI_START_Select=0            SI_TC
2493                    AI_STOP_Polarity=0           rising edge
2494                    AI_STOP_Edge=0               level
2495                    AI_STOP_Sync=1
2496                    AI_STOP_Select=19            external pin (configuration mem)
2497                  */
2498                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2499                 devpriv->stc_writew(dev, start_stop_select,
2500                                     AI_START_STOP_Select_Register);
2501
2502                 mode2 |= AI_SI_Reload_Mode(0);
2503                 /* AI_SI_Initial_Load_Source=A */
2504                 mode2 &= ~AI_SI_Initial_Load_Source;
2505                 /* mode2 |= AI_SC_Reload_Mode; */
2506                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2507
2508                 /* load SI */
2509                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2510                                        TRIG_ROUND_NEAREST);
2511                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2512                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2513                 break;
2514         case TRIG_EXT:
2515                 if (cmd->scan_begin_arg & CR_EDGE)
2516                         start_stop_select |= AI_START_Edge;
2517                 /* AI_START_Polarity==1 is falling edge */
2518                 if (cmd->scan_begin_arg & CR_INVERT)
2519                         start_stop_select |= AI_START_Polarity;
2520                 if (cmd->scan_begin_src != cmd->convert_src ||
2521                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2522                     (cmd->convert_arg & ~CR_EDGE))
2523                         start_stop_select |= AI_START_Sync;
2524                 start_stop_select |=
2525                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2526                 devpriv->stc_writew(dev, start_stop_select,
2527                                     AI_START_STOP_Select_Register);
2528                 break;
2529         }
2530
2531         switch (cmd->convert_src) {
2532         case TRIG_TIMER:
2533         case TRIG_NOW:
2534                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2535                         timer = 1;
2536                 else
2537                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2538                                                TRIG_ROUND_NEAREST);
2539                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2540                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2541
2542                 /* AI_SI2_Reload_Mode = alternate */
2543                 /* AI_SI2_Initial_Load_Source = A */
2544                 mode2 &= ~AI_SI2_Initial_Load_Source;
2545                 mode2 |= AI_SI2_Reload_Mode;
2546                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2547
2548                 /* AI_SI2_Load */
2549                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2550
2551                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2552                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2553
2554                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2555                 break;
2556         case TRIG_EXT:
2557                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2558                 if ((cmd->convert_arg & CR_INVERT) == 0)
2559                         mode1 |= AI_CONVERT_Source_Polarity;
2560                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2561
2562                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2563                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2564
2565                 break;
2566         }
2567
2568         if (dev->irq) {
2569
2570                 /* interrupt on FIFO, errors, SC_TC */
2571                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2572                     AI_SC_TC_Interrupt_Enable;
2573
2574 #ifndef PCIDMA
2575                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2576 #endif
2577
2578                 if (cmd->flags & TRIG_WAKE_EOS
2579                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2580                         /* wake on end-of-scan */
2581                         devpriv->aimode = AIMODE_SCAN;
2582                 } else {
2583                         devpriv->aimode = AIMODE_HALF_FULL;
2584                 }
2585
2586                 switch (devpriv->aimode) {
2587                 case AIMODE_HALF_FULL:
2588                         /*generate FIFO interrupts and DMA requests on half-full */
2589 #ifdef PCIDMA
2590                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2591                                             AI_Mode_3_Register);
2592 #else
2593                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2594                                             AI_Mode_3_Register);
2595 #endif
2596                         break;
2597                 case AIMODE_SAMPLE:
2598                         /*generate FIFO interrupts on non-empty */
2599                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2600                                             AI_Mode_3_Register);
2601                         break;
2602                 case AIMODE_SCAN:
2603 #ifdef PCIDMA
2604                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2605                                             AI_Mode_3_Register);
2606 #else
2607                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2608                                             AI_Mode_3_Register);
2609 #endif
2610                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2611                         break;
2612                 default:
2613                         break;
2614                 }
2615
2616                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2617
2618                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2619                             interrupt_a_enable, 1);
2620
2621                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2622                          devpriv->int_a_enable_reg);
2623         } else {
2624                 /* interrupt on nothing */
2625                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2626
2627                 /* XXX start polling if necessary */
2628                 MDPRINTK("interrupting on nothing\n");
2629         }
2630
2631         /* end configuration */
2632         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2633
2634         switch (cmd->scan_begin_src) {
2635         case TRIG_TIMER:
2636                 devpriv->stc_writew(dev,
2637                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2638                                     AI_SC_Arm, AI_Command_1_Register);
2639                 break;
2640         case TRIG_EXT:
2641                 /* XXX AI_SI_Arm? */
2642                 devpriv->stc_writew(dev,
2643                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2644                                     AI_SC_Arm, AI_Command_1_Register);
2645                 break;
2646         }
2647
2648 #ifdef PCIDMA
2649         {
2650                 int retval = ni_ai_setup_MITE_dma(dev);
2651                 if (retval)
2652                         return retval;
2653         }
2654         /* mite_dump_regs(devpriv->mite); */
2655 #endif
2656
2657         switch (cmd->start_src) {
2658         case TRIG_NOW:
2659                 /* AI_START1_Pulse */
2660                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2661                                     AI_Command_2_Register);
2662                 s->async->inttrig = NULL;
2663                 break;
2664         case TRIG_EXT:
2665                 s->async->inttrig = NULL;
2666                 break;
2667         case TRIG_INT:
2668                 s->async->inttrig = &ni_ai_inttrig;
2669                 break;
2670         }
2671
2672         MDPRINTK("exit ni_ai_cmd\n");
2673
2674         return 0;
2675 }
2676
2677 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2678                          unsigned int trignum)
2679 {
2680         struct ni_private *devpriv = dev->private;
2681
2682         if (trignum != 0)
2683                 return -EINVAL;
2684
2685         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2686                             AI_Command_2_Register);
2687         s->async->inttrig = NULL;
2688
2689         return 1;
2690 }
2691
2692 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2693                                     struct comedi_subdevice *s,
2694                                     struct comedi_insn *insn,
2695                                     unsigned int *data);
2696
2697 static int ni_ai_insn_config(struct comedi_device *dev,
2698                              struct comedi_subdevice *s,
2699                              struct comedi_insn *insn, unsigned int *data)
2700 {
2701         struct ni_private *devpriv = dev->private;
2702
2703         if (insn->n < 1)
2704                 return -EINVAL;
2705
2706         switch (data[0]) {
2707         case INSN_CONFIG_ANALOG_TRIG:
2708                 return ni_ai_config_analog_trig(dev, s, insn, data);
2709         case INSN_CONFIG_ALT_SOURCE:
2710                 if (boardtype.reg_type & ni_reg_m_series_mask) {
2711                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2712                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2713                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2714                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2715                                 return -EINVAL;
2716                         }
2717                         devpriv->ai_calib_source = data[1];
2718                 } else if (boardtype.reg_type == ni_reg_6143) {
2719                         unsigned int calib_source;
2720
2721                         calib_source = data[1] & 0xf;
2722
2723                         if (calib_source > 0xF)
2724                                 return -EINVAL;
2725
2726                         devpriv->ai_calib_source = calib_source;
2727                         ni_writew(calib_source, Calibration_Channel_6143);
2728                 } else {
2729                         unsigned int calib_source;
2730                         unsigned int calib_source_adjust;
2731
2732                         calib_source = data[1] & 0xf;
2733                         calib_source_adjust = (data[1] >> 4) & 0xff;
2734
2735                         if (calib_source >= 8)
2736                                 return -EINVAL;
2737                         devpriv->ai_calib_source = calib_source;
2738                         if (boardtype.reg_type == ni_reg_611x) {
2739                                 ni_writeb(calib_source_adjust,
2740                                           Cal_Gain_Select_611x);
2741                         }
2742                 }
2743                 return 2;
2744         default:
2745                 break;
2746         }
2747
2748         return -EINVAL;
2749 }
2750
2751 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2752                                     struct comedi_subdevice *s,
2753                                     struct comedi_insn *insn,
2754                                     unsigned int *data)
2755 {
2756         struct ni_private *devpriv = dev->private;
2757         unsigned int a, b, modebits;
2758         int err = 0;
2759
2760         /* data[1] is flags
2761          * data[2] is analog line
2762          * data[3] is set level
2763          * data[4] is reset level */
2764         if (!boardtype.has_analog_trig)
2765                 return -EINVAL;
2766         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2767                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2768                 err++;
2769         }
2770         if (data[2] >= boardtype.n_adchan) {
2771                 data[2] = boardtype.n_adchan - 1;
2772                 err++;
2773         }
2774         if (data[3] > 255) {    /* a */
2775                 data[3] = 255;
2776                 err++;
2777         }
2778         if (data[4] > 255) {    /* b */
2779                 data[4] = 255;
2780                 err++;
2781         }
2782         /*
2783          * 00 ignore
2784          * 01 set
2785          * 10 reset
2786          *
2787          * modes:
2788          *   1 level:                    +b-   +a-
2789          *     high mode                00 00 01 10
2790          *     low mode                 00 00 10 01
2791          *   2 level: (a<b)
2792          *     hysteresis low mode      10 00 00 01
2793          *     hysteresis high mode     01 00 00 10
2794          *     middle mode              10 01 01 10
2795          */
2796
2797         a = data[3];
2798         b = data[4];
2799         modebits = data[1] & 0xff;
2800         if (modebits & 0xf0) {
2801                 /* two level mode */
2802                 if (b < a) {
2803                         /* swap order */
2804                         a = data[4];
2805                         b = data[3];
2806                         modebits =
2807                             ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2808                 }
2809                 devpriv->atrig_low = a;
2810                 devpriv->atrig_high = b;
2811                 switch (modebits) {
2812                 case 0x81:      /* low hysteresis mode */
2813                         devpriv->atrig_mode = 6;
2814                         break;
2815                 case 0x42:      /* high hysteresis mode */
2816                         devpriv->atrig_mode = 3;
2817                         break;
2818                 case 0x96:      /* middle window mode */
2819                         devpriv->atrig_mode = 2;
2820                         break;
2821                 default:
2822                         data[1] &= ~0xff;
2823                         err++;
2824                 }
2825         } else {
2826                 /* one level mode */
2827                 if (b != 0) {
2828                         data[4] = 0;
2829                         err++;
2830                 }
2831                 switch (modebits) {
2832                 case 0x06:      /* high window mode */
2833                         devpriv->atrig_high = a;
2834                         devpriv->atrig_mode = 0;
2835                         break;
2836                 case 0x09:      /* low window mode */
2837                         devpriv->atrig_low = a;
2838                         devpriv->atrig_mode = 1;
2839                         break;
2840                 default:
2841                         data[1] &= ~0xff;
2842                         err++;
2843                 }
2844         }
2845         if (err)
2846                 return -EAGAIN;
2847         return 5;
2848 }
2849
2850 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2851 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2852                         void *data, unsigned int num_bytes,
2853                         unsigned int chan_index)
2854 {
2855         struct comedi_async *async = s->async;
2856         unsigned int range;
2857         unsigned int i;
2858         unsigned int offset;
2859         unsigned int length = num_bytes / sizeof(short);
2860         short *array = data;
2861
2862         offset = 1 << (boardtype.aobits - 1);
2863         for (i = 0; i < length; i++) {
2864                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2865                 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2866                         array[i] -= offset;
2867 #ifdef PCIDMA
2868                 array[i] = cpu_to_le16(array[i]);
2869 #endif
2870                 chan_index++;
2871                 chan_index %= async->cmd.chanlist_len;
2872         }
2873 }
2874
2875 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2876                                           struct comedi_subdevice *s,
2877                                           unsigned int chanspec[],
2878                                           unsigned int n_chans, int timed)
2879 {
2880         struct ni_private *devpriv = dev->private;
2881         unsigned int range;
2882         unsigned int chan;
2883         unsigned int conf;
2884         int i;
2885         int invert = 0;
2886
2887         if (timed) {
2888                 for (i = 0; i < boardtype.n_aochan; ++i) {
2889                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2890                         ni_writeb(devpriv->ao_conf[i],
2891                                   M_Offset_AO_Config_Bank(i));
2892                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2893                 }
2894         }
2895         for (i = 0; i < n_chans; i++) {
2896                 const struct comedi_krange *krange;
2897                 chan = CR_CHAN(chanspec[i]);
2898                 range = CR_RANGE(chanspec[i]);
2899                 krange = s->range_table->range + range;
2900                 invert = 0;
2901                 conf = 0;
2902                 switch (krange->max - krange->min) {
2903                 case 20000000:
2904                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2905                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2906                         break;
2907                 case 10000000:
2908                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2909                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2910                         break;
2911                 case 4000000:
2912                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2913                         ni_writeb(MSeries_Attenuate_x5_Bit,
2914                                   M_Offset_AO_Reference_Attenuation(chan));
2915                         break;
2916                 case 2000000:
2917                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2918                         ni_writeb(MSeries_Attenuate_x5_Bit,
2919                                   M_Offset_AO_Reference_Attenuation(chan));
2920                         break;
2921                 default:
2922                         printk("%s: bug! unhandled ao reference voltage\n",
2923                                __func__);
2924                         break;
2925                 }
2926                 switch (krange->max + krange->min) {
2927                 case 0:
2928                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2929                         break;
2930                 case 10000000:
2931                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2932                         break;
2933                 default:
2934                         printk("%s: bug! unhandled ao offset voltage\n",
2935                                __func__);
2936                         break;
2937                 }
2938                 if (timed)
2939                         conf |= MSeries_AO_Update_Timed_Bit;
2940                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2941                 devpriv->ao_conf[chan] = conf;
2942                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2943         }
2944         return invert;
2945 }
2946
2947 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2948                                      struct comedi_subdevice *s,
2949                                      unsigned int chanspec[],
2950                                      unsigned int n_chans)
2951 {
2952         struct ni_private *devpriv = dev->private;
2953         unsigned int range;
2954         unsigned int chan;
2955         unsigned int conf;
2956         int i;
2957         int invert = 0;
2958
2959         for (i = 0; i < n_chans; i++) {
2960                 chan = CR_CHAN(chanspec[i]);
2961                 range = CR_RANGE(chanspec[i]);
2962                 conf = AO_Channel(chan);
2963
2964                 if (boardtype.ao_unipolar) {
2965                         if ((range & 1) == 0) {
2966                                 conf |= AO_Bipolar;
2967                                 invert = (1 << (boardtype.aobits - 1));
2968                         } else {
2969                                 invert = 0;
2970                         }
2971                         if (range & 2)
2972                                 conf |= AO_Ext_Ref;
2973                 } else {
2974                         conf |= AO_Bipolar;
2975                         invert = (1 << (boardtype.aobits - 1));
2976                 }
2977
2978                 /* not all boards can deglitch, but this shouldn't hurt */
2979                 if (chanspec[i] & CR_DEGLITCH)
2980                         conf |= AO_Deglitch;
2981
2982                 /* analog reference */
2983                 /* AREF_OTHER connects AO ground to AI ground, i think */
2984                 conf |= (CR_AREF(chanspec[i]) ==
2985                          AREF_OTHER) ? AO_Ground_Ref : 0;
2986
2987                 ni_writew(conf, AO_Configuration);
2988                 devpriv->ao_conf[chan] = conf;
2989         }
2990         return invert;
2991 }
2992
2993 static int ni_ao_config_chanlist(struct comedi_device *dev,
2994                                  struct comedi_subdevice *s,
2995                                  unsigned int chanspec[], unsigned int n_chans,
2996                                  int timed)
2997 {
2998         if (boardtype.reg_type & ni_reg_m_series_mask)
2999                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3000                                                       timed);
3001         else
3002                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3003 }
3004
3005 static int ni_ao_insn_read(struct comedi_device *dev,
3006                            struct comedi_subdevice *s, struct comedi_insn *insn,
3007                            unsigned int *data)
3008 {
3009         struct ni_private *devpriv = dev->private;
3010
3011         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3012
3013         return 1;
3014 }
3015
3016 static int ni_ao_insn_write(struct comedi_device *dev,
3017                             struct comedi_subdevice *s,
3018                             struct comedi_insn *insn, unsigned int *data)
3019 {
3020         struct ni_private *devpriv = dev->private;
3021         unsigned int chan = CR_CHAN(insn->chanspec);
3022         unsigned int invert;
3023
3024         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3025
3026         devpriv->ao[chan] = data[0];
3027
3028         if (boardtype.reg_type & ni_reg_m_series_mask) {
3029                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3030         } else
3031                 ni_writew(data[0] ^ invert,
3032                           (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3033
3034         return 1;
3035 }
3036
3037 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3038                                  struct comedi_subdevice *s,
3039                                  struct comedi_insn *insn, unsigned int *data)
3040 {
3041         struct ni_private *devpriv = dev->private;
3042         unsigned int chan = CR_CHAN(insn->chanspec);
3043         unsigned int invert;
3044
3045         ao_win_out(1 << chan, AO_Immediate_671x);
3046         invert = 1 << (boardtype.aobits - 1);
3047
3048         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3049
3050         devpriv->ao[chan] = data[0];
3051         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3052
3053         return 1;
3054 }
3055
3056 static int ni_ao_insn_config(struct comedi_device *dev,
3057                              struct comedi_subdevice *s,
3058                              struct comedi_insn *insn, unsigned int *data)
3059 {
3060         struct ni_private *devpriv = dev->private;
3061
3062         switch (data[0]) {
3063         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3064                 switch (data[1]) {
3065                 case COMEDI_OUTPUT:
3066                         data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short);
3067                         if (devpriv->mite)
3068                                 data[2] += devpriv->mite->fifo_size;
3069                         break;
3070                 case COMEDI_INPUT:
3071                         data[2] = 0;
3072                         break;
3073                 default:
3074                         return -EINVAL;
3075                         break;
3076                 }
3077                 return 0;
3078         default:
3079                 break;
3080         }
3081
3082         return -EINVAL;
3083 }
3084
3085 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3086                          unsigned int trignum)
3087 {
3088         struct ni_private *devpriv = dev->private;
3089         int ret;
3090         int interrupt_b_bits;
3091         int i;
3092         static const int timeout = 1000;
3093
3094         if (trignum != 0)
3095                 return -EINVAL;
3096
3097         /* Null trig at beginning prevent ao start trigger from executing more than
3098            once per command (and doing things like trying to allocate the ao dma channel
3099            multiple times) */
3100         s->async->inttrig = NULL;
3101
3102         ni_set_bits(dev, Interrupt_B_Enable_Register,
3103                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3104         interrupt_b_bits = AO_Error_Interrupt_Enable;
3105 #ifdef PCIDMA
3106         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3107         if (boardtype.reg_type & ni_reg_6xxx_mask)
3108                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3109         ret = ni_ao_setup_MITE_dma(dev);
3110         if (ret)
3111                 return ret;
3112         ret = ni_ao_wait_for_dma_load(dev);
3113         if (ret < 0)
3114                 return ret;
3115 #else
3116         ret = ni_ao_prep_fifo(dev, s);
3117         if (ret == 0)
3118                 return -EPIPE;
3119
3120         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3121 #endif
3122
3123         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3124                             AO_Mode_3_Register);
3125         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3126         /* wait for DACs to be loaded */
3127         for (i = 0; i < timeout; i++) {
3128                 udelay(1);
3129                 if ((devpriv->stc_readw(dev,
3130                                         Joint_Status_2_Register) &
3131                      AO_TMRDACWRs_In_Progress_St) == 0)
3132                         break;
3133         }
3134         if (i == timeout) {
3135                 comedi_error(dev,
3136                              "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3137                 return -EIO;
3138         }
3139         /*  stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3140         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3141                             Interrupt_B_Ack_Register);
3142
3143         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3144
3145         devpriv->stc_writew(dev,
3146                             devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3147                             | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3148                             AO_Command_1_Register);
3149
3150         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3151                             AO_Command_2_Register);
3152
3153         return 0;
3154 }
3155
3156 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3157 {
3158         struct ni_private *devpriv = dev->private;
3159         const struct comedi_cmd *cmd = &s->async->cmd;
3160         int bits;
3161         int i;
3162         unsigned trigvar;
3163
3164         if (dev->irq == 0) {
3165                 comedi_error(dev, "cannot run command without an irq");
3166                 return -EIO;
3167         }
3168
3169         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3170
3171         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3172
3173         if (boardtype.reg_type & ni_reg_6xxx_mask) {
3174                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3175
3176                 bits = 0;
3177                 for (i = 0; i < cmd->chanlist_len; i++) {
3178                         int chan;
3179
3180                         chan = CR_CHAN(cmd->chanlist[i]);
3181                         bits |= 1 << chan;
3182                         ao_win_out(chan, AO_Waveform_Generation_611x);
3183                 }
3184                 ao_win_out(bits, AO_Timed_611x);
3185         }
3186
3187         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3188
3189         if (cmd->stop_src == TRIG_NONE) {
3190                 devpriv->ao_mode1 |= AO_Continuous;
3191                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3192         } else {
3193                 devpriv->ao_mode1 &= ~AO_Continuous;
3194                 devpriv->ao_mode1 |= AO_Trigger_Once;
3195         }
3196         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3197         switch (cmd->start_src) {
3198         case TRIG_INT:
3199         case TRIG_NOW:
3200                 devpriv->ao_trigger_select &=
3201                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3202                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3203                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3204                                     AO_Trigger_Select_Register);
3205                 break;
3206         case TRIG_EXT:
3207                 devpriv->ao_trigger_select =
3208                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3209                 if (cmd->start_arg & CR_INVERT)
3210                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3211                 if (cmd->start_arg & CR_EDGE)
3212                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3213                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3214                                     AO_Trigger_Select_Register);
3215                 break;
3216         default:
3217                 BUG();
3218                 break;
3219         }
3220         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3221         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3222
3223         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3224         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3225         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3226         if (cmd->stop_src == TRIG_NONE) {
3227                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3228         } else {
3229                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3230         }
3231         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3232         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3233         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3234         switch (cmd->stop_src) {
3235         case TRIG_COUNT:
3236                 if (boardtype.reg_type & ni_reg_m_series_mask) {
3237                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3238                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3239                                             AO_UC_Load_A_Register);
3240                         devpriv->stc_writew(dev, AO_UC_Load,
3241                                             AO_Command_1_Register);
3242                 } else {
3243                         devpriv->stc_writel(dev, cmd->stop_arg,
3244                                             AO_UC_Load_A_Register);
3245                         devpriv->stc_writew(dev, AO_UC_Load,
3246                                             AO_Command_1_Register);
3247                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3248                                             AO_UC_Load_A_Register);
3249                 }
3250                 break;
3251         case TRIG_NONE:
3252                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3253                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3254                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3255                 break;
3256         default:
3257                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3258                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3259                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3260         }
3261
3262         devpriv->ao_mode1 &=
3263             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3264               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3265         switch (cmd->scan_begin_src) {
3266         case TRIG_TIMER:
3267                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3268                 trigvar =
3269                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3270                                    TRIG_ROUND_NEAREST);
3271                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3272                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3273                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3274                 break;
3275         case TRIG_EXT:
3276                 devpriv->ao_mode1 |=
3277                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3278                 if (cmd->scan_begin_arg & CR_INVERT)
3279                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3280                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3281                 break;
3282         default:
3283                 BUG();
3284                 break;
3285         }
3286         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3287         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3288         devpriv->ao_mode2 &=
3289             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3290         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3291
3292         if (cmd->scan_end_arg > 1) {
3293                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3294                 devpriv->stc_writew(dev,
3295                                     AO_Number_Of_Channels(cmd->scan_end_arg -
3296                                                           1) |
3297                                     AO_UPDATE_Output_Select
3298                                     (AO_Update_Output_High_Z),
3299                                     AO_Output_Control_Register);
3300         } else {
3301                 unsigned bits;
3302                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3303                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3304                 if (boardtype.
3305                     reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3306                         bits |= AO_Number_Of_Channels(0);
3307                 } else {
3308                         bits |=
3309                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3310                 }
3311                 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3312         }
3313         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3314
3315         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3316                             AO_Command_1_Register);
3317
3318         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3319         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3320
3321         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3322 #ifdef PCIDMA
3323         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3324 #else
3325         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3326 #endif
3327         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3328         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3329
3330         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3331             AO_TMRDACWR_Pulse_Width;
3332         if (boardtype.ao_fifo_depth)
3333                 bits |= AO_FIFO_Enable;
3334         else
3335                 bits |= AO_DMA_PIO_Control;
3336 #if 0
3337         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3338            verified with bus analyzer. */
3339         if (boardtype.reg_type & ni_reg_m_series_mask)
3340                 bits |= AO_Number_Of_DAC_Packages;
3341 #endif
3342         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3343         /*  enable sending of ao dma requests */
3344         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3345
3346         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3347
3348         if (cmd->stop_src == TRIG_COUNT) {
3349                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3350                                     Interrupt_B_Ack_Register);
3351                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3352                             AO_BC_TC_Interrupt_Enable, 1);
3353         }
3354
3355         s->async->inttrig = &ni_ao_inttrig;
3356
3357         return 0;
3358 }
3359
3360 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3361                          struct comedi_cmd *cmd)
3362 {
3363         struct ni_private *devpriv = dev->private;
3364         int err = 0;
3365         int tmp;
3366
3367         /* Step 1 : check if triggers are trivially valid */
3368
3369         if ((cmd->flags & CMDF_WRITE) == 0)
3370                 cmd->flags |= CMDF_WRITE;
3371
3372         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3373         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3374                                         TRIG_TIMER | TRIG_EXT);
3375         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3376         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3377         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3378
3379         if (err)
3380                 return 1;
3381
3382         /* Step 2a : make sure trigger sources are unique */
3383
3384         err |= cfc_check_trigger_is_unique(cmd->start_src);
3385         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3386         err |= cfc_check_trigger_is_unique(cmd->stop_src);
3387
3388         /* Step 2b : and mutually compatible */
3389
3390         if (err)
3391                 return 2;
3392
3393         /* Step 3: check if arguments are trivially valid */
3394
3395         if (cmd->start_src == TRIG_EXT) {
3396                 /* external trigger */
3397                 unsigned int tmp = CR_CHAN(cmd->start_arg);
3398
3399                 if (tmp > 18)
3400                         tmp = 18;
3401                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3402                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3403         } else {
3404                 /* true for both TRIG_NOW and TRIG_INT */
3405                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3406         }
3407
3408         if (cmd->scan_begin_src == TRIG_TIMER) {
3409                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3410                                                  boardtype.ao_speed);
3411                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3412                                                  devpriv->clock_ns * 0xffffff);
3413         }
3414
3415         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3416         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3417
3418         if (cmd->stop_src == TRIG_COUNT)
3419                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3420         else    /* TRIG_NONE */
3421                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3422
3423         if (err)
3424                 return 3;
3425
3426         /* step 4: fix up any arguments */
3427         if (cmd->scan_begin_src == TRIG_TIMER) {
3428                 tmp = cmd->scan_begin_arg;
3429                 cmd->scan_begin_arg =
3430                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3431                                                        cmd->scan_begin_arg,
3432                                                        cmd->
3433                                                        flags &
3434                                                        TRIG_ROUND_MASK));
3435                 if (tmp != cmd->scan_begin_arg)
3436                         err++;
3437         }
3438         if (err)
3439                 return 4;
3440
3441         /* step 5: fix up chanlist */
3442
3443         if (err)
3444                 return 5;
3445
3446         return 0;
3447 }
3448
3449 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3450 {
3451         struct ni_private *devpriv = dev->private;
3452
3453         /* devpriv->ao0p=0x0000; */
3454         /* ni_writew(devpriv->ao0p,AO_Configuration); */
3455
3456         /* devpriv->ao1p=AO_Channel(1); */
3457         /* ni_writew(devpriv->ao1p,AO_Configuration); */
3458
3459         ni_release_ao_mite_channel(dev);
3460
3461         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3462         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3463         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3464         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3465         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3466         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3467                             AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3468         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3469         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3470         devpriv->ao_cmd1 = 0;
3471         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3472         devpriv->ao_cmd2 = 0;
3473         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3474         devpriv->ao_mode1 = 0;
3475         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3476         devpriv->ao_mode2 = 0;
3477         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3478         if (boardtype.reg_type & ni_reg_m_series_mask)
3479                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3480         else
3481                 devpriv->ao_mode3 = 0;
3482         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3483         devpriv->ao_trigger_select = 0;
3484         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3485                             AO_Trigger_Select_Register);
3486         if (boardtype.reg_type & ni_reg_6xxx_mask) {
3487                 unsigned immediate_bits = 0;
3488                 unsigned i;
3489                 for (i = 0; i < s->n_chan; ++i) {
3490                         immediate_bits |= 1 << i;
3491                 }
3492                 ao_win_out(immediate_bits, AO_Immediate_671x);
3493                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3494         }
3495         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3496
3497         return 0;
3498 }
3499
3500 /* digital io */
3501
3502 static int ni_dio_insn_config(struct comedi_device *dev,
3503                               struct comedi_subdevice *s,
3504                               struct comedi_insn *insn, unsigned int *data)
3505 {
3506         struct ni_private *devpriv = dev->private;
3507
3508 #ifdef DEBUG_DIO
3509         printk("ni_dio_insn_config() chan=%d io=%d\n",
3510                CR_CHAN(insn->chanspec), data[0]);
3511 #endif
3512         switch (data[0]) {
3513         case INSN_CONFIG_DIO_OUTPUT:
3514                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3515                 break;
3516         case INSN_CONFIG_DIO_INPUT:
3517                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3518                 break;
3519         case INSN_CONFIG_DIO_QUERY:
3520                 data[1] =
3521                     (s->
3522                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3523                     COMEDI_INPUT;
3524                 return insn->n;
3525                 break;
3526         default:
3527                 return -EINVAL;
3528         }
3529
3530         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3531         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3532         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3533
3534         return 1;
3535 }
3536
3537 static int ni_dio_insn_bits(struct comedi_device *dev,
3538                             struct comedi_subdevice *s,
3539                             struct comedi_insn *insn, unsigned int *data)
3540 {
3541         struct ni_private *devpriv = dev->private;
3542
3543 #ifdef DEBUG_DIO
3544         printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3545 #endif
3546
3547         if (data[0]) {
3548                 /* Perform check to make sure we're not using the
3549                    serial part of the dio */
3550                 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3551                     && devpriv->serial_interval_ns)
3552                         return -EBUSY;
3553
3554                 s->state &= ~data[0];
3555                 s->state |= (data[0] & data[1]);
3556                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3557                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3558                 devpriv->stc_writew(dev, devpriv->dio_output,
3559                                     DIO_Output_Register);
3560         }
3561         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3562
3563         return insn->n;
3564 }
3565
3566 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3567                                        struct comedi_subdevice *s,
3568                                        struct comedi_insn *insn,
3569                                        unsigned int *data)
3570 {
3571         struct ni_private *devpriv __maybe_unused = dev->private;
3572
3573 #ifdef DEBUG_DIO
3574         printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3575                CR_CHAN(insn->chanspec), data[0]);
3576 #endif
3577         switch (data[0]) {
3578         case INSN_CONFIG_DIO_OUTPUT:
3579                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3580                 break;
3581         case INSN_CONFIG_DIO_INPUT:
3582                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3583                 break;
3584         case INSN_CONFIG_DIO_QUERY:
3585                 data[1] =
3586                     (s->
3587                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3588                     COMEDI_INPUT;
3589                 return insn->n;
3590                 break;
3591         default:
3592                 return -EINVAL;
3593         }
3594
3595         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3596
3597         return 1;
3598 }
3599
3600 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3601                                      struct comedi_subdevice *s,
3602                                      struct comedi_insn *insn,
3603                                      unsigned int *data)
3604 {
3605         struct ni_private *devpriv __maybe_unused = dev->private;
3606
3607 #ifdef DEBUG_DIO
3608         printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3609                data[1]);
3610 #endif
3611
3612         if (data[0]) {
3613                 s->state &= ~data[0];
3614                 s->state |= (data[0] & data[1]);
3615                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3616         }
3617         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3618
3619         return insn->n;
3620 }
3621
3622 static int ni_cdio_cmdtest(struct comedi_device *dev,
3623                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3624 {
3625         int err = 0;
3626         int tmp;
3627         unsigned i;
3628
3629         /* Step 1 : check if triggers are trivially valid */
3630
3631         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3632         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3633         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3634         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3635         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3636
3637         if (err)
3638                 return 1;
3639
3640         /* Step 2a : make sure trigger sources are unique */
3641         /* Step 2b : and mutually compatible */
3642
3643         if (err)
3644                 return 2;
3645
3646         /* Step 3: check if arguments are trivially valid */
3647
3648         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3649
3650         tmp = cmd->scan_begin_arg;
3651         tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3652         if (tmp != cmd->scan_begin_arg)
3653                 err |= -EINVAL;
3654
3655         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3656         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3657         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3658
3659         if (err)
3660                 return 3;
3661
3662         /* step 4: fix up any arguments */
3663
3664         if (err)
3665                 return 4;
3666
3667         /* step 5: check chanlist */
3668
3669         for (i = 0; i < cmd->chanlist_len; ++i) {
3670                 if (cmd->chanlist[i] != i)
3671                         err = 1;
3672         }
3673
3674         if (err)
3675                 return 5;
3676
3677         return 0;
3678 }
3679
3680 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3681 {
3682         struct ni_private *devpriv __maybe_unused = dev->private;
3683         const struct comedi_cmd *cmd = &s->async->cmd;
3684         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3685         int retval;
3686
3687         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3688         switch (cmd->scan_begin_src) {
3689         case TRIG_EXT:
3690                 cdo_mode_bits |=
3691                     CR_CHAN(cmd->scan_begin_arg) &
3692                     CDO_Sample_Source_Select_Mask;
3693                 break;
3694         default:
3695                 BUG();
3696                 break;
3697         }
3698         if (cmd->scan_begin_arg & CR_INVERT)
3699                 cdo_mode_bits |= CDO_Polarity_Bit;
3700         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3701         if (s->io_bits) {
3702                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3703                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3704                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3705         } else {
3706                 comedi_error(dev,
3707                              "attempted to run digital output command with no lines configured as outputs");
3708                 return -EIO;
3709         }
3710         retval = ni_request_cdo_mite_channel(dev);
3711         if (retval < 0) {
3712                 return retval;
3713         }
3714         s->async->inttrig = &ni_cdo_inttrig;
3715         return 0;
3716 }
3717
3718 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3719                           unsigned int trignum)
3720 {
3721 #ifdef PCIDMA
3722         struct ni_private *devpriv = dev->private;
3723         unsigned long flags;
3724 #endif
3725         int retval = 0;
3726         unsigned i;
3727         const unsigned timeout = 1000;
3728
3729         s->async->inttrig = NULL;
3730
3731         /* read alloc the entire buffer */
3732         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3733
3734 #ifdef PCIDMA
3735         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3736         if (devpriv->cdo_mite_chan) {
3737                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3738                 mite_dma_arm(devpriv->cdo_mite_chan);
3739         } else {
3740                 comedi_error(dev, "BUG: no cdo mite channel?");
3741                 retval = -EIO;
3742         }
3743         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3744         if (retval < 0)
3745                 return retval;
3746 #endif
3747 /*
3748 * XXX not sure what interrupt C group does
3749 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3750 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3751 */
3752         for (i = 0; i < timeout; ++i) {
3753                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3754                         break;
3755                 udelay(10);
3756         }
3757         if (i == timeout) {
3758                 comedi_error(dev, "dma failed to fill cdo fifo!");
3759                 ni_cdio_cancel(dev, s);
3760                 return -EIO;
3761         }
3762         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3763                   CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3764                   M_Offset_CDIO_Command);
3765         return retval;
3766 }
3767
3768 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3769 {
3770         struct ni_private *devpriv __maybe_unused = dev->private;
3771
3772         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3773                   CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3774                   CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3775                   M_Offset_CDIO_Command);
3776 /*
3777 * XXX not sure what interrupt C group does ni_writeb(0,
3778 * M_Offset_Interrupt_C_Enable);
3779 */
3780         ni_writel(0, M_Offset_CDO_Mask_Enable);
3781         ni_release_cdo_mite_channel(dev);
3782         return 0;
3783 }
3784
3785 static void handle_cdio_interrupt(struct comedi_device *dev)
3786 {
3787         struct ni_private *devpriv __maybe_unused = dev->private;
3788         unsigned cdio_status;
3789         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3790 #ifdef PCIDMA
3791         unsigned long flags;
3792 #endif
3793
3794         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3795                 return;
3796         }
3797 #ifdef PCIDMA
3798         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3799         if (devpriv->cdo_mite_chan) {
3800                 unsigned cdo_mite_status =
3801                     mite_get_status(devpriv->cdo_mite_chan);
3802                 if (cdo_mite_status & CHSR_LINKC) {
3803                         writel(CHOR_CLRLC,
3804                                devpriv->mite->mite_io_addr +
3805                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3806                 }
3807                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3808         }
3809         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3810 #endif
3811
3812         cdio_status = ni_readl(M_Offset_CDIO_Status);
3813         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3814 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3815                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      /*  XXX just guessing this is needed and does something useful */
3816                 s->async->events |= COMEDI_CB_OVERFLOW;
3817         }
3818         if (cdio_status & CDO_FIFO_Empty_Bit) {
3819 /* printk("cdio fifo empty\n"); */
3820                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3821                           M_Offset_CDIO_Command);
3822 /* s->async->events |= COMEDI_CB_EOA; */
3823         }
3824         ni_event(dev, s);
3825 }
3826
3827 static int ni_serial_insn_config(struct comedi_device *dev,
3828                                  struct comedi_subdevice *s,
3829                                  struct comedi_insn *insn, unsigned int *data)
3830 {
3831         struct ni_private *devpriv = dev->private;
3832         int err = insn->n;
3833         unsigned char byte_out, byte_in = 0;
3834
3835         if (insn->n != 2)
3836                 return -EINVAL;
3837
3838         switch (data[0]) {
3839         case INSN_CONFIG_SERIAL_CLOCK:
3840
3841 #ifdef DEBUG_DIO
3842                 printk("SPI serial clock Config cd\n", data[1]);
3843 #endif
3844                 devpriv->serial_hw_mode = 1;
3845                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3846
3847                 if (data[1] == SERIAL_DISABLED) {
3848                         devpriv->serial_hw_mode = 0;
3849                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3850                                                   DIO_Software_Serial_Control);
3851                         data[1] = SERIAL_DISABLED;
3852                         devpriv->serial_interval_ns = data[1];
3853                 } else if (data[1] <= SERIAL_600NS) {
3854                         /* Warning: this clock speed is too fast to reliably
3855                            control SCXI. */
3856                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3857                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3858                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3859                         data[1] = SERIAL_600NS;
3860                         devpriv->serial_interval_ns = data[1];
3861                 } else if (data[1] <= SERIAL_1_2US) {
3862                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3863                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3864                             DIO_Serial_Out_Divide_By_2;
3865                         data[1] = SERIAL_1_2US;
3866                         devpriv->serial_interval_ns = data[1];
3867                 } else if (data[1] <= SERIAL_10US) {
3868                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3869                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3870                             DIO_Serial_Out_Divide_By_2;
3871                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3872                            600ns/1.2us. If you turn divide_by_2 off with the
3873                            slow clock, you will still get 10us, except then
3874                            all your delays are wrong. */
3875                         data[1] = SERIAL_10US;
3876                         devpriv->serial_interval_ns = data[1];
3877                 } else {
3878                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3879                                                   DIO_Software_Serial_Control);
3880                         devpriv->serial_hw_mode = 0;
3881                         data[1] = (data[1] / 1000) * 1000;
3882                         devpriv->serial_interval_ns = data[1];
3883                 }
3884
3885                 devpriv->stc_writew(dev, devpriv->dio_control,
3886                                     DIO_Control_Register);
3887                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3888                                     Clock_and_FOUT_Register);
3889                 return 1;
3890
3891                 break;
3892
3893         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3894
3895                 if (devpriv->serial_interval_ns == 0) {
3896                         return -EINVAL;
3897                 }
3898
3899                 byte_out = data[1] & 0xFF;
3900
3901                 if (devpriv->serial_hw_mode) {
3902                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3903                                                       &byte_in);
3904                 } else if (devpriv->serial_interval_ns > 0) {
3905                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3906                                                       &byte_in);
3907                 } else {
3908                         printk("ni_serial_insn_config: serial disabled!\n");
3909                         return -EINVAL;
3910                 }
3911                 if (err < 0)
3912                         return err;
3913                 data[1] = byte_in & 0xFF;
3914                 return insn->n;
3915
3916                 break;
3917         default:
3918                 return -EINVAL;
3919         }
3920
3921 }
3922
3923 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3924                                    struct comedi_subdevice *s,
3925                                    unsigned char data_out,
3926                                    unsigned char *data_in)
3927 {
3928         struct ni_private *devpriv = dev->private;
3929         unsigned int status1;
3930         int err = 0, count = 20;
3931
3932 #ifdef DEBUG_DIO
3933         printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3934 #endif
3935
3936         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3937         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3938         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3939
3940         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3941         if (status1 & DIO_Serial_IO_In_Progress_St) {
3942                 err = -EBUSY;
3943                 goto Error;
3944         }
3945
3946         devpriv->dio_control |= DIO_HW_Serial_Start;
3947         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3948         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3949
3950         /* Wait until STC says we're done, but don't loop infinitely. */
3951         while ((status1 =
3952                 devpriv->stc_readw(dev,
3953                                    Joint_Status_1_Register)) &
3954                DIO_Serial_IO_In_Progress_St) {
3955                 /* Delay one bit per loop */
3956                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3957                 if (--count < 0) {
3958                         printk
3959                             ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3960                         err = -ETIME;
3961                         goto Error;
3962                 }
3963         }
3964
3965         /* Delay for last bit. This delay is absolutely necessary, because
3966            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3967         udelay((devpriv->serial_interval_ns + 999) / 1000);
3968
3969         if (data_in != NULL) {
3970                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3971 #ifdef DEBUG_DIO
3972                 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3973 #endif
3974         }
3975
3976 Error:
3977         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3978
3979         return err;
3980 }
3981
3982 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3983                                    struct comedi_subdevice *s,
3984                                    unsigned char data_out,
3985                                    unsigned char *data_in)
3986 {
3987         struct ni_private *devpriv = dev->private;
3988         unsigned char mask, input = 0;
3989
3990 #ifdef DEBUG_DIO
3991         printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3992 #endif
3993
3994         /* Wait for one bit before transfer */
3995         udelay((devpriv->serial_interval_ns + 999) / 1000);
3996
3997         for (mask = 0x80; mask; mask >>= 1) {
3998                 /* Output current bit; note that we cannot touch s->state
3999                    because it is a per-subdevice field, and serial is
4000                    a separate subdevice from DIO. */
4001                 devpriv->dio_output &= ~DIO_SDOUT;
4002                 if (data_out & mask) {
4003                         devpriv->dio_output |= DIO_SDOUT;
4004                 }
4005                 devpriv->stc_writew(dev, devpriv->dio_output,
4006                                     DIO_Output_Register);
4007
4008                 /* Assert SDCLK (active low, inverted), wait for half of
4009                    the delay, deassert SDCLK, and wait for the other half. */
4010                 devpriv->dio_control |= DIO_Software_Serial_Control;
4011                 devpriv->stc_writew(dev, devpriv->dio_control,
4012                                     DIO_Control_Register);
4013
4014                 udelay((devpriv->serial_interval_ns + 999) / 2000);
4015
4016                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4017                 devpriv->stc_writew(dev, devpriv->dio_control,
4018                                     DIO_Control_Register);
4019
4020                 udelay((devpriv->serial_interval_ns + 999) / 2000);
4021
4022                 /* Input current bit */
4023                 if (devpriv->stc_readw(dev,
4024                                        DIO_Parallel_Input_Register) & DIO_SDIN)
4025                 {
4026 /*                      printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4027                         input |= mask;
4028                 }
4029         }
4030 #ifdef DEBUG_DIO
4031         printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4032 #endif
4033         if (data_in)
4034                 *data_in = input;
4035
4036         return 0;
4037 }
4038
4039 static void mio_common_detach(struct comedi_device *dev)
4040 {
4041         struct ni_private *devpriv = dev->private;
4042         struct comedi_subdevice *s;
4043
4044         if (devpriv) {
4045                 if (devpriv->counter_dev) {
4046                         ni_gpct_device_destroy(devpriv->counter_dev);
4047                 }
4048         }
4049         if (dev->subdevices && boardtype.has_8255) {
4050                 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4051                 subdev_8255_cleanup(dev, s);
4052         }
4053 }
4054
4055 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4056 {
4057         int i;
4058
4059         for (i = 0; i < s->n_chan; i++) {
4060                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4061                                AO_Configuration_2_67xx);
4062         }
4063         ao_win_out(0x0, AO_Later_Single_Point_Updates);
4064 }
4065
4066 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4067 {
4068         unsigned stc_register;
4069         switch (reg) {
4070         case NITIO_G0_Autoincrement_Reg:
4071                 stc_register = G_Autoincrement_Register(0);
4072                 break;
4073         case NITIO_G1_Autoincrement_Reg:
4074                 stc_register = G_Autoincrement_Register(1);
4075                 break;
4076         case NITIO_G0_Command_Reg:
4077                 stc_register = G_Command_Register(0);
4078                 break;
4079         case NITIO_G1_Command_Reg:
4080                 stc_register = G_Command_Register(1);
4081                 break;
4082         case NITIO_G0_HW_Save_Reg:
4083                 stc_register = G_HW_Save_Register(0);
4084                 break;
4085         case NITIO_G1_HW_Save_Reg:
4086                 stc_register = G_HW_Save_Register(1);
4087                 break;
4088         case NITIO_G0_SW_Save_Reg:
4089                 stc_register = G_Save_Register(0);
4090                 break;
4091         case NITIO_G1_SW_Save_Reg:
4092                 stc_register = G_Save_Register(1);
4093                 break;
4094         case NITIO_G0_Mode_Reg:
4095                 stc_register = G_Mode_Register(0);
4096                 break;
4097         case NITIO_G1_Mode_Reg:
4098                 stc_register = G_Mode_Register(1);
4099                 break;
4100         case NITIO_G0_LoadA_Reg:
4101                 stc_register = G_Load_A_Register(0);
4102                 break;
4103         case NITIO_G1_LoadA_Reg:
4104                 stc_register = G_Load_A_Register(1);
4105                 break;
4106         case NITIO_G0_LoadB_Reg:
4107                 stc_register = G_Load_B_Register(0);
4108                 break;
4109         case NITIO_G1_LoadB_Reg:
4110                 stc_register = G_Load_B_Register(1);
4111                 break;
4112         case NITIO_G0_Input_Select_Reg:
4113                 stc_register = G_Input_Select_Register(0);
4114                 break;
4115         case NITIO_G1_Input_Select_Reg:
4116                 stc_register = G_Input_Select_Register(1);
4117                 break;
4118         case NITIO_G01_Status_Reg:
4119                 stc_register = G_Status_Register;
4120                 break;
4121         case NITIO_G01_Joint_Reset_Reg:
4122                 stc_register = Joint_Reset_Register;
4123                 break;
4124         case NITIO_G01_Joint_Status1_Reg:
4125                 stc_register = Joint_Status_1_Register;
4126                 break;
4127         case NITIO_G01_Joint_Status2_Reg:
4128                 stc_register = Joint_Status_2_Register;
4129                 break;
4130         case NITIO_G0_Interrupt_Acknowledge_Reg:
4131                 stc_register = Interrupt_A_Ack_Register;
4132                 break;
4133         case NITIO_G1_Interrupt_Acknowledge_Reg:
4134                 stc_register = Interrupt_B_Ack_Register;
4135                 break;
4136         case NITIO_G0_Status_Reg:
4137                 stc_register = AI_Status_1_Register;
4138                 break;
4139         case NITIO_G1_Status_Reg:
4140                 stc_register = AO_Status_1_Register;
4141                 break;
4142         case NITIO_G0_Interrupt_Enable_Reg:
4143                 stc_register = Interrupt_A_Enable_Register;
4144                 break;
4145         case NITIO_G1_Interrupt_Enable_Reg:
4146                 stc_register = Interrupt_B_Enable_Register;
4147                 break;
4148         default:
4149                 printk("%s: unhandled register 0x%x in switch.\n",
4150                        __func__, reg);
4151                 BUG();
4152                 return 0;
4153                 break;
4154         }
4155         return stc_register;
4156 }
4157
4158 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4159                                    enum ni_gpct_register reg)
4160 {
4161         struct comedi_device *dev = counter->counter_dev->dev;
4162         struct ni_private *devpriv = dev->private;
4163         unsigned stc_register;
4164         /* bits in the join reset register which are relevant to counters */
4165         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4166         static const unsigned gpct_interrupt_a_enable_mask =
4167             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4168         static const unsigned gpct_interrupt_b_enable_mask =
4169             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4170
4171         switch (reg) {
4172                 /* m-series-only registers */
4173         case NITIO_G0_Counting_Mode_Reg:
4174                 ni_writew(bits, M_Offset_G0_Counting_Mode);
4175                 break;
4176         case NITIO_G1_Counting_Mode_Reg:
4177                 ni_writew(bits, M_Offset_G1_Counting_Mode);
4178                 break;
4179         case NITIO_G0_Second_Gate_Reg:
4180                 ni_writew(bits, M_Offset_G0_Second_Gate);
4181                 break;
4182         case NITIO_G1_Second_Gate_Reg:
4183                 ni_writew(bits, M_Offset_G1_Second_Gate);
4184                 break;
4185         case NITIO_G0_DMA_Config_Reg:
4186                 ni_writew(bits, M_Offset_G0_DMA_Config);
4187                 break;
4188         case NITIO_G1_DMA_Config_Reg:
4189                 ni_writew(bits, M_Offset_G1_DMA_Config);
4190                 break;
4191         case NITIO_G0_ABZ_Reg:
4192                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4193                 break;
4194         case NITIO_G1_ABZ_Reg:
4195                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4196                 break;
4197
4198                 /* 32 bit registers */
4199         case NITIO_G0_LoadA_Reg:
4200         case NITIO_G1_LoadA_Reg:
4201         case NITIO_G0_LoadB_Reg:
4202         case NITIO_G1_LoadB_Reg:
4203                 stc_register = ni_gpct_to_stc_register(reg);
4204                 devpriv->stc_writel(dev, bits, stc_register);
4205                 break;
4206
4207                 /* 16 bit registers */
4208         case NITIO_G0_Interrupt_Enable_Reg:
4209                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4210                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4211                                 gpct_interrupt_a_enable_mask, bits);
4212                 break;
4213         case NITIO_G1_Interrupt_Enable_Reg:
4214                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4215                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4216                                 gpct_interrupt_b_enable_mask, bits);
4217                 break;
4218         case NITIO_G01_Joint_Reset_Reg:
4219                 BUG_ON(bits & ~gpct_joint_reset_mask);
4220                 /* fall-through */
4221         default:
4222                 stc_register = ni_gpct_to_stc_register(reg);
4223                 devpriv->stc_writew(dev, bits, stc_register);
4224         }
4225 }
4226
4227 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4228                                       enum ni_gpct_register reg)
4229 {
4230         struct comedi_device *dev = counter->counter_dev->dev;
4231         struct ni_private *devpriv = dev->private;
4232         unsigned stc_register;
4233
4234         switch (reg) {
4235                 /* m-series only registers */
4236         case NITIO_G0_DMA_Status_Reg:
4237                 return ni_readw(M_Offset_G0_DMA_Status);
4238                 break;
4239         case NITIO_G1_DMA_Status_Reg:
4240                 return ni_readw(M_Offset_G1_DMA_Status);
4241                 break;
4242
4243                 /* 32 bit registers */
4244         case NITIO_G0_HW_Save_Reg:
4245         case NITIO_G1_HW_Save_Reg:
4246         case NITIO_G0_SW_Save_Reg:
4247         case NITIO_G1_SW_Save_Reg:
4248                 stc_register = ni_gpct_to_stc_register(reg);
4249                 return devpriv->stc_readl(dev, stc_register);
4250                 break;
4251
4252                 /* 16 bit registers */
4253         default:
4254                 stc_register = ni_gpct_to_stc_register(reg);
4255                 return devpriv->stc_readw(dev, stc_register);
4256                 break;
4257         }
4258         return 0;
4259 }
4260
4261 static int ni_freq_out_insn_read(struct comedi_device *dev,
4262                                  struct comedi_subdevice *s,
4263                                  struct comedi_insn *insn, unsigned int *data)
4264 {
4265         struct ni_private *devpriv = dev->private;
4266
4267         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4268         return 1;
4269 }
4270
4271 static int ni_freq_out_insn_write(struct comedi_device *dev,
4272                                   struct comedi_subdevice *s,
4273                                   struct comedi_insn *insn, unsigned int *data)
4274 {
4275         struct ni_private *devpriv = dev->private;
4276
4277         devpriv->clock_and_fout &= ~FOUT_Enable;
4278         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4279                             Clock_and_FOUT_Register);
4280         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4281         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4282         devpriv->clock_and_fout |= FOUT_Enable;
4283         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4284                             Clock_and_FOUT_Register);
4285         return insn->n;
4286 }
4287
4288 static int ni_set_freq_out_clock(struct comedi_device *dev,
4289                                  unsigned int clock_source)
4290 {
4291         struct ni_private *devpriv = dev->private;
4292
4293         switch (clock_source) {
4294         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4295                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4296                 break;
4297         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4298                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4299                 break;
4300         default:
4301                 return -EINVAL;
4302         }
4303         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4304                             Clock_and_FOUT_Register);
4305         return 3;
4306 }
4307
4308 static void ni_get_freq_out_clock(struct comedi_device *dev,
4309                                   unsigned int *clock_source,
4310                                   unsigned int *clock_period_ns)
4311 {
4312         struct ni_private *devpriv = dev->private;
4313
4314         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4315                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4316                 *clock_period_ns = TIMEBASE_2_NS;
4317         } else {
4318                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4319                 *clock_period_ns = TIMEBASE_1_NS * 2;
4320         }
4321 }
4322
4323 static int ni_freq_out_insn_config(struct comedi_device *dev,
4324                                    struct comedi_subdevice *s,
4325                                    struct comedi_insn *insn, unsigned int *data)
4326 {
4327         switch (data[0]) {
4328         case INSN_CONFIG_SET_CLOCK_SRC:
4329                 return ni_set_freq_out_clock(dev, data[1]);
4330                 break;
4331         case INSN_CONFIG_GET_CLOCK_SRC:
4332                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4333                 return 3;
4334         default:
4335                 break;
4336         }
4337         return -EINVAL;
4338 }
4339
4340 static int ni_alloc_private(struct comedi_device *dev)
4341 {
4342         struct ni_private *devpriv;
4343
4344         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4345         if (!devpriv)
4346                 return -ENOMEM;
4347         dev->private = devpriv;
4348
4349         spin_lock_init(&devpriv->window_lock);
4350         spin_lock_init(&devpriv->soft_reg_copy_lock);
4351         spin_lock_init(&devpriv->mite_channel_lock);
4352
4353         return 0;
4354 };
4355
4356 static int ni_E_init(struct comedi_device *dev)
4357 {
4358         struct ni_private *devpriv = dev->private;
4359         struct comedi_subdevice *s;
4360         unsigned j;
4361         enum ni_gpct_variant counter_variant;
4362         int ret;
4363
4364         if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4365                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4366                 return -EINVAL;
4367         }
4368
4369         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4370         if (ret)
4371                 return ret;
4372
4373         /* analog input subdevice */
4374
4375         s = &dev->subdevices[NI_AI_SUBDEV];
4376         dev->read_subdev = s;
4377         if (boardtype.n_adchan) {
4378                 s->type = COMEDI_SUBD_AI;
4379                 s->subdev_flags =
4380                     SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4381                 if (boardtype.reg_type != ni_reg_611x)
4382                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4383                 if (boardtype.adbits > 16)
4384                         s->subdev_flags |= SDF_LSAMPL;
4385                 if (boardtype.reg_type & ni_reg_m_series_mask)
4386                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4387                 s->n_chan = boardtype.n_adchan;
4388                 s->len_chanlist = 512;
4389                 s->maxdata = (1 << boardtype.adbits) - 1;
4390                 s->range_table = ni_range_lkup[boardtype.gainlkup];
4391                 s->insn_read = &ni_ai_insn_read;
4392                 s->insn_config = &ni_ai_insn_config;
4393                 s->do_cmdtest = &ni_ai_cmdtest;
4394                 s->do_cmd = &ni_ai_cmd;
4395                 s->cancel = &ni_ai_reset;
4396                 s->poll = &ni_ai_poll;
4397                 s->munge = &ni_ai_munge;
4398 #ifdef PCIDMA
4399                 s->async_dma_dir = DMA_FROM_DEVICE;
4400 #endif
4401         } else {
4402                 s->type = COMEDI_SUBD_UNUSED;
4403         }
4404
4405         /* analog output subdevice */
4406
4407         s = &dev->subdevices[NI_AO_SUBDEV];
4408         if (boardtype.n_aochan) {
4409                 s->type = COMEDI_SUBD_AO;
4410                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4411                 if (boardtype.reg_type & ni_reg_m_series_mask)
4412                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4413                 s->n_chan = boardtype.n_aochan;
4414                 s->maxdata = (1 << boardtype.aobits) - 1;
4415                 s->range_table = boardtype.ao_range_table;
4416                 s->insn_read = &ni_ao_insn_read;
4417                 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4418                         s->insn_write = &ni_ao_insn_write_671x;
4419                 } else {
4420                         s->insn_write = &ni_ao_insn_write;
4421                 }
4422                 s->insn_config = &ni_ao_insn_config;
4423 #ifdef PCIDMA
4424                 if (boardtype.n_aochan) {
4425                         s->async_dma_dir = DMA_TO_DEVICE;
4426 #else
4427                 if (boardtype.ao_fifo_depth) {
4428 #endif
4429                         dev->write_subdev = s;
4430                         s->subdev_flags |= SDF_CMD_WRITE;
4431                         s->do_cmd = &ni_ao_cmd;
4432                         s->do_cmdtest = &ni_ao_cmdtest;
4433                         s->len_chanlist = boardtype.n_aochan;
4434                         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4435                                 s->munge = ni_ao_munge;
4436                 }
4437                 s->cancel = &ni_ao_reset;
4438         } else {
4439                 s->type = COMEDI_SUBD_UNUSED;
4440         }
4441         if ((boardtype.reg_type & ni_reg_67xx_mask))
4442                 init_ao_67xx(dev, s);
4443
4444         /* digital i/o subdevice */
4445
4446         s = &dev->subdevices[NI_DIO_SUBDEV];
4447         s->type = COMEDI_SUBD_DIO;
4448         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4449         s->maxdata = 1;
4450         s->io_bits = 0;         /* all bits input */
4451         s->range_table = &range_digital;
4452         s->n_chan = boardtype.num_p0_dio_channels;
4453         if (boardtype.reg_type & ni_reg_m_series_mask) {
4454                 s->subdev_flags |=
4455                     SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4456                 s->insn_bits = &ni_m_series_dio_insn_bits;
4457                 s->insn_config = &ni_m_series_dio_insn_config;
4458                 s->do_cmd = &ni_cdio_cmd;
4459                 s->do_cmdtest = &ni_cdio_cmdtest;
4460                 s->cancel = &ni_cdio_cancel;
4461                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4462                 s->len_chanlist = s->n_chan;
4463
4464                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4465                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4466         } else {
4467                 s->insn_bits = &ni_dio_insn_bits;
4468                 s->insn_config = &ni_dio_insn_config;
4469                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4470                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4471         }
4472
4473         /* 8255 device */
4474         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4475         if (boardtype.has_8255) {
4476                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4477         } else {
4478                 s->type = COMEDI_SUBD_UNUSED;
4479         }
4480
4481         /* formerly general purpose counter/timer device, but no longer used */
4482         s = &dev->subdevices[NI_UNUSED_SUBDEV];
4483         s->type = COMEDI_SUBD_UNUSED;
4484
4485         /* calibration subdevice -- ai and ao */
4486         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4487         s->type = COMEDI_SUBD_CALIB;
4488         if (boardtype.reg_type & ni_reg_m_series_mask) {
4489                 /*  internal PWM analog output used for AI nonlinearity calibration */
4490                 s->subdev_flags = SDF_INTERNAL;
4491                 s->insn_config = &ni_m_series_pwm_config;
4492                 s->n_chan = 1;
4493                 s->maxdata = 0;
4494                 ni_writel(0x0, M_Offset_Cal_PWM);
4495         } else if (boardtype.reg_type == ni_reg_6143) {
4496                 /*  internal PWM analog output used for AI nonlinearity calibration */
4497                 s->subdev_flags = SDF_INTERNAL;
4498                 s->insn_config = &ni_6143_pwm_config;
4499                 s->n_chan = 1;
4500                 s->maxdata = 0;
4501         } else {
4502                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4503                 s->insn_read = &ni_calib_insn_read;
4504                 s->insn_write = &ni_calib_insn_write;
4505                 caldac_setup(dev, s);
4506         }
4507
4508         /* EEPROM */
4509         s = &dev->subdevices[NI_EEPROM_SUBDEV];
4510         s->type = COMEDI_SUBD_MEMORY;
4511         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4512         s->maxdata = 0xff;
4513         if (boardtype.reg_type & ni_reg_m_series_mask) {
4514                 s->n_chan = M_SERIES_EEPROM_SIZE;
4515                 s->insn_read = &ni_m_series_eeprom_insn_read;
4516         } else {
4517                 s->n_chan = 512;
4518                 s->insn_read = &ni_eeprom_insn_read;
4519         }
4520
4521         /* PFI */
4522         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4523         s->type = COMEDI_SUBD_DIO;
4524         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4525         if (boardtype.reg_type & ni_reg_m_series_mask) {
4526                 unsigned i;
4527                 s->n_chan = 16;
4528                 ni_writew(s->state, M_Offset_PFI_DO);
4529                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4530                         ni_writew(devpriv->pfi_output_select_reg[i],
4531                                   M_Offset_PFI_Output_Select(i + 1));
4532                 }
4533         } else {
4534                 s->n_chan = 10;
4535         }
4536         s->maxdata = 1;
4537         if (boardtype.reg_type & ni_reg_m_series_mask) {
4538                 s->insn_bits = &ni_pfi_insn_bits;
4539         }
4540         s->insn_config = &ni_pfi_insn_config;
4541         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4542
4543         /* cs5529 calibration adc */
4544         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4545         if (boardtype.reg_type & ni_reg_67xx_mask) {
4546                 s->type = COMEDI_SUBD_AI;
4547                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4548                 /*  one channel for each analog output channel */
4549                 s->n_chan = boardtype.n_aochan;
4550                 s->maxdata = (1 << 16) - 1;
4551                 s->range_table = &range_unknown;        /* XXX */
4552                 s->insn_read = cs5529_ai_insn_read;
4553                 s->insn_config = NULL;
4554                 init_cs5529(dev);
4555         } else {
4556                 s->type = COMEDI_SUBD_UNUSED;
4557         }
4558
4559         /* Serial */
4560         s = &dev->subdevices[NI_SERIAL_SUBDEV];
4561         s->type = COMEDI_SUBD_SERIAL;
4562         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4563         s->n_chan = 1;
4564         s->maxdata = 0xff;
4565         s->insn_config = ni_serial_insn_config;
4566         devpriv->serial_interval_ns = 0;
4567         devpriv->serial_hw_mode = 0;
4568
4569         /* RTSI */
4570         s = &dev->subdevices[NI_RTSI_SUBDEV];
4571         s->type = COMEDI_SUBD_DIO;
4572         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4573         s->n_chan = 8;
4574         s->maxdata = 1;
4575         s->insn_bits = ni_rtsi_insn_bits;
4576         s->insn_config = ni_rtsi_insn_config;
4577         ni_rtsi_init(dev);
4578
4579         if (boardtype.reg_type & ni_reg_m_series_mask) {
4580                 counter_variant = ni_gpct_variant_m_series;
4581         } else {
4582                 counter_variant = ni_gpct_variant_e_series;
4583         }
4584         devpriv->counter_dev = ni_gpct_device_construct(dev,
4585                                                         &ni_gpct_write_register,
4586                                                         &ni_gpct_read_register,
4587                                                         counter_variant,
4588                                                         NUM_GPCT);
4589         /* General purpose counters */
4590         for (j = 0; j < NUM_GPCT; ++j) {
4591                 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4592                 s->type = COMEDI_SUBD_COUNTER;
4593                 s->subdev_flags =
4594                     SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4595                     /* | SDF_CMD_WRITE */ ;
4596                 s->n_chan = 3;
4597                 if (boardtype.reg_type & ni_reg_m_series_mask)
4598                         s->maxdata = 0xffffffff;
4599                 else
4600                         s->maxdata = 0xffffff;
4601                 s->insn_read = &ni_gpct_insn_read;
4602                 s->insn_write = &ni_gpct_insn_write;
4603                 s->insn_config = &ni_gpct_insn_config;
4604                 s->do_cmd = &ni_gpct_cmd;
4605                 s->len_chanlist = 1;
4606                 s->do_cmdtest = &ni_gpct_cmdtest;
4607                 s->cancel = &ni_gpct_cancel;
4608                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4609                 s->private = &devpriv->counter_dev->counters[j];
4610
4611                 devpriv->counter_dev->counters[j].chip_index = 0;
4612                 devpriv->counter_dev->counters[j].counter_index = j;
4613                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4614         }
4615
4616         /* Frequency output */
4617         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4618         s->type = COMEDI_SUBD_COUNTER;
4619         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4620         s->n_chan = 1;
4621         s->maxdata = 0xf;
4622         s->insn_read = &ni_freq_out_insn_read;
4623         s->insn_write = &ni_freq_out_insn_write;
4624         s->insn_config = &ni_freq_out_insn_config;
4625
4626         /* ai configuration */
4627         s = &dev->subdevices[NI_AI_SUBDEV];
4628         ni_ai_reset(dev, s);
4629         if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4630                 /*  BEAM is this needed for PCI-6143 ?? */
4631                 devpriv->clock_and_fout =
4632                     Slow_Internal_Time_Divide_By_2 |
4633                     Slow_Internal_Timebase |
4634                     Clock_To_Board_Divide_By_2 |
4635                     Clock_To_Board |
4636                     AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4637         } else {
4638                 devpriv->clock_and_fout =
4639                     Slow_Internal_Time_Divide_By_2 |
4640                     Slow_Internal_Timebase |
4641                     Clock_To_Board_Divide_By_2 | Clock_To_Board;
4642         }
4643         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4644                             Clock_and_FOUT_Register);
4645
4646         /* analog output configuration */
4647         s = &dev->subdevices[NI_AO_SUBDEV];
4648         ni_ao_reset(dev, s);
4649
4650         if (dev->irq) {
4651                 devpriv->stc_writew(dev,
4652                                     (IRQ_POLARITY ? Interrupt_Output_Polarity :
4653                                      0) | (Interrupt_Output_On_3_Pins & 0) |
4654                                     Interrupt_A_Enable | Interrupt_B_Enable |
4655                                     Interrupt_A_Output_Select(interrupt_pin
4656                                                               (dev->irq)) |
4657                                     Interrupt_B_Output_Select(interrupt_pin
4658                                                               (dev->irq)),
4659                                     Interrupt_Control_Register);
4660         }
4661
4662         /* DMA setup */
4663         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4664         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4665
4666         if (boardtype.reg_type & ni_reg_6xxx_mask) {
4667                 ni_writeb(0, Magic_611x);
4668         } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4669                 int channel;
4670                 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4671                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4672                         ni_writeb(0x0,
4673                                   M_Offset_AO_Reference_Attenuation(channel));
4674                 }
4675                 ni_writeb(0x0, M_Offset_AO_Calibration);
4676         }
4677
4678         printk("\n");
4679         return 0;
4680 }
4681
4682 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4683 {
4684         struct comedi_device *dev = (struct comedi_device *)arg;
4685         struct ni_private *devpriv __maybe_unused = dev->private;
4686
4687         if (dir) {
4688                 ni_writeb(data, Port_A + 2 * port);
4689                 return 0;
4690         } else {
4691                 return ni_readb(Port_A + 2 * port);
4692         }
4693 }
4694
4695 /*
4696         presents the EEPROM as a subdevice
4697 */
4698
4699 static int ni_eeprom_insn_read(struct comedi_device *dev,
4700                                struct comedi_subdevice *s,
4701                                struct comedi_insn *insn, unsigned int *data)
4702 {
4703         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4704
4705         return 1;
4706 }
4707
4708 /*
4709         reads bytes out of eeprom
4710 */
4711
4712 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4713 {
4714         struct ni_private *devpriv __maybe_unused = dev->private;
4715         int bit;
4716         int bitstring;
4717
4718         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4719         ni_writeb(0x04, Serial_Command);
4720         for (bit = 0x8000; bit; bit >>= 1) {
4721                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4722                           Serial_Command);
4723                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4724                           Serial_Command);
4725         }
4726         bitstring = 0;
4727         for (bit = 0x80; bit; bit >>= 1) {
4728                 ni_writeb(0x04, Serial_Command);
4729                 ni_writeb(0x05, Serial_Command);
4730                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4731         }
4732         ni_writeb(0x00, Serial_Command);
4733
4734         return bitstring;
4735 }
4736
4737 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4738                                         struct comedi_subdevice *s,
4739                                         struct comedi_insn *insn,
4740                                         unsigned int *data)
4741 {
4742         struct ni_private *devpriv = dev->private;
4743
4744         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4745
4746         return 1;
4747 }
4748
4749 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4750 {
4751         struct ni_private *devpriv = dev->private;
4752
4753         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4754         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4755         return 3;
4756 }
4757
4758 static int ni_m_series_pwm_config(struct comedi_device *dev,
4759                                   struct comedi_subdevice *s,
4760                                   struct comedi_insn *insn, unsigned int *data)
4761 {
4762         struct ni_private *devpriv = dev->private;
4763         unsigned up_count, down_count;
4764
4765         switch (data[0]) {
4766         case INSN_CONFIG_PWM_OUTPUT:
4767                 switch (data[1]) {
4768                 case TRIG_ROUND_NEAREST:
4769                         up_count =
4770                             (data[2] +
4771                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4772                         break;
4773                 case TRIG_ROUND_DOWN:
4774                         up_count = data[2] / devpriv->clock_ns;
4775                         break;
4776                 case TRIG_ROUND_UP:
4777                         up_count =
4778                             (data[2] + devpriv->clock_ns -
4779                              1) / devpriv->clock_ns;
4780                         break;
4781                 default:
4782                         return -EINVAL;
4783                         break;
4784                 }
4785                 switch (data[3]) {
4786                 case TRIG_ROUND_NEAREST:
4787                         down_count =
4788                             (data[4] +
4789                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4790                         break;
4791                 case TRIG_ROUND_DOWN:
4792                         down_count = data[4] / devpriv->clock_ns;
4793                         break;
4794                 case TRIG_ROUND_UP:
4795                         down_count =
4796                             (data[4] + devpriv->clock_ns -
4797                              1) / devpriv->clock_ns;
4798                         break;
4799                 default:
4800                         return -EINVAL;
4801                         break;
4802                 }
4803                 if (up_count * devpriv->clock_ns != data[2] ||
4804                     down_count * devpriv->clock_ns != data[4]) {
4805                         data[2] = up_count * devpriv->clock_ns;
4806                         data[4] = down_count * devpriv->clock_ns;
4807                         return -EAGAIN;
4808                 }
4809                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4810                           MSeries_Cal_PWM_Low_Time_Bits(down_count),
4811                           M_Offset_Cal_PWM);
4812                 devpriv->pwm_up_count = up_count;
4813                 devpriv->pwm_down_count = down_count;
4814                 return 5;
4815                 break;
4816         case INSN_CONFIG_GET_PWM_OUTPUT:
4817                 return ni_get_pwm_config(dev, data);
4818                 break;
4819         default:
4820                 return -EINVAL;
4821                 break;
4822         }
4823         return 0;
4824 }
4825
4826 static int ni_6143_pwm_config(struct comedi_device *dev,
4827                               struct comedi_subdevice *s,
4828                               struct comedi_insn *insn, unsigned int *data)
4829 {
4830         struct ni_private *devpriv = dev->private;
4831         unsigned up_count, down_count;
4832
4833         switch (data[0]) {
4834         case INSN_CONFIG_PWM_OUTPUT:
4835                 switch (data[1]) {
4836                 case TRIG_ROUND_NEAREST:
4837                         up_count =
4838                             (data[2] +
4839                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4840                         break;
4841                 case TRIG_ROUND_DOWN:
4842                         up_count = data[2] / devpriv->clock_ns;
4843                         break;
4844                 case TRIG_ROUND_UP:
4845                         up_count =
4846                             (data[2] + devpriv->clock_ns -
4847                              1) / devpriv->clock_ns;
4848                         break;
4849                 default:
4850                         return -EINVAL;
4851                         break;
4852                 }
4853                 switch (data[3]) {
4854                 case TRIG_ROUND_NEAREST:
4855                         down_count =
4856                             (data[4] +
4857                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4858                         break;
4859                 case TRIG_ROUND_DOWN:
4860                         down_count = data[4] / devpriv->clock_ns;
4861                         break;
4862                 case TRIG_ROUND_UP:
4863                         down_count =
4864                             (data[4] + devpriv->clock_ns -
4865                              1) / devpriv->clock_ns;
4866                         break;
4867                 default:
4868                         return -EINVAL;
4869                         break;
4870                 }
4871                 if (up_count * devpriv->clock_ns != data[2] ||
4872                     down_count * devpriv->clock_ns != data[4]) {
4873                         data[2] = up_count * devpriv->clock_ns;
4874                         data[4] = down_count * devpriv->clock_ns;
4875                         return -EAGAIN;
4876                 }
4877                 ni_writel(up_count, Calibration_HighTime_6143);
4878                 devpriv->pwm_up_count = up_count;
4879                 ni_writel(down_count, Calibration_LowTime_6143);
4880                 devpriv->pwm_down_count = down_count;
4881                 return 5;
4882                 break;
4883         case INSN_CONFIG_GET_PWM_OUTPUT:
4884                 return ni_get_pwm_config(dev, data);
4885         default:
4886                 return -EINVAL;
4887                 break;
4888         }
4889         return 0;
4890 }
4891
4892 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4893 /*
4894         calibration subdevice
4895 */
4896 static int ni_calib_insn_write(struct comedi_device *dev,
4897                                struct comedi_subdevice *s,
4898                                struct comedi_insn *insn, unsigned int *data)
4899 {
4900         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4901
4902         return 1;
4903 }
4904
4905 static int ni_calib_insn_read(struct comedi_device *dev,
4906                               struct comedi_subdevice *s,
4907                               struct comedi_insn *insn, unsigned int *data)
4908 {
4909         struct ni_private *devpriv = dev->private;
4910
4911         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4912
4913         return 1;
4914 }
4915
4916 static int pack_mb88341(int addr, int val, int *bitstring);
4917 static int pack_dac8800(int addr, int val, int *bitstring);
4918 static int pack_dac8043(int addr, int val, int *bitstring);
4919 static int pack_ad8522(int addr, int val, int *bitstring);
4920 static int pack_ad8804(int addr, int val, int *bitstring);
4921 static int pack_ad8842(int addr, int val, int *bitstring);
4922
4923 struct caldac_struct {
4924         int n_chans;
4925         int n_bits;
4926         int (*packbits) (int, int, int *);
4927 };
4928
4929 static struct caldac_struct caldacs[] = {
4930         [mb88341] = {12, 8, pack_mb88341},
4931         [dac8800] = {8, 8, pack_dac8800},
4932         [dac8043] = {1, 12, pack_dac8043},
4933         [ad8522] = {2, 12, pack_ad8522},
4934         [ad8804] = {12, 8, pack_ad8804},
4935         [ad8842] = {8, 8, pack_ad8842},
4936         [ad8804_debug] = {16, 8, pack_ad8804},
4937 };
4938
4939 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4940 {
4941         struct ni_private *devpriv = dev->private;
4942         int i, j;
4943         int n_dacs;
4944         int n_chans = 0;
4945         int n_bits;
4946         int diffbits = 0;
4947         int type;
4948         int chan;
4949
4950         type = boardtype.caldac[0];
4951         if (type == caldac_none)
4952                 return;
4953         n_bits = caldacs[type].n_bits;
4954         for (i = 0; i < 3; i++) {
4955                 type = boardtype.caldac[i];
4956                 if (type == caldac_none)
4957                         break;
4958                 if (caldacs[type].n_bits != n_bits)
4959                         diffbits = 1;
4960                 n_chans += caldacs[type].n_chans;
4961         }
4962         n_dacs = i;
4963         s->n_chan = n_chans;
4964
4965         if (diffbits) {
4966                 unsigned int *maxdata_list;
4967
4968                 if (n_chans > MAX_N_CALDACS) {
4969                         printk("BUG! MAX_N_CALDACS too small\n");
4970                 }
4971                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4972                 chan = 0;
4973                 for (i = 0; i < n_dacs; i++) {
4974                         type = boardtype.caldac[i];
4975                         for (j = 0; j < caldacs[type].n_chans; j++) {
4976                                 maxdata_list[chan] =
4977                                     (1 << caldacs[type].n_bits) - 1;
4978                                 chan++;
4979                         }
4980                 }
4981
4982                 for (chan = 0; chan < s->n_chan; chan++)
4983                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4984         } else {
4985                 type = boardtype.caldac[0];
4986                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4987
4988                 for (chan = 0; chan < s->n_chan; chan++)
4989                         ni_write_caldac(dev, i, s->maxdata / 2);
4990         }
4991 }
4992
4993 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4994 {
4995         struct ni_private *devpriv = dev->private;
4996         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4997         int i;
4998         int type;
4999
5000         /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5001         if (devpriv->caldacs[addr] == val)
5002                 return;
5003         devpriv->caldacs[addr] = val;
5004
5005         for (i = 0; i < 3; i++) {
5006                 type = boardtype.caldac[i];
5007                 if (type == caldac_none)
5008                         break;
5009                 if (addr < caldacs[type].n_chans) {
5010                         bits = caldacs[type].packbits(addr, val, &bitstring);
5011                         loadbit = SerDacLd(i);
5012                         /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5013                         break;
5014                 }
5015                 addr -= caldacs[type].n_chans;
5016         }
5017
5018         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5019                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5020                 udelay(1);
5021                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5022                 udelay(1);
5023         }
5024         ni_writeb(loadbit, Serial_Command);
5025         udelay(1);
5026         ni_writeb(0, Serial_Command);
5027 }
5028
5029 static int pack_mb88341(int addr, int val, int *bitstring)
5030 {
5031         /*
5032            Fujitsu MB 88341
5033            Note that address bits are reversed.  Thanks to
5034            Ingo Keen for noticing this.
5035
5036            Note also that the 88341 expects address values from
5037            1-12, whereas we use channel numbers 0-11.  The NI
5038            docs use 1-12, also, so be careful here.
5039          */
5040         addr++;
5041         *bitstring = ((addr & 0x1) << 11) |
5042             ((addr & 0x2) << 9) |
5043             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5044         return 12;
5045 }
5046
5047 static int pack_dac8800(int addr, int val, int *bitstring)
5048 {
5049         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5050         return 11;
5051 }
5052
5053 static int pack_dac8043(int addr, int val, int *bitstring)
5054 {
5055         *bitstring = val & 0xfff;
5056         return 12;
5057 }
5058
5059 static int pack_ad8522(int addr, int val, int *bitstring)
5060 {
5061         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5062         return 16;
5063 }
5064
5065 static int pack_ad8804(int addr, int val, int *bitstring)
5066 {
5067         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5068         return 12;
5069 }
5070
5071 static int pack_ad8842(int addr, int val, int *bitstring)
5072 {
5073         *bitstring = ((addr + 1) << 8) | (val & 0xff);
5074         return 12;
5075 }
5076
5077 #if 0
5078 /*
5079  *      Read the GPCTs current value.
5080  */
5081 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5082 {
5083         unsigned int hi1, hi2, lo;
5084
5085         devpriv->gpct_command[chan] &= ~G_Save_Trace;
5086         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5087                             G_Command_Register(chan));
5088
5089         devpriv->gpct_command[chan] |= G_Save_Trace;
5090         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5091                             G_Command_Register(chan));
5092
5093         /* This procedure is used because the two registers cannot
5094          * be read atomically. */
5095         do {
5096                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5097                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5098                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5099         } while (hi1 != hi2);
5100
5101         return (hi1 << 16) | lo;
5102 }
5103
5104 static void GPCT_Reset(struct comedi_device *dev, int chan)
5105 {
5106         int temp_ack_reg = 0;
5107
5108         /* printk("GPCT_Reset..."); */
5109         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5110
5111         switch (chan) {
5112         case 0:
5113                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5114                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5115                             G0_TC_Interrupt_Enable, 0);
5116                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5117                             G0_Gate_Interrupt_Enable, 0);
5118                 temp_ack_reg |= G0_Gate_Error_Confirm;
5119                 temp_ack_reg |= G0_TC_Error_Confirm;
5120                 temp_ack_reg |= G0_TC_Interrupt_Ack;
5121                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5122                 devpriv->stc_writew(dev, temp_ack_reg,
5123                                     Interrupt_A_Ack_Register);
5124
5125                 /* problem...this interferes with the other ctr... */
5126                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5127                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5128                                     Analog_Trigger_Etc_Register);
5129                 break;
5130         case 1:
5131                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5132                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5133                             G1_TC_Interrupt_Enable, 0);
5134                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5135                             G0_Gate_Interrupt_Enable, 0);
5136                 temp_ack_reg |= G1_Gate_Error_Confirm;
5137                 temp_ack_reg |= G1_TC_Error_Confirm;
5138                 temp_ack_reg |= G1_TC_Interrupt_Ack;
5139                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5140                 devpriv->stc_writew(dev, temp_ack_reg,
5141                                     Interrupt_B_Ack_Register);
5142
5143                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5144                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5145                                     Analog_Trigger_Etc_Register);
5146                 break;
5147         }
5148
5149         devpriv->gpct_mode[chan] = 0;
5150         devpriv->gpct_input_select[chan] = 0;
5151         devpriv->gpct_command[chan] = 0;
5152
5153         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5154
5155         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5156                             G_Mode_Register(chan));
5157         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5158                             G_Input_Select_Register(chan));
5159         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5160
5161         /* printk("exit GPCT_Reset\n"); */
5162 }
5163
5164 #endif
5165
5166 static int ni_gpct_insn_config(struct comedi_device *dev,
5167                                struct comedi_subdevice *s,
5168                                struct comedi_insn *insn, unsigned int *data)
5169 {
5170         struct ni_gpct *counter = s->private;
5171         return ni_tio_insn_config(counter, insn, data);
5172 }
5173
5174 static int ni_gpct_insn_read(struct comedi_device *dev,
5175                              struct comedi_subdevice *s,
5176                              struct comedi_insn *insn, unsigned int *data)
5177 {
5178         struct ni_gpct *counter = s->private;
5179         return ni_tio_rinsn(counter, insn, data);
5180 }
5181
5182 static int ni_gpct_insn_write(struct comedi_device *dev,
5183                               struct comedi_subdevice *s,
5184                               struct comedi_insn *insn, unsigned int *data)
5185 {
5186         struct ni_gpct *counter = s->private;
5187         return ni_tio_winsn(counter, insn, data);
5188 }
5189
5190 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5191 {
5192         int retval;
5193 #ifdef PCIDMA
5194         struct ni_gpct *counter = s->private;
5195 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5196
5197         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5198                                               COMEDI_INPUT);
5199         if (retval) {
5200                 comedi_error(dev,
5201                              "no dma channel available for use by counter");
5202                 return retval;
5203         }
5204         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5205         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5206         retval = ni_tio_cmd(counter, s->async);
5207 #else
5208         retval = -ENOTSUPP;
5209 #endif
5210         return retval;
5211 }
5212
5213 static int ni_gpct_cmdtest(struct comedi_device *dev,
5214                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
5215 {
5216 #ifdef PCIDMA
5217         struct ni_gpct *counter = s->private;
5218
5219         return ni_tio_cmdtest(counter, cmd);
5220 #else
5221         return -ENOTSUPP;
5222 #endif
5223 }
5224
5225 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5226 {
5227 #ifdef PCIDMA
5228         struct ni_gpct *counter = s->private;
5229         int retval;
5230
5231         retval = ni_tio_cancel(counter);
5232         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5233         ni_release_gpct_mite_channel(dev, counter->counter_index);
5234         return retval;
5235 #else
5236         return 0;
5237 #endif
5238 }
5239
5240 /*
5241  *
5242  *  Programmable Function Inputs
5243  *
5244  */
5245
5246 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5247                                        unsigned source)
5248 {
5249         struct ni_private *devpriv = dev->private;
5250         unsigned pfi_reg_index;
5251         unsigned array_offset;
5252
5253         if ((source & 0x1f) != source)
5254                 return -EINVAL;
5255         pfi_reg_index = 1 + chan / 3;
5256         array_offset = pfi_reg_index - 1;
5257         devpriv->pfi_output_select_reg[array_offset] &=
5258             ~MSeries_PFI_Output_Select_Mask(chan);
5259         devpriv->pfi_output_select_reg[array_offset] |=
5260             MSeries_PFI_Output_Select_Bits(chan, source);
5261         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5262                   M_Offset_PFI_Output_Select(pfi_reg_index));
5263         return 2;
5264 }
5265
5266 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5267                                   unsigned source)
5268 {
5269         /*  pre-m-series boards have fixed signals on pfi pins */
5270         if (source != ni_old_get_pfi_routing(dev, chan))
5271                 return -EINVAL;
5272         return 2;
5273 }
5274
5275 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5276                               unsigned source)
5277 {
5278         if (boardtype.reg_type & ni_reg_m_series_mask)
5279                 return ni_m_series_set_pfi_routing(dev, chan, source);
5280         else
5281                 return ni_old_set_pfi_routing(dev, chan, source);
5282 }
5283
5284 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5285                                             unsigned chan)
5286 {
5287         struct ni_private *devpriv = dev->private;
5288         const unsigned array_offset = chan / 3;
5289
5290         return MSeries_PFI_Output_Select_Source(chan,
5291                                                 devpriv->
5292                                                 pfi_output_select_reg
5293                                                 [array_offset]);
5294 }
5295
5296 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5297 {
5298         /*  pre-m-series boards have fixed signals on pfi pins */
5299         switch (chan) {
5300         case 0:
5301                 return NI_PFI_OUTPUT_AI_START1;
5302                 break;
5303         case 1:
5304                 return NI_PFI_OUTPUT_AI_START2;
5305                 break;
5306         case 2:
5307                 return NI_PFI_OUTPUT_AI_CONVERT;
5308                 break;
5309         case 3:
5310                 return NI_PFI_OUTPUT_G_SRC1;
5311                 break;
5312         case 4:
5313                 return NI_PFI_OUTPUT_G_GATE1;
5314                 break;
5315         case 5:
5316                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5317                 break;
5318         case 6:
5319                 return NI_PFI_OUTPUT_AO_START1;
5320                 break;
5321         case 7:
5322                 return NI_PFI_OUTPUT_AI_START_PULSE;
5323                 break;
5324         case 8:
5325                 return NI_PFI_OUTPUT_G_SRC0;
5326                 break;
5327         case 9:
5328                 return NI_PFI_OUTPUT_G_GATE0;
5329                 break;
5330         default:
5331                 printk("%s: bug, unhandled case in switch.\n", __func__);
5332                 break;
5333         }
5334         return 0;
5335 }
5336
5337 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5338 {
5339         if (boardtype.reg_type & ni_reg_m_series_mask)
5340                 return ni_m_series_get_pfi_routing(dev, chan);
5341         else
5342                 return ni_old_get_pfi_routing(dev, chan);
5343 }
5344
5345 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5346                             enum ni_pfi_filter_select filter)
5347 {
5348         struct ni_private *devpriv __maybe_unused = dev->private;
5349         unsigned bits;
5350
5351         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5352                 return -ENOTSUPP;
5353         }
5354         bits = ni_readl(M_Offset_PFI_Filter);
5355         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5356         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5357         ni_writel(bits, M_Offset_PFI_Filter);
5358         return 0;
5359 }
5360
5361 static int ni_pfi_insn_bits(struct comedi_device *dev,
5362                             struct comedi_subdevice *s,
5363                             struct comedi_insn *insn, unsigned int *data)
5364 {
5365         struct ni_private *devpriv __maybe_unused = dev->private;
5366
5367         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5368                 return -ENOTSUPP;
5369         }
5370         if (data[0]) {
5371                 s->state &= ~data[0];
5372                 s->state |= (data[0] & data[1]);
5373                 ni_writew(s->state, M_Offset_PFI_DO);
5374         }
5375         data[1] = ni_readw(M_Offset_PFI_DI);
5376         return insn->n;
5377 }
5378
5379 static int ni_pfi_insn_config(struct comedi_device *dev,
5380                               struct comedi_subdevice *s,
5381                               struct comedi_insn *insn, unsigned int *data)
5382 {
5383         struct ni_private *devpriv = dev->private;
5384         unsigned int chan;
5385
5386         if (insn->n < 1)
5387                 return -EINVAL;
5388
5389         chan = CR_CHAN(insn->chanspec);
5390
5391         switch (data[0]) {
5392         case COMEDI_OUTPUT:
5393                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5394                 break;
5395         case COMEDI_INPUT:
5396                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5397                 break;
5398         case INSN_CONFIG_DIO_QUERY:
5399                 data[1] =
5400                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5401                     COMEDI_OUTPUT : COMEDI_INPUT;
5402                 return 0;
5403                 break;
5404         case INSN_CONFIG_SET_ROUTING:
5405                 return ni_set_pfi_routing(dev, chan, data[1]);
5406                 break;
5407         case INSN_CONFIG_GET_ROUTING:
5408                 data[1] = ni_get_pfi_routing(dev, chan);
5409                 break;
5410         case INSN_CONFIG_FILTER:
5411                 return ni_config_filter(dev, chan, data[1]);
5412                 break;
5413         default:
5414                 return -EINVAL;
5415         }
5416         return 0;
5417 }
5418
5419 /*
5420  *
5421  *  NI RTSI Bus Functions
5422  *
5423  */
5424 static void ni_rtsi_init(struct comedi_device *dev)
5425 {
5426         struct ni_private *devpriv = dev->private;
5427
5428         /*  Initialises the RTSI bus signal switch to a default state */
5429
5430         /*  Set clock mode to internal */
5431         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5432         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5433                 printk("ni_set_master_clock failed, bug?");
5434         }
5435         /*  default internal lines routing to RTSI bus lines */
5436         devpriv->rtsi_trig_a_output_reg =
5437             RTSI_Trig_Output_Bits(0,
5438                                   NI_RTSI_OUTPUT_ADR_START1) |
5439             RTSI_Trig_Output_Bits(1,
5440                                   NI_RTSI_OUTPUT_ADR_START2) |
5441             RTSI_Trig_Output_Bits(2,
5442                                   NI_RTSI_OUTPUT_SCLKG) |
5443             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5444         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5445                             RTSI_Trig_A_Output_Register);
5446         devpriv->rtsi_trig_b_output_reg =
5447             RTSI_Trig_Output_Bits(4,
5448                                   NI_RTSI_OUTPUT_DA_START1) |
5449             RTSI_Trig_Output_Bits(5,
5450                                   NI_RTSI_OUTPUT_G_SRC0) |
5451             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5452         if (boardtype.reg_type & ni_reg_m_series_mask)
5453                 devpriv->rtsi_trig_b_output_reg |=
5454                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5455         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5456                             RTSI_Trig_B_Output_Register);
5457
5458 /*
5459 * Sets the source and direction of the 4 on board lines
5460 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5461 */
5462 }
5463
5464 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5465                              struct comedi_subdevice *s,
5466                              struct comedi_insn *insn, unsigned int *data)
5467 {
5468         data[1] = 0;
5469
5470         return insn->n;
5471 }
5472
5473 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5474  * given an arbitrary frequency input clock */
5475 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5476                                          unsigned *freq_divider,
5477                                          unsigned *freq_multiplier,
5478                                          unsigned *actual_period_ns)
5479 {
5480         unsigned div;
5481         unsigned best_div = 1;
5482         static const unsigned max_div = 0x10;
5483         unsigned mult;
5484         unsigned best_mult = 1;
5485         static const unsigned max_mult = 0x100;
5486         static const unsigned pico_per_nano = 1000;
5487
5488         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5489         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5490          * 20 MHz for most timing clocks */
5491         static const unsigned target_picosec = 12500;
5492         static const unsigned fudge_factor_80_to_20Mhz = 4;
5493         int best_period_picosec = 0;
5494         for (div = 1; div <= max_div; ++div) {
5495                 for (mult = 1; mult <= max_mult; ++mult) {
5496                         unsigned new_period_ps =
5497                             (reference_picosec * div) / mult;
5498                         if (abs(new_period_ps - target_picosec) <
5499                             abs(best_period_picosec - target_picosec)) {
5500                                 best_period_picosec = new_period_ps;
5501                                 best_div = div;
5502                                 best_mult = mult;
5503                         }
5504                 }
5505         }
5506         if (best_period_picosec == 0) {
5507                 printk("%s: bug, failed to find pll parameters\n", __func__);
5508                 return -EIO;
5509         }
5510         *freq_divider = best_div;
5511         *freq_multiplier = best_mult;
5512         *actual_period_ns =
5513             (best_period_picosec * fudge_factor_80_to_20Mhz +
5514              (pico_per_nano / 2)) / pico_per_nano;
5515         return 0;
5516 }
5517
5518 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5519 {
5520         if (boardtype.reg_type & ni_reg_m_series_mask)
5521                 return 8;
5522         else
5523                 return 7;
5524 }
5525
5526 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5527                                            unsigned source, unsigned period_ns)
5528 {
5529         struct ni_private *devpriv = dev->private;
5530         static const unsigned min_period_ns = 50;
5531         static const unsigned max_period_ns = 1000;
5532         static const unsigned timeout = 1000;
5533         unsigned pll_control_bits;
5534         unsigned freq_divider;
5535         unsigned freq_multiplier;
5536         unsigned i;
5537         int retval;
5538
5539         if (source == NI_MIO_PLL_PXI10_CLOCK)
5540                 period_ns = 100;
5541         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5542         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5543                 printk
5544                     ("%s: you must specify an input clock frequency between %i and %i nanosec "
5545                      "for the phased-lock loop.\n", __func__,
5546                      min_period_ns, max_period_ns);
5547                 return -EINVAL;
5548         }
5549         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5550         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5551                             RTSI_Trig_Direction_Register);
5552         pll_control_bits =
5553             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5554         devpriv->clock_and_fout2 |=
5555             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5556         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5557         switch (source) {
5558         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5559                 devpriv->clock_and_fout2 |=
5560                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5561                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5562                                                        &freq_multiplier,
5563                                                        &devpriv->clock_ns);
5564                 if (retval < 0)
5565                         return retval;
5566                 break;
5567         case NI_MIO_PLL_PXI10_CLOCK:
5568                 /* pxi clock is 10MHz */
5569                 devpriv->clock_and_fout2 |=
5570                     MSeries_PLL_In_Source_Select_PXI_Clock10;
5571                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5572                                                        &freq_multiplier,
5573                                                        &devpriv->clock_ns);
5574                 if (retval < 0)
5575                         return retval;
5576                 break;
5577         default:
5578                 {
5579                         unsigned rtsi_channel;
5580                         static const unsigned max_rtsi_channel = 7;
5581                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5582                              ++rtsi_channel) {
5583                                 if (source ==
5584                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5585                                         devpriv->clock_and_fout2 |=
5586                                             MSeries_PLL_In_Source_Select_RTSI_Bits
5587                                             (rtsi_channel);
5588                                         break;
5589                                 }
5590                         }
5591                         if (rtsi_channel > max_rtsi_channel)
5592                                 return -EINVAL;
5593                         retval = ni_mseries_get_pll_parameters(period_ns,
5594                                                                &freq_divider,
5595                                                                &freq_multiplier,
5596                                                                &devpriv->
5597                                                                clock_ns);
5598                         if (retval < 0)
5599                                 return retval;
5600                 }
5601                 break;
5602         }
5603         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5604         pll_control_bits |=
5605             MSeries_PLL_Divisor_Bits(freq_divider) |
5606             MSeries_PLL_Multiplier_Bits(freq_multiplier);
5607
5608         /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5609          * freq_divider, freq_multiplier, pll_control_bits); */
5610         /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5611         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5612         devpriv->clock_source = source;
5613         /* it seems to typically take a few hundred microseconds for PLL to lock */
5614         for (i = 0; i < timeout; ++i) {
5615                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5616                         break;
5617                 }
5618                 udelay(1);
5619         }
5620         if (i == timeout) {
5621                 printk
5622                     ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5623                      __func__, source, period_ns);
5624                 return -ETIMEDOUT;
5625         }
5626         return 3;
5627 }
5628
5629 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5630                                unsigned period_ns)
5631 {
5632         struct ni_private *devpriv = dev->private;
5633
5634         if (source == NI_MIO_INTERNAL_CLOCK) {
5635                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5636                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5637                                     RTSI_Trig_Direction_Register);
5638                 devpriv->clock_ns = TIMEBASE_1_NS;
5639                 if (boardtype.reg_type & ni_reg_m_series_mask) {
5640                         devpriv->clock_and_fout2 &=
5641                             ~(MSeries_Timebase1_Select_Bit |
5642                               MSeries_Timebase3_Select_Bit);
5643                         ni_writew(devpriv->clock_and_fout2,
5644                                   M_Offset_Clock_and_Fout2);
5645                         ni_writew(0, M_Offset_PLL_Control);
5646                 }
5647                 devpriv->clock_source = source;
5648         } else {
5649                 if (boardtype.reg_type & ni_reg_m_series_mask) {
5650                         return ni_mseries_set_pll_master_clock(dev, source,
5651                                                                period_ns);
5652                 } else {
5653                         if (source == NI_MIO_RTSI_CLOCK) {
5654                                 devpriv->rtsi_trig_direction_reg |=
5655                                     Use_RTSI_Clock_Bit;
5656                                 devpriv->stc_writew(dev,
5657                                                     devpriv->
5658                                                     rtsi_trig_direction_reg,
5659                                                     RTSI_Trig_Direction_Register);
5660                                 if (period_ns == 0) {
5661                                         printk
5662                                             ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5663                                              __func__);
5664                                         return -EINVAL;
5665                                 } else {
5666                                         devpriv->clock_ns = period_ns;
5667                                 }
5668                                 devpriv->clock_source = source;
5669                         } else
5670                                 return -EINVAL;
5671                 }
5672         }
5673         return 3;
5674 }
5675
5676 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5677                                        unsigned source)
5678 {
5679         if (chan >= num_configurable_rtsi_channels(dev)) {
5680                 if (chan == old_RTSI_clock_channel) {
5681                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5682                                 return 1;
5683                         else {
5684                                 printk
5685                                     ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5686                                      __func__, chan, old_RTSI_clock_channel);
5687                                 return 0;
5688                         }
5689                 }
5690                 return 0;
5691         }
5692         switch (source) {
5693         case NI_RTSI_OUTPUT_ADR_START1:
5694         case NI_RTSI_OUTPUT_ADR_START2:
5695         case NI_RTSI_OUTPUT_SCLKG:
5696         case NI_RTSI_OUTPUT_DACUPDN:
5697         case NI_RTSI_OUTPUT_DA_START1:
5698         case NI_RTSI_OUTPUT_G_SRC0:
5699         case NI_RTSI_OUTPUT_G_GATE0:
5700         case NI_RTSI_OUTPUT_RGOUT0:
5701         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5702                 return 1;
5703                 break;
5704         case NI_RTSI_OUTPUT_RTSI_OSC:
5705                 if (boardtype.reg_type & ni_reg_m_series_mask)
5706                         return 1;
5707                 else
5708                         return 0;
5709                 break;
5710         default:
5711                 return 0;
5712                 break;
5713         }
5714 }
5715
5716 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5717                                unsigned source)
5718 {
5719         struct ni_private *devpriv = dev->private;
5720
5721         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5722                 return -EINVAL;
5723         if (chan < 4) {
5724                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5725                 devpriv->rtsi_trig_a_output_reg |=
5726                     RTSI_Trig_Output_Bits(chan, source);
5727                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5728                                     RTSI_Trig_A_Output_Register);
5729         } else if (chan < 8) {
5730                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5731                 devpriv->rtsi_trig_b_output_reg |=
5732                     RTSI_Trig_Output_Bits(chan, source);
5733                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5734                                     RTSI_Trig_B_Output_Register);
5735         }
5736         return 2;
5737 }
5738
5739 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5740 {
5741         struct ni_private *devpriv = dev->private;
5742
5743         if (chan < 4) {
5744                 return RTSI_Trig_Output_Source(chan,
5745                                                devpriv->rtsi_trig_a_output_reg);
5746         } else if (chan < num_configurable_rtsi_channels(dev)) {
5747                 return RTSI_Trig_Output_Source(chan,
5748                                                devpriv->rtsi_trig_b_output_reg);
5749         } else {
5750                 if (chan == old_RTSI_clock_channel)
5751                         return NI_RTSI_OUTPUT_RTSI_OSC;
5752                 printk("%s: bug! should never get here?\n", __func__);
5753                 return 0;
5754         }
5755 }
5756
5757 static int ni_rtsi_insn_config(struct comedi_device *dev,
5758                                struct comedi_subdevice *s,
5759                                struct comedi_insn *insn, unsigned int *data)
5760 {
5761         struct ni_private *devpriv = dev->private;
5762         unsigned int chan = CR_CHAN(insn->chanspec);
5763
5764         switch (data[0]) {
5765         case INSN_CONFIG_DIO_OUTPUT:
5766                 if (chan < num_configurable_rtsi_channels(dev)) {
5767                         devpriv->rtsi_trig_direction_reg |=
5768                             RTSI_Output_Bit(chan,
5769                                             (boardtype.
5770                                              reg_type & ni_reg_m_series_mask) !=
5771                                             0);
5772                 } else if (chan == old_RTSI_clock_channel) {
5773                         devpriv->rtsi_trig_direction_reg |=
5774                             Drive_RTSI_Clock_Bit;
5775                 }
5776                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5777                                     RTSI_Trig_Direction_Register);
5778                 break;
5779         case INSN_CONFIG_DIO_INPUT:
5780                 if (chan < num_configurable_rtsi_channels(dev)) {
5781                         devpriv->rtsi_trig_direction_reg &=
5782                             ~RTSI_Output_Bit(chan,
5783                                              (boardtype.
5784                                               reg_type & ni_reg_m_series_mask)
5785                                              != 0);
5786                 } else if (chan == old_RTSI_clock_channel) {
5787                         devpriv->rtsi_trig_direction_reg &=
5788                             ~Drive_RTSI_Clock_Bit;
5789                 }
5790                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5791                                     RTSI_Trig_Direction_Register);
5792                 break;
5793         case INSN_CONFIG_DIO_QUERY:
5794                 if (chan < num_configurable_rtsi_channels(dev)) {
5795                         data[1] =
5796                             (devpriv->rtsi_trig_direction_reg &
5797                              RTSI_Output_Bit(chan,
5798                                              (boardtype.reg_type &
5799                                               ni_reg_m_series_mask)
5800                                              != 0)) ? INSN_CONFIG_DIO_OUTPUT :
5801                             INSN_CONFIG_DIO_INPUT;
5802                 } else if (chan == old_RTSI_clock_channel) {
5803                         data[1] =
5804                             (devpriv->rtsi_trig_direction_reg &
5805                              Drive_RTSI_Clock_Bit)
5806                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5807                 }
5808                 return 2;
5809                 break;
5810         case INSN_CONFIG_SET_CLOCK_SRC:
5811                 return ni_set_master_clock(dev, data[1], data[2]);
5812                 break;
5813         case INSN_CONFIG_GET_CLOCK_SRC:
5814                 data[1] = devpriv->clock_source;
5815                 data[2] = devpriv->clock_ns;
5816                 return 3;
5817                 break;
5818         case INSN_CONFIG_SET_ROUTING:
5819                 return ni_set_rtsi_routing(dev, chan, data[1]);
5820                 break;
5821         case INSN_CONFIG_GET_ROUTING:
5822                 data[1] = ni_get_rtsi_routing(dev, chan);
5823                 return 2;
5824                 break;
5825         default:
5826                 return -EINVAL;
5827                 break;
5828         }
5829         return 1;
5830 }
5831
5832 static int cs5529_wait_for_idle(struct comedi_device *dev)
5833 {
5834         unsigned short status;
5835         const int timeout = HZ;
5836         int i;
5837
5838         for (i = 0; i < timeout; i++) {
5839                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5840                 if ((status & CSS_ADC_BUSY) == 0) {
5841                         break;
5842                 }
5843                 set_current_state(TASK_INTERRUPTIBLE);
5844                 if (schedule_timeout(1)) {
5845                         return -EIO;
5846                 }
5847         }
5848 /* printk("looped %i times waiting for idle\n", i); */
5849         if (i == timeout) {
5850                 printk("%s: %s: timeout\n", __FILE__, __func__);
5851                 return -ETIME;
5852         }
5853         return 0;
5854 }
5855
5856 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5857 {
5858         static const int timeout = 100;
5859         int i;
5860
5861         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5862         /* give time for command to start being serially clocked into cs5529.
5863          * this insures that the CSS_ADC_BUSY bit will get properly
5864          * set before we exit this function.
5865          */
5866         for (i = 0; i < timeout; i++) {
5867                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5868                         break;
5869                 udelay(1);
5870         }
5871 /* printk("looped %i times writing command to cs5529\n", i); */
5872         if (i == timeout) {
5873                 comedi_error(dev, "possible problem - never saw adc go busy?");
5874         }
5875 }
5876
5877 /* write to cs5529 register */
5878 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5879                                 unsigned int reg_select_bits)
5880 {
5881         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5882                        CAL_ADC_Config_Data_High_Word_67xx);
5883         ni_ao_win_outw(dev, (value & 0xffff),
5884                        CAL_ADC_Config_Data_Low_Word_67xx);
5885         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5886         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5887         if (cs5529_wait_for_idle(dev))
5888                 comedi_error(dev, "time or signal in cs5529_config_write()");
5889 }
5890
5891 #ifdef NI_CS5529_DEBUG
5892 /* read from cs5529 register */
5893 static unsigned int cs5529_config_read(struct comedi_device *dev,
5894                                        unsigned int reg_select_bits)
5895 {
5896         unsigned int value;
5897
5898         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5899         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5900         if (cs5529_wait_for_idle(dev))
5901                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5902         value = (ni_ao_win_inw(dev,
5903                                CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5904             0xff0000;
5905         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5906         return value;
5907 }
5908 #endif
5909
5910 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5911 {
5912         int retval;
5913         unsigned short status;
5914
5915         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5916         retval = cs5529_wait_for_idle(dev);
5917         if (retval) {
5918                 comedi_error(dev,
5919                              "timeout or signal in cs5529_do_conversion()");
5920                 return -ETIME;
5921         }
5922         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5923         if (status & CSS_OSC_DETECT) {
5924                 printk
5925                     ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5926                 return -EIO;
5927         }
5928         if (status & CSS_OVERRANGE) {
5929                 printk
5930                     ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5931         }
5932         if (data) {
5933                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5934                 /* cs5529 returns 16 bit signed data in bipolar mode */
5935                 *data ^= (1 << 15);
5936         }
5937         return 0;
5938 }
5939
5940 static int cs5529_ai_insn_read(struct comedi_device *dev,
5941                                struct comedi_subdevice *s,
5942                                struct comedi_insn *insn, unsigned int *data)
5943 {
5944         int n, retval;
5945         unsigned short sample;
5946         unsigned int channel_select;
5947         const unsigned int INTERNAL_REF = 0x1000;
5948
5949         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5950          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5951          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5952         if (insn->chanspec & CR_ALT_SOURCE)
5953                 channel_select = INTERNAL_REF;
5954         else
5955                 channel_select = CR_CHAN(insn->chanspec);
5956         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5957
5958         for (n = 0; n < insn->n; n++) {
5959                 retval = cs5529_do_conversion(dev, &sample);
5960                 if (retval < 0)
5961                         return retval;
5962                 data[n] = sample;
5963         }
5964         return insn->n;
5965 }
5966
5967 static int init_cs5529(struct comedi_device *dev)
5968 {
5969         unsigned int config_bits =
5970             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5971
5972 #if 1
5973         /* do self-calibration */
5974         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5975                             CSCMD_CONFIG_REGISTER);
5976         /* need to force a conversion for calibration to run */
5977         cs5529_do_conversion(dev, NULL);
5978 #else
5979         /* force gain calibration to 1 */
5980         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5981         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5982                             CSCMD_CONFIG_REGISTER);
5983         if (cs5529_wait_for_idle(dev))
5984                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5985 #endif
5986 #ifdef NI_CS5529_DEBUG
5987         printk("config: 0x%x\n", cs5529_config_read(dev,
5988                                                     CSCMD_CONFIG_REGISTER));
5989         printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
5990         printk("offset: 0x%x\n", cs5529_config_read(dev,
5991                                                     CSCMD_OFFSET_REGISTER));
5992 #endif
5993         return 0;
5994 }