2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
29 Interrupt support originally added by Truxton Fulton
32 References (from ftp://ftp.natinst.com/support/manuals):
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
40 Other possibly relevant info:
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
45 320906c.pdf maximum signal ratings
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
54 - the interrupt routine needs to be cleaned up
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
68 #include "comedi_fc.h"
71 #define MDPRINTK(format, args...)
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85 [ai_gain_4] = {0, 1, 4, 7},
86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87 0x003, 0x004, 0x005, 0x006},
88 [ai_gain_622x] = {0, 1, 4, 5},
89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
192 static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
197 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
205 static const struct comedi_lrange *const ni_range_lkup[] = {
206 [ai_gain_16] = &range_ni_E_ai,
207 [ai_gain_8] = &range_ni_E_ai_limited,
208 [ai_gain_14] = &range_ni_E_ai_limited14,
209 [ai_gain_4] = &range_ni_E_ai_bipolar4,
210 [ai_gain_611x] = &range_ni_E_ai_611x,
211 [ai_gain_622x] = &range_ni_M_ai_622x,
212 [ai_gain_628x] = &range_ni_M_ai_628x,
213 [ai_gain_6143] = &range_ni_S_ai_6143
216 static int ni_dio_insn_config(struct comedi_device *dev,
217 struct comedi_subdevice *s,
218 struct comedi_insn *insn, unsigned int *data);
219 static int ni_dio_insn_bits(struct comedi_device *dev,
220 struct comedi_subdevice *s,
221 struct comedi_insn *insn, unsigned int *data);
222 static int ni_cdio_cmdtest(struct comedi_device *dev,
223 struct comedi_subdevice *s, struct comedi_cmd *cmd);
224 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
225 static int ni_cdio_cancel(struct comedi_device *dev,
226 struct comedi_subdevice *s);
227 static void handle_cdio_interrupt(struct comedi_device *dev);
228 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
229 unsigned int trignum);
231 static int ni_serial_insn_config(struct comedi_device *dev,
232 struct comedi_subdevice *s,
233 struct comedi_insn *insn, unsigned int *data);
234 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
235 struct comedi_subdevice *s,
236 unsigned char data_out,
237 unsigned char *data_in);
238 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 unsigned char data_out,
241 unsigned char *data_in);
243 static int ni_calib_insn_read(struct comedi_device *dev,
244 struct comedi_subdevice *s,
245 struct comedi_insn *insn, unsigned int *data);
246 static int ni_calib_insn_write(struct comedi_device *dev,
247 struct comedi_subdevice *s,
248 struct comedi_insn *insn, unsigned int *data);
250 static int ni_eeprom_insn_read(struct comedi_device *dev,
251 struct comedi_subdevice *s,
252 struct comedi_insn *insn, unsigned int *data);
253 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
254 struct comedi_subdevice *s,
255 struct comedi_insn *insn,
258 static int ni_pfi_insn_bits(struct comedi_device *dev,
259 struct comedi_subdevice *s,
260 struct comedi_insn *insn, unsigned int *data);
261 static int ni_pfi_insn_config(struct comedi_device *dev,
262 struct comedi_subdevice *s,
263 struct comedi_insn *insn, unsigned int *data);
264 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
267 static void ni_rtsi_init(struct comedi_device *dev);
268 static int ni_rtsi_insn_bits(struct comedi_device *dev,
269 struct comedi_subdevice *s,
270 struct comedi_insn *insn, unsigned int *data);
271 static int ni_rtsi_insn_config(struct comedi_device *dev,
272 struct comedi_subdevice *s,
273 struct comedi_insn *insn, unsigned int *data);
275 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
276 static int ni_read_eeprom(struct comedi_device *dev, int addr);
278 #ifdef DEBUG_STATUS_A
279 static void ni_mio_print_status_a(int status);
281 #define ni_mio_print_status_a(a)
283 #ifdef DEBUG_STATUS_B
284 static void ni_mio_print_status_b(int status);
286 #define ni_mio_print_status_b(a)
289 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
291 static void ni_handle_fifo_half_full(struct comedi_device *dev);
292 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
293 struct comedi_subdevice *s);
295 static void ni_handle_fifo_dregs(struct comedi_device *dev);
296 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
297 unsigned int trignum);
298 static void ni_load_channelgain_list(struct comedi_device *dev,
299 unsigned int n_chan, unsigned int *list);
300 static void shutdown_ai_command(struct comedi_device *dev);
302 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
303 unsigned int trignum);
305 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
307 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
309 static int ni_gpct_insn_write(struct comedi_device *dev,
310 struct comedi_subdevice *s,
311 struct comedi_insn *insn, unsigned int *data);
312 static int ni_gpct_insn_read(struct comedi_device *dev,
313 struct comedi_subdevice *s,
314 struct comedi_insn *insn, unsigned int *data);
315 static int ni_gpct_insn_config(struct comedi_device *dev,
316 struct comedi_subdevice *s,
317 struct comedi_insn *insn, unsigned int *data);
318 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
319 static int ni_gpct_cmdtest(struct comedi_device *dev,
320 struct comedi_subdevice *s, struct comedi_cmd *cmd);
321 static int ni_gpct_cancel(struct comedi_device *dev,
322 struct comedi_subdevice *s);
323 static void handle_gpct_interrupt(struct comedi_device *dev,
324 unsigned short counter_index);
326 static int init_cs5529(struct comedi_device *dev);
327 static int cs5529_do_conversion(struct comedi_device *dev,
328 unsigned short *data);
329 static int cs5529_ai_insn_read(struct comedi_device *dev,
330 struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data);
332 #ifdef NI_CS5529_DEBUG
333 static unsigned int cs5529_config_read(struct comedi_device *dev,
334 unsigned int reg_select_bits);
336 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
337 unsigned int reg_select_bits);
339 static int ni_m_series_pwm_config(struct comedi_device *dev,
340 struct comedi_subdevice *s,
341 struct comedi_insn *insn, unsigned int *data);
342 static int ni_6143_pwm_config(struct comedi_device *dev,
343 struct comedi_subdevice *s,
344 struct comedi_insn *insn, unsigned int *data);
346 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
348 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
349 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
353 AIMODE_HALF_FULL = 1,
358 enum ni_common_subdevices {
364 NI_CALIBRATION_SUBDEV,
367 NI_CS5529_CALIBRATION_SUBDEV,
375 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
377 switch (counter_index) {
379 return NI_GPCT0_SUBDEV;
382 return NI_GPCT1_SUBDEV;
388 return NI_GPCT0_SUBDEV;
391 enum timebase_nanoseconds {
393 TIMEBASE_2_NS = 10000
396 #define SERIAL_DISABLED 0
397 #define SERIAL_600NS 600
398 #define SERIAL_1_2US 1200
399 #define SERIAL_10US 10000
401 static const int num_adc_stages_611x = 3;
403 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
404 unsigned ai_mite_status);
405 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
406 unsigned ao_mite_status);
407 static void get_last_sample_611x(struct comedi_device *dev);
408 static void get_last_sample_6143(struct comedi_device *dev);
410 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
411 unsigned bit_mask, unsigned bit_values)
413 struct ni_private *devpriv = dev->private;
416 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
418 case Interrupt_A_Enable_Register:
419 devpriv->int_a_enable_reg &= ~bit_mask;
420 devpriv->int_a_enable_reg |= bit_values & bit_mask;
421 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
422 Interrupt_A_Enable_Register);
424 case Interrupt_B_Enable_Register:
425 devpriv->int_b_enable_reg &= ~bit_mask;
426 devpriv->int_b_enable_reg |= bit_values & bit_mask;
427 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
428 Interrupt_B_Enable_Register);
430 case IO_Bidirection_Pin_Register:
431 devpriv->io_bidirection_pin_reg &= ~bit_mask;
432 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
433 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
434 IO_Bidirection_Pin_Register);
437 devpriv->ai_ao_select_reg &= ~bit_mask;
438 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
439 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
442 devpriv->g0_g1_select_reg &= ~bit_mask;
443 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
444 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
447 printk("Warning %s() called with invalid register\n", __func__);
448 printk("reg is %d\n", reg);
452 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
456 static int ni_ai_drain_dma(struct comedi_device *dev);
458 /* DMA channel setup */
460 /* negative channel means no channel */
461 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
467 (ni_stc_dma_channel_select_bitfield(channel) <<
468 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
472 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
475 /* negative channel means no channel */
476 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
482 (ni_stc_dma_channel_select_bitfield(channel) <<
483 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
487 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
490 /* negative mite_channel means no channel */
491 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
497 if (mite_channel >= 0) {
498 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
502 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
506 /* negative mite_channel means no channel */
507 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
510 struct ni_private *devpriv = dev->private;
513 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
514 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
515 if (mite_channel >= 0) {
516 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
517 under the assumption the cdio dma selection works just like ai/ao/gpct.
518 Definitely works for dma channels 0 and 1. */
519 devpriv->cdio_dma_select_reg |=
520 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
521 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
523 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
525 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
528 static int ni_request_ai_mite_channel(struct comedi_device *dev)
530 struct ni_private *devpriv = dev->private;
533 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
534 BUG_ON(devpriv->ai_mite_chan);
535 devpriv->ai_mite_chan =
536 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
537 if (devpriv->ai_mite_chan == NULL) {
538 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
540 "failed to reserve mite dma channel for analog input.");
543 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
544 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
545 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
549 static int ni_request_ao_mite_channel(struct comedi_device *dev)
551 struct ni_private *devpriv = dev->private;
554 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
555 BUG_ON(devpriv->ao_mite_chan);
556 devpriv->ao_mite_chan =
557 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
558 if (devpriv->ao_mite_chan == NULL) {
559 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
561 "failed to reserve mite dma channel for analog outut.");
564 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
565 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
566 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
570 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
572 enum comedi_io_direction direction)
574 struct ni_private *devpriv = dev->private;
576 struct mite_channel *mite_chan;
578 BUG_ON(gpct_index >= NUM_GPCT);
579 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
580 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
582 mite_request_channel(devpriv->mite,
583 devpriv->gpct_mite_ring[gpct_index]);
584 if (mite_chan == NULL) {
585 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
587 "failed to reserve mite dma channel for counter.");
590 mite_chan->dir = direction;
591 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
593 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
594 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
600 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
603 struct ni_private *devpriv = dev->private;
606 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
607 BUG_ON(devpriv->cdo_mite_chan);
608 devpriv->cdo_mite_chan =
609 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
610 if (devpriv->cdo_mite_chan == NULL) {
611 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
613 "failed to reserve mite dma channel for correlated digital outut.");
616 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
617 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
618 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
623 static void ni_release_ai_mite_channel(struct comedi_device *dev)
626 struct ni_private *devpriv = dev->private;
629 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
630 if (devpriv->ai_mite_chan) {
631 ni_set_ai_dma_channel(dev, -1);
632 mite_release_channel(devpriv->ai_mite_chan);
633 devpriv->ai_mite_chan = NULL;
635 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
639 static void ni_release_ao_mite_channel(struct comedi_device *dev)
642 struct ni_private *devpriv = dev->private;
645 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
646 if (devpriv->ao_mite_chan) {
647 ni_set_ao_dma_channel(dev, -1);
648 mite_release_channel(devpriv->ao_mite_chan);
649 devpriv->ao_mite_chan = NULL;
651 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
656 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
659 struct ni_private *devpriv = dev->private;
662 BUG_ON(gpct_index >= NUM_GPCT);
663 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
664 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
665 struct mite_channel *mite_chan =
666 devpriv->counter_dev->counters[gpct_index].mite_chan;
668 ni_set_gpct_dma_channel(dev, gpct_index, -1);
669 ni_tio_set_mite_channel(&devpriv->
670 counter_dev->counters[gpct_index],
672 mite_release_channel(mite_chan);
674 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
678 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
681 struct ni_private *devpriv = dev->private;
684 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
685 if (devpriv->cdo_mite_chan) {
686 ni_set_cdo_dma_channel(dev, -1);
687 mite_release_channel(devpriv->cdo_mite_chan);
688 devpriv->cdo_mite_chan = NULL;
690 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
694 /* e-series boards use the second irq signals to generate dma requests for their counters */
696 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
697 unsigned gpct_index, short enable)
699 struct ni_private *devpriv = dev->private;
701 if (boardtype.reg_type & ni_reg_m_series_mask)
703 switch (gpct_index) {
706 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
707 Second_IRQ_A_Enable_Register);
709 devpriv->stc_writew(dev, 0,
710 Second_IRQ_A_Enable_Register);
715 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
716 Second_IRQ_B_Enable_Register);
718 devpriv->stc_writew(dev, 0,
719 Second_IRQ_B_Enable_Register);
729 static void ni_clear_ai_fifo(struct comedi_device *dev)
731 struct ni_private *devpriv = dev->private;
733 if (boardtype.reg_type == ni_reg_6143) {
734 /* Flush the 6143 data FIFO */
735 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
736 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
737 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
739 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
740 if (boardtype.reg_type == ni_reg_625x) {
741 ni_writeb(0, M_Offset_Static_AI_Control(0));
742 ni_writeb(1, M_Offset_Static_AI_Control(0));
744 /* the NI example code does 3 convert pulses for 625x boards,
745 but that appears to be wrong in practice. */
746 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
747 AI_Command_1_Register);
748 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
749 AI_Command_1_Register);
750 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
751 AI_Command_1_Register);
757 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
759 struct ni_private *devpriv = dev->private;
761 devpriv->stc_writew(dev, data >> 16, reg);
762 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
765 static uint32_t win_in2(struct comedi_device *dev, int reg)
767 struct ni_private *devpriv = dev->private;
770 bits = devpriv->stc_readw(dev, reg) << 16;
771 bits |= devpriv->stc_readw(dev, reg + 1);
775 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
776 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
779 struct ni_private *devpriv = dev->private;
782 spin_lock_irqsave(&devpriv->window_lock, flags);
783 ni_writew(addr, AO_Window_Address_611x);
784 ni_writew(data, AO_Window_Data_611x);
785 spin_unlock_irqrestore(&devpriv->window_lock, flags);
788 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
791 struct ni_private *devpriv = dev->private;
794 spin_lock_irqsave(&devpriv->window_lock, flags);
795 ni_writew(addr, AO_Window_Address_611x);
796 ni_writel(data, AO_Window_Data_611x);
797 spin_unlock_irqrestore(&devpriv->window_lock, flags);
800 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
802 struct ni_private *devpriv = dev->private;
806 spin_lock_irqsave(&devpriv->window_lock, flags);
807 ni_writew(addr, AO_Window_Address_611x);
808 data = ni_readw(AO_Window_Data_611x);
809 spin_unlock_irqrestore(&devpriv->window_lock, flags);
813 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
814 * share registers (such as Interrupt_A_Register) without interfering with
817 * NOTE: the switch/case statements are optimized out for a constant argument
818 * so this is actually quite fast--- If you must wrap another function around this
819 * make it inline to avoid a large speed penalty.
821 * value should only be 1 or 0.
823 static inline void ni_set_bits(struct comedi_device *dev, int reg,
824 unsigned bits, unsigned value)
832 ni_set_bitfield(dev, reg, bits, bit_values);
835 static irqreturn_t ni_E_interrupt(int irq, void *d)
837 struct comedi_device *dev = d;
838 struct ni_private *devpriv = dev->private;
839 unsigned short a_status;
840 unsigned short b_status;
841 unsigned int ai_mite_status = 0;
842 unsigned int ao_mite_status = 0;
845 struct mite_struct *mite = devpriv->mite;
848 if (dev->attached == 0)
850 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
852 /* lock to avoid race with comedi_poll */
853 spin_lock_irqsave(&dev->spinlock, flags);
854 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
855 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
858 unsigned long flags_too;
860 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
861 if (devpriv->ai_mite_chan) {
862 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
863 if (ai_mite_status & CHSR_LINKC)
865 devpriv->mite->mite_io_addr +
867 ai_mite_chan->channel));
869 if (devpriv->ao_mite_chan) {
870 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
871 if (ao_mite_status & CHSR_LINKC)
875 ao_mite_chan->channel));
877 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
880 ack_a_interrupt(dev, a_status);
881 ack_b_interrupt(dev, b_status);
882 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
883 handle_a_interrupt(dev, a_status, ai_mite_status);
884 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
885 handle_b_interrupt(dev, b_status, ao_mite_status);
886 handle_gpct_interrupt(dev, 0);
887 handle_gpct_interrupt(dev, 1);
888 handle_cdio_interrupt(dev);
890 spin_unlock_irqrestore(&dev->spinlock, flags);
895 static void ni_sync_ai_dma(struct comedi_device *dev)
897 struct ni_private *devpriv = dev->private;
898 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
901 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
902 if (devpriv->ai_mite_chan)
903 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
904 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
907 static void mite_handle_b_linkc(struct mite_struct *mite,
908 struct comedi_device *dev)
910 struct ni_private *devpriv = dev->private;
911 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
914 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
915 if (devpriv->ao_mite_chan) {
916 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
918 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
921 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
923 struct ni_private *devpriv = dev->private;
924 static const int timeout = 10000;
926 for (i = 0; i < timeout; i++) {
927 unsigned short b_status;
929 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
930 if (b_status & AO_FIFO_Half_Full_St)
932 /* if we poll too often, the pci bus activity seems
933 to slow the dma transfer down */
937 comedi_error(dev, "timed out waiting for dma load");
944 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
946 struct ni_private *devpriv = dev->private;
948 if (devpriv->aimode == AIMODE_SCAN) {
950 static const int timeout = 10;
953 for (i = 0; i < timeout; i++) {
955 if ((s->async->events & COMEDI_CB_EOS))
960 ni_handle_fifo_dregs(dev);
961 s->async->events |= COMEDI_CB_EOS;
964 /* handle special case of single scan using AI_End_On_End_Of_Scan */
965 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
966 shutdown_ai_command(dev);
970 static void shutdown_ai_command(struct comedi_device *dev)
972 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
975 ni_ai_drain_dma(dev);
977 ni_handle_fifo_dregs(dev);
978 get_last_sample_611x(dev);
979 get_last_sample_6143(dev);
981 s->async->events |= COMEDI_CB_EOA;
984 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
987 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
996 case NI_GPCT0_SUBDEV:
997 case NI_GPCT1_SUBDEV:
998 ni_gpct_cancel(dev, s);
1001 ni_cdio_cancel(dev, s);
1007 comedi_event(dev, s);
1010 static void handle_gpct_interrupt(struct comedi_device *dev,
1011 unsigned short counter_index)
1014 struct ni_private *devpriv = dev->private;
1015 struct comedi_subdevice *s;
1017 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1019 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1021 if (s->async->events)
1026 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1028 struct ni_private *devpriv = dev->private;
1029 unsigned short ack = 0;
1031 if (a_status & AI_SC_TC_St) {
1032 ack |= AI_SC_TC_Interrupt_Ack;
1034 if (a_status & AI_START1_St) {
1035 ack |= AI_START1_Interrupt_Ack;
1037 if (a_status & AI_START_St) {
1038 ack |= AI_START_Interrupt_Ack;
1040 if (a_status & AI_STOP_St) {
1041 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1042 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1045 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1048 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1049 unsigned ai_mite_status)
1051 struct ni_private *devpriv = dev->private;
1052 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1054 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1055 if (s->type == COMEDI_SUBD_UNUSED)
1058 #ifdef DEBUG_INTERRUPT
1060 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1061 status, ai_mite_status);
1062 ni_mio_print_status_a(status);
1065 if (ai_mite_status & CHSR_LINKC) {
1066 ni_sync_ai_dma(dev);
1069 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1070 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1071 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1073 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1075 /* mite_print_chsr(ai_mite_status); */
1076 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1077 /* disable_irq(dev->irq); */
1081 /* test for all uncommon interrupt events at the same time */
1082 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1083 AI_SC_TC_St | AI_START1_St)) {
1084 if (status == 0xffff) {
1086 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1087 /* we probably aren't even running a command now,
1088 * so it's a good idea to be careful. */
1089 if (comedi_is_subdevice_running(s)) {
1091 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1096 if (status & (AI_Overrun_St | AI_Overflow_St |
1097 AI_SC_TC_Error_St)) {
1098 printk("ni_mio_common: ai error a_status=%04x\n",
1100 ni_mio_print_status_a(status);
1102 shutdown_ai_command(dev);
1104 s->async->events |= COMEDI_CB_ERROR;
1105 if (status & (AI_Overrun_St | AI_Overflow_St))
1106 s->async->events |= COMEDI_CB_OVERFLOW;
1112 if (status & AI_SC_TC_St) {
1113 #ifdef DEBUG_INTERRUPT
1114 printk("ni_mio_common: SC_TC interrupt\n");
1116 if (!devpriv->ai_continuous) {
1117 shutdown_ai_command(dev);
1122 if (status & AI_FIFO_Half_Full_St) {
1124 static const int timeout = 10;
1125 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1126 *fail to get the fifo less than half full, so loop to be sure.*/
1127 for (i = 0; i < timeout; ++i) {
1128 ni_handle_fifo_half_full(dev);
1129 if ((devpriv->stc_readw(dev,
1130 AI_Status_1_Register) &
1131 AI_FIFO_Half_Full_St) == 0)
1135 #endif /* !PCIDMA */
1137 if ((status & AI_STOP_St)) {
1138 ni_handle_eos(dev, s);
1143 #ifdef DEBUG_INTERRUPT
1144 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1145 if (status & Interrupt_A_St) {
1147 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1153 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1155 struct ni_private *devpriv = dev->private;
1156 unsigned short ack = 0;
1158 if (b_status & AO_BC_TC_St) {
1159 ack |= AO_BC_TC_Interrupt_Ack;
1161 if (b_status & AO_Overrun_St) {
1162 ack |= AO_Error_Interrupt_Ack;
1164 if (b_status & AO_START_St) {
1165 ack |= AO_START_Interrupt_Ack;
1167 if (b_status & AO_START1_St) {
1168 ack |= AO_START1_Interrupt_Ack;
1170 if (b_status & AO_UC_TC_St) {
1171 ack |= AO_UC_TC_Interrupt_Ack;
1173 if (b_status & AO_UI2_TC_St) {
1174 ack |= AO_UI2_TC_Interrupt_Ack;
1176 if (b_status & AO_UPDATE_St) {
1177 ack |= AO_UPDATE_Interrupt_Ack;
1180 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1183 static void handle_b_interrupt(struct comedi_device *dev,
1184 unsigned short b_status, unsigned ao_mite_status)
1186 struct ni_private *devpriv = dev->private;
1187 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1188 /* unsigned short ack=0; */
1190 #ifdef DEBUG_INTERRUPT
1191 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1192 b_status, ao_mite_status);
1193 ni_mio_print_status_b(b_status);
1197 /* Currently, mite.c requires us to handle LINKC */
1198 if (ao_mite_status & CHSR_LINKC) {
1199 mite_handle_b_linkc(devpriv->mite, dev);
1202 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1203 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1204 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1206 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1208 /* mite_print_chsr(ao_mite_status); */
1209 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1213 if (b_status == 0xffff)
1215 if (b_status & AO_Overrun_St) {
1217 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1218 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1219 s->async->events |= COMEDI_CB_OVERFLOW;
1222 if (b_status & AO_BC_TC_St) {
1224 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1225 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1226 s->async->events |= COMEDI_CB_EOA;
1229 if (b_status & AO_FIFO_Request_St) {
1232 ret = ni_ao_fifo_half_empty(dev, s);
1234 printk("ni_mio_common: AO buffer underrun\n");
1235 ni_set_bits(dev, Interrupt_B_Enable_Register,
1236 AO_FIFO_Interrupt_Enable |
1237 AO_Error_Interrupt_Enable, 0);
1238 s->async->events |= COMEDI_CB_OVERFLOW;
1246 #ifdef DEBUG_STATUS_A
1247 static const char *const status_a_strings[] = {
1248 "passthru0", "fifo", "G0_gate", "G0_TC",
1249 "stop", "start", "sc_tc", "start1",
1250 "start2", "sc_tc_error", "overflow", "overrun",
1251 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1254 static void ni_mio_print_status_a(int status)
1258 printk("A status:");
1259 for (i = 15; i >= 0; i--) {
1260 if (status & (1 << i)) {
1261 printk(" %s", status_a_strings[i]);
1268 #ifdef DEBUG_STATUS_B
1269 static const char *const status_b_strings[] = {
1270 "passthru1", "fifo", "G1_gate", "G1_TC",
1271 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1272 "start1", "overrun", "start", "bc_tc_error",
1273 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1276 static void ni_mio_print_status_b(int status)
1280 printk("B status:");
1281 for (i = 15; i >= 0; i--) {
1282 if (status & (1 << i)) {
1283 printk(" %s", status_b_strings[i]);
1292 static void ni_ao_fifo_load(struct comedi_device *dev,
1293 struct comedi_subdevice *s, int n)
1295 struct comedi_async *async = s->async;
1296 struct comedi_cmd *cmd = &async->cmd;
1304 chan = async->cur_chan;
1305 for (i = 0; i < n; i++) {
1306 err &= comedi_buf_get(async, &d);
1310 range = CR_RANGE(cmd->chanlist[chan]);
1312 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1313 packed_data = d & 0xffff;
1314 /* 6711 only has 16 bit wide ao fifo */
1315 if (boardtype.reg_type != ni_reg_6711) {
1316 err &= comedi_buf_get(async, &d);
1321 packed_data |= (d << 16) & 0xffff0000;
1323 ni_writel(packed_data, DAC_FIFO_Data_611x);
1325 ni_writew(d, DAC_FIFO_Data);
1328 chan %= cmd->chanlist_len;
1330 async->cur_chan = chan;
1332 async->events |= COMEDI_CB_OVERFLOW;
1337 * There's a small problem if the FIFO gets really low and we
1338 * don't have the data to fill it. Basically, if after we fill
1339 * the FIFO with all the data available, the FIFO is _still_
1340 * less than half full, we never clear the interrupt. If the
1341 * IRQ is in edge mode, we never get another interrupt, because
1342 * this one wasn't cleared. If in level mode, we get flooded
1343 * with interrupts that we can't fulfill, because nothing ever
1344 * gets put into the buffer.
1346 * This kind of situation is recoverable, but it is easier to
1347 * just pretend we had a FIFO underrun, since there is a good
1348 * chance it will happen anyway. This is _not_ the case for
1349 * RT code, as RT code might purposely be running close to the
1350 * metal. Needs to be fixed eventually.
1352 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1353 struct comedi_subdevice *s)
1357 n = comedi_buf_read_n_available(s->async);
1359 s->async->events |= COMEDI_CB_OVERFLOW;
1364 if (n > boardtype.ao_fifo_depth / 2)
1365 n = boardtype.ao_fifo_depth / 2;
1367 ni_ao_fifo_load(dev, s, n);
1369 s->async->events |= COMEDI_CB_BLOCK;
1374 static int ni_ao_prep_fifo(struct comedi_device *dev,
1375 struct comedi_subdevice *s)
1377 struct ni_private *devpriv = dev->private;
1381 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1382 if (boardtype.reg_type & ni_reg_6xxx_mask)
1383 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1385 /* load some data */
1386 n = comedi_buf_read_n_available(s->async);
1391 if (n > boardtype.ao_fifo_depth)
1392 n = boardtype.ao_fifo_depth;
1394 ni_ao_fifo_load(dev, s, n);
1399 static void ni_ai_fifo_read(struct comedi_device *dev,
1400 struct comedi_subdevice *s, int n)
1402 struct ni_private *devpriv = dev->private;
1403 struct comedi_async *async = s->async;
1406 if (boardtype.reg_type == ni_reg_611x) {
1410 for (i = 0; i < n / 2; i++) {
1411 dl = ni_readl(ADC_FIFO_Data_611x);
1412 /* This may get the hi/lo data in the wrong order */
1413 data[0] = (dl >> 16) & 0xffff;
1414 data[1] = dl & 0xffff;
1415 cfc_write_array_to_buffer(s, data, sizeof(data));
1417 /* Check if there's a single sample stuck in the FIFO */
1419 dl = ni_readl(ADC_FIFO_Data_611x);
1420 data[0] = dl & 0xffff;
1421 cfc_write_to_buffer(s, data[0]);
1423 } else if (boardtype.reg_type == ni_reg_6143) {
1427 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1428 for (i = 0; i < n / 2; i++) {
1429 dl = ni_readl(AIFIFO_Data_6143);
1431 data[0] = (dl >> 16) & 0xffff;
1432 data[1] = dl & 0xffff;
1433 cfc_write_array_to_buffer(s, data, sizeof(data));
1436 /* Assume there is a single sample stuck in the FIFO */
1437 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1438 dl = ni_readl(AIFIFO_Data_6143);
1439 data[0] = (dl >> 16) & 0xffff;
1440 cfc_write_to_buffer(s, data[0]);
1443 if (n > sizeof(devpriv->ai_fifo_buffer) /
1444 sizeof(devpriv->ai_fifo_buffer[0])) {
1445 comedi_error(dev, "bug! ai_fifo_buffer too small");
1446 async->events |= COMEDI_CB_ERROR;
1449 for (i = 0; i < n; i++) {
1450 devpriv->ai_fifo_buffer[i] =
1451 ni_readw(ADC_FIFO_Data_Register);
1453 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1455 sizeof(devpriv->ai_fifo_buffer[0]));
1459 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1462 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1464 n = boardtype.ai_fifo_depth / 2;
1466 ni_ai_fifo_read(dev, s, n);
1471 static int ni_ai_drain_dma(struct comedi_device *dev)
1473 struct ni_private *devpriv = dev->private;
1475 static const int timeout = 10000;
1476 unsigned long flags;
1479 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1480 if (devpriv->ai_mite_chan) {
1481 for (i = 0; i < timeout; i++) {
1482 if ((devpriv->stc_readw(dev,
1483 AI_Status_1_Register) &
1485 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1491 printk("ni_mio_common: wait for dma drain timed out\n");
1493 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1494 mite_bytes_in_transit(devpriv->ai_mite_chan),
1495 devpriv->stc_readw(dev, AI_Status_1_Register));
1499 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1501 ni_sync_ai_dma(dev);
1509 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1511 struct ni_private *devpriv = dev->private;
1512 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1518 if (boardtype.reg_type == ni_reg_611x) {
1519 while ((devpriv->stc_readw(dev,
1520 AI_Status_1_Register) &
1521 AI_FIFO_Empty_St) == 0) {
1522 dl = ni_readl(ADC_FIFO_Data_611x);
1524 /* This may get the hi/lo data in the wrong order */
1525 data[0] = (dl >> 16);
1526 data[1] = (dl & 0xffff);
1527 cfc_write_array_to_buffer(s, data, sizeof(data));
1529 } else if (boardtype.reg_type == ni_reg_6143) {
1531 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1532 dl = ni_readl(AIFIFO_Data_6143);
1534 /* This may get the hi/lo data in the wrong order */
1535 data[0] = (dl >> 16);
1536 data[1] = (dl & 0xffff);
1537 cfc_write_array_to_buffer(s, data, sizeof(data));
1540 /* Check if stranded sample is present */
1541 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1542 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1543 dl = ni_readl(AIFIFO_Data_6143);
1544 data[0] = (dl >> 16) & 0xffff;
1545 cfc_write_to_buffer(s, data[0]);
1550 devpriv->stc_readw(dev,
1551 AI_Status_1_Register) & AI_FIFO_Empty_St;
1552 while (fifo_empty == 0) {
1555 sizeof(devpriv->ai_fifo_buffer) /
1556 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1558 devpriv->stc_readw(dev,
1559 AI_Status_1_Register) &
1563 devpriv->ai_fifo_buffer[i] =
1564 ni_readw(ADC_FIFO_Data_Register);
1566 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1569 ai_fifo_buffer[0]));
1574 static void get_last_sample_611x(struct comedi_device *dev)
1576 struct ni_private *devpriv __maybe_unused = dev->private;
1577 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1581 if (boardtype.reg_type != ni_reg_611x)
1584 /* Check if there's a single sample stuck in the FIFO */
1585 if (ni_readb(XXX_Status) & 0x80) {
1586 dl = ni_readl(ADC_FIFO_Data_611x);
1587 data = (dl & 0xffff);
1588 cfc_write_to_buffer(s, data);
1592 static void get_last_sample_6143(struct comedi_device *dev)
1594 struct ni_private *devpriv __maybe_unused = dev->private;
1595 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1599 if (boardtype.reg_type != ni_reg_6143)
1602 /* Check if there's a single sample stuck in the FIFO */
1603 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1604 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1605 dl = ni_readl(AIFIFO_Data_6143);
1607 /* This may get the hi/lo data in the wrong order */
1608 data = (dl >> 16) & 0xffff;
1609 cfc_write_to_buffer(s, data);
1613 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1614 void *data, unsigned int num_bytes,
1615 unsigned int chan_index)
1617 struct ni_private *devpriv = dev->private;
1618 struct comedi_async *async = s->async;
1620 unsigned int length = num_bytes / bytes_per_sample(s);
1621 short *array = data;
1622 unsigned int *larray = data;
1624 for (i = 0; i < length; i++) {
1626 if (s->subdev_flags & SDF_LSAMPL)
1627 larray[i] = le32_to_cpu(larray[i]);
1629 array[i] = le16_to_cpu(array[i]);
1631 if (s->subdev_flags & SDF_LSAMPL)
1632 larray[i] += devpriv->ai_offset[chan_index];
1634 array[i] += devpriv->ai_offset[chan_index];
1636 chan_index %= async->cmd.chanlist_len;
1642 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1644 struct ni_private *devpriv = dev->private;
1645 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1647 unsigned long flags;
1649 retval = ni_request_ai_mite_channel(dev);
1652 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1654 /* write alloc the entire buffer */
1655 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1657 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1658 if (devpriv->ai_mite_chan == NULL) {
1659 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1663 switch (boardtype.reg_type) {
1666 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1669 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1672 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1676 mite_dma_arm(devpriv->ai_mite_chan);
1677 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1682 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1684 struct ni_private *devpriv = dev->private;
1685 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1687 unsigned long flags;
1689 retval = ni_request_ao_mite_channel(dev);
1693 /* read alloc the entire buffer */
1694 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1696 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1697 if (devpriv->ao_mite_chan) {
1698 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1699 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1701 /* doing 32 instead of 16 bit wide transfers from memory
1702 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1703 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1705 mite_dma_arm(devpriv->ao_mite_chan);
1708 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1716 used for both cancel ioctl and board initialization
1718 this is pretty harsh for a cancel, but it works...
1721 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1723 struct ni_private *devpriv = dev->private;
1725 ni_release_ai_mite_channel(dev);
1726 /* ai configuration */
1727 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1728 Joint_Reset_Register);
1730 ni_set_bits(dev, Interrupt_A_Enable_Register,
1731 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1732 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1733 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1734 AI_FIFO_Interrupt_Enable, 0);
1736 ni_clear_ai_fifo(dev);
1738 if (boardtype.reg_type != ni_reg_6143)
1739 ni_writeb(0, Misc_Command);
1741 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1742 devpriv->stc_writew(dev,
1743 AI_Start_Stop | AI_Mode_1_Reserved
1744 /*| AI_Trigger_Once */ ,
1745 AI_Mode_1_Register);
1746 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1747 /* generate FIFO interrupts on non-empty */
1748 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1749 if (boardtype.reg_type == ni_reg_611x) {
1750 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1752 AI_LOCALMUX_CLK_Pulse_Width,
1753 AI_Personal_Register);
1754 devpriv->stc_writew(dev,
1755 AI_SCAN_IN_PROG_Output_Select(3) |
1756 AI_EXTMUX_CLK_Output_Select(0) |
1757 AI_LOCALMUX_CLK_Output_Select(2) |
1758 AI_SC_TC_Output_Select(3) |
1759 AI_CONVERT_Output_Select
1760 (AI_CONVERT_Output_Enable_High),
1761 AI_Output_Control_Register);
1762 } else if (boardtype.reg_type == ni_reg_6143) {
1763 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1765 AI_LOCALMUX_CLK_Pulse_Width,
1766 AI_Personal_Register);
1767 devpriv->stc_writew(dev,
1768 AI_SCAN_IN_PROG_Output_Select(3) |
1769 AI_EXTMUX_CLK_Output_Select(0) |
1770 AI_LOCALMUX_CLK_Output_Select(2) |
1771 AI_SC_TC_Output_Select(3) |
1772 AI_CONVERT_Output_Select
1773 (AI_CONVERT_Output_Enable_Low),
1774 AI_Output_Control_Register);
1776 unsigned ai_output_control_bits;
1777 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1779 AI_CONVERT_Pulse_Width |
1780 AI_LOCALMUX_CLK_Pulse_Width,
1781 AI_Personal_Register);
1782 ai_output_control_bits =
1783 AI_SCAN_IN_PROG_Output_Select(3) |
1784 AI_EXTMUX_CLK_Output_Select(0) |
1785 AI_LOCALMUX_CLK_Output_Select(2) |
1786 AI_SC_TC_Output_Select(3);
1787 if (boardtype.reg_type == ni_reg_622x)
1788 ai_output_control_bits |=
1789 AI_CONVERT_Output_Select
1790 (AI_CONVERT_Output_Enable_High);
1792 ai_output_control_bits |=
1793 AI_CONVERT_Output_Select
1794 (AI_CONVERT_Output_Enable_Low);
1795 devpriv->stc_writew(dev, ai_output_control_bits,
1796 AI_Output_Control_Register);
1798 /* the following registers should not be changed, because there
1799 * are no backup registers in devpriv. If you want to change
1800 * any of these, add a backup register and other appropriate code:
1801 * AI_Mode_1_Register
1802 * AI_Mode_3_Register
1803 * AI_Personal_Register
1804 * AI_Output_Control_Register
1806 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1808 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1813 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1815 unsigned long flags;
1818 /* lock to avoid race with interrupt handler */
1819 spin_lock_irqsave(&dev->spinlock, flags);
1821 ni_handle_fifo_dregs(dev);
1823 ni_sync_ai_dma(dev);
1825 count = s->async->buf_write_count - s->async->buf_read_count;
1826 spin_unlock_irqrestore(&dev->spinlock, flags);
1831 static int ni_ai_insn_read(struct comedi_device *dev,
1832 struct comedi_subdevice *s, struct comedi_insn *insn,
1835 struct ni_private *devpriv = dev->private;
1837 const unsigned int mask = (1 << boardtype.adbits) - 1;
1842 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1844 ni_clear_ai_fifo(dev);
1846 signbits = devpriv->ai_offset[0];
1847 if (boardtype.reg_type == ni_reg_611x) {
1848 for (n = 0; n < num_adc_stages_611x; n++) {
1849 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1850 AI_Command_1_Register);
1853 for (n = 0; n < insn->n; n++) {
1854 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1855 AI_Command_1_Register);
1856 /* The 611x has screwy 32-bit FIFOs. */
1858 for (i = 0; i < NI_TIMEOUT; i++) {
1859 if (ni_readb(XXX_Status) & 0x80) {
1860 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1864 if (!(devpriv->stc_readw(dev,
1865 AI_Status_1_Register) &
1866 AI_FIFO_Empty_St)) {
1867 d = ni_readl(ADC_FIFO_Data_611x) &
1872 if (i == NI_TIMEOUT) {
1874 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1880 } else if (boardtype.reg_type == ni_reg_6143) {
1881 for (n = 0; n < insn->n; n++) {
1882 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1883 AI_Command_1_Register);
1885 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1887 for (i = 0; i < NI_TIMEOUT; i++) {
1888 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1889 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1890 dl = ni_readl(AIFIFO_Data_6143);
1894 if (i == NI_TIMEOUT) {
1896 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1899 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1902 for (n = 0; n < insn->n; n++) {
1903 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1904 AI_Command_1_Register);
1905 for (i = 0; i < NI_TIMEOUT; i++) {
1906 if (!(devpriv->stc_readw(dev,
1907 AI_Status_1_Register) &
1911 if (i == NI_TIMEOUT) {
1913 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1916 if (boardtype.reg_type & ni_reg_m_series_mask) {
1918 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1920 d = ni_readw(ADC_FIFO_Data_Register);
1921 d += signbits; /* subtle: needs to be short addition */
1929 static void ni_prime_channelgain_list(struct comedi_device *dev)
1931 struct ni_private *devpriv = dev->private;
1934 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1935 for (i = 0; i < NI_TIMEOUT; ++i) {
1936 if (!(devpriv->stc_readw(dev,
1937 AI_Status_1_Register) &
1938 AI_FIFO_Empty_St)) {
1939 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1944 printk("ni_mio_common: timeout loading channel/gain list\n");
1947 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1948 unsigned int n_chan,
1951 struct ni_private *devpriv = dev->private;
1952 unsigned int chan, range, aref;
1955 unsigned int dither;
1956 unsigned range_code;
1958 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1960 /* offset = 1 << (boardtype.adbits - 1); */
1961 if ((list[0] & CR_ALT_SOURCE)) {
1962 unsigned bypass_bits;
1963 chan = CR_CHAN(list[0]);
1964 range = CR_RANGE(list[0]);
1965 range_code = ni_gainlkup[boardtype.gainlkup][range];
1966 dither = ((list[0] & CR_ALT_FILTER) != 0);
1967 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1968 bypass_bits |= chan;
1970 (devpriv->ai_calib_source) &
1971 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1972 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1973 MSeries_AI_Bypass_Mode_Mux_Mask |
1974 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1975 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1977 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1978 /* don't use 2's complement encoding */
1979 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1980 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1982 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1985 for (i = 0; i < n_chan; i++) {
1986 unsigned config_bits = 0;
1987 chan = CR_CHAN(list[i]);
1988 aref = CR_AREF(list[i]);
1989 range = CR_RANGE(list[i]);
1990 dither = ((list[i] & CR_ALT_FILTER) != 0);
1992 range_code = ni_gainlkup[boardtype.gainlkup][range];
1993 devpriv->ai_offset[i] = offset;
1997 MSeries_AI_Config_Channel_Type_Differential_Bits;
2001 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2005 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2010 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2012 MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
2013 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2014 if (i == n_chan - 1)
2015 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2017 config_bits |= MSeries_AI_Config_Dither_Bit;
2018 /* don't use 2's complement encoding */
2019 config_bits |= MSeries_AI_Config_Polarity_Bit;
2020 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2022 ni_prime_channelgain_list(dev);
2026 * Notes on the 6110 and 6111:
2027 * These boards a slightly different than the rest of the series, since
2028 * they have multiple A/D converters.
2029 * From the driver side, the configuration memory is a
2031 * Configuration Memory Low:
2033 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2034 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2035 * 1001 gain=0.1 (+/- 50)
2044 * Configuration Memory High:
2045 * bits 12-14: Channel Type
2046 * 001 for differential
2047 * 000 for calibration
2048 * bit 11: coupling (this is not currently handled)
2052 * valid channels are 0-3
2054 static void ni_load_channelgain_list(struct comedi_device *dev,
2055 unsigned int n_chan, unsigned int *list)
2057 struct ni_private *devpriv = dev->private;
2058 unsigned int chan, range, aref;
2060 unsigned int hi, lo;
2062 unsigned int dither;
2064 if (boardtype.reg_type & ni_reg_m_series_mask) {
2065 ni_m_series_load_channelgain_list(dev, n_chan, list);
2068 if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
2069 && (boardtype.reg_type != ni_reg_6143)) {
2070 if (devpriv->changain_state
2071 && devpriv->changain_spec == list[0]) {
2075 devpriv->changain_state = 1;
2076 devpriv->changain_spec = list[0];
2078 devpriv->changain_state = 0;
2081 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2083 /* Set up Calibration mode if required */
2084 if (boardtype.reg_type == ni_reg_6143) {
2085 if ((list[0] & CR_ALT_SOURCE)
2086 && !devpriv->ai_calib_source_enabled) {
2087 /* Strobe Relay enable bit */
2088 ni_writew(devpriv->ai_calib_source |
2089 Calibration_Channel_6143_RelayOn,
2090 Calibration_Channel_6143);
2091 ni_writew(devpriv->ai_calib_source,
2092 Calibration_Channel_6143);
2093 devpriv->ai_calib_source_enabled = 1;
2094 msleep_interruptible(100); /* Allow relays to change */
2095 } else if (!(list[0] & CR_ALT_SOURCE)
2096 && devpriv->ai_calib_source_enabled) {
2097 /* Strobe Relay disable bit */
2098 ni_writew(devpriv->ai_calib_source |
2099 Calibration_Channel_6143_RelayOff,
2100 Calibration_Channel_6143);
2101 ni_writew(devpriv->ai_calib_source,
2102 Calibration_Channel_6143);
2103 devpriv->ai_calib_source_enabled = 0;
2104 msleep_interruptible(100); /* Allow relays to change */
2108 offset = 1 << (boardtype.adbits - 1);
2109 for (i = 0; i < n_chan; i++) {
2110 if ((boardtype.reg_type != ni_reg_6143)
2111 && (list[i] & CR_ALT_SOURCE)) {
2112 chan = devpriv->ai_calib_source;
2114 chan = CR_CHAN(list[i]);
2116 aref = CR_AREF(list[i]);
2117 range = CR_RANGE(list[i]);
2118 dither = ((list[i] & CR_ALT_FILTER) != 0);
2120 /* fix the external/internal range differences */
2121 range = ni_gainlkup[boardtype.gainlkup][range];
2122 if (boardtype.reg_type == ni_reg_611x)
2123 devpriv->ai_offset[i] = offset;
2125 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2128 if ((list[i] & CR_ALT_SOURCE)) {
2129 if (boardtype.reg_type == ni_reg_611x)
2130 ni_writew(CR_CHAN(list[i]) & 0x0003,
2131 Calibration_Channel_Select_611x);
2133 if (boardtype.reg_type == ni_reg_611x)
2135 else if (boardtype.reg_type == ni_reg_6143)
2139 hi |= AI_DIFFERENTIAL;
2151 hi |= AI_CONFIG_CHANNEL(chan);
2153 ni_writew(hi, Configuration_Memory_High);
2155 if (boardtype.reg_type != ni_reg_6143) {
2157 if (i == n_chan - 1)
2158 lo |= AI_LAST_CHANNEL;
2162 ni_writew(lo, Configuration_Memory_Low);
2166 /* prime the channel/gain list */
2167 if ((boardtype.reg_type != ni_reg_611x)
2168 && (boardtype.reg_type != ni_reg_6143)) {
2169 ni_prime_channelgain_list(dev);
2173 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2176 struct ni_private *devpriv = dev->private;
2179 switch (round_mode) {
2180 case TRIG_ROUND_NEAREST:
2182 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2184 case TRIG_ROUND_DOWN:
2185 divider = (nanosec) / devpriv->clock_ns;
2188 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2194 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2196 struct ni_private *devpriv = dev->private;
2198 return devpriv->clock_ns * (timer + 1);
2201 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2202 unsigned num_channels)
2204 switch (boardtype.reg_type) {
2207 /* simultaneously-sampled inputs */
2208 return boardtype.ai_speed;
2211 /* multiplexed inputs */
2214 return boardtype.ai_speed * num_channels;
2217 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2218 struct comedi_cmd *cmd)
2220 struct ni_private *devpriv = dev->private;
2223 unsigned int sources;
2225 /* Step 1 : check if triggers are trivially valid */
2227 if ((cmd->flags & CMDF_WRITE))
2228 cmd->flags &= ~CMDF_WRITE;
2230 err |= cfc_check_trigger_src(&cmd->start_src,
2231 TRIG_NOW | TRIG_INT | TRIG_EXT);
2232 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2233 TRIG_TIMER | TRIG_EXT);
2235 sources = TRIG_TIMER | TRIG_EXT;
2236 if (boardtype.reg_type == ni_reg_611x ||
2237 boardtype.reg_type == ni_reg_6143)
2238 sources |= TRIG_NOW;
2239 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2241 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2242 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2247 /* Step 2a : make sure trigger sources are unique */
2249 err |= cfc_check_trigger_is_unique(cmd->start_src);
2250 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2251 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2252 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2254 /* Step 2b : and mutually compatible */
2259 /* Step 3: check if arguments are trivially valid */
2261 if (cmd->start_src == TRIG_EXT) {
2262 /* external trigger */
2263 unsigned int tmp = CR_CHAN(cmd->start_arg);
2267 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2268 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2270 /* true for both TRIG_NOW and TRIG_INT */
2271 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2274 if (cmd->scan_begin_src == TRIG_TIMER) {
2275 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2276 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2277 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2278 devpriv->clock_ns * 0xffffff);
2279 } else if (cmd->scan_begin_src == TRIG_EXT) {
2280 /* external trigger */
2281 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2285 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2286 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2287 } else { /* TRIG_OTHER */
2288 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2291 if (cmd->convert_src == TRIG_TIMER) {
2292 if ((boardtype.reg_type == ni_reg_611x)
2293 || (boardtype.reg_type == ni_reg_6143)) {
2294 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2296 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2297 boardtype.ai_speed);
2298 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2299 devpriv->clock_ns * 0xffff);
2301 } else if (cmd->convert_src == TRIG_EXT) {
2302 /* external trigger */
2303 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2307 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2308 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2309 } else if (cmd->convert_src == TRIG_NOW) {
2310 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2313 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2315 if (cmd->stop_src == TRIG_COUNT) {
2316 unsigned int max_count = 0x01000000;
2318 if (boardtype.reg_type == ni_reg_611x)
2319 max_count -= num_adc_stages_611x;
2320 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2321 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2324 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2330 /* step 4: fix up any arguments */
2332 if (cmd->scan_begin_src == TRIG_TIMER) {
2333 tmp = cmd->scan_begin_arg;
2334 cmd->scan_begin_arg =
2335 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2336 cmd->scan_begin_arg,
2340 if (tmp != cmd->scan_begin_arg)
2343 if (cmd->convert_src == TRIG_TIMER) {
2344 if ((boardtype.reg_type != ni_reg_611x)
2345 && (boardtype.reg_type != ni_reg_6143)) {
2346 tmp = cmd->convert_arg;
2348 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2353 if (tmp != cmd->convert_arg)
2355 if (cmd->scan_begin_src == TRIG_TIMER &&
2356 cmd->scan_begin_arg <
2357 cmd->convert_arg * cmd->scan_end_arg) {
2358 cmd->scan_begin_arg =
2359 cmd->convert_arg * cmd->scan_end_arg;
2371 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2373 struct ni_private *devpriv = dev->private;
2374 const struct comedi_cmd *cmd = &s->async->cmd;
2376 int mode1 = 0; /* mode1 is needed for both stop and convert */
2378 int start_stop_select = 0;
2379 unsigned int stop_count;
2380 int interrupt_a_enable = 0;
2382 MDPRINTK("ni_ai_cmd\n");
2383 if (dev->irq == 0) {
2384 comedi_error(dev, "cannot run command without an irq");
2387 ni_clear_ai_fifo(dev);
2389 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2391 /* start configuration */
2392 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2394 /* disable analog triggering for now, since it
2395 * interferes with the use of pfi0 */
2396 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2397 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2398 Analog_Trigger_Etc_Register);
2400 switch (cmd->start_src) {
2403 devpriv->stc_writew(dev, AI_START2_Select(0) |
2404 AI_START1_Sync | AI_START1_Edge |
2405 AI_START1_Select(0),
2406 AI_Trigger_Select_Register);
2410 int chan = CR_CHAN(cmd->start_arg);
2411 unsigned int bits = AI_START2_Select(0) |
2412 AI_START1_Sync | AI_START1_Select(chan + 1);
2414 if (cmd->start_arg & CR_INVERT)
2415 bits |= AI_START1_Polarity;
2416 if (cmd->start_arg & CR_EDGE)
2417 bits |= AI_START1_Edge;
2418 devpriv->stc_writew(dev, bits,
2419 AI_Trigger_Select_Register);
2424 mode2 &= ~AI_Pre_Trigger;
2425 mode2 &= ~AI_SC_Initial_Load_Source;
2426 mode2 &= ~AI_SC_Reload_Mode;
2427 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2429 if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2430 || (boardtype.reg_type == ni_reg_6143)) {
2431 start_stop_select |= AI_STOP_Polarity;
2432 start_stop_select |= AI_STOP_Select(31); /* logic low */
2433 start_stop_select |= AI_STOP_Sync;
2435 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2437 devpriv->stc_writew(dev, start_stop_select,
2438 AI_START_STOP_Select_Register);
2440 devpriv->ai_cmd2 = 0;
2441 switch (cmd->stop_src) {
2443 stop_count = cmd->stop_arg - 1;
2445 if (boardtype.reg_type == ni_reg_611x) {
2446 /* have to take 3 stage adc pipeline into account */
2447 stop_count += num_adc_stages_611x;
2449 /* stage number of scans */
2450 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2452 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2453 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2454 /* load SC (Scan Count) */
2455 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2457 devpriv->ai_continuous = 0;
2458 if (stop_count == 0) {
2459 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2460 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2461 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2462 if (cmd->chanlist_len > 1)
2463 start_stop_select |=
2464 AI_STOP_Polarity | AI_STOP_Edge;
2468 /* stage number of scans */
2469 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2471 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2472 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2474 /* load SC (Scan Count) */
2475 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2477 devpriv->ai_continuous = 1;
2482 switch (cmd->scan_begin_src) {
2485 stop bits for non 611x boards
2486 AI_SI_Special_Trigger_Delay=0
2488 AI_START_STOP_Select_Register:
2489 AI_START_Polarity=0 (?) rising edge
2490 AI_START_Edge=1 edge triggered
2492 AI_START_Select=0 SI_TC
2493 AI_STOP_Polarity=0 rising edge
2494 AI_STOP_Edge=0 level
2496 AI_STOP_Select=19 external pin (configuration mem)
2498 start_stop_select |= AI_START_Edge | AI_START_Sync;
2499 devpriv->stc_writew(dev, start_stop_select,
2500 AI_START_STOP_Select_Register);
2502 mode2 |= AI_SI_Reload_Mode(0);
2503 /* AI_SI_Initial_Load_Source=A */
2504 mode2 &= ~AI_SI_Initial_Load_Source;
2505 /* mode2 |= AI_SC_Reload_Mode; */
2506 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2509 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2510 TRIG_ROUND_NEAREST);
2511 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2512 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2515 if (cmd->scan_begin_arg & CR_EDGE)
2516 start_stop_select |= AI_START_Edge;
2517 /* AI_START_Polarity==1 is falling edge */
2518 if (cmd->scan_begin_arg & CR_INVERT)
2519 start_stop_select |= AI_START_Polarity;
2520 if (cmd->scan_begin_src != cmd->convert_src ||
2521 (cmd->scan_begin_arg & ~CR_EDGE) !=
2522 (cmd->convert_arg & ~CR_EDGE))
2523 start_stop_select |= AI_START_Sync;
2524 start_stop_select |=
2525 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2526 devpriv->stc_writew(dev, start_stop_select,
2527 AI_START_STOP_Select_Register);
2531 switch (cmd->convert_src) {
2534 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2537 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2538 TRIG_ROUND_NEAREST);
2539 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2540 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2542 /* AI_SI2_Reload_Mode = alternate */
2543 /* AI_SI2_Initial_Load_Source = A */
2544 mode2 &= ~AI_SI2_Initial_Load_Source;
2545 mode2 |= AI_SI2_Reload_Mode;
2546 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2549 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2551 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2552 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2554 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2557 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2558 if ((cmd->convert_arg & CR_INVERT) == 0)
2559 mode1 |= AI_CONVERT_Source_Polarity;
2560 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2562 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2563 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2570 /* interrupt on FIFO, errors, SC_TC */
2571 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2572 AI_SC_TC_Interrupt_Enable;
2575 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2578 if (cmd->flags & TRIG_WAKE_EOS
2579 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2580 /* wake on end-of-scan */
2581 devpriv->aimode = AIMODE_SCAN;
2583 devpriv->aimode = AIMODE_HALF_FULL;
2586 switch (devpriv->aimode) {
2587 case AIMODE_HALF_FULL:
2588 /*generate FIFO interrupts and DMA requests on half-full */
2590 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2591 AI_Mode_3_Register);
2593 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2594 AI_Mode_3_Register);
2598 /*generate FIFO interrupts on non-empty */
2599 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2600 AI_Mode_3_Register);
2604 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2605 AI_Mode_3_Register);
2607 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2608 AI_Mode_3_Register);
2610 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2616 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2618 ni_set_bits(dev, Interrupt_A_Enable_Register,
2619 interrupt_a_enable, 1);
2621 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2622 devpriv->int_a_enable_reg);
2624 /* interrupt on nothing */
2625 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2627 /* XXX start polling if necessary */
2628 MDPRINTK("interrupting on nothing\n");
2631 /* end configuration */
2632 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2634 switch (cmd->scan_begin_src) {
2636 devpriv->stc_writew(dev,
2637 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2638 AI_SC_Arm, AI_Command_1_Register);
2641 /* XXX AI_SI_Arm? */
2642 devpriv->stc_writew(dev,
2643 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2644 AI_SC_Arm, AI_Command_1_Register);
2650 int retval = ni_ai_setup_MITE_dma(dev);
2654 /* mite_dump_regs(devpriv->mite); */
2657 switch (cmd->start_src) {
2659 /* AI_START1_Pulse */
2660 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2661 AI_Command_2_Register);
2662 s->async->inttrig = NULL;
2665 s->async->inttrig = NULL;
2668 s->async->inttrig = &ni_ai_inttrig;
2672 MDPRINTK("exit ni_ai_cmd\n");
2677 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2678 unsigned int trignum)
2680 struct ni_private *devpriv = dev->private;
2685 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2686 AI_Command_2_Register);
2687 s->async->inttrig = NULL;
2692 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2693 struct comedi_subdevice *s,
2694 struct comedi_insn *insn,
2695 unsigned int *data);
2697 static int ni_ai_insn_config(struct comedi_device *dev,
2698 struct comedi_subdevice *s,
2699 struct comedi_insn *insn, unsigned int *data)
2701 struct ni_private *devpriv = dev->private;
2707 case INSN_CONFIG_ANALOG_TRIG:
2708 return ni_ai_config_analog_trig(dev, s, insn, data);
2709 case INSN_CONFIG_ALT_SOURCE:
2710 if (boardtype.reg_type & ni_reg_m_series_mask) {
2711 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2712 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2713 MSeries_AI_Bypass_Mode_Mux_Mask |
2714 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2717 devpriv->ai_calib_source = data[1];
2718 } else if (boardtype.reg_type == ni_reg_6143) {
2719 unsigned int calib_source;
2721 calib_source = data[1] & 0xf;
2723 if (calib_source > 0xF)
2726 devpriv->ai_calib_source = calib_source;
2727 ni_writew(calib_source, Calibration_Channel_6143);
2729 unsigned int calib_source;
2730 unsigned int calib_source_adjust;
2732 calib_source = data[1] & 0xf;
2733 calib_source_adjust = (data[1] >> 4) & 0xff;
2735 if (calib_source >= 8)
2737 devpriv->ai_calib_source = calib_source;
2738 if (boardtype.reg_type == ni_reg_611x) {
2739 ni_writeb(calib_source_adjust,
2740 Cal_Gain_Select_611x);
2751 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2752 struct comedi_subdevice *s,
2753 struct comedi_insn *insn,
2756 struct ni_private *devpriv = dev->private;
2757 unsigned int a, b, modebits;
2761 * data[2] is analog line
2762 * data[3] is set level
2763 * data[4] is reset level */
2764 if (!boardtype.has_analog_trig)
2766 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2767 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2770 if (data[2] >= boardtype.n_adchan) {
2771 data[2] = boardtype.n_adchan - 1;
2774 if (data[3] > 255) { /* a */
2778 if (data[4] > 255) { /* b */
2789 * high mode 00 00 01 10
2790 * low mode 00 00 10 01
2792 * hysteresis low mode 10 00 00 01
2793 * hysteresis high mode 01 00 00 10
2794 * middle mode 10 01 01 10
2799 modebits = data[1] & 0xff;
2800 if (modebits & 0xf0) {
2801 /* two level mode */
2807 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2809 devpriv->atrig_low = a;
2810 devpriv->atrig_high = b;
2812 case 0x81: /* low hysteresis mode */
2813 devpriv->atrig_mode = 6;
2815 case 0x42: /* high hysteresis mode */
2816 devpriv->atrig_mode = 3;
2818 case 0x96: /* middle window mode */
2819 devpriv->atrig_mode = 2;
2826 /* one level mode */
2832 case 0x06: /* high window mode */
2833 devpriv->atrig_high = a;
2834 devpriv->atrig_mode = 0;
2836 case 0x09: /* low window mode */
2837 devpriv->atrig_low = a;
2838 devpriv->atrig_mode = 1;
2850 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2851 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2852 void *data, unsigned int num_bytes,
2853 unsigned int chan_index)
2855 struct comedi_async *async = s->async;
2858 unsigned int offset;
2859 unsigned int length = num_bytes / sizeof(short);
2860 short *array = data;
2862 offset = 1 << (boardtype.aobits - 1);
2863 for (i = 0; i < length; i++) {
2864 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2865 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2868 array[i] = cpu_to_le16(array[i]);
2871 chan_index %= async->cmd.chanlist_len;
2875 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2876 struct comedi_subdevice *s,
2877 unsigned int chanspec[],
2878 unsigned int n_chans, int timed)
2880 struct ni_private *devpriv = dev->private;
2888 for (i = 0; i < boardtype.n_aochan; ++i) {
2889 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2890 ni_writeb(devpriv->ao_conf[i],
2891 M_Offset_AO_Config_Bank(i));
2892 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2895 for (i = 0; i < n_chans; i++) {
2896 const struct comedi_krange *krange;
2897 chan = CR_CHAN(chanspec[i]);
2898 range = CR_RANGE(chanspec[i]);
2899 krange = s->range_table->range + range;
2902 switch (krange->max - krange->min) {
2904 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2905 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2908 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2909 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2912 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2913 ni_writeb(MSeries_Attenuate_x5_Bit,
2914 M_Offset_AO_Reference_Attenuation(chan));
2917 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2918 ni_writeb(MSeries_Attenuate_x5_Bit,
2919 M_Offset_AO_Reference_Attenuation(chan));
2922 printk("%s: bug! unhandled ao reference voltage\n",
2926 switch (krange->max + krange->min) {
2928 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2931 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2934 printk("%s: bug! unhandled ao offset voltage\n",
2939 conf |= MSeries_AO_Update_Timed_Bit;
2940 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2941 devpriv->ao_conf[chan] = conf;
2942 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2947 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2948 struct comedi_subdevice *s,
2949 unsigned int chanspec[],
2950 unsigned int n_chans)
2952 struct ni_private *devpriv = dev->private;
2959 for (i = 0; i < n_chans; i++) {
2960 chan = CR_CHAN(chanspec[i]);
2961 range = CR_RANGE(chanspec[i]);
2962 conf = AO_Channel(chan);
2964 if (boardtype.ao_unipolar) {
2965 if ((range & 1) == 0) {
2967 invert = (1 << (boardtype.aobits - 1));
2975 invert = (1 << (boardtype.aobits - 1));
2978 /* not all boards can deglitch, but this shouldn't hurt */
2979 if (chanspec[i] & CR_DEGLITCH)
2980 conf |= AO_Deglitch;
2982 /* analog reference */
2983 /* AREF_OTHER connects AO ground to AI ground, i think */
2984 conf |= (CR_AREF(chanspec[i]) ==
2985 AREF_OTHER) ? AO_Ground_Ref : 0;
2987 ni_writew(conf, AO_Configuration);
2988 devpriv->ao_conf[chan] = conf;
2993 static int ni_ao_config_chanlist(struct comedi_device *dev,
2994 struct comedi_subdevice *s,
2995 unsigned int chanspec[], unsigned int n_chans,
2998 if (boardtype.reg_type & ni_reg_m_series_mask)
2999 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3002 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3005 static int ni_ao_insn_read(struct comedi_device *dev,
3006 struct comedi_subdevice *s, struct comedi_insn *insn,
3009 struct ni_private *devpriv = dev->private;
3011 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3016 static int ni_ao_insn_write(struct comedi_device *dev,
3017 struct comedi_subdevice *s,
3018 struct comedi_insn *insn, unsigned int *data)
3020 struct ni_private *devpriv = dev->private;
3021 unsigned int chan = CR_CHAN(insn->chanspec);
3022 unsigned int invert;
3024 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3026 devpriv->ao[chan] = data[0];
3028 if (boardtype.reg_type & ni_reg_m_series_mask) {
3029 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3031 ni_writew(data[0] ^ invert,
3032 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3037 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3038 struct comedi_subdevice *s,
3039 struct comedi_insn *insn, unsigned int *data)
3041 struct ni_private *devpriv = dev->private;
3042 unsigned int chan = CR_CHAN(insn->chanspec);
3043 unsigned int invert;
3045 ao_win_out(1 << chan, AO_Immediate_671x);
3046 invert = 1 << (boardtype.aobits - 1);
3048 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3050 devpriv->ao[chan] = data[0];
3051 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3056 static int ni_ao_insn_config(struct comedi_device *dev,
3057 struct comedi_subdevice *s,
3058 struct comedi_insn *insn, unsigned int *data)
3060 struct ni_private *devpriv = dev->private;
3063 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3066 data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short);
3068 data[2] += devpriv->mite->fifo_size;
3085 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3086 unsigned int trignum)
3088 struct ni_private *devpriv = dev->private;
3090 int interrupt_b_bits;
3092 static const int timeout = 1000;
3097 /* Null trig at beginning prevent ao start trigger from executing more than
3098 once per command (and doing things like trying to allocate the ao dma channel
3100 s->async->inttrig = NULL;
3102 ni_set_bits(dev, Interrupt_B_Enable_Register,
3103 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3104 interrupt_b_bits = AO_Error_Interrupt_Enable;
3106 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3107 if (boardtype.reg_type & ni_reg_6xxx_mask)
3108 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3109 ret = ni_ao_setup_MITE_dma(dev);
3112 ret = ni_ao_wait_for_dma_load(dev);
3116 ret = ni_ao_prep_fifo(dev, s);
3120 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3123 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3124 AO_Mode_3_Register);
3125 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3126 /* wait for DACs to be loaded */
3127 for (i = 0; i < timeout; i++) {
3129 if ((devpriv->stc_readw(dev,
3130 Joint_Status_2_Register) &
3131 AO_TMRDACWRs_In_Progress_St) == 0)
3136 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3139 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3140 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3141 Interrupt_B_Ack_Register);
3143 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3145 devpriv->stc_writew(dev,
3146 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3147 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3148 AO_Command_1_Register);
3150 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3151 AO_Command_2_Register);
3156 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3158 struct ni_private *devpriv = dev->private;
3159 const struct comedi_cmd *cmd = &s->async->cmd;
3164 if (dev->irq == 0) {
3165 comedi_error(dev, "cannot run command without an irq");
3169 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3171 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3173 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3174 ao_win_out(CLEAR_WG, AO_Misc_611x);
3177 for (i = 0; i < cmd->chanlist_len; i++) {
3180 chan = CR_CHAN(cmd->chanlist[i]);
3182 ao_win_out(chan, AO_Waveform_Generation_611x);
3184 ao_win_out(bits, AO_Timed_611x);
3187 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3189 if (cmd->stop_src == TRIG_NONE) {
3190 devpriv->ao_mode1 |= AO_Continuous;
3191 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3193 devpriv->ao_mode1 &= ~AO_Continuous;
3194 devpriv->ao_mode1 |= AO_Trigger_Once;
3196 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3197 switch (cmd->start_src) {
3200 devpriv->ao_trigger_select &=
3201 ~(AO_START1_Polarity | AO_START1_Select(-1));
3202 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3203 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3204 AO_Trigger_Select_Register);
3207 devpriv->ao_trigger_select =
3208 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3209 if (cmd->start_arg & CR_INVERT)
3210 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3211 if (cmd->start_arg & CR_EDGE)
3212 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3213 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3214 AO_Trigger_Select_Register);
3220 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3221 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3223 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3224 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3225 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3226 if (cmd->stop_src == TRIG_NONE) {
3227 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3229 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3231 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3232 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3233 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3234 switch (cmd->stop_src) {
3236 if (boardtype.reg_type & ni_reg_m_series_mask) {
3237 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3238 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3239 AO_UC_Load_A_Register);
3240 devpriv->stc_writew(dev, AO_UC_Load,
3241 AO_Command_1_Register);
3243 devpriv->stc_writel(dev, cmd->stop_arg,
3244 AO_UC_Load_A_Register);
3245 devpriv->stc_writew(dev, AO_UC_Load,
3246 AO_Command_1_Register);
3247 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3248 AO_UC_Load_A_Register);
3252 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3253 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3254 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3257 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3258 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3259 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3262 devpriv->ao_mode1 &=
3263 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3264 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3265 switch (cmd->scan_begin_src) {
3267 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3269 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3270 TRIG_ROUND_NEAREST);
3271 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3272 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3273 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3276 devpriv->ao_mode1 |=
3277 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3278 if (cmd->scan_begin_arg & CR_INVERT)
3279 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3280 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3286 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3287 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3288 devpriv->ao_mode2 &=
3289 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3290 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3292 if (cmd->scan_end_arg > 1) {
3293 devpriv->ao_mode1 |= AO_Multiple_Channels;
3294 devpriv->stc_writew(dev,
3295 AO_Number_Of_Channels(cmd->scan_end_arg -
3297 AO_UPDATE_Output_Select
3298 (AO_Update_Output_High_Z),
3299 AO_Output_Control_Register);
3302 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3303 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3305 reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3306 bits |= AO_Number_Of_Channels(0);
3309 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3311 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3313 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3315 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3316 AO_Command_1_Register);
3318 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3319 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3321 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3323 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3325 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3327 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3328 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3330 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3331 AO_TMRDACWR_Pulse_Width;
3332 if (boardtype.ao_fifo_depth)
3333 bits |= AO_FIFO_Enable;
3335 bits |= AO_DMA_PIO_Control;
3337 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3338 verified with bus analyzer. */
3339 if (boardtype.reg_type & ni_reg_m_series_mask)
3340 bits |= AO_Number_Of_DAC_Packages;
3342 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3343 /* enable sending of ao dma requests */
3344 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3346 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3348 if (cmd->stop_src == TRIG_COUNT) {
3349 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3350 Interrupt_B_Ack_Register);
3351 ni_set_bits(dev, Interrupt_B_Enable_Register,
3352 AO_BC_TC_Interrupt_Enable, 1);
3355 s->async->inttrig = &ni_ao_inttrig;
3360 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3361 struct comedi_cmd *cmd)
3363 struct ni_private *devpriv = dev->private;
3367 /* Step 1 : check if triggers are trivially valid */
3369 if ((cmd->flags & CMDF_WRITE) == 0)
3370 cmd->flags |= CMDF_WRITE;
3372 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3373 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3374 TRIG_TIMER | TRIG_EXT);
3375 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3376 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3377 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3382 /* Step 2a : make sure trigger sources are unique */
3384 err |= cfc_check_trigger_is_unique(cmd->start_src);
3385 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3386 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3388 /* Step 2b : and mutually compatible */
3393 /* Step 3: check if arguments are trivially valid */
3395 if (cmd->start_src == TRIG_EXT) {
3396 /* external trigger */
3397 unsigned int tmp = CR_CHAN(cmd->start_arg);
3401 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3402 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3404 /* true for both TRIG_NOW and TRIG_INT */
3405 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3408 if (cmd->scan_begin_src == TRIG_TIMER) {
3409 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3410 boardtype.ao_speed);
3411 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3412 devpriv->clock_ns * 0xffffff);
3415 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3416 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3418 if (cmd->stop_src == TRIG_COUNT)
3419 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3420 else /* TRIG_NONE */
3421 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3426 /* step 4: fix up any arguments */
3427 if (cmd->scan_begin_src == TRIG_TIMER) {
3428 tmp = cmd->scan_begin_arg;
3429 cmd->scan_begin_arg =
3430 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3431 cmd->scan_begin_arg,
3435 if (tmp != cmd->scan_begin_arg)
3441 /* step 5: fix up chanlist */
3449 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3451 struct ni_private *devpriv = dev->private;
3453 /* devpriv->ao0p=0x0000; */
3454 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3456 /* devpriv->ao1p=AO_Channel(1); */
3457 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3459 ni_release_ao_mite_channel(dev);
3461 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3462 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3463 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3464 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3465 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3466 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3467 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3468 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3469 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3470 devpriv->ao_cmd1 = 0;
3471 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3472 devpriv->ao_cmd2 = 0;
3473 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3474 devpriv->ao_mode1 = 0;
3475 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3476 devpriv->ao_mode2 = 0;
3477 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3478 if (boardtype.reg_type & ni_reg_m_series_mask)
3479 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3481 devpriv->ao_mode3 = 0;
3482 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3483 devpriv->ao_trigger_select = 0;
3484 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3485 AO_Trigger_Select_Register);
3486 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3487 unsigned immediate_bits = 0;
3489 for (i = 0; i < s->n_chan; ++i) {
3490 immediate_bits |= 1 << i;
3492 ao_win_out(immediate_bits, AO_Immediate_671x);
3493 ao_win_out(CLEAR_WG, AO_Misc_611x);
3495 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3502 static int ni_dio_insn_config(struct comedi_device *dev,
3503 struct comedi_subdevice *s,
3504 struct comedi_insn *insn, unsigned int *data)
3506 struct ni_private *devpriv = dev->private;
3509 printk("ni_dio_insn_config() chan=%d io=%d\n",
3510 CR_CHAN(insn->chanspec), data[0]);
3513 case INSN_CONFIG_DIO_OUTPUT:
3514 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3516 case INSN_CONFIG_DIO_INPUT:
3517 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3519 case INSN_CONFIG_DIO_QUERY:
3522 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3530 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3531 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3532 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3537 static int ni_dio_insn_bits(struct comedi_device *dev,
3538 struct comedi_subdevice *s,
3539 struct comedi_insn *insn, unsigned int *data)
3541 struct ni_private *devpriv = dev->private;
3544 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3548 /* Perform check to make sure we're not using the
3549 serial part of the dio */
3550 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3551 && devpriv->serial_interval_ns)
3554 s->state &= ~data[0];
3555 s->state |= (data[0] & data[1]);
3556 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3557 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3558 devpriv->stc_writew(dev, devpriv->dio_output,
3559 DIO_Output_Register);
3561 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3566 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3567 struct comedi_subdevice *s,
3568 struct comedi_insn *insn,
3571 struct ni_private *devpriv __maybe_unused = dev->private;
3574 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3575 CR_CHAN(insn->chanspec), data[0]);
3578 case INSN_CONFIG_DIO_OUTPUT:
3579 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3581 case INSN_CONFIG_DIO_INPUT:
3582 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3584 case INSN_CONFIG_DIO_QUERY:
3587 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3595 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3600 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3601 struct comedi_subdevice *s,
3602 struct comedi_insn *insn,
3605 struct ni_private *devpriv __maybe_unused = dev->private;
3608 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3613 s->state &= ~data[0];
3614 s->state |= (data[0] & data[1]);
3615 ni_writel(s->state, M_Offset_Static_Digital_Output);
3617 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3622 static int ni_cdio_cmdtest(struct comedi_device *dev,
3623 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3629 /* Step 1 : check if triggers are trivially valid */
3631 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3632 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3633 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3634 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3635 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3640 /* Step 2a : make sure trigger sources are unique */
3641 /* Step 2b : and mutually compatible */
3646 /* Step 3: check if arguments are trivially valid */
3648 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3650 tmp = cmd->scan_begin_arg;
3651 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3652 if (tmp != cmd->scan_begin_arg)
3655 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3656 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3657 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3662 /* step 4: fix up any arguments */
3667 /* step 5: check chanlist */
3669 for (i = 0; i < cmd->chanlist_len; ++i) {
3670 if (cmd->chanlist[i] != i)
3680 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3682 struct ni_private *devpriv __maybe_unused = dev->private;
3683 const struct comedi_cmd *cmd = &s->async->cmd;
3684 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3687 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3688 switch (cmd->scan_begin_src) {
3691 CR_CHAN(cmd->scan_begin_arg) &
3692 CDO_Sample_Source_Select_Mask;
3698 if (cmd->scan_begin_arg & CR_INVERT)
3699 cdo_mode_bits |= CDO_Polarity_Bit;
3700 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3702 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3703 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3704 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3707 "attempted to run digital output command with no lines configured as outputs");
3710 retval = ni_request_cdo_mite_channel(dev);
3714 s->async->inttrig = &ni_cdo_inttrig;
3718 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3719 unsigned int trignum)
3722 struct ni_private *devpriv = dev->private;
3723 unsigned long flags;
3727 const unsigned timeout = 1000;
3729 s->async->inttrig = NULL;
3731 /* read alloc the entire buffer */
3732 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3735 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3736 if (devpriv->cdo_mite_chan) {
3737 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3738 mite_dma_arm(devpriv->cdo_mite_chan);
3740 comedi_error(dev, "BUG: no cdo mite channel?");
3743 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3748 * XXX not sure what interrupt C group does
3749 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3750 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3752 for (i = 0; i < timeout; ++i) {
3753 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3758 comedi_error(dev, "dma failed to fill cdo fifo!");
3759 ni_cdio_cancel(dev, s);
3762 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3763 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3764 M_Offset_CDIO_Command);
3768 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3770 struct ni_private *devpriv __maybe_unused = dev->private;
3772 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3773 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3774 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3775 M_Offset_CDIO_Command);
3777 * XXX not sure what interrupt C group does ni_writeb(0,
3778 * M_Offset_Interrupt_C_Enable);
3780 ni_writel(0, M_Offset_CDO_Mask_Enable);
3781 ni_release_cdo_mite_channel(dev);
3785 static void handle_cdio_interrupt(struct comedi_device *dev)
3787 struct ni_private *devpriv __maybe_unused = dev->private;
3788 unsigned cdio_status;
3789 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3791 unsigned long flags;
3794 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3798 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3799 if (devpriv->cdo_mite_chan) {
3800 unsigned cdo_mite_status =
3801 mite_get_status(devpriv->cdo_mite_chan);
3802 if (cdo_mite_status & CHSR_LINKC) {
3804 devpriv->mite->mite_io_addr +
3805 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3807 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3809 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3812 cdio_status = ni_readl(M_Offset_CDIO_Status);
3813 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3814 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3815 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3816 s->async->events |= COMEDI_CB_OVERFLOW;
3818 if (cdio_status & CDO_FIFO_Empty_Bit) {
3819 /* printk("cdio fifo empty\n"); */
3820 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3821 M_Offset_CDIO_Command);
3822 /* s->async->events |= COMEDI_CB_EOA; */
3827 static int ni_serial_insn_config(struct comedi_device *dev,
3828 struct comedi_subdevice *s,
3829 struct comedi_insn *insn, unsigned int *data)
3831 struct ni_private *devpriv = dev->private;
3833 unsigned char byte_out, byte_in = 0;
3839 case INSN_CONFIG_SERIAL_CLOCK:
3842 printk("SPI serial clock Config cd\n", data[1]);
3844 devpriv->serial_hw_mode = 1;
3845 devpriv->dio_control |= DIO_HW_Serial_Enable;
3847 if (data[1] == SERIAL_DISABLED) {
3848 devpriv->serial_hw_mode = 0;
3849 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3850 DIO_Software_Serial_Control);
3851 data[1] = SERIAL_DISABLED;
3852 devpriv->serial_interval_ns = data[1];
3853 } else if (data[1] <= SERIAL_600NS) {
3854 /* Warning: this clock speed is too fast to reliably
3856 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3857 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3858 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3859 data[1] = SERIAL_600NS;
3860 devpriv->serial_interval_ns = data[1];
3861 } else if (data[1] <= SERIAL_1_2US) {
3862 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3863 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3864 DIO_Serial_Out_Divide_By_2;
3865 data[1] = SERIAL_1_2US;
3866 devpriv->serial_interval_ns = data[1];
3867 } else if (data[1] <= SERIAL_10US) {
3868 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3869 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3870 DIO_Serial_Out_Divide_By_2;
3871 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3872 600ns/1.2us. If you turn divide_by_2 off with the
3873 slow clock, you will still get 10us, except then
3874 all your delays are wrong. */
3875 data[1] = SERIAL_10US;
3876 devpriv->serial_interval_ns = data[1];
3878 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3879 DIO_Software_Serial_Control);
3880 devpriv->serial_hw_mode = 0;
3881 data[1] = (data[1] / 1000) * 1000;
3882 devpriv->serial_interval_ns = data[1];
3885 devpriv->stc_writew(dev, devpriv->dio_control,
3886 DIO_Control_Register);
3887 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3888 Clock_and_FOUT_Register);
3893 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3895 if (devpriv->serial_interval_ns == 0) {
3899 byte_out = data[1] & 0xFF;
3901 if (devpriv->serial_hw_mode) {
3902 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3904 } else if (devpriv->serial_interval_ns > 0) {
3905 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3908 printk("ni_serial_insn_config: serial disabled!\n");
3913 data[1] = byte_in & 0xFF;
3923 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3924 struct comedi_subdevice *s,
3925 unsigned char data_out,
3926 unsigned char *data_in)
3928 struct ni_private *devpriv = dev->private;
3929 unsigned int status1;
3930 int err = 0, count = 20;
3933 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3936 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3937 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3938 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3940 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3941 if (status1 & DIO_Serial_IO_In_Progress_St) {
3946 devpriv->dio_control |= DIO_HW_Serial_Start;
3947 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3948 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3950 /* Wait until STC says we're done, but don't loop infinitely. */
3952 devpriv->stc_readw(dev,
3953 Joint_Status_1_Register)) &
3954 DIO_Serial_IO_In_Progress_St) {
3955 /* Delay one bit per loop */
3956 udelay((devpriv->serial_interval_ns + 999) / 1000);
3959 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3965 /* Delay for last bit. This delay is absolutely necessary, because
3966 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3967 udelay((devpriv->serial_interval_ns + 999) / 1000);
3969 if (data_in != NULL) {
3970 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3972 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3977 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3982 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3983 struct comedi_subdevice *s,
3984 unsigned char data_out,
3985 unsigned char *data_in)
3987 struct ni_private *devpriv = dev->private;
3988 unsigned char mask, input = 0;
3991 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3994 /* Wait for one bit before transfer */
3995 udelay((devpriv->serial_interval_ns + 999) / 1000);
3997 for (mask = 0x80; mask; mask >>= 1) {
3998 /* Output current bit; note that we cannot touch s->state
3999 because it is a per-subdevice field, and serial is
4000 a separate subdevice from DIO. */
4001 devpriv->dio_output &= ~DIO_SDOUT;
4002 if (data_out & mask) {
4003 devpriv->dio_output |= DIO_SDOUT;
4005 devpriv->stc_writew(dev, devpriv->dio_output,
4006 DIO_Output_Register);
4008 /* Assert SDCLK (active low, inverted), wait for half of
4009 the delay, deassert SDCLK, and wait for the other half. */
4010 devpriv->dio_control |= DIO_Software_Serial_Control;
4011 devpriv->stc_writew(dev, devpriv->dio_control,
4012 DIO_Control_Register);
4014 udelay((devpriv->serial_interval_ns + 999) / 2000);
4016 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4017 devpriv->stc_writew(dev, devpriv->dio_control,
4018 DIO_Control_Register);
4020 udelay((devpriv->serial_interval_ns + 999) / 2000);
4022 /* Input current bit */
4023 if (devpriv->stc_readw(dev,
4024 DIO_Parallel_Input_Register) & DIO_SDIN)
4026 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4031 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4039 static void mio_common_detach(struct comedi_device *dev)
4041 struct ni_private *devpriv = dev->private;
4042 struct comedi_subdevice *s;
4045 if (devpriv->counter_dev) {
4046 ni_gpct_device_destroy(devpriv->counter_dev);
4049 if (dev->subdevices && boardtype.has_8255) {
4050 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4051 subdev_8255_cleanup(dev, s);
4055 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4059 for (i = 0; i < s->n_chan; i++) {
4060 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4061 AO_Configuration_2_67xx);
4063 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4066 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4068 unsigned stc_register;
4070 case NITIO_G0_Autoincrement_Reg:
4071 stc_register = G_Autoincrement_Register(0);
4073 case NITIO_G1_Autoincrement_Reg:
4074 stc_register = G_Autoincrement_Register(1);
4076 case NITIO_G0_Command_Reg:
4077 stc_register = G_Command_Register(0);
4079 case NITIO_G1_Command_Reg:
4080 stc_register = G_Command_Register(1);
4082 case NITIO_G0_HW_Save_Reg:
4083 stc_register = G_HW_Save_Register(0);
4085 case NITIO_G1_HW_Save_Reg:
4086 stc_register = G_HW_Save_Register(1);
4088 case NITIO_G0_SW_Save_Reg:
4089 stc_register = G_Save_Register(0);
4091 case NITIO_G1_SW_Save_Reg:
4092 stc_register = G_Save_Register(1);
4094 case NITIO_G0_Mode_Reg:
4095 stc_register = G_Mode_Register(0);
4097 case NITIO_G1_Mode_Reg:
4098 stc_register = G_Mode_Register(1);
4100 case NITIO_G0_LoadA_Reg:
4101 stc_register = G_Load_A_Register(0);
4103 case NITIO_G1_LoadA_Reg:
4104 stc_register = G_Load_A_Register(1);
4106 case NITIO_G0_LoadB_Reg:
4107 stc_register = G_Load_B_Register(0);
4109 case NITIO_G1_LoadB_Reg:
4110 stc_register = G_Load_B_Register(1);
4112 case NITIO_G0_Input_Select_Reg:
4113 stc_register = G_Input_Select_Register(0);
4115 case NITIO_G1_Input_Select_Reg:
4116 stc_register = G_Input_Select_Register(1);
4118 case NITIO_G01_Status_Reg:
4119 stc_register = G_Status_Register;
4121 case NITIO_G01_Joint_Reset_Reg:
4122 stc_register = Joint_Reset_Register;
4124 case NITIO_G01_Joint_Status1_Reg:
4125 stc_register = Joint_Status_1_Register;
4127 case NITIO_G01_Joint_Status2_Reg:
4128 stc_register = Joint_Status_2_Register;
4130 case NITIO_G0_Interrupt_Acknowledge_Reg:
4131 stc_register = Interrupt_A_Ack_Register;
4133 case NITIO_G1_Interrupt_Acknowledge_Reg:
4134 stc_register = Interrupt_B_Ack_Register;
4136 case NITIO_G0_Status_Reg:
4137 stc_register = AI_Status_1_Register;
4139 case NITIO_G1_Status_Reg:
4140 stc_register = AO_Status_1_Register;
4142 case NITIO_G0_Interrupt_Enable_Reg:
4143 stc_register = Interrupt_A_Enable_Register;
4145 case NITIO_G1_Interrupt_Enable_Reg:
4146 stc_register = Interrupt_B_Enable_Register;
4149 printk("%s: unhandled register 0x%x in switch.\n",
4155 return stc_register;
4158 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4159 enum ni_gpct_register reg)
4161 struct comedi_device *dev = counter->counter_dev->dev;
4162 struct ni_private *devpriv = dev->private;
4163 unsigned stc_register;
4164 /* bits in the join reset register which are relevant to counters */
4165 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4166 static const unsigned gpct_interrupt_a_enable_mask =
4167 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4168 static const unsigned gpct_interrupt_b_enable_mask =
4169 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4172 /* m-series-only registers */
4173 case NITIO_G0_Counting_Mode_Reg:
4174 ni_writew(bits, M_Offset_G0_Counting_Mode);
4176 case NITIO_G1_Counting_Mode_Reg:
4177 ni_writew(bits, M_Offset_G1_Counting_Mode);
4179 case NITIO_G0_Second_Gate_Reg:
4180 ni_writew(bits, M_Offset_G0_Second_Gate);
4182 case NITIO_G1_Second_Gate_Reg:
4183 ni_writew(bits, M_Offset_G1_Second_Gate);
4185 case NITIO_G0_DMA_Config_Reg:
4186 ni_writew(bits, M_Offset_G0_DMA_Config);
4188 case NITIO_G1_DMA_Config_Reg:
4189 ni_writew(bits, M_Offset_G1_DMA_Config);
4191 case NITIO_G0_ABZ_Reg:
4192 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4194 case NITIO_G1_ABZ_Reg:
4195 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4198 /* 32 bit registers */
4199 case NITIO_G0_LoadA_Reg:
4200 case NITIO_G1_LoadA_Reg:
4201 case NITIO_G0_LoadB_Reg:
4202 case NITIO_G1_LoadB_Reg:
4203 stc_register = ni_gpct_to_stc_register(reg);
4204 devpriv->stc_writel(dev, bits, stc_register);
4207 /* 16 bit registers */
4208 case NITIO_G0_Interrupt_Enable_Reg:
4209 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4210 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4211 gpct_interrupt_a_enable_mask, bits);
4213 case NITIO_G1_Interrupt_Enable_Reg:
4214 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4215 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4216 gpct_interrupt_b_enable_mask, bits);
4218 case NITIO_G01_Joint_Reset_Reg:
4219 BUG_ON(bits & ~gpct_joint_reset_mask);
4222 stc_register = ni_gpct_to_stc_register(reg);
4223 devpriv->stc_writew(dev, bits, stc_register);
4227 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4228 enum ni_gpct_register reg)
4230 struct comedi_device *dev = counter->counter_dev->dev;
4231 struct ni_private *devpriv = dev->private;
4232 unsigned stc_register;
4235 /* m-series only registers */
4236 case NITIO_G0_DMA_Status_Reg:
4237 return ni_readw(M_Offset_G0_DMA_Status);
4239 case NITIO_G1_DMA_Status_Reg:
4240 return ni_readw(M_Offset_G1_DMA_Status);
4243 /* 32 bit registers */
4244 case NITIO_G0_HW_Save_Reg:
4245 case NITIO_G1_HW_Save_Reg:
4246 case NITIO_G0_SW_Save_Reg:
4247 case NITIO_G1_SW_Save_Reg:
4248 stc_register = ni_gpct_to_stc_register(reg);
4249 return devpriv->stc_readl(dev, stc_register);
4252 /* 16 bit registers */
4254 stc_register = ni_gpct_to_stc_register(reg);
4255 return devpriv->stc_readw(dev, stc_register);
4261 static int ni_freq_out_insn_read(struct comedi_device *dev,
4262 struct comedi_subdevice *s,
4263 struct comedi_insn *insn, unsigned int *data)
4265 struct ni_private *devpriv = dev->private;
4267 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4271 static int ni_freq_out_insn_write(struct comedi_device *dev,
4272 struct comedi_subdevice *s,
4273 struct comedi_insn *insn, unsigned int *data)
4275 struct ni_private *devpriv = dev->private;
4277 devpriv->clock_and_fout &= ~FOUT_Enable;
4278 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4279 Clock_and_FOUT_Register);
4280 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4281 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4282 devpriv->clock_and_fout |= FOUT_Enable;
4283 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4284 Clock_and_FOUT_Register);
4288 static int ni_set_freq_out_clock(struct comedi_device *dev,
4289 unsigned int clock_source)
4291 struct ni_private *devpriv = dev->private;
4293 switch (clock_source) {
4294 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4295 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4297 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4298 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4303 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4304 Clock_and_FOUT_Register);
4308 static void ni_get_freq_out_clock(struct comedi_device *dev,
4309 unsigned int *clock_source,
4310 unsigned int *clock_period_ns)
4312 struct ni_private *devpriv = dev->private;
4314 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4315 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4316 *clock_period_ns = TIMEBASE_2_NS;
4318 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4319 *clock_period_ns = TIMEBASE_1_NS * 2;
4323 static int ni_freq_out_insn_config(struct comedi_device *dev,
4324 struct comedi_subdevice *s,
4325 struct comedi_insn *insn, unsigned int *data)
4328 case INSN_CONFIG_SET_CLOCK_SRC:
4329 return ni_set_freq_out_clock(dev, data[1]);
4331 case INSN_CONFIG_GET_CLOCK_SRC:
4332 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4340 static int ni_alloc_private(struct comedi_device *dev)
4342 struct ni_private *devpriv;
4344 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4347 dev->private = devpriv;
4349 spin_lock_init(&devpriv->window_lock);
4350 spin_lock_init(&devpriv->soft_reg_copy_lock);
4351 spin_lock_init(&devpriv->mite_channel_lock);
4356 static int ni_E_init(struct comedi_device *dev)
4358 struct ni_private *devpriv = dev->private;
4359 struct comedi_subdevice *s;
4361 enum ni_gpct_variant counter_variant;
4364 if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4365 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4369 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4373 /* analog input subdevice */
4375 s = &dev->subdevices[NI_AI_SUBDEV];
4376 dev->read_subdev = s;
4377 if (boardtype.n_adchan) {
4378 s->type = COMEDI_SUBD_AI;
4380 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4381 if (boardtype.reg_type != ni_reg_611x)
4382 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4383 if (boardtype.adbits > 16)
4384 s->subdev_flags |= SDF_LSAMPL;
4385 if (boardtype.reg_type & ni_reg_m_series_mask)
4386 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4387 s->n_chan = boardtype.n_adchan;
4388 s->len_chanlist = 512;
4389 s->maxdata = (1 << boardtype.adbits) - 1;
4390 s->range_table = ni_range_lkup[boardtype.gainlkup];
4391 s->insn_read = &ni_ai_insn_read;
4392 s->insn_config = &ni_ai_insn_config;
4393 s->do_cmdtest = &ni_ai_cmdtest;
4394 s->do_cmd = &ni_ai_cmd;
4395 s->cancel = &ni_ai_reset;
4396 s->poll = &ni_ai_poll;
4397 s->munge = &ni_ai_munge;
4399 s->async_dma_dir = DMA_FROM_DEVICE;
4402 s->type = COMEDI_SUBD_UNUSED;
4405 /* analog output subdevice */
4407 s = &dev->subdevices[NI_AO_SUBDEV];
4408 if (boardtype.n_aochan) {
4409 s->type = COMEDI_SUBD_AO;
4410 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4411 if (boardtype.reg_type & ni_reg_m_series_mask)
4412 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4413 s->n_chan = boardtype.n_aochan;
4414 s->maxdata = (1 << boardtype.aobits) - 1;
4415 s->range_table = boardtype.ao_range_table;
4416 s->insn_read = &ni_ao_insn_read;
4417 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4418 s->insn_write = &ni_ao_insn_write_671x;
4420 s->insn_write = &ni_ao_insn_write;
4422 s->insn_config = &ni_ao_insn_config;
4424 if (boardtype.n_aochan) {
4425 s->async_dma_dir = DMA_TO_DEVICE;
4427 if (boardtype.ao_fifo_depth) {
4429 dev->write_subdev = s;
4430 s->subdev_flags |= SDF_CMD_WRITE;
4431 s->do_cmd = &ni_ao_cmd;
4432 s->do_cmdtest = &ni_ao_cmdtest;
4433 s->len_chanlist = boardtype.n_aochan;
4434 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4435 s->munge = ni_ao_munge;
4437 s->cancel = &ni_ao_reset;
4439 s->type = COMEDI_SUBD_UNUSED;
4441 if ((boardtype.reg_type & ni_reg_67xx_mask))
4442 init_ao_67xx(dev, s);
4444 /* digital i/o subdevice */
4446 s = &dev->subdevices[NI_DIO_SUBDEV];
4447 s->type = COMEDI_SUBD_DIO;
4448 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4450 s->io_bits = 0; /* all bits input */
4451 s->range_table = &range_digital;
4452 s->n_chan = boardtype.num_p0_dio_channels;
4453 if (boardtype.reg_type & ni_reg_m_series_mask) {
4455 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4456 s->insn_bits = &ni_m_series_dio_insn_bits;
4457 s->insn_config = &ni_m_series_dio_insn_config;
4458 s->do_cmd = &ni_cdio_cmd;
4459 s->do_cmdtest = &ni_cdio_cmdtest;
4460 s->cancel = &ni_cdio_cancel;
4461 s->async_dma_dir = DMA_BIDIRECTIONAL;
4462 s->len_chanlist = s->n_chan;
4464 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4465 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4467 s->insn_bits = &ni_dio_insn_bits;
4468 s->insn_config = &ni_dio_insn_config;
4469 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4470 ni_writew(devpriv->dio_control, DIO_Control_Register);
4474 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4475 if (boardtype.has_8255) {
4476 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4478 s->type = COMEDI_SUBD_UNUSED;
4481 /* formerly general purpose counter/timer device, but no longer used */
4482 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4483 s->type = COMEDI_SUBD_UNUSED;
4485 /* calibration subdevice -- ai and ao */
4486 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4487 s->type = COMEDI_SUBD_CALIB;
4488 if (boardtype.reg_type & ni_reg_m_series_mask) {
4489 /* internal PWM analog output used for AI nonlinearity calibration */
4490 s->subdev_flags = SDF_INTERNAL;
4491 s->insn_config = &ni_m_series_pwm_config;
4494 ni_writel(0x0, M_Offset_Cal_PWM);
4495 } else if (boardtype.reg_type == ni_reg_6143) {
4496 /* internal PWM analog output used for AI nonlinearity calibration */
4497 s->subdev_flags = SDF_INTERNAL;
4498 s->insn_config = &ni_6143_pwm_config;
4502 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4503 s->insn_read = &ni_calib_insn_read;
4504 s->insn_write = &ni_calib_insn_write;
4505 caldac_setup(dev, s);
4509 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4510 s->type = COMEDI_SUBD_MEMORY;
4511 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4513 if (boardtype.reg_type & ni_reg_m_series_mask) {
4514 s->n_chan = M_SERIES_EEPROM_SIZE;
4515 s->insn_read = &ni_m_series_eeprom_insn_read;
4518 s->insn_read = &ni_eeprom_insn_read;
4522 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4523 s->type = COMEDI_SUBD_DIO;
4524 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4525 if (boardtype.reg_type & ni_reg_m_series_mask) {
4528 ni_writew(s->state, M_Offset_PFI_DO);
4529 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4530 ni_writew(devpriv->pfi_output_select_reg[i],
4531 M_Offset_PFI_Output_Select(i + 1));
4537 if (boardtype.reg_type & ni_reg_m_series_mask) {
4538 s->insn_bits = &ni_pfi_insn_bits;
4540 s->insn_config = &ni_pfi_insn_config;
4541 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4543 /* cs5529 calibration adc */
4544 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4545 if (boardtype.reg_type & ni_reg_67xx_mask) {
4546 s->type = COMEDI_SUBD_AI;
4547 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4548 /* one channel for each analog output channel */
4549 s->n_chan = boardtype.n_aochan;
4550 s->maxdata = (1 << 16) - 1;
4551 s->range_table = &range_unknown; /* XXX */
4552 s->insn_read = cs5529_ai_insn_read;
4553 s->insn_config = NULL;
4556 s->type = COMEDI_SUBD_UNUSED;
4560 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4561 s->type = COMEDI_SUBD_SERIAL;
4562 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4565 s->insn_config = ni_serial_insn_config;
4566 devpriv->serial_interval_ns = 0;
4567 devpriv->serial_hw_mode = 0;
4570 s = &dev->subdevices[NI_RTSI_SUBDEV];
4571 s->type = COMEDI_SUBD_DIO;
4572 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4575 s->insn_bits = ni_rtsi_insn_bits;
4576 s->insn_config = ni_rtsi_insn_config;
4579 if (boardtype.reg_type & ni_reg_m_series_mask) {
4580 counter_variant = ni_gpct_variant_m_series;
4582 counter_variant = ni_gpct_variant_e_series;
4584 devpriv->counter_dev = ni_gpct_device_construct(dev,
4585 &ni_gpct_write_register,
4586 &ni_gpct_read_register,
4589 /* General purpose counters */
4590 for (j = 0; j < NUM_GPCT; ++j) {
4591 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4592 s->type = COMEDI_SUBD_COUNTER;
4594 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4595 /* | SDF_CMD_WRITE */ ;
4597 if (boardtype.reg_type & ni_reg_m_series_mask)
4598 s->maxdata = 0xffffffff;
4600 s->maxdata = 0xffffff;
4601 s->insn_read = &ni_gpct_insn_read;
4602 s->insn_write = &ni_gpct_insn_write;
4603 s->insn_config = &ni_gpct_insn_config;
4604 s->do_cmd = &ni_gpct_cmd;
4605 s->len_chanlist = 1;
4606 s->do_cmdtest = &ni_gpct_cmdtest;
4607 s->cancel = &ni_gpct_cancel;
4608 s->async_dma_dir = DMA_BIDIRECTIONAL;
4609 s->private = &devpriv->counter_dev->counters[j];
4611 devpriv->counter_dev->counters[j].chip_index = 0;
4612 devpriv->counter_dev->counters[j].counter_index = j;
4613 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4616 /* Frequency output */
4617 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4618 s->type = COMEDI_SUBD_COUNTER;
4619 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4622 s->insn_read = &ni_freq_out_insn_read;
4623 s->insn_write = &ni_freq_out_insn_write;
4624 s->insn_config = &ni_freq_out_insn_config;
4626 /* ai configuration */
4627 s = &dev->subdevices[NI_AI_SUBDEV];
4628 ni_ai_reset(dev, s);
4629 if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4630 /* BEAM is this needed for PCI-6143 ?? */
4631 devpriv->clock_and_fout =
4632 Slow_Internal_Time_Divide_By_2 |
4633 Slow_Internal_Timebase |
4634 Clock_To_Board_Divide_By_2 |
4636 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4638 devpriv->clock_and_fout =
4639 Slow_Internal_Time_Divide_By_2 |
4640 Slow_Internal_Timebase |
4641 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4643 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4644 Clock_and_FOUT_Register);
4646 /* analog output configuration */
4647 s = &dev->subdevices[NI_AO_SUBDEV];
4648 ni_ao_reset(dev, s);
4651 devpriv->stc_writew(dev,
4652 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4653 0) | (Interrupt_Output_On_3_Pins & 0) |
4654 Interrupt_A_Enable | Interrupt_B_Enable |
4655 Interrupt_A_Output_Select(interrupt_pin
4657 Interrupt_B_Output_Select(interrupt_pin
4659 Interrupt_Control_Register);
4663 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4664 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4666 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4667 ni_writeb(0, Magic_611x);
4668 } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4670 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4671 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4673 M_Offset_AO_Reference_Attenuation(channel));
4675 ni_writeb(0x0, M_Offset_AO_Calibration);
4682 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4684 struct comedi_device *dev = (struct comedi_device *)arg;
4685 struct ni_private *devpriv __maybe_unused = dev->private;
4688 ni_writeb(data, Port_A + 2 * port);
4691 return ni_readb(Port_A + 2 * port);
4696 presents the EEPROM as a subdevice
4699 static int ni_eeprom_insn_read(struct comedi_device *dev,
4700 struct comedi_subdevice *s,
4701 struct comedi_insn *insn, unsigned int *data)
4703 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4709 reads bytes out of eeprom
4712 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4714 struct ni_private *devpriv __maybe_unused = dev->private;
4718 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4719 ni_writeb(0x04, Serial_Command);
4720 for (bit = 0x8000; bit; bit >>= 1) {
4721 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4723 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4727 for (bit = 0x80; bit; bit >>= 1) {
4728 ni_writeb(0x04, Serial_Command);
4729 ni_writeb(0x05, Serial_Command);
4730 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4732 ni_writeb(0x00, Serial_Command);
4737 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4738 struct comedi_subdevice *s,
4739 struct comedi_insn *insn,
4742 struct ni_private *devpriv = dev->private;
4744 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4749 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4751 struct ni_private *devpriv = dev->private;
4753 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4754 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4758 static int ni_m_series_pwm_config(struct comedi_device *dev,
4759 struct comedi_subdevice *s,
4760 struct comedi_insn *insn, unsigned int *data)
4762 struct ni_private *devpriv = dev->private;
4763 unsigned up_count, down_count;
4766 case INSN_CONFIG_PWM_OUTPUT:
4768 case TRIG_ROUND_NEAREST:
4771 devpriv->clock_ns / 2) / devpriv->clock_ns;
4773 case TRIG_ROUND_DOWN:
4774 up_count = data[2] / devpriv->clock_ns;
4778 (data[2] + devpriv->clock_ns -
4779 1) / devpriv->clock_ns;
4786 case TRIG_ROUND_NEAREST:
4789 devpriv->clock_ns / 2) / devpriv->clock_ns;
4791 case TRIG_ROUND_DOWN:
4792 down_count = data[4] / devpriv->clock_ns;
4796 (data[4] + devpriv->clock_ns -
4797 1) / devpriv->clock_ns;
4803 if (up_count * devpriv->clock_ns != data[2] ||
4804 down_count * devpriv->clock_ns != data[4]) {
4805 data[2] = up_count * devpriv->clock_ns;
4806 data[4] = down_count * devpriv->clock_ns;
4809 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4810 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4812 devpriv->pwm_up_count = up_count;
4813 devpriv->pwm_down_count = down_count;
4816 case INSN_CONFIG_GET_PWM_OUTPUT:
4817 return ni_get_pwm_config(dev, data);
4826 static int ni_6143_pwm_config(struct comedi_device *dev,
4827 struct comedi_subdevice *s,
4828 struct comedi_insn *insn, unsigned int *data)
4830 struct ni_private *devpriv = dev->private;
4831 unsigned up_count, down_count;
4834 case INSN_CONFIG_PWM_OUTPUT:
4836 case TRIG_ROUND_NEAREST:
4839 devpriv->clock_ns / 2) / devpriv->clock_ns;
4841 case TRIG_ROUND_DOWN:
4842 up_count = data[2] / devpriv->clock_ns;
4846 (data[2] + devpriv->clock_ns -
4847 1) / devpriv->clock_ns;
4854 case TRIG_ROUND_NEAREST:
4857 devpriv->clock_ns / 2) / devpriv->clock_ns;
4859 case TRIG_ROUND_DOWN:
4860 down_count = data[4] / devpriv->clock_ns;
4864 (data[4] + devpriv->clock_ns -
4865 1) / devpriv->clock_ns;
4871 if (up_count * devpriv->clock_ns != data[2] ||
4872 down_count * devpriv->clock_ns != data[4]) {
4873 data[2] = up_count * devpriv->clock_ns;
4874 data[4] = down_count * devpriv->clock_ns;
4877 ni_writel(up_count, Calibration_HighTime_6143);
4878 devpriv->pwm_up_count = up_count;
4879 ni_writel(down_count, Calibration_LowTime_6143);
4880 devpriv->pwm_down_count = down_count;
4883 case INSN_CONFIG_GET_PWM_OUTPUT:
4884 return ni_get_pwm_config(dev, data);
4892 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4894 calibration subdevice
4896 static int ni_calib_insn_write(struct comedi_device *dev,
4897 struct comedi_subdevice *s,
4898 struct comedi_insn *insn, unsigned int *data)
4900 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4905 static int ni_calib_insn_read(struct comedi_device *dev,
4906 struct comedi_subdevice *s,
4907 struct comedi_insn *insn, unsigned int *data)
4909 struct ni_private *devpriv = dev->private;
4911 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4916 static int pack_mb88341(int addr, int val, int *bitstring);
4917 static int pack_dac8800(int addr, int val, int *bitstring);
4918 static int pack_dac8043(int addr, int val, int *bitstring);
4919 static int pack_ad8522(int addr, int val, int *bitstring);
4920 static int pack_ad8804(int addr, int val, int *bitstring);
4921 static int pack_ad8842(int addr, int val, int *bitstring);
4923 struct caldac_struct {
4926 int (*packbits) (int, int, int *);
4929 static struct caldac_struct caldacs[] = {
4930 [mb88341] = {12, 8, pack_mb88341},
4931 [dac8800] = {8, 8, pack_dac8800},
4932 [dac8043] = {1, 12, pack_dac8043},
4933 [ad8522] = {2, 12, pack_ad8522},
4934 [ad8804] = {12, 8, pack_ad8804},
4935 [ad8842] = {8, 8, pack_ad8842},
4936 [ad8804_debug] = {16, 8, pack_ad8804},
4939 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4941 struct ni_private *devpriv = dev->private;
4950 type = boardtype.caldac[0];
4951 if (type == caldac_none)
4953 n_bits = caldacs[type].n_bits;
4954 for (i = 0; i < 3; i++) {
4955 type = boardtype.caldac[i];
4956 if (type == caldac_none)
4958 if (caldacs[type].n_bits != n_bits)
4960 n_chans += caldacs[type].n_chans;
4963 s->n_chan = n_chans;
4966 unsigned int *maxdata_list;
4968 if (n_chans > MAX_N_CALDACS) {
4969 printk("BUG! MAX_N_CALDACS too small\n");
4971 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4973 for (i = 0; i < n_dacs; i++) {
4974 type = boardtype.caldac[i];
4975 for (j = 0; j < caldacs[type].n_chans; j++) {
4976 maxdata_list[chan] =
4977 (1 << caldacs[type].n_bits) - 1;
4982 for (chan = 0; chan < s->n_chan; chan++)
4983 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4985 type = boardtype.caldac[0];
4986 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4988 for (chan = 0; chan < s->n_chan; chan++)
4989 ni_write_caldac(dev, i, s->maxdata / 2);
4993 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4995 struct ni_private *devpriv = dev->private;
4996 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5000 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5001 if (devpriv->caldacs[addr] == val)
5003 devpriv->caldacs[addr] = val;
5005 for (i = 0; i < 3; i++) {
5006 type = boardtype.caldac[i];
5007 if (type == caldac_none)
5009 if (addr < caldacs[type].n_chans) {
5010 bits = caldacs[type].packbits(addr, val, &bitstring);
5011 loadbit = SerDacLd(i);
5012 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5015 addr -= caldacs[type].n_chans;
5018 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5019 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5021 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5024 ni_writeb(loadbit, Serial_Command);
5026 ni_writeb(0, Serial_Command);
5029 static int pack_mb88341(int addr, int val, int *bitstring)
5033 Note that address bits are reversed. Thanks to
5034 Ingo Keen for noticing this.
5036 Note also that the 88341 expects address values from
5037 1-12, whereas we use channel numbers 0-11. The NI
5038 docs use 1-12, also, so be careful here.
5041 *bitstring = ((addr & 0x1) << 11) |
5042 ((addr & 0x2) << 9) |
5043 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5047 static int pack_dac8800(int addr, int val, int *bitstring)
5049 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5053 static int pack_dac8043(int addr, int val, int *bitstring)
5055 *bitstring = val & 0xfff;
5059 static int pack_ad8522(int addr, int val, int *bitstring)
5061 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5065 static int pack_ad8804(int addr, int val, int *bitstring)
5067 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5071 static int pack_ad8842(int addr, int val, int *bitstring)
5073 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5079 * Read the GPCTs current value.
5081 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5083 unsigned int hi1, hi2, lo;
5085 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5086 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5087 G_Command_Register(chan));
5089 devpriv->gpct_command[chan] |= G_Save_Trace;
5090 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5091 G_Command_Register(chan));
5093 /* This procedure is used because the two registers cannot
5094 * be read atomically. */
5096 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5097 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5098 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5099 } while (hi1 != hi2);
5101 return (hi1 << 16) | lo;
5104 static void GPCT_Reset(struct comedi_device *dev, int chan)
5106 int temp_ack_reg = 0;
5108 /* printk("GPCT_Reset..."); */
5109 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5113 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5114 ni_set_bits(dev, Interrupt_A_Enable_Register,
5115 G0_TC_Interrupt_Enable, 0);
5116 ni_set_bits(dev, Interrupt_A_Enable_Register,
5117 G0_Gate_Interrupt_Enable, 0);
5118 temp_ack_reg |= G0_Gate_Error_Confirm;
5119 temp_ack_reg |= G0_TC_Error_Confirm;
5120 temp_ack_reg |= G0_TC_Interrupt_Ack;
5121 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5122 devpriv->stc_writew(dev, temp_ack_reg,
5123 Interrupt_A_Ack_Register);
5125 /* problem...this interferes with the other ctr... */
5126 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5127 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5128 Analog_Trigger_Etc_Register);
5131 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5132 ni_set_bits(dev, Interrupt_B_Enable_Register,
5133 G1_TC_Interrupt_Enable, 0);
5134 ni_set_bits(dev, Interrupt_B_Enable_Register,
5135 G0_Gate_Interrupt_Enable, 0);
5136 temp_ack_reg |= G1_Gate_Error_Confirm;
5137 temp_ack_reg |= G1_TC_Error_Confirm;
5138 temp_ack_reg |= G1_TC_Interrupt_Ack;
5139 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5140 devpriv->stc_writew(dev, temp_ack_reg,
5141 Interrupt_B_Ack_Register);
5143 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5144 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5145 Analog_Trigger_Etc_Register);
5149 devpriv->gpct_mode[chan] = 0;
5150 devpriv->gpct_input_select[chan] = 0;
5151 devpriv->gpct_command[chan] = 0;
5153 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5155 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5156 G_Mode_Register(chan));
5157 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5158 G_Input_Select_Register(chan));
5159 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5161 /* printk("exit GPCT_Reset\n"); */
5166 static int ni_gpct_insn_config(struct comedi_device *dev,
5167 struct comedi_subdevice *s,
5168 struct comedi_insn *insn, unsigned int *data)
5170 struct ni_gpct *counter = s->private;
5171 return ni_tio_insn_config(counter, insn, data);
5174 static int ni_gpct_insn_read(struct comedi_device *dev,
5175 struct comedi_subdevice *s,
5176 struct comedi_insn *insn, unsigned int *data)
5178 struct ni_gpct *counter = s->private;
5179 return ni_tio_rinsn(counter, insn, data);
5182 static int ni_gpct_insn_write(struct comedi_device *dev,
5183 struct comedi_subdevice *s,
5184 struct comedi_insn *insn, unsigned int *data)
5186 struct ni_gpct *counter = s->private;
5187 return ni_tio_winsn(counter, insn, data);
5190 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5194 struct ni_gpct *counter = s->private;
5195 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5197 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5201 "no dma channel available for use by counter");
5204 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5205 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5206 retval = ni_tio_cmd(counter, s->async);
5213 static int ni_gpct_cmdtest(struct comedi_device *dev,
5214 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5217 struct ni_gpct *counter = s->private;
5219 return ni_tio_cmdtest(counter, cmd);
5225 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5228 struct ni_gpct *counter = s->private;
5231 retval = ni_tio_cancel(counter);
5232 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5233 ni_release_gpct_mite_channel(dev, counter->counter_index);
5242 * Programmable Function Inputs
5246 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5249 struct ni_private *devpriv = dev->private;
5250 unsigned pfi_reg_index;
5251 unsigned array_offset;
5253 if ((source & 0x1f) != source)
5255 pfi_reg_index = 1 + chan / 3;
5256 array_offset = pfi_reg_index - 1;
5257 devpriv->pfi_output_select_reg[array_offset] &=
5258 ~MSeries_PFI_Output_Select_Mask(chan);
5259 devpriv->pfi_output_select_reg[array_offset] |=
5260 MSeries_PFI_Output_Select_Bits(chan, source);
5261 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5262 M_Offset_PFI_Output_Select(pfi_reg_index));
5266 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5269 /* pre-m-series boards have fixed signals on pfi pins */
5270 if (source != ni_old_get_pfi_routing(dev, chan))
5275 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5278 if (boardtype.reg_type & ni_reg_m_series_mask)
5279 return ni_m_series_set_pfi_routing(dev, chan, source);
5281 return ni_old_set_pfi_routing(dev, chan, source);
5284 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5287 struct ni_private *devpriv = dev->private;
5288 const unsigned array_offset = chan / 3;
5290 return MSeries_PFI_Output_Select_Source(chan,
5292 pfi_output_select_reg
5296 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5298 /* pre-m-series boards have fixed signals on pfi pins */
5301 return NI_PFI_OUTPUT_AI_START1;
5304 return NI_PFI_OUTPUT_AI_START2;
5307 return NI_PFI_OUTPUT_AI_CONVERT;
5310 return NI_PFI_OUTPUT_G_SRC1;
5313 return NI_PFI_OUTPUT_G_GATE1;
5316 return NI_PFI_OUTPUT_AO_UPDATE_N;
5319 return NI_PFI_OUTPUT_AO_START1;
5322 return NI_PFI_OUTPUT_AI_START_PULSE;
5325 return NI_PFI_OUTPUT_G_SRC0;
5328 return NI_PFI_OUTPUT_G_GATE0;
5331 printk("%s: bug, unhandled case in switch.\n", __func__);
5337 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5339 if (boardtype.reg_type & ni_reg_m_series_mask)
5340 return ni_m_series_get_pfi_routing(dev, chan);
5342 return ni_old_get_pfi_routing(dev, chan);
5345 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5346 enum ni_pfi_filter_select filter)
5348 struct ni_private *devpriv __maybe_unused = dev->private;
5351 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5354 bits = ni_readl(M_Offset_PFI_Filter);
5355 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5356 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5357 ni_writel(bits, M_Offset_PFI_Filter);
5361 static int ni_pfi_insn_bits(struct comedi_device *dev,
5362 struct comedi_subdevice *s,
5363 struct comedi_insn *insn, unsigned int *data)
5365 struct ni_private *devpriv __maybe_unused = dev->private;
5367 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5371 s->state &= ~data[0];
5372 s->state |= (data[0] & data[1]);
5373 ni_writew(s->state, M_Offset_PFI_DO);
5375 data[1] = ni_readw(M_Offset_PFI_DI);
5379 static int ni_pfi_insn_config(struct comedi_device *dev,
5380 struct comedi_subdevice *s,
5381 struct comedi_insn *insn, unsigned int *data)
5383 struct ni_private *devpriv = dev->private;
5389 chan = CR_CHAN(insn->chanspec);
5393 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5396 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5398 case INSN_CONFIG_DIO_QUERY:
5400 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5401 COMEDI_OUTPUT : COMEDI_INPUT;
5404 case INSN_CONFIG_SET_ROUTING:
5405 return ni_set_pfi_routing(dev, chan, data[1]);
5407 case INSN_CONFIG_GET_ROUTING:
5408 data[1] = ni_get_pfi_routing(dev, chan);
5410 case INSN_CONFIG_FILTER:
5411 return ni_config_filter(dev, chan, data[1]);
5421 * NI RTSI Bus Functions
5424 static void ni_rtsi_init(struct comedi_device *dev)
5426 struct ni_private *devpriv = dev->private;
5428 /* Initialises the RTSI bus signal switch to a default state */
5430 /* Set clock mode to internal */
5431 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5432 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5433 printk("ni_set_master_clock failed, bug?");
5435 /* default internal lines routing to RTSI bus lines */
5436 devpriv->rtsi_trig_a_output_reg =
5437 RTSI_Trig_Output_Bits(0,
5438 NI_RTSI_OUTPUT_ADR_START1) |
5439 RTSI_Trig_Output_Bits(1,
5440 NI_RTSI_OUTPUT_ADR_START2) |
5441 RTSI_Trig_Output_Bits(2,
5442 NI_RTSI_OUTPUT_SCLKG) |
5443 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5444 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5445 RTSI_Trig_A_Output_Register);
5446 devpriv->rtsi_trig_b_output_reg =
5447 RTSI_Trig_Output_Bits(4,
5448 NI_RTSI_OUTPUT_DA_START1) |
5449 RTSI_Trig_Output_Bits(5,
5450 NI_RTSI_OUTPUT_G_SRC0) |
5451 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5452 if (boardtype.reg_type & ni_reg_m_series_mask)
5453 devpriv->rtsi_trig_b_output_reg |=
5454 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5455 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5456 RTSI_Trig_B_Output_Register);
5459 * Sets the source and direction of the 4 on board lines
5460 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5464 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5465 struct comedi_subdevice *s,
5466 struct comedi_insn *insn, unsigned int *data)
5473 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5474 * given an arbitrary frequency input clock */
5475 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5476 unsigned *freq_divider,
5477 unsigned *freq_multiplier,
5478 unsigned *actual_period_ns)
5481 unsigned best_div = 1;
5482 static const unsigned max_div = 0x10;
5484 unsigned best_mult = 1;
5485 static const unsigned max_mult = 0x100;
5486 static const unsigned pico_per_nano = 1000;
5488 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5489 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5490 * 20 MHz for most timing clocks */
5491 static const unsigned target_picosec = 12500;
5492 static const unsigned fudge_factor_80_to_20Mhz = 4;
5493 int best_period_picosec = 0;
5494 for (div = 1; div <= max_div; ++div) {
5495 for (mult = 1; mult <= max_mult; ++mult) {
5496 unsigned new_period_ps =
5497 (reference_picosec * div) / mult;
5498 if (abs(new_period_ps - target_picosec) <
5499 abs(best_period_picosec - target_picosec)) {
5500 best_period_picosec = new_period_ps;
5506 if (best_period_picosec == 0) {
5507 printk("%s: bug, failed to find pll parameters\n", __func__);
5510 *freq_divider = best_div;
5511 *freq_multiplier = best_mult;
5513 (best_period_picosec * fudge_factor_80_to_20Mhz +
5514 (pico_per_nano / 2)) / pico_per_nano;
5518 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5520 if (boardtype.reg_type & ni_reg_m_series_mask)
5526 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5527 unsigned source, unsigned period_ns)
5529 struct ni_private *devpriv = dev->private;
5530 static const unsigned min_period_ns = 50;
5531 static const unsigned max_period_ns = 1000;
5532 static const unsigned timeout = 1000;
5533 unsigned pll_control_bits;
5534 unsigned freq_divider;
5535 unsigned freq_multiplier;
5539 if (source == NI_MIO_PLL_PXI10_CLOCK)
5541 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5542 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5544 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5545 "for the phased-lock loop.\n", __func__,
5546 min_period_ns, max_period_ns);
5549 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5550 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5551 RTSI_Trig_Direction_Register);
5553 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5554 devpriv->clock_and_fout2 |=
5555 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5556 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5558 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5559 devpriv->clock_and_fout2 |=
5560 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5561 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5563 &devpriv->clock_ns);
5567 case NI_MIO_PLL_PXI10_CLOCK:
5568 /* pxi clock is 10MHz */
5569 devpriv->clock_and_fout2 |=
5570 MSeries_PLL_In_Source_Select_PXI_Clock10;
5571 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5573 &devpriv->clock_ns);
5579 unsigned rtsi_channel;
5580 static const unsigned max_rtsi_channel = 7;
5581 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5584 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5585 devpriv->clock_and_fout2 |=
5586 MSeries_PLL_In_Source_Select_RTSI_Bits
5591 if (rtsi_channel > max_rtsi_channel)
5593 retval = ni_mseries_get_pll_parameters(period_ns,
5603 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5605 MSeries_PLL_Divisor_Bits(freq_divider) |
5606 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5608 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5609 * freq_divider, freq_multiplier, pll_control_bits); */
5610 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5611 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5612 devpriv->clock_source = source;
5613 /* it seems to typically take a few hundred microseconds for PLL to lock */
5614 for (i = 0; i < timeout; ++i) {
5615 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5622 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5623 __func__, source, period_ns);
5629 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5632 struct ni_private *devpriv = dev->private;
5634 if (source == NI_MIO_INTERNAL_CLOCK) {
5635 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5636 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5637 RTSI_Trig_Direction_Register);
5638 devpriv->clock_ns = TIMEBASE_1_NS;
5639 if (boardtype.reg_type & ni_reg_m_series_mask) {
5640 devpriv->clock_and_fout2 &=
5641 ~(MSeries_Timebase1_Select_Bit |
5642 MSeries_Timebase3_Select_Bit);
5643 ni_writew(devpriv->clock_and_fout2,
5644 M_Offset_Clock_and_Fout2);
5645 ni_writew(0, M_Offset_PLL_Control);
5647 devpriv->clock_source = source;
5649 if (boardtype.reg_type & ni_reg_m_series_mask) {
5650 return ni_mseries_set_pll_master_clock(dev, source,
5653 if (source == NI_MIO_RTSI_CLOCK) {
5654 devpriv->rtsi_trig_direction_reg |=
5656 devpriv->stc_writew(dev,
5658 rtsi_trig_direction_reg,
5659 RTSI_Trig_Direction_Register);
5660 if (period_ns == 0) {
5662 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5666 devpriv->clock_ns = period_ns;
5668 devpriv->clock_source = source;
5676 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5679 if (chan >= num_configurable_rtsi_channels(dev)) {
5680 if (chan == old_RTSI_clock_channel) {
5681 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5685 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5686 __func__, chan, old_RTSI_clock_channel);
5693 case NI_RTSI_OUTPUT_ADR_START1:
5694 case NI_RTSI_OUTPUT_ADR_START2:
5695 case NI_RTSI_OUTPUT_SCLKG:
5696 case NI_RTSI_OUTPUT_DACUPDN:
5697 case NI_RTSI_OUTPUT_DA_START1:
5698 case NI_RTSI_OUTPUT_G_SRC0:
5699 case NI_RTSI_OUTPUT_G_GATE0:
5700 case NI_RTSI_OUTPUT_RGOUT0:
5701 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5704 case NI_RTSI_OUTPUT_RTSI_OSC:
5705 if (boardtype.reg_type & ni_reg_m_series_mask)
5716 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5719 struct ni_private *devpriv = dev->private;
5721 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5724 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5725 devpriv->rtsi_trig_a_output_reg |=
5726 RTSI_Trig_Output_Bits(chan, source);
5727 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5728 RTSI_Trig_A_Output_Register);
5729 } else if (chan < 8) {
5730 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5731 devpriv->rtsi_trig_b_output_reg |=
5732 RTSI_Trig_Output_Bits(chan, source);
5733 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5734 RTSI_Trig_B_Output_Register);
5739 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5741 struct ni_private *devpriv = dev->private;
5744 return RTSI_Trig_Output_Source(chan,
5745 devpriv->rtsi_trig_a_output_reg);
5746 } else if (chan < num_configurable_rtsi_channels(dev)) {
5747 return RTSI_Trig_Output_Source(chan,
5748 devpriv->rtsi_trig_b_output_reg);
5750 if (chan == old_RTSI_clock_channel)
5751 return NI_RTSI_OUTPUT_RTSI_OSC;
5752 printk("%s: bug! should never get here?\n", __func__);
5757 static int ni_rtsi_insn_config(struct comedi_device *dev,
5758 struct comedi_subdevice *s,
5759 struct comedi_insn *insn, unsigned int *data)
5761 struct ni_private *devpriv = dev->private;
5762 unsigned int chan = CR_CHAN(insn->chanspec);
5765 case INSN_CONFIG_DIO_OUTPUT:
5766 if (chan < num_configurable_rtsi_channels(dev)) {
5767 devpriv->rtsi_trig_direction_reg |=
5768 RTSI_Output_Bit(chan,
5770 reg_type & ni_reg_m_series_mask) !=
5772 } else if (chan == old_RTSI_clock_channel) {
5773 devpriv->rtsi_trig_direction_reg |=
5774 Drive_RTSI_Clock_Bit;
5776 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5777 RTSI_Trig_Direction_Register);
5779 case INSN_CONFIG_DIO_INPUT:
5780 if (chan < num_configurable_rtsi_channels(dev)) {
5781 devpriv->rtsi_trig_direction_reg &=
5782 ~RTSI_Output_Bit(chan,
5784 reg_type & ni_reg_m_series_mask)
5786 } else if (chan == old_RTSI_clock_channel) {
5787 devpriv->rtsi_trig_direction_reg &=
5788 ~Drive_RTSI_Clock_Bit;
5790 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5791 RTSI_Trig_Direction_Register);
5793 case INSN_CONFIG_DIO_QUERY:
5794 if (chan < num_configurable_rtsi_channels(dev)) {
5796 (devpriv->rtsi_trig_direction_reg &
5797 RTSI_Output_Bit(chan,
5798 (boardtype.reg_type &
5799 ni_reg_m_series_mask)
5800 != 0)) ? INSN_CONFIG_DIO_OUTPUT :
5801 INSN_CONFIG_DIO_INPUT;
5802 } else if (chan == old_RTSI_clock_channel) {
5804 (devpriv->rtsi_trig_direction_reg &
5805 Drive_RTSI_Clock_Bit)
5806 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5810 case INSN_CONFIG_SET_CLOCK_SRC:
5811 return ni_set_master_clock(dev, data[1], data[2]);
5813 case INSN_CONFIG_GET_CLOCK_SRC:
5814 data[1] = devpriv->clock_source;
5815 data[2] = devpriv->clock_ns;
5818 case INSN_CONFIG_SET_ROUTING:
5819 return ni_set_rtsi_routing(dev, chan, data[1]);
5821 case INSN_CONFIG_GET_ROUTING:
5822 data[1] = ni_get_rtsi_routing(dev, chan);
5832 static int cs5529_wait_for_idle(struct comedi_device *dev)
5834 unsigned short status;
5835 const int timeout = HZ;
5838 for (i = 0; i < timeout; i++) {
5839 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5840 if ((status & CSS_ADC_BUSY) == 0) {
5843 set_current_state(TASK_INTERRUPTIBLE);
5844 if (schedule_timeout(1)) {
5848 /* printk("looped %i times waiting for idle\n", i); */
5850 printk("%s: %s: timeout\n", __FILE__, __func__);
5856 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5858 static const int timeout = 100;
5861 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5862 /* give time for command to start being serially clocked into cs5529.
5863 * this insures that the CSS_ADC_BUSY bit will get properly
5864 * set before we exit this function.
5866 for (i = 0; i < timeout; i++) {
5867 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5871 /* printk("looped %i times writing command to cs5529\n", i); */
5873 comedi_error(dev, "possible problem - never saw adc go busy?");
5877 /* write to cs5529 register */
5878 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5879 unsigned int reg_select_bits)
5881 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5882 CAL_ADC_Config_Data_High_Word_67xx);
5883 ni_ao_win_outw(dev, (value & 0xffff),
5884 CAL_ADC_Config_Data_Low_Word_67xx);
5885 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5886 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5887 if (cs5529_wait_for_idle(dev))
5888 comedi_error(dev, "time or signal in cs5529_config_write()");
5891 #ifdef NI_CS5529_DEBUG
5892 /* read from cs5529 register */
5893 static unsigned int cs5529_config_read(struct comedi_device *dev,
5894 unsigned int reg_select_bits)
5898 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5899 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5900 if (cs5529_wait_for_idle(dev))
5901 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5902 value = (ni_ao_win_inw(dev,
5903 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5905 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5910 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5913 unsigned short status;
5915 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5916 retval = cs5529_wait_for_idle(dev);
5919 "timeout or signal in cs5529_do_conversion()");
5922 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5923 if (status & CSS_OSC_DETECT) {
5925 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5928 if (status & CSS_OVERRANGE) {
5930 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5933 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5934 /* cs5529 returns 16 bit signed data in bipolar mode */
5940 static int cs5529_ai_insn_read(struct comedi_device *dev,
5941 struct comedi_subdevice *s,
5942 struct comedi_insn *insn, unsigned int *data)
5945 unsigned short sample;
5946 unsigned int channel_select;
5947 const unsigned int INTERNAL_REF = 0x1000;
5949 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5950 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5951 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5952 if (insn->chanspec & CR_ALT_SOURCE)
5953 channel_select = INTERNAL_REF;
5955 channel_select = CR_CHAN(insn->chanspec);
5956 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5958 for (n = 0; n < insn->n; n++) {
5959 retval = cs5529_do_conversion(dev, &sample);
5967 static int init_cs5529(struct comedi_device *dev)
5969 unsigned int config_bits =
5970 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5973 /* do self-calibration */
5974 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5975 CSCMD_CONFIG_REGISTER);
5976 /* need to force a conversion for calibration to run */
5977 cs5529_do_conversion(dev, NULL);
5979 /* force gain calibration to 1 */
5980 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5981 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5982 CSCMD_CONFIG_REGISTER);
5983 if (cs5529_wait_for_idle(dev))
5984 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5986 #ifdef NI_CS5529_DEBUG
5987 printk("config: 0x%x\n", cs5529_config_read(dev,
5988 CSCMD_CONFIG_REGISTER));
5989 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
5990 printk("offset: 0x%x\n", cs5529_config_read(dev,
5991 CSCMD_OFFSET_REGISTER));