2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
29 Interrupt support originally added by Truxton Fulton
32 References (from ftp://ftp.natinst.com/support/manuals):
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
40 Other possibly relevant info:
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
45 320906c.pdf maximum signal ratings
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
54 - the interrupt routine needs to be cleaned up
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
64 #include <linux/interrupt.h>
67 #include "comedi_fc.h"
70 #define MDPRINTK(format, args...)
74 #define NI_TIMEOUT 1000
75 static const unsigned old_RTSI_clock_channel = 7;
77 /* Note: this table must match the ai_gain_* definitions */
78 static const short ni_gainlkup[][16] = {
79 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
80 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
81 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
82 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
83 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
84 [ai_gain_4] = {0, 1, 4, 7},
85 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
86 0x003, 0x004, 0x005, 0x006},
87 [ai_gain_622x] = {0, 1, 4, 5},
88 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
89 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
92 static const struct comedi_lrange range_ni_E_ai = { 16, {
112 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
125 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
150 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
160 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
172 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
180 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
191 static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
196 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
204 static const struct comedi_lrange *const ni_range_lkup[] = {
205 [ai_gain_16] = &range_ni_E_ai,
206 [ai_gain_8] = &range_ni_E_ai_limited,
207 [ai_gain_14] = &range_ni_E_ai_limited14,
208 [ai_gain_4] = &range_ni_E_ai_bipolar4,
209 [ai_gain_611x] = &range_ni_E_ai_611x,
210 [ai_gain_622x] = &range_ni_M_ai_622x,
211 [ai_gain_628x] = &range_ni_M_ai_628x,
212 [ai_gain_6143] = &range_ni_S_ai_6143
215 static int ni_dio_insn_config(struct comedi_device *dev,
216 struct comedi_subdevice *s,
217 struct comedi_insn *insn, unsigned int *data);
218 static int ni_dio_insn_bits(struct comedi_device *dev,
219 struct comedi_subdevice *s,
220 struct comedi_insn *insn, unsigned int *data);
221 static int ni_cdio_cmdtest(struct comedi_device *dev,
222 struct comedi_subdevice *s, struct comedi_cmd *cmd);
223 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
224 static int ni_cdio_cancel(struct comedi_device *dev,
225 struct comedi_subdevice *s);
226 static void handle_cdio_interrupt(struct comedi_device *dev);
227 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
228 unsigned int trignum);
230 static int ni_serial_insn_config(struct comedi_device *dev,
231 struct comedi_subdevice *s,
232 struct comedi_insn *insn, unsigned int *data);
233 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 unsigned char data_out,
236 unsigned char *data_in);
237 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
238 struct comedi_subdevice *s,
239 unsigned char data_out,
240 unsigned char *data_in);
242 static int ni_calib_insn_read(struct comedi_device *dev,
243 struct comedi_subdevice *s,
244 struct comedi_insn *insn, unsigned int *data);
245 static int ni_calib_insn_write(struct comedi_device *dev,
246 struct comedi_subdevice *s,
247 struct comedi_insn *insn, unsigned int *data);
249 static int ni_eeprom_insn_read(struct comedi_device *dev,
250 struct comedi_subdevice *s,
251 struct comedi_insn *insn, unsigned int *data);
252 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
253 struct comedi_subdevice *s,
254 struct comedi_insn *insn,
257 static int ni_pfi_insn_bits(struct comedi_device *dev,
258 struct comedi_subdevice *s,
259 struct comedi_insn *insn, unsigned int *data);
260 static int ni_pfi_insn_config(struct comedi_device *dev,
261 struct comedi_subdevice *s,
262 struct comedi_insn *insn, unsigned int *data);
263 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
266 static void ni_rtsi_init(struct comedi_device *dev);
267 static int ni_rtsi_insn_bits(struct comedi_device *dev,
268 struct comedi_subdevice *s,
269 struct comedi_insn *insn, unsigned int *data);
270 static int ni_rtsi_insn_config(struct comedi_device *dev,
271 struct comedi_subdevice *s,
272 struct comedi_insn *insn, unsigned int *data);
274 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
275 static int ni_read_eeprom(struct comedi_device *dev, int addr);
277 #ifdef DEBUG_STATUS_A
278 static void ni_mio_print_status_a(int status);
280 #define ni_mio_print_status_a(a)
282 #ifdef DEBUG_STATUS_B
283 static void ni_mio_print_status_b(int status);
285 #define ni_mio_print_status_b(a)
288 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
290 static void ni_handle_fifo_half_full(struct comedi_device *dev);
291 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
292 struct comedi_subdevice *s);
294 static void ni_handle_fifo_dregs(struct comedi_device *dev);
295 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
296 unsigned int trignum);
297 static void ni_load_channelgain_list(struct comedi_device *dev,
298 unsigned int n_chan, unsigned int *list);
299 static void shutdown_ai_command(struct comedi_device *dev);
301 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
302 unsigned int trignum);
304 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
306 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
308 static int ni_gpct_insn_write(struct comedi_device *dev,
309 struct comedi_subdevice *s,
310 struct comedi_insn *insn, unsigned int *data);
311 static int ni_gpct_insn_read(struct comedi_device *dev,
312 struct comedi_subdevice *s,
313 struct comedi_insn *insn, unsigned int *data);
314 static int ni_gpct_insn_config(struct comedi_device *dev,
315 struct comedi_subdevice *s,
316 struct comedi_insn *insn, unsigned int *data);
317 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
318 static int ni_gpct_cmdtest(struct comedi_device *dev,
319 struct comedi_subdevice *s, struct comedi_cmd *cmd);
320 static int ni_gpct_cancel(struct comedi_device *dev,
321 struct comedi_subdevice *s);
322 static void handle_gpct_interrupt(struct comedi_device *dev,
323 unsigned short counter_index);
325 static int init_cs5529(struct comedi_device *dev);
326 static int cs5529_do_conversion(struct comedi_device *dev,
327 unsigned short *data);
328 static int cs5529_ai_insn_read(struct comedi_device *dev,
329 struct comedi_subdevice *s,
330 struct comedi_insn *insn, unsigned int *data);
331 #ifdef NI_CS5529_DEBUG
332 static unsigned int cs5529_config_read(struct comedi_device *dev,
333 unsigned int reg_select_bits);
335 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
336 unsigned int reg_select_bits);
338 static int ni_m_series_pwm_config(struct comedi_device *dev,
339 struct comedi_subdevice *s,
340 struct comedi_insn *insn, unsigned int *data);
341 static int ni_6143_pwm_config(struct comedi_device *dev,
342 struct comedi_subdevice *s,
343 struct comedi_insn *insn, unsigned int *data);
345 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
347 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
348 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
352 AIMODE_HALF_FULL = 1,
357 enum ni_common_subdevices {
363 NI_CALIBRATION_SUBDEV,
366 NI_CS5529_CALIBRATION_SUBDEV,
374 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
376 switch (counter_index) {
378 return NI_GPCT0_SUBDEV;
381 return NI_GPCT1_SUBDEV;
387 return NI_GPCT0_SUBDEV;
390 enum timebase_nanoseconds {
392 TIMEBASE_2_NS = 10000
395 #define SERIAL_DISABLED 0
396 #define SERIAL_600NS 600
397 #define SERIAL_1_2US 1200
398 #define SERIAL_10US 10000
400 static const int num_adc_stages_611x = 3;
402 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
403 unsigned ai_mite_status);
404 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
405 unsigned ao_mite_status);
406 static void get_last_sample_611x(struct comedi_device *dev);
407 static void get_last_sample_6143(struct comedi_device *dev);
409 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
410 unsigned bit_mask, unsigned bit_values)
414 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
416 case Interrupt_A_Enable_Register:
417 devpriv->int_a_enable_reg &= ~bit_mask;
418 devpriv->int_a_enable_reg |= bit_values & bit_mask;
419 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
420 Interrupt_A_Enable_Register);
422 case Interrupt_B_Enable_Register:
423 devpriv->int_b_enable_reg &= ~bit_mask;
424 devpriv->int_b_enable_reg |= bit_values & bit_mask;
425 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
426 Interrupt_B_Enable_Register);
428 case IO_Bidirection_Pin_Register:
429 devpriv->io_bidirection_pin_reg &= ~bit_mask;
430 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
431 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
432 IO_Bidirection_Pin_Register);
435 devpriv->ai_ao_select_reg &= ~bit_mask;
436 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
437 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
440 devpriv->g0_g1_select_reg &= ~bit_mask;
441 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
442 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
445 printk("Warning %s() called with invalid register\n", __func__);
446 printk("reg is %d\n", reg);
450 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
454 static int ni_ai_drain_dma(struct comedi_device *dev);
456 /* DMA channel setup */
458 /* negative channel means no channel */
459 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
465 (ni_stc_dma_channel_select_bitfield(channel) <<
466 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
470 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
473 /* negative channel means no channel */
474 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
480 (ni_stc_dma_channel_select_bitfield(channel) <<
481 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
485 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
488 /* negative mite_channel means no channel */
489 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
495 if (mite_channel >= 0) {
496 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
500 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
504 /* negative mite_channel means no channel */
505 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
510 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
511 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
512 if (mite_channel >= 0) {
513 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
514 under the assumption the cdio dma selection works just like ai/ao/gpct.
515 Definitely works for dma channels 0 and 1. */
516 devpriv->cdio_dma_select_reg |=
517 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
518 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
520 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
522 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
525 static int ni_request_ai_mite_channel(struct comedi_device *dev)
529 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
530 BUG_ON(devpriv->ai_mite_chan);
531 devpriv->ai_mite_chan =
532 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
533 if (devpriv->ai_mite_chan == NULL) {
534 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
536 "failed to reserve mite dma channel for analog input.");
539 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
540 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
541 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
545 static int ni_request_ao_mite_channel(struct comedi_device *dev)
549 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
550 BUG_ON(devpriv->ao_mite_chan);
551 devpriv->ao_mite_chan =
552 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
553 if (devpriv->ao_mite_chan == NULL) {
554 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
556 "failed to reserve mite dma channel for analog outut.");
559 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
560 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
561 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
565 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
567 enum comedi_io_direction direction)
570 struct mite_channel *mite_chan;
572 BUG_ON(gpct_index >= NUM_GPCT);
573 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
574 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
576 mite_request_channel(devpriv->mite,
577 devpriv->gpct_mite_ring[gpct_index]);
578 if (mite_chan == NULL) {
579 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
581 "failed to reserve mite dma channel for counter.");
584 mite_chan->dir = direction;
585 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
587 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
588 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
594 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
599 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
600 BUG_ON(devpriv->cdo_mite_chan);
601 devpriv->cdo_mite_chan =
602 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
603 if (devpriv->cdo_mite_chan == NULL) {
604 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
606 "failed to reserve mite dma channel for correlated digital outut.");
609 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
610 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
611 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
616 static void ni_release_ai_mite_channel(struct comedi_device *dev)
621 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
622 if (devpriv->ai_mite_chan) {
623 ni_set_ai_dma_channel(dev, -1);
624 mite_release_channel(devpriv->ai_mite_chan);
625 devpriv->ai_mite_chan = NULL;
627 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
631 static void ni_release_ao_mite_channel(struct comedi_device *dev)
636 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
637 if (devpriv->ao_mite_chan) {
638 ni_set_ao_dma_channel(dev, -1);
639 mite_release_channel(devpriv->ao_mite_chan);
640 devpriv->ao_mite_chan = NULL;
642 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
646 void ni_release_gpct_mite_channel(struct comedi_device *dev,
652 BUG_ON(gpct_index >= NUM_GPCT);
653 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
654 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
655 struct mite_channel *mite_chan =
656 devpriv->counter_dev->counters[gpct_index].mite_chan;
658 ni_set_gpct_dma_channel(dev, gpct_index, -1);
659 ni_tio_set_mite_channel(&devpriv->
660 counter_dev->counters[gpct_index],
662 mite_release_channel(mite_chan);
664 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
668 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
673 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
674 if (devpriv->cdo_mite_chan) {
675 ni_set_cdo_dma_channel(dev, -1);
676 mite_release_channel(devpriv->cdo_mite_chan);
677 devpriv->cdo_mite_chan = NULL;
679 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
683 /* e-series boards use the second irq signals to generate dma requests for their counters */
685 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
686 unsigned gpct_index, short enable)
688 if (boardtype.reg_type & ni_reg_m_series_mask)
690 switch (gpct_index) {
693 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
694 Second_IRQ_A_Enable_Register);
696 devpriv->stc_writew(dev, 0,
697 Second_IRQ_A_Enable_Register);
702 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
703 Second_IRQ_B_Enable_Register);
705 devpriv->stc_writew(dev, 0,
706 Second_IRQ_B_Enable_Register);
716 static void ni_clear_ai_fifo(struct comedi_device *dev)
718 if (boardtype.reg_type == ni_reg_6143) {
719 /* Flush the 6143 data FIFO */
720 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
721 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
722 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
724 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
725 if (boardtype.reg_type == ni_reg_625x) {
726 ni_writeb(0, M_Offset_Static_AI_Control(0));
727 ni_writeb(1, M_Offset_Static_AI_Control(0));
729 /* the NI example code does 3 convert pulses for 625x boards,
730 but that appears to be wrong in practice. */
731 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
732 AI_Command_1_Register);
733 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
734 AI_Command_1_Register);
735 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
736 AI_Command_1_Register);
742 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
744 devpriv->stc_writew(dev, data >> 16, reg);
745 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
748 static uint32_t win_in2(struct comedi_device *dev, int reg)
751 bits = devpriv->stc_readw(dev, reg) << 16;
752 bits |= devpriv->stc_readw(dev, reg + 1);
756 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
757 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
762 spin_lock_irqsave(&devpriv->window_lock, flags);
763 ni_writew(addr, AO_Window_Address_611x);
764 ni_writew(data, AO_Window_Data_611x);
765 spin_unlock_irqrestore(&devpriv->window_lock, flags);
768 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
773 spin_lock_irqsave(&devpriv->window_lock, flags);
774 ni_writew(addr, AO_Window_Address_611x);
775 ni_writel(data, AO_Window_Data_611x);
776 spin_unlock_irqrestore(&devpriv->window_lock, flags);
779 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
784 spin_lock_irqsave(&devpriv->window_lock, flags);
785 ni_writew(addr, AO_Window_Address_611x);
786 data = ni_readw(AO_Window_Data_611x);
787 spin_unlock_irqrestore(&devpriv->window_lock, flags);
791 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
792 * share registers (such as Interrupt_A_Register) without interfering with
795 * NOTE: the switch/case statements are optimized out for a constant argument
796 * so this is actually quite fast--- If you must wrap another function around this
797 * make it inline to avoid a large speed penalty.
799 * value should only be 1 or 0.
801 static inline void ni_set_bits(struct comedi_device *dev, int reg,
802 unsigned bits, unsigned value)
810 ni_set_bitfield(dev, reg, bits, bit_values);
813 static irqreturn_t ni_E_interrupt(int irq, void *d)
815 struct comedi_device *dev = d;
816 unsigned short a_status;
817 unsigned short b_status;
818 unsigned int ai_mite_status = 0;
819 unsigned int ao_mite_status = 0;
822 struct mite_struct *mite = devpriv->mite;
825 if (dev->attached == 0)
827 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
829 /* lock to avoid race with comedi_poll */
830 spin_lock_irqsave(&dev->spinlock, flags);
831 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
832 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
835 unsigned long flags_too;
837 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
838 if (devpriv->ai_mite_chan) {
839 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
840 if (ai_mite_status & CHSR_LINKC)
842 devpriv->mite->mite_io_addr +
844 ai_mite_chan->channel));
846 if (devpriv->ao_mite_chan) {
847 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
848 if (ao_mite_status & CHSR_LINKC)
852 ao_mite_chan->channel));
854 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
857 ack_a_interrupt(dev, a_status);
858 ack_b_interrupt(dev, b_status);
859 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
860 handle_a_interrupt(dev, a_status, ai_mite_status);
861 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
862 handle_b_interrupt(dev, b_status, ao_mite_status);
863 handle_gpct_interrupt(dev, 0);
864 handle_gpct_interrupt(dev, 1);
865 handle_cdio_interrupt(dev);
867 spin_unlock_irqrestore(&dev->spinlock, flags);
872 static void ni_sync_ai_dma(struct comedi_device *dev)
874 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
877 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
878 if (devpriv->ai_mite_chan)
879 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
880 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
883 static void mite_handle_b_linkc(struct mite_struct *mite,
884 struct comedi_device *dev)
886 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
889 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
890 if (devpriv->ao_mite_chan) {
891 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
893 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
896 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
898 static const int timeout = 10000;
900 for (i = 0; i < timeout; i++) {
901 unsigned short b_status;
903 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
904 if (b_status & AO_FIFO_Half_Full_St)
906 /* if we poll too often, the pci bus activity seems
907 to slow the dma transfer down */
911 comedi_error(dev, "timed out waiting for dma load");
918 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
920 if (devpriv->aimode == AIMODE_SCAN) {
922 static const int timeout = 10;
925 for (i = 0; i < timeout; i++) {
927 if ((s->async->events & COMEDI_CB_EOS))
932 ni_handle_fifo_dregs(dev);
933 s->async->events |= COMEDI_CB_EOS;
936 /* handle special case of single scan using AI_End_On_End_Of_Scan */
937 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
938 shutdown_ai_command(dev);
942 static void shutdown_ai_command(struct comedi_device *dev)
944 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
947 ni_ai_drain_dma(dev);
949 ni_handle_fifo_dregs(dev);
950 get_last_sample_611x(dev);
951 get_last_sample_6143(dev);
953 s->async->events |= COMEDI_CB_EOA;
956 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
959 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
961 switch (s - dev->subdevices) {
968 case NI_GPCT0_SUBDEV:
969 case NI_GPCT1_SUBDEV:
970 ni_gpct_cancel(dev, s);
973 ni_cdio_cancel(dev, s);
979 comedi_event(dev, s);
982 static void handle_gpct_interrupt(struct comedi_device *dev,
983 unsigned short counter_index)
986 struct comedi_subdevice *s =
987 dev->subdevices + NI_GPCT_SUBDEV(counter_index);
989 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
991 if (s->async->events)
996 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
998 unsigned short ack = 0;
1000 if (a_status & AI_SC_TC_St) {
1001 ack |= AI_SC_TC_Interrupt_Ack;
1003 if (a_status & AI_START1_St) {
1004 ack |= AI_START1_Interrupt_Ack;
1006 if (a_status & AI_START_St) {
1007 ack |= AI_START_Interrupt_Ack;
1009 if (a_status & AI_STOP_St) {
1010 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1011 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1014 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1017 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1018 unsigned ai_mite_status)
1020 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1022 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1023 if (s->type == COMEDI_SUBD_UNUSED)
1026 #ifdef DEBUG_INTERRUPT
1028 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1029 status, ai_mite_status);
1030 ni_mio_print_status_a(status);
1033 if (ai_mite_status & CHSR_LINKC) {
1034 ni_sync_ai_dma(dev);
1037 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1038 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1039 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1041 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1043 /* mite_print_chsr(ai_mite_status); */
1044 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1045 /* disable_irq(dev->irq); */
1049 /* test for all uncommon interrupt events at the same time */
1050 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1051 AI_SC_TC_St | AI_START1_St)) {
1052 if (status == 0xffff) {
1054 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1055 /* we probably aren't even running a command now,
1056 * so it's a good idea to be careful. */
1057 if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1059 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1064 if (status & (AI_Overrun_St | AI_Overflow_St |
1065 AI_SC_TC_Error_St)) {
1066 printk("ni_mio_common: ai error a_status=%04x\n",
1068 ni_mio_print_status_a(status);
1070 shutdown_ai_command(dev);
1072 s->async->events |= COMEDI_CB_ERROR;
1073 if (status & (AI_Overrun_St | AI_Overflow_St))
1074 s->async->events |= COMEDI_CB_OVERFLOW;
1080 if (status & AI_SC_TC_St) {
1081 #ifdef DEBUG_INTERRUPT
1082 printk("ni_mio_common: SC_TC interrupt\n");
1084 if (!devpriv->ai_continuous) {
1085 shutdown_ai_command(dev);
1090 if (status & AI_FIFO_Half_Full_St) {
1092 static const int timeout = 10;
1093 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1094 *fail to get the fifo less than half full, so loop to be sure.*/
1095 for (i = 0; i < timeout; ++i) {
1096 ni_handle_fifo_half_full(dev);
1097 if ((devpriv->stc_readw(dev,
1098 AI_Status_1_Register) &
1099 AI_FIFO_Half_Full_St) == 0)
1103 #endif /* !PCIDMA */
1105 if ((status & AI_STOP_St)) {
1106 ni_handle_eos(dev, s);
1111 #ifdef DEBUG_INTERRUPT
1112 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1113 if (status & Interrupt_A_St) {
1115 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1121 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1123 unsigned short ack = 0;
1124 if (b_status & AO_BC_TC_St) {
1125 ack |= AO_BC_TC_Interrupt_Ack;
1127 if (b_status & AO_Overrun_St) {
1128 ack |= AO_Error_Interrupt_Ack;
1130 if (b_status & AO_START_St) {
1131 ack |= AO_START_Interrupt_Ack;
1133 if (b_status & AO_START1_St) {
1134 ack |= AO_START1_Interrupt_Ack;
1136 if (b_status & AO_UC_TC_St) {
1137 ack |= AO_UC_TC_Interrupt_Ack;
1139 if (b_status & AO_UI2_TC_St) {
1140 ack |= AO_UI2_TC_Interrupt_Ack;
1142 if (b_status & AO_UPDATE_St) {
1143 ack |= AO_UPDATE_Interrupt_Ack;
1146 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1149 static void handle_b_interrupt(struct comedi_device *dev,
1150 unsigned short b_status, unsigned ao_mite_status)
1152 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1153 /* unsigned short ack=0; */
1154 #ifdef DEBUG_INTERRUPT
1155 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1156 b_status, ao_mite_status);
1157 ni_mio_print_status_b(b_status);
1161 /* Currently, mite.c requires us to handle LINKC */
1162 if (ao_mite_status & CHSR_LINKC) {
1163 mite_handle_b_linkc(devpriv->mite, dev);
1166 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1167 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1168 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1170 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1172 /* mite_print_chsr(ao_mite_status); */
1173 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1177 if (b_status == 0xffff)
1179 if (b_status & AO_Overrun_St) {
1181 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1182 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1183 s->async->events |= COMEDI_CB_OVERFLOW;
1186 if (b_status & AO_BC_TC_St) {
1188 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1189 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1190 s->async->events |= COMEDI_CB_EOA;
1193 if (b_status & AO_FIFO_Request_St) {
1196 ret = ni_ao_fifo_half_empty(dev, s);
1198 printk("ni_mio_common: AO buffer underrun\n");
1199 ni_set_bits(dev, Interrupt_B_Enable_Register,
1200 AO_FIFO_Interrupt_Enable |
1201 AO_Error_Interrupt_Enable, 0);
1202 s->async->events |= COMEDI_CB_OVERFLOW;
1210 #ifdef DEBUG_STATUS_A
1211 static const char *const status_a_strings[] = {
1212 "passthru0", "fifo", "G0_gate", "G0_TC",
1213 "stop", "start", "sc_tc", "start1",
1214 "start2", "sc_tc_error", "overflow", "overrun",
1215 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1218 static void ni_mio_print_status_a(int status)
1222 printk("A status:");
1223 for (i = 15; i >= 0; i--) {
1224 if (status & (1 << i)) {
1225 printk(" %s", status_a_strings[i]);
1232 #ifdef DEBUG_STATUS_B
1233 static const char *const status_b_strings[] = {
1234 "passthru1", "fifo", "G1_gate", "G1_TC",
1235 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1236 "start1", "overrun", "start", "bc_tc_error",
1237 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1240 static void ni_mio_print_status_b(int status)
1244 printk("B status:");
1245 for (i = 15; i >= 0; i--) {
1246 if (status & (1 << i)) {
1247 printk(" %s", status_b_strings[i]);
1256 static void ni_ao_fifo_load(struct comedi_device *dev,
1257 struct comedi_subdevice *s, int n)
1259 struct comedi_async *async = s->async;
1260 struct comedi_cmd *cmd = &async->cmd;
1268 chan = async->cur_chan;
1269 for (i = 0; i < n; i++) {
1270 err &= comedi_buf_get(async, &d);
1274 range = CR_RANGE(cmd->chanlist[chan]);
1276 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1277 packed_data = d & 0xffff;
1278 /* 6711 only has 16 bit wide ao fifo */
1279 if (boardtype.reg_type != ni_reg_6711) {
1280 err &= comedi_buf_get(async, &d);
1285 packed_data |= (d << 16) & 0xffff0000;
1287 ni_writel(packed_data, DAC_FIFO_Data_611x);
1289 ni_writew(d, DAC_FIFO_Data);
1292 chan %= cmd->chanlist_len;
1294 async->cur_chan = chan;
1296 async->events |= COMEDI_CB_OVERFLOW;
1301 * There's a small problem if the FIFO gets really low and we
1302 * don't have the data to fill it. Basically, if after we fill
1303 * the FIFO with all the data available, the FIFO is _still_
1304 * less than half full, we never clear the interrupt. If the
1305 * IRQ is in edge mode, we never get another interrupt, because
1306 * this one wasn't cleared. If in level mode, we get flooded
1307 * with interrupts that we can't fulfill, because nothing ever
1308 * gets put into the buffer.
1310 * This kind of situation is recoverable, but it is easier to
1311 * just pretend we had a FIFO underrun, since there is a good
1312 * chance it will happen anyway. This is _not_ the case for
1313 * RT code, as RT code might purposely be running close to the
1314 * metal. Needs to be fixed eventually.
1316 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1317 struct comedi_subdevice *s)
1321 n = comedi_buf_read_n_available(s->async);
1323 s->async->events |= COMEDI_CB_OVERFLOW;
1328 if (n > boardtype.ao_fifo_depth / 2)
1329 n = boardtype.ao_fifo_depth / 2;
1331 ni_ao_fifo_load(dev, s, n);
1333 s->async->events |= COMEDI_CB_BLOCK;
1338 static int ni_ao_prep_fifo(struct comedi_device *dev,
1339 struct comedi_subdevice *s)
1344 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1345 if (boardtype.reg_type & ni_reg_6xxx_mask)
1346 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1348 /* load some data */
1349 n = comedi_buf_read_n_available(s->async);
1354 if (n > boardtype.ao_fifo_depth)
1355 n = boardtype.ao_fifo_depth;
1357 ni_ao_fifo_load(dev, s, n);
1362 static void ni_ai_fifo_read(struct comedi_device *dev,
1363 struct comedi_subdevice *s, int n)
1365 struct comedi_async *async = s->async;
1368 if (boardtype.reg_type == ni_reg_611x) {
1372 for (i = 0; i < n / 2; i++) {
1373 dl = ni_readl(ADC_FIFO_Data_611x);
1374 /* This may get the hi/lo data in the wrong order */
1375 data[0] = (dl >> 16) & 0xffff;
1376 data[1] = dl & 0xffff;
1377 cfc_write_array_to_buffer(s, data, sizeof(data));
1379 /* Check if there's a single sample stuck in the FIFO */
1381 dl = ni_readl(ADC_FIFO_Data_611x);
1382 data[0] = dl & 0xffff;
1383 cfc_write_to_buffer(s, data[0]);
1385 } else if (boardtype.reg_type == ni_reg_6143) {
1389 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1390 for (i = 0; i < n / 2; i++) {
1391 dl = ni_readl(AIFIFO_Data_6143);
1393 data[0] = (dl >> 16) & 0xffff;
1394 data[1] = dl & 0xffff;
1395 cfc_write_array_to_buffer(s, data, sizeof(data));
1398 /* Assume there is a single sample stuck in the FIFO */
1399 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1400 dl = ni_readl(AIFIFO_Data_6143);
1401 data[0] = (dl >> 16) & 0xffff;
1402 cfc_write_to_buffer(s, data[0]);
1405 if (n > sizeof(devpriv->ai_fifo_buffer) /
1406 sizeof(devpriv->ai_fifo_buffer[0])) {
1407 comedi_error(dev, "bug! ai_fifo_buffer too small");
1408 async->events |= COMEDI_CB_ERROR;
1411 for (i = 0; i < n; i++) {
1412 devpriv->ai_fifo_buffer[i] =
1413 ni_readw(ADC_FIFO_Data_Register);
1415 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1417 sizeof(devpriv->ai_fifo_buffer[0]));
1421 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1424 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1426 n = boardtype.ai_fifo_depth / 2;
1428 ni_ai_fifo_read(dev, s, n);
1433 static int ni_ai_drain_dma(struct comedi_device *dev)
1436 static const int timeout = 10000;
1437 unsigned long flags;
1440 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1441 if (devpriv->ai_mite_chan) {
1442 for (i = 0; i < timeout; i++) {
1443 if ((devpriv->stc_readw(dev,
1444 AI_Status_1_Register) &
1446 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1452 printk("ni_mio_common: wait for dma drain timed out\n");
1454 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1455 mite_bytes_in_transit(devpriv->ai_mite_chan),
1456 devpriv->stc_readw(dev, AI_Status_1_Register));
1460 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1462 ni_sync_ai_dma(dev);
1470 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1472 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1478 if (boardtype.reg_type == ni_reg_611x) {
1479 while ((devpriv->stc_readw(dev,
1480 AI_Status_1_Register) &
1481 AI_FIFO_Empty_St) == 0) {
1482 dl = ni_readl(ADC_FIFO_Data_611x);
1484 /* This may get the hi/lo data in the wrong order */
1485 data[0] = (dl >> 16);
1486 data[1] = (dl & 0xffff);
1487 cfc_write_array_to_buffer(s, data, sizeof(data));
1489 } else if (boardtype.reg_type == ni_reg_6143) {
1491 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1492 dl = ni_readl(AIFIFO_Data_6143);
1494 /* This may get the hi/lo data in the wrong order */
1495 data[0] = (dl >> 16);
1496 data[1] = (dl & 0xffff);
1497 cfc_write_array_to_buffer(s, data, sizeof(data));
1500 /* Check if stranded sample is present */
1501 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1502 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1503 dl = ni_readl(AIFIFO_Data_6143);
1504 data[0] = (dl >> 16) & 0xffff;
1505 cfc_write_to_buffer(s, data[0]);
1510 devpriv->stc_readw(dev,
1511 AI_Status_1_Register) & AI_FIFO_Empty_St;
1512 while (fifo_empty == 0) {
1515 sizeof(devpriv->ai_fifo_buffer) /
1516 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1518 devpriv->stc_readw(dev,
1519 AI_Status_1_Register) &
1523 devpriv->ai_fifo_buffer[i] =
1524 ni_readw(ADC_FIFO_Data_Register);
1526 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1529 ai_fifo_buffer[0]));
1534 static void get_last_sample_611x(struct comedi_device *dev)
1536 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1540 if (boardtype.reg_type != ni_reg_611x)
1543 /* Check if there's a single sample stuck in the FIFO */
1544 if (ni_readb(XXX_Status) & 0x80) {
1545 dl = ni_readl(ADC_FIFO_Data_611x);
1546 data = (dl & 0xffff);
1547 cfc_write_to_buffer(s, data);
1551 static void get_last_sample_6143(struct comedi_device *dev)
1553 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1557 if (boardtype.reg_type != ni_reg_6143)
1560 /* Check if there's a single sample stuck in the FIFO */
1561 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1562 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1563 dl = ni_readl(AIFIFO_Data_6143);
1565 /* This may get the hi/lo data in the wrong order */
1566 data = (dl >> 16) & 0xffff;
1567 cfc_write_to_buffer(s, data);
1571 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1572 void *data, unsigned int num_bytes,
1573 unsigned int chan_index)
1575 struct comedi_async *async = s->async;
1577 unsigned int length = num_bytes / bytes_per_sample(s);
1578 short *array = data;
1579 unsigned int *larray = data;
1580 for (i = 0; i < length; i++) {
1582 if (s->subdev_flags & SDF_LSAMPL)
1583 larray[i] = le32_to_cpu(larray[i]);
1585 array[i] = le16_to_cpu(array[i]);
1587 if (s->subdev_flags & SDF_LSAMPL)
1588 larray[i] += devpriv->ai_offset[chan_index];
1590 array[i] += devpriv->ai_offset[chan_index];
1592 chan_index %= async->cmd.chanlist_len;
1598 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1600 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1602 unsigned long flags;
1604 retval = ni_request_ai_mite_channel(dev);
1607 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1609 /* write alloc the entire buffer */
1610 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1612 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1613 if (devpriv->ai_mite_chan == NULL) {
1614 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1618 switch (boardtype.reg_type) {
1621 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1624 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1627 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1631 mite_dma_arm(devpriv->ai_mite_chan);
1632 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1637 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1639 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1641 unsigned long flags;
1643 retval = ni_request_ao_mite_channel(dev);
1647 /* read alloc the entire buffer */
1648 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1650 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1651 if (devpriv->ao_mite_chan) {
1652 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1653 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1655 /* doing 32 instead of 16 bit wide transfers from memory
1656 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1657 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1659 mite_dma_arm(devpriv->ao_mite_chan);
1662 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1670 used for both cancel ioctl and board initialization
1672 this is pretty harsh for a cancel, but it works...
1675 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1677 ni_release_ai_mite_channel(dev);
1678 /* ai configuration */
1679 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1680 Joint_Reset_Register);
1682 ni_set_bits(dev, Interrupt_A_Enable_Register,
1683 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1684 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1685 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1686 AI_FIFO_Interrupt_Enable, 0);
1688 ni_clear_ai_fifo(dev);
1690 if (boardtype.reg_type != ni_reg_6143)
1691 ni_writeb(0, Misc_Command);
1693 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1694 devpriv->stc_writew(dev,
1695 AI_Start_Stop | AI_Mode_1_Reserved
1696 /*| AI_Trigger_Once */ ,
1697 AI_Mode_1_Register);
1698 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1699 /* generate FIFO interrupts on non-empty */
1700 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1701 if (boardtype.reg_type == ni_reg_611x) {
1702 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1704 AI_LOCALMUX_CLK_Pulse_Width,
1705 AI_Personal_Register);
1706 devpriv->stc_writew(dev,
1707 AI_SCAN_IN_PROG_Output_Select(3) |
1708 AI_EXTMUX_CLK_Output_Select(0) |
1709 AI_LOCALMUX_CLK_Output_Select(2) |
1710 AI_SC_TC_Output_Select(3) |
1711 AI_CONVERT_Output_Select
1712 (AI_CONVERT_Output_Enable_High),
1713 AI_Output_Control_Register);
1714 } else if (boardtype.reg_type == ni_reg_6143) {
1715 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1717 AI_LOCALMUX_CLK_Pulse_Width,
1718 AI_Personal_Register);
1719 devpriv->stc_writew(dev,
1720 AI_SCAN_IN_PROG_Output_Select(3) |
1721 AI_EXTMUX_CLK_Output_Select(0) |
1722 AI_LOCALMUX_CLK_Output_Select(2) |
1723 AI_SC_TC_Output_Select(3) |
1724 AI_CONVERT_Output_Select
1725 (AI_CONVERT_Output_Enable_Low),
1726 AI_Output_Control_Register);
1728 unsigned ai_output_control_bits;
1729 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1731 AI_CONVERT_Pulse_Width |
1732 AI_LOCALMUX_CLK_Pulse_Width,
1733 AI_Personal_Register);
1734 ai_output_control_bits =
1735 AI_SCAN_IN_PROG_Output_Select(3) |
1736 AI_EXTMUX_CLK_Output_Select(0) |
1737 AI_LOCALMUX_CLK_Output_Select(2) |
1738 AI_SC_TC_Output_Select(3);
1739 if (boardtype.reg_type == ni_reg_622x)
1740 ai_output_control_bits |=
1741 AI_CONVERT_Output_Select
1742 (AI_CONVERT_Output_Enable_High);
1744 ai_output_control_bits |=
1745 AI_CONVERT_Output_Select
1746 (AI_CONVERT_Output_Enable_Low);
1747 devpriv->stc_writew(dev, ai_output_control_bits,
1748 AI_Output_Control_Register);
1750 /* the following registers should not be changed, because there
1751 * are no backup registers in devpriv. If you want to change
1752 * any of these, add a backup register and other appropriate code:
1753 * AI_Mode_1_Register
1754 * AI_Mode_3_Register
1755 * AI_Personal_Register
1756 * AI_Output_Control_Register
1758 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1760 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1765 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1767 unsigned long flags = 0;
1770 /* lock to avoid race with interrupt handler */
1771 if (in_interrupt() == 0)
1772 spin_lock_irqsave(&dev->spinlock, flags);
1774 ni_handle_fifo_dregs(dev);
1776 ni_sync_ai_dma(dev);
1778 count = s->async->buf_write_count - s->async->buf_read_count;
1779 if (in_interrupt() == 0)
1780 spin_unlock_irqrestore(&dev->spinlock, flags);
1785 static int ni_ai_insn_read(struct comedi_device *dev,
1786 struct comedi_subdevice *s, struct comedi_insn *insn,
1790 const unsigned int mask = (1 << boardtype.adbits) - 1;
1795 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1797 ni_clear_ai_fifo(dev);
1799 signbits = devpriv->ai_offset[0];
1800 if (boardtype.reg_type == ni_reg_611x) {
1801 for (n = 0; n < num_adc_stages_611x; n++) {
1802 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1803 AI_Command_1_Register);
1806 for (n = 0; n < insn->n; n++) {
1807 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1808 AI_Command_1_Register);
1809 /* The 611x has screwy 32-bit FIFOs. */
1811 for (i = 0; i < NI_TIMEOUT; i++) {
1812 if (ni_readb(XXX_Status) & 0x80) {
1813 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1817 if (!(devpriv->stc_readw(dev,
1818 AI_Status_1_Register) &
1819 AI_FIFO_Empty_St)) {
1820 d = ni_readl(ADC_FIFO_Data_611x) &
1825 if (i == NI_TIMEOUT) {
1827 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1833 } else if (boardtype.reg_type == ni_reg_6143) {
1834 for (n = 0; n < insn->n; n++) {
1835 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1836 AI_Command_1_Register);
1838 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1840 for (i = 0; i < NI_TIMEOUT; i++) {
1841 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1842 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1843 dl = ni_readl(AIFIFO_Data_6143);
1847 if (i == NI_TIMEOUT) {
1849 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1852 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1855 for (n = 0; n < insn->n; n++) {
1856 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1857 AI_Command_1_Register);
1858 for (i = 0; i < NI_TIMEOUT; i++) {
1859 if (!(devpriv->stc_readw(dev,
1860 AI_Status_1_Register) &
1864 if (i == NI_TIMEOUT) {
1866 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1869 if (boardtype.reg_type & ni_reg_m_series_mask) {
1871 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1873 d = ni_readw(ADC_FIFO_Data_Register);
1874 d += signbits; /* subtle: needs to be short addition */
1882 void ni_prime_channelgain_list(struct comedi_device *dev)
1885 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1886 for (i = 0; i < NI_TIMEOUT; ++i) {
1887 if (!(devpriv->stc_readw(dev,
1888 AI_Status_1_Register) &
1889 AI_FIFO_Empty_St)) {
1890 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1895 printk("ni_mio_common: timeout loading channel/gain list\n");
1898 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1899 unsigned int n_chan,
1902 unsigned int chan, range, aref;
1905 unsigned int dither;
1906 unsigned range_code;
1908 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1910 /* offset = 1 << (boardtype.adbits - 1); */
1911 if ((list[0] & CR_ALT_SOURCE)) {
1912 unsigned bypass_bits;
1913 chan = CR_CHAN(list[0]);
1914 range = CR_RANGE(list[0]);
1915 range_code = ni_gainlkup[boardtype.gainlkup][range];
1916 dither = ((list[0] & CR_ALT_FILTER) != 0);
1917 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1918 bypass_bits |= chan;
1920 (devpriv->ai_calib_source) &
1921 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1922 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1923 MSeries_AI_Bypass_Mode_Mux_Mask |
1924 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1925 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1927 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1928 /* don't use 2's complement encoding */
1929 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1930 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1932 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1935 for (i = 0; i < n_chan; i++) {
1936 unsigned config_bits = 0;
1937 chan = CR_CHAN(list[i]);
1938 aref = CR_AREF(list[i]);
1939 range = CR_RANGE(list[i]);
1940 dither = ((list[i] & CR_ALT_FILTER) != 0);
1942 range_code = ni_gainlkup[boardtype.gainlkup][range];
1943 devpriv->ai_offset[i] = offset;
1947 MSeries_AI_Config_Channel_Type_Differential_Bits;
1951 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1955 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1960 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1962 MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
1963 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1964 if (i == n_chan - 1)
1965 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1967 config_bits |= MSeries_AI_Config_Dither_Bit;
1968 /* don't use 2's complement encoding */
1969 config_bits |= MSeries_AI_Config_Polarity_Bit;
1970 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1972 ni_prime_channelgain_list(dev);
1976 * Notes on the 6110 and 6111:
1977 * These boards a slightly different than the rest of the series, since
1978 * they have multiple A/D converters.
1979 * From the driver side, the configuration memory is a
1981 * Configuration Memory Low:
1983 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1984 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1985 * 1001 gain=0.1 (+/- 50)
1994 * Configuration Memory High:
1995 * bits 12-14: Channel Type
1996 * 001 for differential
1997 * 000 for calibration
1998 * bit 11: coupling (this is not currently handled)
2002 * valid channels are 0-3
2004 static void ni_load_channelgain_list(struct comedi_device *dev,
2005 unsigned int n_chan, unsigned int *list)
2007 unsigned int chan, range, aref;
2009 unsigned int hi, lo;
2011 unsigned int dither;
2013 if (boardtype.reg_type & ni_reg_m_series_mask) {
2014 ni_m_series_load_channelgain_list(dev, n_chan, list);
2017 if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
2018 && (boardtype.reg_type != ni_reg_6143)) {
2019 if (devpriv->changain_state
2020 && devpriv->changain_spec == list[0]) {
2024 devpriv->changain_state = 1;
2025 devpriv->changain_spec = list[0];
2027 devpriv->changain_state = 0;
2030 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2032 /* Set up Calibration mode if required */
2033 if (boardtype.reg_type == ni_reg_6143) {
2034 if ((list[0] & CR_ALT_SOURCE)
2035 && !devpriv->ai_calib_source_enabled) {
2036 /* Strobe Relay enable bit */
2037 ni_writew(devpriv->ai_calib_source |
2038 Calibration_Channel_6143_RelayOn,
2039 Calibration_Channel_6143);
2040 ni_writew(devpriv->ai_calib_source,
2041 Calibration_Channel_6143);
2042 devpriv->ai_calib_source_enabled = 1;
2043 msleep_interruptible(100); /* Allow relays to change */
2044 } else if (!(list[0] & CR_ALT_SOURCE)
2045 && devpriv->ai_calib_source_enabled) {
2046 /* Strobe Relay disable bit */
2047 ni_writew(devpriv->ai_calib_source |
2048 Calibration_Channel_6143_RelayOff,
2049 Calibration_Channel_6143);
2050 ni_writew(devpriv->ai_calib_source,
2051 Calibration_Channel_6143);
2052 devpriv->ai_calib_source_enabled = 0;
2053 msleep_interruptible(100); /* Allow relays to change */
2057 offset = 1 << (boardtype.adbits - 1);
2058 for (i = 0; i < n_chan; i++) {
2059 if ((boardtype.reg_type != ni_reg_6143)
2060 && (list[i] & CR_ALT_SOURCE)) {
2061 chan = devpriv->ai_calib_source;
2063 chan = CR_CHAN(list[i]);
2065 aref = CR_AREF(list[i]);
2066 range = CR_RANGE(list[i]);
2067 dither = ((list[i] & CR_ALT_FILTER) != 0);
2069 /* fix the external/internal range differences */
2070 range = ni_gainlkup[boardtype.gainlkup][range];
2071 if (boardtype.reg_type == ni_reg_611x)
2072 devpriv->ai_offset[i] = offset;
2074 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2077 if ((list[i] & CR_ALT_SOURCE)) {
2078 if (boardtype.reg_type == ni_reg_611x)
2079 ni_writew(CR_CHAN(list[i]) & 0x0003,
2080 Calibration_Channel_Select_611x);
2082 if (boardtype.reg_type == ni_reg_611x)
2084 else if (boardtype.reg_type == ni_reg_6143)
2088 hi |= AI_DIFFERENTIAL;
2100 hi |= AI_CONFIG_CHANNEL(chan);
2102 ni_writew(hi, Configuration_Memory_High);
2104 if (boardtype.reg_type != ni_reg_6143) {
2106 if (i == n_chan - 1)
2107 lo |= AI_LAST_CHANNEL;
2111 ni_writew(lo, Configuration_Memory_Low);
2115 /* prime the channel/gain list */
2116 if ((boardtype.reg_type != ni_reg_611x)
2117 && (boardtype.reg_type != ni_reg_6143)) {
2118 ni_prime_channelgain_list(dev);
2122 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2126 switch (round_mode) {
2127 case TRIG_ROUND_NEAREST:
2129 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2131 case TRIG_ROUND_DOWN:
2132 divider = (nanosec) / devpriv->clock_ns;
2135 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2141 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2143 return devpriv->clock_ns * (timer + 1);
2146 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2147 unsigned num_channels)
2149 switch (boardtype.reg_type) {
2152 /* simultaneously-sampled inputs */
2153 return boardtype.ai_speed;
2156 /* multiplexed inputs */
2159 return boardtype.ai_speed * num_channels;
2162 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2163 struct comedi_cmd *cmd)
2169 /* step 1: make sure trigger sources are trivially valid */
2171 if ((cmd->flags & CMDF_WRITE)) {
2172 cmd->flags &= ~CMDF_WRITE;
2175 tmp = cmd->start_src;
2176 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
2177 if (!cmd->start_src || tmp != cmd->start_src)
2180 tmp = cmd->scan_begin_src;
2181 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
2182 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2185 tmp = cmd->convert_src;
2186 sources = TRIG_TIMER | TRIG_EXT;
2187 if ((boardtype.reg_type == ni_reg_611x)
2188 || (boardtype.reg_type == ni_reg_6143))
2189 sources |= TRIG_NOW;
2190 cmd->convert_src &= sources;
2191 if (!cmd->convert_src || tmp != cmd->convert_src)
2194 tmp = cmd->scan_end_src;
2195 cmd->scan_end_src &= TRIG_COUNT;
2196 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2199 tmp = cmd->stop_src;
2200 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
2201 if (!cmd->stop_src || tmp != cmd->stop_src)
2207 /* step 2: make sure trigger sources are unique and mutually compatible */
2209 /* note that mutual compatiblity is not an issue here */
2210 if (cmd->start_src != TRIG_NOW &&
2211 cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
2213 if (cmd->scan_begin_src != TRIG_TIMER &&
2214 cmd->scan_begin_src != TRIG_EXT &&
2215 cmd->scan_begin_src != TRIG_OTHER)
2217 if (cmd->convert_src != TRIG_TIMER &&
2218 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2220 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
2226 /* step 3: make sure arguments are trivially compatible */
2228 if (cmd->start_src == TRIG_EXT) {
2229 /* external trigger */
2230 unsigned int tmp = CR_CHAN(cmd->start_arg);
2234 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2235 if (cmd->start_arg != tmp) {
2236 cmd->start_arg = tmp;
2240 if (cmd->start_arg != 0) {
2241 /* true for both TRIG_NOW and TRIG_INT */
2246 if (cmd->scan_begin_src == TRIG_TIMER) {
2247 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev,
2251 cmd->scan_begin_arg =
2252 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
2255 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {
2256 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2259 } else if (cmd->scan_begin_src == TRIG_EXT) {
2260 /* external trigger */
2261 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2265 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2266 if (cmd->scan_begin_arg != tmp) {
2267 cmd->scan_begin_arg = tmp;
2270 } else { /* TRIG_OTHER */
2271 if (cmd->scan_begin_arg) {
2272 cmd->scan_begin_arg = 0;
2276 if (cmd->convert_src == TRIG_TIMER) {
2277 if ((boardtype.reg_type == ni_reg_611x)
2278 || (boardtype.reg_type == ni_reg_6143)) {
2279 if (cmd->convert_arg != 0) {
2280 cmd->convert_arg = 0;
2284 if (cmd->convert_arg < boardtype.ai_speed) {
2285 cmd->convert_arg = boardtype.ai_speed;
2288 if (cmd->convert_arg > devpriv->clock_ns * 0xffff) {
2289 cmd->convert_arg = devpriv->clock_ns * 0xffff;
2293 } else if (cmd->convert_src == TRIG_EXT) {
2294 /* external trigger */
2295 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2299 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2300 if (cmd->convert_arg != tmp) {
2301 cmd->convert_arg = tmp;
2304 } else if (cmd->convert_src == TRIG_NOW) {
2305 if (cmd->convert_arg != 0) {
2306 cmd->convert_arg = 0;
2311 if (cmd->scan_end_arg != cmd->chanlist_len) {
2312 cmd->scan_end_arg = cmd->chanlist_len;
2315 if (cmd->stop_src == TRIG_COUNT) {
2316 unsigned int max_count = 0x01000000;
2318 if (boardtype.reg_type == ni_reg_611x)
2319 max_count -= num_adc_stages_611x;
2320 if (cmd->stop_arg > max_count) {
2321 cmd->stop_arg = max_count;
2324 if (cmd->stop_arg < 1) {
2330 if (cmd->stop_arg != 0) {
2339 /* step 4: fix up any arguments */
2341 if (cmd->scan_begin_src == TRIG_TIMER) {
2342 tmp = cmd->scan_begin_arg;
2343 cmd->scan_begin_arg =
2344 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2345 cmd->scan_begin_arg,
2349 if (tmp != cmd->scan_begin_arg)
2352 if (cmd->convert_src == TRIG_TIMER) {
2353 if ((boardtype.reg_type != ni_reg_611x)
2354 && (boardtype.reg_type != ni_reg_6143)) {
2355 tmp = cmd->convert_arg;
2357 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2362 if (tmp != cmd->convert_arg)
2364 if (cmd->scan_begin_src == TRIG_TIMER &&
2365 cmd->scan_begin_arg <
2366 cmd->convert_arg * cmd->scan_end_arg) {
2367 cmd->scan_begin_arg =
2368 cmd->convert_arg * cmd->scan_end_arg;
2380 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2382 const struct comedi_cmd *cmd = &s->async->cmd;
2384 int mode1 = 0; /* mode1 is needed for both stop and convert */
2386 int start_stop_select = 0;
2387 unsigned int stop_count;
2388 int interrupt_a_enable = 0;
2390 MDPRINTK("ni_ai_cmd\n");
2391 if (dev->irq == 0) {
2392 comedi_error(dev, "cannot run command without an irq");
2395 ni_clear_ai_fifo(dev);
2397 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2399 /* start configuration */
2400 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2402 /* disable analog triggering for now, since it
2403 * interferes with the use of pfi0 */
2404 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2405 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2406 Analog_Trigger_Etc_Register);
2408 switch (cmd->start_src) {
2411 devpriv->stc_writew(dev, AI_START2_Select(0) |
2412 AI_START1_Sync | AI_START1_Edge |
2413 AI_START1_Select(0),
2414 AI_Trigger_Select_Register);
2418 int chan = CR_CHAN(cmd->start_arg);
2419 unsigned int bits = AI_START2_Select(0) |
2420 AI_START1_Sync | AI_START1_Select(chan + 1);
2422 if (cmd->start_arg & CR_INVERT)
2423 bits |= AI_START1_Polarity;
2424 if (cmd->start_arg & CR_EDGE)
2425 bits |= AI_START1_Edge;
2426 devpriv->stc_writew(dev, bits,
2427 AI_Trigger_Select_Register);
2432 mode2 &= ~AI_Pre_Trigger;
2433 mode2 &= ~AI_SC_Initial_Load_Source;
2434 mode2 &= ~AI_SC_Reload_Mode;
2435 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2437 if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2438 || (boardtype.reg_type == ni_reg_6143)) {
2439 start_stop_select |= AI_STOP_Polarity;
2440 start_stop_select |= AI_STOP_Select(31); /* logic low */
2441 start_stop_select |= AI_STOP_Sync;
2443 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2445 devpriv->stc_writew(dev, start_stop_select,
2446 AI_START_STOP_Select_Register);
2448 devpriv->ai_cmd2 = 0;
2449 switch (cmd->stop_src) {
2451 stop_count = cmd->stop_arg - 1;
2453 if (boardtype.reg_type == ni_reg_611x) {
2454 /* have to take 3 stage adc pipeline into account */
2455 stop_count += num_adc_stages_611x;
2457 /* stage number of scans */
2458 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2460 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2461 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2462 /* load SC (Scan Count) */
2463 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2465 devpriv->ai_continuous = 0;
2466 if (stop_count == 0) {
2467 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2468 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2469 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2470 if (cmd->chanlist_len > 1)
2471 start_stop_select |=
2472 AI_STOP_Polarity | AI_STOP_Edge;
2476 /* stage number of scans */
2477 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2479 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2480 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2482 /* load SC (Scan Count) */
2483 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2485 devpriv->ai_continuous = 1;
2490 switch (cmd->scan_begin_src) {
2493 stop bits for non 611x boards
2494 AI_SI_Special_Trigger_Delay=0
2496 AI_START_STOP_Select_Register:
2497 AI_START_Polarity=0 (?) rising edge
2498 AI_START_Edge=1 edge triggered
2500 AI_START_Select=0 SI_TC
2501 AI_STOP_Polarity=0 rising edge
2502 AI_STOP_Edge=0 level
2504 AI_STOP_Select=19 external pin (configuration mem)
2506 start_stop_select |= AI_START_Edge | AI_START_Sync;
2507 devpriv->stc_writew(dev, start_stop_select,
2508 AI_START_STOP_Select_Register);
2510 mode2 |= AI_SI_Reload_Mode(0);
2511 /* AI_SI_Initial_Load_Source=A */
2512 mode2 &= ~AI_SI_Initial_Load_Source;
2513 /* mode2 |= AI_SC_Reload_Mode; */
2514 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2517 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2518 TRIG_ROUND_NEAREST);
2519 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2520 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2523 if (cmd->scan_begin_arg & CR_EDGE)
2524 start_stop_select |= AI_START_Edge;
2525 /* AI_START_Polarity==1 is falling edge */
2526 if (cmd->scan_begin_arg & CR_INVERT)
2527 start_stop_select |= AI_START_Polarity;
2528 if (cmd->scan_begin_src != cmd->convert_src ||
2529 (cmd->scan_begin_arg & ~CR_EDGE) !=
2530 (cmd->convert_arg & ~CR_EDGE))
2531 start_stop_select |= AI_START_Sync;
2532 start_stop_select |=
2533 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2534 devpriv->stc_writew(dev, start_stop_select,
2535 AI_START_STOP_Select_Register);
2539 switch (cmd->convert_src) {
2542 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2545 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2546 TRIG_ROUND_NEAREST);
2547 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2548 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2550 /* AI_SI2_Reload_Mode = alternate */
2551 /* AI_SI2_Initial_Load_Source = A */
2552 mode2 &= ~AI_SI2_Initial_Load_Source;
2553 mode2 |= AI_SI2_Reload_Mode;
2554 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2557 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2559 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2560 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2562 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2565 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2566 if ((cmd->convert_arg & CR_INVERT) == 0)
2567 mode1 |= AI_CONVERT_Source_Polarity;
2568 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2570 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2571 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2578 /* interrupt on FIFO, errors, SC_TC */
2579 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2580 AI_SC_TC_Interrupt_Enable;
2583 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2586 if (cmd->flags & TRIG_WAKE_EOS
2587 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2588 /* wake on end-of-scan */
2589 devpriv->aimode = AIMODE_SCAN;
2591 devpriv->aimode = AIMODE_HALF_FULL;
2594 switch (devpriv->aimode) {
2595 case AIMODE_HALF_FULL:
2596 /*generate FIFO interrupts and DMA requests on half-full */
2598 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2599 AI_Mode_3_Register);
2601 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2602 AI_Mode_3_Register);
2606 /*generate FIFO interrupts on non-empty */
2607 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2608 AI_Mode_3_Register);
2612 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2613 AI_Mode_3_Register);
2615 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2616 AI_Mode_3_Register);
2618 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2624 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2626 ni_set_bits(dev, Interrupt_A_Enable_Register,
2627 interrupt_a_enable, 1);
2629 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2630 devpriv->int_a_enable_reg);
2632 /* interrupt on nothing */
2633 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2635 /* XXX start polling if necessary */
2636 MDPRINTK("interrupting on nothing\n");
2639 /* end configuration */
2640 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2642 switch (cmd->scan_begin_src) {
2644 devpriv->stc_writew(dev,
2645 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2646 AI_SC_Arm, AI_Command_1_Register);
2649 /* XXX AI_SI_Arm? */
2650 devpriv->stc_writew(dev,
2651 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2652 AI_SC_Arm, AI_Command_1_Register);
2658 int retval = ni_ai_setup_MITE_dma(dev);
2662 /* mite_dump_regs(devpriv->mite); */
2665 switch (cmd->start_src) {
2667 /* AI_START1_Pulse */
2668 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2669 AI_Command_2_Register);
2670 s->async->inttrig = NULL;
2673 s->async->inttrig = NULL;
2676 s->async->inttrig = &ni_ai_inttrig;
2680 MDPRINTK("exit ni_ai_cmd\n");
2685 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2686 unsigned int trignum)
2691 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2692 AI_Command_2_Register);
2693 s->async->inttrig = NULL;
2698 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2699 struct comedi_subdevice *s,
2700 struct comedi_insn *insn,
2701 unsigned int *data);
2703 static int ni_ai_insn_config(struct comedi_device *dev,
2704 struct comedi_subdevice *s,
2705 struct comedi_insn *insn, unsigned int *data)
2711 case INSN_CONFIG_ANALOG_TRIG:
2712 return ni_ai_config_analog_trig(dev, s, insn, data);
2713 case INSN_CONFIG_ALT_SOURCE:
2714 if (boardtype.reg_type & ni_reg_m_series_mask) {
2715 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2716 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2717 MSeries_AI_Bypass_Mode_Mux_Mask |
2718 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2721 devpriv->ai_calib_source = data[1];
2722 } else if (boardtype.reg_type == ni_reg_6143) {
2723 unsigned int calib_source;
2725 calib_source = data[1] & 0xf;
2727 if (calib_source > 0xF)
2730 devpriv->ai_calib_source = calib_source;
2731 ni_writew(calib_source, Calibration_Channel_6143);
2733 unsigned int calib_source;
2734 unsigned int calib_source_adjust;
2736 calib_source = data[1] & 0xf;
2737 calib_source_adjust = (data[1] >> 4) & 0xff;
2739 if (calib_source >= 8)
2741 devpriv->ai_calib_source = calib_source;
2742 if (boardtype.reg_type == ni_reg_611x) {
2743 ni_writeb(calib_source_adjust,
2744 Cal_Gain_Select_611x);
2755 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2756 struct comedi_subdevice *s,
2757 struct comedi_insn *insn,
2760 unsigned int a, b, modebits;
2764 * data[2] is analog line
2765 * data[3] is set level
2766 * data[4] is reset level */
2767 if (!boardtype.has_analog_trig)
2769 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2770 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2773 if (data[2] >= boardtype.n_adchan) {
2774 data[2] = boardtype.n_adchan - 1;
2777 if (data[3] > 255) { /* a */
2781 if (data[4] > 255) { /* b */
2792 * high mode 00 00 01 10
2793 * low mode 00 00 10 01
2795 * hysteresis low mode 10 00 00 01
2796 * hysteresis high mode 01 00 00 10
2797 * middle mode 10 01 01 10
2802 modebits = data[1] & 0xff;
2803 if (modebits & 0xf0) {
2804 /* two level mode */
2810 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2812 devpriv->atrig_low = a;
2813 devpriv->atrig_high = b;
2815 case 0x81: /* low hysteresis mode */
2816 devpriv->atrig_mode = 6;
2818 case 0x42: /* high hysteresis mode */
2819 devpriv->atrig_mode = 3;
2821 case 0x96: /* middle window mode */
2822 devpriv->atrig_mode = 2;
2829 /* one level mode */
2835 case 0x06: /* high window mode */
2836 devpriv->atrig_high = a;
2837 devpriv->atrig_mode = 0;
2839 case 0x09: /* low window mode */
2840 devpriv->atrig_low = a;
2841 devpriv->atrig_mode = 1;
2853 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2854 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2855 void *data, unsigned int num_bytes,
2856 unsigned int chan_index)
2858 struct comedi_async *async = s->async;
2861 unsigned int offset;
2862 unsigned int length = num_bytes / sizeof(short);
2863 short *array = data;
2865 offset = 1 << (boardtype.aobits - 1);
2866 for (i = 0; i < length; i++) {
2867 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2868 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2871 array[i] = cpu_to_le16(array[i]);
2874 chan_index %= async->cmd.chanlist_len;
2878 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2879 struct comedi_subdevice *s,
2880 unsigned int chanspec[],
2881 unsigned int n_chans, int timed)
2890 for (i = 0; i < boardtype.n_aochan; ++i) {
2891 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2892 ni_writeb(devpriv->ao_conf[i],
2893 M_Offset_AO_Config_Bank(i));
2894 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2897 for (i = 0; i < n_chans; i++) {
2898 const struct comedi_krange *krange;
2899 chan = CR_CHAN(chanspec[i]);
2900 range = CR_RANGE(chanspec[i]);
2901 krange = s->range_table->range + range;
2904 switch (krange->max - krange->min) {
2906 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2907 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2910 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2911 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2914 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2915 ni_writeb(MSeries_Attenuate_x5_Bit,
2916 M_Offset_AO_Reference_Attenuation(chan));
2919 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2920 ni_writeb(MSeries_Attenuate_x5_Bit,
2921 M_Offset_AO_Reference_Attenuation(chan));
2924 printk("%s: bug! unhandled ao reference voltage\n",
2928 switch (krange->max + krange->min) {
2930 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2933 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2936 printk("%s: bug! unhandled ao offset voltage\n",
2941 conf |= MSeries_AO_Update_Timed_Bit;
2942 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2943 devpriv->ao_conf[chan] = conf;
2944 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2949 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2950 struct comedi_subdevice *s,
2951 unsigned int chanspec[],
2952 unsigned int n_chans)
2960 for (i = 0; i < n_chans; i++) {
2961 chan = CR_CHAN(chanspec[i]);
2962 range = CR_RANGE(chanspec[i]);
2963 conf = AO_Channel(chan);
2965 if (boardtype.ao_unipolar) {
2966 if ((range & 1) == 0) {
2968 invert = (1 << (boardtype.aobits - 1));
2976 invert = (1 << (boardtype.aobits - 1));
2979 /* not all boards can deglitch, but this shouldn't hurt */
2980 if (chanspec[i] & CR_DEGLITCH)
2981 conf |= AO_Deglitch;
2983 /* analog reference */
2984 /* AREF_OTHER connects AO ground to AI ground, i think */
2985 conf |= (CR_AREF(chanspec[i]) ==
2986 AREF_OTHER) ? AO_Ground_Ref : 0;
2988 ni_writew(conf, AO_Configuration);
2989 devpriv->ao_conf[chan] = conf;
2994 static int ni_ao_config_chanlist(struct comedi_device *dev,
2995 struct comedi_subdevice *s,
2996 unsigned int chanspec[], unsigned int n_chans,
2999 if (boardtype.reg_type & ni_reg_m_series_mask)
3000 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3003 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3006 static int ni_ao_insn_read(struct comedi_device *dev,
3007 struct comedi_subdevice *s, struct comedi_insn *insn,
3010 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3015 static int ni_ao_insn_write(struct comedi_device *dev,
3016 struct comedi_subdevice *s,
3017 struct comedi_insn *insn, unsigned int *data)
3019 unsigned int chan = CR_CHAN(insn->chanspec);
3020 unsigned int invert;
3022 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3024 devpriv->ao[chan] = data[0];
3026 if (boardtype.reg_type & ni_reg_m_series_mask) {
3027 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3029 ni_writew(data[0] ^ invert,
3030 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3035 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3036 struct comedi_subdevice *s,
3037 struct comedi_insn *insn, unsigned int *data)
3039 unsigned int chan = CR_CHAN(insn->chanspec);
3040 unsigned int invert;
3042 ao_win_out(1 << chan, AO_Immediate_671x);
3043 invert = 1 << (boardtype.aobits - 1);
3045 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3047 devpriv->ao[chan] = data[0];
3048 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3053 static int ni_ao_insn_config(struct comedi_device *dev,
3054 struct comedi_subdevice *s,
3055 struct comedi_insn *insn, unsigned int *data)
3058 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3061 data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short);
3063 data[2] += devpriv->mite->fifo_size;
3080 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3081 unsigned int trignum)
3084 int interrupt_b_bits;
3086 static const int timeout = 1000;
3091 /* Null trig at beginning prevent ao start trigger from executing more than
3092 once per command (and doing things like trying to allocate the ao dma channel
3094 s->async->inttrig = NULL;
3096 ni_set_bits(dev, Interrupt_B_Enable_Register,
3097 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3098 interrupt_b_bits = AO_Error_Interrupt_Enable;
3100 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3101 if (boardtype.reg_type & ni_reg_6xxx_mask)
3102 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3103 ret = ni_ao_setup_MITE_dma(dev);
3106 ret = ni_ao_wait_for_dma_load(dev);
3110 ret = ni_ao_prep_fifo(dev, s);
3114 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3117 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3118 AO_Mode_3_Register);
3119 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3120 /* wait for DACs to be loaded */
3121 for (i = 0; i < timeout; i++) {
3123 if ((devpriv->stc_readw(dev,
3124 Joint_Status_2_Register) &
3125 AO_TMRDACWRs_In_Progress_St) == 0)
3130 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3133 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3134 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3135 Interrupt_B_Ack_Register);
3137 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3139 devpriv->stc_writew(dev,
3140 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3141 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3142 AO_Command_1_Register);
3144 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3145 AO_Command_2_Register);
3150 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3152 const struct comedi_cmd *cmd = &s->async->cmd;
3157 if (dev->irq == 0) {
3158 comedi_error(dev, "cannot run command without an irq");
3162 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3164 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3166 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3167 ao_win_out(CLEAR_WG, AO_Misc_611x);
3170 for (i = 0; i < cmd->chanlist_len; i++) {
3173 chan = CR_CHAN(cmd->chanlist[i]);
3175 ao_win_out(chan, AO_Waveform_Generation_611x);
3177 ao_win_out(bits, AO_Timed_611x);
3180 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3182 if (cmd->stop_src == TRIG_NONE) {
3183 devpriv->ao_mode1 |= AO_Continuous;
3184 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3186 devpriv->ao_mode1 &= ~AO_Continuous;
3187 devpriv->ao_mode1 |= AO_Trigger_Once;
3189 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3190 switch (cmd->start_src) {
3193 devpriv->ao_trigger_select &=
3194 ~(AO_START1_Polarity | AO_START1_Select(-1));
3195 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3196 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3197 AO_Trigger_Select_Register);
3200 devpriv->ao_trigger_select =
3201 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3202 if (cmd->start_arg & CR_INVERT)
3203 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3204 if (cmd->start_arg & CR_EDGE)
3205 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3206 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3207 AO_Trigger_Select_Register);
3213 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3214 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3216 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3217 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3218 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3219 if (cmd->stop_src == TRIG_NONE) {
3220 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3222 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3224 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3225 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3226 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3227 switch (cmd->stop_src) {
3229 if (boardtype.reg_type & ni_reg_m_series_mask) {
3230 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3231 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3232 AO_UC_Load_A_Register);
3233 devpriv->stc_writew(dev, AO_UC_Load,
3234 AO_Command_1_Register);
3236 devpriv->stc_writel(dev, cmd->stop_arg,
3237 AO_UC_Load_A_Register);
3238 devpriv->stc_writew(dev, AO_UC_Load,
3239 AO_Command_1_Register);
3240 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3241 AO_UC_Load_A_Register);
3245 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3246 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3247 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3250 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3251 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3252 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3255 devpriv->ao_mode1 &=
3256 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3257 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3258 switch (cmd->scan_begin_src) {
3260 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3262 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3263 TRIG_ROUND_NEAREST);
3264 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3265 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3266 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3269 devpriv->ao_mode1 |=
3270 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3271 if (cmd->scan_begin_arg & CR_INVERT)
3272 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3273 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3279 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3280 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3281 devpriv->ao_mode2 &=
3282 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3283 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3285 if (cmd->scan_end_arg > 1) {
3286 devpriv->ao_mode1 |= AO_Multiple_Channels;
3287 devpriv->stc_writew(dev,
3288 AO_Number_Of_Channels(cmd->scan_end_arg -
3290 AO_UPDATE_Output_Select
3291 (AO_Update_Output_High_Z),
3292 AO_Output_Control_Register);
3295 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3296 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3298 reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3299 bits |= AO_Number_Of_Channels(0);
3302 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3304 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3306 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3308 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3309 AO_Command_1_Register);
3311 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3312 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3314 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3316 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3318 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3320 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3321 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3323 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3324 AO_TMRDACWR_Pulse_Width;
3325 if (boardtype.ao_fifo_depth)
3326 bits |= AO_FIFO_Enable;
3328 bits |= AO_DMA_PIO_Control;
3330 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3331 verified with bus analyzer. */
3332 if (boardtype.reg_type & ni_reg_m_series_mask)
3333 bits |= AO_Number_Of_DAC_Packages;
3335 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3336 /* enable sending of ao dma requests */
3337 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3339 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3341 if (cmd->stop_src == TRIG_COUNT) {
3342 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3343 Interrupt_B_Ack_Register);
3344 ni_set_bits(dev, Interrupt_B_Enable_Register,
3345 AO_BC_TC_Interrupt_Enable, 1);
3348 s->async->inttrig = &ni_ao_inttrig;
3353 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3354 struct comedi_cmd *cmd)
3359 /* step 1: make sure trigger sources are trivially valid */
3361 if ((cmd->flags & CMDF_WRITE) == 0) {
3362 cmd->flags |= CMDF_WRITE;
3365 tmp = cmd->start_src;
3366 cmd->start_src &= TRIG_INT | TRIG_EXT;
3367 if (!cmd->start_src || tmp != cmd->start_src)
3370 tmp = cmd->scan_begin_src;
3371 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3372 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3375 tmp = cmd->convert_src;
3376 cmd->convert_src &= TRIG_NOW;
3377 if (!cmd->convert_src || tmp != cmd->convert_src)
3380 tmp = cmd->scan_end_src;
3381 cmd->scan_end_src &= TRIG_COUNT;
3382 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3385 tmp = cmd->stop_src;
3386 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
3387 if (!cmd->stop_src || tmp != cmd->stop_src)
3393 /* step 2: make sure trigger sources are unique and mutually compatible */
3395 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
3401 /* step 3: make sure arguments are trivially compatible */
3403 if (cmd->start_src == TRIG_EXT) {
3404 /* external trigger */
3405 unsigned int tmp = CR_CHAN(cmd->start_arg);
3409 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3410 if (cmd->start_arg != tmp) {
3411 cmd->start_arg = tmp;
3415 if (cmd->start_arg != 0) {
3416 /* true for both TRIG_NOW and TRIG_INT */
3421 if (cmd->scan_begin_src == TRIG_TIMER) {
3422 if (cmd->scan_begin_arg < boardtype.ao_speed) {
3423 cmd->scan_begin_arg = boardtype.ao_speed;
3426 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { /* XXX check */
3427 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3431 if (cmd->convert_arg != 0) {
3432 cmd->convert_arg = 0;
3435 if (cmd->scan_end_arg != cmd->chanlist_len) {
3436 cmd->scan_end_arg = cmd->chanlist_len;
3439 if (cmd->stop_src == TRIG_COUNT) { /* XXX check */
3440 if (cmd->stop_arg > 0x00ffffff) {
3441 cmd->stop_arg = 0x00ffffff;
3446 if (cmd->stop_arg != 0) {
3455 /* step 4: fix up any arguments */
3456 if (cmd->scan_begin_src == TRIG_TIMER) {
3457 tmp = cmd->scan_begin_arg;
3458 cmd->scan_begin_arg =
3459 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3460 cmd->scan_begin_arg,
3464 if (tmp != cmd->scan_begin_arg)
3470 /* step 5: fix up chanlist */
3478 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3480 /* devpriv->ao0p=0x0000; */
3481 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3483 /* devpriv->ao1p=AO_Channel(1); */
3484 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3486 ni_release_ao_mite_channel(dev);
3488 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3489 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3490 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3491 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3492 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3493 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3494 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3495 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3496 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3497 devpriv->ao_cmd1 = 0;
3498 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3499 devpriv->ao_cmd2 = 0;
3500 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3501 devpriv->ao_mode1 = 0;
3502 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3503 devpriv->ao_mode2 = 0;
3504 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3505 if (boardtype.reg_type & ni_reg_m_series_mask)
3506 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3508 devpriv->ao_mode3 = 0;
3509 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3510 devpriv->ao_trigger_select = 0;
3511 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3512 AO_Trigger_Select_Register);
3513 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3514 unsigned immediate_bits = 0;
3516 for (i = 0; i < s->n_chan; ++i) {
3517 immediate_bits |= 1 << i;
3519 ao_win_out(immediate_bits, AO_Immediate_671x);
3520 ao_win_out(CLEAR_WG, AO_Misc_611x);
3522 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3529 static int ni_dio_insn_config(struct comedi_device *dev,
3530 struct comedi_subdevice *s,
3531 struct comedi_insn *insn, unsigned int *data)
3534 printk("ni_dio_insn_config() chan=%d io=%d\n",
3535 CR_CHAN(insn->chanspec), data[0]);
3538 case INSN_CONFIG_DIO_OUTPUT:
3539 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3541 case INSN_CONFIG_DIO_INPUT:
3542 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3544 case INSN_CONFIG_DIO_QUERY:
3547 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3555 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3556 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3557 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3562 static int ni_dio_insn_bits(struct comedi_device *dev,
3563 struct comedi_subdevice *s,
3564 struct comedi_insn *insn, unsigned int *data)
3567 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3572 /* Perform check to make sure we're not using the
3573 serial part of the dio */
3574 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3575 && devpriv->serial_interval_ns)
3578 s->state &= ~data[0];
3579 s->state |= (data[0] & data[1]);
3580 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3581 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3582 devpriv->stc_writew(dev, devpriv->dio_output,
3583 DIO_Output_Register);
3585 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3590 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3591 struct comedi_subdevice *s,
3592 struct comedi_insn *insn,
3596 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3597 CR_CHAN(insn->chanspec), data[0]);
3600 case INSN_CONFIG_DIO_OUTPUT:
3601 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3603 case INSN_CONFIG_DIO_INPUT:
3604 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3606 case INSN_CONFIG_DIO_QUERY:
3609 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3617 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3622 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3623 struct comedi_subdevice *s,
3624 struct comedi_insn *insn,
3628 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3634 s->state &= ~data[0];
3635 s->state |= (data[0] & data[1]);
3636 ni_writel(s->state, M_Offset_Static_Digital_Output);
3638 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3643 static int ni_cdio_cmdtest(struct comedi_device *dev,
3644 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3651 /* step 1: make sure trigger sources are trivially valid */
3653 tmp = cmd->start_src;
3655 cmd->start_src &= sources;
3656 if (!cmd->start_src || tmp != cmd->start_src)
3659 tmp = cmd->scan_begin_src;
3660 cmd->scan_begin_src &= TRIG_EXT;
3661 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3664 tmp = cmd->convert_src;
3665 cmd->convert_src &= TRIG_NOW;
3666 if (!cmd->convert_src || tmp != cmd->convert_src)
3669 tmp = cmd->scan_end_src;
3670 cmd->scan_end_src &= TRIG_COUNT;
3671 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3674 tmp = cmd->stop_src;
3675 cmd->stop_src &= TRIG_NONE;
3676 if (!cmd->stop_src || tmp != cmd->stop_src)
3682 /* step 2: make sure trigger sources are unique... */
3684 if (cmd->start_src != TRIG_INT)
3686 if (cmd->scan_begin_src != TRIG_EXT)
3688 if (cmd->convert_src != TRIG_NOW)
3690 if (cmd->stop_src != TRIG_NONE)
3692 /* ... and mutually compatible */
3697 /* step 3: make sure arguments are trivially compatible */
3698 if (cmd->start_src == TRIG_INT) {
3699 if (cmd->start_arg != 0) {
3704 if (cmd->scan_begin_src == TRIG_EXT) {
3705 tmp = cmd->scan_begin_arg;
3706 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0,
3708 if (tmp != cmd->scan_begin_arg) {
3712 if (cmd->convert_src == TRIG_NOW) {
3713 if (cmd->convert_arg) {
3714 cmd->convert_arg = 0;
3719 if (cmd->scan_end_arg != cmd->chanlist_len) {
3720 cmd->scan_end_arg = cmd->chanlist_len;
3724 if (cmd->stop_src == TRIG_NONE) {
3725 if (cmd->stop_arg != 0) {
3734 /* step 4: fix up any arguments */
3739 /* step 5: check chanlist */
3741 for (i = 0; i < cmd->chanlist_len; ++i) {
3742 if (cmd->chanlist[i] != i)
3752 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3754 const struct comedi_cmd *cmd = &s->async->cmd;
3755 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3758 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3759 switch (cmd->scan_begin_src) {
3762 CR_CHAN(cmd->scan_begin_arg) &
3763 CDO_Sample_Source_Select_Mask;
3769 if (cmd->scan_begin_arg & CR_INVERT)
3770 cdo_mode_bits |= CDO_Polarity_Bit;
3771 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3773 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3774 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3775 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3778 "attempted to run digital output command with no lines configured as outputs");
3781 retval = ni_request_cdo_mite_channel(dev);
3785 s->async->inttrig = &ni_cdo_inttrig;
3789 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3790 unsigned int trignum)
3793 unsigned long flags;
3797 const unsigned timeout = 100;
3799 s->async->inttrig = NULL;
3801 /* read alloc the entire buffer */
3802 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3805 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3806 if (devpriv->cdo_mite_chan) {
3807 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3808 mite_dma_arm(devpriv->cdo_mite_chan);
3810 comedi_error(dev, "BUG: no cdo mite channel?");
3813 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3818 * XXX not sure what interrupt C group does
3819 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3820 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3822 for (i = 0; i < timeout; ++i) {
3823 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3828 comedi_error(dev, "dma failed to fill cdo fifo!");
3829 ni_cdio_cancel(dev, s);
3832 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3833 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3834 M_Offset_CDIO_Command);
3838 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3840 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3841 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3842 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3843 M_Offset_CDIO_Command);
3845 * XXX not sure what interrupt C group does ni_writeb(0,
3846 * M_Offset_Interrupt_C_Enable);
3848 ni_writel(0, M_Offset_CDO_Mask_Enable);
3849 ni_release_cdo_mite_channel(dev);
3853 static void handle_cdio_interrupt(struct comedi_device *dev)
3855 unsigned cdio_status;
3856 struct comedi_subdevice *s = dev->subdevices + NI_DIO_SUBDEV;
3858 unsigned long flags;
3861 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3865 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3866 if (devpriv->cdo_mite_chan) {
3867 unsigned cdo_mite_status =
3868 mite_get_status(devpriv->cdo_mite_chan);
3869 if (cdo_mite_status & CHSR_LINKC) {
3871 devpriv->mite->mite_io_addr +
3872 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3874 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3876 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3879 cdio_status = ni_readl(M_Offset_CDIO_Status);
3880 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3881 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3882 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3883 s->async->events |= COMEDI_CB_OVERFLOW;
3885 if (cdio_status & CDO_FIFO_Empty_Bit) {
3886 /* printk("cdio fifo empty\n"); */
3887 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3888 M_Offset_CDIO_Command);
3889 /* s->async->events |= COMEDI_CB_EOA; */
3894 static int ni_serial_insn_config(struct comedi_device *dev,
3895 struct comedi_subdevice *s,
3896 struct comedi_insn *insn, unsigned int *data)
3899 unsigned char byte_out, byte_in = 0;
3905 case INSN_CONFIG_SERIAL_CLOCK:
3908 printk("SPI serial clock Config cd\n", data[1]);
3910 devpriv->serial_hw_mode = 1;
3911 devpriv->dio_control |= DIO_HW_Serial_Enable;
3913 if (data[1] == SERIAL_DISABLED) {
3914 devpriv->serial_hw_mode = 0;
3915 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3916 DIO_Software_Serial_Control);
3917 data[1] = SERIAL_DISABLED;
3918 devpriv->serial_interval_ns = data[1];
3919 } else if (data[1] <= SERIAL_600NS) {
3920 /* Warning: this clock speed is too fast to reliably
3922 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3923 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3924 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3925 data[1] = SERIAL_600NS;
3926 devpriv->serial_interval_ns = data[1];
3927 } else if (data[1] <= SERIAL_1_2US) {
3928 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3929 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3930 DIO_Serial_Out_Divide_By_2;
3931 data[1] = SERIAL_1_2US;
3932 devpriv->serial_interval_ns = data[1];
3933 } else if (data[1] <= SERIAL_10US) {
3934 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3935 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3936 DIO_Serial_Out_Divide_By_2;
3937 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3938 600ns/1.2us. If you turn divide_by_2 off with the
3939 slow clock, you will still get 10us, except then
3940 all your delays are wrong. */
3941 data[1] = SERIAL_10US;
3942 devpriv->serial_interval_ns = data[1];
3944 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3945 DIO_Software_Serial_Control);
3946 devpriv->serial_hw_mode = 0;
3947 data[1] = (data[1] / 1000) * 1000;
3948 devpriv->serial_interval_ns = data[1];
3951 devpriv->stc_writew(dev, devpriv->dio_control,
3952 DIO_Control_Register);
3953 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3954 Clock_and_FOUT_Register);
3959 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3961 if (devpriv->serial_interval_ns == 0) {
3965 byte_out = data[1] & 0xFF;
3967 if (devpriv->serial_hw_mode) {
3968 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3970 } else if (devpriv->serial_interval_ns > 0) {
3971 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3974 printk("ni_serial_insn_config: serial disabled!\n");
3979 data[1] = byte_in & 0xFF;
3989 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3990 struct comedi_subdevice *s,
3991 unsigned char data_out,
3992 unsigned char *data_in)
3994 unsigned int status1;
3995 int err = 0, count = 20;
3998 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
4001 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
4002 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
4003 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
4005 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
4006 if (status1 & DIO_Serial_IO_In_Progress_St) {
4011 devpriv->dio_control |= DIO_HW_Serial_Start;
4012 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4013 devpriv->dio_control &= ~DIO_HW_Serial_Start;
4015 /* Wait until STC says we're done, but don't loop infinitely. */
4017 devpriv->stc_readw(dev,
4018 Joint_Status_1_Register)) &
4019 DIO_Serial_IO_In_Progress_St) {
4020 /* Delay one bit per loop */
4021 udelay((devpriv->serial_interval_ns + 999) / 1000);
4024 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
4030 /* Delay for last bit. This delay is absolutely necessary, because
4031 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
4032 udelay((devpriv->serial_interval_ns + 999) / 1000);
4034 if (data_in != NULL) {
4035 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4037 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4042 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4047 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4048 struct comedi_subdevice *s,
4049 unsigned char data_out,
4050 unsigned char *data_in)
4052 unsigned char mask, input = 0;
4055 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4058 /* Wait for one bit before transfer */
4059 udelay((devpriv->serial_interval_ns + 999) / 1000);
4061 for (mask = 0x80; mask; mask >>= 1) {
4062 /* Output current bit; note that we cannot touch s->state
4063 because it is a per-subdevice field, and serial is
4064 a separate subdevice from DIO. */
4065 devpriv->dio_output &= ~DIO_SDOUT;
4066 if (data_out & mask) {
4067 devpriv->dio_output |= DIO_SDOUT;
4069 devpriv->stc_writew(dev, devpriv->dio_output,
4070 DIO_Output_Register);
4072 /* Assert SDCLK (active low, inverted), wait for half of
4073 the delay, deassert SDCLK, and wait for the other half. */
4074 devpriv->dio_control |= DIO_Software_Serial_Control;
4075 devpriv->stc_writew(dev, devpriv->dio_control,
4076 DIO_Control_Register);
4078 udelay((devpriv->serial_interval_ns + 999) / 2000);
4080 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4081 devpriv->stc_writew(dev, devpriv->dio_control,
4082 DIO_Control_Register);
4084 udelay((devpriv->serial_interval_ns + 999) / 2000);
4086 /* Input current bit */
4087 if (devpriv->stc_readw(dev,
4088 DIO_Parallel_Input_Register) & DIO_SDIN)
4090 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4095 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4103 static void mio_common_detach(struct comedi_device *dev)
4106 if (devpriv->counter_dev) {
4107 ni_gpct_device_destroy(devpriv->counter_dev);
4110 if (dev->subdevices && boardtype.has_8255)
4111 subdev_8255_cleanup(dev, dev->subdevices + NI_8255_DIO_SUBDEV);
4114 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4118 for (i = 0; i < s->n_chan; i++) {
4119 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4120 AO_Configuration_2_67xx);
4122 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4125 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4127 unsigned stc_register;
4129 case NITIO_G0_Autoincrement_Reg:
4130 stc_register = G_Autoincrement_Register(0);
4132 case NITIO_G1_Autoincrement_Reg:
4133 stc_register = G_Autoincrement_Register(1);
4135 case NITIO_G0_Command_Reg:
4136 stc_register = G_Command_Register(0);
4138 case NITIO_G1_Command_Reg:
4139 stc_register = G_Command_Register(1);
4141 case NITIO_G0_HW_Save_Reg:
4142 stc_register = G_HW_Save_Register(0);
4144 case NITIO_G1_HW_Save_Reg:
4145 stc_register = G_HW_Save_Register(1);
4147 case NITIO_G0_SW_Save_Reg:
4148 stc_register = G_Save_Register(0);
4150 case NITIO_G1_SW_Save_Reg:
4151 stc_register = G_Save_Register(1);
4153 case NITIO_G0_Mode_Reg:
4154 stc_register = G_Mode_Register(0);
4156 case NITIO_G1_Mode_Reg:
4157 stc_register = G_Mode_Register(1);
4159 case NITIO_G0_LoadA_Reg:
4160 stc_register = G_Load_A_Register(0);
4162 case NITIO_G1_LoadA_Reg:
4163 stc_register = G_Load_A_Register(1);
4165 case NITIO_G0_LoadB_Reg:
4166 stc_register = G_Load_B_Register(0);
4168 case NITIO_G1_LoadB_Reg:
4169 stc_register = G_Load_B_Register(1);
4171 case NITIO_G0_Input_Select_Reg:
4172 stc_register = G_Input_Select_Register(0);
4174 case NITIO_G1_Input_Select_Reg:
4175 stc_register = G_Input_Select_Register(1);
4177 case NITIO_G01_Status_Reg:
4178 stc_register = G_Status_Register;
4180 case NITIO_G01_Joint_Reset_Reg:
4181 stc_register = Joint_Reset_Register;
4183 case NITIO_G01_Joint_Status1_Reg:
4184 stc_register = Joint_Status_1_Register;
4186 case NITIO_G01_Joint_Status2_Reg:
4187 stc_register = Joint_Status_2_Register;
4189 case NITIO_G0_Interrupt_Acknowledge_Reg:
4190 stc_register = Interrupt_A_Ack_Register;
4192 case NITIO_G1_Interrupt_Acknowledge_Reg:
4193 stc_register = Interrupt_B_Ack_Register;
4195 case NITIO_G0_Status_Reg:
4196 stc_register = AI_Status_1_Register;
4198 case NITIO_G1_Status_Reg:
4199 stc_register = AO_Status_1_Register;
4201 case NITIO_G0_Interrupt_Enable_Reg:
4202 stc_register = Interrupt_A_Enable_Register;
4204 case NITIO_G1_Interrupt_Enable_Reg:
4205 stc_register = Interrupt_B_Enable_Register;
4208 printk("%s: unhandled register 0x%x in switch.\n",
4214 return stc_register;
4217 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4218 enum ni_gpct_register reg)
4220 struct comedi_device *dev = counter->counter_dev->dev;
4221 unsigned stc_register;
4222 /* bits in the join reset register which are relevant to counters */
4223 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4224 static const unsigned gpct_interrupt_a_enable_mask =
4225 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4226 static const unsigned gpct_interrupt_b_enable_mask =
4227 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4230 /* m-series-only registers */
4231 case NITIO_G0_Counting_Mode_Reg:
4232 ni_writew(bits, M_Offset_G0_Counting_Mode);
4234 case NITIO_G1_Counting_Mode_Reg:
4235 ni_writew(bits, M_Offset_G1_Counting_Mode);
4237 case NITIO_G0_Second_Gate_Reg:
4238 ni_writew(bits, M_Offset_G0_Second_Gate);
4240 case NITIO_G1_Second_Gate_Reg:
4241 ni_writew(bits, M_Offset_G1_Second_Gate);
4243 case NITIO_G0_DMA_Config_Reg:
4244 ni_writew(bits, M_Offset_G0_DMA_Config);
4246 case NITIO_G1_DMA_Config_Reg:
4247 ni_writew(bits, M_Offset_G1_DMA_Config);
4249 case NITIO_G0_ABZ_Reg:
4250 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4252 case NITIO_G1_ABZ_Reg:
4253 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4256 /* 32 bit registers */
4257 case NITIO_G0_LoadA_Reg:
4258 case NITIO_G1_LoadA_Reg:
4259 case NITIO_G0_LoadB_Reg:
4260 case NITIO_G1_LoadB_Reg:
4261 stc_register = ni_gpct_to_stc_register(reg);
4262 devpriv->stc_writel(dev, bits, stc_register);
4265 /* 16 bit registers */
4266 case NITIO_G0_Interrupt_Enable_Reg:
4267 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4268 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4269 gpct_interrupt_a_enable_mask, bits);
4271 case NITIO_G1_Interrupt_Enable_Reg:
4272 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4273 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4274 gpct_interrupt_b_enable_mask, bits);
4276 case NITIO_G01_Joint_Reset_Reg:
4277 BUG_ON(bits & ~gpct_joint_reset_mask);
4280 stc_register = ni_gpct_to_stc_register(reg);
4281 devpriv->stc_writew(dev, bits, stc_register);
4285 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4286 enum ni_gpct_register reg)
4288 struct comedi_device *dev = counter->counter_dev->dev;
4289 unsigned stc_register;
4291 /* m-series only registers */
4292 case NITIO_G0_DMA_Status_Reg:
4293 return ni_readw(M_Offset_G0_DMA_Status);
4295 case NITIO_G1_DMA_Status_Reg:
4296 return ni_readw(M_Offset_G1_DMA_Status);
4299 /* 32 bit registers */
4300 case NITIO_G0_HW_Save_Reg:
4301 case NITIO_G1_HW_Save_Reg:
4302 case NITIO_G0_SW_Save_Reg:
4303 case NITIO_G1_SW_Save_Reg:
4304 stc_register = ni_gpct_to_stc_register(reg);
4305 return devpriv->stc_readl(dev, stc_register);
4308 /* 16 bit registers */
4310 stc_register = ni_gpct_to_stc_register(reg);
4311 return devpriv->stc_readw(dev, stc_register);
4317 static int ni_freq_out_insn_read(struct comedi_device *dev,
4318 struct comedi_subdevice *s,
4319 struct comedi_insn *insn, unsigned int *data)
4321 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4325 static int ni_freq_out_insn_write(struct comedi_device *dev,
4326 struct comedi_subdevice *s,
4327 struct comedi_insn *insn, unsigned int *data)
4329 devpriv->clock_and_fout &= ~FOUT_Enable;
4330 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4331 Clock_and_FOUT_Register);
4332 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4333 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4334 devpriv->clock_and_fout |= FOUT_Enable;
4335 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4336 Clock_and_FOUT_Register);
4340 static int ni_set_freq_out_clock(struct comedi_device *dev,
4341 unsigned int clock_source)
4343 switch (clock_source) {
4344 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4345 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4347 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4348 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4353 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4354 Clock_and_FOUT_Register);
4358 static void ni_get_freq_out_clock(struct comedi_device *dev,
4359 unsigned int *clock_source,
4360 unsigned int *clock_period_ns)
4362 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4363 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4364 *clock_period_ns = TIMEBASE_2_NS;
4366 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4367 *clock_period_ns = TIMEBASE_1_NS * 2;
4371 static int ni_freq_out_insn_config(struct comedi_device *dev,
4372 struct comedi_subdevice *s,
4373 struct comedi_insn *insn, unsigned int *data)
4376 case INSN_CONFIG_SET_CLOCK_SRC:
4377 return ni_set_freq_out_clock(dev, data[1]);
4379 case INSN_CONFIG_GET_CLOCK_SRC:
4380 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4388 static int ni_alloc_private(struct comedi_device *dev)
4392 ret = alloc_private(dev, sizeof(struct ni_private));
4396 spin_lock_init(&devpriv->window_lock);
4397 spin_lock_init(&devpriv->soft_reg_copy_lock);
4398 spin_lock_init(&devpriv->mite_channel_lock);
4403 static int ni_E_init(struct comedi_device *dev, struct comedi_devconfig *it)
4405 struct comedi_subdevice *s;
4407 enum ni_gpct_variant counter_variant;
4409 if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4410 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4414 if (alloc_subdevices(dev, NI_NUM_SUBDEVICES) < 0)
4417 /* analog input subdevice */
4419 s = dev->subdevices + NI_AI_SUBDEV;
4420 dev->read_subdev = s;
4421 if (boardtype.n_adchan) {
4422 s->type = COMEDI_SUBD_AI;
4424 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4425 if (boardtype.reg_type != ni_reg_611x)
4426 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4427 if (boardtype.adbits > 16)
4428 s->subdev_flags |= SDF_LSAMPL;
4429 if (boardtype.reg_type & ni_reg_m_series_mask)
4430 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4431 s->n_chan = boardtype.n_adchan;
4432 s->len_chanlist = 512;
4433 s->maxdata = (1 << boardtype.adbits) - 1;
4434 s->range_table = ni_range_lkup[boardtype.gainlkup];
4435 s->insn_read = &ni_ai_insn_read;
4436 s->insn_config = &ni_ai_insn_config;
4437 s->do_cmdtest = &ni_ai_cmdtest;
4438 s->do_cmd = &ni_ai_cmd;
4439 s->cancel = &ni_ai_reset;
4440 s->poll = &ni_ai_poll;
4441 s->munge = &ni_ai_munge;
4443 s->async_dma_dir = DMA_FROM_DEVICE;
4446 s->type = COMEDI_SUBD_UNUSED;
4449 /* analog output subdevice */
4451 s = dev->subdevices + NI_AO_SUBDEV;
4452 if (boardtype.n_aochan) {
4453 s->type = COMEDI_SUBD_AO;
4454 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4455 if (boardtype.reg_type & ni_reg_m_series_mask)
4456 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4457 s->n_chan = boardtype.n_aochan;
4458 s->maxdata = (1 << boardtype.aobits) - 1;
4459 s->range_table = boardtype.ao_range_table;
4460 s->insn_read = &ni_ao_insn_read;
4461 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4462 s->insn_write = &ni_ao_insn_write_671x;
4464 s->insn_write = &ni_ao_insn_write;
4466 s->insn_config = &ni_ao_insn_config;
4468 if (boardtype.n_aochan) {
4469 s->async_dma_dir = DMA_TO_DEVICE;
4471 if (boardtype.ao_fifo_depth) {
4473 dev->write_subdev = s;
4474 s->subdev_flags |= SDF_CMD_WRITE;
4475 s->do_cmd = &ni_ao_cmd;
4476 s->do_cmdtest = &ni_ao_cmdtest;
4477 s->len_chanlist = boardtype.n_aochan;
4478 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4479 s->munge = ni_ao_munge;
4481 s->cancel = &ni_ao_reset;
4483 s->type = COMEDI_SUBD_UNUSED;
4485 if ((boardtype.reg_type & ni_reg_67xx_mask))
4486 init_ao_67xx(dev, s);
4488 /* digital i/o subdevice */
4490 s = dev->subdevices + NI_DIO_SUBDEV;
4491 s->type = COMEDI_SUBD_DIO;
4492 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4494 s->io_bits = 0; /* all bits input */
4495 s->range_table = &range_digital;
4496 s->n_chan = boardtype.num_p0_dio_channels;
4497 if (boardtype.reg_type & ni_reg_m_series_mask) {
4499 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4500 s->insn_bits = &ni_m_series_dio_insn_bits;
4501 s->insn_config = &ni_m_series_dio_insn_config;
4502 s->do_cmd = &ni_cdio_cmd;
4503 s->do_cmdtest = &ni_cdio_cmdtest;
4504 s->cancel = &ni_cdio_cancel;
4505 s->async_dma_dir = DMA_BIDIRECTIONAL;
4506 s->len_chanlist = s->n_chan;
4508 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4509 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4511 s->insn_bits = &ni_dio_insn_bits;
4512 s->insn_config = &ni_dio_insn_config;
4513 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4514 ni_writew(devpriv->dio_control, DIO_Control_Register);
4518 s = dev->subdevices + NI_8255_DIO_SUBDEV;
4519 if (boardtype.has_8255) {
4520 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4522 s->type = COMEDI_SUBD_UNUSED;
4525 /* formerly general purpose counter/timer device, but no longer used */
4526 s = dev->subdevices + NI_UNUSED_SUBDEV;
4527 s->type = COMEDI_SUBD_UNUSED;
4529 /* calibration subdevice -- ai and ao */
4530 s = dev->subdevices + NI_CALIBRATION_SUBDEV;
4531 s->type = COMEDI_SUBD_CALIB;
4532 if (boardtype.reg_type & ni_reg_m_series_mask) {
4533 /* internal PWM analog output used for AI nonlinearity calibration */
4534 s->subdev_flags = SDF_INTERNAL;
4535 s->insn_config = &ni_m_series_pwm_config;
4538 ni_writel(0x0, M_Offset_Cal_PWM);
4539 } else if (boardtype.reg_type == ni_reg_6143) {
4540 /* internal PWM analog output used for AI nonlinearity calibration */
4541 s->subdev_flags = SDF_INTERNAL;
4542 s->insn_config = &ni_6143_pwm_config;
4546 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4547 s->insn_read = &ni_calib_insn_read;
4548 s->insn_write = &ni_calib_insn_write;
4549 caldac_setup(dev, s);
4553 s = dev->subdevices + NI_EEPROM_SUBDEV;
4554 s->type = COMEDI_SUBD_MEMORY;
4555 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4557 if (boardtype.reg_type & ni_reg_m_series_mask) {
4558 s->n_chan = M_SERIES_EEPROM_SIZE;
4559 s->insn_read = &ni_m_series_eeprom_insn_read;
4562 s->insn_read = &ni_eeprom_insn_read;
4566 s = dev->subdevices + NI_PFI_DIO_SUBDEV;
4567 s->type = COMEDI_SUBD_DIO;
4568 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4569 if (boardtype.reg_type & ni_reg_m_series_mask) {
4572 ni_writew(s->state, M_Offset_PFI_DO);
4573 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4574 ni_writew(devpriv->pfi_output_select_reg[i],
4575 M_Offset_PFI_Output_Select(i + 1));
4581 if (boardtype.reg_type & ni_reg_m_series_mask) {
4582 s->insn_bits = &ni_pfi_insn_bits;
4584 s->insn_config = &ni_pfi_insn_config;
4585 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4587 /* cs5529 calibration adc */
4588 s = dev->subdevices + NI_CS5529_CALIBRATION_SUBDEV;
4589 if (boardtype.reg_type & ni_reg_67xx_mask) {
4590 s->type = COMEDI_SUBD_AI;
4591 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4592 /* one channel for each analog output channel */
4593 s->n_chan = boardtype.n_aochan;
4594 s->maxdata = (1 << 16) - 1;
4595 s->range_table = &range_unknown; /* XXX */
4596 s->insn_read = cs5529_ai_insn_read;
4597 s->insn_config = NULL;
4600 s->type = COMEDI_SUBD_UNUSED;
4604 s = dev->subdevices + NI_SERIAL_SUBDEV;
4605 s->type = COMEDI_SUBD_SERIAL;
4606 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4609 s->insn_config = ni_serial_insn_config;
4610 devpriv->serial_interval_ns = 0;
4611 devpriv->serial_hw_mode = 0;
4614 s = dev->subdevices + NI_RTSI_SUBDEV;
4615 s->type = COMEDI_SUBD_DIO;
4616 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4619 s->insn_bits = ni_rtsi_insn_bits;
4620 s->insn_config = ni_rtsi_insn_config;
4623 if (boardtype.reg_type & ni_reg_m_series_mask) {
4624 counter_variant = ni_gpct_variant_m_series;
4626 counter_variant = ni_gpct_variant_e_series;
4628 devpriv->counter_dev = ni_gpct_device_construct(dev,
4629 &ni_gpct_write_register,
4630 &ni_gpct_read_register,
4633 /* General purpose counters */
4634 for (j = 0; j < NUM_GPCT; ++j) {
4635 s = dev->subdevices + NI_GPCT_SUBDEV(j);
4636 s->type = COMEDI_SUBD_COUNTER;
4638 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4639 /* | SDF_CMD_WRITE */ ;
4641 if (boardtype.reg_type & ni_reg_m_series_mask)
4642 s->maxdata = 0xffffffff;
4644 s->maxdata = 0xffffff;
4645 s->insn_read = &ni_gpct_insn_read;
4646 s->insn_write = &ni_gpct_insn_write;
4647 s->insn_config = &ni_gpct_insn_config;
4648 s->do_cmd = &ni_gpct_cmd;
4649 s->len_chanlist = 1;
4650 s->do_cmdtest = &ni_gpct_cmdtest;
4651 s->cancel = &ni_gpct_cancel;
4652 s->async_dma_dir = DMA_BIDIRECTIONAL;
4653 s->private = &devpriv->counter_dev->counters[j];
4655 devpriv->counter_dev->counters[j].chip_index = 0;
4656 devpriv->counter_dev->counters[j].counter_index = j;
4657 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4660 /* Frequency output */
4661 s = dev->subdevices + NI_FREQ_OUT_SUBDEV;
4662 s->type = COMEDI_SUBD_COUNTER;
4663 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4666 s->insn_read = &ni_freq_out_insn_read;
4667 s->insn_write = &ni_freq_out_insn_write;
4668 s->insn_config = &ni_freq_out_insn_config;
4670 /* ai configuration */
4671 ni_ai_reset(dev, dev->subdevices + NI_AI_SUBDEV);
4672 if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4673 /* BEAM is this needed for PCI-6143 ?? */
4674 devpriv->clock_and_fout =
4675 Slow_Internal_Time_Divide_By_2 |
4676 Slow_Internal_Timebase |
4677 Clock_To_Board_Divide_By_2 |
4679 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4681 devpriv->clock_and_fout =
4682 Slow_Internal_Time_Divide_By_2 |
4683 Slow_Internal_Timebase |
4684 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4686 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4687 Clock_and_FOUT_Register);
4689 /* analog output configuration */
4690 ni_ao_reset(dev, dev->subdevices + NI_AO_SUBDEV);
4693 devpriv->stc_writew(dev,
4694 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4695 0) | (Interrupt_Output_On_3_Pins & 0) |
4696 Interrupt_A_Enable | Interrupt_B_Enable |
4697 Interrupt_A_Output_Select(interrupt_pin
4699 Interrupt_B_Output_Select(interrupt_pin
4701 Interrupt_Control_Register);
4705 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4706 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4708 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4709 ni_writeb(0, Magic_611x);
4710 } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4712 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4713 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4715 M_Offset_AO_Reference_Attenuation(channel));
4717 ni_writeb(0x0, M_Offset_AO_Calibration);
4724 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4726 struct comedi_device *dev = (struct comedi_device *)arg;
4729 ni_writeb(data, Port_A + 2 * port);
4732 return ni_readb(Port_A + 2 * port);
4737 presents the EEPROM as a subdevice
4740 static int ni_eeprom_insn_read(struct comedi_device *dev,
4741 struct comedi_subdevice *s,
4742 struct comedi_insn *insn, unsigned int *data)
4744 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4750 reads bytes out of eeprom
4753 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4758 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4759 ni_writeb(0x04, Serial_Command);
4760 for (bit = 0x8000; bit; bit >>= 1) {
4761 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4763 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4767 for (bit = 0x80; bit; bit >>= 1) {
4768 ni_writeb(0x04, Serial_Command);
4769 ni_writeb(0x05, Serial_Command);
4770 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4772 ni_writeb(0x00, Serial_Command);
4777 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4778 struct comedi_subdevice *s,
4779 struct comedi_insn *insn,
4782 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4787 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4789 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4790 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4794 static int ni_m_series_pwm_config(struct comedi_device *dev,
4795 struct comedi_subdevice *s,
4796 struct comedi_insn *insn, unsigned int *data)
4798 unsigned up_count, down_count;
4800 case INSN_CONFIG_PWM_OUTPUT:
4802 case TRIG_ROUND_NEAREST:
4805 devpriv->clock_ns / 2) / devpriv->clock_ns;
4807 case TRIG_ROUND_DOWN:
4808 up_count = data[2] / devpriv->clock_ns;
4812 (data[2] + devpriv->clock_ns -
4813 1) / devpriv->clock_ns;
4820 case TRIG_ROUND_NEAREST:
4823 devpriv->clock_ns / 2) / devpriv->clock_ns;
4825 case TRIG_ROUND_DOWN:
4826 down_count = data[4] / devpriv->clock_ns;
4830 (data[4] + devpriv->clock_ns -
4831 1) / devpriv->clock_ns;
4837 if (up_count * devpriv->clock_ns != data[2] ||
4838 down_count * devpriv->clock_ns != data[4]) {
4839 data[2] = up_count * devpriv->clock_ns;
4840 data[4] = down_count * devpriv->clock_ns;
4843 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4844 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4846 devpriv->pwm_up_count = up_count;
4847 devpriv->pwm_down_count = down_count;
4850 case INSN_CONFIG_GET_PWM_OUTPUT:
4851 return ni_get_pwm_config(dev, data);
4860 static int ni_6143_pwm_config(struct comedi_device *dev,
4861 struct comedi_subdevice *s,
4862 struct comedi_insn *insn, unsigned int *data)
4864 unsigned up_count, down_count;
4866 case INSN_CONFIG_PWM_OUTPUT:
4868 case TRIG_ROUND_NEAREST:
4871 devpriv->clock_ns / 2) / devpriv->clock_ns;
4873 case TRIG_ROUND_DOWN:
4874 up_count = data[2] / devpriv->clock_ns;
4878 (data[2] + devpriv->clock_ns -
4879 1) / devpriv->clock_ns;
4886 case TRIG_ROUND_NEAREST:
4889 devpriv->clock_ns / 2) / devpriv->clock_ns;
4891 case TRIG_ROUND_DOWN:
4892 down_count = data[4] / devpriv->clock_ns;
4896 (data[4] + devpriv->clock_ns -
4897 1) / devpriv->clock_ns;
4903 if (up_count * devpriv->clock_ns != data[2] ||
4904 down_count * devpriv->clock_ns != data[4]) {
4905 data[2] = up_count * devpriv->clock_ns;
4906 data[4] = down_count * devpriv->clock_ns;
4909 ni_writel(up_count, Calibration_HighTime_6143);
4910 devpriv->pwm_up_count = up_count;
4911 ni_writel(down_count, Calibration_LowTime_6143);
4912 devpriv->pwm_down_count = down_count;
4915 case INSN_CONFIG_GET_PWM_OUTPUT:
4916 return ni_get_pwm_config(dev, data);
4924 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4926 calibration subdevice
4928 static int ni_calib_insn_write(struct comedi_device *dev,
4929 struct comedi_subdevice *s,
4930 struct comedi_insn *insn, unsigned int *data)
4932 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4937 static int ni_calib_insn_read(struct comedi_device *dev,
4938 struct comedi_subdevice *s,
4939 struct comedi_insn *insn, unsigned int *data)
4941 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4946 static int pack_mb88341(int addr, int val, int *bitstring);
4947 static int pack_dac8800(int addr, int val, int *bitstring);
4948 static int pack_dac8043(int addr, int val, int *bitstring);
4949 static int pack_ad8522(int addr, int val, int *bitstring);
4950 static int pack_ad8804(int addr, int val, int *bitstring);
4951 static int pack_ad8842(int addr, int val, int *bitstring);
4953 struct caldac_struct {
4956 int (*packbits) (int, int, int *);
4959 static struct caldac_struct caldacs[] = {
4960 [mb88341] = {12, 8, pack_mb88341},
4961 [dac8800] = {8, 8, pack_dac8800},
4962 [dac8043] = {1, 12, pack_dac8043},
4963 [ad8522] = {2, 12, pack_ad8522},
4964 [ad8804] = {12, 8, pack_ad8804},
4965 [ad8842] = {8, 8, pack_ad8842},
4966 [ad8804_debug] = {16, 8, pack_ad8804},
4969 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4979 type = boardtype.caldac[0];
4980 if (type == caldac_none)
4982 n_bits = caldacs[type].n_bits;
4983 for (i = 0; i < 3; i++) {
4984 type = boardtype.caldac[i];
4985 if (type == caldac_none)
4987 if (caldacs[type].n_bits != n_bits)
4989 n_chans += caldacs[type].n_chans;
4992 s->n_chan = n_chans;
4995 unsigned int *maxdata_list;
4997 if (n_chans > MAX_N_CALDACS) {
4998 printk("BUG! MAX_N_CALDACS too small\n");
5000 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5002 for (i = 0; i < n_dacs; i++) {
5003 type = boardtype.caldac[i];
5004 for (j = 0; j < caldacs[type].n_chans; j++) {
5005 maxdata_list[chan] =
5006 (1 << caldacs[type].n_bits) - 1;
5011 for (chan = 0; chan < s->n_chan; chan++)
5012 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5014 type = boardtype.caldac[0];
5015 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5017 for (chan = 0; chan < s->n_chan; chan++)
5018 ni_write_caldac(dev, i, s->maxdata / 2);
5022 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5024 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5028 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5029 if (devpriv->caldacs[addr] == val)
5031 devpriv->caldacs[addr] = val;
5033 for (i = 0; i < 3; i++) {
5034 type = boardtype.caldac[i];
5035 if (type == caldac_none)
5037 if (addr < caldacs[type].n_chans) {
5038 bits = caldacs[type].packbits(addr, val, &bitstring);
5039 loadbit = SerDacLd(i);
5040 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5043 addr -= caldacs[type].n_chans;
5046 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5047 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5049 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5052 ni_writeb(loadbit, Serial_Command);
5054 ni_writeb(0, Serial_Command);
5057 static int pack_mb88341(int addr, int val, int *bitstring)
5061 Note that address bits are reversed. Thanks to
5062 Ingo Keen for noticing this.
5064 Note also that the 88341 expects address values from
5065 1-12, whereas we use channel numbers 0-11. The NI
5066 docs use 1-12, also, so be careful here.
5069 *bitstring = ((addr & 0x1) << 11) |
5070 ((addr & 0x2) << 9) |
5071 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5075 static int pack_dac8800(int addr, int val, int *bitstring)
5077 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5081 static int pack_dac8043(int addr, int val, int *bitstring)
5083 *bitstring = val & 0xfff;
5087 static int pack_ad8522(int addr, int val, int *bitstring)
5089 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5093 static int pack_ad8804(int addr, int val, int *bitstring)
5095 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5099 static int pack_ad8842(int addr, int val, int *bitstring)
5101 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5107 * Read the GPCTs current value.
5109 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5111 unsigned int hi1, hi2, lo;
5113 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5114 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5115 G_Command_Register(chan));
5117 devpriv->gpct_command[chan] |= G_Save_Trace;
5118 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5119 G_Command_Register(chan));
5121 /* This procedure is used because the two registers cannot
5122 * be read atomically. */
5124 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5125 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5126 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5127 } while (hi1 != hi2);
5129 return (hi1 << 16) | lo;
5132 static void GPCT_Reset(struct comedi_device *dev, int chan)
5134 int temp_ack_reg = 0;
5136 /* printk("GPCT_Reset..."); */
5137 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5141 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5142 ni_set_bits(dev, Interrupt_A_Enable_Register,
5143 G0_TC_Interrupt_Enable, 0);
5144 ni_set_bits(dev, Interrupt_A_Enable_Register,
5145 G0_Gate_Interrupt_Enable, 0);
5146 temp_ack_reg |= G0_Gate_Error_Confirm;
5147 temp_ack_reg |= G0_TC_Error_Confirm;
5148 temp_ack_reg |= G0_TC_Interrupt_Ack;
5149 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5150 devpriv->stc_writew(dev, temp_ack_reg,
5151 Interrupt_A_Ack_Register);
5153 /* problem...this interferes with the other ctr... */
5154 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5155 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5156 Analog_Trigger_Etc_Register);
5159 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5160 ni_set_bits(dev, Interrupt_B_Enable_Register,
5161 G1_TC_Interrupt_Enable, 0);
5162 ni_set_bits(dev, Interrupt_B_Enable_Register,
5163 G0_Gate_Interrupt_Enable, 0);
5164 temp_ack_reg |= G1_Gate_Error_Confirm;
5165 temp_ack_reg |= G1_TC_Error_Confirm;
5166 temp_ack_reg |= G1_TC_Interrupt_Ack;
5167 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5168 devpriv->stc_writew(dev, temp_ack_reg,
5169 Interrupt_B_Ack_Register);
5171 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5172 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5173 Analog_Trigger_Etc_Register);
5177 devpriv->gpct_mode[chan] = 0;
5178 devpriv->gpct_input_select[chan] = 0;
5179 devpriv->gpct_command[chan] = 0;
5181 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5183 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5184 G_Mode_Register(chan));
5185 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5186 G_Input_Select_Register(chan));
5187 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5189 /* printk("exit GPCT_Reset\n"); */
5194 static int ni_gpct_insn_config(struct comedi_device *dev,
5195 struct comedi_subdevice *s,
5196 struct comedi_insn *insn, unsigned int *data)
5198 struct ni_gpct *counter = s->private;
5199 return ni_tio_insn_config(counter, insn, data);
5202 static int ni_gpct_insn_read(struct comedi_device *dev,
5203 struct comedi_subdevice *s,
5204 struct comedi_insn *insn, unsigned int *data)
5206 struct ni_gpct *counter = s->private;
5207 return ni_tio_rinsn(counter, insn, data);
5210 static int ni_gpct_insn_write(struct comedi_device *dev,
5211 struct comedi_subdevice *s,
5212 struct comedi_insn *insn, unsigned int *data)
5214 struct ni_gpct *counter = s->private;
5215 return ni_tio_winsn(counter, insn, data);
5218 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5222 struct ni_gpct *counter = s->private;
5223 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5225 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5229 "no dma channel available for use by counter");
5232 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5233 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5234 retval = ni_tio_cmd(counter, s->async);
5241 static int ni_gpct_cmdtest(struct comedi_device *dev,
5242 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5245 struct ni_gpct *counter = s->private;
5247 return ni_tio_cmdtest(counter, cmd);
5253 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5256 struct ni_gpct *counter = s->private;
5259 retval = ni_tio_cancel(counter);
5260 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5261 ni_release_gpct_mite_channel(dev, counter->counter_index);
5270 * Programmable Function Inputs
5274 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5277 unsigned pfi_reg_index;
5278 unsigned array_offset;
5279 if ((source & 0x1f) != source)
5281 pfi_reg_index = 1 + chan / 3;
5282 array_offset = pfi_reg_index - 1;
5283 devpriv->pfi_output_select_reg[array_offset] &=
5284 ~MSeries_PFI_Output_Select_Mask(chan);
5285 devpriv->pfi_output_select_reg[array_offset] |=
5286 MSeries_PFI_Output_Select_Bits(chan, source);
5287 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5288 M_Offset_PFI_Output_Select(pfi_reg_index));
5292 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5295 /* pre-m-series boards have fixed signals on pfi pins */
5296 if (source != ni_old_get_pfi_routing(dev, chan))
5301 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5304 if (boardtype.reg_type & ni_reg_m_series_mask)
5305 return ni_m_series_set_pfi_routing(dev, chan, source);
5307 return ni_old_set_pfi_routing(dev, chan, source);
5310 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5313 const unsigned array_offset = chan / 3;
5314 return MSeries_PFI_Output_Select_Source(chan,
5316 pfi_output_select_reg
5320 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5322 /* pre-m-series boards have fixed signals on pfi pins */
5325 return NI_PFI_OUTPUT_AI_START1;
5328 return NI_PFI_OUTPUT_AI_START2;
5331 return NI_PFI_OUTPUT_AI_CONVERT;
5334 return NI_PFI_OUTPUT_G_SRC1;
5337 return NI_PFI_OUTPUT_G_GATE1;
5340 return NI_PFI_OUTPUT_AO_UPDATE_N;
5343 return NI_PFI_OUTPUT_AO_START1;
5346 return NI_PFI_OUTPUT_AI_START_PULSE;
5349 return NI_PFI_OUTPUT_G_SRC0;
5352 return NI_PFI_OUTPUT_G_GATE0;
5355 printk("%s: bug, unhandled case in switch.\n", __func__);
5361 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5363 if (boardtype.reg_type & ni_reg_m_series_mask)
5364 return ni_m_series_get_pfi_routing(dev, chan);
5366 return ni_old_get_pfi_routing(dev, chan);
5369 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5370 enum ni_pfi_filter_select filter)
5373 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5376 bits = ni_readl(M_Offset_PFI_Filter);
5377 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5378 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5379 ni_writel(bits, M_Offset_PFI_Filter);
5383 static int ni_pfi_insn_bits(struct comedi_device *dev,
5384 struct comedi_subdevice *s,
5385 struct comedi_insn *insn, unsigned int *data)
5387 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5391 s->state &= ~data[0];
5392 s->state |= (data[0] & data[1]);
5393 ni_writew(s->state, M_Offset_PFI_DO);
5395 data[1] = ni_readw(M_Offset_PFI_DI);
5399 static int ni_pfi_insn_config(struct comedi_device *dev,
5400 struct comedi_subdevice *s,
5401 struct comedi_insn *insn, unsigned int *data)
5408 chan = CR_CHAN(insn->chanspec);
5412 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5415 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5417 case INSN_CONFIG_DIO_QUERY:
5419 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5420 COMEDI_OUTPUT : COMEDI_INPUT;
5423 case INSN_CONFIG_SET_ROUTING:
5424 return ni_set_pfi_routing(dev, chan, data[1]);
5426 case INSN_CONFIG_GET_ROUTING:
5427 data[1] = ni_get_pfi_routing(dev, chan);
5429 case INSN_CONFIG_FILTER:
5430 return ni_config_filter(dev, chan, data[1]);
5440 * NI RTSI Bus Functions
5443 static void ni_rtsi_init(struct comedi_device *dev)
5445 /* Initialises the RTSI bus signal switch to a default state */
5447 /* Set clock mode to internal */
5448 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5449 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5450 printk("ni_set_master_clock failed, bug?");
5452 /* default internal lines routing to RTSI bus lines */
5453 devpriv->rtsi_trig_a_output_reg =
5454 RTSI_Trig_Output_Bits(0,
5455 NI_RTSI_OUTPUT_ADR_START1) |
5456 RTSI_Trig_Output_Bits(1,
5457 NI_RTSI_OUTPUT_ADR_START2) |
5458 RTSI_Trig_Output_Bits(2,
5459 NI_RTSI_OUTPUT_SCLKG) |
5460 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5461 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5462 RTSI_Trig_A_Output_Register);
5463 devpriv->rtsi_trig_b_output_reg =
5464 RTSI_Trig_Output_Bits(4,
5465 NI_RTSI_OUTPUT_DA_START1) |
5466 RTSI_Trig_Output_Bits(5,
5467 NI_RTSI_OUTPUT_G_SRC0) |
5468 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5469 if (boardtype.reg_type & ni_reg_m_series_mask)
5470 devpriv->rtsi_trig_b_output_reg |=
5471 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5472 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5473 RTSI_Trig_B_Output_Register);
5476 * Sets the source and direction of the 4 on board lines
5477 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5481 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5482 struct comedi_subdevice *s,
5483 struct comedi_insn *insn, unsigned int *data)
5493 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5494 * given an arbitrary frequency input clock */
5495 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5496 unsigned *freq_divider,
5497 unsigned *freq_multiplier,
5498 unsigned *actual_period_ns)
5501 unsigned best_div = 1;
5502 static const unsigned max_div = 0x10;
5504 unsigned best_mult = 1;
5505 static const unsigned max_mult = 0x100;
5506 static const unsigned pico_per_nano = 1000;
5508 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5509 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5510 * 20 MHz for most timing clocks */
5511 static const unsigned target_picosec = 12500;
5512 static const unsigned fudge_factor_80_to_20Mhz = 4;
5513 int best_period_picosec = 0;
5514 for (div = 1; div <= max_div; ++div) {
5515 for (mult = 1; mult <= max_mult; ++mult) {
5516 unsigned new_period_ps =
5517 (reference_picosec * div) / mult;
5518 if (abs(new_period_ps - target_picosec) <
5519 abs(best_period_picosec - target_picosec)) {
5520 best_period_picosec = new_period_ps;
5526 if (best_period_picosec == 0) {
5527 printk("%s: bug, failed to find pll parameters\n", __func__);
5530 *freq_divider = best_div;
5531 *freq_multiplier = best_mult;
5533 (best_period_picosec * fudge_factor_80_to_20Mhz +
5534 (pico_per_nano / 2)) / pico_per_nano;
5538 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5540 if (boardtype.reg_type & ni_reg_m_series_mask)
5546 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5547 unsigned source, unsigned period_ns)
5549 static const unsigned min_period_ns = 50;
5550 static const unsigned max_period_ns = 1000;
5551 static const unsigned timeout = 1000;
5552 unsigned pll_control_bits;
5553 unsigned freq_divider;
5554 unsigned freq_multiplier;
5557 if (source == NI_MIO_PLL_PXI10_CLOCK)
5559 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5560 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5562 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5563 "for the phased-lock loop.\n", __func__,
5564 min_period_ns, max_period_ns);
5567 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5568 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5569 RTSI_Trig_Direction_Register);
5571 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5572 devpriv->clock_and_fout2 |=
5573 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5574 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5576 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5577 devpriv->clock_and_fout2 |=
5578 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5579 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5581 &devpriv->clock_ns);
5585 case NI_MIO_PLL_PXI10_CLOCK:
5586 /* pxi clock is 10MHz */
5587 devpriv->clock_and_fout2 |=
5588 MSeries_PLL_In_Source_Select_PXI_Clock10;
5589 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5591 &devpriv->clock_ns);
5597 unsigned rtsi_channel;
5598 static const unsigned max_rtsi_channel = 7;
5599 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5602 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5603 devpriv->clock_and_fout2 |=
5604 MSeries_PLL_In_Source_Select_RTSI_Bits
5609 if (rtsi_channel > max_rtsi_channel)
5611 retval = ni_mseries_get_pll_parameters(period_ns,
5621 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5623 MSeries_PLL_Divisor_Bits(freq_divider) |
5624 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5626 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5627 * freq_divider, freq_multiplier, pll_control_bits); */
5628 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5629 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5630 devpriv->clock_source = source;
5631 /* it seems to typically take a few hundred microseconds for PLL to lock */
5632 for (i = 0; i < timeout; ++i) {
5633 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5640 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5641 __func__, source, period_ns);
5647 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5650 if (source == NI_MIO_INTERNAL_CLOCK) {
5651 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5652 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5653 RTSI_Trig_Direction_Register);
5654 devpriv->clock_ns = TIMEBASE_1_NS;
5655 if (boardtype.reg_type & ni_reg_m_series_mask) {
5656 devpriv->clock_and_fout2 &=
5657 ~(MSeries_Timebase1_Select_Bit |
5658 MSeries_Timebase3_Select_Bit);
5659 ni_writew(devpriv->clock_and_fout2,
5660 M_Offset_Clock_and_Fout2);
5661 ni_writew(0, M_Offset_PLL_Control);
5663 devpriv->clock_source = source;
5665 if (boardtype.reg_type & ni_reg_m_series_mask) {
5666 return ni_mseries_set_pll_master_clock(dev, source,
5669 if (source == NI_MIO_RTSI_CLOCK) {
5670 devpriv->rtsi_trig_direction_reg |=
5672 devpriv->stc_writew(dev,
5674 rtsi_trig_direction_reg,
5675 RTSI_Trig_Direction_Register);
5676 if (period_ns == 0) {
5678 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5682 devpriv->clock_ns = period_ns;
5684 devpriv->clock_source = source;
5692 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5695 if (chan >= num_configurable_rtsi_channels(dev)) {
5696 if (chan == old_RTSI_clock_channel) {
5697 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5701 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5702 __func__, chan, old_RTSI_clock_channel);
5709 case NI_RTSI_OUTPUT_ADR_START1:
5710 case NI_RTSI_OUTPUT_ADR_START2:
5711 case NI_RTSI_OUTPUT_SCLKG:
5712 case NI_RTSI_OUTPUT_DACUPDN:
5713 case NI_RTSI_OUTPUT_DA_START1:
5714 case NI_RTSI_OUTPUT_G_SRC0:
5715 case NI_RTSI_OUTPUT_G_GATE0:
5716 case NI_RTSI_OUTPUT_RGOUT0:
5717 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5720 case NI_RTSI_OUTPUT_RTSI_OSC:
5721 if (boardtype.reg_type & ni_reg_m_series_mask)
5732 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5735 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5738 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5739 devpriv->rtsi_trig_a_output_reg |=
5740 RTSI_Trig_Output_Bits(chan, source);
5741 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5742 RTSI_Trig_A_Output_Register);
5743 } else if (chan < 8) {
5744 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5745 devpriv->rtsi_trig_b_output_reg |=
5746 RTSI_Trig_Output_Bits(chan, source);
5747 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5748 RTSI_Trig_B_Output_Register);
5753 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5756 return RTSI_Trig_Output_Source(chan,
5757 devpriv->rtsi_trig_a_output_reg);
5758 } else if (chan < num_configurable_rtsi_channels(dev)) {
5759 return RTSI_Trig_Output_Source(chan,
5760 devpriv->rtsi_trig_b_output_reg);
5762 if (chan == old_RTSI_clock_channel)
5763 return NI_RTSI_OUTPUT_RTSI_OSC;
5764 printk("%s: bug! should never get here?\n", __func__);
5769 static int ni_rtsi_insn_config(struct comedi_device *dev,
5770 struct comedi_subdevice *s,
5771 struct comedi_insn *insn, unsigned int *data)
5773 unsigned int chan = CR_CHAN(insn->chanspec);
5775 case INSN_CONFIG_DIO_OUTPUT:
5776 if (chan < num_configurable_rtsi_channels(dev)) {
5777 devpriv->rtsi_trig_direction_reg |=
5778 RTSI_Output_Bit(chan,
5780 reg_type & ni_reg_m_series_mask) !=
5782 } else if (chan == old_RTSI_clock_channel) {
5783 devpriv->rtsi_trig_direction_reg |=
5784 Drive_RTSI_Clock_Bit;
5786 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5787 RTSI_Trig_Direction_Register);
5789 case INSN_CONFIG_DIO_INPUT:
5790 if (chan < num_configurable_rtsi_channels(dev)) {
5791 devpriv->rtsi_trig_direction_reg &=
5792 ~RTSI_Output_Bit(chan,
5794 reg_type & ni_reg_m_series_mask)
5796 } else if (chan == old_RTSI_clock_channel) {
5797 devpriv->rtsi_trig_direction_reg &=
5798 ~Drive_RTSI_Clock_Bit;
5800 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5801 RTSI_Trig_Direction_Register);
5803 case INSN_CONFIG_DIO_QUERY:
5804 if (chan < num_configurable_rtsi_channels(dev)) {
5806 (devpriv->rtsi_trig_direction_reg &
5807 RTSI_Output_Bit(chan,
5808 (boardtype.reg_type &
5809 ni_reg_m_series_mask)
5810 != 0)) ? INSN_CONFIG_DIO_OUTPUT :
5811 INSN_CONFIG_DIO_INPUT;
5812 } else if (chan == old_RTSI_clock_channel) {
5814 (devpriv->rtsi_trig_direction_reg &
5815 Drive_RTSI_Clock_Bit)
5816 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5820 case INSN_CONFIG_SET_CLOCK_SRC:
5821 return ni_set_master_clock(dev, data[1], data[2]);
5823 case INSN_CONFIG_GET_CLOCK_SRC:
5824 data[1] = devpriv->clock_source;
5825 data[2] = devpriv->clock_ns;
5828 case INSN_CONFIG_SET_ROUTING:
5829 return ni_set_rtsi_routing(dev, chan, data[1]);
5831 case INSN_CONFIG_GET_ROUTING:
5832 data[1] = ni_get_rtsi_routing(dev, chan);
5842 static int cs5529_wait_for_idle(struct comedi_device *dev)
5844 unsigned short status;
5845 const int timeout = HZ;
5848 for (i = 0; i < timeout; i++) {
5849 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5850 if ((status & CSS_ADC_BUSY) == 0) {
5853 set_current_state(TASK_INTERRUPTIBLE);
5854 if (schedule_timeout(1)) {
5858 /* printk("looped %i times waiting for idle\n", i); */
5860 printk("%s: %s: timeout\n", __FILE__, __func__);
5866 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5868 static const int timeout = 100;
5871 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5872 /* give time for command to start being serially clocked into cs5529.
5873 * this insures that the CSS_ADC_BUSY bit will get properly
5874 * set before we exit this function.
5876 for (i = 0; i < timeout; i++) {
5877 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5881 /* printk("looped %i times writing command to cs5529\n", i); */
5883 comedi_error(dev, "possible problem - never saw adc go busy?");
5887 /* write to cs5529 register */
5888 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5889 unsigned int reg_select_bits)
5891 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5892 CAL_ADC_Config_Data_High_Word_67xx);
5893 ni_ao_win_outw(dev, (value & 0xffff),
5894 CAL_ADC_Config_Data_Low_Word_67xx);
5895 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5896 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5897 if (cs5529_wait_for_idle(dev))
5898 comedi_error(dev, "time or signal in cs5529_config_write()");
5901 #ifdef NI_CS5529_DEBUG
5902 /* read from cs5529 register */
5903 static unsigned int cs5529_config_read(struct comedi_device *dev,
5904 unsigned int reg_select_bits)
5908 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5909 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5910 if (cs5529_wait_for_idle(dev))
5911 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5912 value = (ni_ao_win_inw(dev,
5913 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5915 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5920 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5923 unsigned short status;
5925 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5926 retval = cs5529_wait_for_idle(dev);
5929 "timeout or signal in cs5529_do_conversion()");
5932 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5933 if (status & CSS_OSC_DETECT) {
5935 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5938 if (status & CSS_OVERRANGE) {
5940 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5943 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5944 /* cs5529 returns 16 bit signed data in bipolar mode */
5950 static int cs5529_ai_insn_read(struct comedi_device *dev,
5951 struct comedi_subdevice *s,
5952 struct comedi_insn *insn, unsigned int *data)
5955 unsigned short sample;
5956 unsigned int channel_select;
5957 const unsigned int INTERNAL_REF = 0x1000;
5959 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5960 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5961 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5962 if (insn->chanspec & CR_ALT_SOURCE)
5963 channel_select = INTERNAL_REF;
5965 channel_select = CR_CHAN(insn->chanspec);
5966 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5968 for (n = 0; n < insn->n; n++) {
5969 retval = cs5529_do_conversion(dev, &sample);
5977 static int init_cs5529(struct comedi_device *dev)
5979 unsigned int config_bits =
5980 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5983 /* do self-calibration */
5984 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5985 CSCMD_CONFIG_REGISTER);
5986 /* need to force a conversion for calibration to run */
5987 cs5529_do_conversion(dev, NULL);
5989 /* force gain calibration to 1 */
5990 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5991 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5992 CSCMD_CONFIG_REGISTER);
5993 if (cs5529_wait_for_idle(dev))
5994 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5996 #ifdef NI_CS5529_DEBUG
5997 printk("config: 0x%x\n", cs5529_config_read(dev,
5998 CSCMD_CONFIG_REGISTER));
5999 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6000 printk("offset: 0x%x\n", cs5529_config_read(dev,
6001 CSCMD_OFFSET_REGISTER));