drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 /* #define DEBUG_INTERRUPT */
  56 /* #define DEBUG_STATUS_A */
  57 /* #define DEBUG_STATUS_B */
  58
  59 #include <linux/interrupt.h>
  60 #include <linux/sched.h>
  61 #include "8255.h"
  62 #include "mite.h"
  63 #include "comedi_fc.h"
  64
  65 #ifndef MDPRINTK
  66 #define MDPRINTK(format, args...)
  67 #endif
  68
  69 /* A timeout count */
  70 #define NI_TIMEOUT 1000
  71 static const unsigned old_RTSI_clock_channel = 7;
  72
  73 /* Note: this table must match the ai_gain_* definitions */
  74 static const short ni_gainlkup[][16] = {
  75         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  76                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  77         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  78         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  79                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  80         [ai_gain_4] = {0, 1, 4, 7},
  81         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  82                           0x003, 0x004, 0x005, 0x006},
  83         [ai_gain_622x] = {0, 1, 4, 5},
  84         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  85         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  86 };
  87
  88 static const struct comedi_lrange range_ni_E_ai = { 16, {
  89                                                          RANGE(-10, 10),
  90                                                          RANGE(-5, 5),
  91                                                          RANGE(-2.5, 2.5),
  92                                                          RANGE(-1, 1),
  93                                                          RANGE(-0.5, 0.5),
  94                                                          RANGE(-0.25, 0.25),
  95                                                          RANGE(-0.1, 0.1),
  96                                                          RANGE(-0.05, 0.05),
  97                                                          RANGE(0, 20),
  98                                                          RANGE(0, 10),
  99                                                          RANGE(0, 5),
 100                                                          RANGE(0, 2),
 101                                                          RANGE(0, 1),
 102                                                          RANGE(0, 0.5),
 103                                                          RANGE(0, 0.2),
 104                                                          RANGE(0, 0.1),
 105                                                          }
 106 };
 107
 108 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
 109                                                                 RANGE(-10, 10),
 110                                                                 RANGE(-5, 5),
 111                                                                 RANGE(-1, 1),
 112                                                                 RANGE(-0.1,
 113                                                                       0.1),
 114                                                                 RANGE(0, 10),
 115                                                                 RANGE(0, 5),
 116                                                                 RANGE(0, 1),
 117                                                                 RANGE(0, 0.1),
 118                                                                 }
 119 };
 120
 121 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
 122                                                                    RANGE(-10,
 123                                                                          10),
 124                                                                    RANGE(-5, 5),
 125                                                                    RANGE(-2, 2),
 126                                                                    RANGE(-1, 1),
 127                                                                    RANGE(-0.5,
 128                                                                          0.5),
 129                                                                    RANGE(-0.2,
 130                                                                          0.2),
 131                                                                    RANGE(-0.1,
 132                                                                          0.1),
 133                                                                    RANGE(0, 10),
 134                                                                    RANGE(0, 5),
 135                                                                    RANGE(0, 2),
 136                                                                    RANGE(0, 1),
 137                                                                    RANGE(0,
 138                                                                          0.5),
 139                                                                    RANGE(0,
 140                                                                          0.2),
 141                                                                    RANGE(0,
 142                                                                          0.1),
 143                                                                    }
 144 };
 145
 146 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
 147                                                                  RANGE(-10, 10),
 148                                                                  RANGE(-5, 5),
 149                                                                  RANGE(-0.5,
 150                                                                        0.5),
 151                                                                  RANGE(-0.05,
 152                                                                        0.05),
 153                                                                  }
 154 };
 155
 156 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
 157                                                              RANGE(-50, 50),
 158                                                              RANGE(-20, 20),
 159                                                              RANGE(-10, 10),
 160                                                              RANGE(-5, 5),
 161                                                              RANGE(-2, 2),
 162                                                              RANGE(-1, 1),
 163                                                              RANGE(-0.5, 0.5),
 164                                                              RANGE(-0.2, 0.2),
 165                                                              }
 166 };
 167
 168 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
 169                                                              RANGE(-10, 10),
 170                                                              RANGE(-5, 5),
 171                                                              RANGE(-1, 1),
 172                                                              RANGE(-0.2, 0.2),
 173                                                              }
 174 };
 175
 176 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
 177                                                              RANGE(-10, 10),
 178                                                              RANGE(-5, 5),
 179                                                              RANGE(-2, 2),
 180                                                              RANGE(-1, 1),
 181                                                              RANGE(-0.5, 0.5),
 182                                                              RANGE(-0.2, 0.2),
 183                                                              RANGE(-0.1, 0.1),
 184                                                              }
 185 };
 186
 187 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
 188                                                             RANGE(-10, 10),
 189                                                             RANGE(0, 10),
 190                                                             RANGE_ext(-1, 1),
 191                                                             RANGE_ext(0, 1),
 192                                                             }
 193 };
 194
 195 static const struct comedi_lrange *const ni_range_lkup[] = {
 196         [ai_gain_16] = &range_ni_E_ai,
 197         [ai_gain_8] = &range_ni_E_ai_limited,
 198         [ai_gain_14] = &range_ni_E_ai_limited14,
 199         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 200         [ai_gain_611x] = &range_ni_E_ai_611x,
 201         [ai_gain_622x] = &range_ni_M_ai_622x,
 202         [ai_gain_628x] = &range_ni_M_ai_628x,
 203         [ai_gain_6143] = &range_bipolar5
 204 };
 205
 206 static int ni_dio_insn_config(struct comedi_device *dev,
 207                               struct comedi_subdevice *s,
 208                               struct comedi_insn *insn, unsigned int *data);
 209 static int ni_dio_insn_bits(struct comedi_device *dev,
 210                             struct comedi_subdevice *s,
 211                             struct comedi_insn *insn, unsigned int *data);
 212 static int ni_cdio_cmdtest(struct comedi_device *dev,
 213                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 214 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 215 static int ni_cdio_cancel(struct comedi_device *dev,
 216                           struct comedi_subdevice *s);
 217 static void handle_cdio_interrupt(struct comedi_device *dev);
 218 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 219                           unsigned int trignum);
 220
 221 static int ni_serial_insn_config(struct comedi_device *dev,
 222                                  struct comedi_subdevice *s,
 223                                  struct comedi_insn *insn, unsigned int *data);
 224 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 225                                    struct comedi_subdevice *s,
 226                                    unsigned char data_out,
 227                                    unsigned char *data_in);
 228 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 229                                    struct comedi_subdevice *s,
 230                                    unsigned char data_out,
 231                                    unsigned char *data_in);
 232
 233 static int ni_calib_insn_read(struct comedi_device *dev,
 234                               struct comedi_subdevice *s,
 235                               struct comedi_insn *insn, unsigned int *data);
 236 static int ni_calib_insn_write(struct comedi_device *dev,
 237                                struct comedi_subdevice *s,
 238                                struct comedi_insn *insn, unsigned int *data);
 239
 240 static int ni_eeprom_insn_read(struct comedi_device *dev,
 241                                struct comedi_subdevice *s,
 242                                struct comedi_insn *insn, unsigned int *data);
 243 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 244                                         struct comedi_subdevice *s,
 245                                         struct comedi_insn *insn,
 246                                         unsigned int *data);
 247
 248 static int ni_pfi_insn_bits(struct comedi_device *dev,
 249                             struct comedi_subdevice *s,
 250                             struct comedi_insn *insn, unsigned int *data);
 251 static int ni_pfi_insn_config(struct comedi_device *dev,
 252                               struct comedi_subdevice *s,
 253                               struct comedi_insn *insn, unsigned int *data);
 254 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 255                                        unsigned chan);
 256
 257 static void ni_rtsi_init(struct comedi_device *dev);
 258 static int ni_rtsi_insn_bits(struct comedi_device *dev,
 259                              struct comedi_subdevice *s,
 260                              struct comedi_insn *insn, unsigned int *data);
 261 static int ni_rtsi_insn_config(struct comedi_device *dev,
 262                                struct comedi_subdevice *s,
 263                                struct comedi_insn *insn, unsigned int *data);
 264
 265 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 266 static int ni_read_eeprom(struct comedi_device *dev, int addr);
 267
 268 #ifdef DEBUG_STATUS_A
 269 static void ni_mio_print_status_a(int status);
 270 #else
 271 #define ni_mio_print_status_a(a)
 272 #endif
 273 #ifdef DEBUG_STATUS_B
 274 static void ni_mio_print_status_b(int status);
 275 #else
 276 #define ni_mio_print_status_b(a)
 277 #endif
 278
 279 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 280 #ifndef PCIDMA
 281 static void ni_handle_fifo_half_full(struct comedi_device *dev);
 282 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 283                                  struct comedi_subdevice *s);
 284 #endif
 285 static void ni_handle_fifo_dregs(struct comedi_device *dev);
 286 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 287                          unsigned int trignum);
 288 static void ni_load_channelgain_list(struct comedi_device *dev,
 289                                      unsigned int n_chan, unsigned int *list);
 290 static void shutdown_ai_command(struct comedi_device *dev);
 291
 292 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 293                          unsigned int trignum);
 294
 295 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 296
 297 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 298
 299 static int ni_gpct_insn_write(struct comedi_device *dev,
 300                               struct comedi_subdevice *s,
 301                               struct comedi_insn *insn, unsigned int *data);
 302 static int ni_gpct_insn_read(struct comedi_device *dev,
 303                              struct comedi_subdevice *s,
 304                              struct comedi_insn *insn, unsigned int *data);
 305 static int ni_gpct_insn_config(struct comedi_device *dev,
 306                                struct comedi_subdevice *s,
 307                                struct comedi_insn *insn, unsigned int *data);
 308 #ifdef PCIDMA
 309 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 310 static int ni_gpct_cmdtest(struct comedi_device *dev,
 311                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 312 #endif
 313 static int ni_gpct_cancel(struct comedi_device *dev,
 314                           struct comedi_subdevice *s);
 315 static void handle_gpct_interrupt(struct comedi_device *dev,
 316                                   unsigned short counter_index);
 317
 318 static int init_cs5529(struct comedi_device *dev);
 319 static int cs5529_do_conversion(struct comedi_device *dev,
 320                                 unsigned short *data);
 321 static int cs5529_ai_insn_read(struct comedi_device *dev,
 322                                struct comedi_subdevice *s,
 323                                struct comedi_insn *insn, unsigned int *data);
 324 #ifdef NI_CS5529_DEBUG
 325 static unsigned int cs5529_config_read(struct comedi_device *dev,
 326                                        unsigned int reg_select_bits);
 327 #endif
 328 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 329                                 unsigned int reg_select_bits);
 330
 331 static int ni_m_series_pwm_config(struct comedi_device *dev,
 332                                   struct comedi_subdevice *s,
 333                                   struct comedi_insn *insn, unsigned int *data);
 334 static int ni_6143_pwm_config(struct comedi_device *dev,
 335                               struct comedi_subdevice *s,
 336                               struct comedi_insn *insn, unsigned int *data);
 337
 338 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 339                                unsigned period_ns);
 340 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 341 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 342
 343 enum aimodes {
 344         AIMODE_NONE = 0,
 345         AIMODE_HALF_FULL = 1,
 346         AIMODE_SCAN = 2,
 347         AIMODE_SAMPLE = 3,
 348 };
 349
 350 enum ni_common_subdevices {
 351         NI_AI_SUBDEV,
 352         NI_AO_SUBDEV,
 353         NI_DIO_SUBDEV,
 354         NI_8255_DIO_SUBDEV,
 355         NI_UNUSED_SUBDEV,
 356         NI_CALIBRATION_SUBDEV,
 357         NI_EEPROM_SUBDEV,
 358         NI_PFI_DIO_SUBDEV,
 359         NI_CS5529_CALIBRATION_SUBDEV,
 360         NI_SERIAL_SUBDEV,
 361         NI_RTSI_SUBDEV,
 362         NI_GPCT0_SUBDEV,
 363         NI_GPCT1_SUBDEV,
 364         NI_FREQ_OUT_SUBDEV,
 365         NI_NUM_SUBDEVICES
 366 };
 367 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 368 {
 369         switch (counter_index) {
 370         case 0:
 371                 return NI_GPCT0_SUBDEV;
 372                 break;
 373         case 1:
 374                 return NI_GPCT1_SUBDEV;
 375                 break;
 376         default:
 377                 break;
 378         }
 379         BUG();
 380         return NI_GPCT0_SUBDEV;
 381 }
 382
 383 enum timebase_nanoseconds {
 384         TIMEBASE_1_NS = 50,
 385         TIMEBASE_2_NS = 10000
 386 };
 387
 388 #define SERIAL_DISABLED         0
 389 #define SERIAL_600NS            600
 390 #define SERIAL_1_2US            1200
 391 #define SERIAL_10US                     10000
 392
 393 static const int num_adc_stages_611x = 3;
 394
 395 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 396                                unsigned ai_mite_status);
 397 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 398                                unsigned ao_mite_status);
 399 static void get_last_sample_611x(struct comedi_device *dev);
 400 static void get_last_sample_6143(struct comedi_device *dev);
 401
 402 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 403                                    unsigned bit_mask, unsigned bit_values)
 404 {
 405         struct ni_private *devpriv = dev->private;
 406         unsigned long flags;
 407
 408         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 409         switch (reg) {
 410         case Interrupt_A_Enable_Register:
 411                 devpriv->int_a_enable_reg &= ~bit_mask;
 412                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 413                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 414                                     Interrupt_A_Enable_Register);
 415                 break;
 416         case Interrupt_B_Enable_Register:
 417                 devpriv->int_b_enable_reg &= ~bit_mask;
 418                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 419                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 420                                     Interrupt_B_Enable_Register);
 421                 break;
 422         case IO_Bidirection_Pin_Register:
 423                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 424                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 425                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 426                                     IO_Bidirection_Pin_Register);
 427                 break;
 428         case AI_AO_Select:
 429                 devpriv->ai_ao_select_reg &= ~bit_mask;
 430                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 431                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 432                 break;
 433         case G0_G1_Select:
 434                 devpriv->g0_g1_select_reg &= ~bit_mask;
 435                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 436                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 437                 break;
 438         default:
 439                 printk("Warning %s() called with invalid register\n", __func__);
 440                 printk("reg is %d\n", reg);
 441                 break;
 442         }
 443         mmiowb();
 444         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 445 }
 446
 447 #ifdef PCIDMA
 448 static int ni_ai_drain_dma(struct comedi_device *dev);
 449
 450 /* DMA channel setup */
 451
 452 /* negative channel means no channel */
 453 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 454 {
 455         unsigned bitfield;
 456
 457         if (channel >= 0) {
 458                 bitfield =
 459                     (ni_stc_dma_channel_select_bitfield(channel) <<
 460                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 461         } else {
 462                 bitfield = 0;
 463         }
 464         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 465 }
 466
 467 /* negative channel means no channel */
 468 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 469 {
 470         unsigned bitfield;
 471
 472         if (channel >= 0) {
 473                 bitfield =
 474                     (ni_stc_dma_channel_select_bitfield(channel) <<
 475                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 476         } else {
 477                 bitfield = 0;
 478         }
 479         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 480 }
 481
 482 /* negative mite_channel means no channel */
 483 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 484                                            unsigned gpct_index,
 485                                            int mite_channel)
 486 {
 487         unsigned bitfield;
 488
 489         if (mite_channel >= 0) {
 490                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 491         } else {
 492                 bitfield = 0;
 493         }
 494         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 495                         bitfield);
 496 }
 497
 498 /* negative mite_channel means no channel */
 499 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 500                                           int mite_channel)
 501 {
 502         struct ni_private *devpriv = dev->private;
 503         unsigned long flags;
 504
 505         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 506         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 507         if (mite_channel >= 0) {
 508                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 509                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 510                    Definitely works for dma channels 0 and 1. */
 511                 devpriv->cdio_dma_select_reg |=
 512                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 513                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 514         }
 515         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 516         mmiowb();
 517         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 518 }
 519
 520 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 521 {
 522         struct ni_private *devpriv = dev->private;
 523         unsigned long flags;
 524
 525         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 526         BUG_ON(devpriv->ai_mite_chan);
 527         devpriv->ai_mite_chan =
 528             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 529         if (devpriv->ai_mite_chan == NULL) {
 530                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 531                 comedi_error(dev,
 532                              "failed to reserve mite dma channel for analog input.");
 533                 return -EBUSY;
 534         }
 535         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 536         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 537         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 538         return 0;
 539 }
 540
 541 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 542 {
 543         struct ni_private *devpriv = dev->private;
 544         unsigned long flags;
 545
 546         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 547         BUG_ON(devpriv->ao_mite_chan);
 548         devpriv->ao_mite_chan =
 549             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 550         if (devpriv->ao_mite_chan == NULL) {
 551                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 552                 comedi_error(dev,
 553                              "failed to reserve mite dma channel for analog outut.");
 554                 return -EBUSY;
 555         }
 556         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 557         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 558         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 559         return 0;
 560 }
 561
 562 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 563                                         unsigned gpct_index,
 564                                         enum comedi_io_direction direction)
 565 {
 566         struct ni_private *devpriv = dev->private;
 567         unsigned long flags;
 568         struct mite_channel *mite_chan;
 569
 570         BUG_ON(gpct_index >= NUM_GPCT);
 571         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 572         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 573         mite_chan =
 574             mite_request_channel(devpriv->mite,
 575                                  devpriv->gpct_mite_ring[gpct_index]);
 576         if (mite_chan == NULL) {
 577                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 578                 comedi_error(dev,
 579                              "failed to reserve mite dma channel for counter.");
 580                 return -EBUSY;
 581         }
 582         mite_chan->dir = direction;
 583         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 584                                 mite_chan);
 585         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 586         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 587         return 0;
 588 }
 589
 590 #endif /*  PCIDMA */
 591
 592 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 593 {
 594 #ifdef PCIDMA
 595         struct ni_private *devpriv = dev->private;
 596         unsigned long flags;
 597
 598         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 599         BUG_ON(devpriv->cdo_mite_chan);
 600         devpriv->cdo_mite_chan =
 601             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 602         if (devpriv->cdo_mite_chan == NULL) {
 603                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 604                 comedi_error(dev,
 605                              "failed to reserve mite dma channel for correlated digital outut.");
 606                 return -EBUSY;
 607         }
 608         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 609         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 610         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 611 #endif /*  PCIDMA */
 612         return 0;
 613 }
 614
 615 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 616 {
 617 #ifdef PCIDMA
 618         struct ni_private *devpriv = dev->private;
 619         unsigned long flags;
 620
 621         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 622         if (devpriv->ai_mite_chan) {
 623                 ni_set_ai_dma_channel(dev, -1);
 624                 mite_release_channel(devpriv->ai_mite_chan);
 625                 devpriv->ai_mite_chan = NULL;
 626         }
 627         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 628 #endif /*  PCIDMA */
 629 }
 630
 631 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 632 {
 633 #ifdef PCIDMA
 634         struct ni_private *devpriv = dev->private;
 635         unsigned long flags;
 636
 637         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 638         if (devpriv->ao_mite_chan) {
 639                 ni_set_ao_dma_channel(dev, -1);
 640                 mite_release_channel(devpriv->ao_mite_chan);
 641                 devpriv->ao_mite_chan = NULL;
 642         }
 643         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 644 #endif /*  PCIDMA */
 645 }
 646
 647 #ifdef PCIDMA
 648 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 649                                          unsigned gpct_index)
 650 {
 651         struct ni_private *devpriv = dev->private;
 652         unsigned long flags;
 653
 654         BUG_ON(gpct_index >= NUM_GPCT);
 655         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 656         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 657                 struct mite_channel *mite_chan =
 658                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 659
 660                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 661                 ni_tio_set_mite_channel(&devpriv->
 662                                         counter_dev->counters[gpct_index],
 663                                         NULL);
 664                 mite_release_channel(mite_chan);
 665         }
 666         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 667 }
 668 #endif /*  PCIDMA */
 669
 670 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 671 {
 672 #ifdef PCIDMA
 673         struct ni_private *devpriv = dev->private;
 674         unsigned long flags;
 675
 676         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 677         if (devpriv->cdo_mite_chan) {
 678                 ni_set_cdo_dma_channel(dev, -1);
 679                 mite_release_channel(devpriv->cdo_mite_chan);
 680                 devpriv->cdo_mite_chan = NULL;
 681         }
 682         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 683 #endif /*  PCIDMA */
 684 }
 685
 686 /* e-series boards use the second irq signals to generate dma requests for their counters */
 687 #ifdef PCIDMA
 688 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 689                                           unsigned gpct_index, short enable)
 690 {
 691         const struct ni_board_struct *board = comedi_board(dev);
 692         struct ni_private *devpriv = dev->private;
 693
 694         if (board->reg_type & ni_reg_m_series_mask)
 695                 return;
 696         switch (gpct_index) {
 697         case 0:
 698                 if (enable) {
 699                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 700                                             Second_IRQ_A_Enable_Register);
 701                 } else {
 702                         devpriv->stc_writew(dev, 0,
 703                                             Second_IRQ_A_Enable_Register);
 704                 }
 705                 break;
 706         case 1:
 707                 if (enable) {
 708                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 709                                             Second_IRQ_B_Enable_Register);
 710                 } else {
 711                         devpriv->stc_writew(dev, 0,
 712                                             Second_IRQ_B_Enable_Register);
 713                 }
 714                 break;
 715         default:
 716                 BUG();
 717                 break;
 718         }
 719 }
 720 #endif /*  PCIDMA */
 721
 722 static void ni_clear_ai_fifo(struct comedi_device *dev)
 723 {
 724         const struct ni_board_struct *board = comedi_board(dev);
 725         struct ni_private *devpriv = dev->private;
 726
 727         if (board->reg_type == ni_reg_6143) {
 728                 /*  Flush the 6143 data FIFO */
 729                 ni_writel(0x10, AIFIFO_Control_6143);   /*  Flush fifo */
 730                 ni_writel(0x00, AIFIFO_Control_6143);   /*  Flush fifo */
 731                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   /*  Wait for complete */
 732         } else {
 733                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 734                 if (board->reg_type == ni_reg_625x) {
 735                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 736                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 737 #if 0
 738                         /* the NI example code does 3 convert pulses for 625x boards,
 739                            but that appears to be wrong in practice. */
 740                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 741                                             AI_Command_1_Register);
 742                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 743                                             AI_Command_1_Register);
 744                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 745                                             AI_Command_1_Register);
 746 #endif
 747                 }
 748         }
 749 }
 750
 751 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 752 {
 753         struct ni_private *devpriv = dev->private;
 754
 755         devpriv->stc_writew(dev, data >> 16, reg);
 756         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 757 }
 758
 759 static uint32_t win_in2(struct comedi_device *dev, int reg)
 760 {
 761         struct ni_private *devpriv = dev->private;
 762         uint32_t bits;
 763
 764         bits = devpriv->stc_readw(dev, reg) << 16;
 765         bits |= devpriv->stc_readw(dev, reg + 1);
 766         return bits;
 767 }
 768
 769 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 770 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 771                                   int addr)
 772 {
 773         struct ni_private *devpriv = dev->private;
 774         unsigned long flags;
 775
 776         spin_lock_irqsave(&devpriv->window_lock, flags);
 777         ni_writew(addr, AO_Window_Address_611x);
 778         ni_writew(data, AO_Window_Data_611x);
 779         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 780 }
 781
 782 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 783                                   int addr)
 784 {
 785         struct ni_private *devpriv = dev->private;
 786         unsigned long flags;
 787
 788         spin_lock_irqsave(&devpriv->window_lock, flags);
 789         ni_writew(addr, AO_Window_Address_611x);
 790         ni_writel(data, AO_Window_Data_611x);
 791         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 792 }
 793
 794 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 795 {
 796         struct ni_private *devpriv = dev->private;
 797         unsigned long flags;
 798         unsigned short data;
 799
 800         spin_lock_irqsave(&devpriv->window_lock, flags);
 801         ni_writew(addr, AO_Window_Address_611x);
 802         data = ni_readw(AO_Window_Data_611x);
 803         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 804         return data;
 805 }
 806
 807 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 808 * share registers (such as Interrupt_A_Register) without interfering with
 809 * each other.
 810 *
 811 * NOTE: the switch/case statements are optimized out for a constant argument
 812 * so this is actually quite fast---  If you must wrap another function around this
 813 * make it inline to avoid a large speed penalty.
 814 *
 815 * value should only be 1 or 0.
 816 */
 817 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 818                                unsigned bits, unsigned value)
 819 {
 820         unsigned bit_values;
 821
 822         if (value)
 823                 bit_values = bits;
 824         else
 825                 bit_values = 0;
 826         ni_set_bitfield(dev, reg, bits, bit_values);
 827 }
 828
 829 static irqreturn_t ni_E_interrupt(int irq, void *d)
 830 {
 831         struct comedi_device *dev = d;
 832         struct ni_private *devpriv = dev->private;
 833         unsigned short a_status;
 834         unsigned short b_status;
 835         unsigned int ai_mite_status = 0;
 836         unsigned int ao_mite_status = 0;
 837         unsigned long flags;
 838 #ifdef PCIDMA
 839         struct mite_struct *mite = devpriv->mite;
 840 #endif
 841
 842         if (!dev->attached)
 843                 return IRQ_NONE;
 844         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
 845
 846         /*  lock to avoid race with comedi_poll */
 847         spin_lock_irqsave(&dev->spinlock, flags);
 848         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 849         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 850 #ifdef PCIDMA
 851         if (mite) {
 852                 unsigned long flags_too;
 853
 854                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 855                 if (devpriv->ai_mite_chan) {
 856                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 857                         if (ai_mite_status & CHSR_LINKC)
 858                                 writel(CHOR_CLRLC,
 859                                        devpriv->mite->mite_io_addr +
 860                                        MITE_CHOR(devpriv->
 861                                                  ai_mite_chan->channel));
 862                 }
 863                 if (devpriv->ao_mite_chan) {
 864                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 865                         if (ao_mite_status & CHSR_LINKC)
 866                                 writel(CHOR_CLRLC,
 867                                        mite->mite_io_addr +
 868                                        MITE_CHOR(devpriv->
 869                                                  ao_mite_chan->channel));
 870                 }
 871                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 872         }
 873 #endif
 874         ack_a_interrupt(dev, a_status);
 875         ack_b_interrupt(dev, b_status);
 876         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 877                 handle_a_interrupt(dev, a_status, ai_mite_status);
 878         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 879                 handle_b_interrupt(dev, b_status, ao_mite_status);
 880         handle_gpct_interrupt(dev, 0);
 881         handle_gpct_interrupt(dev, 1);
 882         handle_cdio_interrupt(dev);
 883
 884         spin_unlock_irqrestore(&dev->spinlock, flags);
 885         return IRQ_HANDLED;
 886 }
 887
 888 #ifdef PCIDMA
 889 static void ni_sync_ai_dma(struct comedi_device *dev)
 890 {
 891         struct ni_private *devpriv = dev->private;
 892         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 893         unsigned long flags;
 894
 895         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 896         if (devpriv->ai_mite_chan)
 897                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 898         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 899 }
 900
 901 static void mite_handle_b_linkc(struct mite_struct *mite,
 902                                 struct comedi_device *dev)
 903 {
 904         struct ni_private *devpriv = dev->private;
 905         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
 906         unsigned long flags;
 907
 908         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 909         if (devpriv->ao_mite_chan) {
 910                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 911         }
 912         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 913 }
 914
 915 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 916 {
 917         struct ni_private *devpriv = dev->private;
 918         static const int timeout = 10000;
 919         int i;
 920         for (i = 0; i < timeout; i++) {
 921                 unsigned short b_status;
 922
 923                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 924                 if (b_status & AO_FIFO_Half_Full_St)
 925                         break;
 926                 /* if we poll too often, the pci bus activity seems
 927                    to slow the dma transfer down */
 928                 udelay(10);
 929         }
 930         if (i == timeout) {
 931                 comedi_error(dev, "timed out waiting for dma load");
 932                 return -EPIPE;
 933         }
 934         return 0;
 935 }
 936
 937 #endif /* PCIDMA */
 938 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 939 {
 940         struct ni_private *devpriv = dev->private;
 941
 942         if (devpriv->aimode == AIMODE_SCAN) {
 943 #ifdef PCIDMA
 944                 static const int timeout = 10;
 945                 int i;
 946
 947                 for (i = 0; i < timeout; i++) {
 948                         ni_sync_ai_dma(dev);
 949                         if ((s->async->events & COMEDI_CB_EOS))
 950                                 break;
 951                         udelay(1);
 952                 }
 953 #else
 954                 ni_handle_fifo_dregs(dev);
 955                 s->async->events |= COMEDI_CB_EOS;
 956 #endif
 957         }
 958         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 959         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 960                 shutdown_ai_command(dev);
 961         }
 962 }
 963
 964 static void shutdown_ai_command(struct comedi_device *dev)
 965 {
 966         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 967
 968 #ifdef PCIDMA
 969         ni_ai_drain_dma(dev);
 970 #endif
 971         ni_handle_fifo_dregs(dev);
 972         get_last_sample_611x(dev);
 973         get_last_sample_6143(dev);
 974
 975         s->async->events |= COMEDI_CB_EOA;
 976 }
 977
 978 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
 979 {
 980         if (s->
 981             async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
 982                              COMEDI_CB_EOA)) {
 983                 switch (s->index) {
 984                 case NI_AI_SUBDEV:
 985                         ni_ai_reset(dev, s);
 986                         break;
 987                 case NI_AO_SUBDEV:
 988                         ni_ao_reset(dev, s);
 989                         break;
 990                 case NI_GPCT0_SUBDEV:
 991                 case NI_GPCT1_SUBDEV:
 992                         ni_gpct_cancel(dev, s);
 993                         break;
 994                 case NI_DIO_SUBDEV:
 995                         ni_cdio_cancel(dev, s);
 996                         break;
 997                 default:
 998                         break;
 999                 }
1000         }
1001         comedi_event(dev, s);
1002 }
1003
1004 static void handle_gpct_interrupt(struct comedi_device *dev,
1005                                   unsigned short counter_index)
1006 {
1007 #ifdef PCIDMA
1008         struct ni_private *devpriv = dev->private;
1009         struct comedi_subdevice *s;
1010
1011         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1012
1013         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1014                                 s);
1015         if (s->async->events)
1016                 ni_event(dev, s);
1017 #endif
1018 }
1019
1020 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1021 {
1022         struct ni_private *devpriv = dev->private;
1023         unsigned short ack = 0;
1024
1025         if (a_status & AI_SC_TC_St) {
1026                 ack |= AI_SC_TC_Interrupt_Ack;
1027         }
1028         if (a_status & AI_START1_St) {
1029                 ack |= AI_START1_Interrupt_Ack;
1030         }
1031         if (a_status & AI_START_St) {
1032                 ack |= AI_START_Interrupt_Ack;
1033         }
1034         if (a_status & AI_STOP_St) {
1035                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1036                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1037         }
1038         if (ack)
1039                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1040 }
1041
1042 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1043                                unsigned ai_mite_status)
1044 {
1045         struct ni_private *devpriv = dev->private;
1046         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1047
1048         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1049         if (s->type == COMEDI_SUBD_UNUSED)
1050                 return;
1051
1052 #ifdef DEBUG_INTERRUPT
1053         printk
1054             ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1055              status, ai_mite_status);
1056         ni_mio_print_status_a(status);
1057 #endif
1058 #ifdef PCIDMA
1059         if (ai_mite_status & CHSR_LINKC) {
1060                 ni_sync_ai_dma(dev);
1061         }
1062
1063         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1064                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1065                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1066                 printk
1067                     ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1068                      ai_mite_status);
1069                 /* mite_print_chsr(ai_mite_status); */
1070                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1071                 /* disable_irq(dev->irq); */
1072         }
1073 #endif
1074
1075         /* test for all uncommon interrupt events at the same time */
1076         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1077                       AI_SC_TC_St | AI_START1_St)) {
1078                 if (status == 0xffff) {
1079                         printk
1080                             ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1081                         /* we probably aren't even running a command now,
1082                          * so it's a good idea to be careful. */
1083                         if (comedi_is_subdevice_running(s)) {
1084                                 s->async->events |=
1085                                     COMEDI_CB_ERROR | COMEDI_CB_EOA;
1086                                 ni_event(dev, s);
1087                         }
1088                         return;
1089                 }
1090                 if (status & (AI_Overrun_St | AI_Overflow_St |
1091                               AI_SC_TC_Error_St)) {
1092                         printk("ni_mio_common: ai error a_status=%04x\n",
1093                                status);
1094                         ni_mio_print_status_a(status);
1095
1096                         shutdown_ai_command(dev);
1097
1098                         s->async->events |= COMEDI_CB_ERROR;
1099                         if (status & (AI_Overrun_St | AI_Overflow_St))
1100                                 s->async->events |= COMEDI_CB_OVERFLOW;
1101
1102                         ni_event(dev, s);
1103
1104                         return;
1105                 }
1106                 if (status & AI_SC_TC_St) {
1107 #ifdef DEBUG_INTERRUPT
1108                         printk("ni_mio_common: SC_TC interrupt\n");
1109 #endif
1110                         if (!devpriv->ai_continuous) {
1111                                 shutdown_ai_command(dev);
1112                         }
1113                 }
1114         }
1115 #ifndef PCIDMA
1116         if (status & AI_FIFO_Half_Full_St) {
1117                 int i;
1118                 static const int timeout = 10;
1119                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1120                  *fail to get the fifo less than half full, so loop to be sure.*/
1121                 for (i = 0; i < timeout; ++i) {
1122                         ni_handle_fifo_half_full(dev);
1123                         if ((devpriv->stc_readw(dev,
1124                                                 AI_Status_1_Register) &
1125                              AI_FIFO_Half_Full_St) == 0)
1126                                 break;
1127                 }
1128         }
1129 #endif /*  !PCIDMA */
1130
1131         if ((status & AI_STOP_St)) {
1132                 ni_handle_eos(dev, s);
1133         }
1134
1135         ni_event(dev, s);
1136
1137 #ifdef DEBUG_INTERRUPT
1138         status = devpriv->stc_readw(dev, AI_Status_1_Register);
1139         if (status & Interrupt_A_St) {
1140                 printk
1141                     ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1142                      status);
1143         }
1144 #endif
1145 }
1146
1147 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1148 {
1149         struct ni_private *devpriv = dev->private;
1150         unsigned short ack = 0;
1151
1152         if (b_status & AO_BC_TC_St) {
1153                 ack |= AO_BC_TC_Interrupt_Ack;
1154         }
1155         if (b_status & AO_Overrun_St) {
1156                 ack |= AO_Error_Interrupt_Ack;
1157         }
1158         if (b_status & AO_START_St) {
1159                 ack |= AO_START_Interrupt_Ack;
1160         }
1161         if (b_status & AO_START1_St) {
1162                 ack |= AO_START1_Interrupt_Ack;
1163         }
1164         if (b_status & AO_UC_TC_St) {
1165                 ack |= AO_UC_TC_Interrupt_Ack;
1166         }
1167         if (b_status & AO_UI2_TC_St) {
1168                 ack |= AO_UI2_TC_Interrupt_Ack;
1169         }
1170         if (b_status & AO_UPDATE_St) {
1171                 ack |= AO_UPDATE_Interrupt_Ack;
1172         }
1173         if (ack)
1174                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1175 }
1176
1177 static void handle_b_interrupt(struct comedi_device *dev,
1178                                unsigned short b_status, unsigned ao_mite_status)
1179 {
1180         struct ni_private *devpriv = dev->private;
1181         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1182         /* unsigned short ack=0; */
1183
1184 #ifdef DEBUG_INTERRUPT
1185         printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1186                b_status, ao_mite_status);
1187         ni_mio_print_status_b(b_status);
1188 #endif
1189
1190 #ifdef PCIDMA
1191         /* Currently, mite.c requires us to handle LINKC */
1192         if (ao_mite_status & CHSR_LINKC) {
1193                 mite_handle_b_linkc(devpriv->mite, dev);
1194         }
1195
1196         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1197                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1198                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1199                 printk
1200                     ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1201                      ao_mite_status);
1202                 /* mite_print_chsr(ao_mite_status); */
1203                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1204         }
1205 #endif
1206
1207         if (b_status == 0xffff)
1208                 return;
1209         if (b_status & AO_Overrun_St) {
1210                 printk
1211                     ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1212                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1213                 s->async->events |= COMEDI_CB_OVERFLOW;
1214         }
1215
1216         if (b_status & AO_BC_TC_St) {
1217                 MDPRINTK
1218                     ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1219                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1220                 s->async->events |= COMEDI_CB_EOA;
1221         }
1222 #ifndef PCIDMA
1223         if (b_status & AO_FIFO_Request_St) {
1224                 int ret;
1225
1226                 ret = ni_ao_fifo_half_empty(dev, s);
1227                 if (!ret) {
1228                         printk("ni_mio_common: AO buffer underrun\n");
1229                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1230                                     AO_FIFO_Interrupt_Enable |
1231                                     AO_Error_Interrupt_Enable, 0);
1232                         s->async->events |= COMEDI_CB_OVERFLOW;
1233                 }
1234         }
1235 #endif
1236
1237         ni_event(dev, s);
1238 }
1239
1240 #ifdef DEBUG_STATUS_A
1241 static const char *const status_a_strings[] = {
1242         "passthru0", "fifo", "G0_gate", "G0_TC",
1243         "stop", "start", "sc_tc", "start1",
1244         "start2", "sc_tc_error", "overflow", "overrun",
1245         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1246 };
1247
1248 static void ni_mio_print_status_a(int status)
1249 {
1250         int i;
1251
1252         printk("A status:");
1253         for (i = 15; i >= 0; i--) {
1254                 if (status & (1 << i)) {
1255                         printk(" %s", status_a_strings[i]);
1256                 }
1257         }
1258         printk("\n");
1259 }
1260 #endif
1261
1262 #ifdef DEBUG_STATUS_B
1263 static const char *const status_b_strings[] = {
1264         "passthru1", "fifo", "G1_gate", "G1_TC",
1265         "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1266         "start1", "overrun", "start", "bc_tc_error",
1267         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1268 };
1269
1270 static void ni_mio_print_status_b(int status)
1271 {
1272         int i;
1273
1274         printk("B status:");
1275         for (i = 15; i >= 0; i--) {
1276                 if (status & (1 << i)) {
1277                         printk(" %s", status_b_strings[i]);
1278                 }
1279         }
1280         printk("\n");
1281 }
1282 #endif
1283
1284 #ifndef PCIDMA
1285
1286 static void ni_ao_fifo_load(struct comedi_device *dev,
1287                             struct comedi_subdevice *s, int n)
1288 {
1289         const struct ni_board_struct *board = comedi_board(dev);
1290         struct comedi_async *async = s->async;
1291         struct comedi_cmd *cmd = &async->cmd;
1292         int chan;
1293         int i;
1294         short d;
1295         u32 packed_data;
1296         int range;
1297         int err = 1;
1298
1299         chan = async->cur_chan;
1300         for (i = 0; i < n; i++) {
1301                 err &= comedi_buf_get(async, &d);
1302                 if (err == 0)
1303                         break;
1304
1305                 range = CR_RANGE(cmd->chanlist[chan]);
1306
1307                 if (board->reg_type & ni_reg_6xxx_mask) {
1308                         packed_data = d & 0xffff;
1309                         /* 6711 only has 16 bit wide ao fifo */
1310                         if (board->reg_type != ni_reg_6711) {
1311                                 err &= comedi_buf_get(async, &d);
1312                                 if (err == 0)
1313                                         break;
1314                                 chan++;
1315                                 i++;
1316                                 packed_data |= (d << 16) & 0xffff0000;
1317                         }
1318                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1319                 } else {
1320                         ni_writew(d, DAC_FIFO_Data);
1321                 }
1322                 chan++;
1323                 chan %= cmd->chanlist_len;
1324         }
1325         async->cur_chan = chan;
1326         if (err == 0) {
1327                 async->events |= COMEDI_CB_OVERFLOW;
1328         }
1329 }
1330
1331 /*
1332  *  There's a small problem if the FIFO gets really low and we
1333  *  don't have the data to fill it.  Basically, if after we fill
1334  *  the FIFO with all the data available, the FIFO is _still_
1335  *  less than half full, we never clear the interrupt.  If the
1336  *  IRQ is in edge mode, we never get another interrupt, because
1337  *  this one wasn't cleared.  If in level mode, we get flooded
1338  *  with interrupts that we can't fulfill, because nothing ever
1339  *  gets put into the buffer.
1340  *
1341  *  This kind of situation is recoverable, but it is easier to
1342  *  just pretend we had a FIFO underrun, since there is a good
1343  *  chance it will happen anyway.  This is _not_ the case for
1344  *  RT code, as RT code might purposely be running close to the
1345  *  metal.  Needs to be fixed eventually.
1346  */
1347 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1348                                  struct comedi_subdevice *s)
1349 {
1350         const struct ni_board_struct *board = comedi_board(dev);
1351         int n;
1352
1353         n = comedi_buf_read_n_available(s->async);
1354         if (n == 0) {
1355                 s->async->events |= COMEDI_CB_OVERFLOW;
1356                 return 0;
1357         }
1358
1359         n /= sizeof(short);
1360         if (n > board->ao_fifo_depth / 2)
1361                 n = board->ao_fifo_depth / 2;
1362
1363         ni_ao_fifo_load(dev, s, n);
1364
1365         s->async->events |= COMEDI_CB_BLOCK;
1366
1367         return 1;
1368 }
1369
1370 static int ni_ao_prep_fifo(struct comedi_device *dev,
1371                            struct comedi_subdevice *s)
1372 {
1373         const struct ni_board_struct *board = comedi_board(dev);
1374         struct ni_private *devpriv = dev->private;
1375         int n;
1376
1377         /* reset fifo */
1378         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1379         if (board->reg_type & ni_reg_6xxx_mask)
1380                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1381
1382         /* load some data */
1383         n = comedi_buf_read_n_available(s->async);
1384         if (n == 0)
1385                 return 0;
1386
1387         n /= sizeof(short);
1388         if (n > board->ao_fifo_depth)
1389                 n = board->ao_fifo_depth;
1390
1391         ni_ao_fifo_load(dev, s, n);
1392
1393         return n;
1394 }
1395
1396 static void ni_ai_fifo_read(struct comedi_device *dev,
1397                             struct comedi_subdevice *s, int n)
1398 {
1399         const struct ni_board_struct *board = comedi_board(dev);
1400         struct ni_private *devpriv = dev->private;
1401         struct comedi_async *async = s->async;
1402         int i;
1403
1404         if (board->reg_type == ni_reg_611x) {
1405                 short data[2];
1406                 u32 dl;
1407
1408                 for (i = 0; i < n / 2; i++) {
1409                         dl = ni_readl(ADC_FIFO_Data_611x);
1410                         /* This may get the hi/lo data in the wrong order */
1411                         data[0] = (dl >> 16) & 0xffff;
1412                         data[1] = dl & 0xffff;
1413                         cfc_write_array_to_buffer(s, data, sizeof(data));
1414                 }
1415                 /* Check if there's a single sample stuck in the FIFO */
1416                 if (n % 2) {
1417                         dl = ni_readl(ADC_FIFO_Data_611x);
1418                         data[0] = dl & 0xffff;
1419                         cfc_write_to_buffer(s, data[0]);
1420                 }
1421         } else if (board->reg_type == ni_reg_6143) {
1422                 short data[2];
1423                 u32 dl;
1424
1425                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1426                 for (i = 0; i < n / 2; i++) {
1427                         dl = ni_readl(AIFIFO_Data_6143);
1428
1429                         data[0] = (dl >> 16) & 0xffff;
1430                         data[1] = dl & 0xffff;
1431                         cfc_write_array_to_buffer(s, data, sizeof(data));
1432                 }
1433                 if (n % 2) {
1434                         /* Assume there is a single sample stuck in the FIFO */
1435                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1436                         dl = ni_readl(AIFIFO_Data_6143);
1437                         data[0] = (dl >> 16) & 0xffff;
1438                         cfc_write_to_buffer(s, data[0]);
1439                 }
1440         } else {
1441                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1442                     sizeof(devpriv->ai_fifo_buffer[0])) {
1443                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1444                         async->events |= COMEDI_CB_ERROR;
1445                         return;
1446                 }
1447                 for (i = 0; i < n; i++) {
1448                         devpriv->ai_fifo_buffer[i] =
1449                             ni_readw(ADC_FIFO_Data_Register);
1450                 }
1451                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1452                                           n *
1453                                           sizeof(devpriv->ai_fifo_buffer[0]));
1454         }
1455 }
1456
1457 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1458 {
1459         const struct ni_board_struct *board = comedi_board(dev);
1460         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1461         int n;
1462
1463         n = board->ai_fifo_depth / 2;
1464
1465         ni_ai_fifo_read(dev, s, n);
1466 }
1467 #endif
1468
1469 #ifdef PCIDMA
1470 static int ni_ai_drain_dma(struct comedi_device *dev)
1471 {
1472         struct ni_private *devpriv = dev->private;
1473         int i;
1474         static const int timeout = 10000;
1475         unsigned long flags;
1476         int retval = 0;
1477
1478         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1479         if (devpriv->ai_mite_chan) {
1480                 for (i = 0; i < timeout; i++) {
1481                         if ((devpriv->stc_readw(dev,
1482                                                 AI_Status_1_Register) &
1483                              AI_FIFO_Empty_St)
1484                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1485                             0)
1486                                 break;
1487                         udelay(5);
1488                 }
1489                 if (i == timeout) {
1490                         printk("ni_mio_common: wait for dma drain timed out\n");
1491                         printk
1492                             ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1493                              mite_bytes_in_transit(devpriv->ai_mite_chan),
1494                              devpriv->stc_readw(dev, AI_Status_1_Register));
1495                         retval = -1;
1496                 }
1497         }
1498         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1499
1500         ni_sync_ai_dma(dev);
1501
1502         return retval;
1503 }
1504 #endif
1505 /*
1506    Empties the AI fifo
1507 */
1508 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1509 {
1510         const struct ni_board_struct *board = comedi_board(dev);
1511         struct ni_private *devpriv = dev->private;
1512         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1513         short data[2];
1514         u32 dl;
1515         short fifo_empty;
1516         int i;
1517
1518         if (board->reg_type == ni_reg_611x) {
1519                 while ((devpriv->stc_readw(dev,
1520                                            AI_Status_1_Register) &
1521                         AI_FIFO_Empty_St) == 0) {
1522                         dl = ni_readl(ADC_FIFO_Data_611x);
1523
1524                         /* This may get the hi/lo data in the wrong order */
1525                         data[0] = (dl >> 16);
1526                         data[1] = (dl & 0xffff);
1527                         cfc_write_array_to_buffer(s, data, sizeof(data));
1528                 }
1529         } else if (board->reg_type == ni_reg_6143) {
1530                 i = 0;
1531                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1532                         dl = ni_readl(AIFIFO_Data_6143);
1533
1534                         /* This may get the hi/lo data in the wrong order */
1535                         data[0] = (dl >> 16);
1536                         data[1] = (dl & 0xffff);
1537                         cfc_write_array_to_buffer(s, data, sizeof(data));
1538                         i += 2;
1539                 }
1540                 /*  Check if stranded sample is present */
1541                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1542                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1543                         dl = ni_readl(AIFIFO_Data_6143);
1544                         data[0] = (dl >> 16) & 0xffff;
1545                         cfc_write_to_buffer(s, data[0]);
1546                 }
1547
1548         } else {
1549                 fifo_empty =
1550                     devpriv->stc_readw(dev,
1551                                        AI_Status_1_Register) & AI_FIFO_Empty_St;
1552                 while (fifo_empty == 0) {
1553                         for (i = 0;
1554                              i <
1555                              sizeof(devpriv->ai_fifo_buffer) /
1556                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1557                                 fifo_empty =
1558                                     devpriv->stc_readw(dev,
1559                                                        AI_Status_1_Register) &
1560                                     AI_FIFO_Empty_St;
1561                                 if (fifo_empty)
1562                                         break;
1563                                 devpriv->ai_fifo_buffer[i] =
1564                                     ni_readw(ADC_FIFO_Data_Register);
1565                         }
1566                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1567                                                   i *
1568                                                   sizeof(devpriv->
1569                                                          ai_fifo_buffer[0]));
1570                 }
1571         }
1572 }
1573
1574 static void get_last_sample_611x(struct comedi_device *dev)
1575 {
1576         const struct ni_board_struct *board = comedi_board(dev);
1577         struct ni_private *devpriv __maybe_unused = dev->private;
1578         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1579         short data;
1580         u32 dl;
1581
1582         if (board->reg_type != ni_reg_611x)
1583                 return;
1584
1585         /* Check if there's a single sample stuck in the FIFO */
1586         if (ni_readb(XXX_Status) & 0x80) {
1587                 dl = ni_readl(ADC_FIFO_Data_611x);
1588                 data = (dl & 0xffff);
1589                 cfc_write_to_buffer(s, data);
1590         }
1591 }
1592
1593 static void get_last_sample_6143(struct comedi_device *dev)
1594 {
1595         const struct ni_board_struct *board = comedi_board(dev);
1596         struct ni_private *devpriv __maybe_unused = dev->private;
1597         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1598         short data;
1599         u32 dl;
1600
1601         if (board->reg_type != ni_reg_6143)
1602                 return;
1603
1604         /* Check if there's a single sample stuck in the FIFO */
1605         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1606                 ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1607                 dl = ni_readl(AIFIFO_Data_6143);
1608
1609                 /* This may get the hi/lo data in the wrong order */
1610                 data = (dl >> 16) & 0xffff;
1611                 cfc_write_to_buffer(s, data);
1612         }
1613 }
1614
1615 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1616                         void *data, unsigned int num_bytes,
1617                         unsigned int chan_index)
1618 {
1619         struct ni_private *devpriv = dev->private;
1620         struct comedi_async *async = s->async;
1621         unsigned int i;
1622         unsigned int length = num_bytes / bytes_per_sample(s);
1623         short *array = data;
1624         unsigned int *larray = data;
1625
1626         for (i = 0; i < length; i++) {
1627 #ifdef PCIDMA
1628                 if (s->subdev_flags & SDF_LSAMPL)
1629                         larray[i] = le32_to_cpu(larray[i]);
1630                 else
1631                         array[i] = le16_to_cpu(array[i]);
1632 #endif
1633                 if (s->subdev_flags & SDF_LSAMPL)
1634                         larray[i] += devpriv->ai_offset[chan_index];
1635                 else
1636                         array[i] += devpriv->ai_offset[chan_index];
1637                 chan_index++;
1638                 chan_index %= async->cmd.chanlist_len;
1639         }
1640 }
1641
1642 #ifdef PCIDMA
1643
1644 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1645 {
1646         const struct ni_board_struct *board = comedi_board(dev);
1647         struct ni_private *devpriv = dev->private;
1648         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1649         int retval;
1650         unsigned long flags;
1651
1652         retval = ni_request_ai_mite_channel(dev);
1653         if (retval)
1654                 return retval;
1655 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1656
1657         /* write alloc the entire buffer */
1658         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1659
1660         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1661         if (devpriv->ai_mite_chan == NULL) {
1662                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1663                 return -EIO;
1664         }
1665
1666         switch (board->reg_type) {
1667         case ni_reg_611x:
1668         case ni_reg_6143:
1669                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1670                 break;
1671         case ni_reg_628x:
1672                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1673                 break;
1674         default:
1675                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1676                 break;
1677         }
1678         /*start the MITE */
1679         mite_dma_arm(devpriv->ai_mite_chan);
1680         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1681
1682         return 0;
1683 }
1684
1685 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1686 {
1687         const struct ni_board_struct *board = comedi_board(dev);
1688         struct ni_private *devpriv = dev->private;
1689         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1690         int retval;
1691         unsigned long flags;
1692
1693         retval = ni_request_ao_mite_channel(dev);
1694         if (retval)
1695                 return retval;
1696
1697         /* read alloc the entire buffer */
1698         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1699
1700         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1701         if (devpriv->ao_mite_chan) {
1702                 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1703                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1704                 } else {
1705                         /* doing 32 instead of 16 bit wide transfers from memory
1706                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1707                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1708                 }
1709                 mite_dma_arm(devpriv->ao_mite_chan);
1710         } else
1711                 retval = -EIO;
1712         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1713
1714         return retval;
1715 }
1716
1717 #endif /*  PCIDMA */
1718
1719 /*
1720    used for both cancel ioctl and board initialization
1721
1722    this is pretty harsh for a cancel, but it works...
1723  */
1724
1725 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1726 {
1727         const struct ni_board_struct *board = comedi_board(dev);
1728         struct ni_private *devpriv = dev->private;
1729
1730         ni_release_ai_mite_channel(dev);
1731         /* ai configuration */
1732         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1733                             Joint_Reset_Register);
1734
1735         ni_set_bits(dev, Interrupt_A_Enable_Register,
1736                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1737                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1738                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1739                     AI_FIFO_Interrupt_Enable, 0);
1740
1741         ni_clear_ai_fifo(dev);
1742
1743         if (board->reg_type != ni_reg_6143)
1744                 ni_writeb(0, Misc_Command);
1745
1746         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1747         devpriv->stc_writew(dev,
1748                             AI_Start_Stop | AI_Mode_1_Reserved
1749                             /*| AI_Trigger_Once */ ,
1750                             AI_Mode_1_Register);
1751         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1752         /* generate FIFO interrupts on non-empty */
1753         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1754         if (board->reg_type == ni_reg_611x) {
1755                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1756                                     AI_SOC_Polarity |
1757                                     AI_LOCALMUX_CLK_Pulse_Width,
1758                                     AI_Personal_Register);
1759                 devpriv->stc_writew(dev,
1760                                     AI_SCAN_IN_PROG_Output_Select(3) |
1761                                     AI_EXTMUX_CLK_Output_Select(0) |
1762                                     AI_LOCALMUX_CLK_Output_Select(2) |
1763                                     AI_SC_TC_Output_Select(3) |
1764                                     AI_CONVERT_Output_Select
1765                                     (AI_CONVERT_Output_Enable_High),
1766                                     AI_Output_Control_Register);
1767         } else if (board->reg_type == ni_reg_6143) {
1768                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1769                                     AI_SOC_Polarity |
1770                                     AI_LOCALMUX_CLK_Pulse_Width,
1771                                     AI_Personal_Register);
1772                 devpriv->stc_writew(dev,
1773                                     AI_SCAN_IN_PROG_Output_Select(3) |
1774                                     AI_EXTMUX_CLK_Output_Select(0) |
1775                                     AI_LOCALMUX_CLK_Output_Select(2) |
1776                                     AI_SC_TC_Output_Select(3) |
1777                                     AI_CONVERT_Output_Select
1778                                     (AI_CONVERT_Output_Enable_Low),
1779                                     AI_Output_Control_Register);
1780         } else {
1781                 unsigned ai_output_control_bits;
1782                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1783                                     AI_SOC_Polarity |
1784                                     AI_CONVERT_Pulse_Width |
1785                                     AI_LOCALMUX_CLK_Pulse_Width,
1786                                     AI_Personal_Register);
1787                 ai_output_control_bits =
1788                     AI_SCAN_IN_PROG_Output_Select(3) |
1789                     AI_EXTMUX_CLK_Output_Select(0) |
1790                     AI_LOCALMUX_CLK_Output_Select(2) |
1791                     AI_SC_TC_Output_Select(3);
1792                 if (board->reg_type == ni_reg_622x)
1793                         ai_output_control_bits |=
1794                             AI_CONVERT_Output_Select
1795                             (AI_CONVERT_Output_Enable_High);
1796                 else
1797                         ai_output_control_bits |=
1798                             AI_CONVERT_Output_Select
1799                             (AI_CONVERT_Output_Enable_Low);
1800                 devpriv->stc_writew(dev, ai_output_control_bits,
1801                                     AI_Output_Control_Register);
1802         }
1803         /* the following registers should not be changed, because there
1804          * are no backup registers in devpriv.  If you want to change
1805          * any of these, add a backup register and other appropriate code:
1806          *      AI_Mode_1_Register
1807          *      AI_Mode_3_Register
1808          *      AI_Personal_Register
1809          *      AI_Output_Control_Register
1810          */
1811         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1812
1813         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1814
1815         return 0;
1816 }
1817
1818 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1819 {
1820         unsigned long flags;
1821         int count;
1822
1823         /*  lock to avoid race with interrupt handler */
1824         spin_lock_irqsave(&dev->spinlock, flags);
1825 #ifndef PCIDMA
1826         ni_handle_fifo_dregs(dev);
1827 #else
1828         ni_sync_ai_dma(dev);
1829 #endif
1830         count = s->async->buf_write_count - s->async->buf_read_count;
1831         spin_unlock_irqrestore(&dev->spinlock, flags);
1832
1833         return count;
1834 }
1835
1836 static int ni_ai_insn_read(struct comedi_device *dev,
1837                            struct comedi_subdevice *s, struct comedi_insn *insn,
1838                            unsigned int *data)
1839 {
1840         const struct ni_board_struct *board = comedi_board(dev);
1841         struct ni_private *devpriv = dev->private;
1842         int i, n;
1843         const unsigned int mask = (1 << board->adbits) - 1;
1844         unsigned signbits;
1845         unsigned short d;
1846         unsigned long dl;
1847
1848         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1849
1850         ni_clear_ai_fifo(dev);
1851
1852         signbits = devpriv->ai_offset[0];
1853         if (board->reg_type == ni_reg_611x) {
1854                 for (n = 0; n < num_adc_stages_611x; n++) {
1855                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1856                                             AI_Command_1_Register);
1857                         udelay(1);
1858                 }
1859                 for (n = 0; n < insn->n; n++) {
1860                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1861                                             AI_Command_1_Register);
1862                         /* The 611x has screwy 32-bit FIFOs. */
1863                         d = 0;
1864                         for (i = 0; i < NI_TIMEOUT; i++) {
1865                                 if (ni_readb(XXX_Status) & 0x80) {
1866                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1867                                             & 0xffff;
1868                                         break;
1869                                 }
1870                                 if (!(devpriv->stc_readw(dev,
1871                                                          AI_Status_1_Register) &
1872                                       AI_FIFO_Empty_St)) {
1873                                         d = ni_readl(ADC_FIFO_Data_611x) &
1874                                             0xffff;
1875                                         break;
1876                                 }
1877                         }
1878                         if (i == NI_TIMEOUT) {
1879                                 printk
1880                                     ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1881                                 return -ETIME;
1882                         }
1883                         d += signbits;
1884                         data[n] = d;
1885                 }
1886         } else if (board->reg_type == ni_reg_6143) {
1887                 for (n = 0; n < insn->n; n++) {
1888                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1889                                             AI_Command_1_Register);
1890
1891                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1892                         dl = 0;
1893                         for (i = 0; i < NI_TIMEOUT; i++) {
1894                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1895                                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1896                                         dl = ni_readl(AIFIFO_Data_6143);
1897                                         break;
1898                                 }
1899                         }
1900                         if (i == NI_TIMEOUT) {
1901                                 printk
1902                                     ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1903                                 return -ETIME;
1904                         }
1905                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1906                 }
1907         } else {
1908                 for (n = 0; n < insn->n; n++) {
1909                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1910                                             AI_Command_1_Register);
1911                         for (i = 0; i < NI_TIMEOUT; i++) {
1912                                 if (!(devpriv->stc_readw(dev,
1913                                                          AI_Status_1_Register) &
1914                                       AI_FIFO_Empty_St))
1915                                         break;
1916                         }
1917                         if (i == NI_TIMEOUT) {
1918                                 printk
1919                                     ("ni_mio_common: timeout in ni_ai_insn_read\n");
1920                                 return -ETIME;
1921                         }
1922                         if (board->reg_type & ni_reg_m_series_mask) {
1923                                 data[n] =
1924                                     ni_readl(M_Offset_AI_FIFO_Data) & mask;
1925                         } else {
1926                                 d = ni_readw(ADC_FIFO_Data_Register);
1927                                 d += signbits;  /* subtle: needs to be short addition */
1928                                 data[n] = d;
1929                         }
1930                 }
1931         }
1932         return insn->n;
1933 }
1934
1935 static void ni_prime_channelgain_list(struct comedi_device *dev)
1936 {
1937         struct ni_private *devpriv = dev->private;
1938         int i;
1939
1940         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1941         for (i = 0; i < NI_TIMEOUT; ++i) {
1942                 if (!(devpriv->stc_readw(dev,
1943                                          AI_Status_1_Register) &
1944                       AI_FIFO_Empty_St)) {
1945                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1946                         return;
1947                 }
1948                 udelay(1);
1949         }
1950         printk("ni_mio_common: timeout loading channel/gain list\n");
1951 }
1952
1953 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1954                                               unsigned int n_chan,
1955                                               unsigned int *list)
1956 {
1957         const struct ni_board_struct *board = comedi_board(dev);
1958         struct ni_private *devpriv = dev->private;
1959         unsigned int chan, range, aref;
1960         unsigned int i;
1961         unsigned offset;
1962         unsigned int dither;
1963         unsigned range_code;
1964
1965         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1966
1967 /* offset = 1 << (board->adbits - 1); */
1968         if ((list[0] & CR_ALT_SOURCE)) {
1969                 unsigned bypass_bits;
1970                 chan = CR_CHAN(list[0]);
1971                 range = CR_RANGE(list[0]);
1972                 range_code = ni_gainlkup[board->gainlkup][range];
1973                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1974                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1975                 bypass_bits |= chan;
1976                 bypass_bits |=
1977                     (devpriv->ai_calib_source) &
1978                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1979                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1980                      MSeries_AI_Bypass_Mode_Mux_Mask |
1981                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1982                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1983                 if (dither)
1984                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1985                 /*  don't use 2's complement encoding */
1986                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1987                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1988         } else {
1989                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1990         }
1991         offset = 0;
1992         for (i = 0; i < n_chan; i++) {
1993                 unsigned config_bits = 0;
1994                 chan = CR_CHAN(list[i]);
1995                 aref = CR_AREF(list[i]);
1996                 range = CR_RANGE(list[i]);
1997                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1998
1999                 range_code = ni_gainlkup[board->gainlkup][range];
2000                 devpriv->ai_offset[i] = offset;
2001                 switch (aref) {
2002                 case AREF_DIFF:
2003                         config_bits |=
2004                             MSeries_AI_Config_Channel_Type_Differential_Bits;
2005                         break;
2006                 case AREF_COMMON:
2007                         config_bits |=
2008                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2009                         break;
2010                 case AREF_GROUND:
2011                         config_bits |=
2012                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2013                         break;
2014                 case AREF_OTHER:
2015                         break;
2016                 }
2017                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2018                 config_bits |=
2019                     MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2020                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2021                 if (i == n_chan - 1)
2022                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2023                 if (dither)
2024                         config_bits |= MSeries_AI_Config_Dither_Bit;
2025                 /*  don't use 2's complement encoding */
2026                 config_bits |= MSeries_AI_Config_Polarity_Bit;
2027                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2028         }
2029         ni_prime_channelgain_list(dev);
2030 }
2031
2032 /*
2033  * Notes on the 6110 and 6111:
2034  * These boards a slightly different than the rest of the series, since
2035  * they have multiple A/D converters.
2036  * From the driver side, the configuration memory is a
2037  * little different.
2038  * Configuration Memory Low:
2039  *   bits 15-9: same
2040  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
2041  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
2042  *       1001 gain=0.1 (+/- 50)
2043  *       1010 0.2
2044  *       1011 0.1
2045  *       0001 1
2046  *       0010 2
2047  *       0011 5
2048  *       0100 10
2049  *       0101 20
2050  *       0110 50
2051  * Configuration Memory High:
2052  *   bits 12-14: Channel Type
2053  *       001 for differential
2054  *       000 for calibration
2055  *   bit 11: coupling  (this is not currently handled)
2056  *       1 AC coupling
2057  *       0 DC coupling
2058  *   bits 0-2: channel
2059  *       valid channels are 0-3
2060  */
2061 static void ni_load_channelgain_list(struct comedi_device *dev,
2062                                      unsigned int n_chan, unsigned int *list)
2063 {
2064         const struct ni_board_struct *board = comedi_board(dev);
2065         struct ni_private *devpriv = dev->private;
2066         unsigned int chan, range, aref;
2067         unsigned int i;
2068         unsigned int hi, lo;
2069         unsigned offset;
2070         unsigned int dither;
2071
2072         if (board->reg_type & ni_reg_m_series_mask) {
2073                 ni_m_series_load_channelgain_list(dev, n_chan, list);
2074                 return;
2075         }
2076         if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2077             && (board->reg_type != ni_reg_6143)) {
2078                 if (devpriv->changain_state
2079                     && devpriv->changain_spec == list[0]) {
2080                         /*  ready to go. */
2081                         return;
2082                 }
2083                 devpriv->changain_state = 1;
2084                 devpriv->changain_spec = list[0];
2085         } else {
2086                 devpriv->changain_state = 0;
2087         }
2088
2089         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2090
2091         /*  Set up Calibration mode if required */
2092         if (board->reg_type == ni_reg_6143) {
2093                 if ((list[0] & CR_ALT_SOURCE)
2094                     && !devpriv->ai_calib_source_enabled) {
2095                         /*  Strobe Relay enable bit */
2096                         ni_writew(devpriv->ai_calib_source |
2097                                   Calibration_Channel_6143_RelayOn,
2098                                   Calibration_Channel_6143);
2099                         ni_writew(devpriv->ai_calib_source,
2100                                   Calibration_Channel_6143);
2101                         devpriv->ai_calib_source_enabled = 1;
2102                         msleep_interruptible(100);      /*  Allow relays to change */
2103                 } else if (!(list[0] & CR_ALT_SOURCE)
2104                            && devpriv->ai_calib_source_enabled) {
2105                         /*  Strobe Relay disable bit */
2106                         ni_writew(devpriv->ai_calib_source |
2107                                   Calibration_Channel_6143_RelayOff,
2108                                   Calibration_Channel_6143);
2109                         ni_writew(devpriv->ai_calib_source,
2110                                   Calibration_Channel_6143);
2111                         devpriv->ai_calib_source_enabled = 0;
2112                         msleep_interruptible(100);      /*  Allow relays to change */
2113                 }
2114         }
2115
2116         offset = 1 << (board->adbits - 1);
2117         for (i = 0; i < n_chan; i++) {
2118                 if ((board->reg_type != ni_reg_6143)
2119                     && (list[i] & CR_ALT_SOURCE)) {
2120                         chan = devpriv->ai_calib_source;
2121                 } else {
2122                         chan = CR_CHAN(list[i]);
2123                 }
2124                 aref = CR_AREF(list[i]);
2125                 range = CR_RANGE(list[i]);
2126                 dither = ((list[i] & CR_ALT_FILTER) != 0);
2127
2128                 /* fix the external/internal range differences */
2129                 range = ni_gainlkup[board->gainlkup][range];
2130                 if (board->reg_type == ni_reg_611x)
2131                         devpriv->ai_offset[i] = offset;
2132                 else
2133                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2134
2135                 hi = 0;
2136                 if ((list[i] & CR_ALT_SOURCE)) {
2137                         if (board->reg_type == ni_reg_611x)
2138                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2139                                           Calibration_Channel_Select_611x);
2140                 } else {
2141                         if (board->reg_type == ni_reg_611x)
2142                                 aref = AREF_DIFF;
2143                         else if (board->reg_type == ni_reg_6143)
2144                                 aref = AREF_OTHER;
2145                         switch (aref) {
2146                         case AREF_DIFF:
2147                                 hi |= AI_DIFFERENTIAL;
2148                                 break;
2149                         case AREF_COMMON:
2150                                 hi |= AI_COMMON;
2151                                 break;
2152                         case AREF_GROUND:
2153                                 hi |= AI_GROUND;
2154                                 break;
2155                         case AREF_OTHER:
2156                                 break;
2157                         }
2158                 }
2159                 hi |= AI_CONFIG_CHANNEL(chan);
2160
2161                 ni_writew(hi, Configuration_Memory_High);
2162
2163                 if (board->reg_type != ni_reg_6143) {
2164                         lo = range;
2165                         if (i == n_chan - 1)
2166                                 lo |= AI_LAST_CHANNEL;
2167                         if (dither)
2168                                 lo |= AI_DITHER;
2169
2170                         ni_writew(lo, Configuration_Memory_Low);
2171                 }
2172         }
2173
2174         /* prime the channel/gain list */
2175         if ((board->reg_type != ni_reg_611x)
2176             && (board->reg_type != ni_reg_6143)) {
2177                 ni_prime_channelgain_list(dev);
2178         }
2179 }
2180
2181 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2182                           int round_mode)
2183 {
2184         struct ni_private *devpriv = dev->private;
2185         int divider;
2186
2187         switch (round_mode) {
2188         case TRIG_ROUND_NEAREST:
2189         default:
2190                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2191                 break;
2192         case TRIG_ROUND_DOWN:
2193                 divider = (nanosec) / devpriv->clock_ns;
2194                 break;
2195         case TRIG_ROUND_UP:
2196                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2197                 break;
2198         }
2199         return divider - 1;
2200 }
2201
2202 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2203 {
2204         struct ni_private *devpriv = dev->private;
2205
2206         return devpriv->clock_ns * (timer + 1);
2207 }
2208
2209 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2210                                          unsigned num_channels)
2211 {
2212         const struct ni_board_struct *board = comedi_board(dev);
2213
2214         switch (board->reg_type) {
2215         case ni_reg_611x:
2216         case ni_reg_6143:
2217                 /*  simultaneously-sampled inputs */
2218                 return board->ai_speed;
2219                 break;
2220         default:
2221                 /*  multiplexed inputs */
2222                 break;
2223         }
2224         return board->ai_speed * num_channels;
2225 }
2226
2227 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2228                          struct comedi_cmd *cmd)
2229 {
2230         const struct ni_board_struct *board = comedi_board(dev);
2231         struct ni_private *devpriv = dev->private;
2232         int err = 0;
2233         int tmp;
2234         unsigned int sources;
2235
2236         /* Step 1 : check if triggers are trivially valid */
2237
2238         if ((cmd->flags & CMDF_WRITE))
2239                 cmd->flags &= ~CMDF_WRITE;
2240
2241         err |= cfc_check_trigger_src(&cmd->start_src,
2242                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2243         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2244                                         TRIG_TIMER | TRIG_EXT);
2245
2246         sources = TRIG_TIMER | TRIG_EXT;
2247         if (board->reg_type == ni_reg_611x ||
2248             board->reg_type == ni_reg_6143)
2249                 sources |= TRIG_NOW;
2250         err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2251
2252         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2253         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2254
2255         if (err)
2256                 return 1;
2257
2258         /* Step 2a : make sure trigger sources are unique */
2259
2260         err |= cfc_check_trigger_is_unique(cmd->start_src);
2261         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2262         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2263         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2264
2265         /* Step 2b : and mutually compatible */
2266
2267         if (err)
2268                 return 2;
2269
2270         /* Step 3: check if arguments are trivially valid */
2271
2272         if (cmd->start_src == TRIG_EXT) {
2273                 /* external trigger */
2274                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2275
2276                 if (tmp > 16)
2277                         tmp = 16;
2278                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2279                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2280         } else {
2281                 /* true for both TRIG_NOW and TRIG_INT */
2282                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2283         }
2284
2285         if (cmd->scan_begin_src == TRIG_TIMER) {
2286                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2287                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2288                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2289                                                  devpriv->clock_ns * 0xffffff);
2290         } else if (cmd->scan_begin_src == TRIG_EXT) {
2291                 /* external trigger */
2292                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2293
2294                 if (tmp > 16)
2295                         tmp = 16;
2296                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2297                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2298         } else {                /* TRIG_OTHER */
2299                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2300         }
2301
2302         if (cmd->convert_src == TRIG_TIMER) {
2303                 if ((board->reg_type == ni_reg_611x)
2304                     || (board->reg_type == ni_reg_6143)) {
2305                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2306                 } else {
2307                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2308                                                          board->ai_speed);
2309                         err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2310                                                 devpriv->clock_ns * 0xffff);
2311                 }
2312         } else if (cmd->convert_src == TRIG_EXT) {
2313                 /* external trigger */
2314                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2315
2316                 if (tmp > 16)
2317                         tmp = 16;
2318                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2319                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2320         } else if (cmd->convert_src == TRIG_NOW) {
2321                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2322         }
2323
2324         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2325
2326         if (cmd->stop_src == TRIG_COUNT) {
2327                 unsigned int max_count = 0x01000000;
2328
2329                 if (board->reg_type == ni_reg_611x)
2330                         max_count -= num_adc_stages_611x;
2331                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2332                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2333         } else {
2334                 /* TRIG_NONE */
2335                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2336         }
2337
2338         if (err)
2339                 return 3;
2340
2341         /* step 4: fix up any arguments */
2342
2343         if (cmd->scan_begin_src == TRIG_TIMER) {
2344                 tmp = cmd->scan_begin_arg;
2345                 cmd->scan_begin_arg =
2346                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2347                                                        cmd->scan_begin_arg,
2348                                                        cmd->
2349                                                        flags &
2350                                                        TRIG_ROUND_MASK));
2351                 if (tmp != cmd->scan_begin_arg)
2352                         err++;
2353         }
2354         if (cmd->convert_src == TRIG_TIMER) {
2355                 if ((board->reg_type != ni_reg_611x)
2356                     && (board->reg_type != ni_reg_6143)) {
2357                         tmp = cmd->convert_arg;
2358                         cmd->convert_arg =
2359                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2360                                                                cmd->convert_arg,
2361                                                                cmd->
2362                                                                flags &
2363                                                                TRIG_ROUND_MASK));
2364                         if (tmp != cmd->convert_arg)
2365                                 err++;
2366                         if (cmd->scan_begin_src == TRIG_TIMER &&
2367                             cmd->scan_begin_arg <
2368                             cmd->convert_arg * cmd->scan_end_arg) {
2369                                 cmd->scan_begin_arg =
2370                                     cmd->convert_arg * cmd->scan_end_arg;
2371                                 err++;
2372                         }
2373                 }
2374         }
2375
2376         if (err)
2377                 return 4;
2378
2379         return 0;
2380 }
2381
2382 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2383 {
2384         const struct ni_board_struct *board = comedi_board(dev);
2385         struct ni_private *devpriv = dev->private;
2386         const struct comedi_cmd *cmd = &s->async->cmd;
2387         int timer;
2388         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2389         int mode2 = 0;
2390         int start_stop_select = 0;
2391         unsigned int stop_count;
2392         int interrupt_a_enable = 0;
2393
2394         MDPRINTK("ni_ai_cmd\n");
2395         if (dev->irq == 0) {
2396                 comedi_error(dev, "cannot run command without an irq");
2397                 return -EIO;
2398         }
2399         ni_clear_ai_fifo(dev);
2400
2401         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2402
2403         /* start configuration */
2404         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2405
2406         /* disable analog triggering for now, since it
2407          * interferes with the use of pfi0 */
2408         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2409         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2410                             Analog_Trigger_Etc_Register);
2411
2412         switch (cmd->start_src) {
2413         case TRIG_INT:
2414         case TRIG_NOW:
2415                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2416                                     AI_START1_Sync | AI_START1_Edge |
2417                                     AI_START1_Select(0),
2418                                     AI_Trigger_Select_Register);
2419                 break;
2420         case TRIG_EXT:
2421                 {
2422                         int chan = CR_CHAN(cmd->start_arg);
2423                         unsigned int bits = AI_START2_Select(0) |
2424                             AI_START1_Sync | AI_START1_Select(chan + 1);
2425
2426                         if (cmd->start_arg & CR_INVERT)
2427                                 bits |= AI_START1_Polarity;
2428                         if (cmd->start_arg & CR_EDGE)
2429                                 bits |= AI_START1_Edge;
2430                         devpriv->stc_writew(dev, bits,
2431                                             AI_Trigger_Select_Register);
2432                         break;
2433                 }
2434         }
2435
2436         mode2 &= ~AI_Pre_Trigger;
2437         mode2 &= ~AI_SC_Initial_Load_Source;
2438         mode2 &= ~AI_SC_Reload_Mode;
2439         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2440
2441         if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2442             || (board->reg_type == ni_reg_6143)) {
2443                 start_stop_select |= AI_STOP_Polarity;
2444                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2445                 start_stop_select |= AI_STOP_Sync;
2446         } else {
2447                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2448         }
2449         devpriv->stc_writew(dev, start_stop_select,
2450                             AI_START_STOP_Select_Register);
2451
2452         devpriv->ai_cmd2 = 0;
2453         switch (cmd->stop_src) {
2454         case TRIG_COUNT:
2455                 stop_count = cmd->stop_arg - 1;
2456
2457                 if (board->reg_type == ni_reg_611x) {
2458                         /*  have to take 3 stage adc pipeline into account */
2459                         stop_count += num_adc_stages_611x;
2460                 }
2461                 /* stage number of scans */
2462                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2463
2464                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2465                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2466                 /* load SC (Scan Count) */
2467                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2468
2469                 devpriv->ai_continuous = 0;
2470                 if (stop_count == 0) {
2471                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2472                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2473                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2474                         if (cmd->chanlist_len > 1)
2475                                 start_stop_select |=
2476                                     AI_STOP_Polarity | AI_STOP_Edge;
2477                 }
2478                 break;
2479         case TRIG_NONE:
2480                 /* stage number of scans */
2481                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2482
2483                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2484                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2485
2486                 /* load SC (Scan Count) */
2487                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2488
2489                 devpriv->ai_continuous = 1;
2490
2491                 break;
2492         }
2493
2494         switch (cmd->scan_begin_src) {
2495         case TRIG_TIMER:
2496                 /*
2497                    stop bits for non 611x boards
2498                    AI_SI_Special_Trigger_Delay=0
2499                    AI_Pre_Trigger=0
2500                    AI_START_STOP_Select_Register:
2501                    AI_START_Polarity=0 (?)      rising edge
2502                    AI_START_Edge=1              edge triggered
2503                    AI_START_Sync=1 (?)
2504                    AI_START_Select=0            SI_TC
2505                    AI_STOP_Polarity=0           rising edge
2506                    AI_STOP_Edge=0               level
2507                    AI_STOP_Sync=1
2508                    AI_STOP_Select=19            external pin (configuration mem)
2509                  */
2510                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2511                 devpriv->stc_writew(dev, start_stop_select,
2512                                     AI_START_STOP_Select_Register);
2513
2514                 mode2 |= AI_SI_Reload_Mode(0);
2515                 /* AI_SI_Initial_Load_Source=A */
2516                 mode2 &= ~AI_SI_Initial_Load_Source;
2517                 /* mode2 |= AI_SC_Reload_Mode; */
2518                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2519
2520                 /* load SI */
2521                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2522                                        TRIG_ROUND_NEAREST);
2523                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2524                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2525                 break;
2526         case TRIG_EXT:
2527                 if (cmd->scan_begin_arg & CR_EDGE)
2528                         start_stop_select |= AI_START_Edge;
2529                 /* AI_START_Polarity==1 is falling edge */
2530                 if (cmd->scan_begin_arg & CR_INVERT)
2531                         start_stop_select |= AI_START_Polarity;
2532                 if (cmd->scan_begin_src != cmd->convert_src ||
2533                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2534                     (cmd->convert_arg & ~CR_EDGE))
2535                         start_stop_select |= AI_START_Sync;
2536                 start_stop_select |=
2537                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2538                 devpriv->stc_writew(dev, start_stop_select,
2539                                     AI_START_STOP_Select_Register);
2540                 break;
2541         }
2542
2543         switch (cmd->convert_src) {
2544         case TRIG_TIMER:
2545         case TRIG_NOW:
2546                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2547                         timer = 1;
2548                 else
2549                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2550                                                TRIG_ROUND_NEAREST);
2551                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2552                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2553
2554                 /* AI_SI2_Reload_Mode = alternate */
2555                 /* AI_SI2_Initial_Load_Source = A */
2556                 mode2 &= ~AI_SI2_Initial_Load_Source;
2557                 mode2 |= AI_SI2_Reload_Mode;
2558                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2559
2560                 /* AI_SI2_Load */
2561                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2562
2563                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2564                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2565
2566                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2567                 break;
2568         case TRIG_EXT:
2569                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2570                 if ((cmd->convert_arg & CR_INVERT) == 0)
2571                         mode1 |= AI_CONVERT_Source_Polarity;
2572                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2573
2574                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2575                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2576
2577                 break;
2578         }
2579
2580         if (dev->irq) {
2581
2582                 /* interrupt on FIFO, errors, SC_TC */
2583                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2584                     AI_SC_TC_Interrupt_Enable;
2585
2586 #ifndef PCIDMA
2587                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2588 #endif
2589
2590                 if (cmd->flags & TRIG_WAKE_EOS
2591                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2592                         /* wake on end-of-scan */
2593                         devpriv->aimode = AIMODE_SCAN;
2594                 } else {
2595                         devpriv->aimode = AIMODE_HALF_FULL;
2596                 }
2597
2598                 switch (devpriv->aimode) {
2599                 case AIMODE_HALF_FULL:
2600                         /*generate FIFO interrupts and DMA requests on half-full */
2601 #ifdef PCIDMA
2602                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2603                                             AI_Mode_3_Register);
2604 #else
2605                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2606                                             AI_Mode_3_Register);
2607 #endif
2608                         break;
2609                 case AIMODE_SAMPLE:
2610                         /*generate FIFO interrupts on non-empty */
2611                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2612                                             AI_Mode_3_Register);
2613                         break;
2614                 case AIMODE_SCAN:
2615 #ifdef PCIDMA
2616                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2617                                             AI_Mode_3_Register);
2618 #else
2619                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2620                                             AI_Mode_3_Register);
2621 #endif
2622                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2623                         break;
2624                 default:
2625                         break;
2626                 }
2627
2628                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2629
2630                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2631                             interrupt_a_enable, 1);
2632
2633                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2634                          devpriv->int_a_enable_reg);
2635         } else {
2636                 /* interrupt on nothing */
2637                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2638
2639                 /* XXX start polling if necessary */
2640                 MDPRINTK("interrupting on nothing\n");
2641         }
2642
2643         /* end configuration */
2644         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2645
2646         switch (cmd->scan_begin_src) {
2647         case TRIG_TIMER:
2648                 devpriv->stc_writew(dev,
2649                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2650                                     AI_SC_Arm, AI_Command_1_Register);
2651                 break;
2652         case TRIG_EXT:
2653                 /* XXX AI_SI_Arm? */
2654                 devpriv->stc_writew(dev,
2655                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2656                                     AI_SC_Arm, AI_Command_1_Register);
2657                 break;
2658         }
2659
2660 #ifdef PCIDMA
2661         {
2662                 int retval = ni_ai_setup_MITE_dma(dev);
2663                 if (retval)
2664                         return retval;
2665         }
2666         /* mite_dump_regs(devpriv->mite); */
2667 #endif
2668
2669         switch (cmd->start_src) {
2670         case TRIG_NOW:
2671                 /* AI_START1_Pulse */
2672                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2673                                     AI_Command_2_Register);
2674                 s->async->inttrig = NULL;
2675                 break;
2676         case TRIG_EXT:
2677                 s->async->inttrig = NULL;
2678                 break;
2679         case TRIG_INT:
2680                 s->async->inttrig = &ni_ai_inttrig;
2681                 break;
2682         }
2683
2684         MDPRINTK("exit ni_ai_cmd\n");
2685
2686         return 0;
2687 }
2688
2689 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2690                          unsigned int trignum)
2691 {
2692         struct ni_private *devpriv = dev->private;
2693
2694         if (trignum != 0)
2695                 return -EINVAL;
2696
2697         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2698                             AI_Command_2_Register);
2699         s->async->inttrig = NULL;
2700
2701         return 1;
2702 }
2703
2704 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2705                                     struct comedi_subdevice *s,
2706                                     struct comedi_insn *insn,
2707                                     unsigned int *data);
2708
2709 static int ni_ai_insn_config(struct comedi_device *dev,
2710                              struct comedi_subdevice *s,
2711                              struct comedi_insn *insn, unsigned int *data)
2712 {
2713         const struct ni_board_struct *board = comedi_board(dev);
2714         struct ni_private *devpriv = dev->private;
2715
2716         if (insn->n < 1)
2717                 return -EINVAL;
2718
2719         switch (data[0]) {
2720         case INSN_CONFIG_ANALOG_TRIG:
2721                 return ni_ai_config_analog_trig(dev, s, insn, data);
2722         case INSN_CONFIG_ALT_SOURCE:
2723                 if (board->reg_type & ni_reg_m_series_mask) {
2724                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2725                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2726                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2727                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2728                                 return -EINVAL;
2729                         }
2730                         devpriv->ai_calib_source = data[1];
2731                 } else if (board->reg_type == ni_reg_6143) {
2732                         unsigned int calib_source;
2733
2734                         calib_source = data[1] & 0xf;
2735
2736                         if (calib_source > 0xF)
2737                                 return -EINVAL;
2738
2739                         devpriv->ai_calib_source = calib_source;
2740                         ni_writew(calib_source, Calibration_Channel_6143);
2741                 } else {
2742                         unsigned int calib_source;
2743                         unsigned int calib_source_adjust;
2744
2745                         calib_source = data[1] & 0xf;
2746                         calib_source_adjust = (data[1] >> 4) & 0xff;
2747
2748                         if (calib_source >= 8)
2749                                 return -EINVAL;
2750                         devpriv->ai_calib_source = calib_source;
2751                         if (board->reg_type == ni_reg_611x) {
2752                                 ni_writeb(calib_source_adjust,
2753                                           Cal_Gain_Select_611x);
2754                         }
2755                 }
2756                 return 2;
2757         default:
2758                 break;
2759         }
2760
2761         return -EINVAL;
2762 }
2763
2764 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2765                                     struct comedi_subdevice *s,
2766                                     struct comedi_insn *insn,
2767                                     unsigned int *data)
2768 {
2769         const struct ni_board_struct *board = comedi_board(dev);
2770         struct ni_private *devpriv = dev->private;
2771         unsigned int a, b, modebits;
2772         int err = 0;
2773
2774         /* data[1] is flags
2775          * data[2] is analog line
2776          * data[3] is set level
2777          * data[4] is reset level */
2778         if (!board->has_analog_trig)
2779                 return -EINVAL;
2780         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2781                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2782                 err++;
2783         }
2784         if (data[2] >= board->n_adchan) {
2785                 data[2] = board->n_adchan - 1;
2786                 err++;
2787         }
2788         if (data[3] > 255) {    /* a */
2789                 data[3] = 255;
2790                 err++;
2791         }
2792         if (data[4] > 255) {    /* b */
2793                 data[4] = 255;
2794                 err++;
2795         }
2796         /*
2797          * 00 ignore
2798          * 01 set
2799          * 10 reset
2800          *
2801          * modes:
2802          *   1 level:                    +b-   +a-
2803          *     high mode                00 00 01 10
2804          *     low mode                 00 00 10 01
2805          *   2 level: (a<b)
2806          *     hysteresis low mode      10 00 00 01
2807          *     hysteresis high mode     01 00 00 10
2808          *     middle mode              10 01 01 10
2809          */
2810
2811         a = data[3];
2812         b = data[4];
2813         modebits = data[1] & 0xff;
2814         if (modebits & 0xf0) {
2815                 /* two level mode */
2816                 if (b < a) {
2817                         /* swap order */
2818                         a = data[4];
2819                         b = data[3];
2820                         modebits =
2821                             ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2822                 }
2823                 devpriv->atrig_low = a;
2824                 devpriv->atrig_high = b;
2825                 switch (modebits) {
2826                 case 0x81:      /* low hysteresis mode */
2827                         devpriv->atrig_mode = 6;
2828                         break;
2829                 case 0x42:      /* high hysteresis mode */
2830                         devpriv->atrig_mode = 3;
2831                         break;
2832                 case 0x96:      /* middle window mode */
2833                         devpriv->atrig_mode = 2;
2834                         break;
2835                 default:
2836                         data[1] &= ~0xff;
2837                         err++;
2838                 }
2839         } else {
2840                 /* one level mode */
2841                 if (b != 0) {
2842                         data[4] = 0;
2843                         err++;
2844                 }
2845                 switch (modebits) {
2846                 case 0x06:      /* high window mode */
2847                         devpriv->atrig_high = a;
2848                         devpriv->atrig_mode = 0;
2849                         break;
2850                 case 0x09:      /* low window mode */
2851                         devpriv->atrig_low = a;
2852                         devpriv->atrig_mode = 1;
2853                         break;
2854                 default:
2855                         data[1] &= ~0xff;
2856                         err++;
2857                 }
2858         }
2859         if (err)
2860                 return -EAGAIN;
2861         return 5;
2862 }
2863
2864 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2865 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2866                         void *data, unsigned int num_bytes,
2867                         unsigned int chan_index)
2868 {
2869         const struct ni_board_struct *board = comedi_board(dev);
2870         struct comedi_async *async = s->async;
2871         unsigned int range;
2872         unsigned int i;
2873         unsigned int offset;
2874         unsigned int length = num_bytes / sizeof(short);
2875         short *array = data;
2876
2877         offset = 1 << (board->aobits - 1);
2878         for (i = 0; i < length; i++) {
2879                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2880                 if (board->ao_unipolar == 0 || (range & 1) == 0)
2881                         array[i] -= offset;
2882 #ifdef PCIDMA
2883                 array[i] = cpu_to_le16(array[i]);
2884 #endif
2885                 chan_index++;
2886                 chan_index %= async->cmd.chanlist_len;
2887         }
2888 }
2889
2890 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2891                                           struct comedi_subdevice *s,
2892                                           unsigned int chanspec[],
2893                                           unsigned int n_chans, int timed)
2894 {
2895         const struct ni_board_struct *board = comedi_board(dev);
2896         struct ni_private *devpriv = dev->private;
2897         unsigned int range;
2898         unsigned int chan;
2899         unsigned int conf;
2900         int i;
2901         int invert = 0;
2902
2903         if (timed) {
2904                 for (i = 0; i < board->n_aochan; ++i) {
2905                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2906                         ni_writeb(devpriv->ao_conf[i],
2907                                   M_Offset_AO_Config_Bank(i));
2908                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2909                 }
2910         }
2911         for (i = 0; i < n_chans; i++) {
2912                 const struct comedi_krange *krange;
2913                 chan = CR_CHAN(chanspec[i]);
2914                 range = CR_RANGE(chanspec[i]);
2915                 krange = s->range_table->range + range;
2916                 invert = 0;
2917                 conf = 0;
2918                 switch (krange->max - krange->min) {
2919                 case 20000000:
2920                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2921                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2922                         break;
2923                 case 10000000:
2924                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2925                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2926                         break;
2927                 case 4000000:
2928                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2929                         ni_writeb(MSeries_Attenuate_x5_Bit,
2930                                   M_Offset_AO_Reference_Attenuation(chan));
2931                         break;
2932                 case 2000000:
2933                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2934                         ni_writeb(MSeries_Attenuate_x5_Bit,
2935                                   M_Offset_AO_Reference_Attenuation(chan));
2936                         break;
2937                 default:
2938                         printk("%s: bug! unhandled ao reference voltage\n",
2939                                __func__);
2940                         break;
2941                 }
2942                 switch (krange->max + krange->min) {
2943                 case 0:
2944                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2945                         break;
2946                 case 10000000:
2947                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2948                         break;
2949                 default:
2950                         printk("%s: bug! unhandled ao offset voltage\n",
2951                                __func__);
2952                         break;
2953                 }
2954                 if (timed)
2955                         conf |= MSeries_AO_Update_Timed_Bit;
2956                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2957                 devpriv->ao_conf[chan] = conf;
2958                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2959         }
2960         return invert;
2961 }
2962
2963 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2964                                      struct comedi_subdevice *s,
2965                                      unsigned int chanspec[],
2966                                      unsigned int n_chans)
2967 {
2968         const struct ni_board_struct *board = comedi_board(dev);
2969         struct ni_private *devpriv = dev->private;
2970         unsigned int range;
2971         unsigned int chan;
2972         unsigned int conf;
2973         int i;
2974         int invert = 0;
2975
2976         for (i = 0; i < n_chans; i++) {
2977                 chan = CR_CHAN(chanspec[i]);
2978                 range = CR_RANGE(chanspec[i]);
2979                 conf = AO_Channel(chan);
2980
2981                 if (board->ao_unipolar) {
2982                         if ((range & 1) == 0) {
2983                                 conf |= AO_Bipolar;
2984                                 invert = (1 << (board->aobits - 1));
2985                         } else {
2986                                 invert = 0;
2987                         }
2988                         if (range & 2)
2989                                 conf |= AO_Ext_Ref;
2990                 } else {
2991                         conf |= AO_Bipolar;
2992                         invert = (1 << (board->aobits - 1));
2993                 }
2994
2995                 /* not all boards can deglitch, but this shouldn't hurt */
2996                 if (chanspec[i] & CR_DEGLITCH)
2997                         conf |= AO_Deglitch;
2998
2999                 /* analog reference */
3000                 /* AREF_OTHER connects AO ground to AI ground, i think */
3001                 conf |= (CR_AREF(chanspec[i]) ==
3002                          AREF_OTHER) ? AO_Ground_Ref : 0;
3003
3004                 ni_writew(conf, AO_Configuration);
3005                 devpriv->ao_conf[chan] = conf;
3006         }
3007         return invert;
3008 }
3009
3010 static int ni_ao_config_chanlist(struct comedi_device *dev,
3011                                  struct comedi_subdevice *s,
3012                                  unsigned int chanspec[], unsigned int n_chans,
3013                                  int timed)
3014 {
3015         const struct ni_board_struct *board = comedi_board(dev);
3016
3017         if (board->reg_type & ni_reg_m_series_mask)
3018                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3019                                                       timed);
3020         else
3021                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3022 }
3023
3024 static int ni_ao_insn_read(struct comedi_device *dev,
3025                            struct comedi_subdevice *s, struct comedi_insn *insn,
3026                            unsigned int *data)
3027 {
3028         struct ni_private *devpriv = dev->private;
3029
3030         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3031
3032         return 1;
3033 }
3034
3035 static int ni_ao_insn_write(struct comedi_device *dev,
3036                             struct comedi_subdevice *s,
3037                             struct comedi_insn *insn, unsigned int *data)
3038 {
3039         const struct ni_board_struct *board = comedi_board(dev);
3040         struct ni_private *devpriv = dev->private;
3041         unsigned int chan = CR_CHAN(insn->chanspec);
3042         unsigned int invert;
3043
3044         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3045
3046         devpriv->ao[chan] = data[0];
3047
3048         if (board->reg_type & ni_reg_m_series_mask) {
3049                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3050         } else
3051                 ni_writew(data[0] ^ invert,
3052                           (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3053
3054         return 1;
3055 }
3056
3057 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3058                                  struct comedi_subdevice *s,
3059                                  struct comedi_insn *insn, unsigned int *data)
3060 {
3061         const struct ni_board_struct *board = comedi_board(dev);
3062         struct ni_private *devpriv = dev->private;
3063         unsigned int chan = CR_CHAN(insn->chanspec);
3064         unsigned int invert;
3065
3066         ao_win_out(1 << chan, AO_Immediate_671x);
3067         invert = 1 << (board->aobits - 1);
3068
3069         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3070
3071         devpriv->ao[chan] = data[0];
3072         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3073
3074         return 1;
3075 }
3076
3077 static int ni_ao_insn_config(struct comedi_device *dev,
3078                              struct comedi_subdevice *s,
3079                              struct comedi_insn *insn, unsigned int *data)
3080 {
3081         const struct ni_board_struct *board = comedi_board(dev);
3082         struct ni_private *devpriv = dev->private;
3083
3084         switch (data[0]) {
3085         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3086                 switch (data[1]) {
3087                 case COMEDI_OUTPUT:
3088                         data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3089                         if (devpriv->mite)
3090                                 data[2] += devpriv->mite->fifo_size;
3091                         break;
3092                 case COMEDI_INPUT:
3093                         data[2] = 0;
3094                         break;
3095                 default:
3096                         return -EINVAL;
3097                         break;
3098                 }
3099                 return 0;
3100         default:
3101                 break;
3102         }
3103
3104         return -EINVAL;
3105 }
3106
3107 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3108                          unsigned int trignum)
3109 {
3110         const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3111         struct ni_private *devpriv = dev->private;
3112         int ret;
3113         int interrupt_b_bits;
3114         int i;
3115         static const int timeout = 1000;
3116
3117         if (trignum != 0)
3118                 return -EINVAL;
3119
3120         /* Null trig at beginning prevent ao start trigger from executing more than
3121            once per command (and doing things like trying to allocate the ao dma channel
3122            multiple times) */
3123         s->async->inttrig = NULL;
3124
3125         ni_set_bits(dev, Interrupt_B_Enable_Register,
3126                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3127         interrupt_b_bits = AO_Error_Interrupt_Enable;
3128 #ifdef PCIDMA
3129         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3130         if (board->reg_type & ni_reg_6xxx_mask)
3131                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3132         ret = ni_ao_setup_MITE_dma(dev);
3133         if (ret)
3134                 return ret;
3135         ret = ni_ao_wait_for_dma_load(dev);
3136         if (ret < 0)
3137                 return ret;
3138 #else
3139         ret = ni_ao_prep_fifo(dev, s);
3140         if (ret == 0)
3141                 return -EPIPE;
3142
3143         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3144 #endif
3145
3146         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3147                             AO_Mode_3_Register);
3148         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3149         /* wait for DACs to be loaded */
3150         for (i = 0; i < timeout; i++) {
3151                 udelay(1);
3152                 if ((devpriv->stc_readw(dev,
3153                                         Joint_Status_2_Register) &
3154                      AO_TMRDACWRs_In_Progress_St) == 0)
3155                         break;
3156         }
3157         if (i == timeout) {
3158                 comedi_error(dev,
3159                              "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3160                 return -EIO;
3161         }
3162         /*  stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3163         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3164                             Interrupt_B_Ack_Register);
3165
3166         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3167
3168         devpriv->stc_writew(dev,
3169                             devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3170                             | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3171                             AO_Command_1_Register);
3172
3173         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3174                             AO_Command_2_Register);
3175
3176         return 0;
3177 }
3178
3179 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3180 {
3181         const struct ni_board_struct *board = comedi_board(dev);
3182         struct ni_private *devpriv = dev->private;
3183         const struct comedi_cmd *cmd = &s->async->cmd;
3184         int bits;
3185         int i;
3186         unsigned trigvar;
3187
3188         if (dev->irq == 0) {
3189                 comedi_error(dev, "cannot run command without an irq");
3190                 return -EIO;
3191         }
3192
3193         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3194
3195         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3196
3197         if (board->reg_type & ni_reg_6xxx_mask) {
3198                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3199
3200                 bits = 0;
3201                 for (i = 0; i < cmd->chanlist_len; i++) {
3202                         int chan;
3203
3204                         chan = CR_CHAN(cmd->chanlist[i]);
3205                         bits |= 1 << chan;
3206                         ao_win_out(chan, AO_Waveform_Generation_611x);
3207                 }
3208                 ao_win_out(bits, AO_Timed_611x);
3209         }
3210
3211         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3212
3213         if (cmd->stop_src == TRIG_NONE) {
3214                 devpriv->ao_mode1 |= AO_Continuous;
3215                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3216         } else {
3217                 devpriv->ao_mode1 &= ~AO_Continuous;
3218                 devpriv->ao_mode1 |= AO_Trigger_Once;
3219         }
3220         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3221         switch (cmd->start_src) {
3222         case TRIG_INT:
3223         case TRIG_NOW:
3224                 devpriv->ao_trigger_select &=
3225                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3226                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3227                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3228                                     AO_Trigger_Select_Register);
3229                 break;
3230         case TRIG_EXT:
3231                 devpriv->ao_trigger_select =
3232                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3233                 if (cmd->start_arg & CR_INVERT)
3234                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3235                 if (cmd->start_arg & CR_EDGE)
3236                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3237                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3238                                     AO_Trigger_Select_Register);
3239                 break;
3240         default:
3241                 BUG();
3242                 break;
3243         }
3244         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3245         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3246
3247         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3248         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3249         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3250         if (cmd->stop_src == TRIG_NONE) {
3251                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3252         } else {
3253                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3254         }
3255         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3256         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3257         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3258         switch (cmd->stop_src) {
3259         case TRIG_COUNT:
3260                 if (board->reg_type & ni_reg_m_series_mask) {
3261                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3262                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3263                                             AO_UC_Load_A_Register);
3264                         devpriv->stc_writew(dev, AO_UC_Load,
3265                                             AO_Command_1_Register);
3266                 } else {
3267                         devpriv->stc_writel(dev, cmd->stop_arg,
3268                                             AO_UC_Load_A_Register);
3269                         devpriv->stc_writew(dev, AO_UC_Load,
3270                                             AO_Command_1_Register);
3271                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3272                                             AO_UC_Load_A_Register);
3273                 }
3274                 break;
3275         case TRIG_NONE:
3276                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3277                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3278                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3279                 break;
3280         default:
3281                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3282                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3283                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3284         }
3285
3286         devpriv->ao_mode1 &=
3287             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3288               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3289         switch (cmd->scan_begin_src) {
3290         case TRIG_TIMER:
3291                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3292                 trigvar =
3293                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3294                                    TRIG_ROUND_NEAREST);
3295                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3296                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3297                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3298                 break;
3299         case TRIG_EXT:
3300                 devpriv->ao_mode1 |=
3301                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3302                 if (cmd->scan_begin_arg & CR_INVERT)
3303                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3304                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3305                 break;
3306         default:
3307                 BUG();
3308                 break;
3309         }
3310         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3311         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3312         devpriv->ao_mode2 &=
3313             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3314         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3315
3316         if (cmd->scan_end_arg > 1) {
3317                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3318                 devpriv->stc_writew(dev,
3319                                     AO_Number_Of_Channels(cmd->scan_end_arg -
3320                                                           1) |
3321                                     AO_UPDATE_Output_Select
3322                                     (AO_Update_Output_High_Z),
3323                                     AO_Output_Control_Register);
3324         } else {
3325                 unsigned bits;
3326                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3327                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3328                 if (board->reg_type &
3329                     (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3330                         bits |= AO_Number_Of_Channels(0);
3331                 } else {
3332                         bits |=
3333                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3334                 }
3335                 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3336         }
3337         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3338
3339         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3340                             AO_Command_1_Register);
3341
3342         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3343         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3344
3345         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3346 #ifdef PCIDMA
3347         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3348 #else
3349         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3350 #endif
3351         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3352         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3353
3354         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3355             AO_TMRDACWR_Pulse_Width;
3356         if (board->ao_fifo_depth)
3357                 bits |= AO_FIFO_Enable;
3358         else
3359                 bits |= AO_DMA_PIO_Control;
3360 #if 0
3361         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3362            verified with bus analyzer. */
3363         if (board->reg_type & ni_reg_m_series_mask)
3364                 bits |= AO_Number_Of_DAC_Packages;
3365 #endif
3366         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3367         /*  enable sending of ao dma requests */
3368         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3369
3370         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3371
3372         if (cmd->stop_src == TRIG_COUNT) {
3373                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3374                                     Interrupt_B_Ack_Register);
3375                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3376                             AO_BC_TC_Interrupt_Enable, 1);
3377         }
3378
3379         s->async->inttrig = &ni_ao_inttrig;
3380
3381         return 0;
3382 }
3383
3384 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3385                          struct comedi_cmd *cmd)
3386 {
3387         const struct ni_board_struct *board = comedi_board(dev);
3388         struct ni_private *devpriv = dev->private;
3389         int err = 0;
3390         int tmp;
3391
3392         /* Step 1 : check if triggers are trivially valid */
3393
3394         if ((cmd->flags & CMDF_WRITE) == 0)
3395                 cmd->flags |= CMDF_WRITE;
3396
3397         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3398         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3399                                         TRIG_TIMER | TRIG_EXT);
3400         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3401         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3402         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3403
3404         if (err)
3405                 return 1;
3406
3407         /* Step 2a : make sure trigger sources are unique */
3408
3409         err |= cfc_check_trigger_is_unique(cmd->start_src);
3410         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3411         err |= cfc_check_trigger_is_unique(cmd->stop_src);
3412
3413         /* Step 2b : and mutually compatible */
3414
3415         if (err)
3416                 return 2;
3417
3418         /* Step 3: check if arguments are trivially valid */
3419
3420         if (cmd->start_src == TRIG_EXT) {
3421                 /* external trigger */
3422                 unsigned int tmp = CR_CHAN(cmd->start_arg);
3423
3424                 if (tmp > 18)
3425                         tmp = 18;
3426                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3427                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3428         } else {
3429                 /* true for both TRIG_NOW and TRIG_INT */
3430                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3431         }
3432
3433         if (cmd->scan_begin_src == TRIG_TIMER) {
3434                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3435                                                  board->ao_speed);
3436                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3437                                                  devpriv->clock_ns * 0xffffff);
3438         }
3439
3440         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3441         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3442
3443         if (cmd->stop_src == TRIG_COUNT)
3444                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3445         else    /* TRIG_NONE */
3446                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3447
3448         if (err)
3449                 return 3;
3450
3451         /* step 4: fix up any arguments */
3452         if (cmd->scan_begin_src == TRIG_TIMER) {
3453                 tmp = cmd->scan_begin_arg;
3454                 cmd->scan_begin_arg =
3455                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3456                                                        cmd->scan_begin_arg,
3457                                                        cmd->
3458                                                        flags &
3459                                                        TRIG_ROUND_MASK));
3460                 if (tmp != cmd->scan_begin_arg)
3461                         err++;
3462         }
3463         if (err)
3464                 return 4;
3465
3466         /* step 5: fix up chanlist */
3467
3468         if (err)
3469                 return 5;
3470
3471         return 0;
3472 }
3473
3474 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3475 {
3476         const struct ni_board_struct *board = comedi_board(dev);
3477         struct ni_private *devpriv = dev->private;
3478
3479         /* devpriv->ao0p=0x0000; */
3480         /* ni_writew(devpriv->ao0p,AO_Configuration); */
3481
3482         /* devpriv->ao1p=AO_Channel(1); */
3483         /* ni_writew(devpriv->ao1p,AO_Configuration); */
3484
3485         ni_release_ao_mite_channel(dev);
3486
3487         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3488         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3489         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3490         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3491         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3492         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3493                             AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3494         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3495         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3496         devpriv->ao_cmd1 = 0;
3497         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3498         devpriv->ao_cmd2 = 0;
3499         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3500         devpriv->ao_mode1 = 0;
3501         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3502         devpriv->ao_mode2 = 0;
3503         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3504         if (board->reg_type & ni_reg_m_series_mask)
3505                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3506         else
3507                 devpriv->ao_mode3 = 0;
3508         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3509         devpriv->ao_trigger_select = 0;
3510         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3511                             AO_Trigger_Select_Register);
3512         if (board->reg_type & ni_reg_6xxx_mask) {
3513                 unsigned immediate_bits = 0;
3514                 unsigned i;
3515                 for (i = 0; i < s->n_chan; ++i) {
3516                         immediate_bits |= 1 << i;
3517                 }
3518                 ao_win_out(immediate_bits, AO_Immediate_671x);
3519                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3520         }
3521         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3522
3523         return 0;
3524 }
3525
3526 /* digital io */
3527
3528 static int ni_dio_insn_config(struct comedi_device *dev,
3529                               struct comedi_subdevice *s,
3530                               struct comedi_insn *insn, unsigned int *data)
3531 {
3532         struct ni_private *devpriv = dev->private;
3533
3534 #ifdef DEBUG_DIO
3535         printk("ni_dio_insn_config() chan=%d io=%d\n",
3536                CR_CHAN(insn->chanspec), data[0]);
3537 #endif
3538         switch (data[0]) {
3539         case INSN_CONFIG_DIO_OUTPUT:
3540                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3541                 break;
3542         case INSN_CONFIG_DIO_INPUT:
3543                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3544                 break;
3545         case INSN_CONFIG_DIO_QUERY:
3546                 data[1] =
3547                     (s->
3548                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3549                     COMEDI_INPUT;
3550                 return insn->n;
3551                 break;
3552         default:
3553                 return -EINVAL;
3554         }
3555
3556         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3557         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3558         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3559
3560         return 1;
3561 }
3562
3563 static int ni_dio_insn_bits(struct comedi_device *dev,
3564                             struct comedi_subdevice *s,
3565                             struct comedi_insn *insn, unsigned int *data)
3566 {
3567         struct ni_private *devpriv = dev->private;
3568
3569 #ifdef DEBUG_DIO
3570         printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3571 #endif
3572
3573         if (data[0]) {
3574                 /* Perform check to make sure we're not using the
3575                    serial part of the dio */
3576                 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3577                     && devpriv->serial_interval_ns)
3578                         return -EBUSY;
3579
3580                 s->state &= ~data[0];
3581                 s->state |= (data[0] & data[1]);
3582                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3583                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3584                 devpriv->stc_writew(dev, devpriv->dio_output,
3585                                     DIO_Output_Register);
3586         }
3587         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3588
3589         return insn->n;
3590 }
3591
3592 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3593                                        struct comedi_subdevice *s,
3594                                        struct comedi_insn *insn,
3595                                        unsigned int *data)
3596 {
3597         struct ni_private *devpriv __maybe_unused = dev->private;
3598
3599 #ifdef DEBUG_DIO
3600         printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3601                CR_CHAN(insn->chanspec), data[0]);
3602 #endif
3603         switch (data[0]) {
3604         case INSN_CONFIG_DIO_OUTPUT:
3605                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3606                 break;
3607         case INSN_CONFIG_DIO_INPUT:
3608                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3609                 break;
3610         case INSN_CONFIG_DIO_QUERY:
3611                 data[1] =
3612                     (s->
3613                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3614                     COMEDI_INPUT;
3615                 return insn->n;
3616                 break;
3617         default:
3618                 return -EINVAL;
3619         }
3620
3621         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3622
3623         return 1;
3624 }
3625
3626 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3627                                      struct comedi_subdevice *s,
3628                                      struct comedi_insn *insn,
3629                                      unsigned int *data)
3630 {
3631         struct ni_private *devpriv __maybe_unused = dev->private;
3632
3633 #ifdef DEBUG_DIO
3634         printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3635                data[1]);
3636 #endif
3637
3638         if (data[0]) {
3639                 s->state &= ~data[0];
3640                 s->state |= (data[0] & data[1]);
3641                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3642         }
3643         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3644
3645         return insn->n;
3646 }
3647
3648 static int ni_cdio_cmdtest(struct comedi_device *dev,
3649                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3650 {
3651         int err = 0;
3652         int tmp;
3653         unsigned i;
3654
3655         /* Step 1 : check if triggers are trivially valid */
3656
3657         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3658         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3659         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3660         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3661         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3662
3663         if (err)
3664                 return 1;
3665
3666         /* Step 2a : make sure trigger sources are unique */
3667         /* Step 2b : and mutually compatible */
3668
3669         if (err)
3670                 return 2;
3671
3672         /* Step 3: check if arguments are trivially valid */
3673
3674         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3675
3676         tmp = cmd->scan_begin_arg;
3677         tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3678         if (tmp != cmd->scan_begin_arg)
3679                 err |= -EINVAL;
3680
3681         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3682         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3683         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3684
3685         if (err)
3686                 return 3;
3687
3688         /* step 4: fix up any arguments */
3689
3690         if (err)
3691                 return 4;
3692
3693         /* step 5: check chanlist */
3694
3695         for (i = 0; i < cmd->chanlist_len; ++i) {
3696                 if (cmd->chanlist[i] != i)
3697                         err = 1;
3698         }
3699
3700         if (err)
3701                 return 5;
3702
3703         return 0;
3704 }
3705
3706 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3707 {
3708         struct ni_private *devpriv __maybe_unused = dev->private;
3709         const struct comedi_cmd *cmd = &s->async->cmd;
3710         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3711         int retval;
3712
3713         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3714         switch (cmd->scan_begin_src) {
3715         case TRIG_EXT:
3716                 cdo_mode_bits |=
3717                     CR_CHAN(cmd->scan_begin_arg) &
3718                     CDO_Sample_Source_Select_Mask;
3719                 break;
3720         default:
3721                 BUG();
3722                 break;
3723         }
3724         if (cmd->scan_begin_arg & CR_INVERT)
3725                 cdo_mode_bits |= CDO_Polarity_Bit;
3726         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3727         if (s->io_bits) {
3728                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3729                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3730                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3731         } else {
3732                 comedi_error(dev,
3733                              "attempted to run digital output command with no lines configured as outputs");
3734                 return -EIO;
3735         }
3736         retval = ni_request_cdo_mite_channel(dev);
3737         if (retval < 0) {
3738                 return retval;
3739         }
3740         s->async->inttrig = &ni_cdo_inttrig;
3741         return 0;
3742 }
3743
3744 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3745                           unsigned int trignum)
3746 {
3747 #ifdef PCIDMA
3748         struct ni_private *devpriv = dev->private;
3749         unsigned long flags;
3750 #endif
3751         int retval = 0;
3752         unsigned i;
3753         const unsigned timeout = 1000;
3754
3755         s->async->inttrig = NULL;
3756
3757         /* read alloc the entire buffer */
3758         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3759
3760 #ifdef PCIDMA
3761         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3762         if (devpriv->cdo_mite_chan) {
3763                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3764                 mite_dma_arm(devpriv->cdo_mite_chan);
3765         } else {
3766                 comedi_error(dev, "BUG: no cdo mite channel?");
3767                 retval = -EIO;
3768         }
3769         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3770         if (retval < 0)
3771                 return retval;
3772 #endif
3773 /*
3774 * XXX not sure what interrupt C group does
3775 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3776 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3777 */
3778         for (i = 0; i < timeout; ++i) {
3779                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3780                         break;
3781                 udelay(10);
3782         }
3783         if (i == timeout) {
3784                 comedi_error(dev, "dma failed to fill cdo fifo!");
3785                 ni_cdio_cancel(dev, s);
3786                 return -EIO;
3787         }
3788         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3789                   CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3790                   M_Offset_CDIO_Command);
3791         return retval;
3792 }
3793
3794 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3795 {
3796         struct ni_private *devpriv __maybe_unused = dev->private;
3797
3798         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3799                   CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3800                   CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3801                   M_Offset_CDIO_Command);
3802 /*
3803 * XXX not sure what interrupt C group does ni_writeb(0,
3804 * M_Offset_Interrupt_C_Enable);
3805 */
3806         ni_writel(0, M_Offset_CDO_Mask_Enable);
3807         ni_release_cdo_mite_channel(dev);
3808         return 0;
3809 }
3810
3811 static void handle_cdio_interrupt(struct comedi_device *dev)
3812 {
3813         const struct ni_board_struct *board = comedi_board(dev);
3814         struct ni_private *devpriv __maybe_unused = dev->private;
3815         unsigned cdio_status;
3816         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3817 #ifdef PCIDMA
3818         unsigned long flags;
3819 #endif
3820
3821         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3822                 return;
3823         }
3824 #ifdef PCIDMA
3825         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3826         if (devpriv->cdo_mite_chan) {
3827                 unsigned cdo_mite_status =
3828                     mite_get_status(devpriv->cdo_mite_chan);
3829                 if (cdo_mite_status & CHSR_LINKC) {
3830                         writel(CHOR_CLRLC,
3831                                devpriv->mite->mite_io_addr +
3832                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3833                 }
3834                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3835         }
3836         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3837 #endif
3838
3839         cdio_status = ni_readl(M_Offset_CDIO_Status);
3840         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3841 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3842                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      /*  XXX just guessing this is needed and does something useful */
3843                 s->async->events |= COMEDI_CB_OVERFLOW;
3844         }
3845         if (cdio_status & CDO_FIFO_Empty_Bit) {
3846 /* printk("cdio fifo empty\n"); */
3847                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3848                           M_Offset_CDIO_Command);
3849 /* s->async->events |= COMEDI_CB_EOA; */
3850         }
3851         ni_event(dev, s);
3852 }
3853
3854 static int ni_serial_insn_config(struct comedi_device *dev,
3855                                  struct comedi_subdevice *s,
3856                                  struct comedi_insn *insn, unsigned int *data)
3857 {
3858         struct ni_private *devpriv = dev->private;
3859         int err = insn->n;
3860         unsigned char byte_out, byte_in = 0;
3861
3862         if (insn->n != 2)
3863                 return -EINVAL;
3864
3865         switch (data[0]) {
3866         case INSN_CONFIG_SERIAL_CLOCK:
3867
3868 #ifdef DEBUG_DIO
3869                 printk("SPI serial clock Config cd\n", data[1]);
3870 #endif
3871                 devpriv->serial_hw_mode = 1;
3872                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3873
3874                 if (data[1] == SERIAL_DISABLED) {
3875                         devpriv->serial_hw_mode = 0;
3876                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3877                                                   DIO_Software_Serial_Control);
3878                         data[1] = SERIAL_DISABLED;
3879                         devpriv->serial_interval_ns = data[1];
3880                 } else if (data[1] <= SERIAL_600NS) {
3881                         /* Warning: this clock speed is too fast to reliably
3882                            control SCXI. */
3883                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3884                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3885                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3886                         data[1] = SERIAL_600NS;
3887                         devpriv->serial_interval_ns = data[1];
3888                 } else if (data[1] <= SERIAL_1_2US) {
3889                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3890                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3891                             DIO_Serial_Out_Divide_By_2;
3892                         data[1] = SERIAL_1_2US;
3893                         devpriv->serial_interval_ns = data[1];
3894                 } else if (data[1] <= SERIAL_10US) {
3895                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3896                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3897                             DIO_Serial_Out_Divide_By_2;
3898                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3899                            600ns/1.2us. If you turn divide_by_2 off with the
3900                            slow clock, you will still get 10us, except then
3901                            all your delays are wrong. */
3902                         data[1] = SERIAL_10US;
3903                         devpriv->serial_interval_ns = data[1];
3904                 } else {
3905                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3906                                                   DIO_Software_Serial_Control);
3907                         devpriv->serial_hw_mode = 0;
3908                         data[1] = (data[1] / 1000) * 1000;
3909                         devpriv->serial_interval_ns = data[1];
3910                 }
3911
3912                 devpriv->stc_writew(dev, devpriv->dio_control,
3913                                     DIO_Control_Register);
3914                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3915                                     Clock_and_FOUT_Register);
3916                 return 1;
3917
3918                 break;
3919
3920         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3921
3922                 if (devpriv->serial_interval_ns == 0) {
3923                         return -EINVAL;
3924                 }
3925
3926                 byte_out = data[1] & 0xFF;
3927
3928                 if (devpriv->serial_hw_mode) {
3929                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3930                                                       &byte_in);
3931                 } else if (devpriv->serial_interval_ns > 0) {
3932                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3933                                                       &byte_in);
3934                 } else {
3935                         printk("ni_serial_insn_config: serial disabled!\n");
3936                         return -EINVAL;
3937                 }
3938                 if (err < 0)
3939                         return err;
3940                 data[1] = byte_in & 0xFF;
3941                 return insn->n;
3942
3943                 break;
3944         default:
3945                 return -EINVAL;
3946         }
3947
3948 }
3949
3950 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3951                                    struct comedi_subdevice *s,
3952                                    unsigned char data_out,
3953                                    unsigned char *data_in)
3954 {
3955         struct ni_private *devpriv = dev->private;
3956         unsigned int status1;
3957         int err = 0, count = 20;
3958
3959 #ifdef DEBUG_DIO
3960         printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3961 #endif
3962
3963         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3964         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3965         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3966
3967         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3968         if (status1 & DIO_Serial_IO_In_Progress_St) {
3969                 err = -EBUSY;
3970                 goto Error;
3971         }
3972
3973         devpriv->dio_control |= DIO_HW_Serial_Start;
3974         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3975         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3976
3977         /* Wait until STC says we're done, but don't loop infinitely. */
3978         while ((status1 =
3979                 devpriv->stc_readw(dev,
3980                                    Joint_Status_1_Register)) &
3981                DIO_Serial_IO_In_Progress_St) {
3982                 /* Delay one bit per loop */
3983                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3984                 if (--count < 0) {
3985                         printk
3986                             ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3987                         err = -ETIME;
3988                         goto Error;
3989                 }
3990         }
3991
3992         /* Delay for last bit. This delay is absolutely necessary, because
3993            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3994         udelay((devpriv->serial_interval_ns + 999) / 1000);
3995
3996         if (data_in != NULL) {
3997                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3998 #ifdef DEBUG_DIO
3999                 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4000 #endif
4001         }
4002
4003 Error:
4004         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4005
4006         return err;
4007 }
4008
4009 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4010                                    struct comedi_subdevice *s,
4011                                    unsigned char data_out,
4012                                    unsigned char *data_in)
4013 {
4014         struct ni_private *devpriv = dev->private;
4015         unsigned char mask, input = 0;
4016
4017 #ifdef DEBUG_DIO
4018         printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4019 #endif
4020
4021         /* Wait for one bit before transfer */
4022         udelay((devpriv->serial_interval_ns + 999) / 1000);
4023
4024         for (mask = 0x80; mask; mask >>= 1) {
4025                 /* Output current bit; note that we cannot touch s->state
4026                    because it is a per-subdevice field, and serial is
4027                    a separate subdevice from DIO. */
4028                 devpriv->dio_output &= ~DIO_SDOUT;
4029                 if (data_out & mask) {
4030                         devpriv->dio_output |= DIO_SDOUT;
4031                 }
4032                 devpriv->stc_writew(dev, devpriv->dio_output,
4033                                     DIO_Output_Register);
4034
4035                 /* Assert SDCLK (active low, inverted), wait for half of
4036                    the delay, deassert SDCLK, and wait for the other half. */
4037                 devpriv->dio_control |= DIO_Software_Serial_Control;
4038                 devpriv->stc_writew(dev, devpriv->dio_control,
4039                                     DIO_Control_Register);
4040
4041                 udelay((devpriv->serial_interval_ns + 999) / 2000);
4042
4043                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4044                 devpriv->stc_writew(dev, devpriv->dio_control,
4045                                     DIO_Control_Register);
4046
4047                 udelay((devpriv->serial_interval_ns + 999) / 2000);
4048
4049                 /* Input current bit */
4050                 if (devpriv->stc_readw(dev,
4051                                        DIO_Parallel_Input_Register) & DIO_SDIN)
4052                 {
4053 /*                      printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4054                         input |= mask;
4055                 }
4056         }
4057 #ifdef DEBUG_DIO
4058         printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4059 #endif
4060         if (data_in)
4061                 *data_in = input;
4062
4063         return 0;
4064 }
4065
4066 static void mio_common_detach(struct comedi_device *dev)
4067 {
4068         struct ni_private *devpriv = dev->private;
4069
4070         if (devpriv) {
4071                 if (devpriv->counter_dev) {
4072                         ni_gpct_device_destroy(devpriv->counter_dev);
4073                 }
4074         }
4075 }
4076
4077 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4078 {
4079         int i;
4080
4081         for (i = 0; i < s->n_chan; i++) {
4082                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4083                                AO_Configuration_2_67xx);
4084         }
4085         ao_win_out(0x0, AO_Later_Single_Point_Updates);
4086 }
4087
4088 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4089 {
4090         unsigned stc_register;
4091         switch (reg) {
4092         case NITIO_G0_Autoincrement_Reg:
4093                 stc_register = G_Autoincrement_Register(0);
4094                 break;
4095         case NITIO_G1_Autoincrement_Reg:
4096                 stc_register = G_Autoincrement_Register(1);
4097                 break;
4098         case NITIO_G0_Command_Reg:
4099                 stc_register = G_Command_Register(0);
4100                 break;
4101         case NITIO_G1_Command_Reg:
4102                 stc_register = G_Command_Register(1);
4103                 break;
4104         case NITIO_G0_HW_Save_Reg:
4105                 stc_register = G_HW_Save_Register(0);
4106                 break;
4107         case NITIO_G1_HW_Save_Reg:
4108                 stc_register = G_HW_Save_Register(1);
4109                 break;
4110         case NITIO_G0_SW_Save_Reg:
4111                 stc_register = G_Save_Register(0);
4112                 break;
4113         case NITIO_G1_SW_Save_Reg:
4114                 stc_register = G_Save_Register(1);
4115                 break;
4116         case NITIO_G0_Mode_Reg:
4117                 stc_register = G_Mode_Register(0);
4118                 break;
4119         case NITIO_G1_Mode_Reg:
4120                 stc_register = G_Mode_Register(1);
4121                 break;
4122         case NITIO_G0_LoadA_Reg:
4123                 stc_register = G_Load_A_Register(0);
4124                 break;
4125         case NITIO_G1_LoadA_Reg:
4126                 stc_register = G_Load_A_Register(1);
4127                 break;
4128         case NITIO_G0_LoadB_Reg:
4129                 stc_register = G_Load_B_Register(0);
4130                 break;
4131         case NITIO_G1_LoadB_Reg:
4132                 stc_register = G_Load_B_Register(1);
4133                 break;
4134         case NITIO_G0_Input_Select_Reg:
4135                 stc_register = G_Input_Select_Register(0);
4136                 break;
4137         case NITIO_G1_Input_Select_Reg:
4138                 stc_register = G_Input_Select_Register(1);
4139                 break;
4140         case NITIO_G01_Status_Reg:
4141                 stc_register = G_Status_Register;
4142                 break;
4143         case NITIO_G01_Joint_Reset_Reg:
4144                 stc_register = Joint_Reset_Register;
4145                 break;
4146         case NITIO_G01_Joint_Status1_Reg:
4147                 stc_register = Joint_Status_1_Register;
4148                 break;
4149         case NITIO_G01_Joint_Status2_Reg:
4150                 stc_register = Joint_Status_2_Register;
4151                 break;
4152         case NITIO_G0_Interrupt_Acknowledge_Reg:
4153                 stc_register = Interrupt_A_Ack_Register;
4154                 break;
4155         case NITIO_G1_Interrupt_Acknowledge_Reg:
4156                 stc_register = Interrupt_B_Ack_Register;
4157                 break;
4158         case NITIO_G0_Status_Reg:
4159                 stc_register = AI_Status_1_Register;
4160                 break;
4161         case NITIO_G1_Status_Reg:
4162                 stc_register = AO_Status_1_Register;
4163                 break;
4164         case NITIO_G0_Interrupt_Enable_Reg:
4165                 stc_register = Interrupt_A_Enable_Register;
4166                 break;
4167         case NITIO_G1_Interrupt_Enable_Reg:
4168                 stc_register = Interrupt_B_Enable_Register;
4169                 break;
4170         default:
4171                 printk("%s: unhandled register 0x%x in switch.\n",
4172                        __func__, reg);
4173                 BUG();
4174                 return 0;
4175                 break;
4176         }
4177         return stc_register;
4178 }
4179
4180 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4181                                    enum ni_gpct_register reg)
4182 {
4183         struct comedi_device *dev = counter->counter_dev->dev;
4184         struct ni_private *devpriv = dev->private;
4185         unsigned stc_register;
4186         /* bits in the join reset register which are relevant to counters */
4187         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4188         static const unsigned gpct_interrupt_a_enable_mask =
4189             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4190         static const unsigned gpct_interrupt_b_enable_mask =
4191             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4192
4193         switch (reg) {
4194                 /* m-series-only registers */
4195         case NITIO_G0_Counting_Mode_Reg:
4196                 ni_writew(bits, M_Offset_G0_Counting_Mode);
4197                 break;
4198         case NITIO_G1_Counting_Mode_Reg:
4199                 ni_writew(bits, M_Offset_G1_Counting_Mode);
4200                 break;
4201         case NITIO_G0_Second_Gate_Reg:
4202                 ni_writew(bits, M_Offset_G0_Second_Gate);
4203                 break;
4204         case NITIO_G1_Second_Gate_Reg:
4205                 ni_writew(bits, M_Offset_G1_Second_Gate);
4206                 break;
4207         case NITIO_G0_DMA_Config_Reg:
4208                 ni_writew(bits, M_Offset_G0_DMA_Config);
4209                 break;
4210         case NITIO_G1_DMA_Config_Reg:
4211                 ni_writew(bits, M_Offset_G1_DMA_Config);
4212                 break;
4213         case NITIO_G0_ABZ_Reg:
4214                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4215                 break;
4216         case NITIO_G1_ABZ_Reg:
4217                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4218                 break;
4219
4220                 /* 32 bit registers */
4221         case NITIO_G0_LoadA_Reg:
4222         case NITIO_G1_LoadA_Reg:
4223         case NITIO_G0_LoadB_Reg:
4224         case NITIO_G1_LoadB_Reg:
4225                 stc_register = ni_gpct_to_stc_register(reg);
4226                 devpriv->stc_writel(dev, bits, stc_register);
4227                 break;
4228
4229                 /* 16 bit registers */
4230         case NITIO_G0_Interrupt_Enable_Reg:
4231                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4232                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4233                                 gpct_interrupt_a_enable_mask, bits);
4234                 break;
4235         case NITIO_G1_Interrupt_Enable_Reg:
4236                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4237                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4238                                 gpct_interrupt_b_enable_mask, bits);
4239                 break;
4240         case NITIO_G01_Joint_Reset_Reg:
4241                 BUG_ON(bits & ~gpct_joint_reset_mask);
4242                 /* fall-through */
4243         default:
4244                 stc_register = ni_gpct_to_stc_register(reg);
4245                 devpriv->stc_writew(dev, bits, stc_register);
4246         }
4247 }
4248
4249 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4250                                       enum ni_gpct_register reg)
4251 {
4252         struct comedi_device *dev = counter->counter_dev->dev;
4253         struct ni_private *devpriv = dev->private;
4254         unsigned stc_register;
4255
4256         switch (reg) {
4257                 /* m-series only registers */
4258         case NITIO_G0_DMA_Status_Reg:
4259                 return ni_readw(M_Offset_G0_DMA_Status);
4260                 break;
4261         case NITIO_G1_DMA_Status_Reg:
4262                 return ni_readw(M_Offset_G1_DMA_Status);
4263                 break;
4264
4265                 /* 32 bit registers */
4266         case NITIO_G0_HW_Save_Reg:
4267         case NITIO_G1_HW_Save_Reg:
4268         case NITIO_G0_SW_Save_Reg:
4269         case NITIO_G1_SW_Save_Reg:
4270                 stc_register = ni_gpct_to_stc_register(reg);
4271                 return devpriv->stc_readl(dev, stc_register);
4272                 break;
4273
4274                 /* 16 bit registers */
4275         default:
4276                 stc_register = ni_gpct_to_stc_register(reg);
4277                 return devpriv->stc_readw(dev, stc_register);
4278                 break;
4279         }
4280         return 0;
4281 }
4282
4283 static int ni_freq_out_insn_read(struct comedi_device *dev,
4284                                  struct comedi_subdevice *s,
4285                                  struct comedi_insn *insn, unsigned int *data)
4286 {
4287         struct ni_private *devpriv = dev->private;
4288
4289         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4290         return 1;
4291 }
4292
4293 static int ni_freq_out_insn_write(struct comedi_device *dev,
4294                                   struct comedi_subdevice *s,
4295                                   struct comedi_insn *insn, unsigned int *data)
4296 {
4297         struct ni_private *devpriv = dev->private;
4298
4299         devpriv->clock_and_fout &= ~FOUT_Enable;
4300         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4301                             Clock_and_FOUT_Register);
4302         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4303         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4304         devpriv->clock_and_fout |= FOUT_Enable;
4305         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4306                             Clock_and_FOUT_Register);
4307         return insn->n;
4308 }
4309
4310 static int ni_set_freq_out_clock(struct comedi_device *dev,
4311                                  unsigned int clock_source)
4312 {
4313         struct ni_private *devpriv = dev->private;
4314
4315         switch (clock_source) {
4316         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4317                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4318                 break;
4319         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4320                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4321                 break;
4322         default:
4323                 return -EINVAL;
4324         }
4325         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4326                             Clock_and_FOUT_Register);
4327         return 3;
4328 }
4329
4330 static void ni_get_freq_out_clock(struct comedi_device *dev,
4331                                   unsigned int *clock_source,
4332                                   unsigned int *clock_period_ns)
4333 {
4334         struct ni_private *devpriv = dev->private;
4335
4336         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4337                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4338                 *clock_period_ns = TIMEBASE_2_NS;
4339         } else {
4340                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4341                 *clock_period_ns = TIMEBASE_1_NS * 2;
4342         }
4343 }
4344
4345 static int ni_freq_out_insn_config(struct comedi_device *dev,
4346                                    struct comedi_subdevice *s,
4347                                    struct comedi_insn *insn, unsigned int *data)
4348 {
4349         switch (data[0]) {
4350         case INSN_CONFIG_SET_CLOCK_SRC:
4351                 return ni_set_freq_out_clock(dev, data[1]);
4352                 break;
4353         case INSN_CONFIG_GET_CLOCK_SRC:
4354                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4355                 return 3;
4356         default:
4357                 break;
4358         }
4359         return -EINVAL;
4360 }
4361
4362 static int ni_alloc_private(struct comedi_device *dev)
4363 {
4364         struct ni_private *devpriv;
4365
4366         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4367         if (!devpriv)
4368                 return -ENOMEM;
4369         dev->private = devpriv;
4370
4371         spin_lock_init(&devpriv->window_lock);
4372         spin_lock_init(&devpriv->soft_reg_copy_lock);
4373         spin_lock_init(&devpriv->mite_channel_lock);
4374
4375         return 0;
4376 };
4377
4378 static int ni_E_init(struct comedi_device *dev)
4379 {
4380         const struct ni_board_struct *board = comedi_board(dev);
4381         struct ni_private *devpriv = dev->private;
4382         struct comedi_subdevice *s;
4383         unsigned j;
4384         enum ni_gpct_variant counter_variant;
4385         int ret;
4386
4387         if (board->n_aochan > MAX_N_AO_CHAN) {
4388                 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4389                 return -EINVAL;
4390         }
4391
4392         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4393         if (ret)
4394                 return ret;
4395
4396         /* analog input subdevice */
4397
4398         s = &dev->subdevices[NI_AI_SUBDEV];
4399         dev->read_subdev = s;
4400         if (board->n_adchan) {
4401                 s->type = COMEDI_SUBD_AI;
4402                 s->subdev_flags =
4403                     SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4404                 if (board->reg_type != ni_reg_611x)
4405                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4406                 if (board->adbits > 16)
4407                         s->subdev_flags |= SDF_LSAMPL;
4408                 if (board->reg_type & ni_reg_m_series_mask)
4409                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4410                 s->n_chan = board->n_adchan;
4411                 s->len_chanlist = 512;
4412                 s->maxdata = (1 << board->adbits) - 1;
4413                 s->range_table = ni_range_lkup[board->gainlkup];
4414                 s->insn_read = &ni_ai_insn_read;
4415                 s->insn_config = &ni_ai_insn_config;
4416                 s->do_cmdtest = &ni_ai_cmdtest;
4417                 s->do_cmd = &ni_ai_cmd;
4418                 s->cancel = &ni_ai_reset;
4419                 s->poll = &ni_ai_poll;
4420                 s->munge = &ni_ai_munge;
4421 #ifdef PCIDMA
4422                 s->async_dma_dir = DMA_FROM_DEVICE;
4423 #endif
4424         } else {
4425                 s->type = COMEDI_SUBD_UNUSED;
4426         }
4427
4428         /* analog output subdevice */
4429
4430         s = &dev->subdevices[NI_AO_SUBDEV];
4431         if (board->n_aochan) {
4432                 s->type = COMEDI_SUBD_AO;
4433                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4434                 if (board->reg_type & ni_reg_m_series_mask)
4435                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4436                 s->n_chan = board->n_aochan;
4437                 s->maxdata = (1 << board->aobits) - 1;
4438                 s->range_table = board->ao_range_table;
4439                 s->insn_read = &ni_ao_insn_read;
4440                 if (board->reg_type & ni_reg_6xxx_mask) {
4441                         s->insn_write = &ni_ao_insn_write_671x;
4442                 } else {
4443                         s->insn_write = &ni_ao_insn_write;
4444                 }
4445                 s->insn_config = &ni_ao_insn_config;
4446 #ifdef PCIDMA
4447                 if (board->n_aochan) {
4448                         s->async_dma_dir = DMA_TO_DEVICE;
4449 #else
4450                 if (board->ao_fifo_depth) {
4451 #endif
4452                         dev->write_subdev = s;
4453                         s->subdev_flags |= SDF_CMD_WRITE;
4454                         s->do_cmd = &ni_ao_cmd;
4455                         s->do_cmdtest = &ni_ao_cmdtest;
4456                         s->len_chanlist = board->n_aochan;
4457                         if ((board->reg_type & ni_reg_m_series_mask) == 0)
4458                                 s->munge = ni_ao_munge;
4459                 }
4460                 s->cancel = &ni_ao_reset;
4461         } else {
4462                 s->type = COMEDI_SUBD_UNUSED;
4463         }
4464         if ((board->reg_type & ni_reg_67xx_mask))
4465                 init_ao_67xx(dev, s);
4466
4467         /* digital i/o subdevice */
4468
4469         s = &dev->subdevices[NI_DIO_SUBDEV];
4470         s->type = COMEDI_SUBD_DIO;
4471         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4472         s->maxdata = 1;
4473         s->io_bits = 0;         /* all bits input */
4474         s->range_table = &range_digital;
4475         s->n_chan = board->num_p0_dio_channels;
4476         if (board->reg_type & ni_reg_m_series_mask) {
4477                 s->subdev_flags |=
4478                     SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4479                 s->insn_bits = &ni_m_series_dio_insn_bits;
4480                 s->insn_config = &ni_m_series_dio_insn_config;
4481                 s->do_cmd = &ni_cdio_cmd;
4482                 s->do_cmdtest = &ni_cdio_cmdtest;
4483                 s->cancel = &ni_cdio_cancel;
4484                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4485                 s->len_chanlist = s->n_chan;
4486
4487                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4488                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4489         } else {
4490                 s->insn_bits = &ni_dio_insn_bits;
4491                 s->insn_config = &ni_dio_insn_config;
4492                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4493                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4494         }
4495
4496         /* 8255 device */
4497         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4498         if (board->has_8255) {
4499                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4500         } else {
4501                 s->type = COMEDI_SUBD_UNUSED;
4502         }
4503
4504         /* formerly general purpose counter/timer device, but no longer used */
4505         s = &dev->subdevices[NI_UNUSED_SUBDEV];
4506         s->type = COMEDI_SUBD_UNUSED;
4507
4508         /* calibration subdevice -- ai and ao */
4509         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4510         s->type = COMEDI_SUBD_CALIB;
4511         if (board->reg_type & ni_reg_m_series_mask) {
4512                 /*  internal PWM analog output used for AI nonlinearity calibration */
4513                 s->subdev_flags = SDF_INTERNAL;
4514                 s->insn_config = &ni_m_series_pwm_config;
4515                 s->n_chan = 1;
4516                 s->maxdata = 0;
4517                 ni_writel(0x0, M_Offset_Cal_PWM);
4518         } else if (board->reg_type == ni_reg_6143) {
4519                 /*  internal PWM analog output used for AI nonlinearity calibration */
4520                 s->subdev_flags = SDF_INTERNAL;
4521                 s->insn_config = &ni_6143_pwm_config;
4522                 s->n_chan = 1;
4523                 s->maxdata = 0;
4524         } else {
4525                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4526                 s->insn_read = &ni_calib_insn_read;
4527                 s->insn_write = &ni_calib_insn_write;
4528                 caldac_setup(dev, s);
4529         }
4530
4531         /* EEPROM */
4532         s = &dev->subdevices[NI_EEPROM_SUBDEV];
4533         s->type = COMEDI_SUBD_MEMORY;
4534         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4535         s->maxdata = 0xff;
4536         if (board->reg_type & ni_reg_m_series_mask) {
4537                 s->n_chan = M_SERIES_EEPROM_SIZE;
4538                 s->insn_read = &ni_m_series_eeprom_insn_read;
4539         } else {
4540                 s->n_chan = 512;
4541                 s->insn_read = &ni_eeprom_insn_read;
4542         }
4543
4544         /* PFI */
4545         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4546         s->type = COMEDI_SUBD_DIO;
4547         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4548         if (board->reg_type & ni_reg_m_series_mask) {
4549                 unsigned i;
4550                 s->n_chan = 16;
4551                 ni_writew(s->state, M_Offset_PFI_DO);
4552                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4553                         ni_writew(devpriv->pfi_output_select_reg[i],
4554                                   M_Offset_PFI_Output_Select(i + 1));
4555                 }
4556         } else {
4557                 s->n_chan = 10;
4558         }
4559         s->maxdata = 1;
4560         if (board->reg_type & ni_reg_m_series_mask) {
4561                 s->insn_bits = &ni_pfi_insn_bits;
4562         }
4563         s->insn_config = &ni_pfi_insn_config;
4564         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4565
4566         /* cs5529 calibration adc */
4567         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4568         if (board->reg_type & ni_reg_67xx_mask) {
4569                 s->type = COMEDI_SUBD_AI;
4570                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4571                 /*  one channel for each analog output channel */
4572                 s->n_chan = board->n_aochan;
4573                 s->maxdata = (1 << 16) - 1;
4574                 s->range_table = &range_unknown;        /* XXX */
4575                 s->insn_read = cs5529_ai_insn_read;
4576                 s->insn_config = NULL;
4577                 init_cs5529(dev);
4578         } else {
4579                 s->type = COMEDI_SUBD_UNUSED;
4580         }
4581
4582         /* Serial */
4583         s = &dev->subdevices[NI_SERIAL_SUBDEV];
4584         s->type = COMEDI_SUBD_SERIAL;
4585         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4586         s->n_chan = 1;
4587         s->maxdata = 0xff;
4588         s->insn_config = ni_serial_insn_config;
4589         devpriv->serial_interval_ns = 0;
4590         devpriv->serial_hw_mode = 0;
4591
4592         /* RTSI */
4593         s = &dev->subdevices[NI_RTSI_SUBDEV];
4594         s->type = COMEDI_SUBD_DIO;
4595         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4596         s->n_chan = 8;
4597         s->maxdata = 1;
4598         s->insn_bits = ni_rtsi_insn_bits;
4599         s->insn_config = ni_rtsi_insn_config;
4600         ni_rtsi_init(dev);
4601
4602         if (board->reg_type & ni_reg_m_series_mask) {
4603                 counter_variant = ni_gpct_variant_m_series;
4604         } else {
4605                 counter_variant = ni_gpct_variant_e_series;
4606         }
4607         devpriv->counter_dev = ni_gpct_device_construct(dev,
4608                                                         &ni_gpct_write_register,
4609                                                         &ni_gpct_read_register,
4610                                                         counter_variant,
4611                                                         NUM_GPCT);
4612         /* General purpose counters */
4613         for (j = 0; j < NUM_GPCT; ++j) {
4614                 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4615                 s->type = COMEDI_SUBD_COUNTER;
4616                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4617                 s->n_chan = 3;
4618                 if (board->reg_type & ni_reg_m_series_mask)
4619                         s->maxdata = 0xffffffff;
4620                 else
4621                         s->maxdata = 0xffffff;
4622                 s->insn_read = &ni_gpct_insn_read;
4623                 s->insn_write = &ni_gpct_insn_write;
4624                 s->insn_config = &ni_gpct_insn_config;
4625 #ifdef PCIDMA
4626                 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4627                 s->do_cmd = &ni_gpct_cmd;
4628                 s->len_chanlist = 1;
4629                 s->do_cmdtest = &ni_gpct_cmdtest;
4630                 s->cancel = &ni_gpct_cancel;
4631                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4632 #endif
4633                 s->private = &devpriv->counter_dev->counters[j];
4634
4635                 devpriv->counter_dev->counters[j].chip_index = 0;
4636                 devpriv->counter_dev->counters[j].counter_index = j;
4637                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4638         }
4639
4640         /* Frequency output */
4641         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4642         s->type = COMEDI_SUBD_COUNTER;
4643         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4644         s->n_chan = 1;
4645         s->maxdata = 0xf;
4646         s->insn_read = &ni_freq_out_insn_read;
4647         s->insn_write = &ni_freq_out_insn_write;
4648         s->insn_config = &ni_freq_out_insn_config;
4649
4650         /* ai configuration */
4651         s = &dev->subdevices[NI_AI_SUBDEV];
4652         ni_ai_reset(dev, s);
4653         if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4654                 /*  BEAM is this needed for PCI-6143 ?? */
4655                 devpriv->clock_and_fout =
4656                     Slow_Internal_Time_Divide_By_2 |
4657                     Slow_Internal_Timebase |
4658                     Clock_To_Board_Divide_By_2 |
4659                     Clock_To_Board |
4660                     AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4661         } else {
4662                 devpriv->clock_and_fout =
4663                     Slow_Internal_Time_Divide_By_2 |
4664                     Slow_Internal_Timebase |
4665                     Clock_To_Board_Divide_By_2 | Clock_To_Board;
4666         }
4667         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4668                             Clock_and_FOUT_Register);
4669
4670         /* analog output configuration */
4671         s = &dev->subdevices[NI_AO_SUBDEV];
4672         ni_ao_reset(dev, s);
4673
4674         if (dev->irq) {
4675                 devpriv->stc_writew(dev,
4676                                     (IRQ_POLARITY ? Interrupt_Output_Polarity :
4677                                      0) | (Interrupt_Output_On_3_Pins & 0) |
4678                                     Interrupt_A_Enable | Interrupt_B_Enable |
4679                                     Interrupt_A_Output_Select(interrupt_pin
4680                                                               (dev->irq)) |
4681                                     Interrupt_B_Output_Select(interrupt_pin
4682                                                               (dev->irq)),
4683                                     Interrupt_Control_Register);
4684         }
4685
4686         /* DMA setup */
4687         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4688         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4689
4690         if (board->reg_type & ni_reg_6xxx_mask) {
4691                 ni_writeb(0, Magic_611x);
4692         } else if (board->reg_type & ni_reg_m_series_mask) {
4693                 int channel;
4694                 for (channel = 0; channel < board->n_aochan; ++channel) {
4695                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4696                         ni_writeb(0x0,
4697                                   M_Offset_AO_Reference_Attenuation(channel));
4698                 }
4699                 ni_writeb(0x0, M_Offset_AO_Calibration);
4700         }
4701
4702         printk("\n");
4703         return 0;
4704 }
4705
4706 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4707 {
4708         struct comedi_device *dev = (struct comedi_device *)arg;
4709         struct ni_private *devpriv __maybe_unused = dev->private;
4710
4711         if (dir) {
4712                 ni_writeb(data, Port_A + 2 * port);
4713                 return 0;
4714         } else {
4715                 return ni_readb(Port_A + 2 * port);
4716         }
4717 }
4718
4719 /*
4720         presents the EEPROM as a subdevice
4721 */
4722
4723 static int ni_eeprom_insn_read(struct comedi_device *dev,
4724                                struct comedi_subdevice *s,
4725                                struct comedi_insn *insn, unsigned int *data)
4726 {
4727         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4728
4729         return 1;
4730 }
4731
4732 /*
4733         reads bytes out of eeprom
4734 */
4735
4736 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4737 {
4738         struct ni_private *devpriv __maybe_unused = dev->private;
4739         int bit;
4740         int bitstring;
4741
4742         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4743         ni_writeb(0x04, Serial_Command);
4744         for (bit = 0x8000; bit; bit >>= 1) {
4745                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4746                           Serial_Command);
4747                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4748                           Serial_Command);
4749         }
4750         bitstring = 0;
4751         for (bit = 0x80; bit; bit >>= 1) {
4752                 ni_writeb(0x04, Serial_Command);
4753                 ni_writeb(0x05, Serial_Command);
4754                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4755         }
4756         ni_writeb(0x00, Serial_Command);
4757
4758         return bitstring;
4759 }
4760
4761 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4762                                         struct comedi_subdevice *s,
4763                                         struct comedi_insn *insn,
4764                                         unsigned int *data)
4765 {
4766         struct ni_private *devpriv = dev->private;
4767
4768         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4769
4770         return 1;
4771 }
4772
4773 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4774 {
4775         struct ni_private *devpriv = dev->private;
4776
4777         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4778         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4779         return 3;
4780 }
4781
4782 static int ni_m_series_pwm_config(struct comedi_device *dev,
4783                                   struct comedi_subdevice *s,
4784                                   struct comedi_insn *insn, unsigned int *data)
4785 {
4786         struct ni_private *devpriv = dev->private;
4787         unsigned up_count, down_count;
4788
4789         switch (data[0]) {
4790         case INSN_CONFIG_PWM_OUTPUT:
4791                 switch (data[1]) {
4792                 case TRIG_ROUND_NEAREST:
4793                         up_count =
4794                             (data[2] +
4795                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4796                         break;
4797                 case TRIG_ROUND_DOWN:
4798                         up_count = data[2] / devpriv->clock_ns;
4799                         break;
4800                 case TRIG_ROUND_UP:
4801                         up_count =
4802                             (data[2] + devpriv->clock_ns -
4803                              1) / devpriv->clock_ns;
4804                         break;
4805                 default:
4806                         return -EINVAL;
4807                         break;
4808                 }
4809                 switch (data[3]) {
4810                 case TRIG_ROUND_NEAREST:
4811                         down_count =
4812                             (data[4] +
4813                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4814                         break;
4815                 case TRIG_ROUND_DOWN:
4816                         down_count = data[4] / devpriv->clock_ns;
4817                         break;
4818                 case TRIG_ROUND_UP:
4819                         down_count =
4820                             (data[4] + devpriv->clock_ns -
4821                              1) / devpriv->clock_ns;
4822                         break;
4823                 default:
4824                         return -EINVAL;
4825                         break;
4826                 }
4827                 if (up_count * devpriv->clock_ns != data[2] ||
4828                     down_count * devpriv->clock_ns != data[4]) {
4829                         data[2] = up_count * devpriv->clock_ns;
4830                         data[4] = down_count * devpriv->clock_ns;
4831                         return -EAGAIN;
4832                 }
4833                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4834                           MSeries_Cal_PWM_Low_Time_Bits(down_count),
4835                           M_Offset_Cal_PWM);
4836                 devpriv->pwm_up_count = up_count;
4837                 devpriv->pwm_down_count = down_count;
4838                 return 5;
4839                 break;
4840         case INSN_CONFIG_GET_PWM_OUTPUT:
4841                 return ni_get_pwm_config(dev, data);
4842                 break;
4843         default:
4844                 return -EINVAL;
4845                 break;
4846         }
4847         return 0;
4848 }
4849
4850 static int ni_6143_pwm_config(struct comedi_device *dev,
4851                               struct comedi_subdevice *s,
4852                               struct comedi_insn *insn, unsigned int *data)
4853 {
4854         struct ni_private *devpriv = dev->private;
4855         unsigned up_count, down_count;
4856
4857         switch (data[0]) {
4858         case INSN_CONFIG_PWM_OUTPUT:
4859                 switch (data[1]) {
4860                 case TRIG_ROUND_NEAREST:
4861                         up_count =
4862                             (data[2] +
4863                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4864                         break;
4865                 case TRIG_ROUND_DOWN:
4866                         up_count = data[2] / devpriv->clock_ns;
4867                         break;
4868                 case TRIG_ROUND_UP:
4869                         up_count =
4870                             (data[2] + devpriv->clock_ns -
4871                              1) / devpriv->clock_ns;
4872                         break;
4873                 default:
4874                         return -EINVAL;
4875                         break;
4876                 }
4877                 switch (data[3]) {
4878                 case TRIG_ROUND_NEAREST:
4879                         down_count =
4880                             (data[4] +
4881                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4882                         break;
4883                 case TRIG_ROUND_DOWN:
4884                         down_count = data[4] / devpriv->clock_ns;
4885                         break;
4886                 case TRIG_ROUND_UP:
4887                         down_count =
4888                             (data[4] + devpriv->clock_ns -
4889                              1) / devpriv->clock_ns;
4890                         break;
4891                 default:
4892                         return -EINVAL;
4893                         break;
4894                 }
4895                 if (up_count * devpriv->clock_ns != data[2] ||
4896                     down_count * devpriv->clock_ns != data[4]) {
4897                         data[2] = up_count * devpriv->clock_ns;
4898                         data[4] = down_count * devpriv->clock_ns;
4899                         return -EAGAIN;
4900                 }
4901                 ni_writel(up_count, Calibration_HighTime_6143);
4902                 devpriv->pwm_up_count = up_count;
4903                 ni_writel(down_count, Calibration_LowTime_6143);
4904                 devpriv->pwm_down_count = down_count;
4905                 return 5;
4906                 break;
4907         case INSN_CONFIG_GET_PWM_OUTPUT:
4908                 return ni_get_pwm_config(dev, data);
4909         default:
4910                 return -EINVAL;
4911                 break;
4912         }
4913         return 0;
4914 }
4915
4916 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4917 /*
4918         calibration subdevice
4919 */
4920 static int ni_calib_insn_write(struct comedi_device *dev,
4921                                struct comedi_subdevice *s,
4922                                struct comedi_insn *insn, unsigned int *data)
4923 {
4924         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4925
4926         return 1;
4927 }
4928
4929 static int ni_calib_insn_read(struct comedi_device *dev,
4930                               struct comedi_subdevice *s,
4931                               struct comedi_insn *insn, unsigned int *data)
4932 {
4933         struct ni_private *devpriv = dev->private;
4934
4935         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4936
4937         return 1;
4938 }
4939
4940 static int pack_mb88341(int addr, int val, int *bitstring);
4941 static int pack_dac8800(int addr, int val, int *bitstring);
4942 static int pack_dac8043(int addr, int val, int *bitstring);
4943 static int pack_ad8522(int addr, int val, int *bitstring);
4944 static int pack_ad8804(int addr, int val, int *bitstring);
4945 static int pack_ad8842(int addr, int val, int *bitstring);
4946
4947 struct caldac_struct {
4948         int n_chans;
4949         int n_bits;
4950         int (*packbits) (int, int, int *);
4951 };
4952
4953 static struct caldac_struct caldacs[] = {
4954         [mb88341] = {12, 8, pack_mb88341},
4955         [dac8800] = {8, 8, pack_dac8800},
4956         [dac8043] = {1, 12, pack_dac8043},
4957         [ad8522] = {2, 12, pack_ad8522},
4958         [ad8804] = {12, 8, pack_ad8804},
4959         [ad8842] = {8, 8, pack_ad8842},
4960         [ad8804_debug] = {16, 8, pack_ad8804},
4961 };
4962
4963 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4964 {
4965         const struct ni_board_struct *board = comedi_board(dev);
4966         struct ni_private *devpriv = dev->private;
4967         int i, j;
4968         int n_dacs;
4969         int n_chans = 0;
4970         int n_bits;
4971         int diffbits = 0;
4972         int type;
4973         int chan;
4974
4975         type = board->caldac[0];
4976         if (type == caldac_none)
4977                 return;
4978         n_bits = caldacs[type].n_bits;
4979         for (i = 0; i < 3; i++) {
4980                 type = board->caldac[i];
4981                 if (type == caldac_none)
4982                         break;
4983                 if (caldacs[type].n_bits != n_bits)
4984                         diffbits = 1;
4985                 n_chans += caldacs[type].n_chans;
4986         }
4987         n_dacs = i;
4988         s->n_chan = n_chans;
4989
4990         if (diffbits) {
4991                 unsigned int *maxdata_list;
4992
4993                 if (n_chans > MAX_N_CALDACS) {
4994                         printk("BUG! MAX_N_CALDACS too small\n");
4995                 }
4996                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4997                 chan = 0;
4998                 for (i = 0; i < n_dacs; i++) {
4999                         type = board->caldac[i];
5000                         for (j = 0; j < caldacs[type].n_chans; j++) {
5001                                 maxdata_list[chan] =
5002                                     (1 << caldacs[type].n_bits) - 1;
5003                                 chan++;
5004                         }
5005                 }
5006
5007                 for (chan = 0; chan < s->n_chan; chan++)
5008                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5009         } else {
5010                 type = board->caldac[0];
5011                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5012
5013                 for (chan = 0; chan < s->n_chan; chan++)
5014                         ni_write_caldac(dev, i, s->maxdata / 2);
5015         }
5016 }
5017
5018 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5019 {
5020         const struct ni_board_struct *board = comedi_board(dev);
5021         struct ni_private *devpriv = dev->private;
5022         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5023         int i;
5024         int type;
5025
5026         /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5027         if (devpriv->caldacs[addr] == val)
5028                 return;
5029         devpriv->caldacs[addr] = val;
5030
5031         for (i = 0; i < 3; i++) {
5032                 type = board->caldac[i];
5033                 if (type == caldac_none)
5034                         break;
5035                 if (addr < caldacs[type].n_chans) {
5036                         bits = caldacs[type].packbits(addr, val, &bitstring);
5037                         loadbit = SerDacLd(i);
5038                         /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5039                         break;
5040                 }
5041                 addr -= caldacs[type].n_chans;
5042         }
5043
5044         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5045                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5046                 udelay(1);
5047                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5048                 udelay(1);
5049         }
5050         ni_writeb(loadbit, Serial_Command);
5051         udelay(1);
5052         ni_writeb(0, Serial_Command);
5053 }
5054
5055 static int pack_mb88341(int addr, int val, int *bitstring)
5056 {
5057         /*
5058            Fujitsu MB 88341
5059            Note that address bits are reversed.  Thanks to
5060            Ingo Keen for noticing this.
5061
5062            Note also that the 88341 expects address values from
5063            1-12, whereas we use channel numbers 0-11.  The NI
5064            docs use 1-12, also, so be careful here.
5065          */
5066         addr++;
5067         *bitstring = ((addr & 0x1) << 11) |
5068             ((addr & 0x2) << 9) |
5069             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5070         return 12;
5071 }
5072
5073 static int pack_dac8800(int addr, int val, int *bitstring)
5074 {
5075         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5076         return 11;
5077 }
5078
5079 static int pack_dac8043(int addr, int val, int *bitstring)
5080 {
5081         *bitstring = val & 0xfff;
5082         return 12;
5083 }
5084
5085 static int pack_ad8522(int addr, int val, int *bitstring)
5086 {
5087         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5088         return 16;
5089 }
5090
5091 static int pack_ad8804(int addr, int val, int *bitstring)
5092 {
5093         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5094         return 12;
5095 }
5096
5097 static int pack_ad8842(int addr, int val, int *bitstring)
5098 {
5099         *bitstring = ((addr + 1) << 8) | (val & 0xff);
5100         return 12;
5101 }
5102
5103 #if 0
5104 /*
5105  *      Read the GPCTs current value.
5106  */
5107 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5108 {
5109         unsigned int hi1, hi2, lo;
5110
5111         devpriv->gpct_command[chan] &= ~G_Save_Trace;
5112         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5113                             G_Command_Register(chan));
5114
5115         devpriv->gpct_command[chan] |= G_Save_Trace;
5116         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5117                             G_Command_Register(chan));
5118
5119         /* This procedure is used because the two registers cannot
5120          * be read atomically. */
5121         do {
5122                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5123                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5124                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5125         } while (hi1 != hi2);
5126
5127         return (hi1 << 16) | lo;
5128 }
5129
5130 static void GPCT_Reset(struct comedi_device *dev, int chan)
5131 {
5132         int temp_ack_reg = 0;
5133
5134         /* printk("GPCT_Reset..."); */
5135         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5136
5137         switch (chan) {
5138         case 0:
5139                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5140                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5141                             G0_TC_Interrupt_Enable, 0);
5142                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5143                             G0_Gate_Interrupt_Enable, 0);
5144                 temp_ack_reg |= G0_Gate_Error_Confirm;
5145                 temp_ack_reg |= G0_TC_Error_Confirm;
5146                 temp_ack_reg |= G0_TC_Interrupt_Ack;
5147                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5148                 devpriv->stc_writew(dev, temp_ack_reg,
5149                                     Interrupt_A_Ack_Register);
5150
5151                 /* problem...this interferes with the other ctr... */
5152                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5153                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5154                                     Analog_Trigger_Etc_Register);
5155                 break;
5156         case 1:
5157                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5158                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5159                             G1_TC_Interrupt_Enable, 0);
5160                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5161                             G0_Gate_Interrupt_Enable, 0);
5162                 temp_ack_reg |= G1_Gate_Error_Confirm;
5163                 temp_ack_reg |= G1_TC_Error_Confirm;
5164                 temp_ack_reg |= G1_TC_Interrupt_Ack;
5165                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5166                 devpriv->stc_writew(dev, temp_ack_reg,
5167                                     Interrupt_B_Ack_Register);
5168
5169                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5170                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5171                                     Analog_Trigger_Etc_Register);
5172                 break;
5173         }
5174
5175         devpriv->gpct_mode[chan] = 0;
5176         devpriv->gpct_input_select[chan] = 0;
5177         devpriv->gpct_command[chan] = 0;
5178
5179         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5180
5181         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5182                             G_Mode_Register(chan));
5183         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5184                             G_Input_Select_Register(chan));
5185         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5186
5187         /* printk("exit GPCT_Reset\n"); */
5188 }
5189
5190 #endif
5191
5192 static int ni_gpct_insn_config(struct comedi_device *dev,
5193                                struct comedi_subdevice *s,
5194                                struct comedi_insn *insn, unsigned int *data)
5195 {
5196         struct ni_gpct *counter = s->private;
5197         return ni_tio_insn_config(counter, insn, data);
5198 }
5199
5200 static int ni_gpct_insn_read(struct comedi_device *dev,
5201                              struct comedi_subdevice *s,
5202                              struct comedi_insn *insn, unsigned int *data)
5203 {
5204         struct ni_gpct *counter = s->private;
5205         return ni_tio_rinsn(counter, insn, data);
5206 }
5207
5208 static int ni_gpct_insn_write(struct comedi_device *dev,
5209                               struct comedi_subdevice *s,
5210                               struct comedi_insn *insn, unsigned int *data)
5211 {
5212         struct ni_gpct *counter = s->private;
5213         return ni_tio_winsn(counter, insn, data);
5214 }
5215
5216 #ifdef PCIDMA
5217 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5218 {
5219         int retval;
5220         struct ni_gpct *counter = s->private;
5221 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5222
5223         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5224                                               COMEDI_INPUT);
5225         if (retval) {
5226                 comedi_error(dev,
5227                              "no dma channel available for use by counter");
5228                 return retval;
5229         }
5230         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5231         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5232         retval = ni_tio_cmd(counter, s->async);
5233         return retval;
5234 }
5235 #endif
5236
5237 #ifdef PCIDMA
5238 static int ni_gpct_cmdtest(struct comedi_device *dev,
5239                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
5240 {
5241         struct ni_gpct *counter = s->private;
5242
5243         return ni_tio_cmdtest(counter, cmd);
5244         return -ENOTSUPP;
5245 }
5246 #endif
5247
5248 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5249 {
5250 #ifdef PCIDMA
5251         struct ni_gpct *counter = s->private;
5252         int retval;
5253
5254         retval = ni_tio_cancel(counter);
5255         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5256         ni_release_gpct_mite_channel(dev, counter->counter_index);
5257         return retval;
5258 #else
5259         return 0;
5260 #endif
5261 }
5262
5263 /*
5264  *
5265  *  Programmable Function Inputs
5266  *
5267  */
5268
5269 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5270                                        unsigned source)
5271 {
5272         struct ni_private *devpriv = dev->private;
5273         unsigned pfi_reg_index;
5274         unsigned array_offset;
5275
5276         if ((source & 0x1f) != source)
5277                 return -EINVAL;
5278         pfi_reg_index = 1 + chan / 3;
5279         array_offset = pfi_reg_index - 1;
5280         devpriv->pfi_output_select_reg[array_offset] &=
5281             ~MSeries_PFI_Output_Select_Mask(chan);
5282         devpriv->pfi_output_select_reg[array_offset] |=
5283             MSeries_PFI_Output_Select_Bits(chan, source);
5284         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5285                   M_Offset_PFI_Output_Select(pfi_reg_index));
5286         return 2;
5287 }
5288
5289 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5290                                   unsigned source)
5291 {
5292         /*  pre-m-series boards have fixed signals on pfi pins */
5293         if (source != ni_old_get_pfi_routing(dev, chan))
5294                 return -EINVAL;
5295         return 2;
5296 }
5297
5298 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5299                               unsigned source)
5300 {
5301         const struct ni_board_struct *board = comedi_board(dev);
5302
5303         if (board->reg_type & ni_reg_m_series_mask)
5304                 return ni_m_series_set_pfi_routing(dev, chan, source);
5305         else
5306                 return ni_old_set_pfi_routing(dev, chan, source);
5307 }
5308
5309 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5310                                             unsigned chan)
5311 {
5312         struct ni_private *devpriv = dev->private;
5313         const unsigned array_offset = chan / 3;
5314
5315         return MSeries_PFI_Output_Select_Source(chan,
5316                                                 devpriv->
5317                                                 pfi_output_select_reg
5318                                                 [array_offset]);
5319 }
5320
5321 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5322 {
5323         /*  pre-m-series boards have fixed signals on pfi pins */
5324         switch (chan) {
5325         case 0:
5326                 return NI_PFI_OUTPUT_AI_START1;
5327                 break;
5328         case 1:
5329                 return NI_PFI_OUTPUT_AI_START2;
5330                 break;
5331         case 2:
5332                 return NI_PFI_OUTPUT_AI_CONVERT;
5333                 break;
5334         case 3:
5335                 return NI_PFI_OUTPUT_G_SRC1;
5336                 break;
5337         case 4:
5338                 return NI_PFI_OUTPUT_G_GATE1;
5339                 break;
5340         case 5:
5341                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5342                 break;
5343         case 6:
5344                 return NI_PFI_OUTPUT_AO_START1;
5345                 break;
5346         case 7:
5347                 return NI_PFI_OUTPUT_AI_START_PULSE;
5348                 break;
5349         case 8:
5350                 return NI_PFI_OUTPUT_G_SRC0;
5351                 break;
5352         case 9:
5353                 return NI_PFI_OUTPUT_G_GATE0;
5354                 break;
5355         default:
5356                 printk("%s: bug, unhandled case in switch.\n", __func__);
5357                 break;
5358         }
5359         return 0;
5360 }
5361
5362 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5363 {
5364         const struct ni_board_struct *board = comedi_board(dev);
5365
5366         if (board->reg_type & ni_reg_m_series_mask)
5367                 return ni_m_series_get_pfi_routing(dev, chan);
5368         else
5369                 return ni_old_get_pfi_routing(dev, chan);
5370 }
5371
5372 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5373                             enum ni_pfi_filter_select filter)
5374 {
5375         const struct ni_board_struct *board = comedi_board(dev);
5376         struct ni_private *devpriv __maybe_unused = dev->private;
5377         unsigned bits;
5378
5379         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5380                 return -ENOTSUPP;
5381         }
5382         bits = ni_readl(M_Offset_PFI_Filter);
5383         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5384         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5385         ni_writel(bits, M_Offset_PFI_Filter);
5386         return 0;
5387 }
5388
5389 static int ni_pfi_insn_bits(struct comedi_device *dev,
5390                             struct comedi_subdevice *s,
5391                             struct comedi_insn *insn, unsigned int *data)
5392 {
5393         const struct ni_board_struct *board = comedi_board(dev);
5394         struct ni_private *devpriv __maybe_unused = dev->private;
5395
5396         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5397                 return -ENOTSUPP;
5398         }
5399         if (data[0]) {
5400                 s->state &= ~data[0];
5401                 s->state |= (data[0] & data[1]);
5402                 ni_writew(s->state, M_Offset_PFI_DO);
5403         }
5404         data[1] = ni_readw(M_Offset_PFI_DI);
5405         return insn->n;
5406 }
5407
5408 static int ni_pfi_insn_config(struct comedi_device *dev,
5409                               struct comedi_subdevice *s,
5410                               struct comedi_insn *insn, unsigned int *data)
5411 {
5412         struct ni_private *devpriv = dev->private;
5413         unsigned int chan;
5414
5415         if (insn->n < 1)
5416                 return -EINVAL;
5417
5418         chan = CR_CHAN(insn->chanspec);
5419
5420         switch (data[0]) {
5421         case COMEDI_OUTPUT:
5422                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5423                 break;
5424         case COMEDI_INPUT:
5425                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5426                 break;
5427         case INSN_CONFIG_DIO_QUERY:
5428                 data[1] =
5429                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5430                     COMEDI_OUTPUT : COMEDI_INPUT;
5431                 return 0;
5432                 break;
5433         case INSN_CONFIG_SET_ROUTING:
5434                 return ni_set_pfi_routing(dev, chan, data[1]);
5435                 break;
5436         case INSN_CONFIG_GET_ROUTING:
5437                 data[1] = ni_get_pfi_routing(dev, chan);
5438                 break;
5439         case INSN_CONFIG_FILTER:
5440                 return ni_config_filter(dev, chan, data[1]);
5441                 break;
5442         default:
5443                 return -EINVAL;
5444         }
5445         return 0;
5446 }
5447
5448 /*
5449  *
5450  *  NI RTSI Bus Functions
5451  *
5452  */
5453 static void ni_rtsi_init(struct comedi_device *dev)
5454 {
5455         const struct ni_board_struct *board = comedi_board(dev);
5456         struct ni_private *devpriv = dev->private;
5457
5458         /*  Initialises the RTSI bus signal switch to a default state */
5459
5460         /*  Set clock mode to internal */
5461         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5462         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5463                 printk("ni_set_master_clock failed, bug?");
5464         }
5465         /*  default internal lines routing to RTSI bus lines */
5466         devpriv->rtsi_trig_a_output_reg =
5467             RTSI_Trig_Output_Bits(0,
5468                                   NI_RTSI_OUTPUT_ADR_START1) |
5469             RTSI_Trig_Output_Bits(1,
5470                                   NI_RTSI_OUTPUT_ADR_START2) |
5471             RTSI_Trig_Output_Bits(2,
5472                                   NI_RTSI_OUTPUT_SCLKG) |
5473             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5474         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5475                             RTSI_Trig_A_Output_Register);
5476         devpriv->rtsi_trig_b_output_reg =
5477             RTSI_Trig_Output_Bits(4,
5478                                   NI_RTSI_OUTPUT_DA_START1) |
5479             RTSI_Trig_Output_Bits(5,
5480                                   NI_RTSI_OUTPUT_G_SRC0) |
5481             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5482         if (board->reg_type & ni_reg_m_series_mask)
5483                 devpriv->rtsi_trig_b_output_reg |=
5484                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5485         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5486                             RTSI_Trig_B_Output_Register);
5487
5488 /*
5489 * Sets the source and direction of the 4 on board lines
5490 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5491 */
5492 }
5493
5494 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5495                              struct comedi_subdevice *s,
5496                              struct comedi_insn *insn, unsigned int *data)
5497 {
5498         data[1] = 0;
5499
5500         return insn->n;
5501 }
5502
5503 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5504  * given an arbitrary frequency input clock */
5505 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5506                                          unsigned *freq_divider,
5507                                          unsigned *freq_multiplier,
5508                                          unsigned *actual_period_ns)
5509 {
5510         unsigned div;
5511         unsigned best_div = 1;
5512         static const unsigned max_div = 0x10;
5513         unsigned mult;
5514         unsigned best_mult = 1;
5515         static const unsigned max_mult = 0x100;
5516         static const unsigned pico_per_nano = 1000;
5517
5518         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5519         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5520          * 20 MHz for most timing clocks */
5521         static const unsigned target_picosec = 12500;
5522         static const unsigned fudge_factor_80_to_20Mhz = 4;
5523         int best_period_picosec = 0;
5524         for (div = 1; div <= max_div; ++div) {
5525                 for (mult = 1; mult <= max_mult; ++mult) {
5526                         unsigned new_period_ps =
5527                             (reference_picosec * div) / mult;
5528                         if (abs(new_period_ps - target_picosec) <
5529                             abs(best_period_picosec - target_picosec)) {
5530                                 best_period_picosec = new_period_ps;
5531                                 best_div = div;
5532                                 best_mult = mult;
5533                         }
5534                 }
5535         }
5536         if (best_period_picosec == 0) {
5537                 printk("%s: bug, failed to find pll parameters\n", __func__);
5538                 return -EIO;
5539         }
5540         *freq_divider = best_div;
5541         *freq_multiplier = best_mult;
5542         *actual_period_ns =
5543             (best_period_picosec * fudge_factor_80_to_20Mhz +
5544              (pico_per_nano / 2)) / pico_per_nano;
5545         return 0;
5546 }
5547
5548 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5549 {
5550         const struct ni_board_struct *board = comedi_board(dev);
5551
5552         if (board->reg_type & ni_reg_m_series_mask)
5553                 return 8;
5554         else
5555                 return 7;
5556 }
5557
5558 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5559                                            unsigned source, unsigned period_ns)
5560 {
5561         struct ni_private *devpriv = dev->private;
5562         static const unsigned min_period_ns = 50;
5563         static const unsigned max_period_ns = 1000;
5564         static const unsigned timeout = 1000;
5565         unsigned pll_control_bits;
5566         unsigned freq_divider;
5567         unsigned freq_multiplier;
5568         unsigned i;
5569         int retval;
5570
5571         if (source == NI_MIO_PLL_PXI10_CLOCK)
5572                 period_ns = 100;
5573         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5574         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5575                 printk
5576                     ("%s: you must specify an input clock frequency between %i and %i nanosec "
5577                      "for the phased-lock loop.\n", __func__,
5578                      min_period_ns, max_period_ns);
5579                 return -EINVAL;
5580         }
5581         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5582         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5583                             RTSI_Trig_Direction_Register);
5584         pll_control_bits =
5585             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5586         devpriv->clock_and_fout2 |=
5587             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5588         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5589         switch (source) {
5590         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5591                 devpriv->clock_and_fout2 |=
5592                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5593                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5594                                                        &freq_multiplier,
5595                                                        &devpriv->clock_ns);
5596                 if (retval < 0)
5597                         return retval;
5598                 break;
5599         case NI_MIO_PLL_PXI10_CLOCK:
5600                 /* pxi clock is 10MHz */
5601                 devpriv->clock_and_fout2 |=
5602                     MSeries_PLL_In_Source_Select_PXI_Clock10;
5603                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5604                                                        &freq_multiplier,
5605                                                        &devpriv->clock_ns);
5606                 if (retval < 0)
5607                         return retval;
5608                 break;
5609         default:
5610                 {
5611                         unsigned rtsi_channel;
5612                         static const unsigned max_rtsi_channel = 7;
5613                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5614                              ++rtsi_channel) {
5615                                 if (source ==
5616                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5617                                         devpriv->clock_and_fout2 |=
5618                                             MSeries_PLL_In_Source_Select_RTSI_Bits
5619                                             (rtsi_channel);
5620                                         break;
5621                                 }
5622                         }
5623                         if (rtsi_channel > max_rtsi_channel)
5624                                 return -EINVAL;
5625                         retval = ni_mseries_get_pll_parameters(period_ns,
5626                                                                &freq_divider,
5627                                                                &freq_multiplier,
5628                                                                &devpriv->
5629                                                                clock_ns);
5630                         if (retval < 0)
5631                                 return retval;
5632                 }
5633                 break;
5634         }
5635         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5636         pll_control_bits |=
5637             MSeries_PLL_Divisor_Bits(freq_divider) |
5638             MSeries_PLL_Multiplier_Bits(freq_multiplier);
5639
5640         /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5641          * freq_divider, freq_multiplier, pll_control_bits); */
5642         /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5643         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5644         devpriv->clock_source = source;
5645         /* it seems to typically take a few hundred microseconds for PLL to lock */
5646         for (i = 0; i < timeout; ++i) {
5647                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5648                         break;
5649                 }
5650                 udelay(1);
5651         }
5652         if (i == timeout) {
5653                 printk
5654                     ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5655                      __func__, source, period_ns);
5656                 return -ETIMEDOUT;
5657         }
5658         return 3;
5659 }
5660
5661 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5662                                unsigned period_ns)
5663 {
5664         const struct ni_board_struct *board = comedi_board(dev);
5665         struct ni_private *devpriv = dev->private;
5666
5667         if (source == NI_MIO_INTERNAL_CLOCK) {
5668                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5669                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5670                                     RTSI_Trig_Direction_Register);
5671                 devpriv->clock_ns = TIMEBASE_1_NS;
5672                 if (board->reg_type & ni_reg_m_series_mask) {
5673                         devpriv->clock_and_fout2 &=
5674                             ~(MSeries_Timebase1_Select_Bit |
5675                               MSeries_Timebase3_Select_Bit);
5676                         ni_writew(devpriv->clock_and_fout2,
5677                                   M_Offset_Clock_and_Fout2);
5678                         ni_writew(0, M_Offset_PLL_Control);
5679                 }
5680                 devpriv->clock_source = source;
5681         } else {
5682                 if (board->reg_type & ni_reg_m_series_mask) {
5683                         return ni_mseries_set_pll_master_clock(dev, source,
5684                                                                period_ns);
5685                 } else {
5686                         if (source == NI_MIO_RTSI_CLOCK) {
5687                                 devpriv->rtsi_trig_direction_reg |=
5688                                     Use_RTSI_Clock_Bit;
5689                                 devpriv->stc_writew(dev,
5690                                                     devpriv->
5691                                                     rtsi_trig_direction_reg,
5692                                                     RTSI_Trig_Direction_Register);
5693                                 if (period_ns == 0) {
5694                                         printk
5695                                             ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5696                                              __func__);
5697                                         return -EINVAL;
5698                                 } else {
5699                                         devpriv->clock_ns = period_ns;
5700                                 }
5701                                 devpriv->clock_source = source;
5702                         } else
5703                                 return -EINVAL;
5704                 }
5705         }
5706         return 3;
5707 }
5708
5709 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5710                                        unsigned source)
5711 {
5712         const struct ni_board_struct *board = comedi_board(dev);
5713
5714         if (chan >= num_configurable_rtsi_channels(dev)) {
5715                 if (chan == old_RTSI_clock_channel) {
5716                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5717                                 return 1;
5718                         else {
5719                                 printk
5720                                     ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5721                                      __func__, chan, old_RTSI_clock_channel);
5722                                 return 0;
5723                         }
5724                 }
5725                 return 0;
5726         }
5727         switch (source) {
5728         case NI_RTSI_OUTPUT_ADR_START1:
5729         case NI_RTSI_OUTPUT_ADR_START2:
5730         case NI_RTSI_OUTPUT_SCLKG:
5731         case NI_RTSI_OUTPUT_DACUPDN:
5732         case NI_RTSI_OUTPUT_DA_START1:
5733         case NI_RTSI_OUTPUT_G_SRC0:
5734         case NI_RTSI_OUTPUT_G_GATE0:
5735         case NI_RTSI_OUTPUT_RGOUT0:
5736         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5737                 return 1;
5738                 break;
5739         case NI_RTSI_OUTPUT_RTSI_OSC:
5740                 if (board->reg_type & ni_reg_m_series_mask)
5741                         return 1;
5742                 else
5743                         return 0;
5744                 break;
5745         default:
5746                 return 0;
5747                 break;
5748         }
5749 }
5750
5751 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5752                                unsigned source)
5753 {
5754         struct ni_private *devpriv = dev->private;
5755
5756         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5757                 return -EINVAL;
5758         if (chan < 4) {
5759                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5760                 devpriv->rtsi_trig_a_output_reg |=
5761                     RTSI_Trig_Output_Bits(chan, source);
5762                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5763                                     RTSI_Trig_A_Output_Register);
5764         } else if (chan < 8) {
5765                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5766                 devpriv->rtsi_trig_b_output_reg |=
5767                     RTSI_Trig_Output_Bits(chan, source);
5768                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5769                                     RTSI_Trig_B_Output_Register);
5770         }
5771         return 2;
5772 }
5773
5774 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5775 {
5776         struct ni_private *devpriv = dev->private;
5777
5778         if (chan < 4) {
5779                 return RTSI_Trig_Output_Source(chan,
5780                                                devpriv->rtsi_trig_a_output_reg);
5781         } else if (chan < num_configurable_rtsi_channels(dev)) {
5782                 return RTSI_Trig_Output_Source(chan,
5783                                                devpriv->rtsi_trig_b_output_reg);
5784         } else {
5785                 if (chan == old_RTSI_clock_channel)
5786                         return NI_RTSI_OUTPUT_RTSI_OSC;
5787                 printk("%s: bug! should never get here?\n", __func__);
5788                 return 0;
5789         }
5790 }
5791
5792 static int ni_rtsi_insn_config(struct comedi_device *dev,
5793                                struct comedi_subdevice *s,
5794                                struct comedi_insn *insn, unsigned int *data)
5795 {
5796         const struct ni_board_struct *board = comedi_board(dev);
5797         struct ni_private *devpriv = dev->private;
5798         unsigned int chan = CR_CHAN(insn->chanspec);
5799
5800         switch (data[0]) {
5801         case INSN_CONFIG_DIO_OUTPUT:
5802                 if (chan < num_configurable_rtsi_channels(dev)) {
5803                         devpriv->rtsi_trig_direction_reg |=
5804                             RTSI_Output_Bit(chan,
5805                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5806                 } else if (chan == old_RTSI_clock_channel) {
5807                         devpriv->rtsi_trig_direction_reg |=
5808                             Drive_RTSI_Clock_Bit;
5809                 }
5810                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5811                                     RTSI_Trig_Direction_Register);
5812                 break;
5813         case INSN_CONFIG_DIO_INPUT:
5814                 if (chan < num_configurable_rtsi_channels(dev)) {
5815                         devpriv->rtsi_trig_direction_reg &=
5816                             ~RTSI_Output_Bit(chan,
5817                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5818                 } else if (chan == old_RTSI_clock_channel) {
5819                         devpriv->rtsi_trig_direction_reg &=
5820                             ~Drive_RTSI_Clock_Bit;
5821                 }
5822                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5823                                     RTSI_Trig_Direction_Register);
5824                 break;
5825         case INSN_CONFIG_DIO_QUERY:
5826                 if (chan < num_configurable_rtsi_channels(dev)) {
5827                         data[1] =
5828                             (devpriv->rtsi_trig_direction_reg &
5829                              RTSI_Output_Bit(chan,
5830                                 (board->reg_type & ni_reg_m_series_mask) != 0))
5831                                 ? INSN_CONFIG_DIO_OUTPUT
5832                                 : INSN_CONFIG_DIO_INPUT;
5833                 } else if (chan == old_RTSI_clock_channel) {
5834                         data[1] =
5835                             (devpriv->rtsi_trig_direction_reg &
5836                              Drive_RTSI_Clock_Bit)
5837                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5838                 }
5839                 return 2;
5840                 break;
5841         case INSN_CONFIG_SET_CLOCK_SRC:
5842                 return ni_set_master_clock(dev, data[1], data[2]);
5843                 break;
5844         case INSN_CONFIG_GET_CLOCK_SRC:
5845                 data[1] = devpriv->clock_source;
5846                 data[2] = devpriv->clock_ns;
5847                 return 3;
5848                 break;
5849         case INSN_CONFIG_SET_ROUTING:
5850                 return ni_set_rtsi_routing(dev, chan, data[1]);
5851                 break;
5852         case INSN_CONFIG_GET_ROUTING:
5853                 data[1] = ni_get_rtsi_routing(dev, chan);
5854                 return 2;
5855                 break;
5856         default:
5857                 return -EINVAL;
5858                 break;
5859         }
5860         return 1;
5861 }
5862
5863 static int cs5529_wait_for_idle(struct comedi_device *dev)
5864 {
5865         unsigned short status;
5866         const int timeout = HZ;
5867         int i;
5868
5869         for (i = 0; i < timeout; i++) {
5870                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5871                 if ((status & CSS_ADC_BUSY) == 0) {
5872                         break;
5873                 }
5874                 set_current_state(TASK_INTERRUPTIBLE);
5875                 if (schedule_timeout(1)) {
5876                         return -EIO;
5877                 }
5878         }
5879 /* printk("looped %i times waiting for idle\n", i); */
5880         if (i == timeout) {
5881                 printk("%s: %s: timeout\n", __FILE__, __func__);
5882                 return -ETIME;
5883         }
5884         return 0;
5885 }
5886
5887 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5888 {
5889         static const int timeout = 100;
5890         int i;
5891
5892         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5893         /* give time for command to start being serially clocked into cs5529.
5894          * this insures that the CSS_ADC_BUSY bit will get properly
5895          * set before we exit this function.
5896          */
5897         for (i = 0; i < timeout; i++) {
5898                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5899                         break;
5900                 udelay(1);
5901         }
5902 /* printk("looped %i times writing command to cs5529\n", i); */
5903         if (i == timeout) {
5904                 comedi_error(dev, "possible problem - never saw adc go busy?");
5905         }
5906 }
5907
5908 /* write to cs5529 register */
5909 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5910                                 unsigned int reg_select_bits)
5911 {
5912         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5913                        CAL_ADC_Config_Data_High_Word_67xx);
5914         ni_ao_win_outw(dev, (value & 0xffff),
5915                        CAL_ADC_Config_Data_Low_Word_67xx);
5916         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5917         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5918         if (cs5529_wait_for_idle(dev))
5919                 comedi_error(dev, "time or signal in cs5529_config_write()");
5920 }
5921
5922 #ifdef NI_CS5529_DEBUG
5923 /* read from cs5529 register */
5924 static unsigned int cs5529_config_read(struct comedi_device *dev,
5925                                        unsigned int reg_select_bits)
5926 {
5927         unsigned int value;
5928
5929         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5930         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5931         if (cs5529_wait_for_idle(dev))
5932                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5933         value = (ni_ao_win_inw(dev,
5934                                CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5935             0xff0000;
5936         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5937         return value;
5938 }
5939 #endif
5940
5941 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5942 {
5943         int retval;
5944         unsigned short status;
5945
5946         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5947         retval = cs5529_wait_for_idle(dev);
5948         if (retval) {
5949                 comedi_error(dev,
5950                              "timeout or signal in cs5529_do_conversion()");
5951                 return -ETIME;
5952         }
5953         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5954         if (status & CSS_OSC_DETECT) {
5955                 printk
5956                     ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5957                 return -EIO;
5958         }
5959         if (status & CSS_OVERRANGE) {
5960                 printk
5961                     ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5962         }
5963         if (data) {
5964                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5965                 /* cs5529 returns 16 bit signed data in bipolar mode */
5966                 *data ^= (1 << 15);
5967         }
5968         return 0;
5969 }
5970
5971 static int cs5529_ai_insn_read(struct comedi_device *dev,
5972                                struct comedi_subdevice *s,
5973                                struct comedi_insn *insn, unsigned int *data)
5974 {
5975         int n, retval;
5976         unsigned short sample;
5977         unsigned int channel_select;
5978         const unsigned int INTERNAL_REF = 0x1000;
5979
5980         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5981          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5982          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5983         if (insn->chanspec & CR_ALT_SOURCE)
5984                 channel_select = INTERNAL_REF;
5985         else
5986                 channel_select = CR_CHAN(insn->chanspec);
5987         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5988
5989         for (n = 0; n < insn->n; n++) {
5990                 retval = cs5529_do_conversion(dev, &sample);
5991                 if (retval < 0)
5992                         return retval;
5993                 data[n] = sample;
5994         }
5995         return insn->n;
5996 }
5997
5998 static int init_cs5529(struct comedi_device *dev)
5999 {
6000         unsigned int config_bits =
6001             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6002
6003 #if 1
6004         /* do self-calibration */
6005         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6006                             CSCMD_CONFIG_REGISTER);
6007         /* need to force a conversion for calibration to run */
6008         cs5529_do_conversion(dev, NULL);
6009 #else
6010         /* force gain calibration to 1 */
6011         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6012         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6013                             CSCMD_CONFIG_REGISTER);
6014         if (cs5529_wait_for_idle(dev))
6015                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6016 #endif
6017 #ifdef NI_CS5529_DEBUG
6018         printk("config: 0x%x\n", cs5529_config_read(dev,
6019                                                     CSCMD_CONFIG_REGISTER));
6020         printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6021         printk("offset: 0x%x\n", cs5529_config_read(dev,
6022                                                     CSCMD_OFFSET_REGISTER));
6023 #endif
6024         return 0;
6025 }