drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 /* #define DEBUG_INTERRUPT */
  56 /* #define DEBUG_STATUS_A */
  57 /* #define DEBUG_STATUS_B */
  58
  59 #include <linux/interrupt.h>
  60 #include <linux/sched.h>
  61 #include <linux/delay.h>
  62 #include "8255.h"
  63 #include "mite.h"
  64 #include "comedi_fc.h"
  65
  66 #ifndef MDPRINTK
  67 #define MDPRINTK(format, args...)
  68 #endif
  69
  70 /* A timeout count */
  71 #define NI_TIMEOUT 1000
  72 static const unsigned old_RTSI_clock_channel = 7;
  73
  74 /* Note: this table must match the ai_gain_* definitions */
  75 static const short ni_gainlkup[][16] = {
  76         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  77                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  78         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  79         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  80                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  81         [ai_gain_4] = {0, 1, 4, 7},
  82         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  83                           0x003, 0x004, 0x005, 0x006},
  84         [ai_gain_622x] = {0, 1, 4, 5},
  85         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  86         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  87 };
  88
  89 static const struct comedi_lrange range_ni_E_ai = { 16, {
  90                                                          RANGE(-10, 10),
  91                                                          RANGE(-5, 5),
  92                                                          RANGE(-2.5, 2.5),
  93                                                          RANGE(-1, 1),
  94                                                          RANGE(-0.5, 0.5),
  95                                                          RANGE(-0.25, 0.25),
  96                                                          RANGE(-0.1, 0.1),
  97                                                          RANGE(-0.05, 0.05),
  98                                                          RANGE(0, 20),
  99                                                          RANGE(0, 10),
 100                                                          RANGE(0, 5),
 101                                                          RANGE(0, 2),
 102                                                          RANGE(0, 1),
 103                                                          RANGE(0, 0.5),
 104                                                          RANGE(0, 0.2),
 105                                                          RANGE(0, 0.1),
 106                                                          }
 107 };
 108
 109 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
 110                                                                 RANGE(-10, 10),
 111                                                                 RANGE(-5, 5),
 112                                                                 RANGE(-1, 1),
 113                                                                 RANGE(-0.1,
 114                                                                       0.1),
 115                                                                 RANGE(0, 10),
 116                                                                 RANGE(0, 5),
 117                                                                 RANGE(0, 1),
 118                                                                 RANGE(0, 0.1),
 119                                                                 }
 120 };
 121
 122 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
 123                                                                    RANGE(-10,
 124                                                                          10),
 125                                                                    RANGE(-5, 5),
 126                                                                    RANGE(-2, 2),
 127                                                                    RANGE(-1, 1),
 128                                                                    RANGE(-0.5,
 129                                                                          0.5),
 130                                                                    RANGE(-0.2,
 131                                                                          0.2),
 132                                                                    RANGE(-0.1,
 133                                                                          0.1),
 134                                                                    RANGE(0, 10),
 135                                                                    RANGE(0, 5),
 136                                                                    RANGE(0, 2),
 137                                                                    RANGE(0, 1),
 138                                                                    RANGE(0,
 139                                                                          0.5),
 140                                                                    RANGE(0,
 141                                                                          0.2),
 142                                                                    RANGE(0,
 143                                                                          0.1),
 144                                                                    }
 145 };
 146
 147 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
 148                                                                  RANGE(-10, 10),
 149                                                                  RANGE(-5, 5),
 150                                                                  RANGE(-0.5,
 151                                                                        0.5),
 152                                                                  RANGE(-0.05,
 153                                                                        0.05),
 154                                                                  }
 155 };
 156
 157 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
 158                                                              RANGE(-50, 50),
 159                                                              RANGE(-20, 20),
 160                                                              RANGE(-10, 10),
 161                                                              RANGE(-5, 5),
 162                                                              RANGE(-2, 2),
 163                                                              RANGE(-1, 1),
 164                                                              RANGE(-0.5, 0.5),
 165                                                              RANGE(-0.2, 0.2),
 166                                                              }
 167 };
 168
 169 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
 170                                                              RANGE(-10, 10),
 171                                                              RANGE(-5, 5),
 172                                                              RANGE(-1, 1),
 173                                                              RANGE(-0.2, 0.2),
 174                                                              }
 175 };
 176
 177 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
 178                                                              RANGE(-10, 10),
 179                                                              RANGE(-5, 5),
 180                                                              RANGE(-2, 2),
 181                                                              RANGE(-1, 1),
 182                                                              RANGE(-0.5, 0.5),
 183                                                              RANGE(-0.2, 0.2),
 184                                                              RANGE(-0.1, 0.1),
 185                                                              }
 186 };
 187
 188 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
 189                                                             RANGE(-10, 10),
 190                                                             RANGE(0, 10),
 191                                                             RANGE_ext(-1, 1),
 192                                                             RANGE_ext(0, 1),
 193                                                             }
 194 };
 195
 196 static const struct comedi_lrange *const ni_range_lkup[] = {
 197         [ai_gain_16] = &range_ni_E_ai,
 198         [ai_gain_8] = &range_ni_E_ai_limited,
 199         [ai_gain_14] = &range_ni_E_ai_limited14,
 200         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 201         [ai_gain_611x] = &range_ni_E_ai_611x,
 202         [ai_gain_622x] = &range_ni_M_ai_622x,
 203         [ai_gain_628x] = &range_ni_M_ai_628x,
 204         [ai_gain_6143] = &range_bipolar5
 205 };
 206
 207 static int ni_dio_insn_config(struct comedi_device *dev,
 208                               struct comedi_subdevice *s,
 209                               struct comedi_insn *insn, unsigned int *data);
 210 static int ni_dio_insn_bits(struct comedi_device *dev,
 211                             struct comedi_subdevice *s,
 212                             struct comedi_insn *insn, unsigned int *data);
 213 static int ni_cdio_cmdtest(struct comedi_device *dev,
 214                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 215 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 216 static int ni_cdio_cancel(struct comedi_device *dev,
 217                           struct comedi_subdevice *s);
 218 static void handle_cdio_interrupt(struct comedi_device *dev);
 219 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 220                           unsigned int trignum);
 221
 222 static int ni_serial_insn_config(struct comedi_device *dev,
 223                                  struct comedi_subdevice *s,
 224                                  struct comedi_insn *insn, unsigned int *data);
 225 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 226                                    struct comedi_subdevice *s,
 227                                    unsigned char data_out,
 228                                    unsigned char *data_in);
 229 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 230                                    struct comedi_subdevice *s,
 231                                    unsigned char data_out,
 232                                    unsigned char *data_in);
 233
 234 static int ni_calib_insn_read(struct comedi_device *dev,
 235                               struct comedi_subdevice *s,
 236                               struct comedi_insn *insn, unsigned int *data);
 237 static int ni_calib_insn_write(struct comedi_device *dev,
 238                                struct comedi_subdevice *s,
 239                                struct comedi_insn *insn, unsigned int *data);
 240
 241 static int ni_eeprom_insn_read(struct comedi_device *dev,
 242                                struct comedi_subdevice *s,
 243                                struct comedi_insn *insn, unsigned int *data);
 244 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 245                                         struct comedi_subdevice *s,
 246                                         struct comedi_insn *insn,
 247                                         unsigned int *data);
 248
 249 static int ni_pfi_insn_bits(struct comedi_device *dev,
 250                             struct comedi_subdevice *s,
 251                             struct comedi_insn *insn, unsigned int *data);
 252 static int ni_pfi_insn_config(struct comedi_device *dev,
 253                               struct comedi_subdevice *s,
 254                               struct comedi_insn *insn, unsigned int *data);
 255 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 256                                        unsigned chan);
 257
 258 static void ni_rtsi_init(struct comedi_device *dev);
 259 static int ni_rtsi_insn_bits(struct comedi_device *dev,
 260                              struct comedi_subdevice *s,
 261                              struct comedi_insn *insn, unsigned int *data);
 262 static int ni_rtsi_insn_config(struct comedi_device *dev,
 263                                struct comedi_subdevice *s,
 264                                struct comedi_insn *insn, unsigned int *data);
 265
 266 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 267 static int ni_read_eeprom(struct comedi_device *dev, int addr);
 268
 269 #ifdef DEBUG_STATUS_A
 270 static void ni_mio_print_status_a(int status);
 271 #else
 272 #define ni_mio_print_status_a(a)
 273 #endif
 274 #ifdef DEBUG_STATUS_B
 275 static void ni_mio_print_status_b(int status);
 276 #else
 277 #define ni_mio_print_status_b(a)
 278 #endif
 279
 280 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 281 #ifndef PCIDMA
 282 static void ni_handle_fifo_half_full(struct comedi_device *dev);
 283 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 284                                  struct comedi_subdevice *s);
 285 #endif
 286 static void ni_handle_fifo_dregs(struct comedi_device *dev);
 287 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 288                          unsigned int trignum);
 289 static void ni_load_channelgain_list(struct comedi_device *dev,
 290                                      unsigned int n_chan, unsigned int *list);
 291 static void shutdown_ai_command(struct comedi_device *dev);
 292
 293 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 294                          unsigned int trignum);
 295
 296 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 297
 298 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 299
 300 static int ni_gpct_insn_write(struct comedi_device *dev,
 301                               struct comedi_subdevice *s,
 302                               struct comedi_insn *insn, unsigned int *data);
 303 static int ni_gpct_insn_read(struct comedi_device *dev,
 304                              struct comedi_subdevice *s,
 305                              struct comedi_insn *insn, unsigned int *data);
 306 static int ni_gpct_insn_config(struct comedi_device *dev,
 307                                struct comedi_subdevice *s,
 308                                struct comedi_insn *insn, unsigned int *data);
 309 #ifdef PCIDMA
 310 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 311 static int ni_gpct_cmdtest(struct comedi_device *dev,
 312                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 313 #endif
 314 static int ni_gpct_cancel(struct comedi_device *dev,
 315                           struct comedi_subdevice *s);
 316 static void handle_gpct_interrupt(struct comedi_device *dev,
 317                                   unsigned short counter_index);
 318
 319 static int init_cs5529(struct comedi_device *dev);
 320 static int cs5529_do_conversion(struct comedi_device *dev,
 321                                 unsigned short *data);
 322 static int cs5529_ai_insn_read(struct comedi_device *dev,
 323                                struct comedi_subdevice *s,
 324                                struct comedi_insn *insn, unsigned int *data);
 325 #ifdef NI_CS5529_DEBUG
 326 static unsigned int cs5529_config_read(struct comedi_device *dev,
 327                                        unsigned int reg_select_bits);
 328 #endif
 329 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 330                                 unsigned int reg_select_bits);
 331
 332 static int ni_m_series_pwm_config(struct comedi_device *dev,
 333                                   struct comedi_subdevice *s,
 334                                   struct comedi_insn *insn, unsigned int *data);
 335 static int ni_6143_pwm_config(struct comedi_device *dev,
 336                               struct comedi_subdevice *s,
 337                               struct comedi_insn *insn, unsigned int *data);
 338
 339 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 340                                unsigned period_ns);
 341 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 342 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 343
 344 enum aimodes {
 345         AIMODE_NONE = 0,
 346         AIMODE_HALF_FULL = 1,
 347         AIMODE_SCAN = 2,
 348         AIMODE_SAMPLE = 3,
 349 };
 350
 351 enum ni_common_subdevices {
 352         NI_AI_SUBDEV,
 353         NI_AO_SUBDEV,
 354         NI_DIO_SUBDEV,
 355         NI_8255_DIO_SUBDEV,
 356         NI_UNUSED_SUBDEV,
 357         NI_CALIBRATION_SUBDEV,
 358         NI_EEPROM_SUBDEV,
 359         NI_PFI_DIO_SUBDEV,
 360         NI_CS5529_CALIBRATION_SUBDEV,
 361         NI_SERIAL_SUBDEV,
 362         NI_RTSI_SUBDEV,
 363         NI_GPCT0_SUBDEV,
 364         NI_GPCT1_SUBDEV,
 365         NI_FREQ_OUT_SUBDEV,
 366         NI_NUM_SUBDEVICES
 367 };
 368 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 369 {
 370         switch (counter_index) {
 371         case 0:
 372                 return NI_GPCT0_SUBDEV;
 373                 break;
 374         case 1:
 375                 return NI_GPCT1_SUBDEV;
 376                 break;
 377         default:
 378                 break;
 379         }
 380         BUG();
 381         return NI_GPCT0_SUBDEV;
 382 }
 383
 384 enum timebase_nanoseconds {
 385         TIMEBASE_1_NS = 50,
 386         TIMEBASE_2_NS = 10000
 387 };
 388
 389 #define SERIAL_DISABLED         0
 390 #define SERIAL_600NS            600
 391 #define SERIAL_1_2US            1200
 392 #define SERIAL_10US                     10000
 393
 394 static const int num_adc_stages_611x = 3;
 395
 396 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 397                                unsigned ai_mite_status);
 398 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 399                                unsigned ao_mite_status);
 400 static void get_last_sample_611x(struct comedi_device *dev);
 401 static void get_last_sample_6143(struct comedi_device *dev);
 402
 403 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 404                                    unsigned bit_mask, unsigned bit_values)
 405 {
 406         struct ni_private *devpriv = dev->private;
 407         unsigned long flags;
 408
 409         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 410         switch (reg) {
 411         case Interrupt_A_Enable_Register:
 412                 devpriv->int_a_enable_reg &= ~bit_mask;
 413                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 414                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 415                                     Interrupt_A_Enable_Register);
 416                 break;
 417         case Interrupt_B_Enable_Register:
 418                 devpriv->int_b_enable_reg &= ~bit_mask;
 419                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 420                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 421                                     Interrupt_B_Enable_Register);
 422                 break;
 423         case IO_Bidirection_Pin_Register:
 424                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 425                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 426                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 427                                     IO_Bidirection_Pin_Register);
 428                 break;
 429         case AI_AO_Select:
 430                 devpriv->ai_ao_select_reg &= ~bit_mask;
 431                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 432                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 433                 break;
 434         case G0_G1_Select:
 435                 devpriv->g0_g1_select_reg &= ~bit_mask;
 436                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 437                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 438                 break;
 439         default:
 440                 printk("Warning %s() called with invalid register\n", __func__);
 441                 printk("reg is %d\n", reg);
 442                 break;
 443         }
 444         mmiowb();
 445         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 446 }
 447
 448 #ifdef PCIDMA
 449 static int ni_ai_drain_dma(struct comedi_device *dev);
 450
 451 /* DMA channel setup */
 452
 453 /* negative channel means no channel */
 454 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 455 {
 456         unsigned bitfield;
 457
 458         if (channel >= 0) {
 459                 bitfield =
 460                     (ni_stc_dma_channel_select_bitfield(channel) <<
 461                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 462         } else {
 463                 bitfield = 0;
 464         }
 465         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 466 }
 467
 468 /* negative channel means no channel */
 469 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 470 {
 471         unsigned bitfield;
 472
 473         if (channel >= 0) {
 474                 bitfield =
 475                     (ni_stc_dma_channel_select_bitfield(channel) <<
 476                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 477         } else {
 478                 bitfield = 0;
 479         }
 480         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 481 }
 482
 483 /* negative mite_channel means no channel */
 484 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 485                                            unsigned gpct_index,
 486                                            int mite_channel)
 487 {
 488         unsigned bitfield;
 489
 490         if (mite_channel >= 0) {
 491                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 492         } else {
 493                 bitfield = 0;
 494         }
 495         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 496                         bitfield);
 497 }
 498
 499 /* negative mite_channel means no channel */
 500 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 501                                           int mite_channel)
 502 {
 503         struct ni_private *devpriv = dev->private;
 504         unsigned long flags;
 505
 506         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 507         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 508         if (mite_channel >= 0) {
 509                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 510                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 511                    Definitely works for dma channels 0 and 1. */
 512                 devpriv->cdio_dma_select_reg |=
 513                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 514                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 515         }
 516         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 517         mmiowb();
 518         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 519 }
 520
 521 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 522 {
 523         struct ni_private *devpriv = dev->private;
 524         unsigned long flags;
 525
 526         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 527         BUG_ON(devpriv->ai_mite_chan);
 528         devpriv->ai_mite_chan =
 529             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 530         if (devpriv->ai_mite_chan == NULL) {
 531                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 532                 comedi_error(dev,
 533                              "failed to reserve mite dma channel for analog input.");
 534                 return -EBUSY;
 535         }
 536         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 537         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 538         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 539         return 0;
 540 }
 541
 542 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 543 {
 544         struct ni_private *devpriv = dev->private;
 545         unsigned long flags;
 546
 547         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 548         BUG_ON(devpriv->ao_mite_chan);
 549         devpriv->ao_mite_chan =
 550             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 551         if (devpriv->ao_mite_chan == NULL) {
 552                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 553                 comedi_error(dev,
 554                              "failed to reserve mite dma channel for analog outut.");
 555                 return -EBUSY;
 556         }
 557         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 558         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 559         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 560         return 0;
 561 }
 562
 563 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 564                                         unsigned gpct_index,
 565                                         enum comedi_io_direction direction)
 566 {
 567         struct ni_private *devpriv = dev->private;
 568         unsigned long flags;
 569         struct mite_channel *mite_chan;
 570
 571         BUG_ON(gpct_index >= NUM_GPCT);
 572         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 573         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 574         mite_chan =
 575             mite_request_channel(devpriv->mite,
 576                                  devpriv->gpct_mite_ring[gpct_index]);
 577         if (mite_chan == NULL) {
 578                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 579                 comedi_error(dev,
 580                              "failed to reserve mite dma channel for counter.");
 581                 return -EBUSY;
 582         }
 583         mite_chan->dir = direction;
 584         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 585                                 mite_chan);
 586         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 587         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 588         return 0;
 589 }
 590
 591 #endif /*  PCIDMA */
 592
 593 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 594 {
 595 #ifdef PCIDMA
 596         struct ni_private *devpriv = dev->private;
 597         unsigned long flags;
 598
 599         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 600         BUG_ON(devpriv->cdo_mite_chan);
 601         devpriv->cdo_mite_chan =
 602             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 603         if (devpriv->cdo_mite_chan == NULL) {
 604                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 605                 comedi_error(dev,
 606                              "failed to reserve mite dma channel for correlated digital outut.");
 607                 return -EBUSY;
 608         }
 609         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 610         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 611         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 612 #endif /*  PCIDMA */
 613         return 0;
 614 }
 615
 616 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 617 {
 618 #ifdef PCIDMA
 619         struct ni_private *devpriv = dev->private;
 620         unsigned long flags;
 621
 622         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 623         if (devpriv->ai_mite_chan) {
 624                 ni_set_ai_dma_channel(dev, -1);
 625                 mite_release_channel(devpriv->ai_mite_chan);
 626                 devpriv->ai_mite_chan = NULL;
 627         }
 628         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 629 #endif /*  PCIDMA */
 630 }
 631
 632 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 633 {
 634 #ifdef PCIDMA
 635         struct ni_private *devpriv = dev->private;
 636         unsigned long flags;
 637
 638         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 639         if (devpriv->ao_mite_chan) {
 640                 ni_set_ao_dma_channel(dev, -1);
 641                 mite_release_channel(devpriv->ao_mite_chan);
 642                 devpriv->ao_mite_chan = NULL;
 643         }
 644         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 645 #endif /*  PCIDMA */
 646 }
 647
 648 #ifdef PCIDMA
 649 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 650                                          unsigned gpct_index)
 651 {
 652         struct ni_private *devpriv = dev->private;
 653         unsigned long flags;
 654
 655         BUG_ON(gpct_index >= NUM_GPCT);
 656         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 657         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 658                 struct mite_channel *mite_chan =
 659                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 660
 661                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 662                 ni_tio_set_mite_channel(&devpriv->
 663                                         counter_dev->counters[gpct_index],
 664                                         NULL);
 665                 mite_release_channel(mite_chan);
 666         }
 667         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 668 }
 669 #endif /*  PCIDMA */
 670
 671 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 672 {
 673 #ifdef PCIDMA
 674         struct ni_private *devpriv = dev->private;
 675         unsigned long flags;
 676
 677         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 678         if (devpriv->cdo_mite_chan) {
 679                 ni_set_cdo_dma_channel(dev, -1);
 680                 mite_release_channel(devpriv->cdo_mite_chan);
 681                 devpriv->cdo_mite_chan = NULL;
 682         }
 683         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 684 #endif /*  PCIDMA */
 685 }
 686
 687 /* e-series boards use the second irq signals to generate dma requests for their counters */
 688 #ifdef PCIDMA
 689 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 690                                           unsigned gpct_index, short enable)
 691 {
 692         const struct ni_board_struct *board = comedi_board(dev);
 693         struct ni_private *devpriv = dev->private;
 694
 695         if (board->reg_type & ni_reg_m_series_mask)
 696                 return;
 697         switch (gpct_index) {
 698         case 0:
 699                 if (enable) {
 700                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 701                                             Second_IRQ_A_Enable_Register);
 702                 } else {
 703                         devpriv->stc_writew(dev, 0,
 704                                             Second_IRQ_A_Enable_Register);
 705                 }
 706                 break;
 707         case 1:
 708                 if (enable) {
 709                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 710                                             Second_IRQ_B_Enable_Register);
 711                 } else {
 712                         devpriv->stc_writew(dev, 0,
 713                                             Second_IRQ_B_Enable_Register);
 714                 }
 715                 break;
 716         default:
 717                 BUG();
 718                 break;
 719         }
 720 }
 721 #endif /*  PCIDMA */
 722
 723 static void ni_clear_ai_fifo(struct comedi_device *dev)
 724 {
 725         const struct ni_board_struct *board = comedi_board(dev);
 726         struct ni_private *devpriv = dev->private;
 727
 728         if (board->reg_type == ni_reg_6143) {
 729                 /*  Flush the 6143 data FIFO */
 730                 ni_writel(0x10, AIFIFO_Control_6143);   /*  Flush fifo */
 731                 ni_writel(0x00, AIFIFO_Control_6143);   /*  Flush fifo */
 732                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   /*  Wait for complete */
 733         } else {
 734                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 735                 if (board->reg_type == ni_reg_625x) {
 736                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 737                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 738 #if 0
 739                         /* the NI example code does 3 convert pulses for 625x boards,
 740                            but that appears to be wrong in practice. */
 741                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 742                                             AI_Command_1_Register);
 743                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 744                                             AI_Command_1_Register);
 745                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 746                                             AI_Command_1_Register);
 747 #endif
 748                 }
 749         }
 750 }
 751
 752 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 753 {
 754         struct ni_private *devpriv = dev->private;
 755
 756         devpriv->stc_writew(dev, data >> 16, reg);
 757         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 758 }
 759
 760 static uint32_t win_in2(struct comedi_device *dev, int reg)
 761 {
 762         struct ni_private *devpriv = dev->private;
 763         uint32_t bits;
 764
 765         bits = devpriv->stc_readw(dev, reg) << 16;
 766         bits |= devpriv->stc_readw(dev, reg + 1);
 767         return bits;
 768 }
 769
 770 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 771 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 772                                   int addr)
 773 {
 774         struct ni_private *devpriv = dev->private;
 775         unsigned long flags;
 776
 777         spin_lock_irqsave(&devpriv->window_lock, flags);
 778         ni_writew(addr, AO_Window_Address_611x);
 779         ni_writew(data, AO_Window_Data_611x);
 780         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 781 }
 782
 783 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 784                                   int addr)
 785 {
 786         struct ni_private *devpriv = dev->private;
 787         unsigned long flags;
 788
 789         spin_lock_irqsave(&devpriv->window_lock, flags);
 790         ni_writew(addr, AO_Window_Address_611x);
 791         ni_writel(data, AO_Window_Data_611x);
 792         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 793 }
 794
 795 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 796 {
 797         struct ni_private *devpriv = dev->private;
 798         unsigned long flags;
 799         unsigned short data;
 800
 801         spin_lock_irqsave(&devpriv->window_lock, flags);
 802         ni_writew(addr, AO_Window_Address_611x);
 803         data = ni_readw(AO_Window_Data_611x);
 804         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 805         return data;
 806 }
 807
 808 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 809 * share registers (such as Interrupt_A_Register) without interfering with
 810 * each other.
 811 *
 812 * NOTE: the switch/case statements are optimized out for a constant argument
 813 * so this is actually quite fast---  If you must wrap another function around this
 814 * make it inline to avoid a large speed penalty.
 815 *
 816 * value should only be 1 or 0.
 817 */
 818 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 819                                unsigned bits, unsigned value)
 820 {
 821         unsigned bit_values;
 822
 823         if (value)
 824                 bit_values = bits;
 825         else
 826                 bit_values = 0;
 827         ni_set_bitfield(dev, reg, bits, bit_values);
 828 }
 829
 830 static irqreturn_t ni_E_interrupt(int irq, void *d)
 831 {
 832         struct comedi_device *dev = d;
 833         struct ni_private *devpriv = dev->private;
 834         unsigned short a_status;
 835         unsigned short b_status;
 836         unsigned int ai_mite_status = 0;
 837         unsigned int ao_mite_status = 0;
 838         unsigned long flags;
 839 #ifdef PCIDMA
 840         struct mite_struct *mite = devpriv->mite;
 841 #endif
 842
 843         if (!dev->attached)
 844                 return IRQ_NONE;
 845         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
 846
 847         /*  lock to avoid race with comedi_poll */
 848         spin_lock_irqsave(&dev->spinlock, flags);
 849         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 850         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 851 #ifdef PCIDMA
 852         if (mite) {
 853                 unsigned long flags_too;
 854
 855                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 856                 if (devpriv->ai_mite_chan) {
 857                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 858                         if (ai_mite_status & CHSR_LINKC)
 859                                 writel(CHOR_CLRLC,
 860                                        devpriv->mite->mite_io_addr +
 861                                        MITE_CHOR(devpriv->
 862                                                  ai_mite_chan->channel));
 863                 }
 864                 if (devpriv->ao_mite_chan) {
 865                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 866                         if (ao_mite_status & CHSR_LINKC)
 867                                 writel(CHOR_CLRLC,
 868                                        mite->mite_io_addr +
 869                                        MITE_CHOR(devpriv->
 870                                                  ao_mite_chan->channel));
 871                 }
 872                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 873         }
 874 #endif
 875         ack_a_interrupt(dev, a_status);
 876         ack_b_interrupt(dev, b_status);
 877         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 878                 handle_a_interrupt(dev, a_status, ai_mite_status);
 879         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 880                 handle_b_interrupt(dev, b_status, ao_mite_status);
 881         handle_gpct_interrupt(dev, 0);
 882         handle_gpct_interrupt(dev, 1);
 883         handle_cdio_interrupt(dev);
 884
 885         spin_unlock_irqrestore(&dev->spinlock, flags);
 886         return IRQ_HANDLED;
 887 }
 888
 889 #ifdef PCIDMA
 890 static void ni_sync_ai_dma(struct comedi_device *dev)
 891 {
 892         struct ni_private *devpriv = dev->private;
 893         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 894         unsigned long flags;
 895
 896         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 897         if (devpriv->ai_mite_chan)
 898                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 899         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 900 }
 901
 902 static void mite_handle_b_linkc(struct mite_struct *mite,
 903                                 struct comedi_device *dev)
 904 {
 905         struct ni_private *devpriv = dev->private;
 906         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
 907         unsigned long flags;
 908
 909         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 910         if (devpriv->ao_mite_chan) {
 911                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 912         }
 913         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 914 }
 915
 916 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 917 {
 918         struct ni_private *devpriv = dev->private;
 919         static const int timeout = 10000;
 920         int i;
 921         for (i = 0; i < timeout; i++) {
 922                 unsigned short b_status;
 923
 924                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 925                 if (b_status & AO_FIFO_Half_Full_St)
 926                         break;
 927                 /* if we poll too often, the pci bus activity seems
 928                    to slow the dma transfer down */
 929                 udelay(10);
 930         }
 931         if (i == timeout) {
 932                 comedi_error(dev, "timed out waiting for dma load");
 933                 return -EPIPE;
 934         }
 935         return 0;
 936 }
 937
 938 #endif /* PCIDMA */
 939 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 940 {
 941         struct ni_private *devpriv = dev->private;
 942
 943         if (devpriv->aimode == AIMODE_SCAN) {
 944 #ifdef PCIDMA
 945                 static const int timeout = 10;
 946                 int i;
 947
 948                 for (i = 0; i < timeout; i++) {
 949                         ni_sync_ai_dma(dev);
 950                         if ((s->async->events & COMEDI_CB_EOS))
 951                                 break;
 952                         udelay(1);
 953                 }
 954 #else
 955                 ni_handle_fifo_dregs(dev);
 956                 s->async->events |= COMEDI_CB_EOS;
 957 #endif
 958         }
 959         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 960         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 961                 shutdown_ai_command(dev);
 962         }
 963 }
 964
 965 static void shutdown_ai_command(struct comedi_device *dev)
 966 {
 967         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 968
 969 #ifdef PCIDMA
 970         ni_ai_drain_dma(dev);
 971 #endif
 972         ni_handle_fifo_dregs(dev);
 973         get_last_sample_611x(dev);
 974         get_last_sample_6143(dev);
 975
 976         s->async->events |= COMEDI_CB_EOA;
 977 }
 978
 979 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
 980 {
 981         if (s->
 982             async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
 983                              COMEDI_CB_EOA)) {
 984                 switch (s->index) {
 985                 case NI_AI_SUBDEV:
 986                         ni_ai_reset(dev, s);
 987                         break;
 988                 case NI_AO_SUBDEV:
 989                         ni_ao_reset(dev, s);
 990                         break;
 991                 case NI_GPCT0_SUBDEV:
 992                 case NI_GPCT1_SUBDEV:
 993                         ni_gpct_cancel(dev, s);
 994                         break;
 995                 case NI_DIO_SUBDEV:
 996                         ni_cdio_cancel(dev, s);
 997                         break;
 998                 default:
 999                         break;
1000                 }
1001         }
1002         comedi_event(dev, s);
1003 }
1004
1005 static void handle_gpct_interrupt(struct comedi_device *dev,
1006                                   unsigned short counter_index)
1007 {
1008 #ifdef PCIDMA
1009         struct ni_private *devpriv = dev->private;
1010         struct comedi_subdevice *s;
1011
1012         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1013
1014         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1015                                 s);
1016         if (s->async->events)
1017                 ni_event(dev, s);
1018 #endif
1019 }
1020
1021 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1022 {
1023         struct ni_private *devpriv = dev->private;
1024         unsigned short ack = 0;
1025
1026         if (a_status & AI_SC_TC_St) {
1027                 ack |= AI_SC_TC_Interrupt_Ack;
1028         }
1029         if (a_status & AI_START1_St) {
1030                 ack |= AI_START1_Interrupt_Ack;
1031         }
1032         if (a_status & AI_START_St) {
1033                 ack |= AI_START_Interrupt_Ack;
1034         }
1035         if (a_status & AI_STOP_St) {
1036                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1037                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1038         }
1039         if (ack)
1040                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1041 }
1042
1043 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1044                                unsigned ai_mite_status)
1045 {
1046         struct ni_private *devpriv = dev->private;
1047         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1048
1049         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1050         if (s->type == COMEDI_SUBD_UNUSED)
1051                 return;
1052
1053 #ifdef DEBUG_INTERRUPT
1054         printk
1055             ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1056              status, ai_mite_status);
1057         ni_mio_print_status_a(status);
1058 #endif
1059 #ifdef PCIDMA
1060         if (ai_mite_status & CHSR_LINKC) {
1061                 ni_sync_ai_dma(dev);
1062         }
1063
1064         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1065                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1066                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1067                 printk
1068                     ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1069                      ai_mite_status);
1070                 /* mite_print_chsr(ai_mite_status); */
1071                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1072                 /* disable_irq(dev->irq); */
1073         }
1074 #endif
1075
1076         /* test for all uncommon interrupt events at the same time */
1077         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1078                       AI_SC_TC_St | AI_START1_St)) {
1079                 if (status == 0xffff) {
1080                         printk
1081                             ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1082                         /* we probably aren't even running a command now,
1083                          * so it's a good idea to be careful. */
1084                         if (comedi_is_subdevice_running(s)) {
1085                                 s->async->events |=
1086                                     COMEDI_CB_ERROR | COMEDI_CB_EOA;
1087                                 ni_event(dev, s);
1088                         }
1089                         return;
1090                 }
1091                 if (status & (AI_Overrun_St | AI_Overflow_St |
1092                               AI_SC_TC_Error_St)) {
1093                         printk("ni_mio_common: ai error a_status=%04x\n",
1094                                status);
1095                         ni_mio_print_status_a(status);
1096
1097                         shutdown_ai_command(dev);
1098
1099                         s->async->events |= COMEDI_CB_ERROR;
1100                         if (status & (AI_Overrun_St | AI_Overflow_St))
1101                                 s->async->events |= COMEDI_CB_OVERFLOW;
1102
1103                         ni_event(dev, s);
1104
1105                         return;
1106                 }
1107                 if (status & AI_SC_TC_St) {
1108 #ifdef DEBUG_INTERRUPT
1109                         printk("ni_mio_common: SC_TC interrupt\n");
1110 #endif
1111                         if (!devpriv->ai_continuous) {
1112                                 shutdown_ai_command(dev);
1113                         }
1114                 }
1115         }
1116 #ifndef PCIDMA
1117         if (status & AI_FIFO_Half_Full_St) {
1118                 int i;
1119                 static const int timeout = 10;
1120                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1121                  *fail to get the fifo less than half full, so loop to be sure.*/
1122                 for (i = 0; i < timeout; ++i) {
1123                         ni_handle_fifo_half_full(dev);
1124                         if ((devpriv->stc_readw(dev,
1125                                                 AI_Status_1_Register) &
1126                              AI_FIFO_Half_Full_St) == 0)
1127                                 break;
1128                 }
1129         }
1130 #endif /*  !PCIDMA */
1131
1132         if ((status & AI_STOP_St)) {
1133                 ni_handle_eos(dev, s);
1134         }
1135
1136         ni_event(dev, s);
1137
1138 #ifdef DEBUG_INTERRUPT
1139         status = devpriv->stc_readw(dev, AI_Status_1_Register);
1140         if (status & Interrupt_A_St) {
1141                 printk
1142                     ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1143                      status);
1144         }
1145 #endif
1146 }
1147
1148 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1149 {
1150         struct ni_private *devpriv = dev->private;
1151         unsigned short ack = 0;
1152
1153         if (b_status & AO_BC_TC_St) {
1154                 ack |= AO_BC_TC_Interrupt_Ack;
1155         }
1156         if (b_status & AO_Overrun_St) {
1157                 ack |= AO_Error_Interrupt_Ack;
1158         }
1159         if (b_status & AO_START_St) {
1160                 ack |= AO_START_Interrupt_Ack;
1161         }
1162         if (b_status & AO_START1_St) {
1163                 ack |= AO_START1_Interrupt_Ack;
1164         }
1165         if (b_status & AO_UC_TC_St) {
1166                 ack |= AO_UC_TC_Interrupt_Ack;
1167         }
1168         if (b_status & AO_UI2_TC_St) {
1169                 ack |= AO_UI2_TC_Interrupt_Ack;
1170         }
1171         if (b_status & AO_UPDATE_St) {
1172                 ack |= AO_UPDATE_Interrupt_Ack;
1173         }
1174         if (ack)
1175                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1176 }
1177
1178 static void handle_b_interrupt(struct comedi_device *dev,
1179                                unsigned short b_status, unsigned ao_mite_status)
1180 {
1181         struct ni_private *devpriv = dev->private;
1182         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1183         /* unsigned short ack=0; */
1184
1185 #ifdef DEBUG_INTERRUPT
1186         printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1187                b_status, ao_mite_status);
1188         ni_mio_print_status_b(b_status);
1189 #endif
1190
1191 #ifdef PCIDMA
1192         /* Currently, mite.c requires us to handle LINKC */
1193         if (ao_mite_status & CHSR_LINKC) {
1194                 mite_handle_b_linkc(devpriv->mite, dev);
1195         }
1196
1197         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1198                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1199                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1200                 printk
1201                     ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1202                      ao_mite_status);
1203                 /* mite_print_chsr(ao_mite_status); */
1204                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1205         }
1206 #endif
1207
1208         if (b_status == 0xffff)
1209                 return;
1210         if (b_status & AO_Overrun_St) {
1211                 printk
1212                     ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1213                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1214                 s->async->events |= COMEDI_CB_OVERFLOW;
1215         }
1216
1217         if (b_status & AO_BC_TC_St) {
1218                 MDPRINTK
1219                     ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1220                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1221                 s->async->events |= COMEDI_CB_EOA;
1222         }
1223 #ifndef PCIDMA
1224         if (b_status & AO_FIFO_Request_St) {
1225                 int ret;
1226
1227                 ret = ni_ao_fifo_half_empty(dev, s);
1228                 if (!ret) {
1229                         printk("ni_mio_common: AO buffer underrun\n");
1230                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1231                                     AO_FIFO_Interrupt_Enable |
1232                                     AO_Error_Interrupt_Enable, 0);
1233                         s->async->events |= COMEDI_CB_OVERFLOW;
1234                 }
1235         }
1236 #endif
1237
1238         ni_event(dev, s);
1239 }
1240
1241 #ifdef DEBUG_STATUS_A
1242 static const char *const status_a_strings[] = {
1243         "passthru0", "fifo", "G0_gate", "G0_TC",
1244         "stop", "start", "sc_tc", "start1",
1245         "start2", "sc_tc_error", "overflow", "overrun",
1246         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1247 };
1248
1249 static void ni_mio_print_status_a(int status)
1250 {
1251         int i;
1252
1253         printk("A status:");
1254         for (i = 15; i >= 0; i--) {
1255                 if (status & (1 << i)) {
1256                         printk(" %s", status_a_strings[i]);
1257                 }
1258         }
1259         printk("\n");
1260 }
1261 #endif
1262
1263 #ifdef DEBUG_STATUS_B
1264 static const char *const status_b_strings[] = {
1265         "passthru1", "fifo", "G1_gate", "G1_TC",
1266         "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1267         "start1", "overrun", "start", "bc_tc_error",
1268         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1269 };
1270
1271 static void ni_mio_print_status_b(int status)
1272 {
1273         int i;
1274
1275         printk("B status:");
1276         for (i = 15; i >= 0; i--) {
1277                 if (status & (1 << i)) {
1278                         printk(" %s", status_b_strings[i]);
1279                 }
1280         }
1281         printk("\n");
1282 }
1283 #endif
1284
1285 #ifndef PCIDMA
1286
1287 static void ni_ao_fifo_load(struct comedi_device *dev,
1288                             struct comedi_subdevice *s, int n)
1289 {
1290         const struct ni_board_struct *board = comedi_board(dev);
1291         struct comedi_async *async = s->async;
1292         struct comedi_cmd *cmd = &async->cmd;
1293         int chan;
1294         int i;
1295         short d;
1296         u32 packed_data;
1297         int range;
1298         int err = 1;
1299
1300         chan = async->cur_chan;
1301         for (i = 0; i < n; i++) {
1302                 err &= comedi_buf_get(async, &d);
1303                 if (err == 0)
1304                         break;
1305
1306                 range = CR_RANGE(cmd->chanlist[chan]);
1307
1308                 if (board->reg_type & ni_reg_6xxx_mask) {
1309                         packed_data = d & 0xffff;
1310                         /* 6711 only has 16 bit wide ao fifo */
1311                         if (board->reg_type != ni_reg_6711) {
1312                                 err &= comedi_buf_get(async, &d);
1313                                 if (err == 0)
1314                                         break;
1315                                 chan++;
1316                                 i++;
1317                                 packed_data |= (d << 16) & 0xffff0000;
1318                         }
1319                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1320                 } else {
1321                         ni_writew(d, DAC_FIFO_Data);
1322                 }
1323                 chan++;
1324                 chan %= cmd->chanlist_len;
1325         }
1326         async->cur_chan = chan;
1327         if (err == 0) {
1328                 async->events |= COMEDI_CB_OVERFLOW;
1329         }
1330 }
1331
1332 /*
1333  *  There's a small problem if the FIFO gets really low and we
1334  *  don't have the data to fill it.  Basically, if after we fill
1335  *  the FIFO with all the data available, the FIFO is _still_
1336  *  less than half full, we never clear the interrupt.  If the
1337  *  IRQ is in edge mode, we never get another interrupt, because
1338  *  this one wasn't cleared.  If in level mode, we get flooded
1339  *  with interrupts that we can't fulfill, because nothing ever
1340  *  gets put into the buffer.
1341  *
1342  *  This kind of situation is recoverable, but it is easier to
1343  *  just pretend we had a FIFO underrun, since there is a good
1344  *  chance it will happen anyway.  This is _not_ the case for
1345  *  RT code, as RT code might purposely be running close to the
1346  *  metal.  Needs to be fixed eventually.
1347  */
1348 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1349                                  struct comedi_subdevice *s)
1350 {
1351         const struct ni_board_struct *board = comedi_board(dev);
1352         int n;
1353
1354         n = comedi_buf_read_n_available(s->async);
1355         if (n == 0) {
1356                 s->async->events |= COMEDI_CB_OVERFLOW;
1357                 return 0;
1358         }
1359
1360         n /= sizeof(short);
1361         if (n > board->ao_fifo_depth / 2)
1362                 n = board->ao_fifo_depth / 2;
1363
1364         ni_ao_fifo_load(dev, s, n);
1365
1366         s->async->events |= COMEDI_CB_BLOCK;
1367
1368         return 1;
1369 }
1370
1371 static int ni_ao_prep_fifo(struct comedi_device *dev,
1372                            struct comedi_subdevice *s)
1373 {
1374         const struct ni_board_struct *board = comedi_board(dev);
1375         struct ni_private *devpriv = dev->private;
1376         int n;
1377
1378         /* reset fifo */
1379         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1380         if (board->reg_type & ni_reg_6xxx_mask)
1381                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1382
1383         /* load some data */
1384         n = comedi_buf_read_n_available(s->async);
1385         if (n == 0)
1386                 return 0;
1387
1388         n /= sizeof(short);
1389         if (n > board->ao_fifo_depth)
1390                 n = board->ao_fifo_depth;
1391
1392         ni_ao_fifo_load(dev, s, n);
1393
1394         return n;
1395 }
1396
1397 static void ni_ai_fifo_read(struct comedi_device *dev,
1398                             struct comedi_subdevice *s, int n)
1399 {
1400         const struct ni_board_struct *board = comedi_board(dev);
1401         struct ni_private *devpriv = dev->private;
1402         struct comedi_async *async = s->async;
1403         int i;
1404
1405         if (board->reg_type == ni_reg_611x) {
1406                 short data[2];
1407                 u32 dl;
1408
1409                 for (i = 0; i < n / 2; i++) {
1410                         dl = ni_readl(ADC_FIFO_Data_611x);
1411                         /* This may get the hi/lo data in the wrong order */
1412                         data[0] = (dl >> 16) & 0xffff;
1413                         data[1] = dl & 0xffff;
1414                         cfc_write_array_to_buffer(s, data, sizeof(data));
1415                 }
1416                 /* Check if there's a single sample stuck in the FIFO */
1417                 if (n % 2) {
1418                         dl = ni_readl(ADC_FIFO_Data_611x);
1419                         data[0] = dl & 0xffff;
1420                         cfc_write_to_buffer(s, data[0]);
1421                 }
1422         } else if (board->reg_type == ni_reg_6143) {
1423                 short data[2];
1424                 u32 dl;
1425
1426                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1427                 for (i = 0; i < n / 2; i++) {
1428                         dl = ni_readl(AIFIFO_Data_6143);
1429
1430                         data[0] = (dl >> 16) & 0xffff;
1431                         data[1] = dl & 0xffff;
1432                         cfc_write_array_to_buffer(s, data, sizeof(data));
1433                 }
1434                 if (n % 2) {
1435                         /* Assume there is a single sample stuck in the FIFO */
1436                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1437                         dl = ni_readl(AIFIFO_Data_6143);
1438                         data[0] = (dl >> 16) & 0xffff;
1439                         cfc_write_to_buffer(s, data[0]);
1440                 }
1441         } else {
1442                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1443                     sizeof(devpriv->ai_fifo_buffer[0])) {
1444                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1445                         async->events |= COMEDI_CB_ERROR;
1446                         return;
1447                 }
1448                 for (i = 0; i < n; i++) {
1449                         devpriv->ai_fifo_buffer[i] =
1450                             ni_readw(ADC_FIFO_Data_Register);
1451                 }
1452                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1453                                           n *
1454                                           sizeof(devpriv->ai_fifo_buffer[0]));
1455         }
1456 }
1457
1458 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1459 {
1460         const struct ni_board_struct *board = comedi_board(dev);
1461         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1462         int n;
1463
1464         n = board->ai_fifo_depth / 2;
1465
1466         ni_ai_fifo_read(dev, s, n);
1467 }
1468 #endif
1469
1470 #ifdef PCIDMA
1471 static int ni_ai_drain_dma(struct comedi_device *dev)
1472 {
1473         struct ni_private *devpriv = dev->private;
1474         int i;
1475         static const int timeout = 10000;
1476         unsigned long flags;
1477         int retval = 0;
1478
1479         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1480         if (devpriv->ai_mite_chan) {
1481                 for (i = 0; i < timeout; i++) {
1482                         if ((devpriv->stc_readw(dev,
1483                                                 AI_Status_1_Register) &
1484                              AI_FIFO_Empty_St)
1485                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1486                             0)
1487                                 break;
1488                         udelay(5);
1489                 }
1490                 if (i == timeout) {
1491                         printk("ni_mio_common: wait for dma drain timed out\n");
1492                         printk
1493                             ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1494                              mite_bytes_in_transit(devpriv->ai_mite_chan),
1495                              devpriv->stc_readw(dev, AI_Status_1_Register));
1496                         retval = -1;
1497                 }
1498         }
1499         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1500
1501         ni_sync_ai_dma(dev);
1502
1503         return retval;
1504 }
1505 #endif
1506 /*
1507    Empties the AI fifo
1508 */
1509 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1510 {
1511         const struct ni_board_struct *board = comedi_board(dev);
1512         struct ni_private *devpriv = dev->private;
1513         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1514         short data[2];
1515         u32 dl;
1516         short fifo_empty;
1517         int i;
1518
1519         if (board->reg_type == ni_reg_611x) {
1520                 while ((devpriv->stc_readw(dev,
1521                                            AI_Status_1_Register) &
1522                         AI_FIFO_Empty_St) == 0) {
1523                         dl = ni_readl(ADC_FIFO_Data_611x);
1524
1525                         /* This may get the hi/lo data in the wrong order */
1526                         data[0] = (dl >> 16);
1527                         data[1] = (dl & 0xffff);
1528                         cfc_write_array_to_buffer(s, data, sizeof(data));
1529                 }
1530         } else if (board->reg_type == ni_reg_6143) {
1531                 i = 0;
1532                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1533                         dl = ni_readl(AIFIFO_Data_6143);
1534
1535                         /* This may get the hi/lo data in the wrong order */
1536                         data[0] = (dl >> 16);
1537                         data[1] = (dl & 0xffff);
1538                         cfc_write_array_to_buffer(s, data, sizeof(data));
1539                         i += 2;
1540                 }
1541                 /*  Check if stranded sample is present */
1542                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1543                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1544                         dl = ni_readl(AIFIFO_Data_6143);
1545                         data[0] = (dl >> 16) & 0xffff;
1546                         cfc_write_to_buffer(s, data[0]);
1547                 }
1548
1549         } else {
1550                 fifo_empty =
1551                     devpriv->stc_readw(dev,
1552                                        AI_Status_1_Register) & AI_FIFO_Empty_St;
1553                 while (fifo_empty == 0) {
1554                         for (i = 0;
1555                              i <
1556                              sizeof(devpriv->ai_fifo_buffer) /
1557                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1558                                 fifo_empty =
1559                                     devpriv->stc_readw(dev,
1560                                                        AI_Status_1_Register) &
1561                                     AI_FIFO_Empty_St;
1562                                 if (fifo_empty)
1563                                         break;
1564                                 devpriv->ai_fifo_buffer[i] =
1565                                     ni_readw(ADC_FIFO_Data_Register);
1566                         }
1567                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1568                                                   i *
1569                                                   sizeof(devpriv->
1570                                                          ai_fifo_buffer[0]));
1571                 }
1572         }
1573 }
1574
1575 static void get_last_sample_611x(struct comedi_device *dev)
1576 {
1577         const struct ni_board_struct *board = comedi_board(dev);
1578         struct ni_private *devpriv __maybe_unused = dev->private;
1579         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1580         short data;
1581         u32 dl;
1582
1583         if (board->reg_type != ni_reg_611x)
1584                 return;
1585
1586         /* Check if there's a single sample stuck in the FIFO */
1587         if (ni_readb(XXX_Status) & 0x80) {
1588                 dl = ni_readl(ADC_FIFO_Data_611x);
1589                 data = (dl & 0xffff);
1590                 cfc_write_to_buffer(s, data);
1591         }
1592 }
1593
1594 static void get_last_sample_6143(struct comedi_device *dev)
1595 {
1596         const struct ni_board_struct *board = comedi_board(dev);
1597         struct ni_private *devpriv __maybe_unused = dev->private;
1598         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1599         short data;
1600         u32 dl;
1601
1602         if (board->reg_type != ni_reg_6143)
1603                 return;
1604
1605         /* Check if there's a single sample stuck in the FIFO */
1606         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1607                 ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1608                 dl = ni_readl(AIFIFO_Data_6143);
1609
1610                 /* This may get the hi/lo data in the wrong order */
1611                 data = (dl >> 16) & 0xffff;
1612                 cfc_write_to_buffer(s, data);
1613         }
1614 }
1615
1616 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1617                         void *data, unsigned int num_bytes,
1618                         unsigned int chan_index)
1619 {
1620         struct ni_private *devpriv = dev->private;
1621         struct comedi_async *async = s->async;
1622         unsigned int i;
1623         unsigned int length = num_bytes / bytes_per_sample(s);
1624         short *array = data;
1625         unsigned int *larray = data;
1626
1627         for (i = 0; i < length; i++) {
1628 #ifdef PCIDMA
1629                 if (s->subdev_flags & SDF_LSAMPL)
1630                         larray[i] = le32_to_cpu(larray[i]);
1631                 else
1632                         array[i] = le16_to_cpu(array[i]);
1633 #endif
1634                 if (s->subdev_flags & SDF_LSAMPL)
1635                         larray[i] += devpriv->ai_offset[chan_index];
1636                 else
1637                         array[i] += devpriv->ai_offset[chan_index];
1638                 chan_index++;
1639                 chan_index %= async->cmd.chanlist_len;
1640         }
1641 }
1642
1643 #ifdef PCIDMA
1644
1645 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1646 {
1647         const struct ni_board_struct *board = comedi_board(dev);
1648         struct ni_private *devpriv = dev->private;
1649         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1650         int retval;
1651         unsigned long flags;
1652
1653         retval = ni_request_ai_mite_channel(dev);
1654         if (retval)
1655                 return retval;
1656 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1657
1658         /* write alloc the entire buffer */
1659         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1660
1661         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1662         if (devpriv->ai_mite_chan == NULL) {
1663                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1664                 return -EIO;
1665         }
1666
1667         switch (board->reg_type) {
1668         case ni_reg_611x:
1669         case ni_reg_6143:
1670                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1671                 break;
1672         case ni_reg_628x:
1673                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1674                 break;
1675         default:
1676                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1677                 break;
1678         }
1679         /*start the MITE */
1680         mite_dma_arm(devpriv->ai_mite_chan);
1681         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1682
1683         return 0;
1684 }
1685
1686 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1687 {
1688         const struct ni_board_struct *board = comedi_board(dev);
1689         struct ni_private *devpriv = dev->private;
1690         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1691         int retval;
1692         unsigned long flags;
1693
1694         retval = ni_request_ao_mite_channel(dev);
1695         if (retval)
1696                 return retval;
1697
1698         /* read alloc the entire buffer */
1699         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1700
1701         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1702         if (devpriv->ao_mite_chan) {
1703                 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1704                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1705                 } else {
1706                         /* doing 32 instead of 16 bit wide transfers from memory
1707                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1708                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1709                 }
1710                 mite_dma_arm(devpriv->ao_mite_chan);
1711         } else
1712                 retval = -EIO;
1713         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1714
1715         return retval;
1716 }
1717
1718 #endif /*  PCIDMA */
1719
1720 /*
1721    used for both cancel ioctl and board initialization
1722
1723    this is pretty harsh for a cancel, but it works...
1724  */
1725
1726 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1727 {
1728         const struct ni_board_struct *board = comedi_board(dev);
1729         struct ni_private *devpriv = dev->private;
1730
1731         ni_release_ai_mite_channel(dev);
1732         /* ai configuration */
1733         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1734                             Joint_Reset_Register);
1735
1736         ni_set_bits(dev, Interrupt_A_Enable_Register,
1737                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1738                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1739                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1740                     AI_FIFO_Interrupt_Enable, 0);
1741
1742         ni_clear_ai_fifo(dev);
1743
1744         if (board->reg_type != ni_reg_6143)
1745                 ni_writeb(0, Misc_Command);
1746
1747         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1748         devpriv->stc_writew(dev,
1749                             AI_Start_Stop | AI_Mode_1_Reserved
1750                             /*| AI_Trigger_Once */ ,
1751                             AI_Mode_1_Register);
1752         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1753         /* generate FIFO interrupts on non-empty */
1754         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1755         if (board->reg_type == ni_reg_611x) {
1756                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1757                                     AI_SOC_Polarity |
1758                                     AI_LOCALMUX_CLK_Pulse_Width,
1759                                     AI_Personal_Register);
1760                 devpriv->stc_writew(dev,
1761                                     AI_SCAN_IN_PROG_Output_Select(3) |
1762                                     AI_EXTMUX_CLK_Output_Select(0) |
1763                                     AI_LOCALMUX_CLK_Output_Select(2) |
1764                                     AI_SC_TC_Output_Select(3) |
1765                                     AI_CONVERT_Output_Select
1766                                     (AI_CONVERT_Output_Enable_High),
1767                                     AI_Output_Control_Register);
1768         } else if (board->reg_type == ni_reg_6143) {
1769                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1770                                     AI_SOC_Polarity |
1771                                     AI_LOCALMUX_CLK_Pulse_Width,
1772                                     AI_Personal_Register);
1773                 devpriv->stc_writew(dev,
1774                                     AI_SCAN_IN_PROG_Output_Select(3) |
1775                                     AI_EXTMUX_CLK_Output_Select(0) |
1776                                     AI_LOCALMUX_CLK_Output_Select(2) |
1777                                     AI_SC_TC_Output_Select(3) |
1778                                     AI_CONVERT_Output_Select
1779                                     (AI_CONVERT_Output_Enable_Low),
1780                                     AI_Output_Control_Register);
1781         } else {
1782                 unsigned ai_output_control_bits;
1783                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1784                                     AI_SOC_Polarity |
1785                                     AI_CONVERT_Pulse_Width |
1786                                     AI_LOCALMUX_CLK_Pulse_Width,
1787                                     AI_Personal_Register);
1788                 ai_output_control_bits =
1789                     AI_SCAN_IN_PROG_Output_Select(3) |
1790                     AI_EXTMUX_CLK_Output_Select(0) |
1791                     AI_LOCALMUX_CLK_Output_Select(2) |
1792                     AI_SC_TC_Output_Select(3);
1793                 if (board->reg_type == ni_reg_622x)
1794                         ai_output_control_bits |=
1795                             AI_CONVERT_Output_Select
1796                             (AI_CONVERT_Output_Enable_High);
1797                 else
1798                         ai_output_control_bits |=
1799                             AI_CONVERT_Output_Select
1800                             (AI_CONVERT_Output_Enable_Low);
1801                 devpriv->stc_writew(dev, ai_output_control_bits,
1802                                     AI_Output_Control_Register);
1803         }
1804         /* the following registers should not be changed, because there
1805          * are no backup registers in devpriv.  If you want to change
1806          * any of these, add a backup register and other appropriate code:
1807          *      AI_Mode_1_Register
1808          *      AI_Mode_3_Register
1809          *      AI_Personal_Register
1810          *      AI_Output_Control_Register
1811          */
1812         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1813
1814         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1815
1816         return 0;
1817 }
1818
1819 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1820 {
1821         unsigned long flags;
1822         int count;
1823
1824         /*  lock to avoid race with interrupt handler */
1825         spin_lock_irqsave(&dev->spinlock, flags);
1826 #ifndef PCIDMA
1827         ni_handle_fifo_dregs(dev);
1828 #else
1829         ni_sync_ai_dma(dev);
1830 #endif
1831         count = s->async->buf_write_count - s->async->buf_read_count;
1832         spin_unlock_irqrestore(&dev->spinlock, flags);
1833
1834         return count;
1835 }
1836
1837 static int ni_ai_insn_read(struct comedi_device *dev,
1838                            struct comedi_subdevice *s, struct comedi_insn *insn,
1839                            unsigned int *data)
1840 {
1841         const struct ni_board_struct *board = comedi_board(dev);
1842         struct ni_private *devpriv = dev->private;
1843         int i, n;
1844         const unsigned int mask = (1 << board->adbits) - 1;
1845         unsigned signbits;
1846         unsigned short d;
1847         unsigned long dl;
1848
1849         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1850
1851         ni_clear_ai_fifo(dev);
1852
1853         signbits = devpriv->ai_offset[0];
1854         if (board->reg_type == ni_reg_611x) {
1855                 for (n = 0; n < num_adc_stages_611x; n++) {
1856                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1857                                             AI_Command_1_Register);
1858                         udelay(1);
1859                 }
1860                 for (n = 0; n < insn->n; n++) {
1861                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1862                                             AI_Command_1_Register);
1863                         /* The 611x has screwy 32-bit FIFOs. */
1864                         d = 0;
1865                         for (i = 0; i < NI_TIMEOUT; i++) {
1866                                 if (ni_readb(XXX_Status) & 0x80) {
1867                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1868                                             & 0xffff;
1869                                         break;
1870                                 }
1871                                 if (!(devpriv->stc_readw(dev,
1872                                                          AI_Status_1_Register) &
1873                                       AI_FIFO_Empty_St)) {
1874                                         d = ni_readl(ADC_FIFO_Data_611x) &
1875                                             0xffff;
1876                                         break;
1877                                 }
1878                         }
1879                         if (i == NI_TIMEOUT) {
1880                                 printk
1881                                     ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1882                                 return -ETIME;
1883                         }
1884                         d += signbits;
1885                         data[n] = d;
1886                 }
1887         } else if (board->reg_type == ni_reg_6143) {
1888                 for (n = 0; n < insn->n; n++) {
1889                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1890                                             AI_Command_1_Register);
1891
1892                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1893                         dl = 0;
1894                         for (i = 0; i < NI_TIMEOUT; i++) {
1895                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1896                                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1897                                         dl = ni_readl(AIFIFO_Data_6143);
1898                                         break;
1899                                 }
1900                         }
1901                         if (i == NI_TIMEOUT) {
1902                                 printk
1903                                     ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1904                                 return -ETIME;
1905                         }
1906                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1907                 }
1908         } else {
1909                 for (n = 0; n < insn->n; n++) {
1910                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1911                                             AI_Command_1_Register);
1912                         for (i = 0; i < NI_TIMEOUT; i++) {
1913                                 if (!(devpriv->stc_readw(dev,
1914                                                          AI_Status_1_Register) &
1915                                       AI_FIFO_Empty_St))
1916                                         break;
1917                         }
1918                         if (i == NI_TIMEOUT) {
1919                                 printk
1920                                     ("ni_mio_common: timeout in ni_ai_insn_read\n");
1921                                 return -ETIME;
1922                         }
1923                         if (board->reg_type & ni_reg_m_series_mask) {
1924                                 data[n] =
1925                                     ni_readl(M_Offset_AI_FIFO_Data) & mask;
1926                         } else {
1927                                 d = ni_readw(ADC_FIFO_Data_Register);
1928                                 d += signbits;  /* subtle: needs to be short addition */
1929                                 data[n] = d;
1930                         }
1931                 }
1932         }
1933         return insn->n;
1934 }
1935
1936 static void ni_prime_channelgain_list(struct comedi_device *dev)
1937 {
1938         struct ni_private *devpriv = dev->private;
1939         int i;
1940
1941         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1942         for (i = 0; i < NI_TIMEOUT; ++i) {
1943                 if (!(devpriv->stc_readw(dev,
1944                                          AI_Status_1_Register) &
1945                       AI_FIFO_Empty_St)) {
1946                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1947                         return;
1948                 }
1949                 udelay(1);
1950         }
1951         printk("ni_mio_common: timeout loading channel/gain list\n");
1952 }
1953
1954 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1955                                               unsigned int n_chan,
1956                                               unsigned int *list)
1957 {
1958         const struct ni_board_struct *board = comedi_board(dev);
1959         struct ni_private *devpriv = dev->private;
1960         unsigned int chan, range, aref;
1961         unsigned int i;
1962         unsigned offset;
1963         unsigned int dither;
1964         unsigned range_code;
1965
1966         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1967
1968 /* offset = 1 << (board->adbits - 1); */
1969         if ((list[0] & CR_ALT_SOURCE)) {
1970                 unsigned bypass_bits;
1971                 chan = CR_CHAN(list[0]);
1972                 range = CR_RANGE(list[0]);
1973                 range_code = ni_gainlkup[board->gainlkup][range];
1974                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1975                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1976                 bypass_bits |= chan;
1977                 bypass_bits |=
1978                     (devpriv->ai_calib_source) &
1979                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1980                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1981                      MSeries_AI_Bypass_Mode_Mux_Mask |
1982                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1983                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1984                 if (dither)
1985                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1986                 /*  don't use 2's complement encoding */
1987                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1988                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1989         } else {
1990                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1991         }
1992         offset = 0;
1993         for (i = 0; i < n_chan; i++) {
1994                 unsigned config_bits = 0;
1995                 chan = CR_CHAN(list[i]);
1996                 aref = CR_AREF(list[i]);
1997                 range = CR_RANGE(list[i]);
1998                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1999
2000                 range_code = ni_gainlkup[board->gainlkup][range];
2001                 devpriv->ai_offset[i] = offset;
2002                 switch (aref) {
2003                 case AREF_DIFF:
2004                         config_bits |=
2005                             MSeries_AI_Config_Channel_Type_Differential_Bits;
2006                         break;
2007                 case AREF_COMMON:
2008                         config_bits |=
2009                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2010                         break;
2011                 case AREF_GROUND:
2012                         config_bits |=
2013                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2014                         break;
2015                 case AREF_OTHER:
2016                         break;
2017                 }
2018                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2019                 config_bits |=
2020                     MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2021                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2022                 if (i == n_chan - 1)
2023                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2024                 if (dither)
2025                         config_bits |= MSeries_AI_Config_Dither_Bit;
2026                 /*  don't use 2's complement encoding */
2027                 config_bits |= MSeries_AI_Config_Polarity_Bit;
2028                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2029         }
2030         ni_prime_channelgain_list(dev);
2031 }
2032
2033 /*
2034  * Notes on the 6110 and 6111:
2035  * These boards a slightly different than the rest of the series, since
2036  * they have multiple A/D converters.
2037  * From the driver side, the configuration memory is a
2038  * little different.
2039  * Configuration Memory Low:
2040  *   bits 15-9: same
2041  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
2042  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
2043  *       1001 gain=0.1 (+/- 50)
2044  *       1010 0.2
2045  *       1011 0.1
2046  *       0001 1
2047  *       0010 2
2048  *       0011 5
2049  *       0100 10
2050  *       0101 20
2051  *       0110 50
2052  * Configuration Memory High:
2053  *   bits 12-14: Channel Type
2054  *       001 for differential
2055  *       000 for calibration
2056  *   bit 11: coupling  (this is not currently handled)
2057  *       1 AC coupling
2058  *       0 DC coupling
2059  *   bits 0-2: channel
2060  *       valid channels are 0-3
2061  */
2062 static void ni_load_channelgain_list(struct comedi_device *dev,
2063                                      unsigned int n_chan, unsigned int *list)
2064 {
2065         const struct ni_board_struct *board = comedi_board(dev);
2066         struct ni_private *devpriv = dev->private;
2067         unsigned int chan, range, aref;
2068         unsigned int i;
2069         unsigned int hi, lo;
2070         unsigned offset;
2071         unsigned int dither;
2072
2073         if (board->reg_type & ni_reg_m_series_mask) {
2074                 ni_m_series_load_channelgain_list(dev, n_chan, list);
2075                 return;
2076         }
2077         if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2078             && (board->reg_type != ni_reg_6143)) {
2079                 if (devpriv->changain_state
2080                     && devpriv->changain_spec == list[0]) {
2081                         /*  ready to go. */
2082                         return;
2083                 }
2084                 devpriv->changain_state = 1;
2085                 devpriv->changain_spec = list[0];
2086         } else {
2087                 devpriv->changain_state = 0;
2088         }
2089
2090         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2091
2092         /*  Set up Calibration mode if required */
2093         if (board->reg_type == ni_reg_6143) {
2094                 if ((list[0] & CR_ALT_SOURCE)
2095                     && !devpriv->ai_calib_source_enabled) {
2096                         /*  Strobe Relay enable bit */
2097                         ni_writew(devpriv->ai_calib_source |
2098                                   Calibration_Channel_6143_RelayOn,
2099                                   Calibration_Channel_6143);
2100                         ni_writew(devpriv->ai_calib_source,
2101                                   Calibration_Channel_6143);
2102                         devpriv->ai_calib_source_enabled = 1;
2103                         msleep_interruptible(100);      /*  Allow relays to change */
2104                 } else if (!(list[0] & CR_ALT_SOURCE)
2105                            && devpriv->ai_calib_source_enabled) {
2106                         /*  Strobe Relay disable bit */
2107                         ni_writew(devpriv->ai_calib_source |
2108                                   Calibration_Channel_6143_RelayOff,
2109                                   Calibration_Channel_6143);
2110                         ni_writew(devpriv->ai_calib_source,
2111                                   Calibration_Channel_6143);
2112                         devpriv->ai_calib_source_enabled = 0;
2113                         msleep_interruptible(100);      /*  Allow relays to change */
2114                 }
2115         }
2116
2117         offset = 1 << (board->adbits - 1);
2118         for (i = 0; i < n_chan; i++) {
2119                 if ((board->reg_type != ni_reg_6143)
2120                     && (list[i] & CR_ALT_SOURCE)) {
2121                         chan = devpriv->ai_calib_source;
2122                 } else {
2123                         chan = CR_CHAN(list[i]);
2124                 }
2125                 aref = CR_AREF(list[i]);
2126                 range = CR_RANGE(list[i]);
2127                 dither = ((list[i] & CR_ALT_FILTER) != 0);
2128
2129                 /* fix the external/internal range differences */
2130                 range = ni_gainlkup[board->gainlkup][range];
2131                 if (board->reg_type == ni_reg_611x)
2132                         devpriv->ai_offset[i] = offset;
2133                 else
2134                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2135
2136                 hi = 0;
2137                 if ((list[i] & CR_ALT_SOURCE)) {
2138                         if (board->reg_type == ni_reg_611x)
2139                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2140                                           Calibration_Channel_Select_611x);
2141                 } else {
2142                         if (board->reg_type == ni_reg_611x)
2143                                 aref = AREF_DIFF;
2144                         else if (board->reg_type == ni_reg_6143)
2145                                 aref = AREF_OTHER;
2146                         switch (aref) {
2147                         case AREF_DIFF:
2148                                 hi |= AI_DIFFERENTIAL;
2149                                 break;
2150                         case AREF_COMMON:
2151                                 hi |= AI_COMMON;
2152                                 break;
2153                         case AREF_GROUND:
2154                                 hi |= AI_GROUND;
2155                                 break;
2156                         case AREF_OTHER:
2157                                 break;
2158                         }
2159                 }
2160                 hi |= AI_CONFIG_CHANNEL(chan);
2161
2162                 ni_writew(hi, Configuration_Memory_High);
2163
2164                 if (board->reg_type != ni_reg_6143) {
2165                         lo = range;
2166                         if (i == n_chan - 1)
2167                                 lo |= AI_LAST_CHANNEL;
2168                         if (dither)
2169                                 lo |= AI_DITHER;
2170
2171                         ni_writew(lo, Configuration_Memory_Low);
2172                 }
2173         }
2174
2175         /* prime the channel/gain list */
2176         if ((board->reg_type != ni_reg_611x)
2177             && (board->reg_type != ni_reg_6143)) {
2178                 ni_prime_channelgain_list(dev);
2179         }
2180 }
2181
2182 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2183                           int round_mode)
2184 {
2185         struct ni_private *devpriv = dev->private;
2186         int divider;
2187
2188         switch (round_mode) {
2189         case TRIG_ROUND_NEAREST:
2190         default:
2191                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2192                 break;
2193         case TRIG_ROUND_DOWN:
2194                 divider = (nanosec) / devpriv->clock_ns;
2195                 break;
2196         case TRIG_ROUND_UP:
2197                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2198                 break;
2199         }
2200         return divider - 1;
2201 }
2202
2203 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2204 {
2205         struct ni_private *devpriv = dev->private;
2206
2207         return devpriv->clock_ns * (timer + 1);
2208 }
2209
2210 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2211                                          unsigned num_channels)
2212 {
2213         const struct ni_board_struct *board = comedi_board(dev);
2214
2215         switch (board->reg_type) {
2216         case ni_reg_611x:
2217         case ni_reg_6143:
2218                 /*  simultaneously-sampled inputs */
2219                 return board->ai_speed;
2220                 break;
2221         default:
2222                 /*  multiplexed inputs */
2223                 break;
2224         }
2225         return board->ai_speed * num_channels;
2226 }
2227
2228 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2229                          struct comedi_cmd *cmd)
2230 {
2231         const struct ni_board_struct *board = comedi_board(dev);
2232         struct ni_private *devpriv = dev->private;
2233         int err = 0;
2234         int tmp;
2235         unsigned int sources;
2236
2237         /* Step 1 : check if triggers are trivially valid */
2238
2239         if ((cmd->flags & CMDF_WRITE))
2240                 cmd->flags &= ~CMDF_WRITE;
2241
2242         err |= cfc_check_trigger_src(&cmd->start_src,
2243                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2244         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2245                                         TRIG_TIMER | TRIG_EXT);
2246
2247         sources = TRIG_TIMER | TRIG_EXT;
2248         if (board->reg_type == ni_reg_611x ||
2249             board->reg_type == ni_reg_6143)
2250                 sources |= TRIG_NOW;
2251         err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2252
2253         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2254         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2255
2256         if (err)
2257                 return 1;
2258
2259         /* Step 2a : make sure trigger sources are unique */
2260
2261         err |= cfc_check_trigger_is_unique(cmd->start_src);
2262         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2263         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2264         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2265
2266         /* Step 2b : and mutually compatible */
2267
2268         if (err)
2269                 return 2;
2270
2271         /* Step 3: check if arguments are trivially valid */
2272
2273         if (cmd->start_src == TRIG_EXT) {
2274                 /* external trigger */
2275                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2276
2277                 if (tmp > 16)
2278                         tmp = 16;
2279                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2280                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2281         } else {
2282                 /* true for both TRIG_NOW and TRIG_INT */
2283                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2284         }
2285
2286         if (cmd->scan_begin_src == TRIG_TIMER) {
2287                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2288                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2289                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2290                                                  devpriv->clock_ns * 0xffffff);
2291         } else if (cmd->scan_begin_src == TRIG_EXT) {
2292                 /* external trigger */
2293                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2294
2295                 if (tmp > 16)
2296                         tmp = 16;
2297                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2298                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2299         } else {                /* TRIG_OTHER */
2300                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2301         }
2302
2303         if (cmd->convert_src == TRIG_TIMER) {
2304                 if ((board->reg_type == ni_reg_611x)
2305                     || (board->reg_type == ni_reg_6143)) {
2306                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2307                 } else {
2308                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2309                                                          board->ai_speed);
2310                         err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2311                                                 devpriv->clock_ns * 0xffff);
2312                 }
2313         } else if (cmd->convert_src == TRIG_EXT) {
2314                 /* external trigger */
2315                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2316
2317                 if (tmp > 16)
2318                         tmp = 16;
2319                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2320                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2321         } else if (cmd->convert_src == TRIG_NOW) {
2322                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2323         }
2324
2325         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2326
2327         if (cmd->stop_src == TRIG_COUNT) {
2328                 unsigned int max_count = 0x01000000;
2329
2330                 if (board->reg_type == ni_reg_611x)
2331                         max_count -= num_adc_stages_611x;
2332                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2333                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2334         } else {
2335                 /* TRIG_NONE */
2336                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2337         }
2338
2339         if (err)
2340                 return 3;
2341
2342         /* step 4: fix up any arguments */
2343
2344         if (cmd->scan_begin_src == TRIG_TIMER) {
2345                 tmp = cmd->scan_begin_arg;
2346                 cmd->scan_begin_arg =
2347                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2348                                                        cmd->scan_begin_arg,
2349                                                        cmd->
2350                                                        flags &
2351                                                        TRIG_ROUND_MASK));
2352                 if (tmp != cmd->scan_begin_arg)
2353                         err++;
2354         }
2355         if (cmd->convert_src == TRIG_TIMER) {
2356                 if ((board->reg_type != ni_reg_611x)
2357                     && (board->reg_type != ni_reg_6143)) {
2358                         tmp = cmd->convert_arg;
2359                         cmd->convert_arg =
2360                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2361                                                                cmd->convert_arg,
2362                                                                cmd->
2363                                                                flags &
2364                                                                TRIG_ROUND_MASK));
2365                         if (tmp != cmd->convert_arg)
2366                                 err++;
2367                         if (cmd->scan_begin_src == TRIG_TIMER &&
2368                             cmd->scan_begin_arg <
2369                             cmd->convert_arg * cmd->scan_end_arg) {
2370                                 cmd->scan_begin_arg =
2371                                     cmd->convert_arg * cmd->scan_end_arg;
2372                                 err++;
2373                         }
2374                 }
2375         }
2376
2377         if (err)
2378                 return 4;
2379
2380         return 0;
2381 }
2382
2383 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2384 {
2385         const struct ni_board_struct *board = comedi_board(dev);
2386         struct ni_private *devpriv = dev->private;
2387         const struct comedi_cmd *cmd = &s->async->cmd;
2388         int timer;
2389         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2390         int mode2 = 0;
2391         int start_stop_select = 0;
2392         unsigned int stop_count;
2393         int interrupt_a_enable = 0;
2394
2395         MDPRINTK("ni_ai_cmd\n");
2396         if (dev->irq == 0) {
2397                 comedi_error(dev, "cannot run command without an irq");
2398                 return -EIO;
2399         }
2400         ni_clear_ai_fifo(dev);
2401
2402         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2403
2404         /* start configuration */
2405         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2406
2407         /* disable analog triggering for now, since it
2408          * interferes with the use of pfi0 */
2409         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2410         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2411                             Analog_Trigger_Etc_Register);
2412
2413         switch (cmd->start_src) {
2414         case TRIG_INT:
2415         case TRIG_NOW:
2416                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2417                                     AI_START1_Sync | AI_START1_Edge |
2418                                     AI_START1_Select(0),
2419                                     AI_Trigger_Select_Register);
2420                 break;
2421         case TRIG_EXT:
2422                 {
2423                         int chan = CR_CHAN(cmd->start_arg);
2424                         unsigned int bits = AI_START2_Select(0) |
2425                             AI_START1_Sync | AI_START1_Select(chan + 1);
2426
2427                         if (cmd->start_arg & CR_INVERT)
2428                                 bits |= AI_START1_Polarity;
2429                         if (cmd->start_arg & CR_EDGE)
2430                                 bits |= AI_START1_Edge;
2431                         devpriv->stc_writew(dev, bits,
2432                                             AI_Trigger_Select_Register);
2433                         break;
2434                 }
2435         }
2436
2437         mode2 &= ~AI_Pre_Trigger;
2438         mode2 &= ~AI_SC_Initial_Load_Source;
2439         mode2 &= ~AI_SC_Reload_Mode;
2440         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2441
2442         if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2443             || (board->reg_type == ni_reg_6143)) {
2444                 start_stop_select |= AI_STOP_Polarity;
2445                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2446                 start_stop_select |= AI_STOP_Sync;
2447         } else {
2448                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2449         }
2450         devpriv->stc_writew(dev, start_stop_select,
2451                             AI_START_STOP_Select_Register);
2452
2453         devpriv->ai_cmd2 = 0;
2454         switch (cmd->stop_src) {
2455         case TRIG_COUNT:
2456                 stop_count = cmd->stop_arg - 1;
2457
2458                 if (board->reg_type == ni_reg_611x) {
2459                         /*  have to take 3 stage adc pipeline into account */
2460                         stop_count += num_adc_stages_611x;
2461                 }
2462                 /* stage number of scans */
2463                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2464
2465                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2466                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2467                 /* load SC (Scan Count) */
2468                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2469
2470                 devpriv->ai_continuous = 0;
2471                 if (stop_count == 0) {
2472                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2473                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2474                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2475                         if (cmd->chanlist_len > 1)
2476                                 start_stop_select |=
2477                                     AI_STOP_Polarity | AI_STOP_Edge;
2478                 }
2479                 break;
2480         case TRIG_NONE:
2481                 /* stage number of scans */
2482                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2483
2484                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2485                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2486
2487                 /* load SC (Scan Count) */
2488                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2489
2490                 devpriv->ai_continuous = 1;
2491
2492                 break;
2493         }
2494
2495         switch (cmd->scan_begin_src) {
2496         case TRIG_TIMER:
2497                 /*
2498                    stop bits for non 611x boards
2499                    AI_SI_Special_Trigger_Delay=0
2500                    AI_Pre_Trigger=0
2501                    AI_START_STOP_Select_Register:
2502                    AI_START_Polarity=0 (?)      rising edge
2503                    AI_START_Edge=1              edge triggered
2504                    AI_START_Sync=1 (?)
2505                    AI_START_Select=0            SI_TC
2506                    AI_STOP_Polarity=0           rising edge
2507                    AI_STOP_Edge=0               level
2508                    AI_STOP_Sync=1
2509                    AI_STOP_Select=19            external pin (configuration mem)
2510                  */
2511                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2512                 devpriv->stc_writew(dev, start_stop_select,
2513                                     AI_START_STOP_Select_Register);
2514
2515                 mode2 |= AI_SI_Reload_Mode(0);
2516                 /* AI_SI_Initial_Load_Source=A */
2517                 mode2 &= ~AI_SI_Initial_Load_Source;
2518                 /* mode2 |= AI_SC_Reload_Mode; */
2519                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2520
2521                 /* load SI */
2522                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2523                                        TRIG_ROUND_NEAREST);
2524                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2525                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2526                 break;
2527         case TRIG_EXT:
2528                 if (cmd->scan_begin_arg & CR_EDGE)
2529                         start_stop_select |= AI_START_Edge;
2530                 /* AI_START_Polarity==1 is falling edge */
2531                 if (cmd->scan_begin_arg & CR_INVERT)
2532                         start_stop_select |= AI_START_Polarity;
2533                 if (cmd->scan_begin_src != cmd->convert_src ||
2534                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2535                     (cmd->convert_arg & ~CR_EDGE))
2536                         start_stop_select |= AI_START_Sync;
2537                 start_stop_select |=
2538                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2539                 devpriv->stc_writew(dev, start_stop_select,
2540                                     AI_START_STOP_Select_Register);
2541                 break;
2542         }
2543
2544         switch (cmd->convert_src) {
2545         case TRIG_TIMER:
2546         case TRIG_NOW:
2547                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2548                         timer = 1;
2549                 else
2550                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2551                                                TRIG_ROUND_NEAREST);
2552                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2553                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2554
2555                 /* AI_SI2_Reload_Mode = alternate */
2556                 /* AI_SI2_Initial_Load_Source = A */
2557                 mode2 &= ~AI_SI2_Initial_Load_Source;
2558                 mode2 |= AI_SI2_Reload_Mode;
2559                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2560
2561                 /* AI_SI2_Load */
2562                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2563
2564                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2565                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2566
2567                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2568                 break;
2569         case TRIG_EXT:
2570                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2571                 if ((cmd->convert_arg & CR_INVERT) == 0)
2572                         mode1 |= AI_CONVERT_Source_Polarity;
2573                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2574
2575                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2576                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2577
2578                 break;
2579         }
2580
2581         if (dev->irq) {
2582
2583                 /* interrupt on FIFO, errors, SC_TC */
2584                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2585                     AI_SC_TC_Interrupt_Enable;
2586
2587 #ifndef PCIDMA
2588                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2589 #endif
2590
2591                 if (cmd->flags & TRIG_WAKE_EOS
2592                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2593                         /* wake on end-of-scan */
2594                         devpriv->aimode = AIMODE_SCAN;
2595                 } else {
2596                         devpriv->aimode = AIMODE_HALF_FULL;
2597                 }
2598
2599                 switch (devpriv->aimode) {
2600                 case AIMODE_HALF_FULL:
2601                         /*generate FIFO interrupts and DMA requests on half-full */
2602 #ifdef PCIDMA
2603                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2604                                             AI_Mode_3_Register);
2605 #else
2606                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2607                                             AI_Mode_3_Register);
2608 #endif
2609                         break;
2610                 case AIMODE_SAMPLE:
2611                         /*generate FIFO interrupts on non-empty */
2612                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2613                                             AI_Mode_3_Register);
2614                         break;
2615                 case AIMODE_SCAN:
2616 #ifdef PCIDMA
2617                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2618                                             AI_Mode_3_Register);
2619 #else
2620                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2621                                             AI_Mode_3_Register);
2622 #endif
2623                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2624                         break;
2625                 default:
2626                         break;
2627                 }
2628
2629                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2630
2631                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2632                             interrupt_a_enable, 1);
2633
2634                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2635                          devpriv->int_a_enable_reg);
2636         } else {
2637                 /* interrupt on nothing */
2638                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2639
2640                 /* XXX start polling if necessary */
2641                 MDPRINTK("interrupting on nothing\n");
2642         }
2643
2644         /* end configuration */
2645         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2646
2647         switch (cmd->scan_begin_src) {
2648         case TRIG_TIMER:
2649                 devpriv->stc_writew(dev,
2650                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2651                                     AI_SC_Arm, AI_Command_1_Register);
2652                 break;
2653         case TRIG_EXT:
2654                 /* XXX AI_SI_Arm? */
2655                 devpriv->stc_writew(dev,
2656                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2657                                     AI_SC_Arm, AI_Command_1_Register);
2658                 break;
2659         }
2660
2661 #ifdef PCIDMA
2662         {
2663                 int retval = ni_ai_setup_MITE_dma(dev);
2664                 if (retval)
2665                         return retval;
2666         }
2667         /* mite_dump_regs(devpriv->mite); */
2668 #endif
2669
2670         switch (cmd->start_src) {
2671         case TRIG_NOW:
2672                 /* AI_START1_Pulse */
2673                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2674                                     AI_Command_2_Register);
2675                 s->async->inttrig = NULL;
2676                 break;
2677         case TRIG_EXT:
2678                 s->async->inttrig = NULL;
2679                 break;
2680         case TRIG_INT:
2681                 s->async->inttrig = &ni_ai_inttrig;
2682                 break;
2683         }
2684
2685         MDPRINTK("exit ni_ai_cmd\n");
2686
2687         return 0;
2688 }
2689
2690 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2691                          unsigned int trignum)
2692 {
2693         struct ni_private *devpriv = dev->private;
2694
2695         if (trignum != 0)
2696                 return -EINVAL;
2697
2698         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2699                             AI_Command_2_Register);
2700         s->async->inttrig = NULL;
2701
2702         return 1;
2703 }
2704
2705 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2706                                     struct comedi_subdevice *s,
2707                                     struct comedi_insn *insn,
2708                                     unsigned int *data);
2709
2710 static int ni_ai_insn_config(struct comedi_device *dev,
2711                              struct comedi_subdevice *s,
2712                              struct comedi_insn *insn, unsigned int *data)
2713 {
2714         const struct ni_board_struct *board = comedi_board(dev);
2715         struct ni_private *devpriv = dev->private;
2716
2717         if (insn->n < 1)
2718                 return -EINVAL;
2719
2720         switch (data[0]) {
2721         case INSN_CONFIG_ANALOG_TRIG:
2722                 return ni_ai_config_analog_trig(dev, s, insn, data);
2723         case INSN_CONFIG_ALT_SOURCE:
2724                 if (board->reg_type & ni_reg_m_series_mask) {
2725                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2726                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2727                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2728                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2729                                 return -EINVAL;
2730                         }
2731                         devpriv->ai_calib_source = data[1];
2732                 } else if (board->reg_type == ni_reg_6143) {
2733                         unsigned int calib_source;
2734
2735                         calib_source = data[1] & 0xf;
2736
2737                         if (calib_source > 0xF)
2738                                 return -EINVAL;
2739
2740                         devpriv->ai_calib_source = calib_source;
2741                         ni_writew(calib_source, Calibration_Channel_6143);
2742                 } else {
2743                         unsigned int calib_source;
2744                         unsigned int calib_source_adjust;
2745
2746                         calib_source = data[1] & 0xf;
2747                         calib_source_adjust = (data[1] >> 4) & 0xff;
2748
2749                         if (calib_source >= 8)
2750                                 return -EINVAL;
2751                         devpriv->ai_calib_source = calib_source;
2752                         if (board->reg_type == ni_reg_611x) {
2753                                 ni_writeb(calib_source_adjust,
2754                                           Cal_Gain_Select_611x);
2755                         }
2756                 }
2757                 return 2;
2758         default:
2759                 break;
2760         }
2761
2762         return -EINVAL;
2763 }
2764
2765 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2766                                     struct comedi_subdevice *s,
2767                                     struct comedi_insn *insn,
2768                                     unsigned int *data)
2769 {
2770         const struct ni_board_struct *board = comedi_board(dev);
2771         struct ni_private *devpriv = dev->private;
2772         unsigned int a, b, modebits;
2773         int err = 0;
2774
2775         /* data[1] is flags
2776          * data[2] is analog line
2777          * data[3] is set level
2778          * data[4] is reset level */
2779         if (!board->has_analog_trig)
2780                 return -EINVAL;
2781         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2782                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2783                 err++;
2784         }
2785         if (data[2] >= board->n_adchan) {
2786                 data[2] = board->n_adchan - 1;
2787                 err++;
2788         }
2789         if (data[3] > 255) {    /* a */
2790                 data[3] = 255;
2791                 err++;
2792         }
2793         if (data[4] > 255) {    /* b */
2794                 data[4] = 255;
2795                 err++;
2796         }
2797         /*
2798          * 00 ignore
2799          * 01 set
2800          * 10 reset
2801          *
2802          * modes:
2803          *   1 level:                    +b-   +a-
2804          *     high mode                00 00 01 10
2805          *     low mode                 00 00 10 01
2806          *   2 level: (a<b)
2807          *     hysteresis low mode      10 00 00 01
2808          *     hysteresis high mode     01 00 00 10
2809          *     middle mode              10 01 01 10
2810          */
2811
2812         a = data[3];
2813         b = data[4];
2814         modebits = data[1] & 0xff;
2815         if (modebits & 0xf0) {
2816                 /* two level mode */
2817                 if (b < a) {
2818                         /* swap order */
2819                         a = data[4];
2820                         b = data[3];
2821                         modebits =
2822                             ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2823                 }
2824                 devpriv->atrig_low = a;
2825                 devpriv->atrig_high = b;
2826                 switch (modebits) {
2827                 case 0x81:      /* low hysteresis mode */
2828                         devpriv->atrig_mode = 6;
2829                         break;
2830                 case 0x42:      /* high hysteresis mode */
2831                         devpriv->atrig_mode = 3;
2832                         break;
2833                 case 0x96:      /* middle window mode */
2834                         devpriv->atrig_mode = 2;
2835                         break;
2836                 default:
2837                         data[1] &= ~0xff;
2838                         err++;
2839                 }
2840         } else {
2841                 /* one level mode */
2842                 if (b != 0) {
2843                         data[4] = 0;
2844                         err++;
2845                 }
2846                 switch (modebits) {
2847                 case 0x06:      /* high window mode */
2848                         devpriv->atrig_high = a;
2849                         devpriv->atrig_mode = 0;
2850                         break;
2851                 case 0x09:      /* low window mode */
2852                         devpriv->atrig_low = a;
2853                         devpriv->atrig_mode = 1;
2854                         break;
2855                 default:
2856                         data[1] &= ~0xff;
2857                         err++;
2858                 }
2859         }
2860         if (err)
2861                 return -EAGAIN;
2862         return 5;
2863 }
2864
2865 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2866 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2867                         void *data, unsigned int num_bytes,
2868                         unsigned int chan_index)
2869 {
2870         const struct ni_board_struct *board = comedi_board(dev);
2871         struct comedi_async *async = s->async;
2872         unsigned int range;
2873         unsigned int i;
2874         unsigned int offset;
2875         unsigned int length = num_bytes / sizeof(short);
2876         short *array = data;
2877
2878         offset = 1 << (board->aobits - 1);
2879         for (i = 0; i < length; i++) {
2880                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2881                 if (board->ao_unipolar == 0 || (range & 1) == 0)
2882                         array[i] -= offset;
2883 #ifdef PCIDMA
2884                 array[i] = cpu_to_le16(array[i]);
2885 #endif
2886                 chan_index++;
2887                 chan_index %= async->cmd.chanlist_len;
2888         }
2889 }
2890
2891 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2892                                           struct comedi_subdevice *s,
2893                                           unsigned int chanspec[],
2894                                           unsigned int n_chans, int timed)
2895 {
2896         const struct ni_board_struct *board = comedi_board(dev);
2897         struct ni_private *devpriv = dev->private;
2898         unsigned int range;
2899         unsigned int chan;
2900         unsigned int conf;
2901         int i;
2902         int invert = 0;
2903
2904         if (timed) {
2905                 for (i = 0; i < board->n_aochan; ++i) {
2906                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2907                         ni_writeb(devpriv->ao_conf[i],
2908                                   M_Offset_AO_Config_Bank(i));
2909                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2910                 }
2911         }
2912         for (i = 0; i < n_chans; i++) {
2913                 const struct comedi_krange *krange;
2914                 chan = CR_CHAN(chanspec[i]);
2915                 range = CR_RANGE(chanspec[i]);
2916                 krange = s->range_table->range + range;
2917                 invert = 0;
2918                 conf = 0;
2919                 switch (krange->max - krange->min) {
2920                 case 20000000:
2921                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2922                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2923                         break;
2924                 case 10000000:
2925                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2926                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2927                         break;
2928                 case 4000000:
2929                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2930                         ni_writeb(MSeries_Attenuate_x5_Bit,
2931                                   M_Offset_AO_Reference_Attenuation(chan));
2932                         break;
2933                 case 2000000:
2934                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2935                         ni_writeb(MSeries_Attenuate_x5_Bit,
2936                                   M_Offset_AO_Reference_Attenuation(chan));
2937                         break;
2938                 default:
2939                         printk("%s: bug! unhandled ao reference voltage\n",
2940                                __func__);
2941                         break;
2942                 }
2943                 switch (krange->max + krange->min) {
2944                 case 0:
2945                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2946                         break;
2947                 case 10000000:
2948                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2949                         break;
2950                 default:
2951                         printk("%s: bug! unhandled ao offset voltage\n",
2952                                __func__);
2953                         break;
2954                 }
2955                 if (timed)
2956                         conf |= MSeries_AO_Update_Timed_Bit;
2957                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2958                 devpriv->ao_conf[chan] = conf;
2959                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2960         }
2961         return invert;
2962 }
2963
2964 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2965                                      struct comedi_subdevice *s,
2966                                      unsigned int chanspec[],
2967                                      unsigned int n_chans)
2968 {
2969         const struct ni_board_struct *board = comedi_board(dev);
2970         struct ni_private *devpriv = dev->private;
2971         unsigned int range;
2972         unsigned int chan;
2973         unsigned int conf;
2974         int i;
2975         int invert = 0;
2976
2977         for (i = 0; i < n_chans; i++) {
2978                 chan = CR_CHAN(chanspec[i]);
2979                 range = CR_RANGE(chanspec[i]);
2980                 conf = AO_Channel(chan);
2981
2982                 if (board->ao_unipolar) {
2983                         if ((range & 1) == 0) {
2984                                 conf |= AO_Bipolar;
2985                                 invert = (1 << (board->aobits - 1));
2986                         } else {
2987                                 invert = 0;
2988                         }
2989                         if (range & 2)
2990                                 conf |= AO_Ext_Ref;
2991                 } else {
2992                         conf |= AO_Bipolar;
2993                         invert = (1 << (board->aobits - 1));
2994                 }
2995
2996                 /* not all boards can deglitch, but this shouldn't hurt */
2997                 if (chanspec[i] & CR_DEGLITCH)
2998                         conf |= AO_Deglitch;
2999
3000                 /* analog reference */
3001                 /* AREF_OTHER connects AO ground to AI ground, i think */
3002                 conf |= (CR_AREF(chanspec[i]) ==
3003                          AREF_OTHER) ? AO_Ground_Ref : 0;
3004
3005                 ni_writew(conf, AO_Configuration);
3006                 devpriv->ao_conf[chan] = conf;
3007         }
3008         return invert;
3009 }
3010
3011 static int ni_ao_config_chanlist(struct comedi_device *dev,
3012                                  struct comedi_subdevice *s,
3013                                  unsigned int chanspec[], unsigned int n_chans,
3014                                  int timed)
3015 {
3016         const struct ni_board_struct *board = comedi_board(dev);
3017
3018         if (board->reg_type & ni_reg_m_series_mask)
3019                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3020                                                       timed);
3021         else
3022                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3023 }
3024
3025 static int ni_ao_insn_read(struct comedi_device *dev,
3026                            struct comedi_subdevice *s, struct comedi_insn *insn,
3027                            unsigned int *data)
3028 {
3029         struct ni_private *devpriv = dev->private;
3030
3031         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3032
3033         return 1;
3034 }
3035
3036 static int ni_ao_insn_write(struct comedi_device *dev,
3037                             struct comedi_subdevice *s,
3038                             struct comedi_insn *insn, unsigned int *data)
3039 {
3040         const struct ni_board_struct *board = comedi_board(dev);
3041         struct ni_private *devpriv = dev->private;
3042         unsigned int chan = CR_CHAN(insn->chanspec);
3043         unsigned int invert;
3044
3045         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3046
3047         devpriv->ao[chan] = data[0];
3048
3049         if (board->reg_type & ni_reg_m_series_mask) {
3050                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3051         } else
3052                 ni_writew(data[0] ^ invert,
3053                           (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3054
3055         return 1;
3056 }
3057
3058 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3059                                  struct comedi_subdevice *s,
3060                                  struct comedi_insn *insn, unsigned int *data)
3061 {
3062         const struct ni_board_struct *board = comedi_board(dev);
3063         struct ni_private *devpriv = dev->private;
3064         unsigned int chan = CR_CHAN(insn->chanspec);
3065         unsigned int invert;
3066
3067         ao_win_out(1 << chan, AO_Immediate_671x);
3068         invert = 1 << (board->aobits - 1);
3069
3070         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3071
3072         devpriv->ao[chan] = data[0];
3073         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3074
3075         return 1;
3076 }
3077
3078 static int ni_ao_insn_config(struct comedi_device *dev,
3079                              struct comedi_subdevice *s,
3080                              struct comedi_insn *insn, unsigned int *data)
3081 {
3082         const struct ni_board_struct *board = comedi_board(dev);
3083         struct ni_private *devpriv = dev->private;
3084
3085         switch (data[0]) {
3086         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3087                 switch (data[1]) {
3088                 case COMEDI_OUTPUT:
3089                         data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3090                         if (devpriv->mite)
3091                                 data[2] += devpriv->mite->fifo_size;
3092                         break;
3093                 case COMEDI_INPUT:
3094                         data[2] = 0;
3095                         break;
3096                 default:
3097                         return -EINVAL;
3098                         break;
3099                 }
3100                 return 0;
3101         default:
3102                 break;
3103         }
3104
3105         return -EINVAL;
3106 }
3107
3108 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3109                          unsigned int trignum)
3110 {
3111         const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3112         struct ni_private *devpriv = dev->private;
3113         int ret;
3114         int interrupt_b_bits;
3115         int i;
3116         static const int timeout = 1000;
3117
3118         if (trignum != 0)
3119                 return -EINVAL;
3120
3121         /* Null trig at beginning prevent ao start trigger from executing more than
3122            once per command (and doing things like trying to allocate the ao dma channel
3123            multiple times) */
3124         s->async->inttrig = NULL;
3125
3126         ni_set_bits(dev, Interrupt_B_Enable_Register,
3127                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3128         interrupt_b_bits = AO_Error_Interrupt_Enable;
3129 #ifdef PCIDMA
3130         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3131         if (board->reg_type & ni_reg_6xxx_mask)
3132                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3133         ret = ni_ao_setup_MITE_dma(dev);
3134         if (ret)
3135                 return ret;
3136         ret = ni_ao_wait_for_dma_load(dev);
3137         if (ret < 0)
3138                 return ret;
3139 #else
3140         ret = ni_ao_prep_fifo(dev, s);
3141         if (ret == 0)
3142                 return -EPIPE;
3143
3144         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3145 #endif
3146
3147         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3148                             AO_Mode_3_Register);
3149         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3150         /* wait for DACs to be loaded */
3151         for (i = 0; i < timeout; i++) {
3152                 udelay(1);
3153                 if ((devpriv->stc_readw(dev,
3154                                         Joint_Status_2_Register) &
3155                      AO_TMRDACWRs_In_Progress_St) == 0)
3156                         break;
3157         }
3158         if (i == timeout) {
3159                 comedi_error(dev,
3160                              "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3161                 return -EIO;
3162         }
3163         /*  stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3164         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3165                             Interrupt_B_Ack_Register);
3166
3167         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3168
3169         devpriv->stc_writew(dev,
3170                             devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3171                             | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3172                             AO_Command_1_Register);
3173
3174         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3175                             AO_Command_2_Register);
3176
3177         return 0;
3178 }
3179
3180 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3181 {
3182         const struct ni_board_struct *board = comedi_board(dev);
3183         struct ni_private *devpriv = dev->private;
3184         const struct comedi_cmd *cmd = &s->async->cmd;
3185         int bits;
3186         int i;
3187         unsigned trigvar;
3188
3189         if (dev->irq == 0) {
3190                 comedi_error(dev, "cannot run command without an irq");
3191                 return -EIO;
3192         }
3193
3194         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3195
3196         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3197
3198         if (board->reg_type & ni_reg_6xxx_mask) {
3199                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3200
3201                 bits = 0;
3202                 for (i = 0; i < cmd->chanlist_len; i++) {
3203                         int chan;
3204
3205                         chan = CR_CHAN(cmd->chanlist[i]);
3206                         bits |= 1 << chan;
3207                         ao_win_out(chan, AO_Waveform_Generation_611x);
3208                 }
3209                 ao_win_out(bits, AO_Timed_611x);
3210         }
3211
3212         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3213
3214         if (cmd->stop_src == TRIG_NONE) {
3215                 devpriv->ao_mode1 |= AO_Continuous;
3216                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3217         } else {
3218                 devpriv->ao_mode1 &= ~AO_Continuous;
3219                 devpriv->ao_mode1 |= AO_Trigger_Once;
3220         }
3221         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3222         switch (cmd->start_src) {
3223         case TRIG_INT:
3224         case TRIG_NOW:
3225                 devpriv->ao_trigger_select &=
3226                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3227                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3228                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3229                                     AO_Trigger_Select_Register);
3230                 break;
3231         case TRIG_EXT:
3232                 devpriv->ao_trigger_select =
3233                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3234                 if (cmd->start_arg & CR_INVERT)
3235                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3236                 if (cmd->start_arg & CR_EDGE)
3237                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3238                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3239                                     AO_Trigger_Select_Register);
3240                 break;
3241         default:
3242                 BUG();
3243                 break;
3244         }
3245         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3246         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3247
3248         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3249         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3250         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3251         if (cmd->stop_src == TRIG_NONE) {
3252                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3253         } else {
3254                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3255         }
3256         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3257         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3258         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3259         switch (cmd->stop_src) {
3260         case TRIG_COUNT:
3261                 if (board->reg_type & ni_reg_m_series_mask) {
3262                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3263                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3264                                             AO_UC_Load_A_Register);
3265                         devpriv->stc_writew(dev, AO_UC_Load,
3266                                             AO_Command_1_Register);
3267                 } else {
3268                         devpriv->stc_writel(dev, cmd->stop_arg,
3269                                             AO_UC_Load_A_Register);
3270                         devpriv->stc_writew(dev, AO_UC_Load,
3271                                             AO_Command_1_Register);
3272                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3273                                             AO_UC_Load_A_Register);
3274                 }
3275                 break;
3276         case TRIG_NONE:
3277                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3278                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3279                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3280                 break;
3281         default:
3282                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3283                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3284                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3285         }
3286
3287         devpriv->ao_mode1 &=
3288             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3289               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3290         switch (cmd->scan_begin_src) {
3291         case TRIG_TIMER:
3292                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3293                 trigvar =
3294                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3295                                    TRIG_ROUND_NEAREST);
3296                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3297                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3298                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3299                 break;
3300         case TRIG_EXT:
3301                 devpriv->ao_mode1 |=
3302                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3303                 if (cmd->scan_begin_arg & CR_INVERT)
3304                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3305                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3306                 break;
3307         default:
3308                 BUG();
3309                 break;
3310         }
3311         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3312         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3313         devpriv->ao_mode2 &=
3314             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3315         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3316
3317         if (cmd->scan_end_arg > 1) {
3318                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3319                 devpriv->stc_writew(dev,
3320                                     AO_Number_Of_Channels(cmd->scan_end_arg -
3321                                                           1) |
3322                                     AO_UPDATE_Output_Select
3323                                     (AO_Update_Output_High_Z),
3324                                     AO_Output_Control_Register);
3325         } else {
3326                 unsigned bits;
3327                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3328                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3329                 if (board->reg_type &
3330                     (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3331                         bits |= AO_Number_Of_Channels(0);
3332                 } else {
3333                         bits |=
3334                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3335                 }
3336                 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3337         }
3338         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3339
3340         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3341                             AO_Command_1_Register);
3342
3343         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3344         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3345
3346         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3347 #ifdef PCIDMA
3348         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3349 #else
3350         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3351 #endif
3352         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3353         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3354
3355         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3356             AO_TMRDACWR_Pulse_Width;
3357         if (board->ao_fifo_depth)
3358                 bits |= AO_FIFO_Enable;
3359         else
3360                 bits |= AO_DMA_PIO_Control;
3361 #if 0
3362         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3363            verified with bus analyzer. */
3364         if (board->reg_type & ni_reg_m_series_mask)
3365                 bits |= AO_Number_Of_DAC_Packages;
3366 #endif
3367         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3368         /*  enable sending of ao dma requests */
3369         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3370
3371         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3372
3373         if (cmd->stop_src == TRIG_COUNT) {
3374                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3375                                     Interrupt_B_Ack_Register);
3376                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3377                             AO_BC_TC_Interrupt_Enable, 1);
3378         }
3379
3380         s->async->inttrig = &ni_ao_inttrig;
3381
3382         return 0;
3383 }
3384
3385 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3386                          struct comedi_cmd *cmd)
3387 {
3388         const struct ni_board_struct *board = comedi_board(dev);
3389         struct ni_private *devpriv = dev->private;
3390         int err = 0;
3391         int tmp;
3392
3393         /* Step 1 : check if triggers are trivially valid */
3394
3395         if ((cmd->flags & CMDF_WRITE) == 0)
3396                 cmd->flags |= CMDF_WRITE;
3397
3398         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3399         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3400                                         TRIG_TIMER | TRIG_EXT);
3401         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3402         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3403         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3404
3405         if (err)
3406                 return 1;
3407
3408         /* Step 2a : make sure trigger sources are unique */
3409
3410         err |= cfc_check_trigger_is_unique(cmd->start_src);
3411         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3412         err |= cfc_check_trigger_is_unique(cmd->stop_src);
3413
3414         /* Step 2b : and mutually compatible */
3415
3416         if (err)
3417                 return 2;
3418
3419         /* Step 3: check if arguments are trivially valid */
3420
3421         if (cmd->start_src == TRIG_EXT) {
3422                 /* external trigger */
3423                 unsigned int tmp = CR_CHAN(cmd->start_arg);
3424
3425                 if (tmp > 18)
3426                         tmp = 18;
3427                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3428                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3429         } else {
3430                 /* true for both TRIG_NOW and TRIG_INT */
3431                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3432         }
3433
3434         if (cmd->scan_begin_src == TRIG_TIMER) {
3435                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3436                                                  board->ao_speed);
3437                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3438                                                  devpriv->clock_ns * 0xffffff);
3439         }
3440
3441         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3442         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3443
3444         if (cmd->stop_src == TRIG_COUNT)
3445                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3446         else    /* TRIG_NONE */
3447                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3448
3449         if (err)
3450                 return 3;
3451
3452         /* step 4: fix up any arguments */
3453         if (cmd->scan_begin_src == TRIG_TIMER) {
3454                 tmp = cmd->scan_begin_arg;
3455                 cmd->scan_begin_arg =
3456                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3457                                                        cmd->scan_begin_arg,
3458                                                        cmd->
3459                                                        flags &
3460                                                        TRIG_ROUND_MASK));
3461                 if (tmp != cmd->scan_begin_arg)
3462                         err++;
3463         }
3464         if (err)
3465                 return 4;
3466
3467         /* step 5: fix up chanlist */
3468
3469         if (err)
3470                 return 5;
3471
3472         return 0;
3473 }
3474
3475 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3476 {
3477         const struct ni_board_struct *board = comedi_board(dev);
3478         struct ni_private *devpriv = dev->private;
3479
3480         /* devpriv->ao0p=0x0000; */
3481         /* ni_writew(devpriv->ao0p,AO_Configuration); */
3482
3483         /* devpriv->ao1p=AO_Channel(1); */
3484         /* ni_writew(devpriv->ao1p,AO_Configuration); */
3485
3486         ni_release_ao_mite_channel(dev);
3487
3488         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3489         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3490         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3491         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3492         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3493         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3494                             AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3495         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3496         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3497         devpriv->ao_cmd1 = 0;
3498         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3499         devpriv->ao_cmd2 = 0;
3500         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3501         devpriv->ao_mode1 = 0;
3502         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3503         devpriv->ao_mode2 = 0;
3504         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3505         if (board->reg_type & ni_reg_m_series_mask)
3506                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3507         else
3508                 devpriv->ao_mode3 = 0;
3509         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3510         devpriv->ao_trigger_select = 0;
3511         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3512                             AO_Trigger_Select_Register);
3513         if (board->reg_type & ni_reg_6xxx_mask) {
3514                 unsigned immediate_bits = 0;
3515                 unsigned i;
3516                 for (i = 0; i < s->n_chan; ++i) {
3517                         immediate_bits |= 1 << i;
3518                 }
3519                 ao_win_out(immediate_bits, AO_Immediate_671x);
3520                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3521         }
3522         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3523
3524         return 0;
3525 }
3526
3527 /* digital io */
3528
3529 static int ni_dio_insn_config(struct comedi_device *dev,
3530                               struct comedi_subdevice *s,
3531                               struct comedi_insn *insn, unsigned int *data)
3532 {
3533         struct ni_private *devpriv = dev->private;
3534
3535 #ifdef DEBUG_DIO
3536         printk("ni_dio_insn_config() chan=%d io=%d\n",
3537                CR_CHAN(insn->chanspec), data[0]);
3538 #endif
3539         switch (data[0]) {
3540         case INSN_CONFIG_DIO_OUTPUT:
3541                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3542                 break;
3543         case INSN_CONFIG_DIO_INPUT:
3544                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3545                 break;
3546         case INSN_CONFIG_DIO_QUERY:
3547                 data[1] =
3548                     (s->
3549                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3550                     COMEDI_INPUT;
3551                 return insn->n;
3552                 break;
3553         default:
3554                 return -EINVAL;
3555         }
3556
3557         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3558         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3559         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3560
3561         return 1;
3562 }
3563
3564 static int ni_dio_insn_bits(struct comedi_device *dev,
3565                             struct comedi_subdevice *s,
3566                             struct comedi_insn *insn, unsigned int *data)
3567 {
3568         struct ni_private *devpriv = dev->private;
3569
3570 #ifdef DEBUG_DIO
3571         printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3572 #endif
3573
3574         if (data[0]) {
3575                 /* Perform check to make sure we're not using the
3576                    serial part of the dio */
3577                 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3578                     && devpriv->serial_interval_ns)
3579                         return -EBUSY;
3580
3581                 s->state &= ~data[0];
3582                 s->state |= (data[0] & data[1]);
3583                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3584                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3585                 devpriv->stc_writew(dev, devpriv->dio_output,
3586                                     DIO_Output_Register);
3587         }
3588         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3589
3590         return insn->n;
3591 }
3592
3593 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3594                                        struct comedi_subdevice *s,
3595                                        struct comedi_insn *insn,
3596                                        unsigned int *data)
3597 {
3598         struct ni_private *devpriv __maybe_unused = dev->private;
3599
3600 #ifdef DEBUG_DIO
3601         printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3602                CR_CHAN(insn->chanspec), data[0]);
3603 #endif
3604         switch (data[0]) {
3605         case INSN_CONFIG_DIO_OUTPUT:
3606                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3607                 break;
3608         case INSN_CONFIG_DIO_INPUT:
3609                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3610                 break;
3611         case INSN_CONFIG_DIO_QUERY:
3612                 data[1] =
3613                     (s->
3614                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3615                     COMEDI_INPUT;
3616                 return insn->n;
3617                 break;
3618         default:
3619                 return -EINVAL;
3620         }
3621
3622         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3623
3624         return 1;
3625 }
3626
3627 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3628                                      struct comedi_subdevice *s,
3629                                      struct comedi_insn *insn,
3630                                      unsigned int *data)
3631 {
3632         struct ni_private *devpriv __maybe_unused = dev->private;
3633
3634 #ifdef DEBUG_DIO
3635         printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3636                data[1]);
3637 #endif
3638
3639         if (data[0]) {
3640                 s->state &= ~data[0];
3641                 s->state |= (data[0] & data[1]);
3642                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3643         }
3644         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3645
3646         return insn->n;
3647 }
3648
3649 static int ni_cdio_cmdtest(struct comedi_device *dev,
3650                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3651 {
3652         int err = 0;
3653         int tmp;
3654         unsigned i;
3655
3656         /* Step 1 : check if triggers are trivially valid */
3657
3658         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3659         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3660         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3661         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3662         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3663
3664         if (err)
3665                 return 1;
3666
3667         /* Step 2a : make sure trigger sources are unique */
3668         /* Step 2b : and mutually compatible */
3669
3670         if (err)
3671                 return 2;
3672
3673         /* Step 3: check if arguments are trivially valid */
3674
3675         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3676
3677         tmp = cmd->scan_begin_arg;
3678         tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3679         if (tmp != cmd->scan_begin_arg)
3680                 err |= -EINVAL;
3681
3682         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3683         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3684         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3685
3686         if (err)
3687                 return 3;
3688
3689         /* step 4: fix up any arguments */
3690
3691         if (err)
3692                 return 4;
3693
3694         /* step 5: check chanlist */
3695
3696         for (i = 0; i < cmd->chanlist_len; ++i) {
3697                 if (cmd->chanlist[i] != i)
3698                         err = 1;
3699         }
3700
3701         if (err)
3702                 return 5;
3703
3704         return 0;
3705 }
3706
3707 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3708 {
3709         struct ni_private *devpriv __maybe_unused = dev->private;
3710         const struct comedi_cmd *cmd = &s->async->cmd;
3711         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3712         int retval;
3713
3714         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3715         switch (cmd->scan_begin_src) {
3716         case TRIG_EXT:
3717                 cdo_mode_bits |=
3718                     CR_CHAN(cmd->scan_begin_arg) &
3719                     CDO_Sample_Source_Select_Mask;
3720                 break;
3721         default:
3722                 BUG();
3723                 break;
3724         }
3725         if (cmd->scan_begin_arg & CR_INVERT)
3726                 cdo_mode_bits |= CDO_Polarity_Bit;
3727         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3728         if (s->io_bits) {
3729                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3730                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3731                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3732         } else {
3733                 comedi_error(dev,
3734                              "attempted to run digital output command with no lines configured as outputs");
3735                 return -EIO;
3736         }
3737         retval = ni_request_cdo_mite_channel(dev);
3738         if (retval < 0) {
3739                 return retval;
3740         }
3741         s->async->inttrig = &ni_cdo_inttrig;
3742         return 0;
3743 }
3744
3745 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3746                           unsigned int trignum)
3747 {
3748 #ifdef PCIDMA
3749         struct ni_private *devpriv = dev->private;
3750         unsigned long flags;
3751 #endif
3752         int retval = 0;
3753         unsigned i;
3754         const unsigned timeout = 1000;
3755
3756         s->async->inttrig = NULL;
3757
3758         /* read alloc the entire buffer */
3759         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3760
3761 #ifdef PCIDMA
3762         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3763         if (devpriv->cdo_mite_chan) {
3764                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3765                 mite_dma_arm(devpriv->cdo_mite_chan);
3766         } else {
3767                 comedi_error(dev, "BUG: no cdo mite channel?");
3768                 retval = -EIO;
3769         }
3770         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3771         if (retval < 0)
3772                 return retval;
3773 #endif
3774 /*
3775 * XXX not sure what interrupt C group does
3776 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3777 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3778 */
3779         for (i = 0; i < timeout; ++i) {
3780                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3781                         break;
3782                 udelay(10);
3783         }
3784         if (i == timeout) {
3785                 comedi_error(dev, "dma failed to fill cdo fifo!");
3786                 ni_cdio_cancel(dev, s);
3787                 return -EIO;
3788         }
3789         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3790                   CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3791                   M_Offset_CDIO_Command);
3792         return retval;
3793 }
3794
3795 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3796 {
3797         struct ni_private *devpriv __maybe_unused = dev->private;
3798
3799         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3800                   CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3801                   CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3802                   M_Offset_CDIO_Command);
3803 /*
3804 * XXX not sure what interrupt C group does ni_writeb(0,
3805 * M_Offset_Interrupt_C_Enable);
3806 */
3807         ni_writel(0, M_Offset_CDO_Mask_Enable);
3808         ni_release_cdo_mite_channel(dev);
3809         return 0;
3810 }
3811
3812 static void handle_cdio_interrupt(struct comedi_device *dev)
3813 {
3814         const struct ni_board_struct *board = comedi_board(dev);
3815         struct ni_private *devpriv __maybe_unused = dev->private;
3816         unsigned cdio_status;
3817         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3818 #ifdef PCIDMA
3819         unsigned long flags;
3820 #endif
3821
3822         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3823                 return;
3824         }
3825 #ifdef PCIDMA
3826         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3827         if (devpriv->cdo_mite_chan) {
3828                 unsigned cdo_mite_status =
3829                     mite_get_status(devpriv->cdo_mite_chan);
3830                 if (cdo_mite_status & CHSR_LINKC) {
3831                         writel(CHOR_CLRLC,
3832                                devpriv->mite->mite_io_addr +
3833                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3834                 }
3835                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3836         }
3837         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3838 #endif
3839
3840         cdio_status = ni_readl(M_Offset_CDIO_Status);
3841         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3842 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3843                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      /*  XXX just guessing this is needed and does something useful */
3844                 s->async->events |= COMEDI_CB_OVERFLOW;
3845         }
3846         if (cdio_status & CDO_FIFO_Empty_Bit) {
3847 /* printk("cdio fifo empty\n"); */
3848                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3849                           M_Offset_CDIO_Command);
3850 /* s->async->events |= COMEDI_CB_EOA; */
3851         }
3852         ni_event(dev, s);
3853 }
3854
3855 static int ni_serial_insn_config(struct comedi_device *dev,
3856                                  struct comedi_subdevice *s,
3857                                  struct comedi_insn *insn, unsigned int *data)
3858 {
3859         struct ni_private *devpriv = dev->private;
3860         int err = insn->n;
3861         unsigned char byte_out, byte_in = 0;
3862
3863         if (insn->n != 2)
3864                 return -EINVAL;
3865
3866         switch (data[0]) {
3867         case INSN_CONFIG_SERIAL_CLOCK:
3868
3869 #ifdef DEBUG_DIO
3870                 printk("SPI serial clock Config cd\n", data[1]);
3871 #endif
3872                 devpriv->serial_hw_mode = 1;
3873                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3874
3875                 if (data[1] == SERIAL_DISABLED) {
3876                         devpriv->serial_hw_mode = 0;
3877                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3878                                                   DIO_Software_Serial_Control);
3879                         data[1] = SERIAL_DISABLED;
3880                         devpriv->serial_interval_ns = data[1];
3881                 } else if (data[1] <= SERIAL_600NS) {
3882                         /* Warning: this clock speed is too fast to reliably
3883                            control SCXI. */
3884                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3885                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3886                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3887                         data[1] = SERIAL_600NS;
3888                         devpriv->serial_interval_ns = data[1];
3889                 } else if (data[1] <= SERIAL_1_2US) {
3890                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3891                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3892                             DIO_Serial_Out_Divide_By_2;
3893                         data[1] = SERIAL_1_2US;
3894                         devpriv->serial_interval_ns = data[1];
3895                 } else if (data[1] <= SERIAL_10US) {
3896                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3897                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3898                             DIO_Serial_Out_Divide_By_2;
3899                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3900                            600ns/1.2us. If you turn divide_by_2 off with the
3901                            slow clock, you will still get 10us, except then
3902                            all your delays are wrong. */
3903                         data[1] = SERIAL_10US;
3904                         devpriv->serial_interval_ns = data[1];
3905                 } else {
3906                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3907                                                   DIO_Software_Serial_Control);
3908                         devpriv->serial_hw_mode = 0;
3909                         data[1] = (data[1] / 1000) * 1000;
3910                         devpriv->serial_interval_ns = data[1];
3911                 }
3912
3913                 devpriv->stc_writew(dev, devpriv->dio_control,
3914                                     DIO_Control_Register);
3915                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3916                                     Clock_and_FOUT_Register);
3917                 return 1;
3918
3919                 break;
3920
3921         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3922
3923                 if (devpriv->serial_interval_ns == 0) {
3924                         return -EINVAL;
3925                 }
3926
3927                 byte_out = data[1] & 0xFF;
3928
3929                 if (devpriv->serial_hw_mode) {
3930                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3931                                                       &byte_in);
3932                 } else if (devpriv->serial_interval_ns > 0) {
3933                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3934                                                       &byte_in);
3935                 } else {
3936                         printk("ni_serial_insn_config: serial disabled!\n");
3937                         return -EINVAL;
3938                 }
3939                 if (err < 0)
3940                         return err;
3941                 data[1] = byte_in & 0xFF;
3942                 return insn->n;
3943
3944                 break;
3945         default:
3946                 return -EINVAL;
3947         }
3948
3949 }
3950
3951 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3952                                    struct comedi_subdevice *s,
3953                                    unsigned char data_out,
3954                                    unsigned char *data_in)
3955 {
3956         struct ni_private *devpriv = dev->private;
3957         unsigned int status1;
3958         int err = 0, count = 20;
3959
3960 #ifdef DEBUG_DIO
3961         printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3962 #endif
3963
3964         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3965         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3966         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3967
3968         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3969         if (status1 & DIO_Serial_IO_In_Progress_St) {
3970                 err = -EBUSY;
3971                 goto Error;
3972         }
3973
3974         devpriv->dio_control |= DIO_HW_Serial_Start;
3975         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3976         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3977
3978         /* Wait until STC says we're done, but don't loop infinitely. */
3979         while ((status1 =
3980                 devpriv->stc_readw(dev,
3981                                    Joint_Status_1_Register)) &
3982                DIO_Serial_IO_In_Progress_St) {
3983                 /* Delay one bit per loop */
3984                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3985                 if (--count < 0) {
3986                         printk
3987                             ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3988                         err = -ETIME;
3989                         goto Error;
3990                 }
3991         }
3992
3993         /* Delay for last bit. This delay is absolutely necessary, because
3994            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3995         udelay((devpriv->serial_interval_ns + 999) / 1000);
3996
3997         if (data_in != NULL) {
3998                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3999 #ifdef DEBUG_DIO
4000                 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4001 #endif
4002         }
4003
4004 Error:
4005         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4006
4007         return err;
4008 }
4009
4010 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4011                                    struct comedi_subdevice *s,
4012                                    unsigned char data_out,
4013                                    unsigned char *data_in)
4014 {
4015         struct ni_private *devpriv = dev->private;
4016         unsigned char mask, input = 0;
4017
4018 #ifdef DEBUG_DIO
4019         printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4020 #endif
4021
4022         /* Wait for one bit before transfer */
4023         udelay((devpriv->serial_interval_ns + 999) / 1000);
4024
4025         for (mask = 0x80; mask; mask >>= 1) {
4026                 /* Output current bit; note that we cannot touch s->state
4027                    because it is a per-subdevice field, and serial is
4028                    a separate subdevice from DIO. */
4029                 devpriv->dio_output &= ~DIO_SDOUT;
4030                 if (data_out & mask) {
4031                         devpriv->dio_output |= DIO_SDOUT;
4032                 }
4033                 devpriv->stc_writew(dev, devpriv->dio_output,
4034                                     DIO_Output_Register);
4035
4036                 /* Assert SDCLK (active low, inverted), wait for half of
4037                    the delay, deassert SDCLK, and wait for the other half. */
4038                 devpriv->dio_control |= DIO_Software_Serial_Control;
4039                 devpriv->stc_writew(dev, devpriv->dio_control,
4040                                     DIO_Control_Register);
4041
4042                 udelay((devpriv->serial_interval_ns + 999) / 2000);
4043
4044                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4045                 devpriv->stc_writew(dev, devpriv->dio_control,
4046                                     DIO_Control_Register);
4047
4048                 udelay((devpriv->serial_interval_ns + 999) / 2000);
4049
4050                 /* Input current bit */
4051                 if (devpriv->stc_readw(dev,
4052                                        DIO_Parallel_Input_Register) & DIO_SDIN)
4053                 {
4054 /*                      printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4055                         input |= mask;
4056                 }
4057         }
4058 #ifdef DEBUG_DIO
4059         printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4060 #endif
4061         if (data_in)
4062                 *data_in = input;
4063
4064         return 0;
4065 }
4066
4067 static void mio_common_detach(struct comedi_device *dev)
4068 {
4069         struct ni_private *devpriv = dev->private;
4070
4071         if (devpriv) {
4072                 if (devpriv->counter_dev) {
4073                         ni_gpct_device_destroy(devpriv->counter_dev);
4074                 }
4075         }
4076 }
4077
4078 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4079 {
4080         int i;
4081
4082         for (i = 0; i < s->n_chan; i++) {
4083                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4084                                AO_Configuration_2_67xx);
4085         }
4086         ao_win_out(0x0, AO_Later_Single_Point_Updates);
4087 }
4088
4089 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4090 {
4091         unsigned stc_register;
4092         switch (reg) {
4093         case NITIO_G0_Autoincrement_Reg:
4094                 stc_register = G_Autoincrement_Register(0);
4095                 break;
4096         case NITIO_G1_Autoincrement_Reg:
4097                 stc_register = G_Autoincrement_Register(1);
4098                 break;
4099         case NITIO_G0_Command_Reg:
4100                 stc_register = G_Command_Register(0);
4101                 break;
4102         case NITIO_G1_Command_Reg:
4103                 stc_register = G_Command_Register(1);
4104                 break;
4105         case NITIO_G0_HW_Save_Reg:
4106                 stc_register = G_HW_Save_Register(0);
4107                 break;
4108         case NITIO_G1_HW_Save_Reg:
4109                 stc_register = G_HW_Save_Register(1);
4110                 break;
4111         case NITIO_G0_SW_Save_Reg:
4112                 stc_register = G_Save_Register(0);
4113                 break;
4114         case NITIO_G1_SW_Save_Reg:
4115                 stc_register = G_Save_Register(1);
4116                 break;
4117         case NITIO_G0_Mode_Reg:
4118                 stc_register = G_Mode_Register(0);
4119                 break;
4120         case NITIO_G1_Mode_Reg:
4121                 stc_register = G_Mode_Register(1);
4122                 break;
4123         case NITIO_G0_LoadA_Reg:
4124                 stc_register = G_Load_A_Register(0);
4125                 break;
4126         case NITIO_G1_LoadA_Reg:
4127                 stc_register = G_Load_A_Register(1);
4128                 break;
4129         case NITIO_G0_LoadB_Reg:
4130                 stc_register = G_Load_B_Register(0);
4131                 break;
4132         case NITIO_G1_LoadB_Reg:
4133                 stc_register = G_Load_B_Register(1);
4134                 break;
4135         case NITIO_G0_Input_Select_Reg:
4136                 stc_register = G_Input_Select_Register(0);
4137                 break;
4138         case NITIO_G1_Input_Select_Reg:
4139                 stc_register = G_Input_Select_Register(1);
4140                 break;
4141         case NITIO_G01_Status_Reg:
4142                 stc_register = G_Status_Register;
4143                 break;
4144         case NITIO_G01_Joint_Reset_Reg:
4145                 stc_register = Joint_Reset_Register;
4146                 break;
4147         case NITIO_G01_Joint_Status1_Reg:
4148                 stc_register = Joint_Status_1_Register;
4149                 break;
4150         case NITIO_G01_Joint_Status2_Reg:
4151                 stc_register = Joint_Status_2_Register;
4152                 break;
4153         case NITIO_G0_Interrupt_Acknowledge_Reg:
4154                 stc_register = Interrupt_A_Ack_Register;
4155                 break;
4156         case NITIO_G1_Interrupt_Acknowledge_Reg:
4157                 stc_register = Interrupt_B_Ack_Register;
4158                 break;
4159         case NITIO_G0_Status_Reg:
4160                 stc_register = AI_Status_1_Register;
4161                 break;
4162         case NITIO_G1_Status_Reg:
4163                 stc_register = AO_Status_1_Register;
4164                 break;
4165         case NITIO_G0_Interrupt_Enable_Reg:
4166                 stc_register = Interrupt_A_Enable_Register;
4167                 break;
4168         case NITIO_G1_Interrupt_Enable_Reg:
4169                 stc_register = Interrupt_B_Enable_Register;
4170                 break;
4171         default:
4172                 printk("%s: unhandled register 0x%x in switch.\n",
4173                        __func__, reg);
4174                 BUG();
4175                 return 0;
4176                 break;
4177         }
4178         return stc_register;
4179 }
4180
4181 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4182                                    enum ni_gpct_register reg)
4183 {
4184         struct comedi_device *dev = counter->counter_dev->dev;
4185         struct ni_private *devpriv = dev->private;
4186         unsigned stc_register;
4187         /* bits in the join reset register which are relevant to counters */
4188         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4189         static const unsigned gpct_interrupt_a_enable_mask =
4190             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4191         static const unsigned gpct_interrupt_b_enable_mask =
4192             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4193
4194         switch (reg) {
4195                 /* m-series-only registers */
4196         case NITIO_G0_Counting_Mode_Reg:
4197                 ni_writew(bits, M_Offset_G0_Counting_Mode);
4198                 break;
4199         case NITIO_G1_Counting_Mode_Reg:
4200                 ni_writew(bits, M_Offset_G1_Counting_Mode);
4201                 break;
4202         case NITIO_G0_Second_Gate_Reg:
4203                 ni_writew(bits, M_Offset_G0_Second_Gate);
4204                 break;
4205         case NITIO_G1_Second_Gate_Reg:
4206                 ni_writew(bits, M_Offset_G1_Second_Gate);
4207                 break;
4208         case NITIO_G0_DMA_Config_Reg:
4209                 ni_writew(bits, M_Offset_G0_DMA_Config);
4210                 break;
4211         case NITIO_G1_DMA_Config_Reg:
4212                 ni_writew(bits, M_Offset_G1_DMA_Config);
4213                 break;
4214         case NITIO_G0_ABZ_Reg:
4215                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4216                 break;
4217         case NITIO_G1_ABZ_Reg:
4218                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4219                 break;
4220
4221                 /* 32 bit registers */
4222         case NITIO_G0_LoadA_Reg:
4223         case NITIO_G1_LoadA_Reg:
4224         case NITIO_G0_LoadB_Reg:
4225         case NITIO_G1_LoadB_Reg:
4226                 stc_register = ni_gpct_to_stc_register(reg);
4227                 devpriv->stc_writel(dev, bits, stc_register);
4228                 break;
4229
4230                 /* 16 bit registers */
4231         case NITIO_G0_Interrupt_Enable_Reg:
4232                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4233                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4234                                 gpct_interrupt_a_enable_mask, bits);
4235                 break;
4236         case NITIO_G1_Interrupt_Enable_Reg:
4237                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4238                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4239                                 gpct_interrupt_b_enable_mask, bits);
4240                 break;
4241         case NITIO_G01_Joint_Reset_Reg:
4242                 BUG_ON(bits & ~gpct_joint_reset_mask);
4243                 /* fall-through */
4244         default:
4245                 stc_register = ni_gpct_to_stc_register(reg);
4246                 devpriv->stc_writew(dev, bits, stc_register);
4247         }
4248 }
4249
4250 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4251                                       enum ni_gpct_register reg)
4252 {
4253         struct comedi_device *dev = counter->counter_dev->dev;
4254         struct ni_private *devpriv = dev->private;
4255         unsigned stc_register;
4256
4257         switch (reg) {
4258                 /* m-series only registers */
4259         case NITIO_G0_DMA_Status_Reg:
4260                 return ni_readw(M_Offset_G0_DMA_Status);
4261                 break;
4262         case NITIO_G1_DMA_Status_Reg:
4263                 return ni_readw(M_Offset_G1_DMA_Status);
4264                 break;
4265
4266                 /* 32 bit registers */
4267         case NITIO_G0_HW_Save_Reg:
4268         case NITIO_G1_HW_Save_Reg:
4269         case NITIO_G0_SW_Save_Reg:
4270         case NITIO_G1_SW_Save_Reg:
4271                 stc_register = ni_gpct_to_stc_register(reg);
4272                 return devpriv->stc_readl(dev, stc_register);
4273                 break;
4274
4275                 /* 16 bit registers */
4276         default:
4277                 stc_register = ni_gpct_to_stc_register(reg);
4278                 return devpriv->stc_readw(dev, stc_register);
4279                 break;
4280         }
4281         return 0;
4282 }
4283
4284 static int ni_freq_out_insn_read(struct comedi_device *dev,
4285                                  struct comedi_subdevice *s,
4286                                  struct comedi_insn *insn, unsigned int *data)
4287 {
4288         struct ni_private *devpriv = dev->private;
4289
4290         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4291         return 1;
4292 }
4293
4294 static int ni_freq_out_insn_write(struct comedi_device *dev,
4295                                   struct comedi_subdevice *s,
4296                                   struct comedi_insn *insn, unsigned int *data)
4297 {
4298         struct ni_private *devpriv = dev->private;
4299
4300         devpriv->clock_and_fout &= ~FOUT_Enable;
4301         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4302                             Clock_and_FOUT_Register);
4303         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4304         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4305         devpriv->clock_and_fout |= FOUT_Enable;
4306         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4307                             Clock_and_FOUT_Register);
4308         return insn->n;
4309 }
4310
4311 static int ni_set_freq_out_clock(struct comedi_device *dev,
4312                                  unsigned int clock_source)
4313 {
4314         struct ni_private *devpriv = dev->private;
4315
4316         switch (clock_source) {
4317         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4318                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4319                 break;
4320         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4321                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4322                 break;
4323         default:
4324                 return -EINVAL;
4325         }
4326         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4327                             Clock_and_FOUT_Register);
4328         return 3;
4329 }
4330
4331 static void ni_get_freq_out_clock(struct comedi_device *dev,
4332                                   unsigned int *clock_source,
4333                                   unsigned int *clock_period_ns)
4334 {
4335         struct ni_private *devpriv = dev->private;
4336
4337         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4338                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4339                 *clock_period_ns = TIMEBASE_2_NS;
4340         } else {
4341                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4342                 *clock_period_ns = TIMEBASE_1_NS * 2;
4343         }
4344 }
4345
4346 static int ni_freq_out_insn_config(struct comedi_device *dev,
4347                                    struct comedi_subdevice *s,
4348                                    struct comedi_insn *insn, unsigned int *data)
4349 {
4350         switch (data[0]) {
4351         case INSN_CONFIG_SET_CLOCK_SRC:
4352                 return ni_set_freq_out_clock(dev, data[1]);
4353                 break;
4354         case INSN_CONFIG_GET_CLOCK_SRC:
4355                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4356                 return 3;
4357         default:
4358                 break;
4359         }
4360         return -EINVAL;
4361 }
4362
4363 static int ni_alloc_private(struct comedi_device *dev)
4364 {
4365         struct ni_private *devpriv;
4366
4367         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
4368         if (!devpriv)
4369                 return -ENOMEM;
4370
4371         spin_lock_init(&devpriv->window_lock);
4372         spin_lock_init(&devpriv->soft_reg_copy_lock);
4373         spin_lock_init(&devpriv->mite_channel_lock);
4374
4375         return 0;
4376 };
4377
4378 static int ni_E_init(struct comedi_device *dev)
4379 {
4380         const struct ni_board_struct *board = comedi_board(dev);
4381         struct ni_private *devpriv = dev->private;
4382         struct comedi_subdevice *s;
4383         unsigned j;
4384         enum ni_gpct_variant counter_variant;
4385         int ret;
4386
4387         if (board->n_aochan > MAX_N_AO_CHAN) {
4388                 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4389                 return -EINVAL;
4390         }
4391
4392         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4393         if (ret)
4394                 return ret;
4395
4396         /* analog input subdevice */
4397
4398         s = &dev->subdevices[NI_AI_SUBDEV];
4399         dev->read_subdev = s;
4400         if (board->n_adchan) {
4401                 s->type = COMEDI_SUBD_AI;
4402                 s->subdev_flags =
4403                     SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4404                 if (board->reg_type != ni_reg_611x)
4405                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4406                 if (board->adbits > 16)
4407                         s->subdev_flags |= SDF_LSAMPL;
4408                 if (board->reg_type & ni_reg_m_series_mask)
4409                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4410                 s->n_chan = board->n_adchan;
4411                 s->len_chanlist = 512;
4412                 s->maxdata = (1 << board->adbits) - 1;
4413                 s->range_table = ni_range_lkup[board->gainlkup];
4414                 s->insn_read = &ni_ai_insn_read;
4415                 s->insn_config = &ni_ai_insn_config;
4416                 s->do_cmdtest = &ni_ai_cmdtest;
4417                 s->do_cmd = &ni_ai_cmd;
4418                 s->cancel = &ni_ai_reset;
4419                 s->poll = &ni_ai_poll;
4420                 s->munge = &ni_ai_munge;
4421 #ifdef PCIDMA
4422                 s->async_dma_dir = DMA_FROM_DEVICE;
4423 #endif
4424         } else {
4425                 s->type = COMEDI_SUBD_UNUSED;
4426         }
4427
4428         /* analog output subdevice */
4429
4430         s = &dev->subdevices[NI_AO_SUBDEV];
4431         if (board->n_aochan) {
4432                 s->type = COMEDI_SUBD_AO;
4433                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4434                 if (board->reg_type & ni_reg_m_series_mask)
4435                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4436                 s->n_chan = board->n_aochan;
4437                 s->maxdata = (1 << board->aobits) - 1;
4438                 s->range_table = board->ao_range_table;
4439                 s->insn_read = &ni_ao_insn_read;
4440                 if (board->reg_type & ni_reg_6xxx_mask) {
4441                         s->insn_write = &ni_ao_insn_write_671x;
4442                 } else {
4443                         s->insn_write = &ni_ao_insn_write;
4444                 }
4445                 s->insn_config = &ni_ao_insn_config;
4446 #ifdef PCIDMA
4447                 if (board->n_aochan) {
4448                         s->async_dma_dir = DMA_TO_DEVICE;
4449 #else
4450                 if (board->ao_fifo_depth) {
4451 #endif
4452                         dev->write_subdev = s;
4453                         s->subdev_flags |= SDF_CMD_WRITE;
4454                         s->do_cmd = &ni_ao_cmd;
4455                         s->do_cmdtest = &ni_ao_cmdtest;
4456                         s->len_chanlist = board->n_aochan;
4457                         if ((board->reg_type & ni_reg_m_series_mask) == 0)
4458                                 s->munge = ni_ao_munge;
4459                 }
4460                 s->cancel = &ni_ao_reset;
4461         } else {
4462                 s->type = COMEDI_SUBD_UNUSED;
4463         }
4464         if ((board->reg_type & ni_reg_67xx_mask))
4465                 init_ao_67xx(dev, s);
4466
4467         /* digital i/o subdevice */
4468
4469         s = &dev->subdevices[NI_DIO_SUBDEV];
4470         s->type = COMEDI_SUBD_DIO;
4471         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4472         s->maxdata = 1;
4473         s->io_bits = 0;         /* all bits input */
4474         s->range_table = &range_digital;
4475         s->n_chan = board->num_p0_dio_channels;
4476         if (board->reg_type & ni_reg_m_series_mask) {
4477                 s->subdev_flags |=
4478                     SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4479                 s->insn_bits = &ni_m_series_dio_insn_bits;
4480                 s->insn_config = &ni_m_series_dio_insn_config;
4481                 s->do_cmd = &ni_cdio_cmd;
4482                 s->do_cmdtest = &ni_cdio_cmdtest;
4483                 s->cancel = &ni_cdio_cancel;
4484                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4485                 s->len_chanlist = s->n_chan;
4486
4487                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4488                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4489         } else {
4490                 s->insn_bits = &ni_dio_insn_bits;
4491                 s->insn_config = &ni_dio_insn_config;
4492                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4493                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4494         }
4495
4496         /* 8255 device */
4497         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4498         if (board->has_8255) {
4499                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4500         } else {
4501                 s->type = COMEDI_SUBD_UNUSED;
4502         }
4503
4504         /* formerly general purpose counter/timer device, but no longer used */
4505         s = &dev->subdevices[NI_UNUSED_SUBDEV];
4506         s->type = COMEDI_SUBD_UNUSED;
4507
4508         /* calibration subdevice -- ai and ao */
4509         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4510         s->type = COMEDI_SUBD_CALIB;
4511         if (board->reg_type & ni_reg_m_series_mask) {
4512                 /*  internal PWM analog output used for AI nonlinearity calibration */
4513                 s->subdev_flags = SDF_INTERNAL;
4514                 s->insn_config = &ni_m_series_pwm_config;
4515                 s->n_chan = 1;
4516                 s->maxdata = 0;
4517                 ni_writel(0x0, M_Offset_Cal_PWM);
4518         } else if (board->reg_type == ni_reg_6143) {
4519                 /*  internal PWM analog output used for AI nonlinearity calibration */
4520                 s->subdev_flags = SDF_INTERNAL;
4521                 s->insn_config = &ni_6143_pwm_config;
4522                 s->n_chan = 1;
4523                 s->maxdata = 0;
4524         } else {
4525                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4526                 s->insn_read = &ni_calib_insn_read;
4527                 s->insn_write = &ni_calib_insn_write;
4528                 caldac_setup(dev, s);
4529         }
4530
4531         /* EEPROM */
4532         s = &dev->subdevices[NI_EEPROM_SUBDEV];
4533         s->type = COMEDI_SUBD_MEMORY;
4534         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4535         s->maxdata = 0xff;
4536         if (board->reg_type & ni_reg_m_series_mask) {
4537                 s->n_chan = M_SERIES_EEPROM_SIZE;
4538                 s->insn_read = &ni_m_series_eeprom_insn_read;
4539         } else {
4540                 s->n_chan = 512;
4541                 s->insn_read = &ni_eeprom_insn_read;
4542         }
4543
4544         /* PFI */
4545         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4546         s->type = COMEDI_SUBD_DIO;
4547         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4548         if (board->reg_type & ni_reg_m_series_mask) {
4549                 unsigned i;
4550                 s->n_chan = 16;
4551                 ni_writew(s->state, M_Offset_PFI_DO);
4552                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4553                         ni_writew(devpriv->pfi_output_select_reg[i],
4554                                   M_Offset_PFI_Output_Select(i + 1));
4555                 }
4556         } else {
4557                 s->n_chan = 10;
4558         }
4559         s->maxdata = 1;
4560         if (board->reg_type & ni_reg_m_series_mask) {
4561                 s->insn_bits = &ni_pfi_insn_bits;
4562         }
4563         s->insn_config = &ni_pfi_insn_config;
4564         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4565
4566         /* cs5529 calibration adc */
4567         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4568         if (board->reg_type & ni_reg_67xx_mask) {
4569                 s->type = COMEDI_SUBD_AI;
4570                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4571                 /*  one channel for each analog output channel */
4572                 s->n_chan = board->n_aochan;
4573                 s->maxdata = (1 << 16) - 1;
4574                 s->range_table = &range_unknown;        /* XXX */
4575                 s->insn_read = cs5529_ai_insn_read;
4576                 s->insn_config = NULL;
4577                 init_cs5529(dev);
4578         } else {
4579                 s->type = COMEDI_SUBD_UNUSED;
4580         }
4581
4582         /* Serial */
4583         s = &dev->subdevices[NI_SERIAL_SUBDEV];
4584         s->type = COMEDI_SUBD_SERIAL;
4585         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4586         s->n_chan = 1;
4587         s->maxdata = 0xff;
4588         s->insn_config = ni_serial_insn_config;
4589         devpriv->serial_interval_ns = 0;
4590         devpriv->serial_hw_mode = 0;
4591
4592         /* RTSI */
4593         s = &dev->subdevices[NI_RTSI_SUBDEV];
4594         s->type = COMEDI_SUBD_DIO;
4595         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4596         s->n_chan = 8;
4597         s->maxdata = 1;
4598         s->insn_bits = ni_rtsi_insn_bits;
4599         s->insn_config = ni_rtsi_insn_config;
4600         ni_rtsi_init(dev);
4601
4602         if (board->reg_type & ni_reg_m_series_mask) {
4603                 counter_variant = ni_gpct_variant_m_series;
4604         } else {
4605                 counter_variant = ni_gpct_variant_e_series;
4606         }
4607         devpriv->counter_dev = ni_gpct_device_construct(dev,
4608                                                         &ni_gpct_write_register,
4609                                                         &ni_gpct_read_register,
4610                                                         counter_variant,
4611                                                         NUM_GPCT);
4612         /* General purpose counters */
4613         for (j = 0; j < NUM_GPCT; ++j) {
4614                 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4615                 s->type = COMEDI_SUBD_COUNTER;
4616                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4617                 s->n_chan = 3;
4618                 if (board->reg_type & ni_reg_m_series_mask)
4619                         s->maxdata = 0xffffffff;
4620                 else
4621                         s->maxdata = 0xffffff;
4622                 s->insn_read = &ni_gpct_insn_read;
4623                 s->insn_write = &ni_gpct_insn_write;
4624                 s->insn_config = &ni_gpct_insn_config;
4625 #ifdef PCIDMA
4626                 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4627                 s->do_cmd = &ni_gpct_cmd;
4628                 s->len_chanlist = 1;
4629                 s->do_cmdtest = &ni_gpct_cmdtest;
4630                 s->cancel = &ni_gpct_cancel;
4631                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4632 #endif
4633                 s->private = &devpriv->counter_dev->counters[j];
4634
4635                 devpriv->counter_dev->counters[j].chip_index = 0;
4636                 devpriv->counter_dev->counters[j].counter_index = j;
4637                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4638         }
4639
4640         /* Frequency output */
4641         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4642         s->type = COMEDI_SUBD_COUNTER;
4643         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4644         s->n_chan = 1;
4645         s->maxdata = 0xf;
4646         s->insn_read = &ni_freq_out_insn_read;
4647         s->insn_write = &ni_freq_out_insn_write;
4648         s->insn_config = &ni_freq_out_insn_config;
4649
4650         /* ai configuration */
4651         s = &dev->subdevices[NI_AI_SUBDEV];
4652         ni_ai_reset(dev, s);
4653         if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4654                 /*  BEAM is this needed for PCI-6143 ?? */
4655                 devpriv->clock_and_fout =
4656                     Slow_Internal_Time_Divide_By_2 |
4657                     Slow_Internal_Timebase |
4658                     Clock_To_Board_Divide_By_2 |
4659                     Clock_To_Board |
4660                     AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4661         } else {
4662                 devpriv->clock_and_fout =
4663                     Slow_Internal_Time_Divide_By_2 |
4664                     Slow_Internal_Timebase |
4665                     Clock_To_Board_Divide_By_2 | Clock_To_Board;
4666         }
4667         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4668                             Clock_and_FOUT_Register);
4669
4670         /* analog output configuration */
4671         s = &dev->subdevices[NI_AO_SUBDEV];
4672         ni_ao_reset(dev, s);
4673
4674         if (dev->irq) {
4675                 devpriv->stc_writew(dev,
4676                                     (IRQ_POLARITY ? Interrupt_Output_Polarity :
4677                                      0) | (Interrupt_Output_On_3_Pins & 0) |
4678                                     Interrupt_A_Enable | Interrupt_B_Enable |
4679                                     Interrupt_A_Output_Select(interrupt_pin
4680                                                               (dev->irq)) |
4681                                     Interrupt_B_Output_Select(interrupt_pin
4682                                                               (dev->irq)),
4683                                     Interrupt_Control_Register);
4684         }
4685
4686         /* DMA setup */
4687         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4688         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4689
4690         if (board->reg_type & ni_reg_6xxx_mask) {
4691                 ni_writeb(0, Magic_611x);
4692         } else if (board->reg_type & ni_reg_m_series_mask) {
4693                 int channel;
4694                 for (channel = 0; channel < board->n_aochan; ++channel) {
4695                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4696                         ni_writeb(0x0,
4697                                   M_Offset_AO_Reference_Attenuation(channel));
4698                 }
4699                 ni_writeb(0x0, M_Offset_AO_Calibration);
4700         }
4701
4702         printk("\n");
4703         return 0;
4704 }
4705
4706 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4707 {
4708         struct comedi_device *dev = (struct comedi_device *)arg;
4709         struct ni_private *devpriv __maybe_unused = dev->private;
4710
4711         if (dir) {
4712                 ni_writeb(data, Port_A + 2 * port);
4713                 return 0;
4714         } else {
4715                 return ni_readb(Port_A + 2 * port);
4716         }
4717 }
4718
4719 /*
4720         presents the EEPROM as a subdevice
4721 */
4722
4723 static int ni_eeprom_insn_read(struct comedi_device *dev,
4724                                struct comedi_subdevice *s,
4725                                struct comedi_insn *insn, unsigned int *data)
4726 {
4727         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4728
4729         return 1;
4730 }
4731
4732 /*
4733         reads bytes out of eeprom
4734 */
4735
4736 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4737 {
4738         struct ni_private *devpriv __maybe_unused = dev->private;
4739         int bit;
4740         int bitstring;
4741
4742         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4743         ni_writeb(0x04, Serial_Command);
4744         for (bit = 0x8000; bit; bit >>= 1) {
4745                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4746                           Serial_Command);
4747                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4748                           Serial_Command);
4749         }
4750         bitstring = 0;
4751         for (bit = 0x80; bit; bit >>= 1) {
4752                 ni_writeb(0x04, Serial_Command);
4753                 ni_writeb(0x05, Serial_Command);
4754                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4755         }
4756         ni_writeb(0x00, Serial_Command);
4757
4758         return bitstring;
4759 }
4760
4761 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4762                                         struct comedi_subdevice *s,
4763                                         struct comedi_insn *insn,
4764                                         unsigned int *data)
4765 {
4766         struct ni_private *devpriv = dev->private;
4767
4768         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4769
4770         return 1;
4771 }
4772
4773 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4774 {
4775         struct ni_private *devpriv = dev->private;
4776
4777         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4778         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4779         return 3;
4780 }
4781
4782 static int ni_m_series_pwm_config(struct comedi_device *dev,
4783                                   struct comedi_subdevice *s,
4784                                   struct comedi_insn *insn, unsigned int *data)
4785 {
4786         struct ni_private *devpriv = dev->private;
4787         unsigned up_count, down_count;
4788
4789         switch (data[0]) {
4790         case INSN_CONFIG_PWM_OUTPUT:
4791                 switch (data[1]) {
4792                 case TRIG_ROUND_NEAREST:
4793                         up_count =
4794                             (data[2] +
4795                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4796                         break;
4797                 case TRIG_ROUND_DOWN:
4798                         up_count = data[2] / devpriv->clock_ns;
4799                         break;
4800                 case TRIG_ROUND_UP:
4801                         up_count =
4802                             (data[2] + devpriv->clock_ns -
4803                              1) / devpriv->clock_ns;
4804                         break;
4805                 default:
4806                         return -EINVAL;
4807                         break;
4808                 }
4809                 switch (data[3]) {
4810                 case TRIG_ROUND_NEAREST:
4811                         down_count =
4812                             (data[4] +
4813                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4814                         break;
4815                 case TRIG_ROUND_DOWN:
4816                         down_count = data[4] / devpriv->clock_ns;
4817                         break;
4818                 case TRIG_ROUND_UP:
4819                         down_count =
4820                             (data[4] + devpriv->clock_ns -
4821                              1) / devpriv->clock_ns;
4822                         break;
4823                 default:
4824                         return -EINVAL;
4825                         break;
4826                 }
4827                 if (up_count * devpriv->clock_ns != data[2] ||
4828                     down_count * devpriv->clock_ns != data[4]) {
4829                         data[2] = up_count * devpriv->clock_ns;
4830                         data[4] = down_count * devpriv->clock_ns;
4831                         return -EAGAIN;
4832                 }
4833                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4834                           MSeries_Cal_PWM_Low_Time_Bits(down_count),
4835                           M_Offset_Cal_PWM);
4836                 devpriv->pwm_up_count = up_count;
4837                 devpriv->pwm_down_count = down_count;
4838                 return 5;
4839                 break;
4840         case INSN_CONFIG_GET_PWM_OUTPUT:
4841                 return ni_get_pwm_config(dev, data);
4842                 break;
4843         default:
4844                 return -EINVAL;
4845                 break;
4846         }
4847         return 0;
4848 }
4849
4850 static int ni_6143_pwm_config(struct comedi_device *dev,
4851                               struct comedi_subdevice *s,
4852                               struct comedi_insn *insn, unsigned int *data)
4853 {
4854         struct ni_private *devpriv = dev->private;
4855         unsigned up_count, down_count;
4856
4857         switch (data[0]) {
4858         case INSN_CONFIG_PWM_OUTPUT:
4859                 switch (data[1]) {
4860                 case TRIG_ROUND_NEAREST:
4861                         up_count =
4862                             (data[2] +
4863                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4864                         break;
4865                 case TRIG_ROUND_DOWN:
4866                         up_count = data[2] / devpriv->clock_ns;
4867                         break;
4868                 case TRIG_ROUND_UP:
4869                         up_count =
4870                             (data[2] + devpriv->clock_ns -
4871                              1) / devpriv->clock_ns;
4872                         break;
4873                 default:
4874                         return -EINVAL;
4875                         break;
4876                 }
4877                 switch (data[3]) {
4878                 case TRIG_ROUND_NEAREST:
4879                         down_count =
4880                             (data[4] +
4881                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4882                         break;
4883                 case TRIG_ROUND_DOWN:
4884                         down_count = data[4] / devpriv->clock_ns;
4885                         break;
4886                 case TRIG_ROUND_UP:
4887                         down_count =
4888                             (data[4] + devpriv->clock_ns -
4889                              1) / devpriv->clock_ns;
4890                         break;
4891                 default:
4892                         return -EINVAL;
4893                         break;
4894                 }
4895                 if (up_count * devpriv->clock_ns != data[2] ||
4896                     down_count * devpriv->clock_ns != data[4]) {
4897                         data[2] = up_count * devpriv->clock_ns;
4898                         data[4] = down_count * devpriv->clock_ns;
4899                         return -EAGAIN;
4900                 }
4901                 ni_writel(up_count, Calibration_HighTime_6143);
4902                 devpriv->pwm_up_count = up_count;
4903                 ni_writel(down_count, Calibration_LowTime_6143);
4904                 devpriv->pwm_down_count = down_count;
4905                 return 5;
4906                 break;
4907         case INSN_CONFIG_GET_PWM_OUTPUT:
4908                 return ni_get_pwm_config(dev, data);
4909         default:
4910                 return -EINVAL;
4911                 break;
4912         }
4913         return 0;
4914 }
4915
4916 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4917 /*
4918         calibration subdevice
4919 */
4920 static int ni_calib_insn_write(struct comedi_device *dev,
4921                                struct comedi_subdevice *s,
4922                                struct comedi_insn *insn, unsigned int *data)
4923 {
4924         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4925
4926         return 1;
4927 }
4928
4929 static int ni_calib_insn_read(struct comedi_device *dev,
4930                               struct comedi_subdevice *s,
4931                               struct comedi_insn *insn, unsigned int *data)
4932 {
4933         struct ni_private *devpriv = dev->private;
4934
4935         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4936
4937         return 1;
4938 }
4939
4940 static int pack_mb88341(int addr, int val, int *bitstring);
4941 static int pack_dac8800(int addr, int val, int *bitstring);
4942 static int pack_dac8043(int addr, int val, int *bitstring);
4943 static int pack_ad8522(int addr, int val, int *bitstring);
4944 static int pack_ad8804(int addr, int val, int *bitstring);
4945 static int pack_ad8842(int addr, int val, int *bitstring);
4946
4947 struct caldac_struct {
4948         int n_chans;
4949         int n_bits;
4950         int (*packbits) (int, int, int *);
4951 };
4952
4953 static struct caldac_struct caldacs[] = {
4954         [mb88341] = {12, 8, pack_mb88341},
4955         [dac8800] = {8, 8, pack_dac8800},
4956         [dac8043] = {1, 12, pack_dac8043},
4957         [ad8522] = {2, 12, pack_ad8522},
4958         [ad8804] = {12, 8, pack_ad8804},
4959         [ad8842] = {8, 8, pack_ad8842},
4960         [ad8804_debug] = {16, 8, pack_ad8804},
4961 };
4962
4963 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4964 {
4965         const struct ni_board_struct *board = comedi_board(dev);
4966         struct ni_private *devpriv = dev->private;
4967         int i, j;
4968         int n_dacs;
4969         int n_chans = 0;
4970         int n_bits;
4971         int diffbits = 0;
4972         int type;
4973         int chan;
4974
4975         type = board->caldac[0];
4976         if (type == caldac_none)
4977                 return;
4978         n_bits = caldacs[type].n_bits;
4979         for (i = 0; i < 3; i++) {
4980                 type = board->caldac[i];
4981                 if (type == caldac_none)
4982                         break;
4983                 if (caldacs[type].n_bits != n_bits)
4984                         diffbits = 1;
4985                 n_chans += caldacs[type].n_chans;
4986         }
4987         n_dacs = i;
4988         s->n_chan = n_chans;
4989
4990         if (diffbits) {
4991                 unsigned int *maxdata_list;
4992
4993                 if (n_chans > MAX_N_CALDACS) {
4994                         printk("BUG! MAX_N_CALDACS too small\n");
4995                 }
4996                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4997                 chan = 0;
4998                 for (i = 0; i < n_dacs; i++) {
4999                         type = board->caldac[i];
5000                         for (j = 0; j < caldacs[type].n_chans; j++) {
5001                                 maxdata_list[chan] =
5002                                     (1 << caldacs[type].n_bits) - 1;
5003                                 chan++;
5004                         }
5005                 }
5006
5007                 for (chan = 0; chan < s->n_chan; chan++)
5008                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5009         } else {
5010                 type = board->caldac[0];
5011                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5012
5013                 for (chan = 0; chan < s->n_chan; chan++)
5014                         ni_write_caldac(dev, i, s->maxdata / 2);
5015         }
5016 }
5017
5018 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5019 {
5020         const struct ni_board_struct *board = comedi_board(dev);
5021         struct ni_private *devpriv = dev->private;
5022         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5023         int i;
5024         int type;
5025
5026         /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5027         if (devpriv->caldacs[addr] == val)
5028                 return;
5029         devpriv->caldacs[addr] = val;
5030
5031         for (i = 0; i < 3; i++) {
5032                 type = board->caldac[i];
5033                 if (type == caldac_none)
5034                         break;
5035                 if (addr < caldacs[type].n_chans) {
5036                         bits = caldacs[type].packbits(addr, val, &bitstring);
5037                         loadbit = SerDacLd(i);
5038                         /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5039                         break;
5040                 }
5041                 addr -= caldacs[type].n_chans;
5042         }
5043
5044         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5045                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5046                 udelay(1);
5047                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5048                 udelay(1);
5049         }
5050         ni_writeb(loadbit, Serial_Command);
5051         udelay(1);
5052         ni_writeb(0, Serial_Command);
5053 }
5054
5055 static int pack_mb88341(int addr, int val, int *bitstring)
5056 {
5057         /*
5058            Fujitsu MB 88341
5059            Note that address bits are reversed.  Thanks to
5060            Ingo Keen for noticing this.
5061
5062            Note also that the 88341 expects address values from
5063            1-12, whereas we use channel numbers 0-11.  The NI
5064            docs use 1-12, also, so be careful here.
5065          */
5066         addr++;
5067         *bitstring = ((addr & 0x1) << 11) |
5068             ((addr & 0x2) << 9) |
5069             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5070         return 12;
5071 }
5072
5073 static int pack_dac8800(int addr, int val, int *bitstring)
5074 {
5075         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5076         return 11;
5077 }
5078
5079 static int pack_dac8043(int addr, int val, int *bitstring)
5080 {
5081         *bitstring = val & 0xfff;
5082         return 12;
5083 }
5084
5085 static int pack_ad8522(int addr, int val, int *bitstring)
5086 {
5087         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5088         return 16;
5089 }
5090
5091 static int pack_ad8804(int addr, int val, int *bitstring)
5092 {
5093         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5094         return 12;
5095 }
5096
5097 static int pack_ad8842(int addr, int val, int *bitstring)
5098 {
5099         *bitstring = ((addr + 1) << 8) | (val & 0xff);
5100         return 12;
5101 }
5102
5103 #if 0
5104 /*
5105  *      Read the GPCTs current value.
5106  */
5107 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5108 {
5109         unsigned int hi1, hi2, lo;
5110
5111         devpriv->gpct_command[chan] &= ~G_Save_Trace;
5112         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5113                             G_Command_Register(chan));
5114
5115         devpriv->gpct_command[chan] |= G_Save_Trace;
5116         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5117                             G_Command_Register(chan));
5118
5119         /* This procedure is used because the two registers cannot
5120          * be read atomically. */
5121         do {
5122                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5123                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5124                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5125         } while (hi1 != hi2);
5126
5127         return (hi1 << 16) | lo;
5128 }
5129
5130 static void GPCT_Reset(struct comedi_device *dev, int chan)
5131 {
5132         int temp_ack_reg = 0;
5133
5134         /* printk("GPCT_Reset..."); */
5135         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5136
5137         switch (chan) {
5138         case 0:
5139                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5140                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5141                             G0_TC_Interrupt_Enable, 0);
5142                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5143                             G0_Gate_Interrupt_Enable, 0);
5144                 temp_ack_reg |= G0_Gate_Error_Confirm;
5145                 temp_ack_reg |= G0_TC_Error_Confirm;
5146                 temp_ack_reg |= G0_TC_Interrupt_Ack;
5147                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5148                 devpriv->stc_writew(dev, temp_ack_reg,
5149                                     Interrupt_A_Ack_Register);
5150
5151                 /* problem...this interferes with the other ctr... */
5152                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5153                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5154                                     Analog_Trigger_Etc_Register);
5155                 break;
5156         case 1:
5157                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5158                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5159                             G1_TC_Interrupt_Enable, 0);
5160                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5161                             G0_Gate_Interrupt_Enable, 0);
5162                 temp_ack_reg |= G1_Gate_Error_Confirm;
5163                 temp_ack_reg |= G1_TC_Error_Confirm;
5164                 temp_ack_reg |= G1_TC_Interrupt_Ack;
5165                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5166                 devpriv->stc_writew(dev, temp_ack_reg,
5167                                     Interrupt_B_Ack_Register);
5168
5169                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5170                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5171                                     Analog_Trigger_Etc_Register);
5172                 break;
5173         }
5174
5175         devpriv->gpct_mode[chan] = 0;
5176         devpriv->gpct_input_select[chan] = 0;
5177         devpriv->gpct_command[chan] = 0;
5178
5179         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5180
5181         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5182                             G_Mode_Register(chan));
5183         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5184                             G_Input_Select_Register(chan));
5185         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5186
5187         /* printk("exit GPCT_Reset\n"); */
5188 }
5189
5190 #endif
5191
5192 static int ni_gpct_insn_config(struct comedi_device *dev,
5193                                struct comedi_subdevice *s,
5194                                struct comedi_insn *insn, unsigned int *data)
5195 {
5196         struct ni_gpct *counter = s->private;
5197         return ni_tio_insn_config(counter, insn, data);
5198 }
5199
5200 static int ni_gpct_insn_read(struct comedi_device *dev,
5201                              struct comedi_subdevice *s,
5202                              struct comedi_insn *insn, unsigned int *data)
5203 {
5204         struct ni_gpct *counter = s->private;
5205         return ni_tio_rinsn(counter, insn, data);
5206 }
5207
5208 static int ni_gpct_insn_write(struct comedi_device *dev,
5209                               struct comedi_subdevice *s,
5210                               struct comedi_insn *insn, unsigned int *data)
5211 {
5212         struct ni_gpct *counter = s->private;
5213         return ni_tio_winsn(counter, insn, data);
5214 }
5215
5216 #ifdef PCIDMA
5217 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5218 {
5219         int retval;
5220         struct ni_gpct *counter = s->private;
5221 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5222
5223         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5224                                               COMEDI_INPUT);
5225         if (retval) {
5226                 comedi_error(dev,
5227                              "no dma channel available for use by counter");
5228                 return retval;
5229         }
5230         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5231         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5232         retval = ni_tio_cmd(counter, s->async);
5233         return retval;
5234 }
5235 #endif
5236
5237 #ifdef PCIDMA
5238 static int ni_gpct_cmdtest(struct comedi_device *dev,
5239                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
5240 {
5241         struct ni_gpct *counter = s->private;
5242
5243         return ni_tio_cmdtest(counter, cmd);
5244         return -ENOTSUPP;
5245 }
5246 #endif
5247
5248 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5249 {
5250 #ifdef PCIDMA
5251         struct ni_gpct *counter = s->private;
5252         int retval;
5253
5254         retval = ni_tio_cancel(counter);
5255         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5256         ni_release_gpct_mite_channel(dev, counter->counter_index);
5257         return retval;
5258 #else
5259         return 0;
5260 #endif
5261 }
5262
5263 /*
5264  *
5265  *  Programmable Function Inputs
5266  *
5267  */
5268
5269 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5270                                        unsigned source)
5271 {
5272         struct ni_private *devpriv = dev->private;
5273         unsigned pfi_reg_index;
5274         unsigned array_offset;
5275
5276         if ((source & 0x1f) != source)
5277                 return -EINVAL;
5278         pfi_reg_index = 1 + chan / 3;
5279         array_offset = pfi_reg_index - 1;
5280         devpriv->pfi_output_select_reg[array_offset] &=
5281             ~MSeries_PFI_Output_Select_Mask(chan);
5282         devpriv->pfi_output_select_reg[array_offset] |=
5283             MSeries_PFI_Output_Select_Bits(chan, source);
5284         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5285                   M_Offset_PFI_Output_Select(pfi_reg_index));
5286         return 2;
5287 }
5288
5289 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5290                                   unsigned source)
5291 {
5292         /*  pre-m-series boards have fixed signals on pfi pins */
5293         if (source != ni_old_get_pfi_routing(dev, chan))
5294                 return -EINVAL;
5295         return 2;
5296 }
5297
5298 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5299                               unsigned source)
5300 {
5301         const struct ni_board_struct *board = comedi_board(dev);
5302
5303         if (board->reg_type & ni_reg_m_series_mask)
5304                 return ni_m_series_set_pfi_routing(dev, chan, source);
5305         else
5306                 return ni_old_set_pfi_routing(dev, chan, source);
5307 }
5308
5309 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5310                                             unsigned chan)
5311 {
5312         struct ni_private *devpriv = dev->private;
5313         const unsigned array_offset = chan / 3;
5314
5315         return MSeries_PFI_Output_Select_Source(chan,
5316                                                 devpriv->
5317                                                 pfi_output_select_reg
5318                                                 [array_offset]);
5319 }
5320
5321 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5322 {
5323         /*  pre-m-series boards have fixed signals on pfi pins */
5324         switch (chan) {
5325         case 0:
5326                 return NI_PFI_OUTPUT_AI_START1;
5327                 break;
5328         case 1:
5329                 return NI_PFI_OUTPUT_AI_START2;
5330                 break;
5331         case 2:
5332                 return NI_PFI_OUTPUT_AI_CONVERT;
5333                 break;
5334         case 3:
5335                 return NI_PFI_OUTPUT_G_SRC1;
5336                 break;
5337         case 4:
5338                 return NI_PFI_OUTPUT_G_GATE1;
5339                 break;
5340         case 5:
5341                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5342                 break;
5343         case 6:
5344                 return NI_PFI_OUTPUT_AO_START1;
5345                 break;
5346         case 7:
5347                 return NI_PFI_OUTPUT_AI_START_PULSE;
5348                 break;
5349         case 8:
5350                 return NI_PFI_OUTPUT_G_SRC0;
5351                 break;
5352         case 9:
5353                 return NI_PFI_OUTPUT_G_GATE0;
5354                 break;
5355         default:
5356                 printk("%s: bug, unhandled case in switch.\n", __func__);
5357                 break;
5358         }
5359         return 0;
5360 }
5361
5362 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5363 {
5364         const struct ni_board_struct *board = comedi_board(dev);
5365
5366         if (board->reg_type & ni_reg_m_series_mask)
5367                 return ni_m_series_get_pfi_routing(dev, chan);
5368         else
5369                 return ni_old_get_pfi_routing(dev, chan);
5370 }
5371
5372 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5373                             enum ni_pfi_filter_select filter)
5374 {
5375         const struct ni_board_struct *board = comedi_board(dev);
5376         struct ni_private *devpriv __maybe_unused = dev->private;
5377         unsigned bits;
5378
5379         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5380                 return -ENOTSUPP;
5381         }
5382         bits = ni_readl(M_Offset_PFI_Filter);
5383         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5384         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5385         ni_writel(bits, M_Offset_PFI_Filter);
5386         return 0;
5387 }
5388
5389 static int ni_pfi_insn_bits(struct comedi_device *dev,
5390                             struct comedi_subdevice *s,
5391                             struct comedi_insn *insn, unsigned int *data)
5392 {
5393         const struct ni_board_struct *board = comedi_board(dev);
5394         struct ni_private *devpriv __maybe_unused = dev->private;
5395
5396         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5397                 return -ENOTSUPP;
5398         }
5399         if (data[0]) {
5400                 s->state &= ~data[0];
5401                 s->state |= (data[0] & data[1]);
5402                 ni_writew(s->state, M_Offset_PFI_DO);
5403         }
5404         data[1] = ni_readw(M_Offset_PFI_DI);
5405         return insn->n;
5406 }
5407
5408 static int ni_pfi_insn_config(struct comedi_device *dev,
5409                               struct comedi_subdevice *s,
5410                               struct comedi_insn *insn, unsigned int *data)
5411 {
5412         struct ni_private *devpriv = dev->private;
5413         unsigned int chan;
5414
5415         if (insn->n < 1)
5416                 return -EINVAL;
5417
5418         chan = CR_CHAN(insn->chanspec);
5419
5420         switch (data[0]) {
5421         case COMEDI_OUTPUT:
5422                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5423                 break;
5424         case COMEDI_INPUT:
5425                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5426                 break;
5427         case INSN_CONFIG_DIO_QUERY:
5428                 data[1] =
5429                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5430                     COMEDI_OUTPUT : COMEDI_INPUT;
5431                 return 0;
5432                 break;
5433         case INSN_CONFIG_SET_ROUTING:
5434                 return ni_set_pfi_routing(dev, chan, data[1]);
5435                 break;
5436         case INSN_CONFIG_GET_ROUTING:
5437                 data[1] = ni_get_pfi_routing(dev, chan);
5438                 break;
5439         case INSN_CONFIG_FILTER:
5440                 return ni_config_filter(dev, chan, data[1]);
5441                 break;
5442         default:
5443                 return -EINVAL;
5444         }
5445         return 0;
5446 }
5447
5448 /*
5449  *
5450  *  NI RTSI Bus Functions
5451  *
5452  */
5453 static void ni_rtsi_init(struct comedi_device *dev)
5454 {
5455         const struct ni_board_struct *board = comedi_board(dev);
5456         struct ni_private *devpriv = dev->private;
5457
5458         /*  Initialises the RTSI bus signal switch to a default state */
5459
5460         /*  Set clock mode to internal */
5461         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5462         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5463                 printk("ni_set_master_clock failed, bug?");
5464         }
5465         /*  default internal lines routing to RTSI bus lines */
5466         devpriv->rtsi_trig_a_output_reg =
5467             RTSI_Trig_Output_Bits(0,
5468                                   NI_RTSI_OUTPUT_ADR_START1) |
5469             RTSI_Trig_Output_Bits(1,
5470                                   NI_RTSI_OUTPUT_ADR_START2) |
5471             RTSI_Trig_Output_Bits(2,
5472                                   NI_RTSI_OUTPUT_SCLKG) |
5473             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5474         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5475                             RTSI_Trig_A_Output_Register);
5476         devpriv->rtsi_trig_b_output_reg =
5477             RTSI_Trig_Output_Bits(4,
5478                                   NI_RTSI_OUTPUT_DA_START1) |
5479             RTSI_Trig_Output_Bits(5,
5480                                   NI_RTSI_OUTPUT_G_SRC0) |
5481             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5482         if (board->reg_type & ni_reg_m_series_mask)
5483                 devpriv->rtsi_trig_b_output_reg |=
5484                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5485         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5486                             RTSI_Trig_B_Output_Register);
5487
5488 /*
5489 * Sets the source and direction of the 4 on board lines
5490 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5491 */
5492 }
5493
5494 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5495                              struct comedi_subdevice *s,
5496                              struct comedi_insn *insn, unsigned int *data)
5497 {
5498         data[1] = 0;
5499
5500         return insn->n;
5501 }
5502
5503 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5504  * given an arbitrary frequency input clock */
5505 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5506                                          unsigned *freq_divider,
5507                                          unsigned *freq_multiplier,
5508                                          unsigned *actual_period_ns)
5509 {
5510         unsigned div;
5511         unsigned best_div = 1;
5512         static const unsigned max_div = 0x10;
5513         unsigned mult;
5514         unsigned best_mult = 1;
5515         static const unsigned max_mult = 0x100;
5516         static const unsigned pico_per_nano = 1000;
5517
5518         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5519         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5520          * 20 MHz for most timing clocks */
5521         static const unsigned target_picosec = 12500;
5522         static const unsigned fudge_factor_80_to_20Mhz = 4;
5523         int best_period_picosec = 0;
5524         for (div = 1; div <= max_div; ++div) {
5525                 for (mult = 1; mult <= max_mult; ++mult) {
5526                         unsigned new_period_ps =
5527                             (reference_picosec * div) / mult;
5528                         if (abs(new_period_ps - target_picosec) <
5529                             abs(best_period_picosec - target_picosec)) {
5530                                 best_period_picosec = new_period_ps;
5531                                 best_div = div;
5532                                 best_mult = mult;
5533                         }
5534                 }
5535         }
5536         if (best_period_picosec == 0) {
5537                 printk("%s: bug, failed to find pll parameters\n", __func__);
5538                 return -EIO;
5539         }
5540         *freq_divider = best_div;
5541         *freq_multiplier = best_mult;
5542         *actual_period_ns =
5543             (best_period_picosec * fudge_factor_80_to_20Mhz +
5544              (pico_per_nano / 2)) / pico_per_nano;
5545         return 0;
5546 }
5547
5548 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5549 {
5550         const struct ni_board_struct *board = comedi_board(dev);
5551
5552         if (board->reg_type & ni_reg_m_series_mask)
5553                 return 8;
5554         else
5555                 return 7;
5556 }
5557
5558 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5559                                            unsigned source, unsigned period_ns)
5560 {
5561         struct ni_private *devpriv = dev->private;
5562         static const unsigned min_period_ns = 50;
5563         static const unsigned max_period_ns = 1000;
5564         static const unsigned timeout = 1000;
5565         unsigned pll_control_bits;
5566         unsigned freq_divider;
5567         unsigned freq_multiplier;
5568         unsigned i;
5569         int retval;
5570
5571         if (source == NI_MIO_PLL_PXI10_CLOCK)
5572                 period_ns = 100;
5573         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5574         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5575                 printk
5576                     ("%s: you must specify an input clock frequency between %i and %i nanosec "
5577                      "for the phased-lock loop.\n", __func__,
5578                      min_period_ns, max_period_ns);
5579                 return -EINVAL;
5580         }
5581         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5582         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5583                             RTSI_Trig_Direction_Register);
5584         pll_control_bits =
5585             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5586         devpriv->clock_and_fout2 |=
5587             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5588         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5589         switch (source) {
5590         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5591                 devpriv->clock_and_fout2 |=
5592                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5593                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5594                                                        &freq_multiplier,
5595                                                        &devpriv->clock_ns);
5596                 if (retval < 0)
5597                         return retval;
5598                 break;
5599         case NI_MIO_PLL_PXI10_CLOCK:
5600                 /* pxi clock is 10MHz */
5601                 devpriv->clock_and_fout2 |=
5602                     MSeries_PLL_In_Source_Select_PXI_Clock10;
5603                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5604                                                        &freq_multiplier,
5605                                                        &devpriv->clock_ns);
5606                 if (retval < 0)
5607                         return retval;
5608                 break;
5609         default:
5610                 {
5611                         unsigned rtsi_channel;
5612                         static const unsigned max_rtsi_channel = 7;
5613                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5614                              ++rtsi_channel) {
5615                                 if (source ==
5616                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5617                                         devpriv->clock_and_fout2 |=
5618                                             MSeries_PLL_In_Source_Select_RTSI_Bits
5619                                             (rtsi_channel);
5620                                         break;
5621                                 }
5622                         }
5623                         if (rtsi_channel > max_rtsi_channel)
5624                                 return -EINVAL;
5625                         retval = ni_mseries_get_pll_parameters(period_ns,
5626                                                                &freq_divider,
5627                                                                &freq_multiplier,
5628                                                                &devpriv->
5629                                                                clock_ns);
5630                         if (retval < 0)
5631                                 return retval;
5632                 }
5633                 break;
5634         }
5635         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5636         pll_control_bits |=
5637             MSeries_PLL_Divisor_Bits(freq_divider) |
5638             MSeries_PLL_Multiplier_Bits(freq_multiplier);
5639
5640         /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5641          * freq_divider, freq_multiplier, pll_control_bits); */
5642         /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5643         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5644         devpriv->clock_source = source;
5645         /* it seems to typically take a few hundred microseconds for PLL to lock */
5646         for (i = 0; i < timeout; ++i) {
5647                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5648                         break;
5649                 }
5650                 udelay(1);
5651         }
5652         if (i == timeout) {
5653                 printk
5654                     ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5655                      __func__, source, period_ns);
5656                 return -ETIMEDOUT;
5657         }
5658         return 3;
5659 }
5660
5661 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5662                                unsigned period_ns)
5663 {
5664         const struct ni_board_struct *board = comedi_board(dev);
5665         struct ni_private *devpriv = dev->private;
5666
5667         if (source == NI_MIO_INTERNAL_CLOCK) {
5668                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5669                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5670                                     RTSI_Trig_Direction_Register);
5671                 devpriv->clock_ns = TIMEBASE_1_NS;
5672                 if (board->reg_type & ni_reg_m_series_mask) {
5673                         devpriv->clock_and_fout2 &=
5674                             ~(MSeries_Timebase1_Select_Bit |
5675                               MSeries_Timebase3_Select_Bit);
5676                         ni_writew(devpriv->clock_and_fout2,
5677                                   M_Offset_Clock_and_Fout2);
5678                         ni_writew(0, M_Offset_PLL_Control);
5679                 }
5680                 devpriv->clock_source = source;
5681         } else {
5682                 if (board->reg_type & ni_reg_m_series_mask) {
5683                         return ni_mseries_set_pll_master_clock(dev, source,
5684                                                                period_ns);
5685                 } else {
5686                         if (source == NI_MIO_RTSI_CLOCK) {
5687                                 devpriv->rtsi_trig_direction_reg |=
5688                                     Use_RTSI_Clock_Bit;
5689                                 devpriv->stc_writew(dev,
5690                                                     devpriv->
5691                                                     rtsi_trig_direction_reg,
5692                                                     RTSI_Trig_Direction_Register);
5693                                 if (period_ns == 0) {
5694                                         printk
5695                                             ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5696                                              __func__);
5697                                         return -EINVAL;
5698                                 } else {
5699                                         devpriv->clock_ns = period_ns;
5700                                 }
5701                                 devpriv->clock_source = source;
5702                         } else
5703                                 return -EINVAL;
5704                 }
5705         }
5706         return 3;
5707 }
5708
5709 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5710                                        unsigned source)
5711 {
5712         const struct ni_board_struct *board = comedi_board(dev);
5713
5714         if (chan >= num_configurable_rtsi_channels(dev)) {
5715                 if (chan == old_RTSI_clock_channel) {
5716                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5717                                 return 1;
5718                         else {
5719                                 printk
5720                                     ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5721                                      __func__, chan, old_RTSI_clock_channel);
5722                                 return 0;
5723                         }
5724                 }
5725                 return 0;
5726         }
5727         switch (source) {
5728         case NI_RTSI_OUTPUT_ADR_START1:
5729         case NI_RTSI_OUTPUT_ADR_START2:
5730         case NI_RTSI_OUTPUT_SCLKG:
5731         case NI_RTSI_OUTPUT_DACUPDN:
5732         case NI_RTSI_OUTPUT_DA_START1:
5733         case NI_RTSI_OUTPUT_G_SRC0:
5734         case NI_RTSI_OUTPUT_G_GATE0:
5735         case NI_RTSI_OUTPUT_RGOUT0:
5736         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5737                 return 1;
5738                 break;
5739         case NI_RTSI_OUTPUT_RTSI_OSC:
5740                 if (board->reg_type & ni_reg_m_series_mask)
5741                         return 1;
5742                 else
5743                         return 0;
5744                 break;
5745         default:
5746                 return 0;
5747                 break;
5748         }
5749 }
5750
5751 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5752                                unsigned source)
5753 {
5754         struct ni_private *devpriv = dev->private;
5755
5756         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5757                 return -EINVAL;
5758         if (chan < 4) {
5759                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5760                 devpriv->rtsi_trig_a_output_reg |=
5761                     RTSI_Trig_Output_Bits(chan, source);
5762                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5763                                     RTSI_Trig_A_Output_Register);
5764         } else if (chan < 8) {
5765                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5766                 devpriv->rtsi_trig_b_output_reg |=
5767                     RTSI_Trig_Output_Bits(chan, source);
5768                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5769                                     RTSI_Trig_B_Output_Register);
5770         }
5771         return 2;
5772 }
5773
5774 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5775 {
5776         struct ni_private *devpriv = dev->private;
5777
5778         if (chan < 4) {
5779                 return RTSI_Trig_Output_Source(chan,
5780                                                devpriv->rtsi_trig_a_output_reg);
5781         } else if (chan < num_configurable_rtsi_channels(dev)) {
5782                 return RTSI_Trig_Output_Source(chan,
5783                                                devpriv->rtsi_trig_b_output_reg);
5784         } else {
5785                 if (chan == old_RTSI_clock_channel)
5786                         return NI_RTSI_OUTPUT_RTSI_OSC;
5787                 printk("%s: bug! should never get here?\n", __func__);
5788                 return 0;
5789         }
5790 }
5791
5792 static int ni_rtsi_insn_config(struct comedi_device *dev,
5793                                struct comedi_subdevice *s,
5794                                struct comedi_insn *insn, unsigned int *data)
5795 {
5796         const struct ni_board_struct *board = comedi_board(dev);
5797         struct ni_private *devpriv = dev->private;
5798         unsigned int chan = CR_CHAN(insn->chanspec);
5799
5800         switch (data[0]) {
5801         case INSN_CONFIG_DIO_OUTPUT:
5802                 if (chan < num_configurable_rtsi_channels(dev)) {
5803                         devpriv->rtsi_trig_direction_reg |=
5804                             RTSI_Output_Bit(chan,
5805                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5806                 } else if (chan == old_RTSI_clock_channel) {
5807                         devpriv->rtsi_trig_direction_reg |=
5808                             Drive_RTSI_Clock_Bit;
5809                 }
5810                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5811                                     RTSI_Trig_Direction_Register);
5812                 break;
5813         case INSN_CONFIG_DIO_INPUT:
5814                 if (chan < num_configurable_rtsi_channels(dev)) {
5815                         devpriv->rtsi_trig_direction_reg &=
5816                             ~RTSI_Output_Bit(chan,
5817                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5818                 } else if (chan == old_RTSI_clock_channel) {
5819                         devpriv->rtsi_trig_direction_reg &=
5820                             ~Drive_RTSI_Clock_Bit;
5821                 }
5822                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5823                                     RTSI_Trig_Direction_Register);
5824                 break;
5825         case INSN_CONFIG_DIO_QUERY:
5826                 if (chan < num_configurable_rtsi_channels(dev)) {
5827                         data[1] =
5828                             (devpriv->rtsi_trig_direction_reg &
5829                              RTSI_Output_Bit(chan,
5830                                 (board->reg_type & ni_reg_m_series_mask) != 0))
5831                                 ? INSN_CONFIG_DIO_OUTPUT
5832                                 : INSN_CONFIG_DIO_INPUT;
5833                 } else if (chan == old_RTSI_clock_channel) {
5834                         data[1] =
5835                             (devpriv->rtsi_trig_direction_reg &
5836                              Drive_RTSI_Clock_Bit)
5837                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5838                 }
5839                 return 2;
5840                 break;
5841         case INSN_CONFIG_SET_CLOCK_SRC:
5842                 return ni_set_master_clock(dev, data[1], data[2]);
5843                 break;
5844         case INSN_CONFIG_GET_CLOCK_SRC:
5845                 data[1] = devpriv->clock_source;
5846                 data[2] = devpriv->clock_ns;
5847                 return 3;
5848                 break;
5849         case INSN_CONFIG_SET_ROUTING:
5850                 return ni_set_rtsi_routing(dev, chan, data[1]);
5851                 break;
5852         case INSN_CONFIG_GET_ROUTING:
5853                 data[1] = ni_get_rtsi_routing(dev, chan);
5854                 return 2;
5855                 break;
5856         default:
5857                 return -EINVAL;
5858                 break;
5859         }
5860         return 1;
5861 }
5862
5863 static int cs5529_wait_for_idle(struct comedi_device *dev)
5864 {
5865         unsigned short status;
5866         const int timeout = HZ;
5867         int i;
5868
5869         for (i = 0; i < timeout; i++) {
5870                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5871                 if ((status & CSS_ADC_BUSY) == 0) {
5872                         break;
5873                 }
5874                 set_current_state(TASK_INTERRUPTIBLE);
5875                 if (schedule_timeout(1)) {
5876                         return -EIO;
5877                 }
5878         }
5879 /* printk("looped %i times waiting for idle\n", i); */
5880         if (i == timeout) {
5881                 printk("%s: %s: timeout\n", __FILE__, __func__);
5882                 return -ETIME;
5883         }
5884         return 0;
5885 }
5886
5887 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5888 {
5889         static const int timeout = 100;
5890         int i;
5891
5892         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5893         /* give time for command to start being serially clocked into cs5529.
5894          * this insures that the CSS_ADC_BUSY bit will get properly
5895          * set before we exit this function.
5896          */
5897         for (i = 0; i < timeout; i++) {
5898                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5899                         break;
5900                 udelay(1);
5901         }
5902 /* printk("looped %i times writing command to cs5529\n", i); */
5903         if (i == timeout) {
5904                 comedi_error(dev, "possible problem - never saw adc go busy?");
5905         }
5906 }
5907
5908 /* write to cs5529 register */
5909 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5910                                 unsigned int reg_select_bits)
5911 {
5912         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5913                        CAL_ADC_Config_Data_High_Word_67xx);
5914         ni_ao_win_outw(dev, (value & 0xffff),
5915                        CAL_ADC_Config_Data_Low_Word_67xx);
5916         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5917         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5918         if (cs5529_wait_for_idle(dev))
5919                 comedi_error(dev, "time or signal in cs5529_config_write()");
5920 }
5921
5922 #ifdef NI_CS5529_DEBUG
5923 /* read from cs5529 register */
5924 static unsigned int cs5529_config_read(struct comedi_device *dev,
5925                                        unsigned int reg_select_bits)
5926 {
5927         unsigned int value;
5928
5929         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5930         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5931         if (cs5529_wait_for_idle(dev))
5932                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5933         value = (ni_ao_win_inw(dev,
5934                                CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5935             0xff0000;
5936         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5937         return value;
5938 }
5939 #endif
5940
5941 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5942 {
5943         int retval;
5944         unsigned short status;
5945
5946         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5947         retval = cs5529_wait_for_idle(dev);
5948         if (retval) {
5949                 comedi_error(dev,
5950                              "timeout or signal in cs5529_do_conversion()");
5951                 return -ETIME;
5952         }
5953         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5954         if (status & CSS_OSC_DETECT) {
5955                 printk
5956                     ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5957                 return -EIO;
5958         }
5959         if (status & CSS_OVERRANGE) {
5960                 printk
5961                     ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5962         }
5963         if (data) {
5964                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5965                 /* cs5529 returns 16 bit signed data in bipolar mode */
5966                 *data ^= (1 << 15);
5967         }
5968         return 0;
5969 }
5970
5971 static int cs5529_ai_insn_read(struct comedi_device *dev,
5972                                struct comedi_subdevice *s,
5973                                struct comedi_insn *insn, unsigned int *data)
5974 {
5975         int n, retval;
5976         unsigned short sample;
5977         unsigned int channel_select;
5978         const unsigned int INTERNAL_REF = 0x1000;
5979
5980         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5981          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5982          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5983         if (insn->chanspec & CR_ALT_SOURCE)
5984                 channel_select = INTERNAL_REF;
5985         else
5986                 channel_select = CR_CHAN(insn->chanspec);
5987         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5988
5989         for (n = 0; n < insn->n; n++) {
5990                 retval = cs5529_do_conversion(dev, &sample);
5991                 if (retval < 0)
5992                         return retval;
5993                 data[n] = sample;
5994         }
5995         return insn->n;
5996 }
5997
5998 static int init_cs5529(struct comedi_device *dev)
5999 {
6000         unsigned int config_bits =
6001             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6002
6003 #if 1
6004         /* do self-calibration */
6005         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6006                             CSCMD_CONFIG_REGISTER);
6007         /* need to force a conversion for calibration to run */
6008         cs5529_do_conversion(dev, NULL);
6009 #else
6010         /* force gain calibration to 1 */
6011         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6012         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6013                             CSCMD_CONFIG_REGISTER);
6014         if (cs5529_wait_for_idle(dev))
6015                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6016 #endif
6017 #ifdef NI_CS5529_DEBUG
6018         printk("config: 0x%x\n", cs5529_config_read(dev,
6019                                                     CSCMD_CONFIG_REGISTER));
6020         printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6021         printk("offset: 0x%x\n", cs5529_config_read(dev,
6022                                                     CSCMD_OFFSET_REGISTER));
6023 #endif
6024         return 0;
6025 }