drivers/staging/comedi/drivers/ni_pcidio.c

   1 /*
   2     comedi/drivers/ni_pcidio.c
   3     driver for National Instruments PCI-DIO-96/PCI-6508
   4                 National Instruments PCI-DIO-32HS
   5                 National Instruments PCI-6503
   6
   7     COMEDI - Linux Control and Measurement Device Interface
   8     Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   9
  10     This program is free software; you can redistribute it and/or modify
  11     it under the terms of the GNU General Public License as published by
  12     the Free Software Foundation; either version 2 of the License, or
  13     (at your option) any later version.
  14
  15     This program is distributed in the hope that it will be useful,
  16     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18     GNU General Public License for more details.
  19
  20     You should have received a copy of the GNU General Public License
  21     along with this program; if not, write to the Free Software
  22     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23
  24 */
  25 /*
  26 Driver: ni_pcidio
  27 Description: National Instruments PCI-DIO32HS, PCI-DIO96, PCI-6533, PCI-6503
  28 Author: ds
  29 Status: works
  30 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio), PXI-6533,
  31   PCI-DIO-96, PCI-DIO-96B, PXI-6508, PCI-6503, PCI-6503B, PCI-6503X,
  32   PXI-6503, PCI-6533, PCI-6534
  33 Updated: Mon, 09 Jan 2012 14:27:23 +0000
  34
  35 The DIO-96 appears as four 8255 subdevices.  See the 8255
  36 driver notes for details.
  37
  38 The DIO32HS board appears as one subdevice, with 32 channels.
  39 Each channel is individually I/O configurable.  The channel order
  40 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0.  The driver only
  41 supports simple digital I/O; no handshaking is supported.
  42
  43 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  44
  45 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  46 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  47 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  48 trailing edge.
  49
  50 This driver could be easily modified to support AT-MIO32HS and
  51 AT-MIO96.
  52
  53 The PCI-6534 requires a firmware upload after power-up to work, the
  54 firmware data and instructions for loading it with comedi_config
  55 it are contained in the
  56 comedi_nonfree_firmware tarball available from http://www.comedi.org
  57 */
  58
  59 /*
  60    This driver is for both the NI PCI-DIO-32HS and the PCI-DIO-96,
  61    which have very different architectures.  But, since the '96 is
  62    so simple, it is included here.
  63
  64    Manuals (available from ftp://ftp.natinst.com/support/manuals)
  65
  66         320938c.pdf     PCI-DIO-96/PXI-6508/PCI-6503 User Manual
  67         321464b.pdf     AT/PCI-DIO-32HS User Manual
  68         341329A.pdf     PCI-6533 Register-Level Programmer Manual
  69         341330A.pdf     DAQ-DIO Technical Reference Manual
  70
  71  */
  72
  73 #define USE_DMA
  74 /* #define DEBUG 1 */
  75 /* #define DEBUG_FLAGS */
  76
  77 #include <linux/interrupt.h>
  78 #include <linux/sched.h>
  79 #include "../comedidev.h"
  80
  81 #include "mite.h"
  82 #include "8255.h"
  83
  84 #undef DPRINTK
  85 #ifdef DEBUG
  86 #define DPRINTK(format, args...)        printk(format, ## args)
  87 #else
  88 #define DPRINTK(format, args...)
  89 #endif
  90
  91 #define PCI_DIO_SIZE 4096
  92 #define PCI_MITE_SIZE 4096
  93
  94 /* defines for the PCI-DIO-96 */
  95
  96 #define NIDIO_8255_BASE(x)      ((x)*4)
  97 #define NIDIO_A 0
  98 #define NIDIO_B 4
  99 #define NIDIO_C 8
 100 #define NIDIO_D 12
 101
 102 /* defines for the PCI-DIO-32HS */
 103
 104 #define Window_Address                  4       /* W */
 105 #define Interrupt_And_Window_Status     4       /* R */
 106 #define IntStatus1                              (1<<0)
 107 #define IntStatus2                              (1<<1)
 108 #define WindowAddressStatus_mask                0x7c
 109
 110 #define Master_DMA_And_Interrupt_Control 5      /* W */
 111 #define InterruptLine(x)                        ((x)&3)
 112 #define OpenInt                         (1<<2)
 113 #define Group_Status                    5       /* R */
 114 #define DataLeft                                (1<<0)
 115 #define Req                                     (1<<2)
 116 #define StopTrig                                (1<<3)
 117
 118 #define Group_1_Flags                   6       /* R */
 119 #define Group_2_Flags                   7       /* R */
 120 #define TransferReady                           (1<<0)
 121 #define CountExpired                            (1<<1)
 122 #define Waited                          (1<<5)
 123 #define PrimaryTC                               (1<<6)
 124 #define SecondaryTC                             (1<<7)
 125   /* #define SerialRose */
 126   /* #define ReqRose */
 127   /* #define Paused */
 128
 129 #define Group_1_First_Clear             6       /* W */
 130 #define Group_2_First_Clear             7       /* W */
 131 #define ClearWaited                             (1<<3)
 132 #define ClearPrimaryTC                  (1<<4)
 133 #define ClearSecondaryTC                        (1<<5)
 134 #define DMAReset                                (1<<6)
 135 #define FIFOReset                               (1<<7)
 136 #define ClearAll                                0xf8
 137
 138 #define Group_1_FIFO                    8       /* W */
 139 #define Group_2_FIFO                    12      /* W */
 140
 141 #define Transfer_Count                  20
 142 #define Chip_ID_D                       24
 143 #define Chip_ID_I                       25
 144 #define Chip_ID_O                       26
 145 #define Chip_Version                    27
 146 #define Port_IO(x)                      (28+(x))
 147 #define Port_Pin_Directions(x)          (32+(x))
 148 #define Port_Pin_Mask(x)                (36+(x))
 149 #define Port_Pin_Polarities(x)          (40+(x))
 150
 151 #define Master_Clock_Routing            45
 152 #define RTSIClocking(x)                 (((x)&3)<<4)
 153
 154 #define Group_1_Second_Clear            46      /* W */
 155 #define Group_2_Second_Clear            47      /* W */
 156 #define ClearExpired                            (1<<0)
 157
 158 #define Port_Pattern(x)                 (48+(x))
 159
 160 #define Data_Path                       64
 161 #define FIFOEnableA             (1<<0)
 162 #define FIFOEnableB             (1<<1)
 163 #define FIFOEnableC             (1<<2)
 164 #define FIFOEnableD             (1<<3)
 165 #define Funneling(x)            (((x)&3)<<4)
 166 #define GroupDirection  (1<<7)
 167
 168 #define Protocol_Register_1             65
 169 #define OpMode                          Protocol_Register_1
 170 #define RunMode(x)              ((x)&7)
 171 #define Numbered                (1<<3)
 172
 173 #define Protocol_Register_2             66
 174 #define ClockReg                        Protocol_Register_2
 175 #define ClockLine(x)            (((x)&3)<<5)
 176 #define InvertStopTrig  (1<<7)
 177 #define DataLatching(x)       (((x)&3)<<5)
 178
 179 #define Protocol_Register_3             67
 180 #define Sequence                        Protocol_Register_3
 181
 182 #define Protocol_Register_14            68      /* 16 bit */
 183 #define ClockSpeed                      Protocol_Register_14
 184
 185 #define Protocol_Register_4             70
 186 #define ReqReg                          Protocol_Register_4
 187 #define ReqConditioning(x)      (((x)&7)<<3)
 188
 189 #define Protocol_Register_5             71
 190 #define BlockMode                       Protocol_Register_5
 191
 192 #define FIFO_Control                    72
 193 #define ReadyLevel(x)           ((x)&7)
 194
 195 #define Protocol_Register_6             73
 196 #define LinePolarities                  Protocol_Register_6
 197 #define InvertAck               (1<<0)
 198 #define InvertReq               (1<<1)
 199 #define InvertClock             (1<<2)
 200 #define InvertSerial            (1<<3)
 201 #define OpenAck         (1<<4)
 202 #define OpenClock               (1<<5)
 203
 204 #define Protocol_Register_7             74
 205 #define AckSer                          Protocol_Register_7
 206 #define AckLine(x)              (((x)&3)<<2)
 207 #define ExchangePins            (1<<7)
 208
 209 #define Interrupt_Control               75
 210   /* bits same as flags */
 211
 212 #define DMA_Line_Control_Group1         76
 213 #define DMA_Line_Control_Group2         108
 214 /* channel zero is none */
 215 static inline unsigned primary_DMAChannel_bits(unsigned channel)
 216 {
 217         return channel & 0x3;
 218 }
 219
 220 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
 221 {
 222         return (channel << 2) & 0xc;
 223 }
 224
 225 #define Transfer_Size_Control           77
 226 #define TransferWidth(x)        ((x)&3)
 227 #define TransferLength(x)       (((x)&3)<<3)
 228 #define RequireRLevel           (1<<5)
 229
 230 #define Protocol_Register_15            79
 231 #define DAQOptions                      Protocol_Register_15
 232 #define StartSource(x)                  ((x)&0x3)
 233 #define InvertStart                             (1<<2)
 234 #define StopSource(x)                           (((x)&0x3)<<3)
 235 #define ReqStart                                (1<<6)
 236 #define PreStart                                (1<<7)
 237
 238 #define Pattern_Detection               81
 239 #define DetectionMethod                 (1<<0)
 240 #define InvertMatch                             (1<<1)
 241 #define IE_Pattern_Detection                    (1<<2)
 242
 243 #define Protocol_Register_9             82
 244 #define ReqDelay                        Protocol_Register_9
 245
 246 #define Protocol_Register_10            83
 247 #define ReqNotDelay                     Protocol_Register_10
 248
 249 #define Protocol_Register_11            84
 250 #define AckDelay                        Protocol_Register_11
 251
 252 #define Protocol_Register_12            85
 253 #define AckNotDelay                     Protocol_Register_12
 254
 255 #define Protocol_Register_13            86
 256 #define Data1Delay                      Protocol_Register_13
 257
 258 #define Protocol_Register_8             88      /* 32 bit */
 259 #define StartDelay                      Protocol_Register_8
 260
 261 enum pci_6534_firmware_registers {      /* 16 bit */
 262         Firmware_Control_Register = 0x100,
 263         Firmware_Status_Register = 0x104,
 264         Firmware_Data_Register = 0x108,
 265         Firmware_Mask_Register = 0x10c,
 266         Firmware_Debug_Register = 0x110,
 267 };
 268 /* main fpga registers (32 bit)*/
 269 enum pci_6534_fpga_registers {
 270         FPGA_Control1_Register = 0x200,
 271         FPGA_Control2_Register = 0x204,
 272         FPGA_Irq_Mask_Register = 0x208,
 273         FPGA_Status_Register = 0x20c,
 274         FPGA_Signature_Register = 0x210,
 275         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 276         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 277         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 278         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 279         FPGA_Temp_Control_Register = 0x2a0,
 280         FPGA_DAR_Register = 0x2a8,
 281         FPGA_ELC_Read_Register = 0x2b8,
 282         FPGA_ELC_Write_Register = 0x2bc,
 283 };
 284 enum FPGA_Control_Bits {
 285         FPGA_Enable_Bit = 0x8000,
 286 };
 287
 288 #define TIMER_BASE 50           /* nanoseconds */
 289
 290 #ifdef USE_DMA
 291 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
 292 #else
 293 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
 294 #endif
 295
 296 static int ni_pcidio_cancel(struct comedi_device *dev,
 297                             struct comedi_subdevice *s);
 298
 299 struct nidio_board {
 300
 301         int dev_id;
 302         const char *name;
 303         int n_8255;
 304         unsigned int is_diodaq:1;
 305         unsigned int uses_firmware:1;
 306 };
 307
 308 static const struct nidio_board nidio_boards[] = {
 309         {
 310          .dev_id = 0x1150,
 311          .name = "pci-dio-32hs",
 312          .n_8255 = 0,
 313          .is_diodaq = 1,
 314          },
 315         {
 316          .dev_id = 0x1320,
 317          .name = "pxi-6533",
 318          .n_8255 = 0,
 319          .is_diodaq = 1,
 320          },
 321         {
 322          .dev_id = 0x12b0,
 323          .name = "pci-6534",
 324          .n_8255 = 0,
 325          .is_diodaq = 1,
 326          .uses_firmware = 1,
 327          },
 328         {
 329          .dev_id = 0x0160,
 330          .name = "pci-dio-96",
 331          .n_8255 = 4,
 332          .is_diodaq = 0,
 333          },
 334         {
 335          .dev_id = 0x1630,
 336          .name = "pci-dio-96b",
 337          .n_8255 = 4,
 338          .is_diodaq = 0,
 339          },
 340         {
 341          .dev_id = 0x13c0,
 342          .name = "pxi-6508",
 343          .n_8255 = 4,
 344          .is_diodaq = 0,
 345          },
 346         {
 347          .dev_id = 0x0400,
 348          .name = "pci-6503",
 349          .n_8255 = 1,
 350          .is_diodaq = 0,
 351          },
 352         {
 353          .dev_id = 0x1250,
 354          .name = "pci-6503b",
 355          .n_8255 = 1,
 356          .is_diodaq = 0,
 357          },
 358         {
 359          .dev_id = 0x17d0,
 360          .name = "pci-6503x",
 361          .n_8255 = 1,
 362          .is_diodaq = 0,
 363          },
 364         {
 365          .dev_id = 0x1800,
 366          .name = "pxi-6503",
 367          .n_8255 = 1,
 368          .is_diodaq = 0,
 369          },
 370 };
 371
 372 #define n_nidio_boards ARRAY_SIZE(nidio_boards)
 373 #define this_board ((const struct nidio_board *)dev->board_ptr)
 374
 375 struct nidio96_private {
 376         struct mite_struct *mite;
 377         int boardtype;
 378         int dio;
 379         unsigned short OpModeBits;
 380         struct mite_channel *di_mite_chan;
 381         struct mite_dma_descriptor_ring *di_mite_ring;
 382         spinlock_t mite_channel_lock;
 383 };
 384 #define devpriv ((struct nidio96_private *)dev->private)
 385
 386 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 387                              struct comedi_subdevice *s,
 388                              struct comedi_cmd *cmd);
 389 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 390 static int ni_pcidio_inttrig(struct comedi_device *dev,
 391                              struct comedi_subdevice *s, unsigned int trignum);
 392 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode);
 393 static int setup_mite_dma(struct comedi_device *dev,
 394                           struct comedi_subdevice *s);
 395
 396 #ifdef DEBUG_FLAGS
 397 static void ni_pcidio_print_flags(unsigned int flags);
 398 static void ni_pcidio_print_status(unsigned int status);
 399 #else
 400 #define ni_pcidio_print_flags(x)
 401 #define ni_pcidio_print_status(x)
 402 #endif
 403
 404 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 405 {
 406         unsigned long flags;
 407
 408         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 409         BUG_ON(devpriv->di_mite_chan);
 410         devpriv->di_mite_chan =
 411             mite_request_channel_in_range(devpriv->mite,
 412                                           devpriv->di_mite_ring, 1, 2);
 413         if (devpriv->di_mite_chan == NULL) {
 414                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 415                 comedi_error(dev, "failed to reserve mite dma channel.");
 416                 return -EBUSY;
 417         }
 418         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 419         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 420                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 421                devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 422         mmiowb();
 423         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 424         return 0;
 425 }
 426
 427 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 428 {
 429         unsigned long flags;
 430
 431         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 432         if (devpriv->di_mite_chan) {
 433                 mite_dma_disarm(devpriv->di_mite_chan);
 434                 mite_dma_reset(devpriv->di_mite_chan);
 435                 mite_release_channel(devpriv->di_mite_chan);
 436                 devpriv->di_mite_chan = NULL;
 437                 writeb(primary_DMAChannel_bits(0) |
 438                        secondary_DMAChannel_bits(0),
 439                        devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 440                 mmiowb();
 441         }
 442         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 443 }
 444
 445 static int nidio96_8255_cb(int dir, int port, int data, unsigned long iobase)
 446 {
 447         if (dir) {
 448                 writeb(data, (void *)(iobase + port));
 449                 return 0;
 450         } else {
 451                 return readb((void *)(iobase + port));
 452         }
 453 }
 454
 455 void ni_pcidio_event(struct comedi_device *dev, struct comedi_subdevice *s)
 456 {
 457         if (s->
 458             async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
 459                              COMEDI_CB_OVERFLOW)) {
 460                 ni_pcidio_cancel(dev, s);
 461         }
 462         comedi_event(dev, s);
 463 }
 464
 465 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 466 {
 467         unsigned long irq_flags;
 468         int count;
 469
 470         spin_lock_irqsave(&dev->spinlock, irq_flags);
 471         spin_lock(&devpriv->mite_channel_lock);
 472         if (devpriv->di_mite_chan)
 473                 mite_sync_input_dma(devpriv->di_mite_chan, s->async);
 474         spin_unlock(&devpriv->mite_channel_lock);
 475         count = s->async->buf_write_count - s->async->buf_read_count;
 476         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 477         return count;
 478 }
 479
 480 static irqreturn_t nidio_interrupt(int irq, void *d)
 481 {
 482         struct comedi_device *dev = d;
 483         struct comedi_subdevice *s = dev->subdevices;
 484         struct comedi_async *async = s->async;
 485         struct mite_struct *mite = devpriv->mite;
 486
 487         /* int i, j; */
 488         long int AuxData = 0;
 489         short data1 = 0;
 490         short data2 = 0;
 491         int flags;
 492         int status;
 493         int work = 0;
 494         unsigned int m_status = 0;
 495
 496         /* interrupcions parasites */
 497         if (dev->attached == 0) {
 498                 /* assume it's from another card */
 499                 return IRQ_NONE;
 500         }
 501
 502         /* Lock to avoid race with comedi_poll */
 503         spin_lock(&dev->spinlock);
 504
 505         status = readb(devpriv->mite->daq_io_addr +
 506                        Interrupt_And_Window_Status);
 507         flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 508
 509         DPRINTK("ni_pcidio_interrupt: status=0x%02x,flags=0x%02x\n",
 510                 status, flags);
 511         ni_pcidio_print_flags(flags);
 512         ni_pcidio_print_status(status);
 513
 514         /* printk("buf[0]=%08x\n",*(unsigned int *)async->prealloc_buf); */
 515         /* printk("buf[4096]=%08x\n",
 516                *(unsigned int *)(async->prealloc_buf+4096)); */
 517
 518         spin_lock(&devpriv->mite_channel_lock);
 519         if (devpriv->di_mite_chan)
 520                 m_status = mite_get_status(devpriv->di_mite_chan);
 521 #ifdef MITE_DEBUG
 522         mite_print_chsr(m_status);
 523 #endif
 524         /* printk("mite_bytes_transferred: %d\n",
 525                mite_bytes_transferred(mite,DI_DMA_CHAN)); */
 526
 527         /* mite_dump_regs(mite); */
 528         if (m_status & CHSR_INT) {
 529                 if (m_status & CHSR_LINKC) {
 530                         writel(CHOR_CLRLC,
 531                                mite->mite_io_addr +
 532                                MITE_CHOR(devpriv->di_mite_chan->channel));
 533                         mite_sync_input_dma(devpriv->di_mite_chan, s->async);
 534                         /* XXX need to byteswap */
 535                 }
 536                 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
 537                                  CHSR_DRQ1 | CHSR_MRDY)) {
 538                         DPRINTK("unknown mite interrupt, disabling IRQ\n");
 539                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 540                         disable_irq(dev->irq);
 541                 }
 542         }
 543         spin_unlock(&devpriv->mite_channel_lock);
 544
 545         while (status & DataLeft) {
 546                 work++;
 547                 if (work > 20) {
 548                         DPRINTK("too much work in interrupt\n");
 549                         writeb(0x00,
 550                                devpriv->mite->daq_io_addr +
 551                                Master_DMA_And_Interrupt_Control);
 552                         break;
 553                 }
 554
 555                 flags &= IntEn;
 556
 557                 if (flags & TransferReady) {
 558                         /* DPRINTK("TransferReady\n"); */
 559                         while (flags & TransferReady) {
 560                                 work++;
 561                                 if (work > 100) {
 562                                         DPRINTK("too much work in interrupt\n");
 563                                         writeb(0x00,
 564                                                devpriv->mite->daq_io_addr +
 565                                                Master_DMA_And_Interrupt_Control
 566                                               );
 567                                         goto out;
 568                                 }
 569                                 AuxData =
 570                                     readl(devpriv->mite->daq_io_addr +
 571                                           Group_1_FIFO);
 572                                 data1 = AuxData & 0xffff;
 573                                 data2 = (AuxData & 0xffff0000) >> 16;
 574                                 comedi_buf_put(async, data1);
 575                                 comedi_buf_put(async, data2);
 576                                 /* DPRINTK("read:%d, %d\n",data1,data2); */
 577                                 flags = readb(devpriv->mite->daq_io_addr +
 578                                               Group_1_Flags);
 579                         }
 580                         /* DPRINTK("buf_int_count: %d\n",
 581                                 async->buf_int_count); */
 582                         /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",
 583                                 IntEn,flags,status); */
 584                         /* ni_pcidio_print_flags(flags); */
 585                         /* ni_pcidio_print_status(status); */
 586                         async->events |= COMEDI_CB_BLOCK;
 587                 }
 588
 589                 if (flags & CountExpired) {
 590                         DPRINTK("CountExpired\n");
 591                         writeb(ClearExpired,
 592                                devpriv->mite->daq_io_addr +
 593                                Group_1_Second_Clear);
 594                         async->events |= COMEDI_CB_EOA;
 595
 596                         writeb(0x00, devpriv->mite->daq_io_addr + OpMode);
 597                         break;
 598                 } else if (flags & Waited) {
 599                         DPRINTK("Waited\n");
 600                         writeb(ClearWaited,
 601                                devpriv->mite->daq_io_addr +
 602                                Group_1_First_Clear);
 603                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 604                         break;
 605                 } else if (flags & PrimaryTC) {
 606                         DPRINTK("PrimaryTC\n");
 607                         writeb(ClearPrimaryTC,
 608                                devpriv->mite->daq_io_addr +
 609                                Group_1_First_Clear);
 610                         async->events |= COMEDI_CB_EOA;
 611                 } else if (flags & SecondaryTC) {
 612                         DPRINTK("SecondaryTC\n");
 613                         writeb(ClearSecondaryTC,
 614                                devpriv->mite->daq_io_addr +
 615                                Group_1_First_Clear);
 616                         async->events |= COMEDI_CB_EOA;
 617                 }
 618 #if 0
 619                 else {
 620                         printk("ni_pcidio: unknown interrupt\n");
 621                         async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 622                         writeb(0x00,
 623                                devpriv->mite->daq_io_addr +
 624                                Master_DMA_And_Interrupt_Control);
 625                 }
 626 #endif
 627                 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 628                 status = readb(devpriv->mite->daq_io_addr +
 629                                Interrupt_And_Window_Status);
 630                 /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,"
 631                         "status=0x%02x\n", IntEn, flags, status); */
 632                 /* ni_pcidio_print_flags(flags); */
 633                 /* ni_pcidio_print_status(status); */
 634         }
 635
 636 out:
 637         ni_pcidio_event(dev, s);
 638 #if 0
 639         if (!tag) {
 640                 writeb(0x03,
 641                        devpriv->mite->daq_io_addr +
 642                        Master_DMA_And_Interrupt_Control);
 643         }
 644 #endif
 645
 646         spin_unlock(&dev->spinlock);
 647         return IRQ_HANDLED;
 648 }
 649
 650 #ifdef DEBUG_FLAGS
 651 static const char *const flags_strings[] = {
 652         "TransferReady", "CountExpired", "2", "3",
 653         "4", "Waited", "PrimaryTC", "SecondaryTC",
 654 };
 655
 656 static void ni_pcidio_print_flags(unsigned int flags)
 657 {
 658         int i;
 659
 660         printk(KERN_INFO "group_1_flags:");
 661         for (i = 7; i >= 0; i--) {
 662                 if (flags & (1 << i))
 663                         printk(" %s", flags_strings[i]);
 664         }
 665         printk("\n");
 666 }
 667
 668 static char *status_strings[] = {
 669         "DataLeft1", "Reserved1", "Req1", "StopTrig1",
 670         "DataLeft2", "Reserved2", "Req2", "StopTrig2",
 671 };
 672
 673 static void ni_pcidio_print_status(unsigned int flags)
 674 {
 675         int i;
 676
 677         printk(KERN_INFO "group_status:");
 678         for (i = 7; i >= 0; i--) {
 679                 if (flags & (1 << i))
 680                         printk(" %s", status_strings[i]);
 681         }
 682         printk("\n");
 683 }
 684 #endif
 685
 686 #ifdef unused
 687 static void debug_int(struct comedi_device *dev)
 688 {
 689         int a, b;
 690         static int n_int;
 691         struct timeval tv;
 692
 693         do_gettimeofday(&tv);
 694         a = readb(devpriv->mite->daq_io_addr + Group_Status);
 695         b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 696
 697         if (n_int < 10) {
 698                 DPRINTK("status 0x%02x flags 0x%02x time %06d\n", a, b,
 699                         (int)tv.tv_usec);
 700         }
 701
 702         while (b & 1) {
 703                 writew(0xff, devpriv->mite->daq_io_addr + Group_1_FIFO);
 704                 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 705         }
 706
 707         b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 708
 709         if (n_int < 10) {
 710                 DPRINTK("new status 0x%02x\n", b);
 711                 n_int++;
 712         }
 713 }
 714 #endif
 715
 716 static int ni_pcidio_insn_config(struct comedi_device *dev,
 717                                  struct comedi_subdevice *s,
 718                                  struct comedi_insn *insn, unsigned int *data)
 719 {
 720         if (insn->n != 1)
 721                 return -EINVAL;
 722         switch (data[0]) {
 723         case INSN_CONFIG_DIO_OUTPUT:
 724                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
 725                 break;
 726         case INSN_CONFIG_DIO_INPUT:
 727                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
 728                 break;
 729         case INSN_CONFIG_DIO_QUERY:
 730                 data[1] =
 731                     (s->
 732                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
 733                     COMEDI_INPUT;
 734                 return insn->n;
 735                 break;
 736         default:
 737                 return -EINVAL;
 738         }
 739         writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
 740
 741         return 1;
 742 }
 743
 744 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 745                                struct comedi_subdevice *s,
 746                                struct comedi_insn *insn, unsigned int *data)
 747 {
 748         if (data[0]) {
 749                 s->state &= ~data[0];
 750                 s->state |= (data[0] & data[1]);
 751                 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0));
 752         }
 753         data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0));
 754
 755         return insn->n;
 756 }
 757
 758 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 759                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 760 {
 761         int err = 0;
 762         int tmp;
 763
 764         /* step 1: make sure trigger sources are trivially valid */
 765
 766         tmp = cmd->start_src;
 767         cmd->start_src &= TRIG_NOW | TRIG_INT;
 768         if (!cmd->start_src || tmp != cmd->start_src)
 769                 err++;
 770
 771         tmp = cmd->scan_begin_src;
 772         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
 773         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
 774                 err++;
 775
 776         tmp = cmd->convert_src;
 777         cmd->convert_src &= TRIG_NOW;
 778         if (!cmd->convert_src || tmp != cmd->convert_src)
 779                 err++;
 780
 781         tmp = cmd->scan_end_src;
 782         cmd->scan_end_src &= TRIG_COUNT;
 783         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
 784                 err++;
 785
 786         tmp = cmd->stop_src;
 787         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
 788         if (!cmd->stop_src || tmp != cmd->stop_src)
 789                 err++;
 790
 791         if (err)
 792                 return 1;
 793
 794         /* step 2: make sure trigger sources are unique and mutually
 795         compatible */
 796
 797         /* note that mutual compatibility is not an issue here */
 798         if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_INT)
 799                 err++;
 800         if (cmd->scan_begin_src != TRIG_TIMER &&
 801             cmd->scan_begin_src != TRIG_EXT)
 802                 err++;
 803
 804         if (err)
 805                 return 2;
 806
 807         /* step 3: make sure arguments are trivially compatible */
 808
 809         if (cmd->start_arg != 0) {
 810                 /* same for both TRIG_INT and TRIG_NOW */
 811                 cmd->start_arg = 0;
 812                 err++;
 813         }
 814 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 815
 816         if (cmd->scan_begin_src == TRIG_TIMER) {
 817                 if (cmd->scan_begin_arg < MAX_SPEED) {
 818                         cmd->scan_begin_arg = MAX_SPEED;
 819                         err++;
 820                 }
 821                 /* no minimum speed */
 822         } else {
 823                 /* TRIG_EXT */
 824                 /* should be level/edge, hi/lo specification here */
 825                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 826                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 827                         err++;
 828                 }
 829         }
 830         if (cmd->convert_arg != 0) {
 831                 cmd->convert_arg = 0;
 832                 err++;
 833         }
 834
 835         if (cmd->scan_end_arg != cmd->chanlist_len) {
 836                 cmd->scan_end_arg = cmd->chanlist_len;
 837                 err++;
 838         }
 839         if (cmd->stop_src == TRIG_COUNT) {
 840                 /* no limit */
 841         } else {
 842                 /* TRIG_NONE */
 843                 if (cmd->stop_arg != 0) {
 844                         cmd->stop_arg = 0;
 845                         err++;
 846                 }
 847         }
 848
 849         if (err)
 850                 return 3;
 851
 852         /* step 4: fix up any arguments */
 853
 854         if (cmd->scan_begin_src == TRIG_TIMER) {
 855                 tmp = cmd->scan_begin_arg;
 856                 ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 857                                       cmd->flags & TRIG_ROUND_MASK);
 858                 if (tmp != cmd->scan_begin_arg)
 859                         err++;
 860         }
 861
 862         if (err)
 863                 return 4;
 864
 865         return 0;
 866 }
 867
 868 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode)
 869 {
 870         int divider, base;
 871
 872         base = TIMER_BASE;
 873
 874         switch (round_mode) {
 875         case TRIG_ROUND_NEAREST:
 876         default:
 877                 divider = (*nanosec + base / 2) / base;
 878                 break;
 879         case TRIG_ROUND_DOWN:
 880                 divider = (*nanosec) / base;
 881                 break;
 882         case TRIG_ROUND_UP:
 883                 divider = (*nanosec + base - 1) / base;
 884                 break;
 885         }
 886
 887         *nanosec = base * divider;
 888         return divider;
 889 }
 890
 891 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 892 {
 893         struct comedi_cmd *cmd = &s->async->cmd;
 894
 895         /* XXX configure ports for input */
 896         writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
 897
 898         if (1) {
 899                 /* enable fifos A B C D */
 900                 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path);
 901
 902                 /* set transfer width a 32 bits */
 903                 writeb(TransferWidth(0) | TransferLength(0),
 904                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
 905         } else {
 906                 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path);
 907                 writeb(TransferWidth(3) | TransferLength(0),
 908                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
 909         }
 910
 911         /* protocol configuration */
 912         if (cmd->scan_begin_src == TRIG_TIMER) {
 913                 /* page 4-5, "input with internal REQs" */
 914                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
 915                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
 916                 writeb(1, devpriv->mite->daq_io_addr + Sequence);
 917                 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg);
 918                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
 919                 writeb(3, devpriv->mite->daq_io_addr + LinePolarities);
 920                 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer);
 921                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 922                                              TRIG_ROUND_NEAREST),
 923                        devpriv->mite->daq_io_addr + StartDelay);
 924                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
 925                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
 926                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
 927                 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay);
 928                 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay);
 929                 /* manual, page 4-5: ClockSpeed comment is incorrectly listed
 930                  * on DAQOptions */
 931                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
 932                 writeb(0, devpriv->mite->daq_io_addr + DAQOptions);
 933         } else {
 934                 /* TRIG_EXT */
 935                 /* page 4-5, "input with external REQs" */
 936                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
 937                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
 938                 writeb(0, devpriv->mite->daq_io_addr + Sequence);
 939                 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg);
 940                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
 941                 if (!(cmd->scan_begin_arg & CR_INVERT)) {
 942                         /* Leading Edge pulse mode */
 943                         writeb(0, devpriv->mite->daq_io_addr + LinePolarities);
 944                 } else {
 945                         /* Trailing Edge pulse mode */
 946                         writeb(2, devpriv->mite->daq_io_addr + LinePolarities);
 947                 }
 948                 writeb(0x00, devpriv->mite->daq_io_addr + AckSer);
 949                 writel(1, devpriv->mite->daq_io_addr + StartDelay);
 950                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
 951                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
 952                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
 953                 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay);
 954                 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay);
 955                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
 956                 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions);
 957         }
 958
 959         if (cmd->stop_src == TRIG_COUNT) {
 960                 writel(cmd->stop_arg,
 961                        devpriv->mite->daq_io_addr + Transfer_Count);
 962         } else {
 963                 /* XXX */
 964         }
 965
 966 #ifdef USE_DMA
 967         writeb(ClearPrimaryTC | ClearSecondaryTC,
 968                devpriv->mite->daq_io_addr + Group_1_First_Clear);
 969
 970         {
 971                 int retval = setup_mite_dma(dev, s);
 972                 if (retval)
 973                         return retval;
 974         }
 975 #else
 976         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 977 #endif
 978         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2);
 979
 980         /* clear and enable interrupts */
 981         writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear);
 982         /* writeb(ClearExpired,
 983                devpriv->mite->daq_io_addr+Group_1_Second_Clear); */
 984
 985         writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control);
 986         writeb(0x03,
 987                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
 988
 989         if (cmd->stop_src == TRIG_NONE) {
 990                 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
 991         } else {                /* TRIG_TIMER */
 992                 devpriv->OpModeBits = Numbered | RunMode(7);
 993         }
 994         if (cmd->start_src == TRIG_NOW) {
 995                 /* start */
 996                 writeb(devpriv->OpModeBits,
 997                        devpriv->mite->daq_io_addr + OpMode);
 998                 s->async->inttrig = NULL;
 999         } else {
1000                 /* TRIG_INT */
1001                 s->async->inttrig = ni_pcidio_inttrig;
1002         }
1003
1004         DPRINTK("ni_pcidio: command started\n");
1005         return 0;
1006 }
1007
1008 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
1009 {
1010         int retval;
1011         unsigned long flags;
1012
1013         retval = ni_pcidio_request_di_mite_channel(dev);
1014         if (retval)
1015                 return retval;
1016
1017         /* write alloc the entire buffer */
1018         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1019
1020         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1021         if (devpriv->di_mite_chan) {
1022                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
1023                 mite_dma_arm(devpriv->di_mite_chan);
1024         } else
1025                 retval = -EIO;
1026         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1027
1028         return retval;
1029 }
1030
1031 static int ni_pcidio_inttrig(struct comedi_device *dev,
1032                              struct comedi_subdevice *s, unsigned int trignum)
1033 {
1034         if (trignum != 0)
1035                 return -EINVAL;
1036
1037         writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode);
1038         s->async->inttrig = NULL;
1039
1040         return 1;
1041 }
1042
1043 static int ni_pcidio_cancel(struct comedi_device *dev,
1044                             struct comedi_subdevice *s)
1045 {
1046         writeb(0x00,
1047                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
1048         ni_pcidio_release_di_mite_channel(dev);
1049
1050         return 0;
1051 }
1052
1053 static int ni_pcidio_change(struct comedi_device *dev,
1054                             struct comedi_subdevice *s, unsigned long new_size)
1055 {
1056         int ret;
1057
1058         ret = mite_buf_change(devpriv->di_mite_ring, s->async);
1059         if (ret < 0)
1060                 return ret;
1061
1062         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
1063
1064         return 0;
1065 }
1066
1067 static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index,
1068                               u8 *data, int data_len)
1069 {
1070         static const int timeout = 1000;
1071         int i, j;
1072         writew(0x80 | fpga_index,
1073                devpriv->mite->daq_io_addr + Firmware_Control_Register);
1074         writew(0xc0 | fpga_index,
1075                devpriv->mite->daq_io_addr + Firmware_Control_Register);
1076         for (i = 0;
1077              (readw(devpriv->mite->daq_io_addr +
1078                     Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) {
1079                 udelay(1);
1080         }
1081         if (i == timeout) {
1082                 printk(KERN_WARNING "ni_pcidio: failed to load fpga %i, "
1083                        "waiting for status 0x2\n", fpga_index);
1084                 return -EIO;
1085         }
1086         writew(0x80 | fpga_index,
1087                devpriv->mite->daq_io_addr + Firmware_Control_Register);
1088         for (i = 0;
1089              readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) !=
1090              0x3 && i < timeout; ++i) {
1091                 udelay(1);
1092         }
1093         if (i == timeout) {
1094                 printk(KERN_WARNING "ni_pcidio: failed to load fpga %i, "
1095                        "waiting for status 0x3\n", fpga_index);
1096                 return -EIO;
1097         }
1098         for (j = 0; j + 1 < data_len;) {
1099                 unsigned int value = data[j++];
1100                 value |= data[j++] << 8;
1101                 writew(value,
1102                        devpriv->mite->daq_io_addr + Firmware_Data_Register);
1103                 for (i = 0;
1104                      (readw(devpriv->mite->daq_io_addr +
1105                             Firmware_Status_Register) & 0x2) == 0
1106                      && i < timeout; ++i) {
1107                         udelay(1);
1108                 }
1109                 if (i == timeout) {
1110                         printk("ni_pcidio: failed to load word into fpga %i\n",
1111                                fpga_index);
1112                         return -EIO;
1113                 }
1114                 if (need_resched())
1115                         schedule();
1116         }
1117         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1118         return 0;
1119 }
1120
1121 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
1122 {
1123         return pci_6534_load_fpga(dev, fpga_index, NULL, 0);
1124 }
1125
1126 static int pci_6534_reset_fpgas(struct comedi_device *dev)
1127 {
1128         int ret;
1129         int i;
1130         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1131         for (i = 0; i < 3; ++i) {
1132                 ret = pci_6534_reset_fpga(dev, i);
1133                 if (ret < 0)
1134                         break;
1135         }
1136         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register);
1137         return ret;
1138 }
1139
1140 static void pci_6534_init_main_fpga(struct comedi_device *dev)
1141 {
1142         writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register);
1143         writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register);
1144         writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register);
1145         writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register);
1146         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register);
1147         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register);
1148 }
1149
1150 static int pci_6534_upload_firmware(struct comedi_device *dev, int options[])
1151 {
1152         int ret;
1153         void *main_fpga_data, *scarab_a_data, *scarab_b_data;
1154         int main_fpga_data_len, scarab_a_data_len, scarab_b_data_len;
1155
1156         if (options[COMEDI_DEVCONF_AUX_DATA_LENGTH] == 0)
1157                 return 0;
1158         ret = pci_6534_reset_fpgas(dev);
1159         if (ret < 0)
1160                 return ret;
1161         main_fpga_data = comedi_aux_data(options, 0);
1162         main_fpga_data_len = options[COMEDI_DEVCONF_AUX_DATA0_LENGTH];
1163         ret = pci_6534_load_fpga(dev, 2, main_fpga_data, main_fpga_data_len);
1164         if (ret < 0)
1165                 return ret;
1166         pci_6534_init_main_fpga(dev);
1167         scarab_a_data = comedi_aux_data(options, 1);
1168         scarab_a_data_len = options[COMEDI_DEVCONF_AUX_DATA1_LENGTH];
1169         ret = pci_6534_load_fpga(dev, 0, scarab_a_data, scarab_a_data_len);
1170         if (ret < 0)
1171                 return ret;
1172         scarab_b_data = comedi_aux_data(options, 2);
1173         scarab_b_data_len = options[COMEDI_DEVCONF_AUX_DATA2_LENGTH];
1174         ret = pci_6534_load_fpga(dev, 1, scarab_b_data, scarab_b_data_len);
1175         if (ret < 0)
1176                 return ret;
1177         return 0;
1178 }
1179
1180 static int nidio_find_device(struct comedi_device *dev, int bus, int slot)
1181 {
1182         struct mite_struct *mite;
1183         int i;
1184
1185         for (mite = mite_devices; mite; mite = mite->next) {
1186                 if (mite->used)
1187                         continue;
1188                 if (bus || slot) {
1189                         if (bus != mite->pcidev->bus->number ||
1190                             slot != PCI_SLOT(mite->pcidev->devfn))
1191                                 continue;
1192                 }
1193                 for (i = 0; i < n_nidio_boards; i++) {
1194                         if (mite_device_id(mite) == nidio_boards[i].dev_id) {
1195                                 dev->board_ptr = nidio_boards + i;
1196                                 devpriv->mite = mite;
1197
1198                                 return 0;
1199                         }
1200                 }
1201         }
1202         printk(KERN_WARNING "no device found\n");
1203         mite_list_devices();
1204         return -EIO;
1205 }
1206
1207 static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1208 {
1209         struct comedi_subdevice *s;
1210         int i;
1211         int ret;
1212         int n_subdevices;
1213         unsigned int irq;
1214
1215         printk(KERN_INFO "comedi%d: nidio:", dev->minor);
1216
1217         ret = alloc_private(dev, sizeof(struct nidio96_private));
1218         if (ret < 0)
1219                 return ret;
1220         spin_lock_init(&devpriv->mite_channel_lock);
1221
1222         ret = nidio_find_device(dev, it->options[0], it->options[1]);
1223         if (ret < 0)
1224                 return ret;
1225
1226         ret = mite_setup(devpriv->mite);
1227         if (ret < 0) {
1228                 printk(KERN_WARNING "error setting up mite\n");
1229                 return ret;
1230         }
1231         comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1232         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
1233         if (devpriv->di_mite_ring == NULL)
1234                 return -ENOMEM;
1235
1236         dev->board_name = this_board->name;
1237         irq = mite_irq(devpriv->mite);
1238         printk(KERN_INFO " %s", dev->board_name);
1239         if (this_board->uses_firmware) {
1240                 ret = pci_6534_upload_firmware(dev, it->options);
1241                 if (ret < 0)
1242                         return ret;
1243         }
1244         if (!this_board->is_diodaq)
1245                 n_subdevices = this_board->n_8255;
1246         else
1247                 n_subdevices = 1;
1248
1249         ret = comedi_alloc_subdevices(dev, n_subdevices);
1250         if (ret)
1251                 return ret;
1252
1253         if (!this_board->is_diodaq) {
1254                 for (i = 0; i < this_board->n_8255; i++) {
1255                         subdev_8255_init(dev, dev->subdevices + i,
1256                                          nidio96_8255_cb,
1257                                          (unsigned long)(devpriv->mite->
1258                                                          daq_io_addr +
1259                                                          NIDIO_8255_BASE(i)));
1260                 }
1261         } else {
1262
1263                 printk(KERN_INFO " rev=%d",
1264                        readb(devpriv->mite->daq_io_addr + Chip_Version));
1265
1266                 s = dev->subdevices + 0;
1267
1268                 dev->read_subdev = s;
1269                 s->type = COMEDI_SUBD_DIO;
1270                 s->subdev_flags =
1271                     SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
1272                     SDF_CMD_READ;
1273                 s->n_chan = 32;
1274                 s->range_table = &range_digital;
1275                 s->maxdata = 1;
1276                 s->insn_config = &ni_pcidio_insn_config;
1277                 s->insn_bits = &ni_pcidio_insn_bits;
1278                 s->do_cmd = &ni_pcidio_cmd;
1279                 s->do_cmdtest = &ni_pcidio_cmdtest;
1280                 s->cancel = &ni_pcidio_cancel;
1281                 s->len_chanlist = 32;   /* XXX */
1282                 s->buf_change = &ni_pcidio_change;
1283                 s->async_dma_dir = DMA_BIDIRECTIONAL;
1284                 s->poll = &ni_pcidio_poll;
1285
1286                 writel(0, devpriv->mite->daq_io_addr + Port_IO(0));
1287                 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
1288                 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0));
1289
1290                 /* disable interrupts on board */
1291                 writeb(0x00,
1292                        devpriv->mite->daq_io_addr +
1293                        Master_DMA_And_Interrupt_Control);
1294
1295                 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
1296                                   "ni_pcidio", dev);
1297                 if (ret < 0)
1298                         printk(KERN_WARNING " irq not available");
1299
1300                 dev->irq = irq;
1301         }
1302
1303         printk("\n");
1304
1305         return 0;
1306 }
1307
1308 static void nidio_detach(struct comedi_device *dev)
1309 {
1310         int i;
1311
1312         if (this_board && !this_board->is_diodaq) {
1313                 for (i = 0; i < this_board->n_8255; i++)
1314                         subdev_8255_cleanup(dev, dev->subdevices + i);
1315         }
1316         if (dev->irq)
1317                 free_irq(dev->irq, dev);
1318         if (devpriv) {
1319                 if (devpriv->di_mite_ring) {
1320                         mite_free_ring(devpriv->di_mite_ring);
1321                         devpriv->di_mite_ring = NULL;
1322                 }
1323                 if (devpriv->mite)
1324                         mite_unsetup(devpriv->mite);
1325         }
1326 }
1327
1328 static struct comedi_driver ni_pcidio_driver = {
1329         .driver_name    = "ni_pcidio",
1330         .module         = THIS_MODULE,
1331         .attach         = nidio_attach,
1332         .detach         = nidio_detach,
1333 };
1334
1335 static int __devinit ni_pcidio_pci_probe(struct pci_dev *dev,
1336                                          const struct pci_device_id *ent)
1337 {
1338         return comedi_pci_auto_config(dev, &ni_pcidio_driver);
1339 }
1340
1341 static void __devexit ni_pcidio_pci_remove(struct pci_dev *dev)
1342 {
1343         comedi_pci_auto_unconfig(dev);
1344 }
1345
1346 static DEFINE_PCI_DEVICE_TABLE(ni_pcidio_pci_table) = {
1347         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1150) },
1348         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1320) },
1349         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x12b0) },
1350         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0160) },
1351         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1630) },
1352         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x13c0) },
1353         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0400) },
1354         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1250) },
1355         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x17d0) },
1356         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1800) },
1357         { 0 }
1358 };
1359 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1360
1361 static struct pci_driver ni_pcidio_pci_driver = {
1362         .name           = "ni_pcidio",
1363         .id_table       = ni_pcidio_pci_table,
1364         .probe          = ni_pcidio_pci_probe,
1365         .remove         = __devexit_p(ni_pcidio_pci_remove),
1366 };
1367 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1368
1369 MODULE_AUTHOR("Comedi http://www.comedi.org");
1370 MODULE_DESCRIPTION("Comedi low-level driver");
1371 MODULE_LICENSE("GPL");