drivers/staging/comedi/drivers/ni_pcidio.c

   1 /*
   2  * Comedi driver for National Instruments PCI-DIO-32HS
   3  *
   4  * COMEDI - Linux Control and Measurement Device Interface
   5  * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 /*
  19  * Driver: ni_pcidio
  20  * Description: National Instruments PCI-DIO32HS, PCI-6533
  21  * Author: ds
  22  * Status: works
  23  * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
  24  *   [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
  25  *   [National Instruments] PCI-6534 (pci-6534)
  26  * Updated: Mon, 09 Jan 2012 14:27:23 +0000
  27  *
  28  * The DIO32HS board appears as one subdevice, with 32 channels. Each
  29  * channel is individually I/O configurable. The channel order is 0=A0,
  30  * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
  31  * digital I/O; no handshaking is supported.
  32  *
  33  * DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  34  *
  35  * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  36  * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  37  * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  38  * trailing edge.
  39  *
  40  * This driver could be easily modified to support AT-MIO32HS and AT-MIO96.
  41  *
  42  * The PCI-6534 requires a firmware upload after power-up to work, the
  43  * firmware data and instructions for loading it with comedi_config
  44  * it are contained in the comedi_nonfree_firmware tarball available from
  45  * http://www.comedi.org
  46  */
  47
  48 #define USE_DMA
  49
  50 #include <linux/module.h>
  51 #include <linux/delay.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/sched.h>
  54
  55 #include "../comedi_pci.h"
  56
  57 #include "mite.h"
  58
  59 /* defines for the PCI-DIO-32HS */
  60
  61 #define Window_Address                  4       /* W */
  62 #define Interrupt_And_Window_Status     4       /* R */
  63 #define IntStatus1                              BIT(0)
  64 #define IntStatus2                              BIT(1)
  65 #define WindowAddressStatus_mask                0x7c
  66
  67 #define Master_DMA_And_Interrupt_Control 5      /* W */
  68 #define InterruptLine(x)                        ((x)&3)
  69 #define OpenInt                         BIT(2)
  70 #define Group_Status                    5       /* R */
  71 #define DataLeft                                BIT(0)
  72 #define Req                                     BIT(2)
  73 #define StopTrig                                BIT(3)
  74
  75 #define Group_1_Flags                   6       /* R */
  76 #define Group_2_Flags                   7       /* R */
  77 #define TransferReady                           BIT(0)
  78 #define CountExpired                            BIT(1)
  79 #define Waited                                  BIT(5)
  80 #define PrimaryTC                               BIT(6)
  81 #define SecondaryTC                             BIT(7)
  82   /* #define SerialRose */
  83   /* #define ReqRose */
  84   /* #define Paused */
  85
  86 #define Group_1_First_Clear             6       /* W */
  87 #define Group_2_First_Clear             7       /* W */
  88 #define ClearWaited                             BIT(3)
  89 #define ClearPrimaryTC                          BIT(4)
  90 #define ClearSecondaryTC                        BIT(5)
  91 #define DMAReset                                BIT(6)
  92 #define FIFOReset                               BIT(7)
  93 #define ClearAll                                0xf8
  94
  95 #define Group_1_FIFO                    8       /* W */
  96 #define Group_2_FIFO                    12      /* W */
  97
  98 #define Transfer_Count                  20
  99 #define Chip_ID_D                       24
 100 #define Chip_ID_I                       25
 101 #define Chip_ID_O                       26
 102 #define Chip_Version                    27
 103 #define Port_IO(x)                      (28+(x))
 104 #define Port_Pin_Directions(x)          (32+(x))
 105 #define Port_Pin_Mask(x)                (36+(x))
 106 #define Port_Pin_Polarities(x)          (40+(x))
 107
 108 #define Master_Clock_Routing            45
 109 #define RTSIClocking(x)                 (((x)&3)<<4)
 110
 111 #define Group_1_Second_Clear            46      /* W */
 112 #define Group_2_Second_Clear            47      /* W */
 113 #define ClearExpired                            BIT(0)
 114
 115 #define Port_Pattern(x)                 (48+(x))
 116
 117 #define Data_Path                       64
 118 #define FIFOEnableA             BIT(0)
 119 #define FIFOEnableB             BIT(1)
 120 #define FIFOEnableC             BIT(2)
 121 #define FIFOEnableD             BIT(3)
 122 #define Funneling(x)            (((x)&3)<<4)
 123 #define GroupDirection          BIT(7)
 124
 125 #define Protocol_Register_1             65
 126 #define OpMode                          Protocol_Register_1
 127 #define RunMode(x)              ((x)&7)
 128 #define Numbered                BIT(3)
 129
 130 #define Protocol_Register_2             66
 131 #define ClockReg                        Protocol_Register_2
 132 #define ClockLine(x)            (((x)&3)<<5)
 133 #define InvertStopTrig          BIT(7)
 134 #define DataLatching(x)       (((x)&3)<<5)
 135
 136 #define Protocol_Register_3             67
 137 #define Sequence                        Protocol_Register_3
 138
 139 #define Protocol_Register_14            68      /* 16 bit */
 140 #define ClockSpeed                      Protocol_Register_14
 141
 142 #define Protocol_Register_4             70
 143 #define ReqReg                          Protocol_Register_4
 144 #define ReqConditioning(x)      (((x)&7)<<3)
 145
 146 #define Protocol_Register_5             71
 147 #define BlockMode                       Protocol_Register_5
 148
 149 #define FIFO_Control                    72
 150 #define ReadyLevel(x)           ((x)&7)
 151
 152 #define Protocol_Register_6             73
 153 #define LinePolarities                  Protocol_Register_6
 154 #define InvertAck               BIT(0)
 155 #define InvertReq               BIT(1)
 156 #define InvertClock             BIT(2)
 157 #define InvertSerial            BIT(3)
 158 #define OpenAck         BIT(4)
 159 #define OpenClock               BIT(5)
 160
 161 #define Protocol_Register_7             74
 162 #define AckSer                          Protocol_Register_7
 163 #define AckLine(x)              (((x)&3)<<2)
 164 #define ExchangePins            BIT(7)
 165
 166 #define Interrupt_Control               75
 167   /* bits same as flags */
 168
 169 #define DMA_Line_Control_Group1         76
 170 #define DMA_Line_Control_Group2         108
 171 /* channel zero is none */
 172 static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
 173 {
 174         return channel & 0x3;
 175 }
 176
 177 static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
 178 {
 179         return (channel << 2) & 0xc;
 180 }
 181
 182 #define Transfer_Size_Control           77
 183 #define TransferWidth(x)        ((x)&3)
 184 #define TransferLength(x)       (((x)&3)<<3)
 185 #define RequireRLevel           BIT(5)
 186
 187 #define Protocol_Register_15            79
 188 #define DAQOptions                      Protocol_Register_15
 189 #define StartSource(x)                  ((x)&0x3)
 190 #define InvertStart                             BIT(2)
 191 #define StopSource(x)                           (((x)&0x3)<<3)
 192 #define ReqStart                                BIT(6)
 193 #define PreStart                                BIT(7)
 194
 195 #define Pattern_Detection               81
 196 #define DetectionMethod                 BIT(0)
 197 #define InvertMatch                             BIT(1)
 198 #define IE_Pattern_Detection                    BIT(2)
 199
 200 #define Protocol_Register_9             82
 201 #define ReqDelay                        Protocol_Register_9
 202
 203 #define Protocol_Register_10            83
 204 #define ReqNotDelay                     Protocol_Register_10
 205
 206 #define Protocol_Register_11            84
 207 #define AckDelay                        Protocol_Register_11
 208
 209 #define Protocol_Register_12            85
 210 #define AckNotDelay                     Protocol_Register_12
 211
 212 #define Protocol_Register_13            86
 213 #define Data1Delay                      Protocol_Register_13
 214
 215 #define Protocol_Register_8             88      /* 32 bit */
 216 #define StartDelay                      Protocol_Register_8
 217
 218 /* Firmware files for PCI-6524 */
 219 #define FW_PCI_6534_MAIN                "ni6534a.bin"
 220 #define FW_PCI_6534_SCARAB_DI           "niscrb01.bin"
 221 #define FW_PCI_6534_SCARAB_DO           "niscrb02.bin"
 222 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
 223 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
 224 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
 225
 226 enum pci_6534_firmware_registers {      /* 16 bit */
 227         Firmware_Control_Register = 0x100,
 228         Firmware_Status_Register = 0x104,
 229         Firmware_Data_Register = 0x108,
 230         Firmware_Mask_Register = 0x10c,
 231         Firmware_Debug_Register = 0x110,
 232 };
 233
 234 /* main fpga registers (32 bit)*/
 235 enum pci_6534_fpga_registers {
 236         FPGA_Control1_Register = 0x200,
 237         FPGA_Control2_Register = 0x204,
 238         FPGA_Irq_Mask_Register = 0x208,
 239         FPGA_Status_Register = 0x20c,
 240         FPGA_Signature_Register = 0x210,
 241         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 242         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 243         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 244         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 245         FPGA_Temp_Control_Register = 0x2a0,
 246         FPGA_DAR_Register = 0x2a8,
 247         FPGA_ELC_Read_Register = 0x2b8,
 248         FPGA_ELC_Write_Register = 0x2bc,
 249 };
 250
 251 enum FPGA_Control_Bits {
 252         FPGA_Enable_Bit = 0x8000,
 253 };
 254
 255 #define TIMER_BASE 50           /* nanoseconds */
 256
 257 #ifdef USE_DMA
 258 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
 259 #else
 260 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
 261 #endif
 262
 263 enum nidio_boardid {
 264         BOARD_PCIDIO_32HS,
 265         BOARD_PXI6533,
 266         BOARD_PCI6534,
 267 };
 268
 269 struct nidio_board {
 270         const char *name;
 271         unsigned int uses_firmware:1;
 272 };
 273
 274 static const struct nidio_board nidio_boards[] = {
 275         [BOARD_PCIDIO_32HS] = {
 276                 .name           = "pci-dio-32hs",
 277         },
 278         [BOARD_PXI6533] = {
 279                 .name           = "pxi-6533",
 280         },
 281         [BOARD_PCI6534] = {
 282                 .name           = "pci-6534",
 283                 .uses_firmware  = 1,
 284         },
 285 };
 286
 287 struct nidio96_private {
 288         struct mite *mite;
 289         int boardtype;
 290         int dio;
 291         unsigned short OpModeBits;
 292         struct mite_channel *di_mite_chan;
 293         struct mite_ring *di_mite_ring;
 294         spinlock_t mite_channel_lock;
 295 };
 296
 297 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 298 {
 299         struct nidio96_private *devpriv = dev->private;
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 303         BUG_ON(devpriv->di_mite_chan);
 304         devpriv->di_mite_chan =
 305             mite_request_channel_in_range(devpriv->mite,
 306                                           devpriv->di_mite_ring, 1, 2);
 307         if (!devpriv->di_mite_chan) {
 308                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 309                 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
 310                 return -EBUSY;
 311         }
 312         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 313         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 314                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 315                dev->mmio + DMA_Line_Control_Group1);
 316         mmiowb();
 317         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 318         return 0;
 319 }
 320
 321 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 322 {
 323         struct nidio96_private *devpriv = dev->private;
 324         unsigned long flags;
 325
 326         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 327         if (devpriv->di_mite_chan) {
 328                 mite_release_channel(devpriv->di_mite_chan);
 329                 devpriv->di_mite_chan = NULL;
 330                 writeb(primary_DMAChannel_bits(0) |
 331                        secondary_DMAChannel_bits(0),
 332                        dev->mmio + DMA_Line_Control_Group1);
 333                 mmiowb();
 334         }
 335         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 336 }
 337
 338 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
 339 {
 340         struct nidio96_private *devpriv = dev->private;
 341         int retval;
 342         unsigned long flags;
 343
 344         retval = ni_pcidio_request_di_mite_channel(dev);
 345         if (retval)
 346                 return retval;
 347
 348         /* write alloc the entire buffer */
 349         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
 350
 351         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 352         if (devpriv->di_mite_chan) {
 353                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
 354                 mite_dma_arm(devpriv->di_mite_chan);
 355         } else {
 356                 retval = -EIO;
 357         }
 358         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 359
 360         return retval;
 361 }
 362
 363 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 364 {
 365         struct nidio96_private *devpriv = dev->private;
 366         unsigned long irq_flags;
 367         int count;
 368
 369         spin_lock_irqsave(&dev->spinlock, irq_flags);
 370         spin_lock(&devpriv->mite_channel_lock);
 371         if (devpriv->di_mite_chan)
 372                 mite_sync_dma(devpriv->di_mite_chan, s);
 373         spin_unlock(&devpriv->mite_channel_lock);
 374         count = comedi_buf_n_bytes_ready(s);
 375         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 376         return count;
 377 }
 378
 379 static irqreturn_t nidio_interrupt(int irq, void *d)
 380 {
 381         struct comedi_device *dev = d;
 382         struct nidio96_private *devpriv = dev->private;
 383         struct comedi_subdevice *s = dev->read_subdev;
 384         struct comedi_async *async = s->async;
 385         unsigned int auxdata;
 386         int flags;
 387         int status;
 388         int work = 0;
 389
 390         /* interrupcions parasites */
 391         if (!dev->attached) {
 392                 /* assume it's from another card */
 393                 return IRQ_NONE;
 394         }
 395
 396         /* Lock to avoid race with comedi_poll */
 397         spin_lock(&dev->spinlock);
 398
 399         status = readb(dev->mmio + Interrupt_And_Window_Status);
 400         flags = readb(dev->mmio + Group_1_Flags);
 401
 402         spin_lock(&devpriv->mite_channel_lock);
 403         if (devpriv->di_mite_chan) {
 404                 mite_ack_linkc(devpriv->di_mite_chan, s, false);
 405                 /* XXX need to byteswap sync'ed dma */
 406         }
 407         spin_unlock(&devpriv->mite_channel_lock);
 408
 409         while (status & DataLeft) {
 410                 work++;
 411                 if (work > 20) {
 412                         dev_dbg(dev->class_dev, "too much work in interrupt\n");
 413                         writeb(0x00,
 414                                dev->mmio + Master_DMA_And_Interrupt_Control);
 415                         break;
 416                 }
 417
 418                 flags &= IntEn;
 419
 420                 if (flags & TransferReady) {
 421                         while (flags & TransferReady) {
 422                                 work++;
 423                                 if (work > 100) {
 424                                         dev_dbg(dev->class_dev,
 425                                                 "too much work in interrupt\n");
 426                                         writeb(0x00, dev->mmio +
 427                                                Master_DMA_And_Interrupt_Control
 428                                               );
 429                                         goto out;
 430                                 }
 431                                 auxdata = readl(dev->mmio + Group_1_FIFO);
 432                                 comedi_buf_write_samples(s, &auxdata, 1);
 433                                 flags = readb(dev->mmio + Group_1_Flags);
 434                         }
 435                 }
 436
 437                 if (flags & CountExpired) {
 438                         writeb(ClearExpired, dev->mmio + Group_1_Second_Clear);
 439                         async->events |= COMEDI_CB_EOA;
 440
 441                         writeb(0x00, dev->mmio + OpMode);
 442                         break;
 443                 } else if (flags & Waited) {
 444                         writeb(ClearWaited, dev->mmio + Group_1_First_Clear);
 445                         async->events |= COMEDI_CB_ERROR;
 446                         break;
 447                 } else if (flags & PrimaryTC) {
 448                         writeb(ClearPrimaryTC,
 449                                dev->mmio + Group_1_First_Clear);
 450                         async->events |= COMEDI_CB_EOA;
 451                 } else if (flags & SecondaryTC) {
 452                         writeb(ClearSecondaryTC,
 453                                dev->mmio + Group_1_First_Clear);
 454                         async->events |= COMEDI_CB_EOA;
 455                 }
 456
 457                 flags = readb(dev->mmio + Group_1_Flags);
 458                 status = readb(dev->mmio + Interrupt_And_Window_Status);
 459         }
 460
 461 out:
 462         comedi_handle_events(dev, s);
 463 #if 0
 464         if (!tag)
 465                 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
 466 #endif
 467
 468         spin_unlock(&dev->spinlock);
 469         return IRQ_HANDLED;
 470 }
 471
 472 static int ni_pcidio_insn_config(struct comedi_device *dev,
 473                                  struct comedi_subdevice *s,
 474                                  struct comedi_insn *insn,
 475                                  unsigned int *data)
 476 {
 477         int ret;
 478
 479         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
 480         if (ret)
 481                 return ret;
 482
 483         writel(s->io_bits, dev->mmio + Port_Pin_Directions(0));
 484
 485         return insn->n;
 486 }
 487
 488 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 489                                struct comedi_subdevice *s,
 490                                struct comedi_insn *insn,
 491                                unsigned int *data)
 492 {
 493         if (comedi_dio_update_state(s, data))
 494                 writel(s->state, dev->mmio + Port_IO(0));
 495
 496         data[1] = readl(dev->mmio + Port_IO(0));
 497
 498         return insn->n;
 499 }
 500
 501 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
 502 {
 503         int divider, base;
 504
 505         base = TIMER_BASE;
 506
 507         switch (flags & CMDF_ROUND_MASK) {
 508         case CMDF_ROUND_NEAREST:
 509         default:
 510                 divider = DIV_ROUND_CLOSEST(*nanosec, base);
 511                 break;
 512         case CMDF_ROUND_DOWN:
 513                 divider = (*nanosec) / base;
 514                 break;
 515         case CMDF_ROUND_UP:
 516                 divider = DIV_ROUND_UP(*nanosec, base);
 517                 break;
 518         }
 519
 520         *nanosec = base * divider;
 521         return divider;
 522 }
 523
 524 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 525                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 526 {
 527         int err = 0;
 528         unsigned int arg;
 529
 530         /* Step 1 : check if triggers are trivially valid */
 531
 532         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
 533         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
 534                                         TRIG_TIMER | TRIG_EXT);
 535         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 536         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 537         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 538
 539         if (err)
 540                 return 1;
 541
 542         /* Step 2a : make sure trigger sources are unique */
 543
 544         err |= comedi_check_trigger_is_unique(cmd->start_src);
 545         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
 546         err |= comedi_check_trigger_is_unique(cmd->stop_src);
 547
 548         /* Step 2b : and mutually compatible */
 549
 550         if (err)
 551                 return 2;
 552
 553         /* Step 3: check if arguments are trivially valid */
 554
 555         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 556
 557 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 558
 559         if (cmd->scan_begin_src == TRIG_TIMER) {
 560                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
 561                                                     MAX_SPEED);
 562                 /* no minimum speed */
 563         } else {
 564                 /* TRIG_EXT */
 565                 /* should be level/edge, hi/lo specification here */
 566                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 567                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 568                         err |= -EINVAL;
 569                 }
 570         }
 571
 572         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 573         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 574                                            cmd->chanlist_len);
 575
 576         if (cmd->stop_src == TRIG_COUNT)
 577                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
 578         else    /* TRIG_NONE */
 579                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 580
 581         if (err)
 582                 return 3;
 583
 584         /* step 4: fix up any arguments */
 585
 586         if (cmd->scan_begin_src == TRIG_TIMER) {
 587                 arg = cmd->scan_begin_arg;
 588                 ni_pcidio_ns_to_timer(&arg, cmd->flags);
 589                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
 590         }
 591
 592         if (err)
 593                 return 4;
 594
 595         return 0;
 596 }
 597
 598 static int ni_pcidio_inttrig(struct comedi_device *dev,
 599                              struct comedi_subdevice *s,
 600                              unsigned int trig_num)
 601 {
 602         struct nidio96_private *devpriv = dev->private;
 603         struct comedi_cmd *cmd = &s->async->cmd;
 604
 605         if (trig_num != cmd->start_arg)
 606                 return -EINVAL;
 607
 608         writeb(devpriv->OpModeBits, dev->mmio + OpMode);
 609         s->async->inttrig = NULL;
 610
 611         return 1;
 612 }
 613
 614 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 615 {
 616         struct nidio96_private *devpriv = dev->private;
 617         struct comedi_cmd *cmd = &s->async->cmd;
 618
 619         /* XXX configure ports for input */
 620         writel(0x0000, dev->mmio + Port_Pin_Directions(0));
 621
 622         if (1) {
 623                 /* enable fifos A B C D */
 624                 writeb(0x0f, dev->mmio + Data_Path);
 625
 626                 /* set transfer width a 32 bits */
 627                 writeb(TransferWidth(0) | TransferLength(0),
 628                        dev->mmio + Transfer_Size_Control);
 629         } else {
 630                 writeb(0x03, dev->mmio + Data_Path);
 631                 writeb(TransferWidth(3) | TransferLength(0),
 632                        dev->mmio + Transfer_Size_Control);
 633         }
 634
 635         /* protocol configuration */
 636         if (cmd->scan_begin_src == TRIG_TIMER) {
 637                 /* page 4-5, "input with internal REQs" */
 638                 writeb(0, dev->mmio + OpMode);
 639                 writeb(0x00, dev->mmio + ClockReg);
 640                 writeb(1, dev->mmio + Sequence);
 641                 writeb(0x04, dev->mmio + ReqReg);
 642                 writeb(4, dev->mmio + BlockMode);
 643                 writeb(3, dev->mmio + LinePolarities);
 644                 writeb(0xc0, dev->mmio + AckSer);
 645                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 646                                              CMDF_ROUND_NEAREST),
 647                        dev->mmio + StartDelay);
 648                 writeb(1, dev->mmio + ReqDelay);
 649                 writeb(1, dev->mmio + ReqNotDelay);
 650                 writeb(1, dev->mmio + AckDelay);
 651                 writeb(0x0b, dev->mmio + AckNotDelay);
 652                 writeb(0x01, dev->mmio + Data1Delay);
 653                 /*
 654                  * manual, page 4-5:
 655                  * ClockSpeed comment is incorrectly listed on DAQOptions
 656                  */
 657                 writew(0, dev->mmio + ClockSpeed);
 658                 writeb(0, dev->mmio + DAQOptions);
 659         } else {
 660                 /* TRIG_EXT */
 661                 /* page 4-5, "input with external REQs" */
 662                 writeb(0, dev->mmio + OpMode);
 663                 writeb(0x00, dev->mmio + ClockReg);
 664                 writeb(0, dev->mmio + Sequence);
 665                 writeb(0x00, dev->mmio + ReqReg);
 666                 writeb(4, dev->mmio + BlockMode);
 667                 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
 668                         writeb(0, dev->mmio + LinePolarities);
 669                 else                                    /* Trailing Edge */
 670                         writeb(2, dev->mmio + LinePolarities);
 671                 writeb(0x00, dev->mmio + AckSer);
 672                 writel(1, dev->mmio + StartDelay);
 673                 writeb(1, dev->mmio + ReqDelay);
 674                 writeb(1, dev->mmio + ReqNotDelay);
 675                 writeb(1, dev->mmio + AckDelay);
 676                 writeb(0x0C, dev->mmio + AckNotDelay);
 677                 writeb(0x10, dev->mmio + Data1Delay);
 678                 writew(0, dev->mmio + ClockSpeed);
 679                 writeb(0x60, dev->mmio + DAQOptions);
 680         }
 681
 682         if (cmd->stop_src == TRIG_COUNT) {
 683                 writel(cmd->stop_arg,
 684                        dev->mmio + Transfer_Count);
 685         } else {
 686                 /* XXX */
 687         }
 688
 689 #ifdef USE_DMA
 690         writeb(ClearPrimaryTC | ClearSecondaryTC,
 691                dev->mmio + Group_1_First_Clear);
 692
 693         {
 694                 int retval = setup_mite_dma(dev, s);
 695
 696                 if (retval)
 697                         return retval;
 698         }
 699 #else
 700         writeb(0x00, dev->mmio + DMA_Line_Control_Group1);
 701 #endif
 702         writeb(0x00, dev->mmio + DMA_Line_Control_Group2);
 703
 704         /* clear and enable interrupts */
 705         writeb(0xff, dev->mmio + Group_1_First_Clear);
 706         /* writeb(ClearExpired, dev->mmio+Group_1_Second_Clear); */
 707
 708         writeb(IntEn, dev->mmio + Interrupt_Control);
 709         writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
 710
 711         if (cmd->stop_src == TRIG_NONE) {
 712                 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
 713         } else {                /* TRIG_TIMER */
 714                 devpriv->OpModeBits = Numbered | RunMode(7);
 715         }
 716         if (cmd->start_src == TRIG_NOW) {
 717                 /* start */
 718                 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
 719                 s->async->inttrig = NULL;
 720         } else {
 721                 /* TRIG_INT */
 722                 s->async->inttrig = ni_pcidio_inttrig;
 723         }
 724
 725         return 0;
 726 }
 727
 728 static int ni_pcidio_cancel(struct comedi_device *dev,
 729                             struct comedi_subdevice *s)
 730 {
 731         writeb(0x00, dev->mmio + Master_DMA_And_Interrupt_Control);
 732         ni_pcidio_release_di_mite_channel(dev);
 733
 734         return 0;
 735 }
 736
 737 static int ni_pcidio_change(struct comedi_device *dev,
 738                             struct comedi_subdevice *s)
 739 {
 740         struct nidio96_private *devpriv = dev->private;
 741         int ret;
 742
 743         ret = mite_buf_change(devpriv->di_mite_ring, s);
 744         if (ret < 0)
 745                 return ret;
 746
 747         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
 748
 749         return 0;
 750 }
 751
 752 static int pci_6534_load_fpga(struct comedi_device *dev,
 753                               const u8 *data, size_t data_len,
 754                               unsigned long context)
 755 {
 756         static const int timeout = 1000;
 757         int fpga_index = context;
 758         int i;
 759         size_t j;
 760
 761         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 762         writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
 763         for (i = 0;
 764              (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
 765              i < timeout; ++i) {
 766                 udelay(1);
 767         }
 768         if (i == timeout) {
 769                 dev_warn(dev->class_dev,
 770                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
 771                          fpga_index);
 772                 return -EIO;
 773         }
 774         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 775         for (i = 0;
 776              readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
 777              i < timeout; ++i) {
 778                 udelay(1);
 779         }
 780         if (i == timeout) {
 781                 dev_warn(dev->class_dev,
 782                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
 783                          fpga_index);
 784                 return -EIO;
 785         }
 786         for (j = 0; j + 1 < data_len;) {
 787                 unsigned int value = data[j++];
 788
 789                 value |= data[j++] << 8;
 790                 writew(value, dev->mmio + Firmware_Data_Register);
 791                 for (i = 0;
 792                      (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
 793                      && i < timeout; ++i) {
 794                         udelay(1);
 795                 }
 796                 if (i == timeout) {
 797                         dev_warn(dev->class_dev,
 798                                  "ni_pcidio: failed to load word into fpga %i\n",
 799                                  fpga_index);
 800                         return -EIO;
 801                 }
 802                 if (need_resched())
 803                         schedule();
 804         }
 805         writew(0x0, dev->mmio + Firmware_Control_Register);
 806         return 0;
 807 }
 808
 809 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
 810 {
 811         return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
 812 }
 813
 814 static int pci_6534_reset_fpgas(struct comedi_device *dev)
 815 {
 816         int ret;
 817         int i;
 818
 819         writew(0x0, dev->mmio + Firmware_Control_Register);
 820         for (i = 0; i < 3; ++i) {
 821                 ret = pci_6534_reset_fpga(dev, i);
 822                 if (ret < 0)
 823                         break;
 824         }
 825         writew(0x0, dev->mmio + Firmware_Mask_Register);
 826         return ret;
 827 }
 828
 829 static void pci_6534_init_main_fpga(struct comedi_device *dev)
 830 {
 831         writel(0, dev->mmio + FPGA_Control1_Register);
 832         writel(0, dev->mmio + FPGA_Control2_Register);
 833         writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
 834         writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
 835         writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
 836         writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
 837 }
 838
 839 static int pci_6534_upload_firmware(struct comedi_device *dev)
 840 {
 841         struct nidio96_private *devpriv = dev->private;
 842         static const char *const fw_file[3] = {
 843                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
 844                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
 845                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
 846         };
 847         int ret;
 848         int n;
 849
 850         ret = pci_6534_reset_fpgas(dev);
 851         if (ret < 0)
 852                 return ret;
 853         /* load main FPGA first, then the two scarabs */
 854         for (n = 2; n >= 0; n--) {
 855                 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
 856                                            fw_file[n],
 857                                            pci_6534_load_fpga, n);
 858                 if (ret == 0 && n == 2)
 859                         pci_6534_init_main_fpga(dev);
 860                 if (ret < 0)
 861                         break;
 862         }
 863         return ret;
 864 }
 865
 866 static void nidio_reset_board(struct comedi_device *dev)
 867 {
 868         writel(0, dev->mmio + Port_IO(0));
 869         writel(0, dev->mmio + Port_Pin_Directions(0));
 870         writel(0, dev->mmio + Port_Pin_Mask(0));
 871
 872         /* disable interrupts on board */
 873         writeb(0, dev->mmio + Master_DMA_And_Interrupt_Control);
 874 }
 875
 876 static int nidio_auto_attach(struct comedi_device *dev,
 877                              unsigned long context)
 878 {
 879         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 880         const struct nidio_board *board = NULL;
 881         struct nidio96_private *devpriv;
 882         struct comedi_subdevice *s;
 883         int ret;
 884         unsigned int irq;
 885
 886         if (context < ARRAY_SIZE(nidio_boards))
 887                 board = &nidio_boards[context];
 888         if (!board)
 889                 return -ENODEV;
 890         dev->board_ptr = board;
 891         dev->board_name = board->name;
 892
 893         ret = comedi_pci_enable(dev);
 894         if (ret)
 895                 return ret;
 896
 897         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 898         if (!devpriv)
 899                 return -ENOMEM;
 900
 901         spin_lock_init(&devpriv->mite_channel_lock);
 902
 903         devpriv->mite = mite_attach(dev, false);        /* use win0 */
 904         if (!devpriv->mite)
 905                 return -ENOMEM;
 906
 907         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
 908         if (!devpriv->di_mite_ring)
 909                 return -ENOMEM;
 910
 911         if (board->uses_firmware) {
 912                 ret = pci_6534_upload_firmware(dev);
 913                 if (ret < 0)
 914                         return ret;
 915         }
 916
 917         nidio_reset_board(dev);
 918
 919         ret = comedi_alloc_subdevices(dev, 1);
 920         if (ret)
 921                 return ret;
 922
 923         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
 924                  readb(dev->mmio + Chip_Version));
 925
 926         s = &dev->subdevices[0];
 927
 928         dev->read_subdev = s;
 929         s->type = COMEDI_SUBD_DIO;
 930         s->subdev_flags =
 931                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
 932                 SDF_CMD_READ;
 933         s->n_chan = 32;
 934         s->range_table = &range_digital;
 935         s->maxdata = 1;
 936         s->insn_config = &ni_pcidio_insn_config;
 937         s->insn_bits = &ni_pcidio_insn_bits;
 938         s->do_cmd = &ni_pcidio_cmd;
 939         s->do_cmdtest = &ni_pcidio_cmdtest;
 940         s->cancel = &ni_pcidio_cancel;
 941         s->len_chanlist = 32;   /* XXX */
 942         s->buf_change = &ni_pcidio_change;
 943         s->async_dma_dir = DMA_BIDIRECTIONAL;
 944         s->poll = &ni_pcidio_poll;
 945
 946         irq = pcidev->irq;
 947         if (irq) {
 948                 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
 949                                   dev->board_name, dev);
 950                 if (ret == 0)
 951                         dev->irq = irq;
 952         }
 953
 954         return 0;
 955 }
 956
 957 static void nidio_detach(struct comedi_device *dev)
 958 {
 959         struct nidio96_private *devpriv = dev->private;
 960
 961         if (dev->irq)
 962                 free_irq(dev->irq, dev);
 963         if (devpriv) {
 964                 if (devpriv->di_mite_ring) {
 965                         mite_free_ring(devpriv->di_mite_ring);
 966                         devpriv->di_mite_ring = NULL;
 967                 }
 968                 mite_detach(devpriv->mite);
 969         }
 970         if (dev->mmio)
 971                 iounmap(dev->mmio);
 972         comedi_pci_disable(dev);
 973 }
 974
 975 static struct comedi_driver ni_pcidio_driver = {
 976         .driver_name    = "ni_pcidio",
 977         .module         = THIS_MODULE,
 978         .auto_attach    = nidio_auto_attach,
 979         .detach         = nidio_detach,
 980 };
 981
 982 static int ni_pcidio_pci_probe(struct pci_dev *dev,
 983                                const struct pci_device_id *id)
 984 {
 985         return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
 986 }
 987
 988 static const struct pci_device_id ni_pcidio_pci_table[] = {
 989         { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
 990         { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
 991         { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
 992         { 0 }
 993 };
 994 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
 995
 996 static struct pci_driver ni_pcidio_pci_driver = {
 997         .name           = "ni_pcidio",
 998         .id_table       = ni_pcidio_pci_table,
 999         .probe          = ni_pcidio_pci_probe,
1000         .remove         = comedi_pci_auto_unconfig,
1001 };
1002 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1003
1004 MODULE_AUTHOR("Comedi http://www.comedi.org");
1005 MODULE_DESCRIPTION("Comedi low-level driver");
1006 MODULE_LICENSE("GPL");