drivers/staging/comedi/drivers/ni_pcimio.c

   1 /*
   2     comedi/drivers/ni_pcimio.c
   3     Hardware driver for NI PCI-MIO E series cards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22 /*
  23 Driver: ni_pcimio
  24 Description: National Instruments PCI-MIO-E series and M series (all boards)
  25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
  26   Herman Bruyninckx, Terry Barnaby
  27 Status: works
  28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
  29   PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
  30   PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
  31   PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
  32   PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
  33   PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
  34   PCI-6254, PCI-6259, PCIe-6259,
  35   PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
  36   PCI-6711, PXI-6711, PCI-6713, PXI-6713,
  37   PXI-6071E, PCI-6070E, PXI-6070E,
  38   PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
  39   PCI-6143, PXI-6143
  40 Updated: Mon, 09 Jan 2012 14:52:48 +0000
  41
  42 These boards are almost identical to the AT-MIO E series, except that
  43 they use the PCI bus instead of ISA (i.e., AT).  See the notes for
  44 the ni_atmio.o driver for additional information about these boards.
  45
  46 Autocalibration is supported on many of the devices, using the
  47 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
  48 M-Series boards do analog input and analog output calibration entirely
  49 in software. The software calibration corrects
  50 the analog input for offset, gain and
  51 nonlinearity.  The analog outputs are corrected for offset and gain.
  52 See the comedilib documentation on comedi_get_softcal_converter() for
  53 more information.
  54
  55 By default, the driver uses DMA to transfer analog input data to
  56 memory.  When DMA is enabled, not all triggering features are
  57 supported.
  58
  59 Digital I/O may not work on 673x.
  60
  61 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
  62 With this board all of the convertors perform one simultaineous sample during
  63 a scan interval. The period for a scan is used for the convert time in a
  64 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
  65
  66 The RTSI trigger bus is supported on these cards on
  67 subdevice 10. See the comedilib documentation for details.
  68
  69 Information (number of channels, bits, etc.) for some devices may be
  70 incorrect.  Please check this and submit a bug if there are problems
  71 for your device.
  72
  73 SCXI is probably broken for m-series boards.
  74
  75 Bugs:
  76  - When DMA is enabled, COMEDI_EV_CONVERT does
  77    not work correctly.
  78
  79 */
  80 /*
  81         The PCI-MIO E series driver was originally written by
  82         Tomasz Motylewski <...>, and ported to comedi by ds.
  83
  84         References:
  85
  86            341079b.pdf  PCI E Series Register-Level Programmer Manual
  87            340934b.pdf  DAQ-STC reference manual
  88
  89            322080b.pdf  6711/6713/6715 User Manual
  90
  91            320945c.pdf  PCI E Series User Manual
  92            322138a.pdf  PCI-6052E and DAQPad-6052E User Manual
  93
  94         ISSUES:
  95
  96         need to deal with external reference for DAC, and other DAC
  97         properties in board properties
  98
  99         deal with at-mio-16de-10 revision D to N changes, etc.
 100
 101         need to add other CALDAC type
 102
 103         need to slow down DAC loading.  I don't trust NI's claim that
 104         two writes to the PCI bus slows IO enough.  I would prefer to
 105         use udelay().  Timing specs: (clock)
 106                 AD8522          30ns
 107                 DAC8043         120ns
 108                 DAC8800         60ns
 109                 MB88341         ?
 110
 111 */
 112
 113 #include <linux/delay.h>
 114 #include <linux/delay.h>
 115
 116 #include "../comedidev.h"
 117
 118 #include <asm/byteorder.h>
 119
 120 #include "ni_stc.h"
 121 #include "mite.h"
 122
 123 /* #define PCI_DEBUG */
 124
 125 #define PCIDMA
 126
 127 #define PCIMIO 1
 128 #undef ATMIO
 129
 130 #define MAX_N_CALDACS (16+16+2)
 131
 132 #define DRV_NAME "ni_pcimio"
 133
 134 /* These are not all the possible ao ranges for 628x boards.
 135  They can do OFFSET +- REFERENCE where OFFSET can be
 136  0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
 137  be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>.  That's
 138  63 different possibilities.  An AO channel
 139  can not act as it's own OFFSET or REFERENCE.
 140 */
 141 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
 142                                                              RANGE(-10, 10),
 143                                                              RANGE(-5, 5),
 144                                                              RANGE(-2, 2),
 145                                                              RANGE(-1, 1),
 146                                                              RANGE(-5, 15),
 147                                                              RANGE(0, 10),
 148                                                              RANGE(3, 7),
 149                                                              RANGE(4, 6),
 150                                                              RANGE_ext(-1, 1)
 151                                                              }
 152 };
 153
 154 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
 155                                                              RANGE(-10, 10),
 156                                                              RANGE(-5, 5),
 157                                                              RANGE_ext(-1, 1)
 158                                                              }
 159 };
 160
 161 static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
 162                                                              RANGE(-10, 10),
 163                                                              }
 164 };
 165
 166 static const struct ni_board_struct ni_boards[] = {
 167         {
 168          .device_id = 0x0162,   /*  NI also says 0x1620.  typo? */
 169          .name = "pci-mio-16xe-50",
 170          .n_adchan = 16,
 171          .adbits = 16,
 172          .ai_fifo_depth = 2048,
 173          .alwaysdither = 1,
 174          .gainlkup = ai_gain_8,
 175          .ai_speed = 50000,
 176          .n_aochan = 2,
 177          .aobits = 12,
 178          .ao_fifo_depth = 0,
 179          .ao_range_table = &range_bipolar10,
 180          .ao_unipolar = 0,
 181          .ao_speed = 50000,
 182          .num_p0_dio_channels = 8,
 183          .caldac = {dac8800, dac8043},
 184          .has_8255 = 0,
 185          },
 186         {
 187          .device_id = 0x1170,
 188          .name = "pci-mio-16xe-10",     /*  aka pci-6030E */
 189          .n_adchan = 16,
 190          .adbits = 16,
 191          .ai_fifo_depth = 512,
 192          .alwaysdither = 1,
 193          .gainlkup = ai_gain_14,
 194          .ai_speed = 10000,
 195          .n_aochan = 2,
 196          .aobits = 16,
 197          .ao_fifo_depth = 2048,
 198          .ao_range_table = &range_ni_E_ao_ext,
 199          .ao_unipolar = 1,
 200          .ao_speed = 10000,
 201          .num_p0_dio_channels = 8,
 202          .caldac = {dac8800, dac8043, ad8522},
 203          .has_8255 = 0,
 204          },
 205         {
 206          .device_id = 0x28c0,
 207          .name = "pci-6014",
 208          .n_adchan = 16,
 209          .adbits = 16,
 210          .ai_fifo_depth = 512,
 211          .alwaysdither = 1,
 212          .gainlkup = ai_gain_4,
 213          .ai_speed = 5000,
 214          .n_aochan = 2,
 215          .aobits = 16,
 216          .ao_fifo_depth = 0,
 217          .ao_range_table = &range_bipolar10,
 218          .ao_unipolar = 0,
 219          .ao_speed = 100000,
 220          .num_p0_dio_channels = 8,
 221          .caldac = {ad8804_debug},
 222          .has_8255 = 0,
 223          },
 224         {
 225          .device_id = 0x11d0,
 226          .name = "pxi-6030e",
 227          .n_adchan = 16,
 228          .adbits = 16,
 229          .ai_fifo_depth = 512,
 230          .alwaysdither = 1,
 231          .gainlkup = ai_gain_14,
 232          .ai_speed = 10000,
 233          .n_aochan = 2,
 234          .aobits = 16,
 235          .ao_fifo_depth = 2048,
 236          .ao_range_table = &range_ni_E_ao_ext,
 237          .ao_unipolar = 1,
 238          .ao_speed = 10000,
 239          .num_p0_dio_channels = 8,
 240          .caldac = {dac8800, dac8043, ad8522},
 241          .has_8255 = 0,
 242          },
 243         {
 244          .device_id = 0x1180,
 245          .name = "pci-mio-16e-1",       /* aka pci-6070e */
 246          .n_adchan = 16,
 247          .adbits = 12,
 248          .ai_fifo_depth = 512,
 249          .alwaysdither = 0,
 250          .gainlkup = ai_gain_16,
 251          .ai_speed = 800,
 252          .n_aochan = 2,
 253          .aobits = 12,
 254          .ao_fifo_depth = 2048,
 255          .ao_range_table = &range_ni_E_ao_ext,
 256          .ao_unipolar = 1,
 257          .ao_speed = 1000,
 258          .num_p0_dio_channels = 8,
 259          .caldac = {mb88341},
 260          .has_8255 = 0,
 261          },
 262         {
 263          .device_id = 0x1190,
 264          .name = "pci-mio-16e-4",       /* aka pci-6040e */
 265          .n_adchan = 16,
 266          .adbits = 12,
 267          .ai_fifo_depth = 512,
 268          .alwaysdither = 0,
 269          .gainlkup = ai_gain_16,
 270          /*      .Note = there have been reported problems with full speed
 271           * on this board */
 272          .ai_speed = 2000,
 273          .n_aochan = 2,
 274          .aobits = 12,
 275          .ao_fifo_depth = 512,
 276          .ao_range_table = &range_ni_E_ao_ext,
 277          .ao_unipolar = 1,
 278          .ao_speed = 1000,
 279          .num_p0_dio_channels = 8,
 280          .caldac = {ad8804_debug},      /*  doc says mb88341 */
 281          .has_8255 = 0,
 282          },
 283         {
 284          .device_id = 0x11c0,
 285          .name = "pxi-6040e",
 286          .n_adchan = 16,
 287          .adbits = 12,
 288          .ai_fifo_depth = 512,
 289          .alwaysdither = 0,
 290          .gainlkup = ai_gain_16,
 291          .ai_speed = 2000,
 292          .n_aochan = 2,
 293          .aobits = 12,
 294          .ao_fifo_depth = 512,
 295          .ao_range_table = &range_ni_E_ao_ext,
 296          .ao_unipolar = 1,
 297          .ao_speed = 1000,
 298          .num_p0_dio_channels = 8,
 299          .caldac = {mb88341},
 300          .has_8255 = 0,
 301          },
 302
 303         {
 304          .device_id = 0x1330,
 305          .name = "pci-6031e",
 306          .n_adchan = 64,
 307          .adbits = 16,
 308          .ai_fifo_depth = 512,
 309          .alwaysdither = 1,
 310          .gainlkup = ai_gain_14,
 311          .ai_speed = 10000,
 312          .n_aochan = 2,
 313          .aobits = 16,
 314          .ao_fifo_depth = 2048,
 315          .ao_range_table = &range_ni_E_ao_ext,
 316          .ao_unipolar = 1,
 317          .ao_speed = 10000,
 318          .num_p0_dio_channels = 8,
 319          .caldac = {dac8800, dac8043, ad8522},
 320          .has_8255 = 0,
 321          },
 322         {
 323          .device_id = 0x1270,
 324          .name = "pci-6032e",
 325          .n_adchan = 16,
 326          .adbits = 16,
 327          .ai_fifo_depth = 512,
 328          .alwaysdither = 1,
 329          .gainlkup = ai_gain_14,
 330          .ai_speed = 10000,
 331          .n_aochan = 0,
 332          .aobits = 0,
 333          .ao_fifo_depth = 0,
 334          .ao_unipolar = 0,
 335          .num_p0_dio_channels = 8,
 336          .caldac = {dac8800, dac8043, ad8522},
 337          .has_8255 = 0,
 338          },
 339         {
 340          .device_id = 0x1340,
 341          .name = "pci-6033e",
 342          .n_adchan = 64,
 343          .adbits = 16,
 344          .ai_fifo_depth = 512,
 345          .alwaysdither = 1,
 346          .gainlkup = ai_gain_14,
 347          .ai_speed = 10000,
 348          .n_aochan = 0,
 349          .aobits = 0,
 350          .ao_fifo_depth = 0,
 351          .ao_unipolar = 0,
 352          .num_p0_dio_channels = 8,
 353          .caldac = {dac8800, dac8043, ad8522},
 354          .has_8255 = 0,
 355          },
 356         {
 357          .device_id = 0x1350,
 358          .name = "pci-6071e",
 359          .n_adchan = 64,
 360          .adbits = 12,
 361          .ai_fifo_depth = 512,
 362          .alwaysdither = 1,
 363          .gainlkup = ai_gain_16,
 364          .ai_speed = 800,
 365          .n_aochan = 2,
 366          .aobits = 12,
 367          .ao_fifo_depth = 2048,
 368          .ao_range_table = &range_ni_E_ao_ext,
 369          .ao_unipolar = 1,
 370          .ao_speed = 1000,
 371          .num_p0_dio_channels = 8,
 372          .caldac = {ad8804_debug},
 373          .has_8255 = 0,
 374          },
 375         {
 376          .device_id = 0x2a60,
 377          .name = "pci-6023e",
 378          .n_adchan = 16,
 379          .adbits = 12,
 380          .ai_fifo_depth = 512,
 381          .alwaysdither = 0,
 382          .gainlkup = ai_gain_4,
 383          .ai_speed = 5000,
 384          .n_aochan = 0,
 385          .aobits = 0,
 386          .ao_unipolar = 0,
 387          .num_p0_dio_channels = 8,
 388          .caldac = {ad8804_debug},      /* manual is wrong */
 389          .has_8255 = 0,
 390          },
 391         {
 392          .device_id = 0x2a70,
 393          .name = "pci-6024e",
 394          .n_adchan = 16,
 395          .adbits = 12,
 396          .ai_fifo_depth = 512,
 397          .alwaysdither = 0,
 398          .gainlkup = ai_gain_4,
 399          .ai_speed = 5000,
 400          .n_aochan = 2,
 401          .aobits = 12,
 402          .ao_fifo_depth = 0,
 403          .ao_range_table = &range_bipolar10,
 404          .ao_unipolar = 0,
 405          .ao_speed = 100000,
 406          .num_p0_dio_channels = 8,
 407          .caldac = {ad8804_debug},      /* manual is wrong */
 408          .has_8255 = 0,
 409          },
 410         {
 411          .device_id = 0x2a80,
 412          .name = "pci-6025e",
 413          .n_adchan = 16,
 414          .adbits = 12,
 415          .ai_fifo_depth = 512,
 416          .alwaysdither = 0,
 417          .gainlkup = ai_gain_4,
 418          .ai_speed = 5000,
 419          .n_aochan = 2,
 420          .aobits = 12,
 421          .ao_fifo_depth = 0,
 422          .ao_range_table = &range_bipolar10,
 423          .ao_unipolar = 0,
 424          .ao_speed = 100000,
 425          .num_p0_dio_channels = 8,
 426          .caldac = {ad8804_debug},      /* manual is wrong */
 427          .has_8255 = 1,
 428          },
 429         {
 430          .device_id = 0x2ab0,
 431          .name = "pxi-6025e",
 432          .n_adchan = 16,
 433          .adbits = 12,
 434          .ai_fifo_depth = 512,
 435          .alwaysdither = 0,
 436          .gainlkup = ai_gain_4,
 437          .ai_speed = 5000,
 438          .n_aochan = 2,
 439          .aobits = 12,
 440          .ao_fifo_depth = 0,
 441          .ao_range_table = &range_ni_E_ao_ext,
 442          .ao_unipolar = 1,
 443          .ao_speed = 100000,
 444          .num_p0_dio_channels = 8,
 445          .caldac = {ad8804_debug},      /* manual is wrong */
 446          .has_8255 = 1,
 447          },
 448
 449         {
 450          .device_id = 0x2ca0,
 451          .name = "pci-6034e",
 452          .n_adchan = 16,
 453          .adbits = 16,
 454          .ai_fifo_depth = 512,
 455          .alwaysdither = 1,
 456          .gainlkup = ai_gain_4,
 457          .ai_speed = 5000,
 458          .n_aochan = 0,
 459          .aobits = 0,
 460          .ao_fifo_depth = 0,
 461          .ao_unipolar = 0,
 462          .num_p0_dio_channels = 8,
 463          .caldac = {ad8804_debug},
 464          .has_8255 = 0,
 465          },
 466         {
 467          .device_id = 0x2c80,
 468          .name = "pci-6035e",
 469          .n_adchan = 16,
 470          .adbits = 16,
 471          .ai_fifo_depth = 512,
 472          .alwaysdither = 1,
 473          .gainlkup = ai_gain_4,
 474          .ai_speed = 5000,
 475          .n_aochan = 2,
 476          .aobits = 12,
 477          .ao_fifo_depth = 0,
 478          .ao_range_table = &range_bipolar10,
 479          .ao_unipolar = 0,
 480          .ao_speed = 100000,
 481          .num_p0_dio_channels = 8,
 482          .caldac = {ad8804_debug},
 483          .has_8255 = 0,
 484          },
 485         {
 486          .device_id = 0x18b0,
 487          .name = "pci-6052e",
 488          .n_adchan = 16,
 489          .adbits = 16,
 490          .ai_fifo_depth = 512,
 491          .alwaysdither = 1,
 492          .gainlkup = ai_gain_16,
 493          .ai_speed = 3000,
 494          .n_aochan = 2,
 495          .aobits = 16,
 496          .ao_unipolar = 1,
 497          .ao_fifo_depth = 2048,
 498          .ao_range_table = &range_ni_E_ao_ext,
 499          .ao_speed = 3000,
 500          .num_p0_dio_channels = 8,
 501          .caldac = {ad8804_debug, ad8804_debug, ad8522},        /* manual is wrong */
 502          },
 503         {.device_id = 0x14e0,
 504          .name = "pci-6110",
 505          .n_adchan = 4,
 506          .adbits = 12,
 507          .ai_fifo_depth = 8192,
 508          .alwaysdither = 0,
 509          .gainlkup = ai_gain_611x,
 510          .ai_speed = 200,
 511          .n_aochan = 2,
 512          .aobits = 16,
 513          .reg_type = ni_reg_611x,
 514          .ao_range_table = &range_bipolar10,
 515          .ao_unipolar = 0,
 516          .ao_fifo_depth = 2048,
 517          .ao_speed = 250,
 518          .num_p0_dio_channels = 8,
 519          .caldac = {ad8804, ad8804},
 520          },
 521         {
 522          .device_id = 0x14f0,
 523          .name = "pci-6111",
 524          .n_adchan = 2,
 525          .adbits = 12,
 526          .ai_fifo_depth = 8192,
 527          .alwaysdither = 0,
 528          .gainlkup = ai_gain_611x,
 529          .ai_speed = 200,
 530          .n_aochan = 2,
 531          .aobits = 16,
 532          .reg_type = ni_reg_611x,
 533          .ao_range_table = &range_bipolar10,
 534          .ao_unipolar = 0,
 535          .ao_fifo_depth = 2048,
 536          .ao_speed = 250,
 537          .num_p0_dio_channels = 8,
 538          .caldac = {ad8804, ad8804},
 539          },
 540 #if 0
 541         /* The 6115 boards probably need their own driver */
 542         {
 543          .device_id = 0x2ed0,
 544          .name = "pci-6115",
 545          .n_adchan = 4,
 546          .adbits = 12,
 547          .ai_fifo_depth = 8192,
 548          .alwaysdither = 0,
 549          .gainlkup = ai_gain_611x,
 550          .ai_speed = 100,
 551          .n_aochan = 2,
 552          .aobits = 16,
 553          .ao_671x = 1,
 554          .ao_unipolar = 0,
 555          .ao_fifo_depth = 2048,
 556          .ao_speed = 250,
 557          .num_p0_dio_channels = 8,
 558          .reg_611x = 1,
 559          .caldac = {ad8804_debug, ad8804_debug, ad8804_debug},  /* XXX */
 560          },
 561 #endif
 562 #if 0
 563         {
 564          .device_id = 0x0000,
 565          .name = "pxi-6115",
 566          .n_adchan = 4,
 567          .adbits = 12,
 568          .ai_fifo_depth = 8192,
 569          .alwaysdither = 0,
 570          .gainlkup = ai_gain_611x,
 571          .ai_speed = 100,
 572          .n_aochan = 2,
 573          .aobits = 16,
 574          .ao_671x = 1,
 575          .ao_unipolar = 0,
 576          .ao_fifo_depth = 2048,
 577          .ao_speed = 250,
 578          .reg_611x = 1,
 579          .num_p0_dio_channels = 8,
 580          caldac = {ad8804_debug, ad8804_debug, ad8804_debug},   /* XXX */
 581          },
 582 #endif
 583         {
 584          .device_id = 0x1880,
 585          .name = "pci-6711",
 586          .n_adchan = 0,         /* no analog input */
 587          .n_aochan = 4,
 588          .aobits = 12,
 589          .ao_unipolar = 0,
 590          .ao_fifo_depth = 16384,
 591          /* data sheet says 8192, but fifo really holds 16384 samples */
 592          .ao_range_table = &range_bipolar10,
 593          .ao_speed = 1000,
 594          .num_p0_dio_channels = 8,
 595          .reg_type = ni_reg_6711,
 596          .caldac = {ad8804_debug},
 597          },
 598         {
 599          .device_id = 0x2b90,
 600          .name = "pxi-6711",
 601          .n_adchan = 0,         /* no analog input */
 602          .n_aochan = 4,
 603          .aobits = 12,
 604          .ao_unipolar = 0,
 605          .ao_fifo_depth = 16384,
 606          .ao_range_table = &range_bipolar10,
 607          .ao_speed = 1000,
 608          .num_p0_dio_channels = 8,
 609          .reg_type = ni_reg_6711,
 610          .caldac = {ad8804_debug},
 611          },
 612         {
 613          .device_id = 0x1870,
 614          .name = "pci-6713",
 615          .n_adchan = 0,         /* no analog input */
 616          .n_aochan = 8,
 617          .aobits = 12,
 618          .ao_unipolar = 0,
 619          .ao_fifo_depth = 16384,
 620          .ao_range_table = &range_bipolar10,
 621          .ao_speed = 1000,
 622          .num_p0_dio_channels = 8,
 623          .reg_type = ni_reg_6713,
 624          .caldac = {ad8804_debug, ad8804_debug},
 625          },
 626         {
 627          .device_id = 0x2b80,
 628          .name = "pxi-6713",
 629          .n_adchan = 0,         /* no analog input */
 630          .n_aochan = 8,
 631          .aobits = 12,
 632          .ao_unipolar = 0,
 633          .ao_fifo_depth = 16384,
 634          .ao_range_table = &range_bipolar10,
 635          .ao_speed = 1000,
 636          .num_p0_dio_channels = 8,
 637          .reg_type = ni_reg_6713,
 638          .caldac = {ad8804_debug, ad8804_debug},
 639          },
 640         {
 641          .device_id = 0x2430,
 642          .name = "pci-6731",
 643          .n_adchan = 0,         /* no analog input */
 644          .n_aochan = 4,
 645          .aobits = 16,
 646          .ao_unipolar = 0,
 647          .ao_fifo_depth = 8192,
 648          .ao_range_table = &range_bipolar10,
 649          .ao_speed = 1000,
 650          .num_p0_dio_channels = 8,
 651          .reg_type = ni_reg_6711,
 652          .caldac = {ad8804_debug},
 653          },
 654 #if 0                           /* need device ids */
 655         {
 656          .device_id = 0x0,
 657          .name = "pxi-6731",
 658          .n_adchan = 0,         /* no analog input */
 659          .n_aochan = 4,
 660          .aobits = 16,
 661          .ao_unipolar = 0,
 662          .ao_fifo_depth = 8192,
 663          .ao_range_table = &range_bipolar10,
 664          .num_p0_dio_channels = 8,
 665          .reg_type = ni_reg_6711,
 666          .caldac = {ad8804_debug},
 667          },
 668 #endif
 669         {
 670          .device_id = 0x2410,
 671          .name = "pci-6733",
 672          .n_adchan = 0,         /* no analog input */
 673          .n_aochan = 8,
 674          .aobits = 16,
 675          .ao_unipolar = 0,
 676          .ao_fifo_depth = 16384,
 677          .ao_range_table = &range_bipolar10,
 678          .ao_speed = 1000,
 679          .num_p0_dio_channels = 8,
 680          .reg_type = ni_reg_6713,
 681          .caldac = {ad8804_debug, ad8804_debug},
 682          },
 683         {
 684          .device_id = 0x2420,
 685          .name = "pxi-6733",
 686          .n_adchan = 0,         /* no analog input */
 687          .n_aochan = 8,
 688          .aobits = 16,
 689          .ao_unipolar = 0,
 690          .ao_fifo_depth = 16384,
 691          .ao_range_table = &range_bipolar10,
 692          .ao_speed = 1000,
 693          .num_p0_dio_channels = 8,
 694          .reg_type = ni_reg_6713,
 695          .caldac = {ad8804_debug, ad8804_debug},
 696          },
 697         {
 698          .device_id = 0x15b0,
 699          .name = "pxi-6071e",
 700          .n_adchan = 64,
 701          .adbits = 12,
 702          .ai_fifo_depth = 512,
 703          .alwaysdither = 1,
 704          .gainlkup = ai_gain_16,
 705          .ai_speed = 800,
 706          .n_aochan = 2,
 707          .aobits = 12,
 708          .ao_fifo_depth = 2048,
 709          .ao_range_table = &range_ni_E_ao_ext,
 710          .ao_unipolar = 1,
 711          .ao_speed = 1000,
 712          .num_p0_dio_channels = 8,
 713          .caldac = {ad8804_debug},
 714          .has_8255 = 0,
 715          },
 716         {
 717          .device_id = 0x11b0,
 718          .name = "pxi-6070e",
 719          .n_adchan = 16,
 720          .adbits = 12,
 721          .ai_fifo_depth = 512,
 722          .alwaysdither = 1,
 723          .gainlkup = ai_gain_16,
 724          .ai_speed = 800,
 725          .n_aochan = 2,
 726          .aobits = 12,
 727          .ao_fifo_depth = 2048,
 728          .ao_range_table = &range_ni_E_ao_ext,
 729          .ao_unipolar = 1,
 730          .ao_speed = 1000,
 731          .num_p0_dio_channels = 8,
 732          .caldac = {ad8804_debug},
 733          .has_8255 = 0,
 734          },
 735         {
 736          .device_id = 0x18c0,
 737          .name = "pxi-6052e",
 738          .n_adchan = 16,
 739          .adbits = 16,
 740          .ai_fifo_depth = 512,
 741          .alwaysdither = 1,
 742          .gainlkup = ai_gain_16,
 743          .ai_speed = 3000,
 744          .n_aochan = 2,
 745          .aobits = 16,
 746          .ao_unipolar = 1,
 747          .ao_fifo_depth = 2048,
 748          .ao_range_table = &range_ni_E_ao_ext,
 749          .ao_speed = 3000,
 750          .num_p0_dio_channels = 8,
 751          .caldac = {mb88341, mb88341, ad8522},
 752          },
 753         {
 754          .device_id = 0x1580,
 755          .name = "pxi-6031e",
 756          .n_adchan = 64,
 757          .adbits = 16,
 758          .ai_fifo_depth = 512,
 759          .alwaysdither = 1,
 760          .gainlkup = ai_gain_14,
 761          .ai_speed = 10000,
 762          .n_aochan = 2,
 763          .aobits = 16,
 764          .ao_fifo_depth = 2048,
 765          .ao_range_table = &range_ni_E_ao_ext,
 766          .ao_unipolar = 1,
 767          .ao_speed = 10000,
 768          .num_p0_dio_channels = 8,
 769          .caldac = {dac8800, dac8043, ad8522},
 770          },
 771         {
 772          .device_id = 0x2890,
 773          .name = "pci-6036e",
 774          .n_adchan = 16,
 775          .adbits = 16,
 776          .ai_fifo_depth = 512,
 777          .alwaysdither = 1,
 778          .gainlkup = ai_gain_4,
 779          .ai_speed = 5000,
 780          .n_aochan = 2,
 781          .aobits = 16,
 782          .ao_fifo_depth = 0,
 783          .ao_range_table = &range_bipolar10,
 784          .ao_unipolar = 0,
 785          .ao_speed = 100000,
 786          .num_p0_dio_channels = 8,
 787          .caldac = {ad8804_debug},
 788          .has_8255 = 0,
 789          },
 790         {
 791          .device_id = 0x70b0,
 792          .name = "pci-6220",
 793          .n_adchan = 16,
 794          .adbits = 16,
 795          .ai_fifo_depth = 512,
 796          /*      .FIXME = guess */
 797          .gainlkup = ai_gain_622x,
 798          .ai_speed = 4000,
 799          .n_aochan = 0,
 800          .aobits = 0,
 801          .ao_fifo_depth = 0,
 802          .num_p0_dio_channels = 8,
 803          .reg_type = ni_reg_622x,
 804          .ao_unipolar = 0,
 805          .caldac = {caldac_none},
 806          .has_8255 = 0,
 807          },
 808         {
 809          .device_id = 0x70af,
 810          .name = "pci-6221",
 811          .n_adchan = 16,
 812          .adbits = 16,
 813          .ai_fifo_depth = 4095,
 814          .gainlkup = ai_gain_622x,
 815          .ai_speed = 4000,
 816          .n_aochan = 2,
 817          .aobits = 16,
 818          .ao_fifo_depth = 8191,
 819          .ao_range_table = &range_ni_M_622x_ao,
 820          .reg_type = ni_reg_622x,
 821          .ao_unipolar = 0,
 822          .ao_speed = 1200,
 823          .num_p0_dio_channels = 8,
 824          .caldac = {caldac_none},
 825          .has_8255 = 0,
 826          },
 827         {
 828          .device_id = 0x71bc,
 829          .name = "pci-6221_37pin",
 830          .n_adchan = 16,
 831          .adbits = 16,
 832          .ai_fifo_depth = 4095,
 833          .gainlkup = ai_gain_622x,
 834          .ai_speed = 4000,
 835          .n_aochan = 2,
 836          .aobits = 16,
 837          .ao_fifo_depth = 8191,
 838          .ao_range_table = &range_ni_M_622x_ao,
 839          .reg_type = ni_reg_622x,
 840          .ao_unipolar = 0,
 841          .ao_speed = 1200,
 842          .num_p0_dio_channels = 8,
 843          .caldac = {caldac_none},
 844          .has_8255 = 0,
 845          },
 846         {
 847          .device_id = 0x70f2,
 848          .name = "pci-6224",
 849          .n_adchan = 32,
 850          .adbits = 16,
 851          .ai_fifo_depth = 4095,
 852          .gainlkup = ai_gain_622x,
 853          .ai_speed = 4000,
 854          .n_aochan = 0,
 855          .aobits = 0,
 856          .ao_fifo_depth = 0,
 857          .reg_type = ni_reg_622x,
 858          .ao_unipolar = 0,
 859          .num_p0_dio_channels = 32,
 860          .caldac = {caldac_none},
 861          .has_8255 = 0,
 862          },
 863         {
 864          .device_id = 0x70f3,
 865          .name = "pxi-6224",
 866          .n_adchan = 32,
 867          .adbits = 16,
 868          .ai_fifo_depth = 4095,
 869          .gainlkup = ai_gain_622x,
 870          .ai_speed = 4000,
 871          .n_aochan = 0,
 872          .aobits = 0,
 873          .ao_fifo_depth = 0,
 874          .reg_type = ni_reg_622x,
 875          .ao_unipolar = 0,
 876          .num_p0_dio_channels = 32,
 877          .caldac = {caldac_none},
 878          .has_8255 = 0,
 879          },
 880         {
 881          .device_id = 0x716c,
 882          .name = "pci-6225",
 883          .n_adchan = 80,
 884          .adbits = 16,
 885          .ai_fifo_depth = 4095,
 886          .gainlkup = ai_gain_622x,
 887          .ai_speed = 4000,
 888          .n_aochan = 2,
 889          .aobits = 16,
 890          .ao_fifo_depth = 8191,
 891          .ao_range_table = &range_ni_M_622x_ao,
 892          .reg_type = ni_reg_622x,
 893          .ao_unipolar = 0,
 894          .ao_speed = 1200,
 895          .num_p0_dio_channels = 32,
 896          .caldac = {caldac_none},
 897          .has_8255 = 0,
 898          },
 899         {
 900          .device_id = 0x716d,
 901          .name = "pxi-6225",
 902          .n_adchan = 80,
 903          .adbits = 16,
 904          .ai_fifo_depth = 4095,
 905          .gainlkup = ai_gain_622x,
 906          .ai_speed = 4000,
 907          .n_aochan = 2,
 908          .aobits = 16,
 909          .ao_fifo_depth = 8191,
 910          .ao_range_table = &range_ni_M_622x_ao,
 911          .reg_type = ni_reg_622x,
 912          .ao_unipolar = 0,
 913          .ao_speed = 1200,
 914          .num_p0_dio_channels = 32,
 915          .caldac = {caldac_none},
 916          .has_8255 = 0,
 917         },
 918         {
 919          .device_id = 0x70aa,
 920          .name = "pci-6229",
 921          .n_adchan = 32,
 922          .adbits = 16,
 923          .ai_fifo_depth = 4095,
 924          .gainlkup = ai_gain_622x,
 925          .ai_speed = 4000,
 926          .n_aochan = 4,
 927          .aobits = 16,
 928          .ao_fifo_depth = 8191,
 929          .ao_range_table = &range_ni_M_622x_ao,
 930          .reg_type = ni_reg_622x,
 931          .ao_unipolar = 0,
 932          .ao_speed = 1200,
 933          .num_p0_dio_channels = 32,
 934          .caldac = {caldac_none},
 935          .has_8255 = 0,
 936          },
 937         {
 938          .device_id = 0x70b4,
 939          .name = "pci-6250",
 940          .n_adchan = 16,
 941          .adbits = 16,
 942          .ai_fifo_depth = 4095,
 943          .gainlkup = ai_gain_628x,
 944          .ai_speed = 800,
 945          .n_aochan = 0,
 946          .aobits = 0,
 947          .ao_fifo_depth = 0,
 948          .reg_type = ni_reg_625x,
 949          .ao_unipolar = 0,
 950          .num_p0_dio_channels = 8,
 951          .caldac = {caldac_none},
 952          .has_8255 = 0,
 953          },
 954         {
 955          .device_id = 0x70b8,
 956          .name = "pci-6251",
 957          .n_adchan = 16,
 958          .adbits = 16,
 959          .ai_fifo_depth = 4095,
 960          .gainlkup = ai_gain_628x,
 961          .ai_speed = 800,
 962          .n_aochan = 2,
 963          .aobits = 16,
 964          .ao_fifo_depth = 8191,
 965          .ao_range_table = &range_ni_M_625x_ao,
 966          .reg_type = ni_reg_625x,
 967          .ao_unipolar = 0,
 968          .ao_speed = 350,
 969          .num_p0_dio_channels = 8,
 970          .caldac = {caldac_none},
 971          .has_8255 = 0,
 972          },
 973         {
 974          .device_id = 0x717d,
 975          .name = "pcie-6251",
 976          .n_adchan = 16,
 977          .adbits = 16,
 978          .ai_fifo_depth = 4095,
 979          .gainlkup = ai_gain_628x,
 980          .ai_speed = 800,
 981          .n_aochan = 2,
 982          .aobits = 16,
 983          .ao_fifo_depth = 8191,
 984          .ao_range_table = &range_ni_M_625x_ao,
 985          .reg_type = ni_reg_625x,
 986          .ao_unipolar = 0,
 987          .ao_speed = 350,
 988          .num_p0_dio_channels = 8,
 989          .caldac = {caldac_none},
 990          .has_8255 = 0,
 991          },
 992         {
 993          .device_id = 0x72e8,
 994          .name = "pxie-6251",
 995          .n_adchan = 16,
 996          .adbits = 16,
 997          .ai_fifo_depth = 4095,
 998          .gainlkup = ai_gain_628x,
 999          .ai_speed = 800,
1000          .n_aochan = 2,
1001          .aobits = 16,
1002          .ao_fifo_depth = 8191,
1003          .ao_range_table = &range_ni_M_625x_ao,
1004          .reg_type = ni_reg_625x,
1005          .ao_unipolar = 0,
1006          .ao_speed = 350,
1007          .num_p0_dio_channels = 8,
1008          .caldac = {caldac_none},
1009          .has_8255 = 0,
1010          },
1011         {
1012          .device_id = 0x70b7,
1013          .name = "pci-6254",
1014          .n_adchan = 32,
1015          .adbits = 16,
1016          .ai_fifo_depth = 4095,
1017          .gainlkup = ai_gain_628x,
1018          .ai_speed = 800,
1019          .n_aochan = 0,
1020          .aobits = 0,
1021          .ao_fifo_depth = 0,
1022          .reg_type = ni_reg_625x,
1023          .ao_unipolar = 0,
1024          .num_p0_dio_channels = 32,
1025          .caldac = {caldac_none},
1026          .has_8255 = 0,
1027          },
1028         {
1029          .device_id = 0x70ab,
1030          .name = "pci-6259",
1031          .n_adchan = 32,
1032          .adbits = 16,
1033          .ai_fifo_depth = 4095,
1034          .gainlkup = ai_gain_628x,
1035          .ai_speed = 800,
1036          .n_aochan = 4,
1037          .aobits = 16,
1038          .ao_fifo_depth = 8191,
1039          .ao_range_table = &range_ni_M_625x_ao,
1040          .reg_type = ni_reg_625x,
1041          .ao_unipolar = 0,
1042          .ao_speed = 350,
1043          .num_p0_dio_channels = 32,
1044          .caldac = {caldac_none},
1045          .has_8255 = 0,
1046          },
1047         {
1048          .device_id = 0x717f,
1049          .name = "pcie-6259",
1050          .n_adchan = 32,
1051          .adbits = 16,
1052          .ai_fifo_depth = 4095,
1053          .gainlkup = ai_gain_628x,
1054          .ai_speed = 800,
1055          .n_aochan = 4,
1056          .aobits = 16,
1057          .ao_fifo_depth = 8191,
1058          .ao_range_table = &range_ni_M_625x_ao,
1059          .reg_type = ni_reg_625x,
1060          .ao_unipolar = 0,
1061          .ao_speed = 350,
1062          .num_p0_dio_channels = 32,
1063          .caldac = {caldac_none},
1064          .has_8255 = 0,
1065          },
1066         {
1067          .device_id = 0x70b6,
1068          .name = "pci-6280",
1069          .n_adchan = 16,
1070          .adbits = 18,
1071          .ai_fifo_depth = 2047,
1072          .gainlkup = ai_gain_628x,
1073          .ai_speed = 1600,
1074          .n_aochan = 0,
1075          .aobits = 0,
1076          .ao_fifo_depth = 8191,
1077          .reg_type = ni_reg_628x,
1078          .ao_unipolar = 0,
1079          .num_p0_dio_channels = 8,
1080          .caldac = {caldac_none},
1081          .has_8255 = 0,
1082          },
1083         {
1084          .device_id = 0x70bd,
1085          .name = "pci-6281",
1086          .n_adchan = 16,
1087          .adbits = 18,
1088          .ai_fifo_depth = 2047,
1089          .gainlkup = ai_gain_628x,
1090          .ai_speed = 1600,
1091          .n_aochan = 2,
1092          .aobits = 16,
1093          .ao_fifo_depth = 8191,
1094          .ao_range_table = &range_ni_M_628x_ao,
1095          .reg_type = ni_reg_628x,
1096          .ao_unipolar = 1,
1097          .ao_speed = 350,
1098          .num_p0_dio_channels = 8,
1099          .caldac = {caldac_none},
1100          .has_8255 = 0,
1101          },
1102         {
1103          .device_id = 0x70bf,
1104          .name = "pxi-6281",
1105          .n_adchan = 16,
1106          .adbits = 18,
1107          .ai_fifo_depth = 2047,
1108          .gainlkup = ai_gain_628x,
1109          .ai_speed = 1600,
1110          .n_aochan = 2,
1111          .aobits = 16,
1112          .ao_fifo_depth = 8191,
1113          .ao_range_table = &range_ni_M_628x_ao,
1114          .reg_type = ni_reg_628x,
1115          .ao_unipolar = 1,
1116          .ao_speed = 350,
1117          .num_p0_dio_channels = 8,
1118          .caldac = {caldac_none},
1119          .has_8255 = 0,
1120          },
1121         {
1122          .device_id = 0x70bc,
1123          .name = "pci-6284",
1124          .n_adchan = 32,
1125          .adbits = 18,
1126          .ai_fifo_depth = 2047,
1127          .gainlkup = ai_gain_628x,
1128          .ai_speed = 1600,
1129          .n_aochan = 0,
1130          .aobits = 0,
1131          .ao_fifo_depth = 0,
1132          .reg_type = ni_reg_628x,
1133          .ao_unipolar = 0,
1134          .num_p0_dio_channels = 32,
1135          .caldac = {caldac_none},
1136          .has_8255 = 0,
1137          },
1138         {
1139          .device_id = 0x70ac,
1140          .name = "pci-6289",
1141          .n_adchan = 32,
1142          .adbits = 18,
1143          .ai_fifo_depth = 2047,
1144          .gainlkup = ai_gain_628x,
1145          .ai_speed = 1600,
1146          .n_aochan = 4,
1147          .aobits = 16,
1148          .ao_fifo_depth = 8191,
1149          .ao_range_table = &range_ni_M_628x_ao,
1150          .reg_type = ni_reg_628x,
1151          .ao_unipolar = 1,
1152          .ao_speed = 350,
1153          .num_p0_dio_channels = 32,
1154          .caldac = {caldac_none},
1155          .has_8255 = 0,
1156          },
1157         {
1158          .device_id = 0x70C0,
1159          .name = "pci-6143",
1160          .n_adchan = 8,
1161          .adbits = 16,
1162          .ai_fifo_depth = 1024,
1163          .alwaysdither = 0,
1164          .gainlkup = ai_gain_6143,
1165          .ai_speed = 4000,
1166          .n_aochan = 0,
1167          .aobits = 0,
1168          .reg_type = ni_reg_6143,
1169          .ao_unipolar = 0,
1170          .ao_fifo_depth = 0,
1171          .num_p0_dio_channels = 8,
1172          .caldac = {ad8804_debug, ad8804_debug},
1173          },
1174         {
1175          .device_id = 0x710D,
1176          .name = "pxi-6143",
1177          .n_adchan = 8,
1178          .adbits = 16,
1179          .ai_fifo_depth = 1024,
1180          .alwaysdither = 0,
1181          .gainlkup = ai_gain_6143,
1182          .ai_speed = 4000,
1183          .n_aochan = 0,
1184          .aobits = 0,
1185          .reg_type = ni_reg_6143,
1186          .ao_unipolar = 0,
1187          .ao_fifo_depth = 0,
1188          .num_p0_dio_channels = 8,
1189          .caldac = {ad8804_debug, ad8804_debug},
1190          },
1191 };
1192
1193 struct ni_private {
1194 NI_PRIVATE_COMMON};
1195
1196 /* How we access registers */
1197
1198 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1199 #define ni_readl(a)     (readl(devpriv->mite->daq_io_addr + (a)))
1200 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1201 #define ni_readw(a)     (readw(devpriv->mite->daq_io_addr + (a)))
1202 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1203 #define ni_readb(a)     (readb(devpriv->mite->daq_io_addr + (a)))
1204
1205 /* How we access STC registers */
1206
1207 /* We automatically take advantage of STC registers that can be
1208  * read/written directly in the I/O space of the board.  Most
1209  * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1210  * The 611x devices map the write registers to iobase+addr*2, and
1211  * the read registers to iobase+(addr-1)*2. */
1212 /* However, the 611x boards still aren't working, so I'm disabling
1213  * non-windowed STC access temporarily */
1214
1215 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1216 {
1217         struct ni_private *devpriv = dev->private;
1218         unsigned long flags;
1219
1220         spin_lock_irqsave(&devpriv->window_lock, flags);
1221         ni_writew(reg, Window_Address);
1222         ni_writew(data, Window_Data);
1223         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1224 }
1225
1226 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1227 {
1228         struct ni_private *devpriv = dev->private;
1229         unsigned long flags;
1230         uint16_t ret;
1231
1232         spin_lock_irqsave(&devpriv->window_lock, flags);
1233         ni_writew(reg, Window_Address);
1234         ret = ni_readw(Window_Data);
1235         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1236
1237         return ret;
1238 }
1239
1240 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1241                                 int reg)
1242 {
1243         struct ni_private *devpriv = dev->private;
1244         unsigned offset;
1245
1246         switch (reg) {
1247         case ADC_FIFO_Clear:
1248                 offset = M_Offset_AI_FIFO_Clear;
1249                 break;
1250         case AI_Command_1_Register:
1251                 offset = M_Offset_AI_Command_1;
1252                 break;
1253         case AI_Command_2_Register:
1254                 offset = M_Offset_AI_Command_2;
1255                 break;
1256         case AI_Mode_1_Register:
1257                 offset = M_Offset_AI_Mode_1;
1258                 break;
1259         case AI_Mode_2_Register:
1260                 offset = M_Offset_AI_Mode_2;
1261                 break;
1262         case AI_Mode_3_Register:
1263                 offset = M_Offset_AI_Mode_3;
1264                 break;
1265         case AI_Output_Control_Register:
1266                 offset = M_Offset_AI_Output_Control;
1267                 break;
1268         case AI_Personal_Register:
1269                 offset = M_Offset_AI_Personal;
1270                 break;
1271         case AI_SI2_Load_A_Register:
1272                 /*  this is actually a 32 bit register on m series boards */
1273                 ni_writel(data, M_Offset_AI_SI2_Load_A);
1274                 return;
1275                 break;
1276         case AI_SI2_Load_B_Register:
1277                 /*  this is actually a 32 bit register on m series boards */
1278                 ni_writel(data, M_Offset_AI_SI2_Load_B);
1279                 return;
1280                 break;
1281         case AI_START_STOP_Select_Register:
1282                 offset = M_Offset_AI_START_STOP_Select;
1283                 break;
1284         case AI_Trigger_Select_Register:
1285                 offset = M_Offset_AI_Trigger_Select;
1286                 break;
1287         case Analog_Trigger_Etc_Register:
1288                 offset = M_Offset_Analog_Trigger_Etc;
1289                 break;
1290         case AO_Command_1_Register:
1291                 offset = M_Offset_AO_Command_1;
1292                 break;
1293         case AO_Command_2_Register:
1294                 offset = M_Offset_AO_Command_2;
1295                 break;
1296         case AO_Mode_1_Register:
1297                 offset = M_Offset_AO_Mode_1;
1298                 break;
1299         case AO_Mode_2_Register:
1300                 offset = M_Offset_AO_Mode_2;
1301                 break;
1302         case AO_Mode_3_Register:
1303                 offset = M_Offset_AO_Mode_3;
1304                 break;
1305         case AO_Output_Control_Register:
1306                 offset = M_Offset_AO_Output_Control;
1307                 break;
1308         case AO_Personal_Register:
1309                 offset = M_Offset_AO_Personal;
1310                 break;
1311         case AO_Start_Select_Register:
1312                 offset = M_Offset_AO_Start_Select;
1313                 break;
1314         case AO_Trigger_Select_Register:
1315                 offset = M_Offset_AO_Trigger_Select;
1316                 break;
1317         case Clock_and_FOUT_Register:
1318                 offset = M_Offset_Clock_and_FOUT;
1319                 break;
1320         case Configuration_Memory_Clear:
1321                 offset = M_Offset_Configuration_Memory_Clear;
1322                 break;
1323         case DAC_FIFO_Clear:
1324                 offset = M_Offset_AO_FIFO_Clear;
1325                 break;
1326         case DIO_Control_Register:
1327                 printk
1328                     ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1329                      __func__, reg);
1330                 return;
1331                 break;
1332         case G_Autoincrement_Register(0):
1333                 offset = M_Offset_G0_Autoincrement;
1334                 break;
1335         case G_Autoincrement_Register(1):
1336                 offset = M_Offset_G1_Autoincrement;
1337                 break;
1338         case G_Command_Register(0):
1339                 offset = M_Offset_G0_Command;
1340                 break;
1341         case G_Command_Register(1):
1342                 offset = M_Offset_G1_Command;
1343                 break;
1344         case G_Input_Select_Register(0):
1345                 offset = M_Offset_G0_Input_Select;
1346                 break;
1347         case G_Input_Select_Register(1):
1348                 offset = M_Offset_G1_Input_Select;
1349                 break;
1350         case G_Mode_Register(0):
1351                 offset = M_Offset_G0_Mode;
1352                 break;
1353         case G_Mode_Register(1):
1354                 offset = M_Offset_G1_Mode;
1355                 break;
1356         case Interrupt_A_Ack_Register:
1357                 offset = M_Offset_Interrupt_A_Ack;
1358                 break;
1359         case Interrupt_A_Enable_Register:
1360                 offset = M_Offset_Interrupt_A_Enable;
1361                 break;
1362         case Interrupt_B_Ack_Register:
1363                 offset = M_Offset_Interrupt_B_Ack;
1364                 break;
1365         case Interrupt_B_Enable_Register:
1366                 offset = M_Offset_Interrupt_B_Enable;
1367                 break;
1368         case Interrupt_Control_Register:
1369                 offset = M_Offset_Interrupt_Control;
1370                 break;
1371         case IO_Bidirection_Pin_Register:
1372                 offset = M_Offset_IO_Bidirection_Pin;
1373                 break;
1374         case Joint_Reset_Register:
1375                 offset = M_Offset_Joint_Reset;
1376                 break;
1377         case RTSI_Trig_A_Output_Register:
1378                 offset = M_Offset_RTSI_Trig_A_Output;
1379                 break;
1380         case RTSI_Trig_B_Output_Register:
1381                 offset = M_Offset_RTSI_Trig_B_Output;
1382                 break;
1383         case RTSI_Trig_Direction_Register:
1384                 offset = M_Offset_RTSI_Trig_Direction;
1385                 break;
1386                 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1387                    and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1388         default:
1389                 dev_warn(dev->class_dev,
1390                          "%s: bug! unhandled register=0x%x in switch.\n",
1391                          __func__, reg);
1392                 BUG();
1393                 return;
1394                 break;
1395         }
1396         ni_writew(data, offset);
1397 }
1398
1399 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1400 {
1401         struct ni_private *devpriv = dev->private;
1402         unsigned offset;
1403
1404         switch (reg) {
1405         case AI_Status_1_Register:
1406                 offset = M_Offset_AI_Status_1;
1407                 break;
1408         case AO_Status_1_Register:
1409                 offset = M_Offset_AO_Status_1;
1410                 break;
1411         case AO_Status_2_Register:
1412                 offset = M_Offset_AO_Status_2;
1413                 break;
1414         case DIO_Serial_Input_Register:
1415                 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1416                 break;
1417         case Joint_Status_1_Register:
1418                 offset = M_Offset_Joint_Status_1;
1419                 break;
1420         case Joint_Status_2_Register:
1421                 offset = M_Offset_Joint_Status_2;
1422                 break;
1423         case G_Status_Register:
1424                 offset = M_Offset_G01_Status;
1425                 break;
1426         default:
1427                 dev_warn(dev->class_dev,
1428                          "%s: bug! unhandled register=0x%x in switch.\n",
1429                          __func__, reg);
1430                 BUG();
1431                 return 0;
1432                 break;
1433         }
1434         return ni_readw(offset);
1435 }
1436
1437 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1438                                 int reg)
1439 {
1440         struct ni_private *devpriv = dev->private;
1441         unsigned offset;
1442
1443         switch (reg) {
1444         case AI_SC_Load_A_Registers:
1445                 offset = M_Offset_AI_SC_Load_A;
1446                 break;
1447         case AI_SI_Load_A_Registers:
1448                 offset = M_Offset_AI_SI_Load_A;
1449                 break;
1450         case AO_BC_Load_A_Register:
1451                 offset = M_Offset_AO_BC_Load_A;
1452                 break;
1453         case AO_UC_Load_A_Register:
1454                 offset = M_Offset_AO_UC_Load_A;
1455                 break;
1456         case AO_UI_Load_A_Register:
1457                 offset = M_Offset_AO_UI_Load_A;
1458                 break;
1459         case G_Load_A_Register(0):
1460                 offset = M_Offset_G0_Load_A;
1461                 break;
1462         case G_Load_A_Register(1):
1463                 offset = M_Offset_G1_Load_A;
1464                 break;
1465         case G_Load_B_Register(0):
1466                 offset = M_Offset_G0_Load_B;
1467                 break;
1468         case G_Load_B_Register(1):
1469                 offset = M_Offset_G1_Load_B;
1470                 break;
1471         default:
1472                 dev_warn(dev->class_dev,
1473                          "%s: bug! unhandled register=0x%x in switch.\n",
1474                          __func__, reg);
1475                 BUG();
1476                 return;
1477                 break;
1478         }
1479         ni_writel(data, offset);
1480 }
1481
1482 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1483 {
1484         struct ni_private *devpriv = dev->private;
1485         unsigned offset;
1486
1487         switch (reg) {
1488         case G_HW_Save_Register(0):
1489                 offset = M_Offset_G0_HW_Save;
1490                 break;
1491         case G_HW_Save_Register(1):
1492                 offset = M_Offset_G1_HW_Save;
1493                 break;
1494         case G_Save_Register(0):
1495                 offset = M_Offset_G0_Save;
1496                 break;
1497         case G_Save_Register(1):
1498                 offset = M_Offset_G1_Save;
1499                 break;
1500         default:
1501                 dev_warn(dev->class_dev,
1502                          "%s: bug! unhandled register=0x%x in switch.\n",
1503                          __func__, reg);
1504                 BUG();
1505                 return 0;
1506                 break;
1507         }
1508         return ni_readl(offset);
1509 }
1510
1511 #define interrupt_pin(a)        0
1512 #define IRQ_POLARITY 1
1513
1514 #define NI_E_IRQ_FLAGS          IRQF_SHARED
1515
1516 #include "ni_mio_common.c"
1517
1518 static int pcimio_ai_change(struct comedi_device *dev,
1519                             struct comedi_subdevice *s, unsigned long new_size);
1520 static int pcimio_ao_change(struct comedi_device *dev,
1521                             struct comedi_subdevice *s, unsigned long new_size);
1522 static int pcimio_gpct0_change(struct comedi_device *dev,
1523                                struct comedi_subdevice *s,
1524                                unsigned long new_size);
1525 static int pcimio_gpct1_change(struct comedi_device *dev,
1526                                struct comedi_subdevice *s,
1527                                unsigned long new_size);
1528 static int pcimio_dio_change(struct comedi_device *dev,
1529                              struct comedi_subdevice *s,
1530                              unsigned long new_size);
1531
1532 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1533 {
1534         struct ni_private *devpriv = dev->private;
1535         static const int Start_Cal_EEPROM = 0x400;
1536         static const unsigned window_size = 10;
1537         static const int serial_number_eeprom_offset = 0x4;
1538         static const int serial_number_eeprom_length = 0x4;
1539         unsigned old_iodwbsr_bits;
1540         unsigned old_iodwbsr1_bits;
1541         unsigned old_iodwcr1_bits;
1542         int i;
1543
1544         old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1545         old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1546         old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1547         writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1548         writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1549                devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1550         writel(0x1 | old_iodwcr1_bits,
1551                devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1552         writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1553
1554         BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1555         for (i = 0; i < serial_number_eeprom_length; ++i) {
1556                 char *byte_ptr = (char *)&devpriv->serial_number + i;
1557                 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1558         }
1559         devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1560
1561         for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1562                 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1563
1564         writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1565         writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1566         writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1567         writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1568 }
1569
1570 static void init_6143(struct comedi_device *dev)
1571 {
1572         struct ni_private *devpriv = dev->private;
1573
1574         /*  Disable interrupts */
1575         devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1576
1577         /*  Initialise 6143 AI specific bits */
1578         ni_writeb(0x00, Magic_6143);    /*  Set G0,G1 DMA mode to E series version */
1579         ni_writeb(0x80, PipelineDelay_6143);    /*  Set EOCMode, ADCMode and pipelinedelay */
1580         ni_writeb(0x00, EOC_Set_6143);  /*  Set EOC Delay */
1581
1582         ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143);       /*  Set the FIFO half full level */
1583
1584         /*  Strobe Relay disable bit */
1585         devpriv->ai_calib_source_enabled = 0;
1586         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1587                   Calibration_Channel_6143);
1588         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1589 }
1590
1591 static void pcimio_detach(struct comedi_device *dev)
1592 {
1593         struct ni_private *devpriv = dev->private;
1594
1595         mio_common_detach(dev);
1596         if (dev->irq)
1597                 free_irq(dev->irq, dev);
1598         if (devpriv) {
1599                 mite_free_ring(devpriv->ai_mite_ring);
1600                 mite_free_ring(devpriv->ao_mite_ring);
1601                 mite_free_ring(devpriv->cdo_mite_ring);
1602                 mite_free_ring(devpriv->gpct_mite_ring[0]);
1603                 mite_free_ring(devpriv->gpct_mite_ring[1]);
1604                 if (devpriv->mite) {
1605                         mite_unsetup(devpriv->mite);
1606                         mite_free(devpriv->mite);
1607                 }
1608         }
1609 }
1610
1611 static const struct ni_board_struct *
1612 pcimio_find_boardinfo(struct pci_dev *pcidev)
1613 {
1614         unsigned int device_id = pcidev->device;
1615         unsigned int n;
1616
1617         for (n = 0; n < ARRAY_SIZE(ni_boards); n++) {
1618                 const struct ni_board_struct *board = &ni_boards[n];
1619                 if (board->device_id == device_id)
1620                         return board;
1621         }
1622         return NULL;
1623 }
1624
1625 static int pcimio_auto_attach(struct comedi_device *dev,
1626                                         unsigned long context_unused)
1627 {
1628         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1629         struct ni_private *devpriv;
1630         int ret;
1631
1632         dev_info(dev->class_dev, "ni_pcimio: attach %s\n", pci_name(pcidev));
1633
1634         ret = ni_alloc_private(dev);
1635         if (ret)
1636                 return ret;
1637         devpriv = dev->private;
1638
1639         dev->board_ptr = pcimio_find_boardinfo(pcidev);
1640         if (!dev->board_ptr)
1641                 return -ENODEV;
1642
1643         devpriv->mite = mite_alloc(pcidev);
1644         if (!devpriv->mite)
1645                 return -ENOMEM;
1646
1647         dev_dbg(dev->class_dev, "%s\n", boardtype.name);
1648         dev->board_name = boardtype.name;
1649
1650         if (boardtype.reg_type & ni_reg_m_series_mask) {
1651                 devpriv->stc_writew = &m_series_stc_writew;
1652                 devpriv->stc_readw = &m_series_stc_readw;
1653                 devpriv->stc_writel = &m_series_stc_writel;
1654                 devpriv->stc_readl = &m_series_stc_readl;
1655         } else {
1656                 devpriv->stc_writew = &e_series_win_out;
1657                 devpriv->stc_readw = &e_series_win_in;
1658                 devpriv->stc_writel = &win_out2;
1659                 devpriv->stc_readl = &win_in2;
1660         }
1661
1662         ret = mite_setup(devpriv->mite);
1663         if (ret < 0) {
1664                 pr_warn("error setting up mite\n");
1665                 return ret;
1666         }
1667
1668         devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1669         if (devpriv->ai_mite_ring == NULL)
1670                 return -ENOMEM;
1671         devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1672         if (devpriv->ao_mite_ring == NULL)
1673                 return -ENOMEM;
1674         devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1675         if (devpriv->cdo_mite_ring == NULL)
1676                 return -ENOMEM;
1677         devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1678         if (devpriv->gpct_mite_ring[0] == NULL)
1679                 return -ENOMEM;
1680         devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1681         if (devpriv->gpct_mite_ring[1] == NULL)
1682                 return -ENOMEM;
1683
1684         if (boardtype.reg_type & ni_reg_m_series_mask)
1685                 m_series_init_eeprom_buffer(dev);
1686         if (boardtype.reg_type == ni_reg_6143)
1687                 init_6143(dev);
1688
1689         dev->irq = mite_irq(devpriv->mite);
1690
1691         if (dev->irq == 0) {
1692                 pr_warn("unknown irq (bad)\n");
1693         } else {
1694                 pr_debug("( irq = %u )\n", dev->irq);
1695                 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1696                                   DRV_NAME, dev);
1697                 if (ret < 0) {
1698                         pr_warn("irq not available\n");
1699                         dev->irq = 0;
1700                 }
1701         }
1702
1703         ret = ni_E_init(dev);
1704         if (ret < 0)
1705                 return ret;
1706
1707         dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1708         dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1709         dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1710         dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1711         dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1712
1713         return ret;
1714 }
1715
1716 static int pcimio_ai_change(struct comedi_device *dev,
1717                             struct comedi_subdevice *s, unsigned long new_size)
1718 {
1719         struct ni_private *devpriv = dev->private;
1720         int ret;
1721
1722         ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1723         if (ret < 0)
1724                 return ret;
1725
1726         return 0;
1727 }
1728
1729 static int pcimio_ao_change(struct comedi_device *dev,
1730                             struct comedi_subdevice *s, unsigned long new_size)
1731 {
1732         struct ni_private *devpriv = dev->private;
1733         int ret;
1734
1735         ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1736         if (ret < 0)
1737                 return ret;
1738
1739         return 0;
1740 }
1741
1742 static int pcimio_gpct0_change(struct comedi_device *dev,
1743                                struct comedi_subdevice *s,
1744                                unsigned long new_size)
1745 {
1746         struct ni_private *devpriv = dev->private;
1747         int ret;
1748
1749         ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1750         if (ret < 0)
1751                 return ret;
1752
1753         return 0;
1754 }
1755
1756 static int pcimio_gpct1_change(struct comedi_device *dev,
1757                                struct comedi_subdevice *s,
1758                                unsigned long new_size)
1759 {
1760         struct ni_private *devpriv = dev->private;
1761         int ret;
1762
1763         ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1764         if (ret < 0)
1765                 return ret;
1766
1767         return 0;
1768 }
1769
1770 static int pcimio_dio_change(struct comedi_device *dev,
1771                              struct comedi_subdevice *s, unsigned long new_size)
1772 {
1773         struct ni_private *devpriv = dev->private;
1774         int ret;
1775
1776         ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1777         if (ret < 0)
1778                 return ret;
1779
1780         return 0;
1781 }
1782
1783 static struct comedi_driver ni_pcimio_driver = {
1784         .driver_name    = "ni_pcimio",
1785         .module         = THIS_MODULE,
1786         .auto_attach    = pcimio_auto_attach,
1787         .detach         = pcimio_detach,
1788 };
1789
1790 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1791                                          const struct pci_device_id *ent)
1792 {
1793         return comedi_pci_auto_config(dev, &ni_pcimio_driver);
1794 }
1795
1796 static DEFINE_PCI_DEVICE_TABLE(ni_pcimio_pci_table) = {
1797         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0162) },
1798         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1170) },
1799         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1180) },
1800         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1190) },
1801         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11b0) },
1802         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11c0) },
1803         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11d0) },
1804         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1270) },
1805         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1330) },
1806         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1340) },
1807         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1350) },
1808         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14e0) },
1809         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14f0) },
1810         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1580) },
1811         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x15b0) },
1812         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1880) },
1813         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1870) },
1814         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18b0) },
1815         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18c0) },
1816         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2410) },
1817         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2420) },
1818         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2430) },
1819         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2890) },
1820         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x28c0) },
1821         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a60) },
1822         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a70) },
1823         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a80) },
1824         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ab0) },
1825         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b80) },
1826         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b90) },
1827         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c80) },
1828         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ca0) },
1829         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70aa) },
1830         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ab) },
1831         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ac) },
1832         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70af) },
1833         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b0) },
1834         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b4) },
1835         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b6) },
1836         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b7) },
1837         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b8) },
1838         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bc) },
1839         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bd) },
1840         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bf) },
1841         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c0) },
1842         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70f2) },
1843         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x710d) },
1844         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716c) },
1845         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716d) },
1846         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717f) },
1847         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71bc) },
1848         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717d) },
1849         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x72e8) },
1850         { 0 }
1851 };
1852 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1853
1854 static struct pci_driver ni_pcimio_pci_driver = {
1855         .name           = "ni_pcimio",
1856         .id_table       = ni_pcimio_pci_table,
1857         .probe          = ni_pcimio_pci_probe,
1858         .remove         = comedi_pci_auto_unconfig,
1859 };
1860 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1861
1862 MODULE_AUTHOR("Comedi http://www.comedi.org");
1863 MODULE_DESCRIPTION("Comedi low-level driver");
1864 MODULE_LICENSE("GPL");