3 Register descriptions for NI DAQ-STC chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 DAQ-STC Technical Reference Manual
29 #ifndef _COMEDI_NI_STC_H
30 #define _COMEDI_NI_STC_H
51 #define NUM_PFI_OUTPUT_SELECT_REGS 6
53 /* Registers in the National Instruments DAQ-STC chip */
55 #define Interrupt_A_Ack_Register 2
56 #define G0_Gate_Interrupt_Ack _bit15
57 #define G0_TC_Interrupt_Ack _bit14
58 #define AI_Error_Interrupt_Ack _bit13
59 #define AI_STOP_Interrupt_Ack _bit12
60 #define AI_START_Interrupt_Ack _bit11
61 #define AI_START2_Interrupt_Ack _bit10
62 #define AI_START1_Interrupt_Ack _bit9
63 #define AI_SC_TC_Interrupt_Ack _bit8
64 #define AI_SC_TC_Error_Confirm _bit7
65 #define G0_TC_Error_Confirm _bit6
66 #define G0_Gate_Error_Confirm _bit5
68 #define AI_Status_1_Register 2
69 #define Interrupt_A_St 0x8000
70 #define AI_FIFO_Full_St 0x4000
71 #define AI_FIFO_Half_Full_St 0x2000
72 #define AI_FIFO_Empty_St 0x1000
73 #define AI_Overrun_St 0x0800
74 #define AI_Overflow_St 0x0400
75 #define AI_SC_TC_Error_St 0x0200
76 #define AI_START2_St 0x0100
77 #define AI_START1_St 0x0080
78 #define AI_SC_TC_St 0x0040
79 #define AI_START_St 0x0020
80 #define AI_STOP_St 0x0010
81 #define G0_TC_St 0x0008
82 #define G0_Gate_Interrupt_St 0x0004
83 #define AI_FIFO_Request_St 0x0002
84 #define Pass_Thru_0_Interrupt_St 0x0001
86 #define AI_Status_2_Register 5
88 #define Interrupt_B_Ack_Register 3
89 enum Interrupt_B_Ack_Bits {
90 G1_Gate_Error_Confirm = _bit1,
91 G1_TC_Error_Confirm = _bit2,
92 AO_BC_TC_Trigger_Error_Confirm = _bit3,
93 AO_BC_TC_Error_Confirm = _bit4,
94 AO_UI2_TC_Error_Confrim = _bit5,
95 AO_UI2_TC_Interrupt_Ack = _bit6,
96 AO_UC_TC_Interrupt_Ack = _bit7,
97 AO_BC_TC_Interrupt_Ack = _bit8,
98 AO_START1_Interrupt_Ack = _bit9,
99 AO_UPDATE_Interrupt_Ack = _bit10,
100 AO_START_Interrupt_Ack = _bit11,
101 AO_STOP_Interrupt_Ack = _bit12,
102 AO_Error_Interrupt_Ack = _bit13,
103 G1_TC_Interrupt_Ack = _bit14,
104 G1_Gate_Interrupt_Ack = _bit15
107 #define AO_Status_1_Register 3
108 #define Interrupt_B_St _bit15
109 #define AO_FIFO_Full_St _bit14
110 #define AO_FIFO_Half_Full_St _bit13
111 #define AO_FIFO_Empty_St _bit12
112 #define AO_BC_TC_Error_St _bit11
113 #define AO_START_St _bit10
114 #define AO_Overrun_St _bit9
115 #define AO_START1_St _bit8
116 #define AO_BC_TC_St _bit7
117 #define AO_UC_TC_St _bit6
118 #define AO_UPDATE_St _bit5
119 #define AO_UI2_TC_St _bit4
120 #define G1_TC_St _bit3
121 #define G1_Gate_Interrupt_St _bit2
122 #define AO_FIFO_Request_St _bit1
123 #define Pass_Thru_1_Interrupt_St _bit0
125 #define AI_Command_2_Register 4
126 #define AI_End_On_SC_TC _bit15
127 #define AI_End_On_End_Of_Scan _bit14
128 #define AI_START1_Disable _bit11
129 #define AI_SC_Save_Trace _bit10
130 #define AI_SI_Switch_Load_On_SC_TC _bit9
131 #define AI_SI_Switch_Load_On_STOP _bit8
132 #define AI_SI_Switch_Load_On_TC _bit7
133 #define AI_SC_Switch_Load_On_TC _bit4
134 #define AI_STOP_Pulse _bit3
135 #define AI_START_Pulse _bit2
136 #define AI_START2_Pulse _bit1
137 #define AI_START1_Pulse _bit0
139 #define AO_Command_2_Register 5
140 #define AO_End_On_BC_TC(x) (((x) & 0x3) << 14)
141 #define AO_Start_Stop_Gate_Enable _bit13
142 #define AO_UC_Save_Trace _bit12
143 #define AO_BC_Gate_Enable _bit11
144 #define AO_BC_Save_Trace _bit10
145 #define AO_UI_Switch_Load_On_BC_TC _bit9
146 #define AO_UI_Switch_Load_On_Stop _bit8
147 #define AO_UI_Switch_Load_On_TC _bit7
148 #define AO_UC_Switch_Load_On_BC_TC _bit6
149 #define AO_UC_Switch_Load_On_TC _bit5
150 #define AO_BC_Switch_Load_On_TC _bit4
151 #define AO_Mute_B _bit3
152 #define AO_Mute_A _bit2
153 #define AO_UPDATE2_Pulse _bit1
154 #define AO_START1_Pulse _bit0
156 #define AO_Status_2_Register 6
158 #define DIO_Parallel_Input_Register 7
160 #define AI_Command_1_Register 8
161 #define AI_Analog_Trigger_Reset _bit14
162 #define AI_Disarm _bit13
163 #define AI_SI2_Arm _bit12
164 #define AI_SI2_Load _bit11
165 #define AI_SI_Arm _bit10
166 #define AI_SI_Load _bit9
167 #define AI_DIV_Arm _bit8
168 #define AI_DIV_Load _bit7
169 #define AI_SC_Arm _bit6
170 #define AI_SC_Load _bit5
171 #define AI_SCAN_IN_PROG_Pulse _bit4
172 #define AI_EXTMUX_CLK_Pulse _bit3
173 #define AI_LOCALMUX_CLK_Pulse _bit2
174 #define AI_SC_TC_Pulse _bit1
175 #define AI_CONVERT_Pulse _bit0
177 #define AO_Command_1_Register 9
178 #define AO_Analog_Trigger_Reset _bit15
179 #define AO_START_Pulse _bit14
180 #define AO_Disarm _bit13
181 #define AO_UI2_Arm_Disarm _bit12
182 #define AO_UI2_Load _bit11
183 #define AO_UI_Arm _bit10
184 #define AO_UI_Load _bit9
185 #define AO_UC_Arm _bit8
186 #define AO_UC_Load _bit7
187 #define AO_BC_Arm _bit6
188 #define AO_BC_Load _bit5
189 #define AO_DAC1_Update_Mode _bit4
190 #define AO_LDAC1_Source_Select _bit3
191 #define AO_DAC0_Update_Mode _bit2
192 #define AO_LDAC0_Source_Select _bit1
193 #define AO_UPDATE_Pulse _bit0
195 #define DIO_Output_Register 10
196 #define DIO_Parallel_Data_Out(a) ((a)&0xff)
197 #define DIO_Parallel_Data_Mask 0xff
198 #define DIO_SDOUT _bit0
199 #define DIO_SDIN _bit4
200 #define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
201 #define DIO_Serial_Data_Mask 0xff00
203 #define DIO_Control_Register 11
204 #define DIO_Software_Serial_Control _bit11
205 #define DIO_HW_Serial_Timebase _bit10
206 #define DIO_HW_Serial_Enable _bit9
207 #define DIO_HW_Serial_Start _bit8
208 #define DIO_Pins_Dir(a) ((a)&0xff)
209 #define DIO_Pins_Dir_Mask 0xff
211 #define AI_Mode_1_Register 12
212 #define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11)
213 #define AI_SI_Source_select(a) (((a) & 0x1f) << 6)
214 #define AI_CONVERT_Source_Polarity _bit5
215 #define AI_SI_Source_Polarity _bit4
216 #define AI_Start_Stop _bit3
217 #define AI_Mode_1_Reserved _bit2
218 #define AI_Continuous _bit1
219 #define AI_Trigger_Once _bit0
221 #define AI_Mode_2_Register 13
222 #define AI_SC_Gate_Enable _bit15
223 #define AI_Start_Stop_Gate_Enable _bit14
224 #define AI_Pre_Trigger _bit13
225 #define AI_External_MUX_Present _bit12
226 #define AI_SI2_Initial_Load_Source _bit9
227 #define AI_SI2_Reload_Mode _bit8
228 #define AI_SI_Initial_Load_Source _bit7
229 #define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4)
230 #define AI_SI_Write_Switch _bit3
231 #define AI_SC_Initial_Load_Source _bit2
232 #define AI_SC_Reload_Mode _bit1
233 #define AI_SC_Write_Switch _bit0
235 #define AI_SI_Load_A_Registers 14
236 #define AI_SI_Load_B_Registers 16
237 #define AI_SC_Load_A_Registers 18
238 #define AI_SC_Load_B_Registers 20
239 #define AI_SI_Save_Registers 64
240 #define AI_SC_Save_Registers 66
242 #define AI_SI2_Load_A_Register 23
243 #define AI_SI2_Load_B_Register 25
245 #define Joint_Status_1_Register 27
246 #define DIO_Serial_IO_In_Progress_St _bit12
248 #define DIO_Serial_Input_Register 28
249 #define Joint_Status_2_Register 29
250 enum Joint_Status_2_Bits {
251 AO_TMRDACWRs_In_Progress_St = 0x20,
254 #define AO_Mode_1_Register 38
255 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
256 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
257 #define AO_Multiple_Channels _bit5
258 #define AO_UPDATE_Source_Polarity _bit4
259 #define AO_UI_Source_Polarity _bit3
260 #define AO_UC_Switch_Load_Every_TC _bit2
261 #define AO_Continuous _bit1
262 #define AO_Trigger_Once _bit0
264 #define AO_Mode_2_Register 39
265 #define AO_FIFO_Mode_Mask (0x3 << 14)
266 enum AO_FIFO_Mode_Bits {
267 AO_FIFO_Mode_HF_to_F = (3 << 14),
268 AO_FIFO_Mode_F = (2 << 14),
269 AO_FIFO_Mode_HF = (1 << 14),
270 AO_FIFO_Mode_E = (0 << 14),
272 #define AO_FIFO_Retransmit_Enable _bit13
273 #define AO_START1_Disable _bit12
274 #define AO_UC_Initial_Load_Source _bit11
275 #define AO_UC_Write_Switch _bit10
276 #define AO_UI2_Initial_Load_Source _bit9
277 #define AO_UI2_Reload_Mode _bit8
278 #define AO_UI_Initial_Load_Source _bit7
279 #define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4)
280 #define AO_UI_Write_Switch _bit3
281 #define AO_BC_Initial_Load_Source _bit2
282 #define AO_BC_Reload_Mode _bit1
283 #define AO_BC_Write_Switch _bit0
285 #define AO_UI_Load_A_Register 40
286 #define AO_UI_Load_A_Register_High 40
287 #define AO_UI_Load_A_Register_Low 41
288 #define AO_UI_Load_B_Register 42
289 #define AO_UI_Save_Registers 16
290 #define AO_BC_Load_A_Register 44
291 #define AO_BC_Load_A_Register_High 44
292 #define AO_BC_Load_A_Register_Low 45
293 #define AO_BC_Load_B_Register 46
294 #define AO_BC_Load_B_Register_High 46
295 #define AO_BC_Load_B_Register_Low 47
296 #define AO_BC_Save_Registers 18
297 #define AO_UC_Load_A_Register 48
298 #define AO_UC_Load_A_Register_High 48
299 #define AO_UC_Load_A_Register_Low 49
300 #define AO_UC_Load_B_Register 50
301 #define AO_UC_Save_Registers 20
303 #define Clock_and_FOUT_Register 56
304 enum Clock_and_FOUT_bits {
305 FOUT_Enable = _bit15,
306 FOUT_Timebase_Select = _bit14,
307 DIO_Serial_Out_Divide_By_2 = _bit13,
308 Slow_Internal_Time_Divide_By_2 = _bit12,
309 Slow_Internal_Timebase = _bit11,
310 G_Source_Divide_By_2 = _bit10,
311 Clock_To_Board_Divide_By_2 = _bit9,
312 Clock_To_Board = _bit8,
313 AI_Output_Divide_By_2 = _bit7,
314 AI_Source_Divide_By_2 = _bit6,
315 AO_Output_Divide_By_2 = _bit5,
316 AO_Source_Divide_By_2 = _bit4,
317 FOUT_Divider_mask = 0xf
319 static inline unsigned FOUT_Divider(unsigned divider)
321 return divider & FOUT_Divider_mask;
324 #define IO_Bidirection_Pin_Register 57
325 #define RTSI_Trig_Direction_Register 58
326 enum RTSI_Trig_Direction_Bits {
327 Drive_RTSI_Clock_Bit = 0x1,
328 Use_RTSI_Clock_Bit = 0x2,
330 static inline unsigned RTSI_Output_Bit(unsigned channel, int is_mseries)
332 unsigned max_channel;
333 unsigned base_bit_shift;
341 if (channel > max_channel) {
342 printk("%s: bug, invalid RTSI_channel=%i\n", __func__,
346 return 1 << (base_bit_shift + channel);
349 #define Interrupt_Control_Register 59
350 #define Interrupt_B_Enable _bit15
351 #define Interrupt_B_Output_Select(x) ((x)<<12)
352 #define Interrupt_A_Enable _bit11
353 #define Interrupt_A_Output_Select(x) ((x)<<8)
354 #define Pass_Thru_0_Interrupt_Polarity _bit3
355 #define Pass_Thru_1_Interrupt_Polarity _bit2
356 #define Interrupt_Output_On_3_Pins _bit1
357 #define Interrupt_Output_Polarity _bit0
359 #define AI_Output_Control_Register 60
360 #define AI_START_Output_Select _bit10
361 #define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8)
362 #define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6)
363 #define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4)
364 #define AI_SC_TC_Output_Select(x) ((x)<<2)
365 enum ai_convert_output_selection {
366 AI_CONVERT_Output_High_Z = 0,
367 AI_CONVERT_Output_Ground = 1,
368 AI_CONVERT_Output_Enable_Low = 2,
369 AI_CONVERT_Output_Enable_High = 3
371 static unsigned AI_CONVERT_Output_Select(enum ai_convert_output_selection
374 return selection & 0x3;
377 #define AI_START_STOP_Select_Register 62
378 #define AI_START_Polarity _bit15
379 #define AI_STOP_Polarity _bit14
380 #define AI_STOP_Sync _bit13
381 #define AI_STOP_Edge _bit12
382 #define AI_STOP_Select(a) (((a) & 0x1f)<<7)
383 #define AI_START_Sync _bit6
384 #define AI_START_Edge _bit5
385 #define AI_START_Select(a) ((a) & 0x1f)
387 #define AI_Trigger_Select_Register 63
388 #define AI_START1_Polarity _bit15
389 #define AI_START2_Polarity _bit14
390 #define AI_START2_Sync _bit13
391 #define AI_START2_Edge _bit12
392 #define AI_START2_Select(a) (((a) & 0x1f) << 7)
393 #define AI_START1_Sync _bit6
394 #define AI_START1_Edge _bit5
395 #define AI_START1_Select(a) ((a) & 0x1f)
397 #define AI_DIV_Load_A_Register 64
399 #define AO_Start_Select_Register 66
400 #define AO_UI2_Software_Gate _bit15
401 #define AO_UI2_External_Gate_Polarity _bit14
402 #define AO_START_Polarity _bit13
403 #define AO_AOFREQ_Enable _bit12
404 #define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7)
405 #define AO_START_Sync _bit6
406 #define AO_START_Edge _bit5
407 #define AO_START_Select(a) ((a) & 0x1f)
409 #define AO_Trigger_Select_Register 67
410 #define AO_UI2_External_Gate_Enable _bit15
411 #define AO_Delayed_START1 _bit14
412 #define AO_START1_Polarity _bit13
413 #define AO_UI2_Source_Polarity _bit12
414 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
415 #define AO_START1_Sync _bit6
416 #define AO_START1_Edge _bit5
417 #define AO_START1_Select(x) (((x)&0x1f)<<0)
419 #define AO_Mode_3_Register 70
420 #define AO_UI2_Switch_Load_Next_TC _bit13
421 #define AO_UC_Switch_Load_Every_BC_TC _bit12
422 #define AO_Trigger_Length _bit11
423 #define AO_Stop_On_Overrun_Error _bit5
424 #define AO_Stop_On_BC_TC_Trigger_Error _bit4
425 #define AO_Stop_On_BC_TC_Error _bit3
426 #define AO_Not_An_UPDATE _bit2
427 #define AO_Software_Gate _bit1
428 #define AO_Last_Gate_Disable _bit0 /* M Series only */
430 #define Joint_Reset_Register 72
431 #define Software_Reset _bit11
432 #define AO_Configuration_End _bit9
433 #define AI_Configuration_End _bit8
434 #define AO_Configuration_Start _bit5
435 #define AI_Configuration_Start _bit4
436 #define G1_Reset _bit3
437 #define G0_Reset _bit2
438 #define AO_Reset _bit1
439 #define AI_Reset _bit0
441 #define Interrupt_A_Enable_Register 73
442 #define Pass_Thru_0_Interrupt_Enable _bit9
443 #define G0_Gate_Interrupt_Enable _bit8
444 #define AI_FIFO_Interrupt_Enable _bit7
445 #define G0_TC_Interrupt_Enable _bit6
446 #define AI_Error_Interrupt_Enable _bit5
447 #define AI_STOP_Interrupt_Enable _bit4
448 #define AI_START_Interrupt_Enable _bit3
449 #define AI_START2_Interrupt_Enable _bit2
450 #define AI_START1_Interrupt_Enable _bit1
451 #define AI_SC_TC_Interrupt_Enable _bit0
453 #define Interrupt_B_Enable_Register 75
454 #define Pass_Thru_1_Interrupt_Enable _bit11
455 #define G1_Gate_Interrupt_Enable _bit10
456 #define G1_TC_Interrupt_Enable _bit9
457 #define AO_FIFO_Interrupt_Enable _bit8
458 #define AO_UI2_TC_Interrupt_Enable _bit7
459 #define AO_UC_TC_Interrupt_Enable _bit6
460 #define AO_Error_Interrupt_Enable _bit5
461 #define AO_STOP_Interrupt_Enable _bit4
462 #define AO_START_Interrupt_Enable _bit3
463 #define AO_UPDATE_Interrupt_Enable _bit2
464 #define AO_START1_Interrupt_Enable _bit1
465 #define AO_BC_TC_Interrupt_Enable _bit0
467 #define Second_IRQ_A_Enable_Register 74
468 enum Second_IRQ_A_Enable_Bits {
469 AI_SC_TC_Second_Irq_Enable = _bit0,
470 AI_START1_Second_Irq_Enable = _bit1,
471 AI_START2_Second_Irq_Enable = _bit2,
472 AI_START_Second_Irq_Enable = _bit3,
473 AI_STOP_Second_Irq_Enable = _bit4,
474 AI_Error_Second_Irq_Enable = _bit5,
475 G0_TC_Second_Irq_Enable = _bit6,
476 AI_FIFO_Second_Irq_Enable = _bit7,
477 G0_Gate_Second_Irq_Enable = _bit8,
478 Pass_Thru_0_Second_Irq_Enable = _bit9
481 #define Second_IRQ_B_Enable_Register 76
482 enum Second_IRQ_B_Enable_Bits {
483 AO_BC_TC_Second_Irq_Enable = _bit0,
484 AO_START1_Second_Irq_Enable = _bit1,
485 AO_UPDATE_Second_Irq_Enable = _bit2,
486 AO_START_Second_Irq_Enable = _bit3,
487 AO_STOP_Second_Irq_Enable = _bit4,
488 AO_Error_Second_Irq_Enable = _bit5,
489 AO_UC_TC_Second_Irq_Enable = _bit6,
490 AO_UI2_TC_Second_Irq_Enable = _bit7,
491 AO_FIFO_Second_Irq_Enable = _bit8,
492 G1_TC_Second_Irq_Enable = _bit9,
493 G1_Gate_Second_Irq_Enable = _bit10,
494 Pass_Thru_1_Second_Irq_Enable = _bit11
497 #define AI_Personal_Register 77
498 #define AI_SHIFTIN_Pulse_Width _bit15
499 #define AI_EOC_Polarity _bit14
500 #define AI_SOC_Polarity _bit13
501 #define AI_SHIFTIN_Polarity _bit12
502 #define AI_CONVERT_Pulse_Timebase _bit11
503 #define AI_CONVERT_Pulse_Width _bit10
504 #define AI_CONVERT_Original_Pulse _bit9
505 #define AI_FIFO_Flags_Polarity _bit8
506 #define AI_Overrun_Mode _bit7
507 #define AI_EXTMUX_CLK_Pulse_Width _bit6
508 #define AI_LOCALMUX_CLK_Pulse_Width _bit5
509 #define AI_AIFREQ_Polarity _bit4
511 #define AO_Personal_Register 78
512 enum AO_Personal_Bits {
513 AO_Interval_Buffer_Mode = 1 << 3,
514 AO_BC_Source_Select = 1 << 4,
515 AO_UPDATE_Pulse_Width = 1 << 5,
516 AO_UPDATE_Pulse_Timebase = 1 << 6,
517 AO_UPDATE_Original_Pulse = 1 << 7,
518 AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */
519 AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */
520 AO_FIFO_Enable = 1 << 10,
521 AO_FIFO_Flags_Polarity = 1 << 11, /* M Series: reserved */
522 AO_TMRDACWR_Pulse_Width = 1 << 12,
523 AO_Fast_CPU = 1 << 13, /* M Series: reserved */
524 AO_Number_Of_DAC_Packages = 1 << 14, /* 1 for "single" mode, 0 for "dual" */
525 AO_Multiple_DACS_Per_Package = 1 << 15 /* m-series only */
527 #define RTSI_Trig_A_Output_Register 79
528 #define RTSI_Trig_B_Output_Register 80
529 enum RTSI_Trig_B_Output_Bits {
530 RTSI_Sub_Selection_1_Bit = 0x8000 /* not for m-series */
532 static inline unsigned RTSI_Trig_Output_Bits(unsigned rtsi_channel,
535 return (source & 0xf) << ((rtsi_channel % 4) * 4);
537 static inline unsigned RTSI_Trig_Output_Mask(unsigned rtsi_channel)
539 return 0xf << ((rtsi_channel % 4) * 4);
542 /* inverse to RTSI_Trig_Output_Bits() */
543 static inline unsigned RTSI_Trig_Output_Source(unsigned rtsi_channel,
546 return (bits >> ((rtsi_channel % 4) * 4)) & 0xf;
549 #define RTSI_Board_Register 81
550 #define Write_Strobe_0_Register 82
551 #define Write_Strobe_1_Register 83
552 #define Write_Strobe_2_Register 84
553 #define Write_Strobe_3_Register 85
555 #define AO_Output_Control_Register 86
556 #define AO_External_Gate_Enable _bit15
557 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
558 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
559 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
560 #define AO_External_Gate_Polarity _bit3
561 #define AO_UPDATE2_Output_Toggle _bit2
562 enum ao_update_output_selection {
563 AO_Update_Output_High_Z = 0,
564 AO_Update_Output_Ground = 1,
565 AO_Update_Output_Enable_Low = 2,
566 AO_Update_Output_Enable_High = 3
568 static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection
571 return selection & 0x3;
574 #define AI_Mode_3_Register 87
575 #define AI_Trigger_Length _bit15
576 #define AI_Delay_START _bit14
577 #define AI_Software_Gate _bit13
578 #define AI_SI_Special_Trigger_Delay _bit12
579 #define AI_SI2_Source_Select _bit11
580 #define AI_Delayed_START2 _bit10
581 #define AI_Delayed_START1 _bit9
582 #define AI_External_Gate_Mode _bit8
583 #define AI_FIFO_Mode_HF_to_E (3<<6)
584 #define AI_FIFO_Mode_F (2<<6)
585 #define AI_FIFO_Mode_HF (1<<6)
586 #define AI_FIFO_Mode_NE (0<<6)
587 #define AI_External_Gate_Polarity _bit5
588 #define AI_External_Gate_Select(a) ((a) & 0x1f)
590 #define G_Autoincrement_Register(a) (68+(a))
591 #define G_Command_Register(a) (6+(a))
592 #define G_HW_Save_Register(a) (8+(a)*2)
593 #define G_HW_Save_Register_High(a) (8+(a)*2)
594 #define G_HW_Save_Register_Low(a) (9+(a)*2)
595 #define G_Input_Select_Register(a) (36+(a))
596 #define G_Load_A_Register(a) (28+(a)*4)
597 #define G_Load_A_Register_High(a) (28+(a)*4)
598 #define G_Load_A_Register_Low(a) (29+(a)*4)
599 #define G_Load_B_Register(a) (30+(a)*4)
600 #define G_Load_B_Register_High(a) (30+(a)*4)
601 #define G_Load_B_Register_Low(a) (31+(a)*4)
602 #define G_Mode_Register(a) (26+(a))
603 #define G_Save_Register(a) (12+(a)*2)
604 #define G_Save_Register_High(a) (12+(a)*2)
605 #define G_Save_Register_Low(a) (13+(a)*2)
606 #define G_Status_Register 4
607 #define Analog_Trigger_Etc_Register 61
609 /* command register */
610 #define G_Disarm_Copy _bit15 /* strobe */
611 #define G_Save_Trace_Copy _bit14
612 #define G_Arm_Copy _bit13 /* strobe */
613 #define G_Bank_Switch_Start _bit10 /* strobe */
614 #define G_Little_Big_Endian _bit9
615 #define G_Synchronized_Gate _bit8
616 #define G_Write_Switch _bit7
617 #define G_Up_Down(a) (((a)&0x03)<<5)
618 #define G_Disarm _bit4 /* strobe */
619 #define G_Analog_Trigger_Reset _bit3 /* strobe */
620 #define G_Save_Trace _bit1
621 #define G_Arm _bit0 /* strobe */
623 /*channel agnostic names for the command register #defines */
624 #define G_Bank_Switch_Enable _bit12
625 #define G_Bank_Switch_Mode _bit11
626 #define G_Load _bit2 /* strobe */
628 /* input select register */
629 #define G_Gate_Select(a) (((a)&0x1f)<<7)
630 #define G_Source_Select(a) (((a)&0x1f)<<2)
631 #define G_Write_Acknowledges_Irq _bit1
632 #define G_Read_Acknowledges_Irq _bit0
634 /* same input select register, but with channel agnostic names */
635 #define G_Source_Polarity _bit15
636 #define G_Output_Polarity _bit14
637 #define G_OR_Gate _bit13
638 #define G_Gate_Select_Load_Source _bit12
641 #define G_Loading_On_TC _bit12
642 #define G_Output_Mode(a) (((a)&0x03)<<8)
643 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
644 #define G_Gating_Mode(a) (((a)&0x03)<<0)
646 /* same input mode register, but with channel agnostic names */
647 #define G_Load_Source_Select _bit7
648 #define G_Reload_Source_Switching _bit15
649 #define G_Loading_On_Gate _bit14
650 #define G_Gate_Polarity _bit13
652 #define G_Counting_Once(a) (((a)&0x03)<<10)
653 #define G_Stop_Mode(a) (((a)&0x03)<<5)
654 #define G_Gate_On_Both_Edges _bit2
656 /* G_Status_Register */
657 #define G1_Gate_Error_St _bit15
658 #define G0_Gate_Error_St _bit14
659 #define G1_TC_Error_St _bit13
660 #define G0_TC_Error_St _bit12
661 #define G1_No_Load_Between_Gates_St _bit11
662 #define G0_No_Load_Between_Gates_St _bit10
663 #define G1_Armed_St _bit9
664 #define G0_Armed_St _bit8
665 #define G1_Stale_Data_St _bit7
666 #define G0_Stale_Data_St _bit6
667 #define G1_Next_Load_Source_St _bit5
668 #define G0_Next_Load_Source_St _bit4
669 #define G1_Counting_St _bit3
670 #define G0_Counting_St _bit2
671 #define G1_Save_St _bit1
672 #define G0_Save_St _bit0
674 /* general purpose counter timer */
675 #define G_Autoincrement(a) ((a)<<0)
677 /*Analog_Trigger_Etc_Register*/
678 #define Analog_Trigger_Mode(x) ((x) & 0x7)
679 #define Analog_Trigger_Enable _bit3
680 #define Analog_Trigger_Drive _bit4
681 #define GPFO_1_Output_Select _bit7
682 #define GPFO_0_Output_Select(a) ((a)<<11)
683 #define GPFO_0_Output_Enable _bit14
684 #define GPFO_1_Output_Enable _bit15
686 /* Additional windowed registers unique to E series */
688 /* 16 bit registers shadowed from DAQ-STC */
689 #define Window_Address 0x00
690 #define Window_Data 0x02
692 #define Configuration_Memory_Clear 82
693 #define ADC_FIFO_Clear 83
694 #define DAC_FIFO_Clear 84
696 /* i/o port offsets */
698 /* 8 bit registers */
699 #define XXX_Status 0x01
700 enum XXX_Status_Bits {
702 AI_FIFO_LOWER_NOT_EMPTY = 0x8,
704 #define Serial_Command 0x0d
705 #define Misc_Command 0x0f
709 #define Configuration 0x1f
711 #define Channel_A_Mode 0x03
712 #define Channel_B_Mode 0x05
713 #define Channel_C_Mode 0x07
714 #define AI_AO_Select 0x09
715 enum AI_AO_Select_Bits {
716 AI_DMA_Select_Shift = 0,
717 AI_DMA_Select_Mask = 0xf,
718 AO_DMA_Select_Shift = 4,
719 AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift
721 #define G0_G1_Select 0x0b
722 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
733 static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index,
734 unsigned mite_channel)
736 BUG_ON(gpct_index > 1);
737 return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 *
740 static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index)
742 BUG_ON(gpct_index > 1);
743 return 0xf << (4 * gpct_index);
746 /* 16 bit registers */
748 #define Configuration_Memory_Low 0x10
749 enum Configuration_Memory_Low_Bits {
751 AI_LAST_CHANNEL = 0x8000,
753 #define Configuration_Memory_High 0x12
754 enum Configuration_Memory_High_Bits {
755 AI_AC_COUPLE = 0x800,
756 AI_DIFFERENTIAL = 0x1000,
760 static inline unsigned int AI_CONFIG_CHANNEL(unsigned int channel)
762 return channel & 0x3f;
765 #define ADC_FIFO_Data_Register 0x1c
767 #define AO_Configuration 0x16
768 #define AO_Bipolar _bit0
769 #define AO_Deglitch _bit1
770 #define AO_Ext_Ref _bit2
771 #define AO_Ground_Ref _bit3
772 #define AO_Channel(x) ((x) << 8)
774 #define DAC_FIFO_Data 0x1e
775 #define DAC0_Direct_Data 0x18
776 #define DAC1_Direct_Data 0x1a
778 /* 611x registers (these boards differ from the e-series) */
780 #define Magic_611x 0x19 /* w8 (new) */
781 #define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
782 #define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */
783 #define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */
784 #define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */
785 #define Cal_Gain_Select_611x 0x05 /* w8 (new) */
787 #define AO_Window_Address_611x 0x18
788 #define AO_Window_Data_611x 0x1e
791 #define Magic_6143 0x19 /* w8 */
792 #define G0G1_DMA_Select_6143 0x0B /* w8 */
793 #define PipelineDelay_6143 0x1f /* w8 */
794 #define EOC_Set_6143 0x1D /* w8 */
795 #define AIDMA_Select_6143 0x09 /* w8 */
796 #define AIFIFO_Data_6143 0x8C /* w32 */
797 #define AIFIFO_Flag_6143 0x84 /* w32 */
798 #define AIFIFO_Control_6143 0x88 /* w32 */
799 #define AIFIFO_Status_6143 0x88 /* w32 */
800 #define AIFIFO_DMAThreshold_6143 0x90 /* w32 */
801 #define AIFIFO_Words_Available_6143 0x94 /* w32 */
803 #define Calibration_Channel_6143 0x42 /* w16 */
804 #define Calibration_LowTime_6143 0x20 /* w16 */
805 #define Calibration_HighTime_6143 0x22 /* w16 */
806 #define Relay_Counter_Load_Val__6143 0x4C /* w32 */
807 #define Signature_6143 0x50 /* w32 */
808 #define Release_Date_6143 0x54 /* w32 */
809 #define Release_Oldest_Date_6143 0x58 /* w32 */
811 #define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */
812 #define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */
813 #define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */
814 #define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */
815 #define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */
816 #define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */
817 #define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */
818 #define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */
820 /* 671x, 611x registers */
822 /* 671xi, 611x windowed ao registers */
823 enum windowed_regs_67xx_61xx {
824 AO_Immediate_671x = 0x11, /* W 16 */
825 AO_Timed_611x = 0x10, /* W 16 */
826 AO_FIFO_Offset_Load_611x = 0x13, /* W32 */
827 AO_Later_Single_Point_Updates = 0x14, /* W 16 */
828 AO_Waveform_Generation_611x = 0x15, /* W 16 */
829 AO_Misc_611x = 0x16, /* W 16 */
830 AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */
831 AO_Configuration_2_67xx = 0x18, /* W 16 */
832 CAL_ADC_Command_67xx = 0x19, /* W 8 */
833 CAL_ADC_Status_67xx = 0x1a, /* R 8 */
834 CAL_ADC_Data_67xx = 0x1b, /* R 16 */
835 CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */
836 CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */
838 static inline unsigned int DACx_Direct_Data_671x(int channel)
842 enum AO_Misc_611x_Bits {
845 enum cs5529_configuration_bits {
846 CSCFG_CAL_CONTROL_MASK = 0x7,
847 CSCFG_SELF_CAL_OFFSET = 0x1,
848 CSCFG_SELF_CAL_GAIN = 0x2,
849 CSCFG_SELF_CAL_OFFSET_GAIN = 0x3,
850 CSCFG_SYSTEM_CAL_OFFSET = 0x5,
851 CSCFG_SYSTEM_CAL_GAIN = 0x6,
853 CSCFG_POWER_SAVE_SELECT = 1 << 4,
854 CSCFG_PORT_MODE = 1 << 5,
855 CSCFG_RESET_VALID = 1 << 6,
856 CSCFG_RESET = 1 << 7,
857 CSCFG_UNIPOLAR = 1 << 12,
858 CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13,
859 CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13,
860 CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13,
861 CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13,
862 CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13,
863 CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13,
864 CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13,
865 CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13,
866 CSCFG_WORD_RATE_MASK = 0x7 << 13,
867 CSCFG_LOW_POWER = 1 << 16,
869 static inline unsigned int CS5529_CONFIG_DOUT(int output)
871 return 1 << (18 + output);
873 static inline unsigned int CS5529_CONFIG_AOUT(int output)
875 return 1 << (22 + output);
877 enum cs5529_command_bits {
878 CSCMD_POWER_SAVE = 0x1,
879 CSCMD_REGISTER_SELECT_MASK = 0xe,
880 CSCMD_OFFSET_REGISTER = 0x0,
881 CSCMD_GAIN_REGISTER = 0x2,
882 CSCMD_CONFIG_REGISTER = 0x4,
884 CSCMD_CONTINUOUS_CONVERSIONS = 0x20,
885 CSCMD_SINGLE_CONVERSION = 0x40,
886 CSCMD_COMMAND = 0x80,
888 enum cs5529_status_bits {
890 CSS_OSC_DETECT = 0x2, /* indicates adc error */
893 #define SerDacLd(x) (0x08<<(x))
896 This is stuff unique to the NI E series drivers,
897 but I thought I'd put it here anyway.
901 0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x,
902 ai_gain_628x, ai_gain_6143 };
903 enum caldac_enum { caldac_none = 0, mb88341, dac8800, dac8043, ad8522,
904 ad8804, ad8842, ad8804_debug
911 ni_reg_67xx_mask = 0x6,
912 ni_reg_6xxx_mask = 0x7,
916 ni_reg_m_series_mask = 0x18,
920 static const struct comedi_lrange range_ni_E_ao_ext;
922 enum m_series_register_offsets {
923 M_Offset_CDIO_DMA_Select = 0x7, /* write */
924 M_Offset_SCXI_Status = 0x7, /* read */
925 M_Offset_AI_AO_Select = 0x9, /* write, same offset as e-series */
926 M_Offset_SCXI_Serial_Data_In = 0x9, /* read */
927 M_Offset_G0_G1_Select = 0xb, /* write, same offset as e-series */
928 M_Offset_Misc_Command = 0xf,
929 M_Offset_SCXI_Serial_Data_Out = 0x11,
930 M_Offset_SCXI_Control = 0x13,
931 M_Offset_SCXI_Output_Enable = 0x15,
932 M_Offset_AI_FIFO_Data = 0x1c,
933 M_Offset_Static_Digital_Output = 0x24, /* write */
934 M_Offset_Static_Digital_Input = 0x24, /* read */
935 M_Offset_DIO_Direction = 0x28,
936 M_Offset_Cal_PWM = 0x40,
937 M_Offset_AI_Config_FIFO_Data = 0x5e,
938 M_Offset_Interrupt_C_Enable = 0x88, /* write */
939 M_Offset_Interrupt_C_Status = 0x88, /* read */
940 M_Offset_Analog_Trigger_Control = 0x8c,
941 M_Offset_AO_Serial_Interrupt_Enable = 0xa0,
942 M_Offset_AO_Serial_Interrupt_Ack = 0xa1, /* write */
943 M_Offset_AO_Serial_Interrupt_Status = 0xa1, /* read */
944 M_Offset_AO_Calibration = 0xa3,
945 M_Offset_AO_FIFO_Data = 0xa4,
946 M_Offset_PFI_Filter = 0xb0,
947 M_Offset_RTSI_Filter = 0xb4,
948 M_Offset_SCXI_Legacy_Compatibility = 0xbc,
949 M_Offset_Interrupt_A_Ack = 0x104, /* write */
950 M_Offset_AI_Status_1 = 0x104, /* read */
951 M_Offset_Interrupt_B_Ack = 0x106, /* write */
952 M_Offset_AO_Status_1 = 0x106, /* read */
953 M_Offset_AI_Command_2 = 0x108, /* write */
954 M_Offset_G01_Status = 0x108, /* read */
955 M_Offset_AO_Command_2 = 0x10a,
956 M_Offset_AO_Status_2 = 0x10c, /* read */
957 M_Offset_G0_Command = 0x10c, /* write */
958 M_Offset_G1_Command = 0x10e, /* write */
959 M_Offset_G0_HW_Save = 0x110,
960 M_Offset_G0_HW_Save_High = 0x110,
961 M_Offset_AI_Command_1 = 0x110,
962 M_Offset_G0_HW_Save_Low = 0x112,
963 M_Offset_AO_Command_1 = 0x112,
964 M_Offset_G1_HW_Save = 0x114,
965 M_Offset_G1_HW_Save_High = 0x114,
966 M_Offset_G1_HW_Save_Low = 0x116,
967 M_Offset_AI_Mode_1 = 0x118,
968 M_Offset_G0_Save = 0x118,
969 M_Offset_G0_Save_High = 0x118,
970 M_Offset_AI_Mode_2 = 0x11a,
971 M_Offset_G0_Save_Low = 0x11a,
972 M_Offset_AI_SI_Load_A = 0x11c,
973 M_Offset_G1_Save = 0x11c,
974 M_Offset_G1_Save_High = 0x11c,
975 M_Offset_G1_Save_Low = 0x11e,
976 M_Offset_AI_SI_Load_B = 0x120, /* write */
977 M_Offset_AO_UI_Save = 0x120, /* read */
978 M_Offset_AI_SC_Load_A = 0x124, /* write */
979 M_Offset_AO_BC_Save = 0x124, /* read */
980 M_Offset_AI_SC_Load_B = 0x128, /* write */
981 M_Offset_AO_UC_Save = 0x128, /* read */
982 M_Offset_AI_SI2_Load_A = 0x12c,
983 M_Offset_AI_SI2_Load_B = 0x130,
984 M_Offset_G0_Mode = 0x134,
985 M_Offset_G1_Mode = 0x136, /* write */
986 M_Offset_Joint_Status_1 = 0x136, /* read */
987 M_Offset_G0_Load_A = 0x138,
988 M_Offset_Joint_Status_2 = 0x13a,
989 M_Offset_G0_Load_B = 0x13c,
990 M_Offset_G1_Load_A = 0x140,
991 M_Offset_G1_Load_B = 0x144,
992 M_Offset_G0_Input_Select = 0x148,
993 M_Offset_G1_Input_Select = 0x14a,
994 M_Offset_AO_Mode_1 = 0x14c,
995 M_Offset_AO_Mode_2 = 0x14e,
996 M_Offset_AO_UI_Load_A = 0x150,
997 M_Offset_AO_UI_Load_B = 0x154,
998 M_Offset_AO_BC_Load_A = 0x158,
999 M_Offset_AO_BC_Load_B = 0x15c,
1000 M_Offset_AO_UC_Load_A = 0x160,
1001 M_Offset_AO_UC_Load_B = 0x164,
1002 M_Offset_Clock_and_FOUT = 0x170,
1003 M_Offset_IO_Bidirection_Pin = 0x172,
1004 M_Offset_RTSI_Trig_Direction = 0x174,
1005 M_Offset_Interrupt_Control = 0x176,
1006 M_Offset_AI_Output_Control = 0x178,
1007 M_Offset_Analog_Trigger_Etc = 0x17a,
1008 M_Offset_AI_START_STOP_Select = 0x17c,
1009 M_Offset_AI_Trigger_Select = 0x17e,
1010 M_Offset_AI_SI_Save = 0x180, /* read */
1011 M_Offset_AI_DIV_Load_A = 0x180, /* write */
1012 M_Offset_AI_SC_Save = 0x184, /* read */
1013 M_Offset_AO_Start_Select = 0x184, /* write */
1014 M_Offset_AO_Trigger_Select = 0x186,
1015 M_Offset_AO_Mode_3 = 0x18c,
1016 M_Offset_G0_Autoincrement = 0x188,
1017 M_Offset_G1_Autoincrement = 0x18a,
1018 M_Offset_Joint_Reset = 0x190,
1019 M_Offset_Interrupt_A_Enable = 0x192,
1020 M_Offset_Interrupt_B_Enable = 0x196,
1021 M_Offset_AI_Personal = 0x19a,
1022 M_Offset_AO_Personal = 0x19c,
1023 M_Offset_RTSI_Trig_A_Output = 0x19e,
1024 M_Offset_RTSI_Trig_B_Output = 0x1a0,
1025 M_Offset_RTSI_Shared_MUX = 0x1a2,
1026 M_Offset_AO_Output_Control = 0x1ac,
1027 M_Offset_AI_Mode_3 = 0x1ae,
1028 M_Offset_Configuration_Memory_Clear = 0x1a4,
1029 M_Offset_AI_FIFO_Clear = 0x1a6,
1030 M_Offset_AO_FIFO_Clear = 0x1a8,
1031 M_Offset_G0_Counting_Mode = 0x1b0,
1032 M_Offset_G1_Counting_Mode = 0x1b2,
1033 M_Offset_G0_Second_Gate = 0x1b4,
1034 M_Offset_G1_Second_Gate = 0x1b6,
1035 M_Offset_G0_DMA_Config = 0x1b8, /* write */
1036 M_Offset_G0_DMA_Status = 0x1b8, /* read */
1037 M_Offset_G1_DMA_Config = 0x1ba, /* write */
1038 M_Offset_G1_DMA_Status = 0x1ba, /* read */
1039 M_Offset_G0_MSeries_ABZ = 0x1c0,
1040 M_Offset_G1_MSeries_ABZ = 0x1c2,
1041 M_Offset_Clock_and_Fout2 = 0x1c4,
1042 M_Offset_PLL_Control = 0x1c6,
1043 M_Offset_PLL_Status = 0x1c8,
1044 M_Offset_PFI_Output_Select_1 = 0x1d0,
1045 M_Offset_PFI_Output_Select_2 = 0x1d2,
1046 M_Offset_PFI_Output_Select_3 = 0x1d4,
1047 M_Offset_PFI_Output_Select_4 = 0x1d6,
1048 M_Offset_PFI_Output_Select_5 = 0x1d8,
1049 M_Offset_PFI_Output_Select_6 = 0x1da,
1050 M_Offset_PFI_DI = 0x1dc,
1051 M_Offset_PFI_DO = 0x1de,
1052 M_Offset_AI_Config_FIFO_Bypass = 0x218,
1053 M_Offset_SCXI_DIO_Enable = 0x21c,
1054 M_Offset_CDI_FIFO_Data = 0x220, /* read */
1055 M_Offset_CDO_FIFO_Data = 0x220, /* write */
1056 M_Offset_CDIO_Status = 0x224, /* read */
1057 M_Offset_CDIO_Command = 0x224, /* write */
1058 M_Offset_CDI_Mode = 0x228,
1059 M_Offset_CDO_Mode = 0x22c,
1060 M_Offset_CDI_Mask_Enable = 0x230,
1061 M_Offset_CDO_Mask_Enable = 0x234,
1063 static inline int M_Offset_AO_Waveform_Order(int channel)
1065 return 0xc2 + 0x4 * channel;
1067 static inline int M_Offset_AO_Config_Bank(int channel)
1069 return 0xc3 + 0x4 * channel;
1071 static inline int M_Offset_DAC_Direct_Data(int channel)
1073 return 0xc0 + 0x4 * channel;
1075 static inline int M_Offset_Gen_PWM(int channel)
1077 return 0x44 + 0x2 * channel;
1079 static inline int M_Offset_Static_AI_Control(int i)
1087 if (((unsigned)i) >= ARRAY_SIZE(offset)) {
1088 printk("%s: invalid channel=%i\n", __func__, i);
1093 static inline int M_Offset_AO_Reference_Attenuation(int channel)
1101 if (((unsigned)channel) >= ARRAY_SIZE(offset)) {
1102 printk("%s: invalid channel=%i\n", __func__, channel);
1105 return offset[channel];
1107 static inline unsigned M_Offset_PFI_Output_Select(unsigned n)
1109 if (n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS) {
1110 printk("%s: invalid pfi output select register=%i\n",
1112 return M_Offset_PFI_Output_Select_1;
1114 return M_Offset_PFI_Output_Select_1 + (n - 1) * 2;
1117 enum MSeries_AI_Config_FIFO_Data_Bits {
1118 MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6,
1119 MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0,
1120 MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6,
1121 MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6,
1122 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6,
1123 MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6,
1124 MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6,
1125 MSeries_AI_Config_Polarity_Bit = 0x1000, /* 0 for 2's complement encoding */
1126 MSeries_AI_Config_Dither_Bit = 0x2000,
1127 MSeries_AI_Config_Last_Channel_Bit = 0x4000,
1129 static inline unsigned MSeries_AI_Config_Channel_Bits(unsigned channel)
1131 return channel & 0xf;
1133 static inline unsigned MSeries_AI_Config_Bank_Bits(enum ni_reg_type reg_type,
1136 unsigned bits = channel & 0x30;
1137 if (reg_type == ni_reg_622x) {
1143 static inline unsigned MSeries_AI_Config_Gain_Bits(unsigned range)
1145 return (range & 0x7) << 9;
1148 enum MSeries_Clock_and_Fout2_Bits {
1149 MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb,
1150 MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14,
1151 MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b,
1152 MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d,
1153 MSeries_PLL_In_Source_Select_Mask = 0x1f,
1154 MSeries_Timebase1_Select_Bit = 0x20, /* use PLL for timebase 1 */
1155 MSeries_Timebase3_Select_Bit = 0x40, /* use PLL for timebase 3 */
1156 /* use 10MHz instead of 20MHz for RTSI clock frequency. Appears
1157 to have no effect, at least on pxi-6281, which always uses
1158 20MHz rtsi clock frequency */
1159 MSeries_RTSI_10MHz_Bit = 0x80
1161 static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned
1164 if (RTSI_channel > 7) {
1165 printk("%s: bug, invalid RTSI_channel=%i\n", __func__,
1169 if (RTSI_channel == 7)
1170 return MSeries_PLL_In_Source_Select_RTSI7_Bits;
1172 return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel;
1175 enum MSeries_PLL_Control_Bits {
1176 MSeries_PLL_Enable_Bit = 0x1000,
1177 MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0,
1178 MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000,
1179 MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000,
1180 MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000,
1182 static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor)
1184 static const unsigned max_divisor = 0x10;
1185 if (divisor < 1 || divisor > max_divisor) {
1186 printk("%s: bug, invalid divisor=%i\n", __func__,
1190 return (divisor & 0xf) << 8;
1192 static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier)
1194 static const unsigned max_multiplier = 0x100;
1195 if (multiplier < 1 || multiplier > max_multiplier) {
1196 printk("%s: bug, invalid multiplier=%i\n", __func__,
1200 return multiplier & 0xff;
1203 enum MSeries_PLL_Status {
1204 MSeries_PLL_Locked_Bit = 0x1
1207 enum MSeries_AI_Config_FIFO_Bypass_Bits {
1208 MSeries_AI_Bypass_Channel_Mask = 0x7,
1209 MSeries_AI_Bypass_Bank_Mask = 0x78,
1210 MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380,
1211 MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00,
1212 MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000,
1213 MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000,
1214 MSeries_AI_Bypass_Gain_Mask = 0x1c0000,
1215 MSeries_AI_Bypass_Dither_Bit = 0x200000,
1216 MSeries_AI_Bypass_Polarity_Bit = 0x400000, /* 0 for 2's complement encoding */
1217 MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000
1219 static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int
1222 return (calibration_source << 7) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;
1224 static inline unsigned MSeries_AI_Bypass_Cal_Sel_Neg_Bits(int
1227 return (calibration_source << 10) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;
1229 static inline unsigned MSeries_AI_Bypass_Gain_Bits(int gain)
1231 return (gain << 18) & MSeries_AI_Bypass_Gain_Mask;
1234 enum MSeries_AO_Config_Bank_Bits {
1235 MSeries_AO_DAC_Offset_Select_Mask = 0x7,
1236 MSeries_AO_DAC_Offset_0V_Bits = 0x0,
1237 MSeries_AO_DAC_Offset_5V_Bits = 0x1,
1238 MSeries_AO_DAC_Reference_Mask = 0x38,
1239 MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0,
1240 MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8,
1241 MSeries_AO_Update_Timed_Bit = 0x40,
1242 MSeries_AO_Bipolar_Bit = 0x80 /* turns on 2's complement encoding */
1245 enum MSeries_AO_Reference_Attenuation_Bits {
1246 MSeries_Attenuate_x5_Bit = 0x1
1249 static inline unsigned MSeries_Cal_PWM_High_Time_Bits(unsigned count)
1251 return (count << 16) & 0xffff0000;
1254 static inline unsigned MSeries_Cal_PWM_Low_Time_Bits(unsigned count)
1256 return count & 0xffff;
1259 static inline unsigned MSeries_PFI_Output_Select_Mask(unsigned channel)
1261 return 0x1f << (channel % 3) * 5;
1263 static inline unsigned MSeries_PFI_Output_Select_Bits(unsigned channel,
1266 return (source & 0x1f) << ((channel % 3) * 5);
1269 /* inverse to MSeries_PFI_Output_Select_Bits */
1270 static inline unsigned MSeries_PFI_Output_Select_Source(unsigned channel,
1273 return (bits >> ((channel % 3) * 5)) & 0x1f;
1276 enum MSeries_Gi_DMA_Config_Bits {
1277 Gi_DMA_BankSW_Error_Bit = 0x10,
1278 Gi_DMA_Reset_Bit = 0x8,
1279 Gi_DMA_Int_Enable_Bit = 0x4,
1280 Gi_DMA_Write_Bit = 0x2,
1281 Gi_DMA_Enable_Bit = 0x1,
1284 static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel)
1286 return 0x3 << (channel * 2);
1288 static inline unsigned MSeries_PFI_Filter_Select_Bits(unsigned channel,
1291 return (filter << (channel *
1292 2)) & MSeries_PFI_Filter_Select_Mask(channel);
1295 enum CDIO_DMA_Select_Bits {
1296 CDI_DMA_Select_Shift = 0,
1297 CDI_DMA_Select_Mask = 0xf,
1298 CDO_DMA_Select_Shift = 4,
1299 CDO_DMA_Select_Mask = 0xf << CDO_DMA_Select_Shift
1302 enum CDIO_Status_Bits {
1303 CDO_FIFO_Empty_Bit = 0x1,
1304 CDO_FIFO_Full_Bit = 0x2,
1305 CDO_FIFO_Request_Bit = 0x4,
1306 CDO_Overrun_Bit = 0x8,
1307 CDO_Underflow_Bit = 0x10,
1308 CDI_FIFO_Empty_Bit = 0x10000,
1309 CDI_FIFO_Full_Bit = 0x20000,
1310 CDI_FIFO_Request_Bit = 0x40000,
1311 CDI_Overrun_Bit = 0x80000,
1312 CDI_Overflow_Bit = 0x100000
1315 enum CDIO_Command_Bits {
1316 CDO_Disarm_Bit = 0x1,
1318 CDI_Disarm_Bit = 0x4,
1320 CDO_Reset_Bit = 0x10,
1321 CDI_Reset_Bit = 0x20,
1322 CDO_Error_Interrupt_Enable_Set_Bit = 0x40,
1323 CDO_Error_Interrupt_Enable_Clear_Bit = 0x80,
1324 CDI_Error_Interrupt_Enable_Set_Bit = 0x100,
1325 CDI_Error_Interrupt_Enable_Clear_Bit = 0x200,
1326 CDO_FIFO_Request_Interrupt_Enable_Set_Bit = 0x400,
1327 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x800,
1328 CDI_FIFO_Request_Interrupt_Enable_Set_Bit = 0x1000,
1329 CDI_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x2000,
1330 CDO_Error_Interrupt_Confirm_Bit = 0x4000,
1331 CDI_Error_Interrupt_Confirm_Bit = 0x8000,
1332 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit = 0x10000,
1333 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit = 0x20000,
1334 CDO_SW_Update_Bit = 0x80000,
1335 CDI_SW_Update_Bit = 0x100000
1338 enum CDI_Mode_Bits {
1339 CDI_Sample_Source_Select_Mask = 0x3f,
1340 CDI_Halt_On_Error_Bit = 0x200,
1341 CDI_Polarity_Bit = 0x400, /* sample clock on falling edge */
1342 CDI_FIFO_Mode_Bit = 0x800, /* set for half full mode, clear for not empty mode */
1343 CDI_Data_Lane_Mask = 0x3000, /* data lanes specify which dio channels map to byte or word accesses to the dio fifos */
1344 CDI_Data_Lane_0_15_Bits = 0x0,
1345 CDI_Data_Lane_16_31_Bits = 0x1000,
1346 CDI_Data_Lane_0_7_Bits = 0x0,
1347 CDI_Data_Lane_8_15_Bits = 0x1000,
1348 CDI_Data_Lane_16_23_Bits = 0x2000,
1349 CDI_Data_Lane_24_31_Bits = 0x3000
1352 enum CDO_Mode_Bits {
1353 CDO_Sample_Source_Select_Mask = 0x3f,
1354 CDO_Retransmit_Bit = 0x100,
1355 CDO_Halt_On_Error_Bit = 0x200,
1356 CDO_Polarity_Bit = 0x400, /* sample clock on falling edge */
1357 CDO_FIFO_Mode_Bit = 0x800, /* set for half full mode, clear for not full mode */
1358 CDO_Data_Lane_Mask = 0x3000, /* data lanes specify which dio channels map to byte or word accesses to the dio fifos */
1359 CDO_Data_Lane_0_15_Bits = 0x0,
1360 CDO_Data_Lane_16_31_Bits = 0x1000,
1361 CDO_Data_Lane_0_7_Bits = 0x0,
1362 CDO_Data_Lane_8_15_Bits = 0x1000,
1363 CDO_Data_Lane_16_23_Bits = 0x2000,
1364 CDO_Data_Lane_24_31_Bits = 0x3000
1367 enum Interrupt_C_Enable_Bits {
1368 Interrupt_Group_C_Enable_Bit = 0x1
1371 enum Interrupt_C_Status_Bits {
1372 Interrupt_Group_C_Status_Bit = 0x1
1375 #define M_SERIES_EEPROM_SIZE 1024
1377 struct ni_board_struct {
1386 unsigned int alwaysdither:1;
1393 const struct comedi_lrange *ao_range_table;
1396 unsigned num_p0_dio_channels;
1399 unsigned int ao_unipolar:1;
1400 unsigned int has_8255:1;
1401 unsigned int has_analog_trig:1;
1403 enum caldac_enum caldac[3];
1406 #define n_ni_boards (sizeof(ni_boards)/sizeof(struct ni_board_struct))
1408 #define boardtype (*(struct ni_board_struct *)dev->board_ptr)
1410 #define MAX_N_AO_CHAN 8
1413 #define NI_PRIVATE_COMMON \
1414 uint16_t (*stc_readw)(struct comedi_device *dev, int register); \
1415 uint32_t (*stc_readl)(struct comedi_device *dev, int register); \
1416 void (*stc_writew)(struct comedi_device *dev, uint16_t value, int register); \
1417 void (*stc_writel)(struct comedi_device *dev, uint32_t value, int register); \
1419 unsigned short dio_output; \
1420 unsigned short dio_control; \
1427 int ai_continuous; \
1430 unsigned int ai_calib_source; \
1431 unsigned int ai_calib_source_enabled; \
1432 spinlock_t window_lock; \
1433 spinlock_t soft_reg_copy_lock; \
1434 spinlock_t mite_channel_lock; \
1436 int changain_state; \
1437 unsigned int changain_spec; \
1439 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
1440 unsigned short ao[MAX_N_AO_CHAN]; \
1441 unsigned short caldacs[MAX_N_CALDACS]; \
1443 unsigned short ai_cmd2; \
1445 unsigned short ao_conf[MAX_N_AO_CHAN]; \
1446 unsigned short ao_mode1; \
1447 unsigned short ao_mode2; \
1448 unsigned short ao_mode3; \
1449 unsigned short ao_cmd1; \
1450 unsigned short ao_cmd2; \
1451 unsigned short ao_cmd3; \
1452 unsigned short ao_trigger_select; \
1454 struct ni_gpct_device *counter_dev; \
1455 unsigned short an_trig_etc_reg; \
1457 unsigned ai_offset[512]; \
1459 unsigned long serial_interval_ns; \
1460 unsigned char serial_hw_mode; \
1461 unsigned short clock_and_fout; \
1462 unsigned short clock_and_fout2; \
1464 unsigned short int_a_enable_reg; \
1465 unsigned short int_b_enable_reg; \
1466 unsigned short io_bidirection_pin_reg; \
1467 unsigned short rtsi_trig_direction_reg; \
1468 unsigned short rtsi_trig_a_output_reg; \
1469 unsigned short rtsi_trig_b_output_reg; \
1470 unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; \
1471 unsigned short ai_ao_select_reg; \
1472 unsigned short g0_g1_select_reg; \
1473 unsigned short cdio_dma_select_reg; \
1475 unsigned clock_ns; \
1476 unsigned clock_source; \
1478 unsigned short atrig_mode; \
1479 unsigned short atrig_high; \
1480 unsigned short atrig_low; \
1482 unsigned short pwm_up_count; \
1483 unsigned short pwm_down_count; \
1485 short ai_fifo_buffer[0x2000]; \
1486 uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \
1487 uint32_t serial_number; \
1489 struct mite_struct *mite; \
1490 struct mite_channel *ai_mite_chan; \
1491 struct mite_channel *ao_mite_chan;\
1492 struct mite_channel *cdo_mite_chan;\
1493 struct mite_dma_descriptor_ring *ai_mite_ring; \
1494 struct mite_dma_descriptor_ring *ao_mite_ring; \
1495 struct mite_dma_descriptor_ring *cdo_mite_ring; \
1496 struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT];
1498 #endif /* _COMEDI_NI_STC_H */